1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-3-Clause 4 * 5 * Copyright (c) 2000-2010, LSI Logic Corporation and its contributors. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are 10 * met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon including 16 * a substantially similar Disclaimer requirement for further binary 17 * redistribution. 18 * 3. Neither the name of the LSI Logic Corporation nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 32 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * Name: mpi_cnfg.h 35 * Title: MPI Config message, structures, and Pages 36 * Creation Date: July 27, 2000 37 * 38 * mpi_cnfg.h Version: 01.05.19 39 * 40 * Version History 41 * --------------- 42 * 43 * Date Version Description 44 * -------- -------- ------------------------------------------------------ 45 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 46 * 06-06-00 01.00.01 Update version number for 1.0 release. 47 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 48 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 49 * fields to FC_DEVICE_0 page, updated the page version. 50 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 51 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 52 * and updated the page versions. 53 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 54 * page and updated the page version. 55 * Added Information field and _INFO_PARAMS_NEGOTIATED 56 * definitionto SCSI_DEVICE_0 page. 57 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 58 * page version. 59 * Added BucketsRemaining to LAN_1 page, redefined the 60 * state values, and updated the page version. 61 * Revised bus width definitions in SCSI_PORT_0, 62 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 63 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 64 * version. 65 * Moved FC_DEVICE_0 PageAddress description to spec. 66 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 67 * widths in IOC_0 page and updated the page version. 68 * 11-02-00 01.01.01 Original release for post 1.0 work 69 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 70 * Port Page 2, FC Port Page 4, FC Port Page 5 71 * 11-15-00 01.01.02 Interim changes to match proposals 72 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 73 * 12-05-00 01.01.04 Modified config page actions. 74 * 01-09-01 01.01.05 Added defines for page address formats. 75 * Data size for Manufacturing pages 2 and 3 no longer 76 * defined here. 77 * Io Unit Page 2 size is fixed at 4 adapters and some 78 * flags were changed. 79 * SCSI Port Page 2 Device Settings modified. 80 * New fields added to FC Port Page 0 and some flags 81 * cleaned up. 82 * Removed impedance flash from FC Port Page 1. 83 * Added FC Port pages 6 and 7. 84 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 85 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 86 * Added some LinkType defines for FcPortPage0. 87 * 02-20-01 01.01.08 Started using MPI_POINTER. 88 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 89 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 90 * Added definitions and structures for IOC Page 2 and 91 * RAID Volume Page 2. 92 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 93 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 94 * Added VendorId and ProductRevLevel fields to 95 * RAIDVOL2_IM_PHYS_ID struct. 96 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 97 * defines to make them compatible to MPI version 1.0. 98 * Added structure offset comments. 99 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 100 * removed some obsolete ones. 101 * Added IO Unit Page 3. 102 * Modified defines for Scsi Port Page 2. 103 * Modified RAID Volume Pages. 104 * 08-08-01 01.02.01 Original release for v1.2 work. 105 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 106 * Added defines for the SEP bits in RVP2 VolumeSettings. 107 * Modified the DeviceSettings field in RVP2 to use the 108 * proper structure. 109 * Added defines for SES, SAF-TE, and cross channel for 110 * IOCPage2 CapabilitiesFlags. 111 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 112 * Removed define for 113 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 114 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 115 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 116 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 117 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 118 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 119 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 120 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 121 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 122 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 123 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 124 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 125 * Added rejected bits to SCSI Device Page 0 Information. 126 * Increased size of ALPA array in FC Port Page 2 by one 127 * and removed a one byte reserved field. 128 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 129 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 130 * Added structures for Manufacturing Page 4, IO Unit 131 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 132 * RAID PhysDisk Page 0. 133 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 134 * Modified some of the new defines to make them 32 135 * character unique. 136 * Modified how variable length pages (arrays) are defined. 137 * Added generic defines for hot spare pools and RAID 138 * volume types. 139 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 140 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with 141 * related define, and bumped the page version define. 142 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a 143 * reserved byte and added a define. 144 * Added define for 145 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE. 146 * Added new config page: CONFIG_PAGE_IOC_5. 147 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases 148 * fields to CONFIG_PAGE_FC_PORT_0. 149 * Added AltConnector and NumRequestedAliases fields to 150 * CONFIG_PAGE_FC_PORT_1. 151 * Added new config page: CONFIG_PAGE_FC_PORT_10. 152 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines. 153 * Added additional MPI_SCSIDEVPAGE0_NP_ defines. 154 * Added more MPI_SCSIDEVPAGE1_RP_ defines. 155 * Added define for 156 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE. 157 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3. 158 * Modified MPI_FCPORTPAGE5_FLAGS_ defines. 159 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define. 160 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0. 161 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 162 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0. 163 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for 164 * CONFIG_PAGE_FC_PORT_1. 165 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable 166 * an alias. 167 * Added more device id defines. 168 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define. 169 * Added TargetConfig and IDConfig fields to 170 * CONFIG_PAGE_SCSI_PORT_1. 171 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2 172 * to control DV. 173 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 174 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field 175 * with ADISCHardALPA. 176 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define. 177 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout 178 * fields and related defines to CONFIG_PAGE_FC_PORT_1. 179 * Added define for 180 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK. 181 * Added new fields to the substructures of 182 * CONFIG_PAGE_FC_PORT_10. 183 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0, 184 * CONFIG_PAGE_SCSI_DEVICE_0, and 185 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for 186 * these pages. 187 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0. 188 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config 189 * pages. 190 * Added a new structure for extended config page header. 191 * Added new extended config pages types and structures for 192 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY. 193 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4 194 * to add a Flags field. 195 * Two new Manufacturing config pages (5 and 6). 196 * Two new bits defined for IO Unit Page 1 Flags field. 197 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields 198 * to specify the BIOS boot device. 199 * Four new Flags bits defined for IO Unit Page 2. 200 * Added IO Unit Page 4. 201 * Added EEDP Flags settings to IOC Page 1. 202 * Added new BIOS Page 1 config page. 203 * 10-05-04 01.05.02 Added define for 204 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE. 205 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and 206 * associated defines. 207 * Added more defines for SAS IO Unit Page 0 208 * DiscoveryStatus field. 209 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK 210 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK. 211 * Added defines for Physical Mapping Modes to SAS IO Unit 212 * Page 2. 213 * Added define for 214 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH. 215 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode. 216 * Added defines for MaxTargetSpinUp to BIOS Page 1. 217 * Added 5 new ControlFlags defines for SAS IO Unit 218 * Page 1. 219 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit 220 * Page 2. 221 * Added AccessStatus field to SAS Device Page 0 and added 222 * new Flags bits for supported SATA features. 223 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID 224 * Volume Page 1, and RAID Physical Disk Page 1. 225 * Replaced IO Unit Page 1 BootTargetID,BootBus, and 226 * BootAdapterNum with reserved field. 227 * Added DataScrubRate and ResyncRate to RAID Volume 228 * Page 0. 229 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT 230 * define. 231 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1 232 * Flags field. 233 * Added Auto Port Config flag define for SAS IOUNIT 234 * Page 1 ControlFlags. 235 * Added Disabled bad Phy define to Expander Page 1 236 * Discovery Info field. 237 * Added SAS/SATA device support to SAS IOUnit Page 1 238 * ControlFlags. 239 * Added Unsupported device to SAS Dev Page 0 Flags field 240 * Added disable use SATA Hash Address for SAS IOUNIT 241 * page 1 in ControlFields. 242 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to 243 * Manufacturing Page 4. 244 * Added new defines for BIOS Page 1 IOCSettings field. 245 * Added ExtDiskIdentifier field to RAID Physical Disk 246 * Page 0. 247 * Added new defines for SAS IO Unit Page 1 ControlFlags 248 * and to SAS Device Page 0 Flags to control SATA devices. 249 * Added defines and structures for the new Log Page 0, a 250 * new type of configuration page. 251 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0. 252 * Added WWID field to RAID Volume Page 1. 253 * Added PhysicalPort field to SAS Expander pages 0 and 1. 254 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1. 255 * Added Enclosure/Slot boot device format to BIOS Page 2. 256 * New status value for RAID Volume Page 0 VolumeStatus 257 * (VolumeState subfield). 258 * New value for RAID Physical Page 0 InactiveStatus. 259 * Added Inactive Volume Member flag RAID Physical Disk 260 * Page 0 PhysDiskStatus field. 261 * New physical mapping mode in SAS IO Unit Page 2. 262 * Added CONFIG_PAGE_SAS_ENCLOSURE_0. 263 * Added Slot and Enclosure fields to SAS Device Page 0. 264 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1. 265 * Added more RAID type defines to IOC Page 2. 266 * Added Port Enable Delay settings to BIOS Page 1. 267 * Added Bad Block Table Full define to RAID Volume Page 0. 268 * Added Previous State defines to RAID Physical Disk 269 * Page 0. 270 * Added Max Sata Targets define for DiscoveryStatus field 271 * of SAS IO Unit Page 0. 272 * Added Device Self Test to Control Flags of SAS IO Unit 273 * Page 1. 274 * Added Direct Attach Starting Slot Number define for SAS 275 * IO Unit Page 2. 276 * Added new fields in SAS Device Page 2 for enclosure 277 * mapping. 278 * Added OwnerDevHandle and Flags field to SAS PHY Page 0. 279 * Added IOC GPIO Flags define to SAS Enclosure Page 0. 280 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT. 281 * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from 282 * Manufacturing Page 4. 283 * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit. 284 * Added NumDevsPerEnclosure field to SAS IO Unit page 2. 285 * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP 286 * define. 287 * Added EnclosureHandle field to SAS Expander page 0. 288 * Removed redundant NumTableEntriesProg field from SAS 289 * Expander Page 1. 290 * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for 291 * SAS1078. 292 * Added more defines for Manufacturing Page 4 Flags field. 293 * Added more defines for IOCSettings and added 294 * ExpanderSpinup field to Bios Page 1. 295 * Added postpone SATA Init bit to SAS IO Unit Page 1 296 * ControlFlags. 297 * Changed LogEntry format for Log Page 0. 298 * 03-27-06 01.05.12 Added two new Flags defines for Manufacturing Page 4. 299 * Added Manufacturing Page 7. 300 * Added MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING. 301 * Added IOC Page 6. 302 * Added PrevBootDeviceForm field to CONFIG_PAGE_BIOS_2. 303 * Added MaxLBAHigh field to RAID Volume Page 0. 304 * Added Nvdata version fields to SAS IO Unit Page 0. 305 * Added AdditionalControlFlags, MaxTargetPortConnectTime, 306 * ReportDeviceMissingDelay, and IODeviceMissingDelay 307 * fields to SAS IO Unit Page 1. 308 * 10-11-06 01.05.13 Added NumForceWWID field and ForceWWID array to 309 * Manufacturing Page 5. 310 * Added Manufacturing pages 8 through 10. 311 * Added defines for supported metadata size bits in 312 * CapabilitiesFlags field of IOC Page 6. 313 * Added defines for metadata size bits in VolumeSettings 314 * field of RAID Volume Page 0. 315 * Added SATA Link Reset settings, Enable SATA Asynchronous 316 * Notification bit, and HideNonZeroAttachedPhyIdentifiers 317 * bit to AdditionalControlFlags field of SAS IO Unit 318 * Page 1. 319 * Added defines for Enclosure Devices Unmapped and 320 * Device Limit Exceeded bits in Status field of SAS IO 321 * Unit Page 2. 322 * Added more AccessStatus values for SAS Device Page 0. 323 * Added bit for SATA Asynchronous Notification Support in 324 * Flags field of SAS Device Page 0. 325 * 02-28-07 01.05.14 Added ExtFlags field to Manufacturing Page 4. 326 * Added Disable SMART Polling for CapabilitiesFlags of 327 * IOC Page 6. 328 * Added Disable SMART Polling to DeviceSettings of BIOS 329 * Page 1. 330 * Added Multi-Port Domain bit for DiscoveryStatus field 331 * of SAS IO Unit Page. 332 * Added Multi-Port Domain Illegal flag for SAS IO Unit 333 * Page 1 AdditionalControlFlags field. 334 * 05-24-07 01.05.15 Added Hide Physical Disks with Non-Integrated RAID 335 * Metadata bit to Manufacturing Page 4 ExtFlags field. 336 * Added Internal Connector to End Device Present bit to 337 * Expander Page 0 Flags field. 338 * Fixed define for 339 * MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED. 340 * 08-07-07 01.05.16 Added MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT 341 * define. 342 * Added BIOS Page 4 structure. 343 * Added MPI_RAID_PHYS_DISK1_PATH_MAX define for RAID 344 * Physical Disk Page 1. 345 * 01-15-07 01.05.17 Added additional bit defines for ExtFlags field of 346 * Manufacturing Page 4. 347 * Added Solid State Drives Supported bit to IOC Page 6 348 * Capabilities Flags. 349 * Added new value for AccessStatus field of SAS Device 350 * Page 0 (_SATA_NEEDS_INITIALIZATION). 351 * 03-28-08 01.05.18 Defined new bits in Manufacturing Page 4 ExtFlags field 352 * to control coercion size and the mixing of SAS and SATA 353 * SSD drives. 354 * 07-11-08 01.05.19 Added defines MPI_MANPAGE4_EXTFLAGS_RAID0_SINGLE_DRIVE 355 * and MPI_MANPAGE4_EXTFLAGS_SSD_SCRUB_DISABLE for ExtFlags 356 * field of Manufacturing Page 4. 357 * Added defines for a new bit in BIOS Page 1 BiosOptions 358 * field to control adapter scan order. 359 * Added BootDeviceWaitTime field to SAS IO Unit Page 2. 360 * Added MPI_SAS_PHY0_PHYINFO_PHY_VACANT for use in PhyInfo 361 * field of SAS Expander Page 1. 362 * -------------------------------------------------------------------------- 363 */ 364 365 #ifndef MPI_CNFG_H 366 #define MPI_CNFG_H 367 368 /***************************************************************************** 369 * 370 * C o n f i g M e s s a g e a n d S t r u c t u r e s 371 * 372 *****************************************************************************/ 373 374 typedef struct _CONFIG_PAGE_HEADER 375 { 376 U8 PageVersion; /* 00h */ 377 U8 PageLength; /* 01h */ 378 U8 PageNumber; /* 02h */ 379 U8 PageType; /* 03h */ 380 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 381 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 382 383 typedef union _CONFIG_PAGE_HEADER_UNION 384 { 385 ConfigPageHeader_t Struct; 386 U8 Bytes[4]; 387 U16 Word16[2]; 388 U32 Word32; 389 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 390 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 391 392 typedef struct _CONFIG_EXTENDED_PAGE_HEADER 393 { 394 U8 PageVersion; /* 00h */ 395 U8 Reserved1; /* 01h */ 396 U8 PageNumber; /* 02h */ 397 U8 PageType; /* 03h */ 398 U16 ExtPageLength; /* 04h */ 399 U8 ExtPageType; /* 06h */ 400 U8 Reserved2; /* 07h */ 401 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER, 402 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t; 403 404 /**************************************************************************** 405 * PageType field values 406 ****************************************************************************/ 407 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 408 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 409 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 410 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 411 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 412 413 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 414 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 415 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 416 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 417 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 418 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 419 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 420 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 421 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 422 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 423 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 424 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B) 425 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F) 426 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 427 428 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 429 430 /**************************************************************************** 431 * ExtPageType field values 432 ****************************************************************************/ 433 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 434 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 435 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 436 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 437 #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14) 438 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 439 440 /**************************************************************************** 441 * PageAddress field values 442 ****************************************************************************/ 443 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 444 445 #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000) 446 #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000) 447 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 448 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 449 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 450 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 451 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000) 452 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF) 453 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0) 454 #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00) 455 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8) 456 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000) 457 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16) 458 459 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 460 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 461 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 462 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 463 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 464 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 465 466 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 467 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 468 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 469 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 470 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 471 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 472 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 473 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 474 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 475 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 476 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 477 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 478 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 479 480 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 481 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 482 483 #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 484 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28) 485 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 486 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001) 487 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002) 488 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF) 489 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0) 490 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000) 491 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16) 492 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF) 493 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0) 494 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF) 495 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0) 496 497 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 498 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28) 499 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 500 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001) 501 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002) 502 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 503 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0) 504 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 505 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8) 506 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 507 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0) 508 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF) 509 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0) 510 511 #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 512 #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28) 513 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0) 514 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1) 515 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 516 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0) 517 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 518 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0) 519 520 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 521 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28) 522 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 523 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001) 524 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 525 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0) 526 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF) 527 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0) 528 529 /**************************************************************************** 530 * Config Request Message 531 ****************************************************************************/ 532 typedef struct _MSG_CONFIG 533 { 534 U8 Action; /* 00h */ 535 U8 Reserved; /* 01h */ 536 U8 ChainOffset; /* 02h */ 537 U8 Function; /* 03h */ 538 U16 ExtPageLength; /* 04h */ 539 U8 ExtPageType; /* 06h */ 540 U8 MsgFlags; /* 07h */ 541 U32 MsgContext; /* 08h */ 542 U8 Reserved2[8]; /* 0Ch */ 543 CONFIG_PAGE_HEADER Header; /* 14h */ 544 U32 PageAddress; /* 18h */ 545 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 546 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 547 Config_t, MPI_POINTER pConfig_t; 548 549 /**************************************************************************** 550 * Action field values 551 ****************************************************************************/ 552 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 553 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 554 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 555 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 556 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 557 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 558 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 559 560 /* Config Reply Message */ 561 typedef struct _MSG_CONFIG_REPLY 562 { 563 U8 Action; /* 00h */ 564 U8 Reserved; /* 01h */ 565 U8 MsgLength; /* 02h */ 566 U8 Function; /* 03h */ 567 U16 ExtPageLength; /* 04h */ 568 U8 ExtPageType; /* 06h */ 569 U8 MsgFlags; /* 07h */ 570 U32 MsgContext; /* 08h */ 571 U8 Reserved2[2]; /* 0Ch */ 572 U16 IOCStatus; /* 0Eh */ 573 U32 IOCLogInfo; /* 10h */ 574 CONFIG_PAGE_HEADER Header; /* 14h */ 575 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 576 ConfigReply_t, MPI_POINTER pConfigReply_t; 577 578 /***************************************************************************** 579 * 580 * C o n f i g u r a t i o n P a g e s 581 * 582 *****************************************************************************/ 583 584 /**************************************************************************** 585 * Manufacturing Config pages 586 ****************************************************************************/ 587 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000) 588 /* Fibre Channel */ 589 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 590 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 591 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 592 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 593 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 594 #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642) 595 #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640) 596 #define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646) 597 /* SCSI */ 598 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 599 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 600 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 601 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 602 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 603 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 604 /* SAS */ 605 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050) 606 #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C) 607 #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056) 608 #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E) 609 #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A) 610 #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054) 611 #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058) 612 #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062) 613 614 typedef struct _CONFIG_PAGE_MANUFACTURING_0 615 { 616 CONFIG_PAGE_HEADER Header; /* 00h */ 617 U8 ChipName[16]; /* 04h */ 618 U8 ChipRevision[8]; /* 14h */ 619 U8 BoardName[16]; /* 1Ch */ 620 U8 BoardAssembly[16]; /* 2Ch */ 621 U8 BoardTracerNumber[16]; /* 3Ch */ 622 623 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 624 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 625 626 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 627 628 typedef struct _CONFIG_PAGE_MANUFACTURING_1 629 { 630 CONFIG_PAGE_HEADER Header; /* 00h */ 631 U8 VPD[256]; /* 04h */ 632 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 633 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 634 635 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 636 637 typedef struct _MPI_CHIP_REVISION_ID 638 { 639 U16 DeviceID; /* 00h */ 640 U8 PCIRevisionID; /* 02h */ 641 U8 Reserved; /* 03h */ 642 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 643 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 644 645 /* 646 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 647 * one and check Header.PageLength at runtime. 648 */ 649 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 650 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 651 #endif 652 653 typedef struct _CONFIG_PAGE_MANUFACTURING_2 654 { 655 CONFIG_PAGE_HEADER Header; /* 00h */ 656 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 657 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 658 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 659 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 660 661 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 662 663 /* 664 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 665 * one and check Header.PageLength at runtime. 666 */ 667 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 668 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 669 #endif 670 671 typedef struct _CONFIG_PAGE_MANUFACTURING_3 672 { 673 CONFIG_PAGE_HEADER Header; /* 00h */ 674 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 675 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 676 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 677 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 678 679 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 680 681 typedef struct _CONFIG_PAGE_MANUFACTURING_4 682 { 683 CONFIG_PAGE_HEADER Header; /* 00h */ 684 U32 Reserved1; /* 04h */ 685 U8 InfoOffset0; /* 08h */ 686 U8 InfoSize0; /* 09h */ 687 U8 InfoOffset1; /* 0Ah */ 688 U8 InfoSize1; /* 0Bh */ 689 U8 InquirySize; /* 0Ch */ 690 U8 Flags; /* 0Dh */ 691 U16 ExtFlags; /* 0Eh */ 692 U8 InquiryData[56]; /* 10h */ 693 U32 ISVolumeSettings; /* 48h */ 694 U32 IMEVolumeSettings; /* 4Ch */ 695 U32 IMVolumeSettings; /* 50h */ 696 U32 Reserved3; /* 54h */ 697 U32 Reserved4; /* 58h */ 698 U32 Reserved5; /* 5Ch */ 699 U8 IMEDataScrubRate; /* 60h */ 700 U8 IMEResyncRate; /* 61h */ 701 U16 Reserved6; /* 62h */ 702 U8 IMDataScrubRate; /* 64h */ 703 U8 IMResyncRate; /* 65h */ 704 U16 Reserved7; /* 66h */ 705 U32 Reserved8; /* 68h */ 706 U32 Reserved9; /* 6Ch */ 707 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 708 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 709 710 #define MPI_MANUFACTURING4_PAGEVERSION (0x05) 711 712 /* defines for the Flags field */ 713 #define MPI_MANPAGE4_FORCE_BAD_BLOCK_TABLE (0x80) 714 #define MPI_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x40) 715 #define MPI_MANPAGE4_IME_DISABLE (0x20) 716 #define MPI_MANPAGE4_IM_DISABLE (0x10) 717 #define MPI_MANPAGE4_IS_DISABLE (0x08) 718 #define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04) 719 #define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02) 720 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01) 721 722 /* defines for the ExtFlags field */ 723 #define MPI_MANPAGE4_EXTFLAGS_RAID0_SINGLE_DRIVE (0x0400) 724 #define MPI_MANPAGE4_EXTFLAGS_SSD_SCRUB_DISABLE (0x0200) 725 #define MPI_MANPAGE4_EXTFLAGS_MASK_COERCION_SIZE (0x0180) 726 #define MPI_MANPAGE4_EXTFLAGS_SHIFT_COERCION_SIZE (7) 727 #define MPI_MANPAGE4_EXTFLAGS_1GB_COERCION_SIZE (0) 728 #define MPI_MANPAGE4_EXTFLAGS_128MB_COERCION_SIZE (1) 729 730 #define MPI_MANPAGE4_EXTFLAGS_NO_MIX_SSD_SAS_SATA (0x0040) 731 #define MPI_MANPAGE4_EXTFLAGS_MIX_SSD_AND_NON_SSD (0x0020) 732 #define MPI_MANPAGE4_EXTFLAGS_DUAL_PORT_SUPPORT (0x0010) 733 #define MPI_MANPAGE4_EXTFLAGS_HIDE_NON_IR_METADATA (0x0008) 734 #define MPI_MANPAGE4_EXTFLAGS_SAS_CACHE_DISABLE (0x0004) 735 #define MPI_MANPAGE4_EXTFLAGS_SATA_CACHE_DISABLE (0x0002) 736 #define MPI_MANPAGE4_EXTFLAGS_LEGACY_MODE (0x0001) 737 738 #ifndef MPI_MANPAGE5_NUM_FORCEWWID 739 #define MPI_MANPAGE5_NUM_FORCEWWID (1) 740 #endif 741 742 typedef struct _CONFIG_PAGE_MANUFACTURING_5 743 { 744 CONFIG_PAGE_HEADER Header; /* 00h */ 745 U64 BaseWWID; /* 04h */ 746 U8 Flags; /* 0Ch */ 747 U8 NumForceWWID; /* 0Dh */ 748 U16 Reserved2; /* 0Eh */ 749 U32 Reserved3; /* 10h */ 750 U32 Reserved4; /* 14h */ 751 U64 ForceWWID[MPI_MANPAGE5_NUM_FORCEWWID]; /* 18h */ 752 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5, 753 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t; 754 755 #define MPI_MANUFACTURING5_PAGEVERSION (0x02) 756 757 /* defines for the Flags field */ 758 #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01) 759 760 typedef struct _CONFIG_PAGE_MANUFACTURING_6 761 { 762 CONFIG_PAGE_HEADER Header; /* 00h */ 763 U32 ProductSpecificInfo;/* 04h */ 764 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6, 765 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t; 766 767 #define MPI_MANUFACTURING6_PAGEVERSION (0x00) 768 769 typedef struct _MPI_MANPAGE7_CONNECTOR_INFO 770 { 771 U32 Pinout; /* 00h */ 772 U8 Connector[16]; /* 04h */ 773 U8 Location; /* 14h */ 774 U8 Reserved1; /* 15h */ 775 U16 Slot; /* 16h */ 776 U32 Reserved2; /* 18h */ 777 } MPI_MANPAGE7_CONNECTOR_INFO, MPI_POINTER PTR_MPI_MANPAGE7_CONNECTOR_INFO, 778 MpiManPage7ConnectorInfo_t, MPI_POINTER pMpiManPage7ConnectorInfo_t; 779 780 /* defines for the Pinout field */ 781 #define MPI_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000) 782 #define MPI_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000) 783 #define MPI_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000) 784 #define MPI_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000) 785 #define MPI_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800) 786 #define MPI_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400) 787 #define MPI_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200) 788 #define MPI_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100) 789 #define MPI_MANPAGE7_PINOUT_SFF_8482 (0x00000002) 790 #define MPI_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001) 791 792 /* defines for the Location field */ 793 #define MPI_MANPAGE7_LOCATION_UNKNOWN (0x01) 794 #define MPI_MANPAGE7_LOCATION_INTERNAL (0x02) 795 #define MPI_MANPAGE7_LOCATION_EXTERNAL (0x04) 796 #define MPI_MANPAGE7_LOCATION_SWITCHABLE (0x08) 797 #define MPI_MANPAGE7_LOCATION_AUTO (0x10) 798 #define MPI_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 799 #define MPI_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 800 801 /* 802 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 803 * one and check NumPhys at runtime. 804 */ 805 #ifndef MPI_MANPAGE7_CONNECTOR_INFO_MAX 806 #define MPI_MANPAGE7_CONNECTOR_INFO_MAX (1) 807 #endif 808 809 typedef struct _CONFIG_PAGE_MANUFACTURING_7 810 { 811 CONFIG_PAGE_HEADER Header; /* 00h */ 812 U32 Reserved1; /* 04h */ 813 U32 Reserved2; /* 08h */ 814 U32 Flags; /* 0Ch */ 815 U8 EnclosureName[16]; /* 10h */ 816 U8 NumPhys; /* 20h */ 817 U8 Reserved3; /* 21h */ 818 U16 Reserved4; /* 22h */ 819 MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */ 820 } CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7, 821 ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t; 822 823 #define MPI_MANUFACTURING7_PAGEVERSION (0x00) 824 825 /* defines for the Flags field */ 826 #define MPI_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 827 828 typedef struct _CONFIG_PAGE_MANUFACTURING_8 829 { 830 CONFIG_PAGE_HEADER Header; /* 00h */ 831 U32 ProductSpecificInfo;/* 04h */ 832 } CONFIG_PAGE_MANUFACTURING_8, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_8, 833 ManufacturingPage8_t, MPI_POINTER pManufacturingPage8_t; 834 835 #define MPI_MANUFACTURING8_PAGEVERSION (0x00) 836 837 typedef struct _CONFIG_PAGE_MANUFACTURING_9 838 { 839 CONFIG_PAGE_HEADER Header; /* 00h */ 840 U32 ProductSpecificInfo;/* 04h */ 841 } CONFIG_PAGE_MANUFACTURING_9, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_9, 842 ManufacturingPage9_t, MPI_POINTER pManufacturingPage9_t; 843 844 #define MPI_MANUFACTURING9_PAGEVERSION (0x00) 845 846 typedef struct _CONFIG_PAGE_MANUFACTURING_10 847 { 848 CONFIG_PAGE_HEADER Header; /* 00h */ 849 U32 ProductSpecificInfo;/* 04h */ 850 } CONFIG_PAGE_MANUFACTURING_10, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_10, 851 ManufacturingPage10_t, MPI_POINTER pManufacturingPage10_t; 852 853 #define MPI_MANUFACTURING10_PAGEVERSION (0x00) 854 855 /**************************************************************************** 856 * IO Unit Config Pages 857 ****************************************************************************/ 858 859 typedef struct _CONFIG_PAGE_IO_UNIT_0 860 { 861 CONFIG_PAGE_HEADER Header; /* 00h */ 862 U64 UniqueValue; /* 04h */ 863 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 864 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 865 866 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 867 868 typedef struct _CONFIG_PAGE_IO_UNIT_1 869 { 870 CONFIG_PAGE_HEADER Header; /* 00h */ 871 U32 Flags; /* 04h */ 872 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 873 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 874 875 #define MPI_IOUNITPAGE1_PAGEVERSION (0x02) 876 877 /* IO Unit Page 1 Flags defines */ 878 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 879 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 880 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 881 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 882 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 883 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020) 884 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 885 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 886 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 887 #define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200) 888 889 typedef struct _MPI_ADAPTER_INFO 890 { 891 U8 PciBusNumber; /* 00h */ 892 U8 PciDeviceAndFunctionNumber; /* 01h */ 893 U16 AdapterFlags; /* 02h */ 894 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 895 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 896 897 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 898 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 899 900 typedef struct _CONFIG_PAGE_IO_UNIT_2 901 { 902 CONFIG_PAGE_HEADER Header; /* 00h */ 903 U32 Flags; /* 04h */ 904 U32 BiosVersion; /* 08h */ 905 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 906 U32 Reserved1; /* 1Ch */ 907 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 908 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 909 910 #define MPI_IOUNITPAGE2_PAGEVERSION (0x02) 911 912 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 913 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 914 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 915 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 916 917 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 918 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 919 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020) 920 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 921 922 /* 923 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 924 * one and check Header.PageLength at runtime. 925 */ 926 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 927 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 928 #endif 929 930 typedef struct _CONFIG_PAGE_IO_UNIT_3 931 { 932 CONFIG_PAGE_HEADER Header; /* 00h */ 933 U8 GPIOCount; /* 04h */ 934 U8 Reserved1; /* 05h */ 935 U16 Reserved2; /* 06h */ 936 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 937 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 938 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 939 940 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 941 942 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 943 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 944 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 945 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 946 947 typedef struct _CONFIG_PAGE_IO_UNIT_4 948 { 949 CONFIG_PAGE_HEADER Header; /* 00h */ 950 U32 Reserved1; /* 04h */ 951 SGE_SIMPLE_UNION FWImageSGE; /* 08h */ 952 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4, 953 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t; 954 955 #define MPI_IOUNITPAGE4_PAGEVERSION (0x00) 956 957 /**************************************************************************** 958 * IOC Config Pages 959 ****************************************************************************/ 960 961 typedef struct _CONFIG_PAGE_IOC_0 962 { 963 CONFIG_PAGE_HEADER Header; /* 00h */ 964 U32 TotalNVStore; /* 04h */ 965 U32 FreeNVStore; /* 08h */ 966 U16 VendorID; /* 0Ch */ 967 U16 DeviceID; /* 0Eh */ 968 U8 RevisionID; /* 10h */ 969 U8 Reserved[3]; /* 11h */ 970 U32 ClassCode; /* 14h */ 971 U16 SubsystemVendorID; /* 18h */ 972 U16 SubsystemID; /* 1Ah */ 973 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 974 IOCPage0_t, MPI_POINTER pIOCPage0_t; 975 976 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 977 978 typedef struct _CONFIG_PAGE_IOC_1 979 { 980 CONFIG_PAGE_HEADER Header; /* 00h */ 981 U32 Flags; /* 04h */ 982 U32 CoalescingTimeout; /* 08h */ 983 U8 CoalescingDepth; /* 0Ch */ 984 U8 PCISlotNum; /* 0Dh */ 985 U8 Reserved[2]; /* 0Eh */ 986 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 987 IOCPage1_t, MPI_POINTER pIOCPage1_t; 988 989 #define MPI_IOCPAGE1_PAGEVERSION (0x03) 990 991 /* defines for the Flags field */ 992 #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000) 993 #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000) 994 #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000) 995 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000) 996 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010) 997 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 998 999 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1000 1001 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 1002 { 1003 U8 VolumeID; /* 00h */ 1004 U8 VolumeBus; /* 01h */ 1005 U8 VolumeIOC; /* 02h */ 1006 U8 VolumePageNumber; /* 03h */ 1007 U8 VolumeType; /* 04h */ 1008 U8 Flags; /* 05h */ 1009 U16 Reserved3; /* 06h */ 1010 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 1011 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 1012 1013 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 1014 1015 #define MPI_RAID_VOL_TYPE_IS (0x00) 1016 #define MPI_RAID_VOL_TYPE_IME (0x01) 1017 #define MPI_RAID_VOL_TYPE_IM (0x02) 1018 #define MPI_RAID_VOL_TYPE_RAID_5 (0x03) 1019 #define MPI_RAID_VOL_TYPE_RAID_6 (0x04) 1020 #define MPI_RAID_VOL_TYPE_RAID_10 (0x05) 1021 #define MPI_RAID_VOL_TYPE_RAID_50 (0x06) 1022 #define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF) 1023 1024 /* IOC Page 2 Volume Flags values */ 1025 1026 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08) 1027 1028 /* 1029 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1030 * one and check Header.PageLength at runtime. 1031 */ 1032 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 1033 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 1034 #endif 1035 1036 typedef struct _CONFIG_PAGE_IOC_2 1037 { 1038 CONFIG_PAGE_HEADER Header; /* 00h */ 1039 U32 CapabilitiesFlags; /* 04h */ 1040 U8 NumActiveVolumes; /* 08h */ 1041 U8 MaxVolumes; /* 09h */ 1042 U8 NumActivePhysDisks; /* 0Ah */ 1043 U8 MaxPhysDisks; /* 0Bh */ 1044 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 1045 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 1046 IOCPage2_t, MPI_POINTER pIOCPage2_t; 1047 1048 #define MPI_IOCPAGE2_PAGEVERSION (0x04) 1049 1050 /* IOC Page 2 Capabilities flags */ 1051 1052 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 1053 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 1054 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 1055 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008) 1056 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010) 1057 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020) 1058 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040) 1059 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING (0x10000000) 1060 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 1061 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 1062 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 1063 1064 typedef struct _IOC_3_PHYS_DISK 1065 { 1066 U8 PhysDiskID; /* 00h */ 1067 U8 PhysDiskBus; /* 01h */ 1068 U8 PhysDiskIOC; /* 02h */ 1069 U8 PhysDiskNum; /* 03h */ 1070 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 1071 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 1072 1073 /* 1074 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1075 * one and check Header.PageLength at runtime. 1076 */ 1077 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 1078 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 1079 #endif 1080 1081 typedef struct _CONFIG_PAGE_IOC_3 1082 { 1083 CONFIG_PAGE_HEADER Header; /* 00h */ 1084 U8 NumPhysDisks; /* 04h */ 1085 U8 Reserved1; /* 05h */ 1086 U16 Reserved2; /* 06h */ 1087 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 1088 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 1089 IOCPage3_t, MPI_POINTER pIOCPage3_t; 1090 1091 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 1092 1093 typedef struct _IOC_4_SEP 1094 { 1095 U8 SEPTargetID; /* 00h */ 1096 U8 SEPBus; /* 01h */ 1097 U16 Reserved; /* 02h */ 1098 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 1099 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 1100 1101 /* 1102 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1103 * one and check Header.PageLength at runtime. 1104 */ 1105 #ifndef MPI_IOC_PAGE_4_SEP_MAX 1106 #define MPI_IOC_PAGE_4_SEP_MAX (1) 1107 #endif 1108 1109 typedef struct _CONFIG_PAGE_IOC_4 1110 { 1111 CONFIG_PAGE_HEADER Header; /* 00h */ 1112 U8 ActiveSEP; /* 04h */ 1113 U8 MaxSEP; /* 05h */ 1114 U16 Reserved1; /* 06h */ 1115 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 1116 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 1117 IOCPage4_t, MPI_POINTER pIOCPage4_t; 1118 1119 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 1120 1121 typedef struct _IOC_5_HOT_SPARE 1122 { 1123 U8 PhysDiskNum; /* 00h */ 1124 U8 Reserved; /* 01h */ 1125 U8 HotSparePool; /* 02h */ 1126 U8 Flags; /* 03h */ 1127 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE, 1128 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t; 1129 1130 /* IOC Page 5 HotSpare Flags */ 1131 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01) 1132 1133 /* 1134 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1135 * one and check Header.PageLength at runtime. 1136 */ 1137 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX 1138 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1) 1139 #endif 1140 1141 typedef struct _CONFIG_PAGE_IOC_5 1142 { 1143 CONFIG_PAGE_HEADER Header; /* 00h */ 1144 U32 Reserved1; /* 04h */ 1145 U8 NumHotSpares; /* 08h */ 1146 U8 Reserved2; /* 09h */ 1147 U16 Reserved3; /* 0Ah */ 1148 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */ 1149 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5, 1150 IOCPage5_t, MPI_POINTER pIOCPage5_t; 1151 1152 #define MPI_IOCPAGE5_PAGEVERSION (0x00) 1153 1154 typedef struct _CONFIG_PAGE_IOC_6 1155 { 1156 CONFIG_PAGE_HEADER Header; /* 00h */ 1157 U32 CapabilitiesFlags; /* 04h */ 1158 U8 MaxDrivesIS; /* 08h */ 1159 U8 MaxDrivesIM; /* 09h */ 1160 U8 MaxDrivesIME; /* 0Ah */ 1161 U8 Reserved1; /* 0Bh */ 1162 U8 MinDrivesIS; /* 0Ch */ 1163 U8 MinDrivesIM; /* 0Dh */ 1164 U8 MinDrivesIME; /* 0Eh */ 1165 U8 Reserved2; /* 0Fh */ 1166 U8 MaxGlobalHotSpares; /* 10h */ 1167 U8 Reserved3; /* 11h */ 1168 U16 Reserved4; /* 12h */ 1169 U32 Reserved5; /* 14h */ 1170 U32 SupportedStripeSizeMapIS; /* 18h */ 1171 U32 SupportedStripeSizeMapIME; /* 1Ch */ 1172 U32 Reserved6; /* 20h */ 1173 U8 MetadataSize; /* 24h */ 1174 U8 Reserved7; /* 25h */ 1175 U16 Reserved8; /* 26h */ 1176 U16 MaxBadBlockTableEntries; /* 28h */ 1177 U16 Reserved9; /* 2Ah */ 1178 U16 IRNvsramUsage; /* 2Ch */ 1179 U16 Reserved10; /* 2Eh */ 1180 U32 IRNvsramVersion; /* 30h */ 1181 U32 Reserved11; /* 34h */ 1182 U32 Reserved12; /* 38h */ 1183 } CONFIG_PAGE_IOC_6, MPI_POINTER PTR_CONFIG_PAGE_IOC_6, 1184 IOCPage6_t, MPI_POINTER pIOCPage6_t; 1185 1186 #define MPI_IOCPAGE6_PAGEVERSION (0x01) 1187 1188 /* IOC Page 6 Capabilities Flags */ 1189 1190 #define MPI_IOCPAGE6_CAP_FLAGS_SSD_SUPPORT (0x00000020) 1191 #define MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT (0x00000010) 1192 #define MPI_IOCPAGE6_CAP_FLAGS_DISABLE_SMART_POLLING (0x00000008) 1193 1194 #define MPI_IOCPAGE6_CAP_FLAGS_MASK_METADATA_SIZE (0x00000006) 1195 #define MPI_IOCPAGE6_CAP_FLAGS_64MB_METADATA_SIZE (0x00000000) 1196 #define MPI_IOCPAGE6_CAP_FLAGS_512MB_METADATA_SIZE (0x00000002) 1197 1198 #define MPI_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1199 1200 /**************************************************************************** 1201 * BIOS Config Pages 1202 ****************************************************************************/ 1203 1204 typedef struct _CONFIG_PAGE_BIOS_1 1205 { 1206 CONFIG_PAGE_HEADER Header; /* 00h */ 1207 U32 BiosOptions; /* 04h */ 1208 U32 IOCSettings; /* 08h */ 1209 U32 Reserved1; /* 0Ch */ 1210 U32 DeviceSettings; /* 10h */ 1211 U16 NumberOfDevices; /* 14h */ 1212 U8 ExpanderSpinup; /* 16h */ 1213 U8 Reserved2; /* 17h */ 1214 U16 IOTimeoutBlockDevicesNonRM; /* 18h */ 1215 U16 IOTimeoutSequential; /* 1Ah */ 1216 U16 IOTimeoutOther; /* 1Ch */ 1217 U16 IOTimeoutBlockDevicesRM; /* 1Eh */ 1218 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1, 1219 BIOSPage1_t, MPI_POINTER pBIOSPage1_t; 1220 1221 #define MPI_BIOSPAGE1_PAGEVERSION (0x03) 1222 1223 /* values for the BiosOptions field */ 1224 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400) 1225 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200) 1226 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100) 1227 1228 #define MPI_BIOSPAGE1_OPTIONS_SCAN_HIGH_TO_LOW (0x00000002) 1229 #define MPI_BIOSPAGE1_OPTIONS_SCAN_LOW_TO_HIGH (0x00000000) 1230 1231 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1232 1233 /* values for the IOCSettings field */ 1234 #define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000) 1235 #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24) 1236 1237 #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000) 1238 #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20) 1239 1240 #define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000) 1241 #define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000) 1242 1243 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1244 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1245 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1246 1247 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000) 1248 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12) 1249 1250 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00) 1251 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8) 1252 1253 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1254 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1255 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1256 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1257 1258 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1259 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1260 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1261 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1262 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1263 1264 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1265 1266 /* values for the DeviceSettings field */ 1267 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1268 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1269 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1270 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1271 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1272 1273 /* defines for the ExpanderSpinup field */ 1274 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0) 1275 #define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4) 1276 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F) 1277 1278 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER 1279 { 1280 U32 Reserved1; /* 00h */ 1281 U32 Reserved2; /* 04h */ 1282 U32 Reserved3; /* 08h */ 1283 U32 Reserved4; /* 0Ch */ 1284 U32 Reserved5; /* 10h */ 1285 U32 Reserved6; /* 14h */ 1286 U32 Reserved7; /* 18h */ 1287 U32 Reserved8; /* 1Ch */ 1288 U32 Reserved9; /* 20h */ 1289 U32 Reserved10; /* 24h */ 1290 U32 Reserved11; /* 28h */ 1291 U32 Reserved12; /* 2Ch */ 1292 U32 Reserved13; /* 30h */ 1293 U32 Reserved14; /* 34h */ 1294 U32 Reserved15; /* 38h */ 1295 U32 Reserved16; /* 3Ch */ 1296 U32 Reserved17; /* 40h */ 1297 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER; 1298 1299 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER 1300 { 1301 U8 TargetID; /* 00h */ 1302 U8 Bus; /* 01h */ 1303 U8 AdapterNumber; /* 02h */ 1304 U8 Reserved1; /* 03h */ 1305 U32 Reserved2; /* 04h */ 1306 U32 Reserved3; /* 08h */ 1307 U32 Reserved4; /* 0Ch */ 1308 U8 LUN[8]; /* 10h */ 1309 U32 Reserved5; /* 18h */ 1310 U32 Reserved6; /* 1Ch */ 1311 U32 Reserved7; /* 20h */ 1312 U32 Reserved8; /* 24h */ 1313 U32 Reserved9; /* 28h */ 1314 U32 Reserved10; /* 2Ch */ 1315 U32 Reserved11; /* 30h */ 1316 U32 Reserved12; /* 34h */ 1317 U32 Reserved13; /* 38h */ 1318 U32 Reserved14; /* 3Ch */ 1319 U32 Reserved15; /* 40h */ 1320 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER; 1321 1322 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS 1323 { 1324 U8 TargetID; /* 00h */ 1325 U8 Bus; /* 01h */ 1326 U16 PCIAddress; /* 02h */ 1327 U32 Reserved1; /* 04h */ 1328 U32 Reserved2; /* 08h */ 1329 U32 Reserved3; /* 0Ch */ 1330 U8 LUN[8]; /* 10h */ 1331 U32 Reserved4; /* 18h */ 1332 U32 Reserved5; /* 1Ch */ 1333 U32 Reserved6; /* 20h */ 1334 U32 Reserved7; /* 24h */ 1335 U32 Reserved8; /* 28h */ 1336 U32 Reserved9; /* 2Ch */ 1337 U32 Reserved10; /* 30h */ 1338 U32 Reserved11; /* 34h */ 1339 U32 Reserved12; /* 38h */ 1340 U32 Reserved13; /* 3Ch */ 1341 U32 Reserved14; /* 40h */ 1342 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS; 1343 1344 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER 1345 { 1346 U8 TargetID; /* 00h */ 1347 U8 Bus; /* 01h */ 1348 U8 PCISlotNumber; /* 02h */ 1349 U8 Reserved1; /* 03h */ 1350 U32 Reserved2; /* 04h */ 1351 U32 Reserved3; /* 08h */ 1352 U32 Reserved4; /* 0Ch */ 1353 U8 LUN[8]; /* 10h */ 1354 U32 Reserved5; /* 18h */ 1355 U32 Reserved6; /* 1Ch */ 1356 U32 Reserved7; /* 20h */ 1357 U32 Reserved8; /* 24h */ 1358 U32 Reserved9; /* 28h */ 1359 U32 Reserved10; /* 2Ch */ 1360 U32 Reserved11; /* 30h */ 1361 U32 Reserved12; /* 34h */ 1362 U32 Reserved13; /* 38h */ 1363 U32 Reserved14; /* 3Ch */ 1364 U32 Reserved15; /* 40h */ 1365 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER; 1366 1367 typedef struct _MPI_BOOT_DEVICE_FC_WWN 1368 { 1369 U64 WWPN; /* 00h */ 1370 U32 Reserved1; /* 08h */ 1371 U32 Reserved2; /* 0Ch */ 1372 U8 LUN[8]; /* 10h */ 1373 U32 Reserved3; /* 18h */ 1374 U32 Reserved4; /* 1Ch */ 1375 U32 Reserved5; /* 20h */ 1376 U32 Reserved6; /* 24h */ 1377 U32 Reserved7; /* 28h */ 1378 U32 Reserved8; /* 2Ch */ 1379 U32 Reserved9; /* 30h */ 1380 U32 Reserved10; /* 34h */ 1381 U32 Reserved11; /* 38h */ 1382 U32 Reserved12; /* 3Ch */ 1383 U32 Reserved13; /* 40h */ 1384 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN; 1385 1386 typedef struct _MPI_BOOT_DEVICE_SAS_WWN 1387 { 1388 U64 SASAddress; /* 00h */ 1389 U32 Reserved1; /* 08h */ 1390 U32 Reserved2; /* 0Ch */ 1391 U8 LUN[8]; /* 10h */ 1392 U32 Reserved3; /* 18h */ 1393 U32 Reserved4; /* 1Ch */ 1394 U32 Reserved5; /* 20h */ 1395 U32 Reserved6; /* 24h */ 1396 U32 Reserved7; /* 28h */ 1397 U32 Reserved8; /* 2Ch */ 1398 U32 Reserved9; /* 30h */ 1399 U32 Reserved10; /* 34h */ 1400 U32 Reserved11; /* 38h */ 1401 U32 Reserved12; /* 3Ch */ 1402 U32 Reserved13; /* 40h */ 1403 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN; 1404 1405 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT 1406 { 1407 U64 EnclosureLogicalID; /* 00h */ 1408 U32 Reserved1; /* 08h */ 1409 U32 Reserved2; /* 0Ch */ 1410 U8 LUN[8]; /* 10h */ 1411 U16 SlotNumber; /* 18h */ 1412 U16 Reserved3; /* 1Ah */ 1413 U32 Reserved4; /* 1Ch */ 1414 U32 Reserved5; /* 20h */ 1415 U32 Reserved6; /* 24h */ 1416 U32 Reserved7; /* 28h */ 1417 U32 Reserved8; /* 2Ch */ 1418 U32 Reserved9; /* 30h */ 1419 U32 Reserved10; /* 34h */ 1420 U32 Reserved11; /* 38h */ 1421 U32 Reserved12; /* 3Ch */ 1422 U32 Reserved13; /* 40h */ 1423 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT, 1424 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT; 1425 1426 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE 1427 { 1428 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1429 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber; 1430 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress; 1431 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber; 1432 MPI_BOOT_DEVICE_FC_WWN FcWwn; 1433 MPI_BOOT_DEVICE_SAS_WWN SasWwn; 1434 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1435 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE; 1436 1437 typedef struct _CONFIG_PAGE_BIOS_2 1438 { 1439 CONFIG_PAGE_HEADER Header; /* 00h */ 1440 U32 Reserved1; /* 04h */ 1441 U32 Reserved2; /* 08h */ 1442 U32 Reserved3; /* 0Ch */ 1443 U32 Reserved4; /* 10h */ 1444 U32 Reserved5; /* 14h */ 1445 U32 Reserved6; /* 18h */ 1446 U8 BootDeviceForm; /* 1Ch */ 1447 U8 PrevBootDeviceForm; /* 1Ch */ 1448 U16 Reserved8; /* 1Eh */ 1449 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */ 1450 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2, 1451 BIOSPage2_t, MPI_POINTER pBIOSPage2_t; 1452 1453 #define MPI_BIOSPAGE2_PAGEVERSION (0x02) 1454 1455 #define MPI_BIOSPAGE2_FORM_MASK (0x0F) 1456 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00) 1457 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01) 1458 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02) 1459 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03) 1460 #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04) 1461 #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05) 1462 #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1463 1464 typedef struct _CONFIG_PAGE_BIOS_4 1465 { 1466 CONFIG_PAGE_HEADER Header; /* 00h */ 1467 U64 ReassignmentBaseWWID; /* 04h */ 1468 } CONFIG_PAGE_BIOS_4, MPI_POINTER PTR_CONFIG_PAGE_BIOS_4, 1469 BIOSPage4_t, MPI_POINTER pBIOSPage4_t; 1470 1471 #define MPI_BIOSPAGE4_PAGEVERSION (0x00) 1472 1473 /**************************************************************************** 1474 * SCSI Port Config Pages 1475 ****************************************************************************/ 1476 1477 typedef struct _CONFIG_PAGE_SCSI_PORT_0 1478 { 1479 CONFIG_PAGE_HEADER Header; /* 00h */ 1480 U32 Capabilities; /* 04h */ 1481 U32 PhysicalInterface; /* 08h */ 1482 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 1483 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 1484 1485 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02) 1486 1487 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 1488 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 1489 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 1490 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1491 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00) 1492 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32) 1493 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19) 1494 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C) 1495 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B) 1496 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A) 1497 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09) 1498 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08) 1499 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF) 1500 1501 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8) 1502 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \ 1503 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \ 1504 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \ 1505 ) 1506 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1507 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16) 1508 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \ 1509 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \ 1510 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \ 1511 ) 1512 #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000) 1513 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 1514 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 1515 1516 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 1517 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 1518 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 1519 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 1520 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000) 1521 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24) 1522 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE) 1523 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF) 1524 1525 typedef struct _CONFIG_PAGE_SCSI_PORT_1 1526 { 1527 CONFIG_PAGE_HEADER Header; /* 00h */ 1528 U32 Configuration; /* 04h */ 1529 U32 OnBusTimerValue; /* 08h */ 1530 U8 TargetConfig; /* 0Ch */ 1531 U8 Reserved1; /* 0Dh */ 1532 U16 IDConfig; /* 0Eh */ 1533 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 1534 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 1535 1536 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03) 1537 1538 /* Configuration values */ 1539 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 1540 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 1541 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16) 1542 1543 /* TargetConfig values */ 1544 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01) 1545 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02) 1546 1547 typedef struct _MPI_DEVICE_INFO 1548 { 1549 U8 Timeout; /* 00h */ 1550 U8 SyncFactor; /* 01h */ 1551 U16 DeviceFlags; /* 02h */ 1552 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 1553 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 1554 1555 typedef struct _CONFIG_PAGE_SCSI_PORT_2 1556 { 1557 CONFIG_PAGE_HEADER Header; /* 00h */ 1558 U32 PortFlags; /* 04h */ 1559 U32 PortSettings; /* 08h */ 1560 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 1561 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 1562 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 1563 1564 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02) 1565 1566 /* PortFlags values */ 1567 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 1568 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 1569 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1570 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 1571 1572 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060) 1573 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000) 1574 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020) 1575 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060) 1576 1577 /* PortSettings values */ 1578 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 1579 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 1580 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 1581 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 1582 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 1583 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 1584 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 1585 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000) 1586 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040) 1587 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080) 1588 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 1589 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8) 1590 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 1591 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 1592 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 1593 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 1594 1595 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 1596 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 1597 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 1598 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 1599 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 1600 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 1601 1602 /**************************************************************************** 1603 * SCSI Target Device Config Pages 1604 ****************************************************************************/ 1605 1606 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 1607 { 1608 CONFIG_PAGE_HEADER Header; /* 00h */ 1609 U32 NegotiatedParameters; /* 04h */ 1610 U32 Information; /* 08h */ 1611 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 1612 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 1613 1614 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04) 1615 1616 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 1617 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 1618 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 1619 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008) 1620 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010) 1621 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020) 1622 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040) 1623 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080) 1624 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 1625 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8) 1626 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 1627 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16) 1628 #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000) 1629 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 1630 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 1631 1632 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 1633 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 1634 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 1635 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 1636 1637 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 1638 { 1639 CONFIG_PAGE_HEADER Header; /* 00h */ 1640 U32 RequestedParameters; /* 04h */ 1641 U32 Reserved; /* 08h */ 1642 U32 Configuration; /* 0Ch */ 1643 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 1644 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 1645 1646 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05) 1647 1648 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 1649 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 1650 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 1651 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008) 1652 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010) 1653 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020) 1654 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040) 1655 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080) 1656 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1657 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8) 1658 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1659 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16) 1660 #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000) 1661 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 1662 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 1663 1664 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 1665 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 1666 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008) 1667 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010) 1668 1669 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 1670 { 1671 CONFIG_PAGE_HEADER Header; /* 00h */ 1672 U32 DomainValidation; /* 04h */ 1673 U32 ParityPipeSelect; /* 08h */ 1674 U32 DataPipeSelect; /* 0Ch */ 1675 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 1676 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 1677 1678 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01) 1679 1680 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 1681 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 1682 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 1683 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 1684 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 1685 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 1686 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 1687 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 1688 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 1689 1690 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 1691 1692 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 1693 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 1694 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 1695 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 1696 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 1697 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 1698 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 1699 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 1700 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 1701 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 1702 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 1703 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 1704 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 1705 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 1706 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 1707 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 1708 1709 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3 1710 { 1711 CONFIG_PAGE_HEADER Header; /* 00h */ 1712 U16 MsgRejectCount; /* 04h */ 1713 U16 PhaseErrorCount; /* 06h */ 1714 U16 ParityErrorCount; /* 08h */ 1715 U16 Reserved; /* 0Ah */ 1716 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3, 1717 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t; 1718 1719 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00) 1720 1721 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE) 1722 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF) 1723 1724 /**************************************************************************** 1725 * FC Port Config Pages 1726 ****************************************************************************/ 1727 1728 typedef struct _CONFIG_PAGE_FC_PORT_0 1729 { 1730 CONFIG_PAGE_HEADER Header; /* 00h */ 1731 U32 Flags; /* 04h */ 1732 U8 MPIPortNumber; /* 08h */ 1733 U8 LinkType; /* 09h */ 1734 U8 PortState; /* 0Ah */ 1735 U8 Reserved; /* 0Bh */ 1736 U32 PortIdentifier; /* 0Ch */ 1737 U64 WWNN; /* 10h */ 1738 U64 WWPN; /* 18h */ 1739 U32 SupportedServiceClass; /* 20h */ 1740 U32 SupportedSpeeds; /* 24h */ 1741 U32 CurrentSpeed; /* 28h */ 1742 U32 MaxFrameSize; /* 2Ch */ 1743 U64 FabricWWNN; /* 30h */ 1744 U64 FabricWWPN; /* 38h */ 1745 U32 DiscoveredPortsCount; /* 40h */ 1746 U32 MaxInitiators; /* 44h */ 1747 U8 MaxAliasesSupported; /* 48h */ 1748 U8 MaxHardAliasesSupported; /* 49h */ 1749 U8 NumCurrentAliases; /* 4Ah */ 1750 U8 Reserved1; /* 4Bh */ 1751 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 1752 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 1753 1754 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02) 1755 1756 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 1757 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 1758 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 1759 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 1760 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 1761 1762 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 1763 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 1764 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040) 1765 1766 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 1767 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 1768 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 1769 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 1770 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 1771 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 1772 1773 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 1774 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 1775 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 1776 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 1777 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 1778 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 1779 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 1780 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 1781 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 1782 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 1783 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 1784 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 1785 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 1786 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 1787 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 1788 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 1789 1790 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 1791 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 1792 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 1793 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 1794 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 1795 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 1796 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 1797 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 1798 1799 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 1800 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 1801 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 1802 1803 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */ 1804 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 1805 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 1806 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 1807 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */ 1808 1809 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN 1810 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 1811 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 1812 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 1813 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED 1814 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */ 1815 1816 typedef struct _CONFIG_PAGE_FC_PORT_1 1817 { 1818 CONFIG_PAGE_HEADER Header; /* 00h */ 1819 U32 Flags; /* 04h */ 1820 U64 NoSEEPROMWWNN; /* 08h */ 1821 U64 NoSEEPROMWWPN; /* 10h */ 1822 U8 HardALPA; /* 18h */ 1823 U8 LinkConfig; /* 19h */ 1824 U8 TopologyConfig; /* 1Ah */ 1825 U8 AltConnector; /* 1Bh */ 1826 U8 NumRequestedAliases; /* 1Ch */ 1827 U8 RR_TOV; /* 1Dh */ 1828 U8 InitiatorDeviceTimeout; /* 1Eh */ 1829 U8 InitiatorIoPendTimeout; /* 1Fh */ 1830 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 1831 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 1832 1833 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06) 1834 1835 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 1836 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 1837 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000) 1838 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000) 1839 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000) 1840 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000) 1841 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000) 1842 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080) 1843 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070) 1844 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008) 1845 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004) 1846 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002) 1847 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 1848 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 1849 1850 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 1851 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 1852 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1853 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1854 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1855 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1856 1857 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000) 1858 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010) 1859 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030) 1860 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050) 1861 1862 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 1863 1864 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 1865 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 1866 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 1867 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 1868 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 1869 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 1870 1871 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 1872 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 1873 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 1874 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 1875 1876 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00) 1877 1878 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F) 1879 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80) 1880 1881 typedef struct _CONFIG_PAGE_FC_PORT_2 1882 { 1883 CONFIG_PAGE_HEADER Header; /* 00h */ 1884 U8 NumberActive; /* 04h */ 1885 U8 ALPA[127]; /* 05h */ 1886 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 1887 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 1888 1889 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 1890 1891 typedef struct _WWN_FORMAT 1892 { 1893 U64 WWNN; /* 00h */ 1894 U64 WWPN; /* 08h */ 1895 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 1896 WWNFormat, MPI_POINTER pWWNFormat; 1897 1898 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 1899 { 1900 WWN_FORMAT WWN; 1901 U32 Did; 1902 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 1903 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 1904 1905 typedef struct _FC_PORT_PERSISTENT 1906 { 1907 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 1908 U8 TargetID; /* 10h */ 1909 U8 Bus; /* 11h */ 1910 U16 Flags; /* 12h */ 1911 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 1912 PersistentData_t, MPI_POINTER pPersistentData_t; 1913 1914 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 1915 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 1916 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 1917 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 1918 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 1919 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 1920 1921 /* 1922 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1923 * one and check Header.PageLength at runtime. 1924 */ 1925 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 1926 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 1927 #endif 1928 1929 typedef struct _CONFIG_PAGE_FC_PORT_3 1930 { 1931 CONFIG_PAGE_HEADER Header; /* 00h */ 1932 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 1933 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 1934 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 1935 1936 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 1937 1938 typedef struct _CONFIG_PAGE_FC_PORT_4 1939 { 1940 CONFIG_PAGE_HEADER Header; /* 00h */ 1941 U32 PortFlags; /* 04h */ 1942 U32 PortSettings; /* 08h */ 1943 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 1944 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 1945 1946 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 1947 1948 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1949 1950 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 1951 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 1952 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 1953 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 1954 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 1955 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 1956 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 1957 1958 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 1959 { 1960 U8 Flags; /* 00h */ 1961 U8 AliasAlpa; /* 01h */ 1962 U16 Reserved; /* 02h */ 1963 U64 AliasWWNN; /* 04h */ 1964 U64 AliasWWPN; /* 0Ch */ 1965 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1966 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1967 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 1968 1969 typedef struct _CONFIG_PAGE_FC_PORT_5 1970 { 1971 CONFIG_PAGE_HEADER Header; /* 00h */ 1972 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */ 1973 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 1974 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 1975 1976 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02) 1977 1978 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01) 1979 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02) 1980 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04) 1981 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08) 1982 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10) 1983 1984 typedef struct _CONFIG_PAGE_FC_PORT_6 1985 { 1986 CONFIG_PAGE_HEADER Header; /* 00h */ 1987 U32 Reserved; /* 04h */ 1988 U64 TimeSinceReset; /* 08h */ 1989 U64 TxFrames; /* 10h */ 1990 U64 RxFrames; /* 18h */ 1991 U64 TxWords; /* 20h */ 1992 U64 RxWords; /* 28h */ 1993 U64 LipCount; /* 30h */ 1994 U64 NosCount; /* 38h */ 1995 U64 ErrorFrames; /* 40h */ 1996 U64 DumpedFrames; /* 48h */ 1997 U64 LinkFailureCount; /* 50h */ 1998 U64 LossOfSyncCount; /* 58h */ 1999 U64 LossOfSignalCount; /* 60h */ 2000 U64 PrimativeSeqErrCount; /* 68h */ 2001 U64 InvalidTxWordCount; /* 70h */ 2002 U64 InvalidCrcCount; /* 78h */ 2003 U64 FcpInitiatorIoCount; /* 80h */ 2004 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 2005 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 2006 2007 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 2008 2009 typedef struct _CONFIG_PAGE_FC_PORT_7 2010 { 2011 CONFIG_PAGE_HEADER Header; /* 00h */ 2012 U32 Reserved; /* 04h */ 2013 U8 PortSymbolicName[256]; /* 08h */ 2014 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 2015 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 2016 2017 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 2018 2019 typedef struct _CONFIG_PAGE_FC_PORT_8 2020 { 2021 CONFIG_PAGE_HEADER Header; /* 00h */ 2022 U32 BitVector[8]; /* 04h */ 2023 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 2024 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 2025 2026 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 2027 2028 typedef struct _CONFIG_PAGE_FC_PORT_9 2029 { 2030 CONFIG_PAGE_HEADER Header; /* 00h */ 2031 U32 Reserved; /* 04h */ 2032 U64 GlobalWWPN; /* 08h */ 2033 U64 GlobalWWNN; /* 10h */ 2034 U32 UnitType; /* 18h */ 2035 U32 PhysicalPortNumber; /* 1Ch */ 2036 U32 NumAttachedNodes; /* 20h */ 2037 U16 IPVersion; /* 24h */ 2038 U16 UDPPortNumber; /* 26h */ 2039 U8 IPAddress[16]; /* 28h */ 2040 U16 Reserved1; /* 38h */ 2041 U16 TopologyDiscoveryFlags; /* 3Ah */ 2042 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 2043 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 2044 2045 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 2046 2047 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA 2048 { 2049 U8 Id; /* 10h */ 2050 U8 ExtId; /* 11h */ 2051 U8 Connector; /* 12h */ 2052 U8 Transceiver[8]; /* 13h */ 2053 U8 Encoding; /* 1Bh */ 2054 U8 BitRate_100mbs; /* 1Ch */ 2055 U8 Reserved1; /* 1Dh */ 2056 U8 Length9u_km; /* 1Eh */ 2057 U8 Length9u_100m; /* 1Fh */ 2058 U8 Length50u_10m; /* 20h */ 2059 U8 Length62p5u_10m; /* 21h */ 2060 U8 LengthCopper_m; /* 22h */ 2061 U8 Reseverved2; /* 22h */ 2062 U8 VendorName[16]; /* 24h */ 2063 U8 Reserved3; /* 34h */ 2064 U8 VendorOUI[3]; /* 35h */ 2065 U8 VendorPN[16]; /* 38h */ 2066 U8 VendorRev[4]; /* 48h */ 2067 U16 Wavelength; /* 4Ch */ 2068 U8 Reserved4; /* 4Eh */ 2069 U8 CC_BASE; /* 4Fh */ 2070 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 2071 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 2072 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t; 2073 2074 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00) 2075 #define MPI_FCPORT10_BASE_ID_GBIC (0x01) 2076 #define MPI_FCPORT10_BASE_ID_FIXED (0x02) 2077 #define MPI_FCPORT10_BASE_ID_SFP (0x03) 2078 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04) 2079 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F) 2080 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80) 2081 2082 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00) 2083 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01) 2084 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02) 2085 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03) 2086 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04) 2087 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05) 2088 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06) 2089 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07) 2090 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80) 2091 2092 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00) 2093 #define MPI_FCPORT10_BASE_CONN_SC (0x01) 2094 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02) 2095 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03) 2096 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04) 2097 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05) 2098 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06) 2099 #define MPI_FCPORT10_BASE_CONN_LC (0x07) 2100 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08) 2101 #define MPI_FCPORT10_BASE_CONN_MU (0x09) 2102 #define MPI_FCPORT10_BASE_CONN_SG (0x0A) 2103 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B) 2104 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C) 2105 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F) 2106 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20) 2107 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21) 2108 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22) 2109 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F) 2110 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80) 2111 2112 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00) 2113 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01) 2114 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02) 2115 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03) 2116 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04) 2117 2118 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA 2119 { 2120 U8 Options[2]; /* 50h */ 2121 U8 BitRateMax; /* 52h */ 2122 U8 BitRateMin; /* 53h */ 2123 U8 VendorSN[16]; /* 54h */ 2124 U8 DateCode[8]; /* 64h */ 2125 U8 DiagMonitoringType; /* 6Ch */ 2126 U8 EnhancedOptions; /* 6Dh */ 2127 U8 SFF8472Compliance; /* 6Eh */ 2128 U8 CC_EXT; /* 6Fh */ 2129 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 2130 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 2131 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t; 2132 2133 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20) 2134 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10) 2135 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08) 2136 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04) 2137 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02) 2138 2139 typedef struct _CONFIG_PAGE_FC_PORT_10 2140 { 2141 CONFIG_PAGE_HEADER Header; /* 00h */ 2142 U8 Flags; /* 04h */ 2143 U8 Reserved1; /* 05h */ 2144 U16 Reserved2; /* 06h */ 2145 U32 HwConfig1; /* 08h */ 2146 U32 HwConfig2; /* 0Ch */ 2147 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */ 2148 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */ 2149 U8 VendorSpecific[32]; /* 70h */ 2150 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10, 2151 FCPortPage10_t, MPI_POINTER pFCPortPage10_t; 2152 2153 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01) 2154 2155 /* standard MODDEF pin definitions (from GBIC spec.) */ 2156 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007) 2157 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001) 2158 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002) 2159 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004) 2160 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007) 2161 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006) 2162 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005) 2163 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004) 2164 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003) 2165 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002) 2166 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001) 2167 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000) 2168 2169 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010) 2170 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020) 2171 2172 /**************************************************************************** 2173 * FC Device Config Pages 2174 ****************************************************************************/ 2175 2176 typedef struct _CONFIG_PAGE_FC_DEVICE_0 2177 { 2178 CONFIG_PAGE_HEADER Header; /* 00h */ 2179 U64 WWNN; /* 04h */ 2180 U64 WWPN; /* 0Ch */ 2181 U32 PortIdentifier; /* 14h */ 2182 U8 Protocol; /* 18h */ 2183 U8 Flags; /* 19h */ 2184 U16 BBCredit; /* 1Ah */ 2185 U16 MaxRxFrameSize; /* 1Ch */ 2186 U8 ADISCHardALPA; /* 1Eh */ 2187 U8 PortNumber; /* 1Fh */ 2188 U8 FcPhLowestVersion; /* 20h */ 2189 U8 FcPhHighestVersion; /* 21h */ 2190 U8 CurrentTargetID; /* 22h */ 2191 U8 CurrentBus; /* 23h */ 2192 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 2193 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 2194 2195 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03) 2196 2197 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 2198 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02) 2199 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04) 2200 2201 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 2202 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 2203 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 2204 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08) 2205 2206 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 2207 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 2208 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 2209 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 2210 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 2211 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 2212 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 2213 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 2214 2215 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF) 2216 2217 /**************************************************************************** 2218 * RAID Volume Config Pages 2219 ****************************************************************************/ 2220 2221 typedef struct _RAID_VOL0_PHYS_DISK 2222 { 2223 U16 Reserved; /* 00h */ 2224 U8 PhysDiskMap; /* 02h */ 2225 U8 PhysDiskNum; /* 03h */ 2226 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 2227 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 2228 2229 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 2230 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 2231 2232 typedef struct _RAID_VOL0_STATUS 2233 { 2234 U8 Flags; /* 00h */ 2235 U8 State; /* 01h */ 2236 U16 Reserved; /* 02h */ 2237 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 2238 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 2239 2240 /* RAID Volume Page 0 VolumeStatus defines */ 2241 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 2242 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 2243 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 2244 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08) 2245 #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10) 2246 2247 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 2248 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 2249 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 2250 #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03) 2251 2252 typedef struct _RAID_VOL0_SETTINGS 2253 { 2254 U16 Settings; /* 00h */ 2255 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2256 U8 Reserved; /* 02h */ 2257 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 2258 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 2259 2260 /* RAID Volume Page 0 VolumeSettings defines */ 2261 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 2262 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 2263 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 2264 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 2265 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */ 2266 2267 #define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE (0x00C0) 2268 #define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE (0x0000) 2269 #define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE (0x0040) 2270 2271 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 2272 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 2273 2274 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 2275 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 2276 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 2277 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 2278 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 2279 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 2280 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 2281 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 2282 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 2283 2284 /* 2285 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2286 * one and check Header.PageLength at runtime. 2287 */ 2288 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 2289 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 2290 #endif 2291 2292 typedef struct _CONFIG_PAGE_RAID_VOL_0 2293 { 2294 CONFIG_PAGE_HEADER Header; /* 00h */ 2295 U8 VolumeID; /* 04h */ 2296 U8 VolumeBus; /* 05h */ 2297 U8 VolumeIOC; /* 06h */ 2298 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 2299 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 2300 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 2301 U32 MaxLBA; /* 10h */ 2302 U32 MaxLBAHigh; /* 14h */ 2303 U32 StripeSize; /* 18h */ 2304 U32 Reserved2; /* 1Ch */ 2305 U32 Reserved3; /* 20h */ 2306 U8 NumPhysDisks; /* 24h */ 2307 U8 DataScrubRate; /* 25h */ 2308 U8 ResyncRate; /* 26h */ 2309 U8 InactiveStatus; /* 27h */ 2310 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 2311 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 2312 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 2313 2314 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x07) 2315 2316 /* values for RAID Volume Page 0 InactiveStatus field */ 2317 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 2318 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 2319 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 2320 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 2321 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 2322 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 2323 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 2324 2325 typedef struct _CONFIG_PAGE_RAID_VOL_1 2326 { 2327 CONFIG_PAGE_HEADER Header; /* 00h */ 2328 U8 VolumeID; /* 04h */ 2329 U8 VolumeBus; /* 05h */ 2330 U8 VolumeIOC; /* 06h */ 2331 U8 Reserved0; /* 07h */ 2332 U8 GUID[24]; /* 08h */ 2333 U8 Name[32]; /* 20h */ 2334 U64 WWID; /* 40h */ 2335 U32 Reserved1; /* 48h */ 2336 U32 Reserved2; /* 4Ch */ 2337 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1, 2338 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t; 2339 2340 #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01) 2341 2342 /**************************************************************************** 2343 * RAID Physical Disk Config Pages 2344 ****************************************************************************/ 2345 2346 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 2347 { 2348 U8 ErrorCdbByte; /* 00h */ 2349 U8 ErrorSenseKey; /* 01h */ 2350 U16 Reserved; /* 02h */ 2351 U16 ErrorCount; /* 04h */ 2352 U8 ErrorASC; /* 06h */ 2353 U8 ErrorASCQ; /* 07h */ 2354 U16 SmartCount; /* 08h */ 2355 U8 SmartASC; /* 0Ah */ 2356 U8 SmartASCQ; /* 0Bh */ 2357 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 2358 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 2359 2360 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 2361 { 2362 U8 VendorID[8]; /* 00h */ 2363 U8 ProductID[16]; /* 08h */ 2364 U8 ProductRevLevel[4]; /* 18h */ 2365 U8 Info[32]; /* 1Ch */ 2366 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 2367 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 2368 2369 typedef struct _RAID_PHYS_DISK0_SETTINGS 2370 { 2371 U8 SepID; /* 00h */ 2372 U8 SepBus; /* 01h */ 2373 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2374 U8 PhysDiskSettings; /* 03h */ 2375 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 2376 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 2377 2378 typedef struct _RAID_PHYS_DISK0_STATUS 2379 { 2380 U8 Flags; /* 00h */ 2381 U8 State; /* 01h */ 2382 U16 Reserved; /* 02h */ 2383 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 2384 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 2385 2386 /* RAID Physical Disk PhysDiskStatus flags */ 2387 2388 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 2389 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 2390 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04) 2391 #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00) 2392 #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08) 2393 2394 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 2395 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 2396 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 2397 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 2398 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 2399 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 2400 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 2401 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 2402 2403 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 2404 { 2405 CONFIG_PAGE_HEADER Header; /* 00h */ 2406 U8 PhysDiskID; /* 04h */ 2407 U8 PhysDiskBus; /* 05h */ 2408 U8 PhysDiskIOC; /* 06h */ 2409 U8 PhysDiskNum; /* 07h */ 2410 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 2411 U32 Reserved1; /* 0Ch */ 2412 U8 ExtDiskIdentifier[8]; /* 10h */ 2413 U8 DiskIdentifier[16]; /* 18h */ 2414 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 2415 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 2416 U32 MaxLBA; /* 68h */ 2417 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 2418 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 2419 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 2420 2421 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02) 2422 2423 typedef struct _RAID_PHYS_DISK1_PATH 2424 { 2425 U8 PhysDiskID; /* 00h */ 2426 U8 PhysDiskBus; /* 01h */ 2427 U16 Reserved1; /* 02h */ 2428 U64 WWID; /* 04h */ 2429 U64 OwnerWWID; /* 0Ch */ 2430 U8 OwnerIdentifier; /* 14h */ 2431 U8 Reserved2; /* 15h */ 2432 U16 Flags; /* 16h */ 2433 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH, 2434 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t; 2435 2436 /* RAID Physical Disk Page 1 Flags field defines */ 2437 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2438 #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2439 2440 /* 2441 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2442 * one and check Header.PageLength or NumPhysDiskPaths at runtime. 2443 */ 2444 #ifndef MPI_RAID_PHYS_DISK1_PATH_MAX 2445 #define MPI_RAID_PHYS_DISK1_PATH_MAX (1) 2446 #endif 2447 2448 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1 2449 { 2450 CONFIG_PAGE_HEADER Header; /* 00h */ 2451 U8 NumPhysDiskPaths; /* 04h */ 2452 U8 PhysDiskNum; /* 05h */ 2453 U16 Reserved2; /* 06h */ 2454 U32 Reserved1; /* 08h */ 2455 RAID_PHYS_DISK1_PATH Path[MPI_RAID_PHYS_DISK1_PATH_MAX];/* 0Ch */ 2456 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1, 2457 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t; 2458 2459 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00) 2460 2461 /**************************************************************************** 2462 * LAN Config Pages 2463 ****************************************************************************/ 2464 2465 typedef struct _CONFIG_PAGE_LAN_0 2466 { 2467 ConfigPageHeader_t Header; /* 00h */ 2468 U16 TxRxModes; /* 04h */ 2469 U16 Reserved; /* 06h */ 2470 U32 PacketPrePad; /* 08h */ 2471 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 2472 LANPage0_t, MPI_POINTER pLANPage0_t; 2473 2474 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 2475 2476 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 2477 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 2478 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 2479 2480 typedef struct _CONFIG_PAGE_LAN_1 2481 { 2482 ConfigPageHeader_t Header; /* 00h */ 2483 U16 Reserved; /* 04h */ 2484 U8 CurrentDeviceState; /* 06h */ 2485 U8 Reserved1; /* 07h */ 2486 U32 MinPacketSize; /* 08h */ 2487 U32 MaxPacketSize; /* 0Ch */ 2488 U32 HardwareAddressLow; /* 10h */ 2489 U32 HardwareAddressHigh; /* 14h */ 2490 U32 MaxWireSpeedLow; /* 18h */ 2491 U32 MaxWireSpeedHigh; /* 1Ch */ 2492 U32 BucketsRemaining; /* 20h */ 2493 U32 MaxReplySize; /* 24h */ 2494 U32 NegWireSpeedLow; /* 28h */ 2495 U32 NegWireSpeedHigh; /* 2Ch */ 2496 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 2497 LANPage1_t, MPI_POINTER pLANPage1_t; 2498 2499 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 2500 2501 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 2502 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 2503 2504 /**************************************************************************** 2505 * Inband Config Pages 2506 ****************************************************************************/ 2507 2508 typedef struct _CONFIG_PAGE_INBAND_0 2509 { 2510 CONFIG_PAGE_HEADER Header; /* 00h */ 2511 MPI_VERSION_FORMAT InbandVersion; /* 04h */ 2512 U16 MaximumBuffers; /* 08h */ 2513 U16 Reserved1; /* 0Ah */ 2514 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0, 2515 InbandPage0_t, MPI_POINTER pInbandPage0_t; 2516 2517 #define MPI_INBAND_PAGEVERSION (0x00) 2518 2519 /**************************************************************************** 2520 * SAS IO Unit Config Pages 2521 ****************************************************************************/ 2522 2523 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA 2524 { 2525 U8 Port; /* 00h */ 2526 U8 PortFlags; /* 01h */ 2527 U8 PhyFlags; /* 02h */ 2528 U8 NegotiatedLinkRate; /* 03h */ 2529 U32 ControllerPhyDeviceInfo;/* 04h */ 2530 U16 AttachedDeviceHandle; /* 08h */ 2531 U16 ControllerDevHandle; /* 0Ah */ 2532 U32 DiscoveryStatus; /* 0Ch */ 2533 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA, 2534 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData; 2535 2536 /* 2537 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2538 * one and check Header.PageLength at runtime. 2539 */ 2540 #ifndef MPI_SAS_IOUNIT0_PHY_MAX 2541 #define MPI_SAS_IOUNIT0_PHY_MAX (1) 2542 #endif 2543 2544 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0 2545 { 2546 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2547 U16 NvdataVersionDefault; /* 08h */ 2548 U16 NvdataVersionPersistent; /* 0Ah */ 2549 U8 NumPhys; /* 0Ch */ 2550 U8 Reserved2; /* 0Dh */ 2551 U16 Reserved3; /* 0Eh */ 2552 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */ 2553 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0, 2554 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t; 2555 2556 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x04) 2557 2558 /* values for SAS IO Unit Page 0 PortFlags */ 2559 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08) 2560 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 2561 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 2562 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2563 2564 /* values for SAS IO Unit Page 0 PhyFlags */ 2565 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04) 2566 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02) 2567 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01) 2568 2569 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */ 2570 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00) 2571 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01) 2572 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02) 2573 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03) 2574 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08) 2575 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09) 2576 #define MPI_SAS_IOUNIT0_RATE_6_0 (0x0A) 2577 2578 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2579 2580 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 2581 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001) 2582 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2583 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2584 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008) 2585 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2586 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2587 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2588 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2589 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2590 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2591 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400) 2592 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2593 #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000) 2594 #define MPI_SAS_IOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2595 2596 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA 2597 { 2598 U8 Port; /* 00h */ 2599 U8 PortFlags; /* 01h */ 2600 U8 PhyFlags; /* 02h */ 2601 U8 MaxMinLinkRate; /* 03h */ 2602 U32 ControllerPhyDeviceInfo; /* 04h */ 2603 U16 MaxTargetPortConnectTime; /* 08h */ 2604 U16 Reserved1; /* 0Ah */ 2605 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA, 2606 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData; 2607 2608 /* 2609 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2610 * one and check Header.PageLength at runtime. 2611 */ 2612 #ifndef MPI_SAS_IOUNIT1_PHY_MAX 2613 #define MPI_SAS_IOUNIT1_PHY_MAX (1) 2614 #endif 2615 2616 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1 2617 { 2618 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2619 U16 ControlFlags; /* 08h */ 2620 U16 MaxNumSATATargets; /* 0Ah */ 2621 U16 AdditionalControlFlags; /* 0Ch */ 2622 U16 Reserved1; /* 0Eh */ 2623 U8 NumPhys; /* 10h */ 2624 U8 SATAMaxQDepth; /* 11h */ 2625 U8 ReportDeviceMissingDelay; /* 12h */ 2626 U8 IODeviceMissingDelay; /* 13h */ 2627 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */ 2628 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1, 2629 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t; 2630 2631 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x07) 2632 2633 /* values for SAS IO Unit Page 1 ControlFlags */ 2634 #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2635 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2636 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2637 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2638 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800) 2639 2640 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2641 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2642 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00) 2643 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01) 2644 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02) 2645 2646 #define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100) 2647 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2648 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2649 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2650 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2651 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008) 2652 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2653 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2654 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2655 2656 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 2657 #define MPI_SAS_IOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2658 #define MPI_SAS_IOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2659 #define MPI_SAS_IOUNIT1_ACONTROL_HIDE_NONZERO_ATTACHED_PHY_IDENT (0x0020) 2660 #define MPI_SAS_IOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2661 #define MPI_SAS_IOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2662 #define MPI_SAS_IOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2663 #define MPI_SAS_IOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2664 #define MPI_SAS_IOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2665 2666 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2667 #define MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2668 #define MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2669 2670 /* values for SAS IO Unit Page 1 PortFlags */ 2671 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 2672 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 2673 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2674 2675 /* values for SAS IO Unit Page 0 PhyFlags */ 2676 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04) 2677 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02) 2678 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01) 2679 2680 /* values for SAS IO Unit Page 0 MaxMinLinkRate */ 2681 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0) 2682 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80) 2683 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90) 2684 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F) 2685 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08) 2686 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09) 2687 2688 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2689 2690 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2 2691 { 2692 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2693 U8 NumDevsPerEnclosure; /* 08h */ 2694 U8 BootDeviceWaitTime; /* 09h */ 2695 U16 Reserved2; /* 0Ah */ 2696 U16 MaxPersistentIDs; /* 0Ch */ 2697 U16 NumPersistentIDsUsed; /* 0Eh */ 2698 U8 Status; /* 10h */ 2699 U8 Flags; /* 11h */ 2700 U16 MaxNumPhysicalMappedIDs;/* 12h */ 2701 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2, 2702 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t; 2703 2704 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x07) 2705 2706 /* values for SAS IO Unit Page 2 Status field */ 2707 #define MPI_SAS_IOUNIT2_STATUS_DEVICE_LIMIT_EXCEEDED (0x08) 2708 #define MPI_SAS_IOUNIT2_STATUS_ENCLOSURE_DEVICES_UNMAPPED (0x04) 2709 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02) 2710 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01) 2711 2712 /* values for SAS IO Unit Page 2 Flags field */ 2713 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01) 2714 /* Physical Mapping Modes */ 2715 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E) 2716 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1) 2717 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00) 2718 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01) 2719 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02) 2720 #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07) 2721 2722 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10) 2723 #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20) 2724 2725 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3 2726 { 2727 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2728 U32 Reserved1; /* 08h */ 2729 U32 MaxInvalidDwordCount; /* 0Ch */ 2730 U32 InvalidDwordCountTime; /* 10h */ 2731 U32 MaxRunningDisparityErrorCount; /* 14h */ 2732 U32 RunningDisparityErrorTime; /* 18h */ 2733 U32 MaxLossDwordSynchCount; /* 1Ch */ 2734 U32 LossDwordSynchCountTime; /* 20h */ 2735 U32 MaxPhyResetProblemCount; /* 24h */ 2736 U32 PhyResetProblemTime; /* 28h */ 2737 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3, 2738 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t; 2739 2740 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00) 2741 2742 /**************************************************************************** 2743 * SAS Expander Config Pages 2744 ****************************************************************************/ 2745 2746 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0 2747 { 2748 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2749 U8 PhysicalPort; /* 08h */ 2750 U8 Reserved1; /* 09h */ 2751 U16 EnclosureHandle; /* 0Ah */ 2752 U64 SASAddress; /* 0Ch */ 2753 U32 DiscoveryStatus; /* 14h */ 2754 U16 DevHandle; /* 18h */ 2755 U16 ParentDevHandle; /* 1Ah */ 2756 U16 ExpanderChangeCount; /* 1Ch */ 2757 U16 ExpanderRouteIndexes; /* 1Eh */ 2758 U8 NumPhys; /* 20h */ 2759 U8 SASLevel; /* 21h */ 2760 U8 Flags; /* 22h */ 2761 U8 Reserved3; /* 23h */ 2762 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0, 2763 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t; 2764 2765 #define MPI_SASEXPANDER0_PAGEVERSION (0x03) 2766 2767 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2768 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2769 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2770 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2771 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008) 2772 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2773 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2774 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2775 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2776 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2777 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2778 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2779 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2780 2781 /* values for SAS Expander Page 0 Flags field */ 2782 #define MPI_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x04) 2783 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02) 2784 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01) 2785 2786 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1 2787 { 2788 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2789 U8 PhysicalPort; /* 08h */ 2790 U8 Reserved1; /* 09h */ 2791 U16 Reserved2; /* 0Ah */ 2792 U8 NumPhys; /* 0Ch */ 2793 U8 Phy; /* 0Dh */ 2794 U16 NumTableEntriesProgrammed; /* 0Eh */ 2795 U8 ProgrammedLinkRate; /* 10h */ 2796 U8 HwLinkRate; /* 11h */ 2797 U16 AttachedDevHandle; /* 12h */ 2798 U32 PhyInfo; /* 14h */ 2799 U32 AttachedDeviceInfo; /* 18h */ 2800 U16 OwnerDevHandle; /* 1Ch */ 2801 U8 ChangeCount; /* 1Eh */ 2802 U8 NegotiatedLinkRate; /* 1Fh */ 2803 U8 PhyIdentifier; /* 20h */ 2804 U8 AttachedPhyIdentifier; /* 21h */ 2805 U8 Reserved3; /* 22h */ 2806 U8 DiscoveryInfo; /* 23h */ 2807 U32 Reserved4; /* 24h */ 2808 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1, 2809 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t; 2810 2811 #define MPI_SASEXPANDER1_PAGEVERSION (0x01) 2812 2813 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */ 2814 2815 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */ 2816 2817 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */ 2818 2819 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */ 2820 2821 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2822 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2823 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2824 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2825 2826 /* values for SAS Expander Page 1 NegotiatedLinkRate field */ 2827 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00) 2828 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01) 2829 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02) 2830 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03) 2831 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08) 2832 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09) 2833 2834 /**************************************************************************** 2835 * SAS Device Config Pages 2836 ****************************************************************************/ 2837 2838 typedef struct _CONFIG_PAGE_SAS_DEVICE_0 2839 { 2840 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2841 U16 Slot; /* 08h */ 2842 U16 EnclosureHandle; /* 0Ah */ 2843 U64 SASAddress; /* 0Ch */ 2844 U16 ParentDevHandle; /* 14h */ 2845 U8 PhyNum; /* 16h */ 2846 U8 AccessStatus; /* 17h */ 2847 U16 DevHandle; /* 18h */ 2848 U8 TargetID; /* 1Ah */ 2849 U8 Bus; /* 1Bh */ 2850 U32 DeviceInfo; /* 1Ch */ 2851 U16 Flags; /* 20h */ 2852 U8 PhysicalPort; /* 22h */ 2853 U8 Reserved2; /* 23h */ 2854 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0, 2855 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t; 2856 2857 #define MPI_SASDEVICE0_PAGEVERSION (0x05) 2858 2859 /* values for SAS Device Page 0 AccessStatus field */ 2860 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2861 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2862 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2863 #define MPI_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2864 #define MPI_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2865 /* specific values for SATA Init failures */ 2866 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2867 #define MPI_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2868 #define MPI_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2869 #define MPI_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2870 #define MPI_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2871 #define MPI_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2872 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2873 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2874 #define MPI_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2875 #define MPI_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2876 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2877 2878 /* values for SAS Device Page 0 Flags field */ 2879 #define MPI_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2880 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2881 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2882 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2883 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2884 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2885 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2886 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2887 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004) 2888 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002) 2889 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2890 2891 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2892 2893 typedef struct _CONFIG_PAGE_SAS_DEVICE_1 2894 { 2895 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2896 U32 Reserved1; /* 08h */ 2897 U64 SASAddress; /* 0Ch */ 2898 U32 Reserved2; /* 14h */ 2899 U16 DevHandle; /* 18h */ 2900 U8 TargetID; /* 1Ah */ 2901 U8 Bus; /* 1Bh */ 2902 U8 InitialRegDeviceFIS[20];/* 1Ch */ 2903 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1, 2904 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t; 2905 2906 #define MPI_SASDEVICE1_PAGEVERSION (0x00) 2907 2908 typedef struct _CONFIG_PAGE_SAS_DEVICE_2 2909 { 2910 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2911 U64 PhysicalIdentifier; /* 08h */ 2912 U32 EnclosureMapping; /* 10h */ 2913 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2, 2914 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t; 2915 2916 #define MPI_SASDEVICE2_PAGEVERSION (0x01) 2917 2918 /* defines for SAS Device Page 2 EnclosureMapping field */ 2919 #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F) 2920 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0) 2921 #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0) 2922 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4) 2923 #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800) 2924 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11) 2925 2926 /**************************************************************************** 2927 * SAS PHY Config Pages 2928 ****************************************************************************/ 2929 2930 typedef struct _CONFIG_PAGE_SAS_PHY_0 2931 { 2932 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2933 U16 OwnerDevHandle; /* 08h */ 2934 U16 Reserved1; /* 0Ah */ 2935 U64 SASAddress; /* 0Ch */ 2936 U16 AttachedDevHandle; /* 14h */ 2937 U8 AttachedPhyIdentifier; /* 16h */ 2938 U8 Reserved2; /* 17h */ 2939 U32 AttachedDeviceInfo; /* 18h */ 2940 U8 ProgrammedLinkRate; /* 1Ch */ 2941 U8 HwLinkRate; /* 1Dh */ 2942 U8 ChangeCount; /* 1Eh */ 2943 U8 Flags; /* 1Fh */ 2944 U32 PhyInfo; /* 20h */ 2945 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0, 2946 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t; 2947 2948 #define MPI_SASPHY0_PAGEVERSION (0x01) 2949 2950 /* values for SAS PHY Page 0 ProgrammedLinkRate field */ 2951 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0) 2952 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2953 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80) 2954 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90) 2955 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F) 2956 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2957 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08) 2958 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09) 2959 2960 /* values for SAS PHY Page 0 HwLinkRate field */ 2961 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0) 2962 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80) 2963 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90) 2964 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F) 2965 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08) 2966 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09) 2967 2968 /* values for SAS PHY Page 0 Flags field */ 2969 #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2970 2971 /* values for SAS PHY Page 0 PhyInfo field */ 2972 #define MPI_SAS_PHY0_PHYINFO_PHY_VACANT (0x80000000) 2973 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2974 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000) 2975 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000) 2976 2977 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2978 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2979 2980 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2981 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000) 2982 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2983 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020) 2984 2985 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F) 2986 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000) 2987 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001) 2988 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002) 2989 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003) 2990 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008) 2991 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009) 2992 2993 typedef struct _CONFIG_PAGE_SAS_PHY_1 2994 { 2995 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2996 U32 Reserved1; /* 08h */ 2997 U32 InvalidDwordCount; /* 0Ch */ 2998 U32 RunningDisparityErrorCount; /* 10h */ 2999 U32 LossDwordSynchCount; /* 14h */ 3000 U32 PhyResetProblemCount; /* 18h */ 3001 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1, 3002 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t; 3003 3004 #define MPI_SASPHY1_PAGEVERSION (0x00) 3005 3006 /**************************************************************************** 3007 * SAS Enclosure Config Pages 3008 ****************************************************************************/ 3009 3010 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0 3011 { 3012 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3013 U32 Reserved1; /* 08h */ 3014 U64 EnclosureLogicalID; /* 0Ch */ 3015 U16 Flags; /* 14h */ 3016 U16 EnclosureHandle; /* 16h */ 3017 U16 NumSlots; /* 18h */ 3018 U16 StartSlot; /* 1Ah */ 3019 U8 StartTargetID; /* 1Ch */ 3020 U8 StartBus; /* 1Dh */ 3021 U8 SEPTargetID; /* 1Eh */ 3022 U8 SEPBus; /* 1Fh */ 3023 U32 Reserved2; /* 20h */ 3024 U32 Reserved3; /* 24h */ 3025 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0, 3026 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t; 3027 3028 #define MPI_SASENCLOSURE0_PAGEVERSION (0x01) 3029 3030 /* values for SAS Enclosure Page 0 Flags field */ 3031 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020) 3032 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010) 3033 3034 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3035 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3036 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3037 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3038 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3039 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3040 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3041 3042 /**************************************************************************** 3043 * Log Config Pages 3044 ****************************************************************************/ 3045 /* 3046 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3047 * one and check NumLogEntries at runtime. 3048 */ 3049 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES 3050 #define MPI_LOG_0_NUM_LOG_ENTRIES (1) 3051 #endif 3052 3053 #define MPI_LOG_0_LOG_DATA_LENGTH (0x1C) 3054 3055 typedef struct _MPI_LOG_0_ENTRY 3056 { 3057 U32 TimeStamp; /* 00h */ 3058 U32 Reserved1; /* 04h */ 3059 U16 LogSequence; /* 08h */ 3060 U16 LogEntryQualifier; /* 0Ah */ 3061 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */ 3062 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY, 3063 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t; 3064 3065 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 3066 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3067 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3068 3069 typedef struct _CONFIG_PAGE_LOG_0 3070 { 3071 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3072 U32 Reserved1; /* 08h */ 3073 U32 Reserved2; /* 0Ch */ 3074 U16 NumLogEntries; /* 10h */ 3075 U16 Reserved3; /* 12h */ 3076 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */ 3077 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0, 3078 LogPage0_t, MPI_POINTER pLogPage0_t; 3079 3080 #define MPI_LOG_0_PAGEVERSION (0x01) 3081 3082 #endif 3083