1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006-2015 LSI Corp. 5 * Copyright (c) 2013-2015 Avago Technologies 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 30 * 31 * $FreeBSD$ 32 */ 33 34 /* 35 * Copyright (c) 2006-2015 LSI Corporation. 36 * Copyright (c) 2013-2015 Avago Technologies 37 * 38 * 39 * Name: mpi2.h 40 * Title: MPI Message independent structures and definitions 41 * including System Interface Register Set and 42 * scatter/gather formats. 43 * Creation Date: June 21, 2006 44 * 45 * mpi2.h Version: 02.00.18 46 * 47 * Version History 48 * --------------- 49 * 50 * Date Version Description 51 * -------- -------- ------------------------------------------------------ 52 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 53 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 54 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 55 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 56 * Moved ReplyPostHostIndex register to offset 0x6C of the 57 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 58 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 59 * Added union of request descriptors. 60 * Added union of reply descriptors. 61 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 62 * Added define for MPI2_VERSION_02_00. 63 * Fixed the size of the FunctionDependent5 field in the 64 * MPI2_DEFAULT_REPLY structure. 65 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 66 * Removed the MPI-defined Fault Codes and extended the 67 * product specific codes up to 0xEFFF. 68 * Added a sixth key value for the WriteSequence register 69 * and changed the flush value to 0x0. 70 * Added message function codes for Diagnostic Buffer Post 71 * and Diagnsotic Release. 72 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 73 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 74 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 75 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 76 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 77 * Added #defines for marking a reply descriptor as unused. 78 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 79 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 80 * Moved LUN field defines from mpi2_init.h. 81 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 82 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 83 * In all request and reply descriptors, replaced VF_ID 84 * field with MSIxIndex field. 85 * Removed DevHandle field from 86 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 87 * bytes reserved. 88 * Added RAID Accelerator functionality. 89 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 90 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 91 * Added MSI-x index mask and shift for Reply Post Host 92 * Index register. 93 * Added function code for Host Based Discovery Action. 94 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 95 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 96 * Added defines for product-specific range of message 97 * function codes, 0xF0 to 0xFF. 98 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 99 * Added alternative defines for the SGE Direction bit. 100 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 101 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 102 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 103 * -------------------------------------------------------------------------- 104 */ 105 106 #ifndef MPI2_H 107 #define MPI2_H 108 109 110 /***************************************************************************** 111 * 112 * MPI Version Definitions 113 * 114 *****************************************************************************/ 115 116 #define MPI2_VERSION_MAJOR (0x02) 117 #define MPI2_VERSION_MINOR (0x00) 118 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 119 #define MPI2_VERSION_MAJOR_SHIFT (8) 120 #define MPI2_VERSION_MINOR_MASK (0x00FF) 121 #define MPI2_VERSION_MINOR_SHIFT (0) 122 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 123 MPI2_VERSION_MINOR) 124 125 #define MPI2_VERSION_02_00 (0x0200) 126 127 /* versioning for this MPI header set */ 128 #define MPI2_HEADER_VERSION_UNIT (0x12) 129 #define MPI2_HEADER_VERSION_DEV (0x00) 130 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 131 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 132 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 133 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 134 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 135 136 137 /***************************************************************************** 138 * 139 * IOC State Definitions 140 * 141 *****************************************************************************/ 142 143 #define MPI2_IOC_STATE_RESET (0x00000000) 144 #define MPI2_IOC_STATE_READY (0x10000000) 145 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 146 #define MPI2_IOC_STATE_FAULT (0x40000000) 147 148 #define MPI2_IOC_STATE_MASK (0xF0000000) 149 #define MPI2_IOC_STATE_SHIFT (28) 150 151 /* Fault state range for prodcut specific codes */ 152 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 153 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 154 155 156 /***************************************************************************** 157 * 158 * System Interface Register Definitions 159 * 160 *****************************************************************************/ 161 162 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 163 { 164 U32 Doorbell; /* 0x00 */ 165 U32 WriteSequence; /* 0x04 */ 166 U32 HostDiagnostic; /* 0x08 */ 167 U32 Reserved1; /* 0x0C */ 168 U32 DiagRWData; /* 0x10 */ 169 U32 DiagRWAddressLow; /* 0x14 */ 170 U32 DiagRWAddressHigh; /* 0x18 */ 171 U32 Reserved2[5]; /* 0x1C */ 172 U32 HostInterruptStatus; /* 0x30 */ 173 U32 HostInterruptMask; /* 0x34 */ 174 U32 DCRData; /* 0x38 */ 175 U32 DCRAddress; /* 0x3C */ 176 U32 Reserved3[2]; /* 0x40 */ 177 U32 ReplyFreeHostIndex; /* 0x48 */ 178 U32 Reserved4[8]; /* 0x4C */ 179 U32 ReplyPostHostIndex; /* 0x6C */ 180 U32 Reserved5; /* 0x70 */ 181 U32 HCBSize; /* 0x74 */ 182 U32 HCBAddressLow; /* 0x78 */ 183 U32 HCBAddressHigh; /* 0x7C */ 184 U32 Reserved6[16]; /* 0x80 */ 185 U32 RequestDescriptorPostLow; /* 0xC0 */ 186 U32 RequestDescriptorPostHigh; /* 0xC4 */ 187 U32 Reserved7[14]; /* 0xC8 */ 188 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 189 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 190 191 /* 192 * Defines for working with the Doorbell register. 193 */ 194 #define MPI2_DOORBELL_OFFSET (0x00000000) 195 196 /* IOC --> System values */ 197 #define MPI2_DOORBELL_USED (0x08000000) 198 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 199 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 200 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 201 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 202 203 /* System --> IOC values */ 204 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 205 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 206 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 207 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 208 209 210 /* 211 * Defines for the WriteSequence register 212 */ 213 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 214 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 215 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 216 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 217 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 218 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 219 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 220 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 221 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 222 223 /* 224 * Defines for the HostDiagnostic register 225 */ 226 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 227 228 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 229 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 230 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 231 232 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 233 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 234 #define MPI2_DIAG_HCB_MODE (0x00000100) 235 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 236 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 237 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 238 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 239 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 240 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 241 242 /* 243 * Offsets for DiagRWData and address 244 */ 245 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 246 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 247 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 248 249 /* 250 * Defines for the HostInterruptStatus register 251 */ 252 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 253 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 254 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 255 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 256 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 257 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 258 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 259 260 /* 261 * Defines for the HostInterruptMask register 262 */ 263 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 264 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 265 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 266 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 267 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 268 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 269 270 /* 271 * Offsets for DCRData and address 272 */ 273 #define MPI2_DCR_DATA_OFFSET (0x00000038) 274 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 275 276 /* 277 * Offset for the Reply Free Queue 278 */ 279 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 280 281 /* 282 * Defines for the Reply Descriptor Post Queue 283 */ 284 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 285 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 286 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 287 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 288 289 /* 290 * Defines for the HCBSize and address 291 */ 292 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 293 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 294 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 295 296 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 297 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 298 299 /* 300 * Offsets for the Request Queue 301 */ 302 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 303 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 304 305 306 /***************************************************************************** 307 * 308 * Message Descriptors 309 * 310 *****************************************************************************/ 311 312 /* Request Descriptors */ 313 314 /* Default Request Descriptor */ 315 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 316 { 317 U8 RequestFlags; /* 0x00 */ 318 U8 MSIxIndex; /* 0x01 */ 319 U16 SMID; /* 0x02 */ 320 U16 LMID; /* 0x04 */ 321 U16 DescriptorTypeDependent; /* 0x06 */ 322 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 323 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 324 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 325 326 /* defines for the RequestFlags field */ 327 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 328 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 329 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 330 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 331 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 332 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 333 334 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 335 336 337 /* High Priority Request Descriptor */ 338 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 339 { 340 U8 RequestFlags; /* 0x00 */ 341 U8 MSIxIndex; /* 0x01 */ 342 U16 SMID; /* 0x02 */ 343 U16 LMID; /* 0x04 */ 344 U16 Reserved1; /* 0x06 */ 345 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 346 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 347 Mpi2HighPriorityRequestDescriptor_t, 348 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 349 350 351 /* SCSI IO Request Descriptor */ 352 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 353 { 354 U8 RequestFlags; /* 0x00 */ 355 U8 MSIxIndex; /* 0x01 */ 356 U16 SMID; /* 0x02 */ 357 U16 LMID; /* 0x04 */ 358 U16 DevHandle; /* 0x06 */ 359 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 360 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 361 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 362 363 364 /* SCSI Target Request Descriptor */ 365 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 366 { 367 U8 RequestFlags; /* 0x00 */ 368 U8 MSIxIndex; /* 0x01 */ 369 U16 SMID; /* 0x02 */ 370 U16 LMID; /* 0x04 */ 371 U16 IoIndex; /* 0x06 */ 372 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 373 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 374 Mpi2SCSITargetRequestDescriptor_t, 375 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 376 377 378 /* RAID Accelerator Request Descriptor */ 379 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 380 { 381 U8 RequestFlags; /* 0x00 */ 382 U8 MSIxIndex; /* 0x01 */ 383 U16 SMID; /* 0x02 */ 384 U16 LMID; /* 0x04 */ 385 U16 Reserved; /* 0x06 */ 386 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 387 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 388 Mpi2RAIDAcceleratorRequestDescriptor_t, 389 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 390 391 392 /* union of Request Descriptors */ 393 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 394 { 395 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 396 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 397 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 398 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 399 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 400 U64 Words; 401 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 402 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 403 404 405 /* Reply Descriptors */ 406 407 /* Default Reply Descriptor */ 408 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 409 { 410 U8 ReplyFlags; /* 0x00 */ 411 U8 MSIxIndex; /* 0x01 */ 412 U16 DescriptorTypeDependent1; /* 0x02 */ 413 U32 DescriptorTypeDependent2; /* 0x04 */ 414 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 415 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 416 417 /* defines for the ReplyFlags field */ 418 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 419 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 420 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 421 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 422 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 423 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 424 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 425 426 /* values for marking a reply descriptor as unused */ 427 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 428 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 429 430 /* Address Reply Descriptor */ 431 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 432 { 433 U8 ReplyFlags; /* 0x00 */ 434 U8 MSIxIndex; /* 0x01 */ 435 U16 SMID; /* 0x02 */ 436 U32 ReplyFrameAddress; /* 0x04 */ 437 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 438 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 439 440 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 441 442 443 /* SCSI IO Success Reply Descriptor */ 444 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 445 { 446 U8 ReplyFlags; /* 0x00 */ 447 U8 MSIxIndex; /* 0x01 */ 448 U16 SMID; /* 0x02 */ 449 U16 TaskTag; /* 0x04 */ 450 U16 Reserved1; /* 0x06 */ 451 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 452 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 453 Mpi2SCSIIOSuccessReplyDescriptor_t, 454 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 455 456 457 /* TargetAssist Success Reply Descriptor */ 458 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 459 { 460 U8 ReplyFlags; /* 0x00 */ 461 U8 MSIxIndex; /* 0x01 */ 462 U16 SMID; /* 0x02 */ 463 U8 SequenceNumber; /* 0x04 */ 464 U8 Reserved1; /* 0x05 */ 465 U16 IoIndex; /* 0x06 */ 466 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 467 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 468 Mpi2TargetAssistSuccessReplyDescriptor_t, 469 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 470 471 472 /* Target Command Buffer Reply Descriptor */ 473 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 474 { 475 U8 ReplyFlags; /* 0x00 */ 476 U8 MSIxIndex; /* 0x01 */ 477 U8 VP_ID; /* 0x02 */ 478 U8 Flags; /* 0x03 */ 479 U16 InitiatorDevHandle; /* 0x04 */ 480 U16 IoIndex; /* 0x06 */ 481 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 482 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 483 Mpi2TargetCommandBufferReplyDescriptor_t, 484 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 485 486 /* defines for Flags field */ 487 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 488 489 490 /* RAID Accelerator Success Reply Descriptor */ 491 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 492 { 493 U8 ReplyFlags; /* 0x00 */ 494 U8 MSIxIndex; /* 0x01 */ 495 U16 SMID; /* 0x02 */ 496 U32 Reserved; /* 0x04 */ 497 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 498 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 499 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 500 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 501 502 503 /* union of Reply Descriptors */ 504 typedef union _MPI2_REPLY_DESCRIPTORS_UNION 505 { 506 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 507 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 508 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 509 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 510 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 511 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 512 U64 Words; 513 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 514 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 515 516 517 518 /***************************************************************************** 519 * 520 * Message Functions 521 * 522 *****************************************************************************/ 523 524 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 525 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 526 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 527 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 528 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 529 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 530 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 531 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 532 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 533 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 534 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 535 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 536 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 537 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 538 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 539 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 540 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 541 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 542 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 543 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 544 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 545 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 546 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 547 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 548 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 549 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 550 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 551 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 552 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 553 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 554 555 556 557 /* Doorbell functions */ 558 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 559 #define MPI2_FUNCTION_HANDSHAKE (0x42) 560 561 562 /***************************************************************************** 563 * 564 * IOC Status Values 565 * 566 *****************************************************************************/ 567 568 /* mask for IOCStatus status value */ 569 #define MPI2_IOCSTATUS_MASK (0x7FFF) 570 571 /**************************************************************************** 572 * Common IOCStatus values for all replies 573 ****************************************************************************/ 574 575 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 576 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 577 #define MPI2_IOCSTATUS_BUSY (0x0002) 578 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 579 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 580 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 581 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 582 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 583 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 584 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 585 586 /**************************************************************************** 587 * Config IOCStatus values 588 ****************************************************************************/ 589 590 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 591 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 592 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 593 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 594 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 595 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 596 597 /**************************************************************************** 598 * SCSI IO Reply 599 ****************************************************************************/ 600 601 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 602 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 603 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 604 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 605 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 606 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 607 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 608 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 609 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 610 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 611 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 612 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 613 614 /**************************************************************************** 615 * For use by SCSI Initiator and SCSI Target end-to-end data protection 616 ****************************************************************************/ 617 618 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 619 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 620 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 621 622 /**************************************************************************** 623 * SCSI Target values 624 ****************************************************************************/ 625 626 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 627 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 628 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 629 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 630 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 631 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 632 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 633 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 634 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 635 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 636 637 /**************************************************************************** 638 * Serial Attached SCSI values 639 ****************************************************************************/ 640 641 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 642 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 643 644 /**************************************************************************** 645 * Diagnostic Buffer Post / Diagnostic Release values 646 ****************************************************************************/ 647 648 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 649 650 /**************************************************************************** 651 * RAID Accelerator values 652 ****************************************************************************/ 653 654 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 655 656 /**************************************************************************** 657 * IOCStatus flag to indicate that log info is available 658 ****************************************************************************/ 659 660 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 661 662 /**************************************************************************** 663 * IOCLogInfo Types 664 ****************************************************************************/ 665 666 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 667 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 668 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 669 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 670 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 671 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 672 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 673 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 674 675 676 /***************************************************************************** 677 * 678 * Standard Message Structures 679 * 680 *****************************************************************************/ 681 682 /**************************************************************************** 683 * Request Message Header for all request messages 684 ****************************************************************************/ 685 686 typedef struct _MPI2_REQUEST_HEADER 687 { 688 U16 FunctionDependent1; /* 0x00 */ 689 U8 ChainOffset; /* 0x02 */ 690 U8 Function; /* 0x03 */ 691 U16 FunctionDependent2; /* 0x04 */ 692 U8 FunctionDependent3; /* 0x06 */ 693 U8 MsgFlags; /* 0x07 */ 694 U8 VP_ID; /* 0x08 */ 695 U8 VF_ID; /* 0x09 */ 696 U16 Reserved1; /* 0x0A */ 697 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 698 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 699 700 701 /**************************************************************************** 702 * Default Reply 703 ****************************************************************************/ 704 705 typedef struct _MPI2_DEFAULT_REPLY 706 { 707 U16 FunctionDependent1; /* 0x00 */ 708 U8 MsgLength; /* 0x02 */ 709 U8 Function; /* 0x03 */ 710 U16 FunctionDependent2; /* 0x04 */ 711 U8 FunctionDependent3; /* 0x06 */ 712 U8 MsgFlags; /* 0x07 */ 713 U8 VP_ID; /* 0x08 */ 714 U8 VF_ID; /* 0x09 */ 715 U16 Reserved1; /* 0x0A */ 716 U16 FunctionDependent5; /* 0x0C */ 717 U16 IOCStatus; /* 0x0E */ 718 U32 IOCLogInfo; /* 0x10 */ 719 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 720 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 721 722 723 /* common version structure/union used in messages and configuration pages */ 724 725 typedef struct _MPI2_VERSION_STRUCT 726 { 727 U8 Dev; /* 0x00 */ 728 U8 Unit; /* 0x01 */ 729 U8 Minor; /* 0x02 */ 730 U8 Major; /* 0x03 */ 731 } MPI2_VERSION_STRUCT; 732 733 typedef union _MPI2_VERSION_UNION 734 { 735 MPI2_VERSION_STRUCT Struct; 736 U32 Word; 737 } MPI2_VERSION_UNION; 738 739 740 /* LUN field defines, common to many structures */ 741 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 742 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 743 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 744 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 745 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 746 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 747 748 749 /***************************************************************************** 750 * 751 * Fusion-MPT MPI Scatter Gather Elements 752 * 753 *****************************************************************************/ 754 755 /**************************************************************************** 756 * MPI Simple Element structures 757 ****************************************************************************/ 758 759 typedef struct _MPI2_SGE_SIMPLE32 760 { 761 U32 FlagsLength; 762 U32 Address; 763 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 764 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 765 766 typedef struct _MPI2_SGE_SIMPLE64 767 { 768 U32 FlagsLength; 769 U64 Address; 770 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 771 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 772 773 typedef struct _MPI2_SGE_SIMPLE_UNION 774 { 775 U32 FlagsLength; 776 union 777 { 778 U32 Address32; 779 U64 Address64; 780 } u; 781 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 782 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 783 784 785 /**************************************************************************** 786 * MPI Chain Element structures 787 ****************************************************************************/ 788 789 typedef struct _MPI2_SGE_CHAIN32 790 { 791 U16 Length; 792 U8 NextChainOffset; 793 U8 Flags; 794 U32 Address; 795 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 796 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 797 798 typedef struct _MPI2_SGE_CHAIN64 799 { 800 U16 Length; 801 U8 NextChainOffset; 802 U8 Flags; 803 U64 Address; 804 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 805 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 806 807 typedef struct _MPI2_SGE_CHAIN_UNION 808 { 809 U16 Length; 810 U8 NextChainOffset; 811 U8 Flags; 812 union 813 { 814 U32 Address32; 815 U64 Address64; 816 } u; 817 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 818 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 819 820 821 /**************************************************************************** 822 * MPI Transaction Context Element structures 823 ****************************************************************************/ 824 825 typedef struct _MPI2_SGE_TRANSACTION32 826 { 827 U8 Reserved; 828 U8 ContextSize; 829 U8 DetailsLength; 830 U8 Flags; 831 U32 TransactionContext[1]; 832 U32 TransactionDetails[1]; 833 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 834 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 835 836 typedef struct _MPI2_SGE_TRANSACTION64 837 { 838 U8 Reserved; 839 U8 ContextSize; 840 U8 DetailsLength; 841 U8 Flags; 842 U32 TransactionContext[2]; 843 U32 TransactionDetails[1]; 844 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 845 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 846 847 typedef struct _MPI2_SGE_TRANSACTION96 848 { 849 U8 Reserved; 850 U8 ContextSize; 851 U8 DetailsLength; 852 U8 Flags; 853 U32 TransactionContext[3]; 854 U32 TransactionDetails[1]; 855 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 856 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 857 858 typedef struct _MPI2_SGE_TRANSACTION128 859 { 860 U8 Reserved; 861 U8 ContextSize; 862 U8 DetailsLength; 863 U8 Flags; 864 U32 TransactionContext[4]; 865 U32 TransactionDetails[1]; 866 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 867 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 868 869 typedef struct _MPI2_SGE_TRANSACTION_UNION 870 { 871 U8 Reserved; 872 U8 ContextSize; 873 U8 DetailsLength; 874 U8 Flags; 875 union 876 { 877 U32 TransactionContext32[1]; 878 U32 TransactionContext64[2]; 879 U32 TransactionContext96[3]; 880 U32 TransactionContext128[4]; 881 } u; 882 U32 TransactionDetails[1]; 883 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 884 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 885 886 887 /**************************************************************************** 888 * MPI SGE union for IO SGL's 889 ****************************************************************************/ 890 891 typedef struct _MPI2_MPI_SGE_IO_UNION 892 { 893 union 894 { 895 MPI2_SGE_SIMPLE_UNION Simple; 896 MPI2_SGE_CHAIN_UNION Chain; 897 } u; 898 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 899 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 900 901 902 /**************************************************************************** 903 * MPI SGE union for SGL's with Simple and Transaction elements 904 ****************************************************************************/ 905 906 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 907 { 908 union 909 { 910 MPI2_SGE_SIMPLE_UNION Simple; 911 MPI2_SGE_TRANSACTION_UNION Transaction; 912 } u; 913 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 914 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 915 916 917 /**************************************************************************** 918 * All MPI SGE types union 919 ****************************************************************************/ 920 921 typedef struct _MPI2_MPI_SGE_UNION 922 { 923 union 924 { 925 MPI2_SGE_SIMPLE_UNION Simple; 926 MPI2_SGE_CHAIN_UNION Chain; 927 MPI2_SGE_TRANSACTION_UNION Transaction; 928 } u; 929 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 930 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 931 932 933 /**************************************************************************** 934 * MPI SGE field definition and masks 935 ****************************************************************************/ 936 937 /* Flags field bit definitions */ 938 939 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 940 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 941 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 942 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 943 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 944 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 945 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 946 947 #define MPI2_SGE_FLAGS_SHIFT (24) 948 949 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 950 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 951 952 /* Element Type */ 953 954 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 955 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 956 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 957 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 958 959 /* Address location */ 960 961 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 962 963 /* Direction */ 964 965 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 966 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 967 968 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 969 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 970 971 /* Address Size */ 972 973 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 974 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 975 976 /* Context Size */ 977 978 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 979 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 980 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 981 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 982 983 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 984 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 985 986 /**************************************************************************** 987 * MPI SGE operation Macros 988 ****************************************************************************/ 989 990 /* SIMPLE FlagsLength manipulations... */ 991 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 992 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 993 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 994 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 995 996 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 997 998 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 999 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 1000 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 1001 1002 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1003 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 1004 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 1005 1006 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 1007 1008 1009 /***************************************************************************** 1010 * 1011 * Fusion-MPT IEEE Scatter Gather Elements 1012 * 1013 *****************************************************************************/ 1014 1015 /**************************************************************************** 1016 * IEEE Simple Element structures 1017 ****************************************************************************/ 1018 1019 typedef struct _MPI2_IEEE_SGE_SIMPLE32 1020 { 1021 U32 Address; 1022 U32 FlagsLength; 1023 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 1024 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 1025 1026 typedef struct _MPI2_IEEE_SGE_SIMPLE64 1027 { 1028 U64 Address; 1029 U32 Length; 1030 U16 Reserved1; 1031 U8 Reserved2; 1032 U8 Flags; 1033 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 1034 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 1035 1036 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 1037 { 1038 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1039 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1040 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1041 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1042 1043 1044 /**************************************************************************** 1045 * IEEE Chain Element structures 1046 ****************************************************************************/ 1047 1048 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1049 1050 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1051 1052 typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1053 { 1054 MPI2_IEEE_SGE_CHAIN32 Chain32; 1055 MPI2_IEEE_SGE_CHAIN64 Chain64; 1056 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1057 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1058 1059 1060 /**************************************************************************** 1061 * All IEEE SGE types union 1062 ****************************************************************************/ 1063 1064 typedef struct _MPI2_IEEE_SGE_UNION 1065 { 1066 union 1067 { 1068 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1069 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1070 } u; 1071 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1072 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1073 1074 1075 /**************************************************************************** 1076 * IEEE SGE field definitions and masks 1077 ****************************************************************************/ 1078 1079 /* Flags field bit definitions */ 1080 1081 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1082 1083 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1084 1085 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1086 1087 /* Element Type */ 1088 1089 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1090 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1091 1092 /* Data Location Address Space */ 1093 1094 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1095 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* IEEE Simple Element only */ 1096 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* IEEE Simple Element only */ 1097 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1098 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* IEEE Simple Element only */ 1099 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (0x03) /* IEEE Chain Element only */ 1100 1101 /**************************************************************************** 1102 * IEEE SGE operation Macros 1103 ****************************************************************************/ 1104 1105 /* SIMPLE FlagsLength manipulations... */ 1106 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1107 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1108 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1109 1110 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1111 1112 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1113 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1114 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1115 1116 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1117 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1118 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1119 1120 1121 1122 1123 /***************************************************************************** 1124 * 1125 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1126 * 1127 *****************************************************************************/ 1128 1129 typedef union _MPI2_SIMPLE_SGE_UNION 1130 { 1131 MPI2_SGE_SIMPLE_UNION MpiSimple; 1132 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1133 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1134 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1135 1136 1137 typedef union _MPI2_SGE_IO_UNION 1138 { 1139 MPI2_SGE_SIMPLE_UNION MpiSimple; 1140 MPI2_SGE_CHAIN_UNION MpiChain; 1141 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1142 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1143 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1144 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1145 1146 1147 /**************************************************************************** 1148 * 1149 * Values for SGLFlags field, used in many request messages with an SGL 1150 * 1151 ****************************************************************************/ 1152 1153 /* values for MPI SGL Data Location Address Space subfield */ 1154 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1155 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1156 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1157 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1158 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1159 /* values for SGL Type subfield */ 1160 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1161 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1162 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1163 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1164 1165 1166 #endif 1167 1168