1 /*- 2 * Copyright (c) 2009 Yahoo! Inc. 3 * Copyright (c) 2011-2015 LSI Corp. 4 * Copyright (c) 2013-2016 Avago Technologies 5 * Copyright 2000-2020 Broadcom Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 /* Communications core for Avago Technologies (LSI) MPT3 */ 35 36 /* TODO Move headers to mprvar */ 37 #include <sys/types.h> 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/selinfo.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #include <sys/bus.h> 46 #include <sys/conf.h> 47 #include <sys/bio.h> 48 #include <sys/malloc.h> 49 #include <sys/uio.h> 50 #include <sys/sysctl.h> 51 #include <sys/smp.h> 52 #include <sys/queue.h> 53 #include <sys/kthread.h> 54 #include <sys/taskqueue.h> 55 #include <sys/endian.h> 56 #include <sys/eventhandler.h> 57 #include <sys/sbuf.h> 58 #include <sys/priv.h> 59 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/rman.h> 63 #include <sys/proc.h> 64 65 #include <dev/pci/pcivar.h> 66 67 #include <cam/cam.h> 68 #include <cam/cam_ccb.h> 69 #include <cam/scsi/scsi_all.h> 70 71 #include <dev/mpr/mpi/mpi2_type.h> 72 #include <dev/mpr/mpi/mpi2.h> 73 #include <dev/mpr/mpi/mpi2_ioc.h> 74 #include <dev/mpr/mpi/mpi2_sas.h> 75 #include <dev/mpr/mpi/mpi2_pci.h> 76 #include <dev/mpr/mpi/mpi2_cnfg.h> 77 #include <dev/mpr/mpi/mpi2_init.h> 78 #include <dev/mpr/mpi/mpi2_tool.h> 79 #include <dev/mpr/mpr_ioctl.h> 80 #include <dev/mpr/mprvar.h> 81 #include <dev/mpr/mpr_table.h> 82 #include <dev/mpr/mpr_sas.h> 83 84 static int mpr_diag_reset(struct mpr_softc *sc, int sleep_flag); 85 static int mpr_init_queues(struct mpr_softc *sc); 86 static void mpr_resize_queues(struct mpr_softc *sc); 87 static int mpr_message_unit_reset(struct mpr_softc *sc, int sleep_flag); 88 static int mpr_transition_operational(struct mpr_softc *sc); 89 static int mpr_iocfacts_allocate(struct mpr_softc *sc, uint8_t attaching); 90 static void mpr_iocfacts_free(struct mpr_softc *sc); 91 static void mpr_startup(void *arg); 92 static int mpr_send_iocinit(struct mpr_softc *sc); 93 static int mpr_alloc_queues(struct mpr_softc *sc); 94 static int mpr_alloc_hw_queues(struct mpr_softc *sc); 95 static int mpr_alloc_replies(struct mpr_softc *sc); 96 static int mpr_alloc_requests(struct mpr_softc *sc); 97 static int mpr_alloc_nvme_prp_pages(struct mpr_softc *sc); 98 static int mpr_attach_log(struct mpr_softc *sc); 99 static __inline void mpr_complete_command(struct mpr_softc *sc, 100 struct mpr_command *cm); 101 static void mpr_dispatch_event(struct mpr_softc *sc, uintptr_t data, 102 MPI2_EVENT_NOTIFICATION_REPLY *reply); 103 static void mpr_config_complete(struct mpr_softc *sc, struct mpr_command *cm); 104 static void mpr_periodic(void *); 105 static int mpr_reregister_events(struct mpr_softc *sc); 106 static void mpr_enqueue_request(struct mpr_softc *sc, struct mpr_command *cm); 107 static int mpr_get_iocfacts(struct mpr_softc *sc, MPI2_IOC_FACTS_REPLY *facts); 108 static int mpr_wait_db_ack(struct mpr_softc *sc, int timeout, int sleep_flag); 109 static int mpr_debug_sysctl(SYSCTL_HANDLER_ARGS); 110 static int mpr_dump_reqs(SYSCTL_HANDLER_ARGS); 111 static void mpr_parse_debug(struct mpr_softc *sc, char *list); 112 static void adjust_iocfacts_endianness(MPI2_IOC_FACTS_REPLY *facts); 113 114 SYSCTL_NODE(_hw, OID_AUTO, mpr, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 115 "MPR Driver Parameters"); 116 117 MALLOC_DEFINE(M_MPR, "mpr", "mpr driver memory"); 118 119 /* 120 * Do a "Diagnostic Reset" aka a hard reset. This should get the chip out of 121 * any state and back to its initialization state machine. 122 */ 123 static char mpt2_reset_magic[] = { 0x00, 0x0f, 0x04, 0x0b, 0x02, 0x07, 0x0d }; 124 125 /* 126 * Added this union to smoothly convert le64toh cm->cm_desc.Words. 127 * Compiler only supports uint64_t to be passed as an argument. 128 * Otherwise it will throw this error: 129 * "aggregate value used where an integer was expected" 130 */ 131 typedef union { 132 u64 word; 133 struct { 134 u32 low; 135 u32 high; 136 } u; 137 } request_descriptor_t; 138 139 /* Rate limit chain-fail messages to 1 per minute */ 140 static struct timeval mpr_chainfail_interval = { 60, 0 }; 141 142 /* 143 * sleep_flag can be either CAN_SLEEP or NO_SLEEP. 144 * If this function is called from process context, it can sleep 145 * and there is no harm to sleep, in case if this fuction is called 146 * from Interrupt handler, we can not sleep and need NO_SLEEP flag set. 147 * based on sleep flags driver will call either msleep, pause or DELAY. 148 * msleep and pause are of same variant, but pause is used when mpr_mtx 149 * is not hold by driver. 150 */ 151 static int 152 mpr_diag_reset(struct mpr_softc *sc,int sleep_flag) 153 { 154 uint32_t reg; 155 int i, error, tries = 0; 156 uint8_t first_wait_done = FALSE; 157 158 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 159 160 /* Clear any pending interrupts */ 161 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 162 163 /* 164 * Force NO_SLEEP for threads prohibited to sleep 165 * e.a Thread from interrupt handler are prohibited to sleep. 166 */ 167 if (curthread->td_no_sleeping) 168 sleep_flag = NO_SLEEP; 169 170 mpr_dprint(sc, MPR_INIT, "sequence start, sleep_flag=%d\n", sleep_flag); 171 /* Push the magic sequence */ 172 error = ETIMEDOUT; 173 while (tries++ < 20) { 174 for (i = 0; i < sizeof(mpt2_reset_magic); i++) 175 mpr_regwrite(sc, MPI2_WRITE_SEQUENCE_OFFSET, 176 mpt2_reset_magic[i]); 177 178 /* wait 100 msec */ 179 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) 180 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, 181 "mprdiag", hz/10); 182 else if (sleep_flag == CAN_SLEEP) 183 pause("mprdiag", hz/10); 184 else 185 DELAY(100 * 1000); 186 187 reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET); 188 if (reg & MPI2_DIAG_DIAG_WRITE_ENABLE) { 189 error = 0; 190 break; 191 } 192 } 193 if (error) { 194 mpr_dprint(sc, MPR_INIT, "sequence failed, error=%d, exit\n", 195 error); 196 return (error); 197 } 198 199 /* Send the actual reset. XXX need to refresh the reg? */ 200 reg |= MPI2_DIAG_RESET_ADAPTER; 201 mpr_dprint(sc, MPR_INIT, "sequence success, sending reset, reg= 0x%x\n", 202 reg); 203 mpr_regwrite(sc, MPI2_HOST_DIAGNOSTIC_OFFSET, reg); 204 205 /* Wait up to 300 seconds in 50ms intervals */ 206 error = ETIMEDOUT; 207 for (i = 0; i < 6000; i++) { 208 /* 209 * Wait 50 msec. If this is the first time through, wait 256 210 * msec to satisfy Diag Reset timing requirements. 211 */ 212 if (first_wait_done) { 213 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) 214 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, 215 "mprdiag", hz/20); 216 else if (sleep_flag == CAN_SLEEP) 217 pause("mprdiag", hz/20); 218 else 219 DELAY(50 * 1000); 220 } else { 221 DELAY(256 * 1000); 222 first_wait_done = TRUE; 223 } 224 /* 225 * Check for the RESET_ADAPTER bit to be cleared first, then 226 * wait for the RESET state to be cleared, which takes a little 227 * longer. 228 */ 229 reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET); 230 if (reg & MPI2_DIAG_RESET_ADAPTER) { 231 continue; 232 } 233 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 234 if ((reg & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_RESET) { 235 error = 0; 236 break; 237 } 238 } 239 if (error) { 240 mpr_dprint(sc, MPR_INIT, "reset failed, error= %d, exit\n", 241 error); 242 return (error); 243 } 244 245 mpr_regwrite(sc, MPI2_WRITE_SEQUENCE_OFFSET, 0x0); 246 mpr_dprint(sc, MPR_INIT, "diag reset success, exit\n"); 247 248 return (0); 249 } 250 251 static int 252 mpr_message_unit_reset(struct mpr_softc *sc, int sleep_flag) 253 { 254 int error; 255 256 MPR_FUNCTRACE(sc); 257 258 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 259 260 error = 0; 261 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET, 262 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET << 263 MPI2_DOORBELL_FUNCTION_SHIFT); 264 265 if (mpr_wait_db_ack(sc, 5, sleep_flag) != 0) { 266 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 267 "Doorbell handshake failed\n"); 268 error = ETIMEDOUT; 269 } 270 271 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 272 return (error); 273 } 274 275 static int 276 mpr_transition_ready(struct mpr_softc *sc) 277 { 278 uint32_t reg, state; 279 int error, tries = 0; 280 int sleep_flags; 281 282 MPR_FUNCTRACE(sc); 283 /* If we are in attach call, do not sleep */ 284 sleep_flags = (sc->mpr_flags & MPR_FLAGS_ATTACH_DONE) 285 ? CAN_SLEEP : NO_SLEEP; 286 287 error = 0; 288 289 mpr_dprint(sc, MPR_INIT, "%s entered, sleep_flags= %d\n", 290 __func__, sleep_flags); 291 292 while (tries++ < 1200) { 293 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 294 mpr_dprint(sc, MPR_INIT, " Doorbell= 0x%x\n", reg); 295 296 /* 297 * Ensure the IOC is ready to talk. If it's not, try 298 * resetting it. 299 */ 300 if (reg & MPI2_DOORBELL_USED) { 301 mpr_dprint(sc, MPR_INIT, " Not ready, sending diag " 302 "reset\n"); 303 mpr_diag_reset(sc, sleep_flags); 304 DELAY(50000); 305 continue; 306 } 307 308 /* Is the adapter owned by another peer? */ 309 if ((reg & MPI2_DOORBELL_WHO_INIT_MASK) == 310 (MPI2_WHOINIT_PCI_PEER << MPI2_DOORBELL_WHO_INIT_SHIFT)) { 311 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC is under the " 312 "control of another peer host, aborting " 313 "initialization.\n"); 314 error = ENXIO; 315 break; 316 } 317 318 state = reg & MPI2_IOC_STATE_MASK; 319 if (state == MPI2_IOC_STATE_READY) { 320 /* Ready to go! */ 321 error = 0; 322 break; 323 } else if (state == MPI2_IOC_STATE_FAULT) { 324 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC in fault " 325 "state 0x%x, resetting\n", 326 state & MPI2_DOORBELL_FAULT_CODE_MASK); 327 mpr_diag_reset(sc, sleep_flags); 328 } else if (state == MPI2_IOC_STATE_OPERATIONAL) { 329 /* Need to take ownership */ 330 mpr_message_unit_reset(sc, sleep_flags); 331 } else if (state == MPI2_IOC_STATE_RESET) { 332 /* Wait a bit, IOC might be in transition */ 333 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 334 "IOC in unexpected reset state\n"); 335 } else { 336 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 337 "IOC in unknown state 0x%x\n", state); 338 error = EINVAL; 339 break; 340 } 341 342 /* Wait 50ms for things to settle down. */ 343 DELAY(50000); 344 } 345 346 if (error) 347 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 348 "Cannot transition IOC to ready\n"); 349 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 350 return (error); 351 } 352 353 static int 354 mpr_transition_operational(struct mpr_softc *sc) 355 { 356 uint32_t reg, state; 357 int error; 358 359 MPR_FUNCTRACE(sc); 360 361 error = 0; 362 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 363 mpr_dprint(sc, MPR_INIT, "%s entered, Doorbell= 0x%x\n", __func__, reg); 364 365 state = reg & MPI2_IOC_STATE_MASK; 366 if (state != MPI2_IOC_STATE_READY) { 367 mpr_dprint(sc, MPR_INIT, "IOC not ready\n"); 368 if ((error = mpr_transition_ready(sc)) != 0) { 369 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 370 "failed to transition ready, exit\n"); 371 return (error); 372 } 373 } 374 375 error = mpr_send_iocinit(sc); 376 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 377 378 return (error); 379 } 380 381 static void 382 mpr_resize_queues(struct mpr_softc *sc) 383 { 384 u_int reqcr, prireqcr, maxio, sges_per_frame, chain_seg_size; 385 386 /* 387 * Size the queues. Since the reply queues always need one free 388 * entry, we'll deduct one reply message here. The LSI documents 389 * suggest instead to add a count to the request queue, but I think 390 * that it's better to deduct from reply queue. 391 */ 392 prireqcr = MAX(1, sc->max_prireqframes); 393 prireqcr = MIN(prireqcr, sc->facts->HighPriorityCredit); 394 395 reqcr = MAX(2, sc->max_reqframes); 396 reqcr = MIN(reqcr, sc->facts->RequestCredit); 397 398 sc->num_reqs = prireqcr + reqcr; 399 sc->num_prireqs = prireqcr; 400 sc->num_replies = MIN(sc->max_replyframes + sc->max_evtframes, 401 sc->facts->MaxReplyDescriptorPostQueueDepth) - 1; 402 403 /* Store the request frame size in bytes rather than as 32bit words */ 404 sc->reqframesz = sc->facts->IOCRequestFrameSize * 4; 405 406 /* 407 * Gen3 and beyond uses the IOCMaxChainSegmentSize from IOC Facts to 408 * get the size of a Chain Frame. Previous versions use the size as a 409 * Request Frame for the Chain Frame size. If IOCMaxChainSegmentSize 410 * is 0, use the default value. The IOCMaxChainSegmentSize is the 411 * number of 16-byte elelements that can fit in a Chain Frame, which is 412 * the size of an IEEE Simple SGE. 413 */ 414 if (sc->facts->MsgVersion >= MPI2_VERSION_02_05) { 415 chain_seg_size = sc->facts->IOCMaxChainSegmentSize; 416 if (chain_seg_size == 0) 417 chain_seg_size = MPR_DEFAULT_CHAIN_SEG_SIZE; 418 sc->chain_frame_size = chain_seg_size * 419 MPR_MAX_CHAIN_ELEMENT_SIZE; 420 } else { 421 sc->chain_frame_size = sc->reqframesz; 422 } 423 424 /* 425 * Max IO Size is Page Size * the following: 426 * ((SGEs per frame - 1 for chain element) * Max Chain Depth) 427 * + 1 for no chain needed in last frame 428 * 429 * If user suggests a Max IO size to use, use the smaller of the 430 * user's value and the calculated value as long as the user's 431 * value is larger than 0. The user's value is in pages. 432 */ 433 sges_per_frame = sc->chain_frame_size/sizeof(MPI2_IEEE_SGE_SIMPLE64)-1; 434 maxio = (sges_per_frame * sc->facts->MaxChainDepth + 1) * PAGE_SIZE; 435 436 /* 437 * If I/O size limitation requested then use it and pass up to CAM. 438 * If not, use maxphys as an optimization hint, but report HW limit. 439 */ 440 if (sc->max_io_pages > 0) { 441 maxio = min(maxio, sc->max_io_pages * PAGE_SIZE); 442 sc->maxio = maxio; 443 } else { 444 sc->maxio = maxio; 445 maxio = min(maxio, maxphys); 446 } 447 448 sc->num_chains = (maxio / PAGE_SIZE + sges_per_frame - 2) / 449 sges_per_frame * reqcr; 450 if (sc->max_chains > 0 && sc->max_chains < sc->num_chains) 451 sc->num_chains = sc->max_chains; 452 453 /* 454 * Figure out the number of MSIx-based queues. If the firmware or 455 * user has done something crazy and not allowed enough credit for 456 * the queues to be useful then don't enable multi-queue. 457 */ 458 if (sc->facts->MaxMSIxVectors < 2) 459 sc->msi_msgs = 1; 460 461 if (sc->msi_msgs > 1) { 462 sc->msi_msgs = MIN(sc->msi_msgs, mp_ncpus); 463 sc->msi_msgs = MIN(sc->msi_msgs, sc->facts->MaxMSIxVectors); 464 if (sc->num_reqs / sc->msi_msgs < 2) 465 sc->msi_msgs = 1; 466 } 467 468 mpr_dprint(sc, MPR_INIT, "Sized queues to q=%d reqs=%d replies=%d\n", 469 sc->msi_msgs, sc->num_reqs, sc->num_replies); 470 } 471 472 /* 473 * This is called during attach and when re-initializing due to a Diag Reset. 474 * IOC Facts is used to allocate many of the structures needed by the driver. 475 * If called from attach, de-allocation is not required because the driver has 476 * not allocated any structures yet, but if called from a Diag Reset, previously 477 * allocated structures based on IOC Facts will need to be freed and re- 478 * allocated bases on the latest IOC Facts. 479 */ 480 static int 481 mpr_iocfacts_allocate(struct mpr_softc *sc, uint8_t attaching) 482 { 483 int error; 484 Mpi2IOCFactsReply_t saved_facts; 485 uint8_t saved_mode, reallocating; 486 487 mpr_dprint(sc, MPR_INIT|MPR_TRACE, "%s entered\n", __func__); 488 489 /* Save old IOC Facts and then only reallocate if Facts have changed */ 490 if (!attaching) { 491 bcopy(sc->facts, &saved_facts, sizeof(MPI2_IOC_FACTS_REPLY)); 492 } 493 494 /* 495 * Get IOC Facts. In all cases throughout this function, panic if doing 496 * a re-initialization and only return the error if attaching so the OS 497 * can handle it. 498 */ 499 if ((error = mpr_get_iocfacts(sc, sc->facts)) != 0) { 500 if (attaching) { 501 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to get " 502 "IOC Facts with error %d, exit\n", error); 503 return (error); 504 } else { 505 panic("%s failed to get IOC Facts with error %d\n", 506 __func__, error); 507 } 508 } 509 510 MPR_DPRINT_PAGE(sc, MPR_XINFO, iocfacts, sc->facts); 511 512 snprintf(sc->fw_version, sizeof(sc->fw_version), 513 "%02d.%02d.%02d.%02d", 514 sc->facts->FWVersion.Struct.Major, 515 sc->facts->FWVersion.Struct.Minor, 516 sc->facts->FWVersion.Struct.Unit, 517 sc->facts->FWVersion.Struct.Dev); 518 519 snprintf(sc->msg_version, sizeof(sc->msg_version), "%d.%d", 520 (sc->facts->MsgVersion & MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK) >> 521 MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT, 522 (sc->facts->MsgVersion & MPI2_IOCFACTS_MSGVERSION_MINOR_MASK) >> 523 MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT); 524 525 mpr_dprint(sc, MPR_INFO, "Firmware: %s, Driver: %s\n", sc->fw_version, 526 MPR_DRIVER_VERSION); 527 mpr_dprint(sc, MPR_INFO, 528 "IOCCapabilities: %b\n", sc->facts->IOCCapabilities, 529 "\20" "\3ScsiTaskFull" "\4DiagTrace" "\5SnapBuf" "\6ExtBuf" 530 "\7EEDP" "\10BiDirTarg" "\11Multicast" "\14TransRetry" "\15IR" 531 "\16EventReplay" "\17RaidAccel" "\20MSIXIndex" "\21HostDisc" 532 "\22FastPath" "\23RDPQArray" "\24AtomicReqDesc" "\25PCIeSRIOV"); 533 534 /* 535 * If the chip doesn't support event replay then a hard reset will be 536 * required to trigger a full discovery. Do the reset here then 537 * retransition to Ready. A hard reset might have already been done, 538 * but it doesn't hurt to do it again. Only do this if attaching, not 539 * for a Diag Reset. 540 */ 541 if (attaching && ((sc->facts->IOCCapabilities & 542 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY) == 0)) { 543 mpr_dprint(sc, MPR_INIT, "No event replay, resetting\n"); 544 mpr_diag_reset(sc, NO_SLEEP); 545 if ((error = mpr_transition_ready(sc)) != 0) { 546 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to " 547 "transition to ready with error %d, exit\n", 548 error); 549 return (error); 550 } 551 } 552 553 /* 554 * Set flag if IR Firmware is loaded. If the RAID Capability has 555 * changed from the previous IOC Facts, log a warning, but only if 556 * checking this after a Diag Reset and not during attach. 557 */ 558 saved_mode = sc->ir_firmware; 559 if (sc->facts->IOCCapabilities & 560 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) 561 sc->ir_firmware = 1; 562 if (!attaching) { 563 if (sc->ir_firmware != saved_mode) { 564 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "new IR/IT mode " 565 "in IOC Facts does not match previous mode\n"); 566 } 567 } 568 569 /* Only deallocate and reallocate if relevant IOC Facts have changed */ 570 reallocating = FALSE; 571 sc->mpr_flags &= ~MPR_FLAGS_REALLOCATED; 572 573 if ((!attaching) && 574 ((saved_facts.MsgVersion != sc->facts->MsgVersion) || 575 (saved_facts.HeaderVersion != sc->facts->HeaderVersion) || 576 (saved_facts.MaxChainDepth != sc->facts->MaxChainDepth) || 577 (saved_facts.RequestCredit != sc->facts->RequestCredit) || 578 (saved_facts.ProductID != sc->facts->ProductID) || 579 (saved_facts.IOCCapabilities != sc->facts->IOCCapabilities) || 580 (saved_facts.IOCRequestFrameSize != 581 sc->facts->IOCRequestFrameSize) || 582 (saved_facts.IOCMaxChainSegmentSize != 583 sc->facts->IOCMaxChainSegmentSize) || 584 (saved_facts.MaxTargets != sc->facts->MaxTargets) || 585 (saved_facts.MaxSasExpanders != sc->facts->MaxSasExpanders) || 586 (saved_facts.MaxEnclosures != sc->facts->MaxEnclosures) || 587 (saved_facts.HighPriorityCredit != sc->facts->HighPriorityCredit) || 588 (saved_facts.MaxReplyDescriptorPostQueueDepth != 589 sc->facts->MaxReplyDescriptorPostQueueDepth) || 590 (saved_facts.ReplyFrameSize != sc->facts->ReplyFrameSize) || 591 (saved_facts.MaxVolumes != sc->facts->MaxVolumes) || 592 (saved_facts.MaxPersistentEntries != 593 sc->facts->MaxPersistentEntries))) { 594 reallocating = TRUE; 595 596 /* Record that we reallocated everything */ 597 sc->mpr_flags |= MPR_FLAGS_REALLOCATED; 598 } 599 600 /* 601 * Some things should be done if attaching or re-allocating after a Diag 602 * Reset, but are not needed after a Diag Reset if the FW has not 603 * changed. 604 */ 605 if (attaching || reallocating) { 606 /* 607 * Check if controller supports FW diag buffers and set flag to 608 * enable each type. 609 */ 610 if (sc->facts->IOCCapabilities & 611 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) 612 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_TRACE]. 613 enabled = TRUE; 614 if (sc->facts->IOCCapabilities & 615 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) 616 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_SNAPSHOT]. 617 enabled = TRUE; 618 if (sc->facts->IOCCapabilities & 619 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) 620 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_EXTENDED]. 621 enabled = TRUE; 622 623 /* 624 * Set flags for some supported items. 625 */ 626 if (sc->facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) 627 sc->eedp_enabled = TRUE; 628 if (sc->facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) 629 sc->control_TLR = TRUE; 630 if ((sc->facts->IOCCapabilities & 631 MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ) && 632 (sc->mpr_flags & MPR_FLAGS_SEA_IOC)) 633 sc->atomic_desc_capable = TRUE; 634 635 mpr_resize_queues(sc); 636 637 /* 638 * Initialize all Tail Queues 639 */ 640 TAILQ_INIT(&sc->req_list); 641 TAILQ_INIT(&sc->high_priority_req_list); 642 TAILQ_INIT(&sc->chain_list); 643 TAILQ_INIT(&sc->prp_page_list); 644 TAILQ_INIT(&sc->tm_list); 645 } 646 647 /* 648 * If doing a Diag Reset and the FW is significantly different 649 * (reallocating will be set above in IOC Facts comparison), then all 650 * buffers based on the IOC Facts will need to be freed before they are 651 * reallocated. 652 */ 653 if (reallocating) { 654 mpr_iocfacts_free(sc); 655 mprsas_realloc_targets(sc, saved_facts.MaxTargets + 656 saved_facts.MaxVolumes); 657 } 658 659 /* 660 * Any deallocation has been completed. Now start reallocating 661 * if needed. Will only need to reallocate if attaching or if the new 662 * IOC Facts are different from the previous IOC Facts after a Diag 663 * Reset. Targets have already been allocated above if needed. 664 */ 665 error = 0; 666 while (attaching || reallocating) { 667 if ((error = mpr_alloc_hw_queues(sc)) != 0) 668 break; 669 if ((error = mpr_alloc_replies(sc)) != 0) 670 break; 671 if ((error = mpr_alloc_requests(sc)) != 0) 672 break; 673 if ((error = mpr_alloc_queues(sc)) != 0) 674 break; 675 break; 676 } 677 if (error) { 678 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 679 "Failed to alloc queues with error %d\n", error); 680 mpr_free(sc); 681 return (error); 682 } 683 684 /* Always initialize the queues */ 685 bzero(sc->free_queue, sc->fqdepth * 4); 686 mpr_init_queues(sc); 687 688 /* 689 * Always get the chip out of the reset state, but only panic if not 690 * attaching. If attaching and there is an error, that is handled by 691 * the OS. 692 */ 693 error = mpr_transition_operational(sc); 694 if (error != 0) { 695 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to " 696 "transition to operational with error %d\n", error); 697 mpr_free(sc); 698 return (error); 699 } 700 701 /* 702 * Finish the queue initialization. 703 * These are set here instead of in mpr_init_queues() because the 704 * IOC resets these values during the state transition in 705 * mpr_transition_operational(). The free index is set to 1 706 * because the corresponding index in the IOC is set to 0, and the 707 * IOC treats the queues as full if both are set to the same value. 708 * Hence the reason that the queue can't hold all of the possible 709 * replies. 710 */ 711 sc->replypostindex = 0; 712 mpr_regwrite(sc, MPI2_REPLY_FREE_HOST_INDEX_OFFSET, sc->replyfreeindex); 713 mpr_regwrite(sc, MPI2_REPLY_POST_HOST_INDEX_OFFSET, 0); 714 715 /* 716 * Attach the subsystems so they can prepare their event masks. 717 * XXX Should be dynamic so that IM/IR and user modules can attach 718 */ 719 error = 0; 720 while (attaching) { 721 mpr_dprint(sc, MPR_INIT, "Attaching subsystems\n"); 722 if ((error = mpr_attach_log(sc)) != 0) 723 break; 724 if ((error = mpr_attach_sas(sc)) != 0) 725 break; 726 if ((error = mpr_attach_user(sc)) != 0) 727 break; 728 break; 729 } 730 if (error) { 731 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 732 "Failed to attach all subsystems: error %d\n", error); 733 mpr_free(sc); 734 return (error); 735 } 736 737 /* 738 * XXX If the number of MSI-X vectors changes during re-init, this 739 * won't see it and adjust. 740 */ 741 if ((attaching || reallocating) && (error = mpr_pci_setup_interrupts(sc)) != 0) { 742 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 743 "Failed to setup interrupts\n"); 744 mpr_free(sc); 745 return (error); 746 } 747 748 return (error); 749 } 750 751 /* 752 * This is called if memory is being free (during detach for example) and when 753 * buffers need to be reallocated due to a Diag Reset. 754 */ 755 static void 756 mpr_iocfacts_free(struct mpr_softc *sc) 757 { 758 struct mpr_command *cm; 759 int i; 760 761 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 762 763 if (sc->free_busaddr != 0) 764 bus_dmamap_unload(sc->queues_dmat, sc->queues_map); 765 if (sc->free_queue != NULL) 766 bus_dmamem_free(sc->queues_dmat, sc->free_queue, 767 sc->queues_map); 768 if (sc->queues_dmat != NULL) 769 bus_dma_tag_destroy(sc->queues_dmat); 770 771 if (sc->chain_frames != NULL) { 772 bus_dmamap_unload(sc->chain_dmat, sc->chain_map); 773 bus_dmamem_free(sc->chain_dmat, sc->chain_frames, 774 sc->chain_map); 775 } 776 if (sc->chain_dmat != NULL) 777 bus_dma_tag_destroy(sc->chain_dmat); 778 779 if (sc->sense_busaddr != 0) 780 bus_dmamap_unload(sc->sense_dmat, sc->sense_map); 781 if (sc->sense_frames != NULL) 782 bus_dmamem_free(sc->sense_dmat, sc->sense_frames, 783 sc->sense_map); 784 if (sc->sense_dmat != NULL) 785 bus_dma_tag_destroy(sc->sense_dmat); 786 787 if (sc->prp_page_busaddr != 0) 788 bus_dmamap_unload(sc->prp_page_dmat, sc->prp_page_map); 789 if (sc->prp_pages != NULL) 790 bus_dmamem_free(sc->prp_page_dmat, sc->prp_pages, 791 sc->prp_page_map); 792 if (sc->prp_page_dmat != NULL) 793 bus_dma_tag_destroy(sc->prp_page_dmat); 794 795 if (sc->reply_busaddr != 0) 796 bus_dmamap_unload(sc->reply_dmat, sc->reply_map); 797 if (sc->reply_frames != NULL) 798 bus_dmamem_free(sc->reply_dmat, sc->reply_frames, 799 sc->reply_map); 800 if (sc->reply_dmat != NULL) 801 bus_dma_tag_destroy(sc->reply_dmat); 802 803 if (sc->req_busaddr != 0) 804 bus_dmamap_unload(sc->req_dmat, sc->req_map); 805 if (sc->req_frames != NULL) 806 bus_dmamem_free(sc->req_dmat, sc->req_frames, sc->req_map); 807 if (sc->req_dmat != NULL) 808 bus_dma_tag_destroy(sc->req_dmat); 809 810 if (sc->chains != NULL) 811 free(sc->chains, M_MPR); 812 if (sc->prps != NULL) 813 free(sc->prps, M_MPR); 814 if (sc->commands != NULL) { 815 for (i = 1; i < sc->num_reqs; i++) { 816 cm = &sc->commands[i]; 817 bus_dmamap_destroy(sc->buffer_dmat, cm->cm_dmamap); 818 } 819 free(sc->commands, M_MPR); 820 } 821 if (sc->buffer_dmat != NULL) 822 bus_dma_tag_destroy(sc->buffer_dmat); 823 824 mpr_pci_free_interrupts(sc); 825 free(sc->queues, M_MPR); 826 sc->queues = NULL; 827 } 828 829 /* 830 * The terms diag reset and hard reset are used interchangeably in the MPI 831 * docs to mean resetting the controller chip. In this code diag reset 832 * cleans everything up, and the hard reset function just sends the reset 833 * sequence to the chip. This should probably be refactored so that every 834 * subsystem gets a reset notification of some sort, and can clean up 835 * appropriately. 836 */ 837 int 838 mpr_reinit(struct mpr_softc *sc) 839 { 840 int error; 841 struct mprsas_softc *sassc; 842 843 sassc = sc->sassc; 844 845 MPR_FUNCTRACE(sc); 846 847 mtx_assert(&sc->mpr_mtx, MA_OWNED); 848 849 mpr_dprint(sc, MPR_INIT|MPR_INFO, "Reinitializing controller\n"); 850 if (sc->mpr_flags & MPR_FLAGS_DIAGRESET) { 851 mpr_dprint(sc, MPR_INIT, "Reset already in progress\n"); 852 return 0; 853 } 854 855 /* 856 * Make sure the completion callbacks can recognize they're getting 857 * a NULL cm_reply due to a reset. 858 */ 859 sc->mpr_flags |= MPR_FLAGS_DIAGRESET; 860 861 /* 862 * Mask interrupts here. 863 */ 864 mpr_dprint(sc, MPR_INIT, "Masking interrupts and resetting\n"); 865 mpr_mask_intr(sc); 866 867 error = mpr_diag_reset(sc, CAN_SLEEP); 868 if (error != 0) { 869 panic("%s hard reset failed with error %d\n", __func__, error); 870 } 871 872 /* Restore the PCI state, including the MSI-X registers */ 873 mpr_pci_restore(sc); 874 875 /* Give the I/O subsystem special priority to get itself prepared */ 876 mprsas_handle_reinit(sc); 877 878 /* 879 * Get IOC Facts and allocate all structures based on this information. 880 * The attach function will also call mpr_iocfacts_allocate at startup. 881 * If relevant values have changed in IOC Facts, this function will free 882 * all of the memory based on IOC Facts and reallocate that memory. 883 */ 884 if ((error = mpr_iocfacts_allocate(sc, FALSE)) != 0) { 885 panic("%s IOC Facts based allocation failed with error %d\n", 886 __func__, error); 887 } 888 889 /* 890 * Mapping structures will be re-allocated after getting IOC Page8, so 891 * free these structures here. 892 */ 893 mpr_mapping_exit(sc); 894 895 /* 896 * The static page function currently read is IOC Page8. Others can be 897 * added in future. It's possible that the values in IOC Page8 have 898 * changed after a Diag Reset due to user modification, so always read 899 * these. Interrupts are masked, so unmask them before getting config 900 * pages. 901 */ 902 mpr_unmask_intr(sc); 903 sc->mpr_flags &= ~MPR_FLAGS_DIAGRESET; 904 mpr_base_static_config_pages(sc); 905 906 /* 907 * Some mapping info is based in IOC Page8 data, so re-initialize the 908 * mapping tables. 909 */ 910 mpr_mapping_initialize(sc); 911 912 /* 913 * Restart will reload the event masks clobbered by the reset, and 914 * then enable the port. 915 */ 916 mpr_reregister_events(sc); 917 918 /* the end of discovery will release the simq, so we're done. */ 919 mpr_dprint(sc, MPR_INIT|MPR_XINFO, "Finished sc %p post %u free %u\n", 920 sc, sc->replypostindex, sc->replyfreeindex); 921 mprsas_release_simq_reinit(sassc); 922 mpr_dprint(sc, MPR_INIT, "%s exit error= %d\n", __func__, error); 923 924 return 0; 925 } 926 927 /* Wait for the chip to ACK a word that we've put into its FIFO 928 * Wait for <timeout> seconds. In single loop wait for busy loop 929 * for 500 microseconds. 930 * Total is [ 0.5 * (2000 * <timeout>) ] in miliseconds. 931 * */ 932 static int 933 mpr_wait_db_ack(struct mpr_softc *sc, int timeout, int sleep_flag) 934 { 935 u32 cntdn, count; 936 u32 int_status; 937 u32 doorbell; 938 939 count = 0; 940 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; 941 do { 942 int_status = mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET); 943 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { 944 mpr_dprint(sc, MPR_TRACE, "%s: successful count(%d), " 945 "timeout(%d)\n", __func__, count, timeout); 946 return 0; 947 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 948 doorbell = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 949 if ((doorbell & MPI2_IOC_STATE_MASK) == 950 MPI2_IOC_STATE_FAULT) { 951 mpr_dprint(sc, MPR_FAULT, 952 "fault_state(0x%04x)!\n", doorbell); 953 return (EFAULT); 954 } 955 } else if (int_status == 0xFFFFFFFF) 956 goto out; 957 958 /* 959 * If it can sleep, sleep for 1 milisecond, else busy loop for 960 * 0.5 milisecond 961 */ 962 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) 963 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, "mprdba", 964 hz/1000); 965 else if (sleep_flag == CAN_SLEEP) 966 pause("mprdba", hz/1000); 967 else 968 DELAY(500); 969 count++; 970 } while (--cntdn); 971 972 out: 973 mpr_dprint(sc, MPR_FAULT, "%s: failed due to timeout count(%d), " 974 "int_status(%x)!\n", __func__, count, int_status); 975 return (ETIMEDOUT); 976 } 977 978 /* Wait for the chip to signal that the next word in its FIFO can be fetched */ 979 static int 980 mpr_wait_db_int(struct mpr_softc *sc) 981 { 982 int retry; 983 984 for (retry = 0; retry < MPR_DB_MAX_WAIT; retry++) { 985 if ((mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET) & 986 MPI2_HIS_IOC2SYS_DB_STATUS) != 0) 987 return (0); 988 DELAY(2000); 989 } 990 return (ETIMEDOUT); 991 } 992 993 /* Step through the synchronous command state machine, i.e. "Doorbell mode" */ 994 static int 995 mpr_request_sync(struct mpr_softc *sc, void *req, MPI2_DEFAULT_REPLY *reply, 996 int req_sz, int reply_sz, int timeout) 997 { 998 uint32_t *data32; 999 uint16_t *data16; 1000 int i, count, ioc_sz, residual; 1001 int sleep_flags = CAN_SLEEP; 1002 1003 if (curthread->td_no_sleeping) 1004 sleep_flags = NO_SLEEP; 1005 1006 /* Step 1 */ 1007 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1008 1009 /* Step 2 */ 1010 if (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED) 1011 return (EBUSY); 1012 1013 /* Step 3 1014 * Announce that a message is coming through the doorbell. Messages 1015 * are pushed at 32bit words, so round up if needed. 1016 */ 1017 count = (req_sz + 3) / 4; 1018 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET, 1019 (MPI2_FUNCTION_HANDSHAKE << MPI2_DOORBELL_FUNCTION_SHIFT) | 1020 (count << MPI2_DOORBELL_ADD_DWORDS_SHIFT)); 1021 1022 /* Step 4 */ 1023 if (mpr_wait_db_int(sc) || 1024 (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED) == 0) { 1025 mpr_dprint(sc, MPR_FAULT, "Doorbell failed to activate\n"); 1026 return (ENXIO); 1027 } 1028 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1029 if (mpr_wait_db_ack(sc, 5, sleep_flags) != 0) { 1030 mpr_dprint(sc, MPR_FAULT, "Doorbell handshake failed\n"); 1031 return (ENXIO); 1032 } 1033 1034 /* Step 5 */ 1035 /* Clock out the message data synchronously in 32-bit dwords*/ 1036 data32 = (uint32_t *)req; 1037 for (i = 0; i < count; i++) { 1038 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET, htole32(data32[i])); 1039 if (mpr_wait_db_ack(sc, 5, sleep_flags) != 0) { 1040 mpr_dprint(sc, MPR_FAULT, 1041 "Timeout while writing doorbell\n"); 1042 return (ENXIO); 1043 } 1044 } 1045 1046 /* Step 6 */ 1047 /* Clock in the reply in 16-bit words. The total length of the 1048 * message is always in the 4th byte, so clock out the first 2 words 1049 * manually, then loop the rest. 1050 */ 1051 data16 = (uint16_t *)reply; 1052 if (mpr_wait_db_int(sc) != 0) { 1053 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell 0\n"); 1054 return (ENXIO); 1055 } 1056 1057 /* 1058 * If in a BE platform, swap bytes using le16toh to not 1059 * disturb 8 bit field neighbors in destination structure 1060 * pointed by data16. 1061 */ 1062 data16[0] = 1063 le16toh(mpr_regread(sc, MPI2_DOORBELL_OFFSET)) & MPI2_DOORBELL_DATA_MASK; 1064 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1065 if (mpr_wait_db_int(sc) != 0) { 1066 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell 1\n"); 1067 return (ENXIO); 1068 } 1069 data16[1] = 1070 le16toh(mpr_regread(sc, MPI2_DOORBELL_OFFSET)) & MPI2_DOORBELL_DATA_MASK; 1071 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1072 1073 /* Number of 32bit words in the message */ 1074 ioc_sz = reply->MsgLength; 1075 1076 /* 1077 * Figure out how many 16bit words to clock in without overrunning. 1078 * The precision loss with dividing reply_sz can safely be 1079 * ignored because the messages can only be multiples of 32bits. 1080 */ 1081 residual = 0; 1082 count = MIN((reply_sz / 4), ioc_sz) * 2; 1083 if (count < ioc_sz * 2) { 1084 residual = ioc_sz * 2 - count; 1085 mpr_dprint(sc, MPR_ERROR, "Driver error, throwing away %d " 1086 "residual message words\n", residual); 1087 } 1088 1089 for (i = 2; i < count; i++) { 1090 if (mpr_wait_db_int(sc) != 0) { 1091 mpr_dprint(sc, MPR_FAULT, 1092 "Timeout reading doorbell %d\n", i); 1093 return (ENXIO); 1094 } 1095 data16[i] = le16toh(mpr_regread(sc, MPI2_DOORBELL_OFFSET)) & 1096 MPI2_DOORBELL_DATA_MASK; 1097 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1098 } 1099 1100 /* 1101 * Pull out residual words that won't fit into the provided buffer. 1102 * This keeps the chip from hanging due to a driver programming 1103 * error. 1104 */ 1105 while (residual--) { 1106 if (mpr_wait_db_int(sc) != 0) { 1107 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell\n"); 1108 return (ENXIO); 1109 } 1110 (void)mpr_regread(sc, MPI2_DOORBELL_OFFSET); 1111 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1112 } 1113 1114 /* Step 7 */ 1115 if (mpr_wait_db_int(sc) != 0) { 1116 mpr_dprint(sc, MPR_FAULT, "Timeout waiting to exit doorbell\n"); 1117 return (ENXIO); 1118 } 1119 if (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED) 1120 mpr_dprint(sc, MPR_FAULT, "Warning, doorbell still active\n"); 1121 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1122 1123 return (0); 1124 } 1125 1126 static void 1127 mpr_enqueue_request(struct mpr_softc *sc, struct mpr_command *cm) 1128 { 1129 request_descriptor_t rd; 1130 1131 MPR_FUNCTRACE(sc); 1132 mpr_dprint(sc, MPR_TRACE, "SMID %u cm %p ccb %p\n", 1133 cm->cm_desc.Default.SMID, cm, cm->cm_ccb); 1134 1135 if (sc->mpr_flags & MPR_FLAGS_ATTACH_DONE && !(sc->mpr_flags & 1136 MPR_FLAGS_SHUTDOWN)) 1137 mtx_assert(&sc->mpr_mtx, MA_OWNED); 1138 1139 if (++sc->io_cmds_active > sc->io_cmds_highwater) 1140 sc->io_cmds_highwater++; 1141 1142 KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, 1143 ("command not busy, state = %u\n", cm->cm_state)); 1144 cm->cm_state = MPR_CM_STATE_INQUEUE; 1145 1146 if (sc->atomic_desc_capable) { 1147 rd.u.low = cm->cm_desc.Words.Low; 1148 mpr_regwrite(sc, MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET, 1149 rd.u.low); 1150 } else { 1151 rd.u.low = htole32(cm->cm_desc.Words.Low); 1152 rd.u.high = htole32(cm->cm_desc.Words.High); 1153 mpr_regwrite(sc, MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET, 1154 rd.u.low); 1155 mpr_regwrite(sc, MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET, 1156 rd.u.high); 1157 } 1158 } 1159 1160 /* 1161 * Ioc facts are read in 16 bit words and and stored with le16toh, 1162 * this takes care of proper U8 fields endianness in 1163 * MPI2_IOC_FACTS_REPLY, but we still need to swap back U16 fields. 1164 */ 1165 static void 1166 adjust_iocfacts_endianness(MPI2_IOC_FACTS_REPLY *facts) 1167 { 1168 facts->HeaderVersion = le16toh(facts->HeaderVersion); 1169 facts->Reserved1 = le16toh(facts->Reserved1); 1170 facts->IOCExceptions = le16toh(facts->IOCExceptions); 1171 facts->IOCStatus = le16toh(facts->IOCStatus); 1172 facts->IOCLogInfo = le32toh(facts->IOCLogInfo); 1173 facts->RequestCredit = le16toh(facts->RequestCredit); 1174 facts->ProductID = le16toh(facts->ProductID); 1175 facts->IOCCapabilities = le32toh(facts->IOCCapabilities); 1176 facts->IOCRequestFrameSize = le16toh(facts->IOCRequestFrameSize); 1177 facts->IOCMaxChainSegmentSize = le16toh(facts->IOCMaxChainSegmentSize); 1178 facts->MaxInitiators = le16toh(facts->MaxInitiators); 1179 facts->MaxTargets = le16toh(facts->MaxTargets); 1180 facts->MaxSasExpanders = le16toh(facts->MaxSasExpanders); 1181 facts->MaxEnclosures = le16toh(facts->MaxEnclosures); 1182 facts->ProtocolFlags = le16toh(facts->ProtocolFlags); 1183 facts->HighPriorityCredit = le16toh(facts->HighPriorityCredit); 1184 facts->MaxReplyDescriptorPostQueueDepth = le16toh(facts->MaxReplyDescriptorPostQueueDepth); 1185 facts->MaxDevHandle = le16toh(facts->MaxDevHandle); 1186 facts->MaxPersistentEntries = le16toh(facts->MaxPersistentEntries); 1187 facts->MinDevHandle = le16toh(facts->MinDevHandle); 1188 } 1189 1190 /* 1191 * Just the FACTS, ma'am. 1192 */ 1193 static int 1194 mpr_get_iocfacts(struct mpr_softc *sc, MPI2_IOC_FACTS_REPLY *facts) 1195 { 1196 MPI2_DEFAULT_REPLY *reply; 1197 MPI2_IOC_FACTS_REQUEST request; 1198 int error, req_sz, reply_sz, retry = 0; 1199 1200 MPR_FUNCTRACE(sc); 1201 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 1202 1203 req_sz = sizeof(MPI2_IOC_FACTS_REQUEST); 1204 reply_sz = sizeof(MPI2_IOC_FACTS_REPLY); 1205 reply = (MPI2_DEFAULT_REPLY *)facts; 1206 1207 /* 1208 * Retry sending the initialization sequence. Sometimes, especially with 1209 * older firmware, the initialization process fails. Retrying allows the 1210 * error to clear in the firmware. 1211 */ 1212 bzero(&request, req_sz); 1213 request.Function = MPI2_FUNCTION_IOC_FACTS; 1214 while (retry < 5) { 1215 error = mpr_request_sync(sc, &request, reply, req_sz, reply_sz, 5); 1216 if (error == 0) 1217 break; 1218 mpr_dprint(sc, MPR_FAULT, "%s failed retry %d\n", __func__, retry); 1219 DELAY(1000); 1220 retry++; 1221 } 1222 1223 if (error == 0) { 1224 adjust_iocfacts_endianness(facts); 1225 mpr_dprint(sc, MPR_TRACE, "facts->IOCCapabilities 0x%x\n", facts->IOCCapabilities); 1226 } 1227 mpr_dprint(sc, MPR_INIT, "%s exit, error= %d\n", __func__, error); 1228 return (error); 1229 } 1230 1231 static int 1232 mpr_send_iocinit(struct mpr_softc *sc) 1233 { 1234 MPI2_IOC_INIT_REQUEST init; 1235 MPI2_DEFAULT_REPLY reply; 1236 int req_sz, reply_sz, error; 1237 struct timeval now; 1238 uint64_t time_in_msec; 1239 1240 MPR_FUNCTRACE(sc); 1241 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 1242 1243 /* Do a quick sanity check on proper initialization */ 1244 if ((sc->pqdepth == 0) || (sc->fqdepth == 0) || (sc->reqframesz == 0) 1245 || (sc->replyframesz == 0)) { 1246 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 1247 "Driver not fully initialized for IOCInit\n"); 1248 return (EINVAL); 1249 } 1250 1251 req_sz = sizeof(MPI2_IOC_INIT_REQUEST); 1252 reply_sz = sizeof(MPI2_IOC_INIT_REPLY); 1253 bzero(&init, req_sz); 1254 bzero(&reply, reply_sz); 1255 1256 /* 1257 * Fill in the init block. Note that most addresses are 1258 * deliberately in the lower 32bits of memory. This is a micro- 1259 * optimzation for PCI/PCIX, though it's not clear if it helps PCIe. 1260 */ 1261 init.Function = MPI2_FUNCTION_IOC_INIT; 1262 init.WhoInit = MPI2_WHOINIT_HOST_DRIVER; 1263 init.MsgVersion = htole16(MPI2_VERSION); 1264 init.HeaderVersion = htole16(MPI2_HEADER_VERSION); 1265 init.SystemRequestFrameSize = htole16((uint16_t)(sc->reqframesz / 4)); 1266 init.ReplyDescriptorPostQueueDepth = htole16(sc->pqdepth); 1267 init.ReplyFreeQueueDepth = htole16(sc->fqdepth); 1268 init.SenseBufferAddressHigh = 0; 1269 init.SystemReplyAddressHigh = 0; 1270 init.SystemRequestFrameBaseAddress.High = 0; 1271 init.SystemRequestFrameBaseAddress.Low = 1272 htole32((uint32_t)sc->req_busaddr); 1273 init.ReplyDescriptorPostQueueAddress.High = 0; 1274 init.ReplyDescriptorPostQueueAddress.Low = 1275 htole32((uint32_t)sc->post_busaddr); 1276 init.ReplyFreeQueueAddress.High = 0; 1277 init.ReplyFreeQueueAddress.Low = htole32((uint32_t)sc->free_busaddr); 1278 getmicrotime(&now); 1279 time_in_msec = (now.tv_sec * 1000 + now.tv_usec/1000); 1280 init.TimeStamp.High = htole32((time_in_msec >> 32) & 0xFFFFFFFF); 1281 init.TimeStamp.Low = htole32(time_in_msec & 0xFFFFFFFF); 1282 init.HostPageSize = HOST_PAGE_SIZE_4K; 1283 1284 error = mpr_request_sync(sc, &init, &reply, req_sz, reply_sz, 5); 1285 if ((le16toh(reply.IOCStatus) & MPI2_IOCSTATUS_MASK) != MPI2_IOCSTATUS_SUCCESS) 1286 error = ENXIO; 1287 1288 mpr_dprint(sc, MPR_INIT, "IOCInit status= 0x%x\n", le16toh(reply.IOCStatus)); 1289 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 1290 return (error); 1291 } 1292 1293 void 1294 mpr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1295 { 1296 bus_addr_t *addr; 1297 1298 addr = arg; 1299 *addr = segs[0].ds_addr; 1300 } 1301 1302 void 1303 mpr_memaddr_wait_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1304 { 1305 struct mpr_busdma_context *ctx; 1306 int need_unload, need_free; 1307 1308 ctx = (struct mpr_busdma_context *)arg; 1309 need_unload = 0; 1310 need_free = 0; 1311 1312 mpr_lock(ctx->softc); 1313 ctx->error = error; 1314 ctx->completed = 1; 1315 if ((error == 0) && (ctx->abandoned == 0)) { 1316 *ctx->addr = segs[0].ds_addr; 1317 } else { 1318 if (nsegs != 0) 1319 need_unload = 1; 1320 if (ctx->abandoned != 0) 1321 need_free = 1; 1322 } 1323 if (need_free == 0) 1324 wakeup(ctx); 1325 1326 mpr_unlock(ctx->softc); 1327 1328 if (need_unload != 0) { 1329 bus_dmamap_unload(ctx->buffer_dmat, 1330 ctx->buffer_dmamap); 1331 *ctx->addr = 0; 1332 } 1333 1334 if (need_free != 0) 1335 free(ctx, M_MPR); 1336 } 1337 1338 static int 1339 mpr_alloc_queues(struct mpr_softc *sc) 1340 { 1341 struct mpr_queue *q; 1342 int nq, i; 1343 1344 nq = sc->msi_msgs; 1345 mpr_dprint(sc, MPR_INIT|MPR_XINFO, "Allocating %d I/O queues\n", nq); 1346 1347 sc->queues = malloc(sizeof(struct mpr_queue) * nq, M_MPR, 1348 M_NOWAIT|M_ZERO); 1349 if (sc->queues == NULL) 1350 return (ENOMEM); 1351 1352 for (i = 0; i < nq; i++) { 1353 q = &sc->queues[i]; 1354 mpr_dprint(sc, MPR_INIT, "Configuring queue %d %p\n", i, q); 1355 q->sc = sc; 1356 q->qnum = i; 1357 } 1358 return (0); 1359 } 1360 1361 static int 1362 mpr_alloc_hw_queues(struct mpr_softc *sc) 1363 { 1364 bus_dma_template_t t; 1365 bus_addr_t queues_busaddr; 1366 uint8_t *queues; 1367 int qsize, fqsize, pqsize; 1368 1369 /* 1370 * The reply free queue contains 4 byte entries in multiples of 16 and 1371 * aligned on a 16 byte boundary. There must always be an unused entry. 1372 * This queue supplies fresh reply frames for the firmware to use. 1373 * 1374 * The reply descriptor post queue contains 8 byte entries in 1375 * multiples of 16 and aligned on a 16 byte boundary. This queue 1376 * contains filled-in reply frames sent from the firmware to the host. 1377 * 1378 * These two queues are allocated together for simplicity. 1379 */ 1380 sc->fqdepth = roundup2(sc->num_replies + 1, 16); 1381 sc->pqdepth = roundup2(sc->num_replies + 1, 16); 1382 fqsize= sc->fqdepth * 4; 1383 pqsize = sc->pqdepth * 8; 1384 qsize = fqsize + pqsize; 1385 1386 bus_dma_template_init(&t, sc->mpr_parent_dmat); 1387 BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(16), BD_MAXSIZE(qsize), 1388 BD_MAXSEGSIZE(qsize), BD_NSEGMENTS(1), 1389 BD_LOWADDR(BUS_SPACE_MAXADDR_32BIT)); 1390 if (bus_dma_template_tag(&t, &sc->queues_dmat)) { 1391 mpr_dprint(sc, MPR_ERROR, "Cannot allocate queues DMA tag\n"); 1392 return (ENOMEM); 1393 } 1394 if (bus_dmamem_alloc(sc->queues_dmat, (void **)&queues, BUS_DMA_NOWAIT, 1395 &sc->queues_map)) { 1396 mpr_dprint(sc, MPR_ERROR, "Cannot allocate queues memory\n"); 1397 return (ENOMEM); 1398 } 1399 bzero(queues, qsize); 1400 bus_dmamap_load(sc->queues_dmat, sc->queues_map, queues, qsize, 1401 mpr_memaddr_cb, &queues_busaddr, 0); 1402 1403 sc->free_queue = (uint32_t *)queues; 1404 sc->free_busaddr = queues_busaddr; 1405 sc->post_queue = (MPI2_REPLY_DESCRIPTORS_UNION *)(queues + fqsize); 1406 sc->post_busaddr = queues_busaddr + fqsize; 1407 mpr_dprint(sc, MPR_INIT, "free queue busaddr= %#016jx size= %d\n", 1408 (uintmax_t)sc->free_busaddr, fqsize); 1409 mpr_dprint(sc, MPR_INIT, "reply queue busaddr= %#016jx size= %d\n", 1410 (uintmax_t)sc->post_busaddr, pqsize); 1411 1412 return (0); 1413 } 1414 1415 static int 1416 mpr_alloc_replies(struct mpr_softc *sc) 1417 { 1418 bus_dma_template_t t; 1419 int rsize, num_replies; 1420 1421 /* Store the reply frame size in bytes rather than as 32bit words */ 1422 sc->replyframesz = sc->facts->ReplyFrameSize * 4; 1423 1424 /* 1425 * sc->num_replies should be one less than sc->fqdepth. We need to 1426 * allocate space for sc->fqdepth replies, but only sc->num_replies 1427 * replies can be used at once. 1428 */ 1429 num_replies = max(sc->fqdepth, sc->num_replies); 1430 1431 rsize = sc->replyframesz * num_replies; 1432 bus_dma_template_init(&t, sc->mpr_parent_dmat); 1433 BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(4), BD_MAXSIZE(rsize), 1434 BD_MAXSEGSIZE(rsize), BD_NSEGMENTS(1), 1435 BD_LOWADDR(BUS_SPACE_MAXADDR_32BIT)); 1436 if (bus_dma_template_tag(&t, &sc->reply_dmat)) { 1437 mpr_dprint(sc, MPR_ERROR, "Cannot allocate replies DMA tag\n"); 1438 return (ENOMEM); 1439 } 1440 if (bus_dmamem_alloc(sc->reply_dmat, (void **)&sc->reply_frames, 1441 BUS_DMA_NOWAIT, &sc->reply_map)) { 1442 mpr_dprint(sc, MPR_ERROR, "Cannot allocate replies memory\n"); 1443 return (ENOMEM); 1444 } 1445 bzero(sc->reply_frames, rsize); 1446 bus_dmamap_load(sc->reply_dmat, sc->reply_map, sc->reply_frames, rsize, 1447 mpr_memaddr_cb, &sc->reply_busaddr, 0); 1448 mpr_dprint(sc, MPR_INIT, "reply frames busaddr= %#016jx size= %d\n", 1449 (uintmax_t)sc->reply_busaddr, rsize); 1450 1451 return (0); 1452 } 1453 1454 static void 1455 mpr_load_chains_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1456 { 1457 struct mpr_softc *sc = arg; 1458 struct mpr_chain *chain; 1459 bus_size_t bo; 1460 int i, o, s; 1461 1462 if (error != 0) 1463 return; 1464 1465 for (i = 0, o = 0, s = 0; s < nsegs; s++) { 1466 for (bo = 0; bo + sc->chain_frame_size <= segs[s].ds_len; 1467 bo += sc->chain_frame_size) { 1468 chain = &sc->chains[i++]; 1469 chain->chain =(MPI2_SGE_IO_UNION *)(sc->chain_frames+o); 1470 chain->chain_busaddr = segs[s].ds_addr + bo; 1471 o += sc->chain_frame_size; 1472 mpr_free_chain(sc, chain); 1473 } 1474 if (bo != segs[s].ds_len) 1475 o += segs[s].ds_len - bo; 1476 } 1477 sc->chain_free_lowwater = i; 1478 } 1479 1480 static int 1481 mpr_alloc_requests(struct mpr_softc *sc) 1482 { 1483 bus_dma_template_t t; 1484 struct mpr_command *cm; 1485 int i, rsize, nsegs; 1486 1487 rsize = sc->reqframesz * sc->num_reqs; 1488 bus_dma_template_init(&t, sc->mpr_parent_dmat); 1489 BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(16), BD_MAXSIZE(rsize), 1490 BD_MAXSEGSIZE(rsize), BD_NSEGMENTS(1), 1491 BD_LOWADDR(BUS_SPACE_MAXADDR_32BIT)); 1492 if (bus_dma_template_tag(&t, &sc->req_dmat)) { 1493 mpr_dprint(sc, MPR_ERROR, "Cannot allocate request DMA tag\n"); 1494 return (ENOMEM); 1495 } 1496 if (bus_dmamem_alloc(sc->req_dmat, (void **)&sc->req_frames, 1497 BUS_DMA_NOWAIT, &sc->req_map)) { 1498 mpr_dprint(sc, MPR_ERROR, "Cannot allocate request memory\n"); 1499 return (ENOMEM); 1500 } 1501 bzero(sc->req_frames, rsize); 1502 bus_dmamap_load(sc->req_dmat, sc->req_map, sc->req_frames, rsize, 1503 mpr_memaddr_cb, &sc->req_busaddr, 0); 1504 mpr_dprint(sc, MPR_INIT, "request frames busaddr= %#016jx size= %d\n", 1505 (uintmax_t)sc->req_busaddr, rsize); 1506 1507 sc->chains = malloc(sizeof(struct mpr_chain) * sc->num_chains, M_MPR, 1508 M_NOWAIT | M_ZERO); 1509 if (!sc->chains) { 1510 mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain memory\n"); 1511 return (ENOMEM); 1512 } 1513 rsize = sc->chain_frame_size * sc->num_chains; 1514 bus_dma_template_init(&t, sc->mpr_parent_dmat); 1515 BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(16), BD_MAXSIZE(rsize), 1516 BD_MAXSEGSIZE(rsize), BD_NSEGMENTS((howmany(rsize, PAGE_SIZE))), 1517 BD_BOUNDARY(BUS_SPACE_MAXSIZE_32BIT+1)); 1518 if (bus_dma_template_tag(&t, &sc->chain_dmat)) { 1519 mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain DMA tag\n"); 1520 return (ENOMEM); 1521 } 1522 if (bus_dmamem_alloc(sc->chain_dmat, (void **)&sc->chain_frames, 1523 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->chain_map)) { 1524 mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain memory\n"); 1525 return (ENOMEM); 1526 } 1527 if (bus_dmamap_load(sc->chain_dmat, sc->chain_map, sc->chain_frames, 1528 rsize, mpr_load_chains_cb, sc, BUS_DMA_NOWAIT)) { 1529 mpr_dprint(sc, MPR_ERROR, "Cannot load chain memory\n"); 1530 bus_dmamem_free(sc->chain_dmat, sc->chain_frames, 1531 sc->chain_map); 1532 return (ENOMEM); 1533 } 1534 1535 rsize = MPR_SENSE_LEN * sc->num_reqs; 1536 bus_dma_template_clone(&t, sc->req_dmat); 1537 BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(1), BD_MAXSIZE(rsize), 1538 BD_MAXSEGSIZE(rsize)); 1539 if (bus_dma_template_tag(&t, &sc->sense_dmat)) { 1540 mpr_dprint(sc, MPR_ERROR, "Cannot allocate sense DMA tag\n"); 1541 return (ENOMEM); 1542 } 1543 if (bus_dmamem_alloc(sc->sense_dmat, (void **)&sc->sense_frames, 1544 BUS_DMA_NOWAIT, &sc->sense_map)) { 1545 mpr_dprint(sc, MPR_ERROR, "Cannot allocate sense memory\n"); 1546 return (ENOMEM); 1547 } 1548 bzero(sc->sense_frames, rsize); 1549 bus_dmamap_load(sc->sense_dmat, sc->sense_map, sc->sense_frames, rsize, 1550 mpr_memaddr_cb, &sc->sense_busaddr, 0); 1551 mpr_dprint(sc, MPR_INIT, "sense frames busaddr= %#016jx size= %d\n", 1552 (uintmax_t)sc->sense_busaddr, rsize); 1553 1554 /* 1555 * Allocate NVMe PRP Pages for NVMe SGL support only if the FW supports 1556 * these devices. 1557 */ 1558 if ((sc->facts->MsgVersion >= MPI2_VERSION_02_06) && 1559 (sc->facts->ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES)) { 1560 if (mpr_alloc_nvme_prp_pages(sc) == ENOMEM) 1561 return (ENOMEM); 1562 } 1563 1564 nsegs = (sc->maxio / PAGE_SIZE) + 1; 1565 bus_dma_template_init(&t, sc->mpr_parent_dmat); 1566 BUS_DMA_TEMPLATE_FILL(&t, BD_MAXSIZE(BUS_SPACE_MAXSIZE_32BIT), 1567 BD_NSEGMENTS(nsegs), BD_MAXSEGSIZE(BUS_SPACE_MAXSIZE_32BIT), 1568 BD_FLAGS(BUS_DMA_ALLOCNOW), BD_LOCKFUNC(busdma_lock_mutex), 1569 BD_LOCKFUNCARG(&sc->mpr_mtx), 1570 BD_BOUNDARY(BUS_SPACE_MAXSIZE_32BIT+1)); 1571 if (bus_dma_template_tag(&t, &sc->buffer_dmat)) { 1572 mpr_dprint(sc, MPR_ERROR, "Cannot allocate buffer DMA tag\n"); 1573 return (ENOMEM); 1574 } 1575 1576 /* 1577 * SMID 0 cannot be used as a free command per the firmware spec. 1578 * Just drop that command instead of risking accounting bugs. 1579 */ 1580 sc->commands = malloc(sizeof(struct mpr_command) * sc->num_reqs, 1581 M_MPR, M_WAITOK | M_ZERO); 1582 for (i = 1; i < sc->num_reqs; i++) { 1583 cm = &sc->commands[i]; 1584 cm->cm_req = sc->req_frames + i * sc->reqframesz; 1585 cm->cm_req_busaddr = sc->req_busaddr + i * sc->reqframesz; 1586 cm->cm_sense = &sc->sense_frames[i]; 1587 cm->cm_sense_busaddr = sc->sense_busaddr + i * MPR_SENSE_LEN; 1588 cm->cm_desc.Default.SMID = htole16(i); 1589 cm->cm_sc = sc; 1590 cm->cm_state = MPR_CM_STATE_BUSY; 1591 TAILQ_INIT(&cm->cm_chain_list); 1592 TAILQ_INIT(&cm->cm_prp_page_list); 1593 callout_init_mtx(&cm->cm_callout, &sc->mpr_mtx, 0); 1594 1595 /* XXX Is a failure here a critical problem? */ 1596 if (bus_dmamap_create(sc->buffer_dmat, 0, &cm->cm_dmamap) 1597 == 0) { 1598 if (i <= sc->num_prireqs) 1599 mpr_free_high_priority_command(sc, cm); 1600 else 1601 mpr_free_command(sc, cm); 1602 } else { 1603 panic("failed to allocate command %d\n", i); 1604 sc->num_reqs = i; 1605 break; 1606 } 1607 } 1608 1609 return (0); 1610 } 1611 1612 /* 1613 * Allocate contiguous buffers for PCIe NVMe devices for building native PRPs, 1614 * which are scatter/gather lists for NVMe devices. 1615 * 1616 * This buffer must be contiguous due to the nature of how NVMe PRPs are built 1617 * and translated by FW. 1618 * 1619 * returns ENOMEM if memory could not be allocated, otherwise returns 0. 1620 */ 1621 static int 1622 mpr_alloc_nvme_prp_pages(struct mpr_softc *sc) 1623 { 1624 bus_dma_template_t t; 1625 struct mpr_prp_page *prp_page; 1626 int PRPs_per_page, PRPs_required, pages_required; 1627 int rsize, i; 1628 1629 /* 1630 * Assuming a MAX_IO_SIZE of 1MB and a PAGE_SIZE of 4k, the max number 1631 * of PRPs (NVMe's Scatter/Gather Element) needed per I/O is: 1632 * MAX_IO_SIZE / PAGE_SIZE = 256 1633 * 1634 * 1 PRP entry in main frame for PRP list pointer still leaves 255 PRPs 1635 * required for the remainder of the 1MB I/O. 512 PRPs can fit into one 1636 * page (4096 / 8 = 512), so only one page is required for each I/O. 1637 * 1638 * Each of these buffers will need to be contiguous. For simplicity, 1639 * only one buffer is allocated here, which has all of the space 1640 * required for the NVMe Queue Depth. If there are problems allocating 1641 * this one buffer, this function will need to change to allocate 1642 * individual, contiguous NVME_QDEPTH buffers. 1643 * 1644 * The real calculation will use the real max io size. Above is just an 1645 * example. 1646 * 1647 */ 1648 PRPs_required = sc->maxio / PAGE_SIZE; 1649 PRPs_per_page = (PAGE_SIZE / PRP_ENTRY_SIZE) - 1; 1650 pages_required = (PRPs_required / PRPs_per_page) + 1; 1651 1652 sc->prp_buffer_size = PAGE_SIZE * pages_required; 1653 rsize = sc->prp_buffer_size * NVME_QDEPTH; 1654 bus_dma_template_init(&t, sc->mpr_parent_dmat); 1655 BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(4), BD_MAXSIZE(rsize), 1656 BD_MAXSEGSIZE(rsize), BD_NSEGMENTS(1), 1657 BD_LOWADDR(BUS_SPACE_MAXADDR_32BIT)); 1658 if (bus_dma_template_tag(&t, &sc->prp_page_dmat)) { 1659 mpr_dprint(sc, MPR_ERROR, "Cannot allocate NVMe PRP DMA " 1660 "tag\n"); 1661 return (ENOMEM); 1662 } 1663 if (bus_dmamem_alloc(sc->prp_page_dmat, (void **)&sc->prp_pages, 1664 BUS_DMA_NOWAIT, &sc->prp_page_map)) { 1665 mpr_dprint(sc, MPR_ERROR, "Cannot allocate NVMe PRP memory\n"); 1666 return (ENOMEM); 1667 } 1668 bzero(sc->prp_pages, rsize); 1669 bus_dmamap_load(sc->prp_page_dmat, sc->prp_page_map, sc->prp_pages, 1670 rsize, mpr_memaddr_cb, &sc->prp_page_busaddr, 0); 1671 1672 sc->prps = malloc(sizeof(struct mpr_prp_page) * NVME_QDEPTH, M_MPR, 1673 M_WAITOK | M_ZERO); 1674 for (i = 0; i < NVME_QDEPTH; i++) { 1675 prp_page = &sc->prps[i]; 1676 prp_page->prp_page = (uint64_t *)(sc->prp_pages + 1677 i * sc->prp_buffer_size); 1678 prp_page->prp_page_busaddr = (uint64_t)(sc->prp_page_busaddr + 1679 i * sc->prp_buffer_size); 1680 mpr_free_prp_page(sc, prp_page); 1681 sc->prp_pages_free_lowwater++; 1682 } 1683 1684 return (0); 1685 } 1686 1687 static int 1688 mpr_init_queues(struct mpr_softc *sc) 1689 { 1690 int i; 1691 1692 memset((uint8_t *)sc->post_queue, 0xff, sc->pqdepth * 8); 1693 1694 /* 1695 * According to the spec, we need to use one less reply than we 1696 * have space for on the queue. So sc->num_replies (the number we 1697 * use) should be less than sc->fqdepth (allocated size). 1698 */ 1699 if (sc->num_replies >= sc->fqdepth) 1700 return (EINVAL); 1701 1702 /* 1703 * Initialize all of the free queue entries. 1704 */ 1705 for (i = 0; i < sc->fqdepth; i++) { 1706 sc->free_queue[i] = htole32(sc->reply_busaddr + (i * sc->replyframesz)); 1707 } 1708 sc->replyfreeindex = sc->num_replies; 1709 1710 return (0); 1711 } 1712 1713 /* Get the driver parameter tunables. Lowest priority are the driver defaults. 1714 * Next are the global settings, if they exist. Highest are the per-unit 1715 * settings, if they exist. 1716 */ 1717 void 1718 mpr_get_tunables(struct mpr_softc *sc) 1719 { 1720 char tmpstr[80], mpr_debug[80]; 1721 1722 /* XXX default to some debugging for now */ 1723 sc->mpr_debug = MPR_INFO | MPR_FAULT; 1724 sc->disable_msix = 0; 1725 sc->disable_msi = 0; 1726 sc->max_msix = MPR_MSIX_MAX; 1727 sc->max_chains = MPR_CHAIN_FRAMES; 1728 sc->max_io_pages = MPR_MAXIO_PAGES; 1729 sc->enable_ssu = MPR_SSU_ENABLE_SSD_DISABLE_HDD; 1730 sc->spinup_wait_time = DEFAULT_SPINUP_WAIT; 1731 sc->use_phynum = 1; 1732 sc->max_reqframes = MPR_REQ_FRAMES; 1733 sc->max_prireqframes = MPR_PRI_REQ_FRAMES; 1734 sc->max_replyframes = MPR_REPLY_FRAMES; 1735 sc->max_evtframes = MPR_EVT_REPLY_FRAMES; 1736 1737 /* 1738 * Grab the global variables. 1739 */ 1740 bzero(mpr_debug, 80); 1741 if (TUNABLE_STR_FETCH("hw.mpr.debug_level", mpr_debug, 80) != 0) 1742 mpr_parse_debug(sc, mpr_debug); 1743 TUNABLE_INT_FETCH("hw.mpr.disable_msix", &sc->disable_msix); 1744 TUNABLE_INT_FETCH("hw.mpr.disable_msi", &sc->disable_msi); 1745 TUNABLE_INT_FETCH("hw.mpr.max_msix", &sc->max_msix); 1746 TUNABLE_INT_FETCH("hw.mpr.max_chains", &sc->max_chains); 1747 TUNABLE_INT_FETCH("hw.mpr.max_io_pages", &sc->max_io_pages); 1748 TUNABLE_INT_FETCH("hw.mpr.enable_ssu", &sc->enable_ssu); 1749 TUNABLE_INT_FETCH("hw.mpr.spinup_wait_time", &sc->spinup_wait_time); 1750 TUNABLE_INT_FETCH("hw.mpr.use_phy_num", &sc->use_phynum); 1751 TUNABLE_INT_FETCH("hw.mpr.max_reqframes", &sc->max_reqframes); 1752 TUNABLE_INT_FETCH("hw.mpr.max_prireqframes", &sc->max_prireqframes); 1753 TUNABLE_INT_FETCH("hw.mpr.max_replyframes", &sc->max_replyframes); 1754 TUNABLE_INT_FETCH("hw.mpr.max_evtframes", &sc->max_evtframes); 1755 1756 /* Grab the unit-instance variables */ 1757 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.debug_level", 1758 device_get_unit(sc->mpr_dev)); 1759 bzero(mpr_debug, 80); 1760 if (TUNABLE_STR_FETCH(tmpstr, mpr_debug, 80) != 0) 1761 mpr_parse_debug(sc, mpr_debug); 1762 1763 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.disable_msix", 1764 device_get_unit(sc->mpr_dev)); 1765 TUNABLE_INT_FETCH(tmpstr, &sc->disable_msix); 1766 1767 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.disable_msi", 1768 device_get_unit(sc->mpr_dev)); 1769 TUNABLE_INT_FETCH(tmpstr, &sc->disable_msi); 1770 1771 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_msix", 1772 device_get_unit(sc->mpr_dev)); 1773 TUNABLE_INT_FETCH(tmpstr, &sc->max_msix); 1774 1775 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_chains", 1776 device_get_unit(sc->mpr_dev)); 1777 TUNABLE_INT_FETCH(tmpstr, &sc->max_chains); 1778 1779 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_io_pages", 1780 device_get_unit(sc->mpr_dev)); 1781 TUNABLE_INT_FETCH(tmpstr, &sc->max_io_pages); 1782 1783 bzero(sc->exclude_ids, sizeof(sc->exclude_ids)); 1784 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.exclude_ids", 1785 device_get_unit(sc->mpr_dev)); 1786 TUNABLE_STR_FETCH(tmpstr, sc->exclude_ids, sizeof(sc->exclude_ids)); 1787 1788 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.enable_ssu", 1789 device_get_unit(sc->mpr_dev)); 1790 TUNABLE_INT_FETCH(tmpstr, &sc->enable_ssu); 1791 1792 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.spinup_wait_time", 1793 device_get_unit(sc->mpr_dev)); 1794 TUNABLE_INT_FETCH(tmpstr, &sc->spinup_wait_time); 1795 1796 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.use_phy_num", 1797 device_get_unit(sc->mpr_dev)); 1798 TUNABLE_INT_FETCH(tmpstr, &sc->use_phynum); 1799 1800 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_reqframes", 1801 device_get_unit(sc->mpr_dev)); 1802 TUNABLE_INT_FETCH(tmpstr, &sc->max_reqframes); 1803 1804 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_prireqframes", 1805 device_get_unit(sc->mpr_dev)); 1806 TUNABLE_INT_FETCH(tmpstr, &sc->max_prireqframes); 1807 1808 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_replyframes", 1809 device_get_unit(sc->mpr_dev)); 1810 TUNABLE_INT_FETCH(tmpstr, &sc->max_replyframes); 1811 1812 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_evtframes", 1813 device_get_unit(sc->mpr_dev)); 1814 TUNABLE_INT_FETCH(tmpstr, &sc->max_evtframes); 1815 } 1816 1817 static void 1818 mpr_setup_sysctl(struct mpr_softc *sc) 1819 { 1820 struct sysctl_ctx_list *sysctl_ctx = NULL; 1821 struct sysctl_oid *sysctl_tree = NULL; 1822 char tmpstr[80], tmpstr2[80]; 1823 1824 /* 1825 * Setup the sysctl variable so the user can change the debug level 1826 * on the fly. 1827 */ 1828 snprintf(tmpstr, sizeof(tmpstr), "MPR controller %d", 1829 device_get_unit(sc->mpr_dev)); 1830 snprintf(tmpstr2, sizeof(tmpstr2), "%d", device_get_unit(sc->mpr_dev)); 1831 1832 sysctl_ctx = device_get_sysctl_ctx(sc->mpr_dev); 1833 if (sysctl_ctx != NULL) 1834 sysctl_tree = device_get_sysctl_tree(sc->mpr_dev); 1835 1836 if (sysctl_tree == NULL) { 1837 sysctl_ctx_init(&sc->sysctl_ctx); 1838 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 1839 SYSCTL_STATIC_CHILDREN(_hw_mpr), OID_AUTO, tmpstr2, 1840 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, tmpstr); 1841 if (sc->sysctl_tree == NULL) 1842 return; 1843 sysctl_ctx = &sc->sysctl_ctx; 1844 sysctl_tree = sc->sysctl_tree; 1845 } 1846 1847 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1848 OID_AUTO, "debug_level", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 1849 sc, 0, mpr_debug_sysctl, "A", "mpr debug level"); 1850 1851 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1852 OID_AUTO, "disable_msix", CTLFLAG_RD, &sc->disable_msix, 0, 1853 "Disable the use of MSI-X interrupts"); 1854 1855 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1856 OID_AUTO, "max_msix", CTLFLAG_RD, &sc->max_msix, 0, 1857 "User-defined maximum number of MSIX queues"); 1858 1859 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1860 OID_AUTO, "msix_msgs", CTLFLAG_RD, &sc->msi_msgs, 0, 1861 "Negotiated number of MSIX queues"); 1862 1863 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1864 OID_AUTO, "max_reqframes", CTLFLAG_RD, &sc->max_reqframes, 0, 1865 "Total number of allocated request frames"); 1866 1867 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1868 OID_AUTO, "max_prireqframes", CTLFLAG_RD, &sc->max_prireqframes, 0, 1869 "Total number of allocated high priority request frames"); 1870 1871 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1872 OID_AUTO, "max_replyframes", CTLFLAG_RD, &sc->max_replyframes, 0, 1873 "Total number of allocated reply frames"); 1874 1875 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1876 OID_AUTO, "max_evtframes", CTLFLAG_RD, &sc->max_evtframes, 0, 1877 "Total number of event frames allocated"); 1878 1879 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1880 OID_AUTO, "firmware_version", CTLFLAG_RD, sc->fw_version, 1881 strlen(sc->fw_version), "firmware version"); 1882 1883 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1884 OID_AUTO, "driver_version", CTLFLAG_RD, MPR_DRIVER_VERSION, 1885 strlen(MPR_DRIVER_VERSION), "driver version"); 1886 1887 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1888 OID_AUTO, "msg_version", CTLFLAG_RD, sc->msg_version, 1889 strlen(sc->msg_version), "message interface version (deprecated)"); 1890 1891 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1892 OID_AUTO, "io_cmds_active", CTLFLAG_RD, 1893 &sc->io_cmds_active, 0, "number of currently active commands"); 1894 1895 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1896 OID_AUTO, "io_cmds_highwater", CTLFLAG_RD, 1897 &sc->io_cmds_highwater, 0, "maximum active commands seen"); 1898 1899 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1900 OID_AUTO, "chain_free", CTLFLAG_RD, 1901 &sc->chain_free, 0, "number of free chain elements"); 1902 1903 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1904 OID_AUTO, "chain_free_lowwater", CTLFLAG_RD, 1905 &sc->chain_free_lowwater, 0,"lowest number of free chain elements"); 1906 1907 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1908 OID_AUTO, "max_chains", CTLFLAG_RD, 1909 &sc->max_chains, 0,"maximum chain frames that will be allocated"); 1910 1911 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1912 OID_AUTO, "max_io_pages", CTLFLAG_RD, 1913 &sc->max_io_pages, 0,"maximum pages to allow per I/O (if <1 use " 1914 "IOCFacts)"); 1915 1916 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1917 OID_AUTO, "enable_ssu", CTLFLAG_RW, &sc->enable_ssu, 0, 1918 "enable SSU to SATA SSD/HDD at shutdown"); 1919 1920 SYSCTL_ADD_UQUAD(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1921 OID_AUTO, "chain_alloc_fail", CTLFLAG_RD, 1922 &sc->chain_alloc_fail, "chain allocation failures"); 1923 1924 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1925 OID_AUTO, "spinup_wait_time", CTLFLAG_RD, 1926 &sc->spinup_wait_time, DEFAULT_SPINUP_WAIT, "seconds to wait for " 1927 "spinup after SATA ID error"); 1928 1929 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1930 OID_AUTO, "dump_reqs", 1931 CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, 1932 sc, 0, mpr_dump_reqs, "I", "Dump Active Requests"); 1933 1934 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1935 OID_AUTO, "dump_reqs_alltypes", CTLFLAG_RW, 1936 &sc->dump_reqs_alltypes, 0, 1937 "dump all request types not just inqueue"); 1938 1939 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1940 OID_AUTO, "use_phy_num", CTLFLAG_RD, &sc->use_phynum, 0, 1941 "Use the phy number for enumeration"); 1942 1943 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1944 OID_AUTO, "prp_pages_free", CTLFLAG_RD, 1945 &sc->prp_pages_free, 0, "number of free PRP pages"); 1946 1947 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1948 OID_AUTO, "prp_pages_free_lowwater", CTLFLAG_RD, 1949 &sc->prp_pages_free_lowwater, 0,"lowest number of free PRP pages"); 1950 1951 SYSCTL_ADD_UQUAD(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1952 OID_AUTO, "prp_page_alloc_fail", CTLFLAG_RD, 1953 &sc->prp_page_alloc_fail, "PRP page allocation failures"); 1954 } 1955 1956 static struct mpr_debug_string { 1957 char *name; 1958 int flag; 1959 } mpr_debug_strings[] = { 1960 {"info", MPR_INFO}, 1961 {"fault", MPR_FAULT}, 1962 {"event", MPR_EVENT}, 1963 {"log", MPR_LOG}, 1964 {"recovery", MPR_RECOVERY}, 1965 {"error", MPR_ERROR}, 1966 {"init", MPR_INIT}, 1967 {"xinfo", MPR_XINFO}, 1968 {"user", MPR_USER}, 1969 {"mapping", MPR_MAPPING}, 1970 {"trace", MPR_TRACE} 1971 }; 1972 1973 enum mpr_debug_level_combiner { 1974 COMB_NONE, 1975 COMB_ADD, 1976 COMB_SUB 1977 }; 1978 1979 static int 1980 mpr_debug_sysctl(SYSCTL_HANDLER_ARGS) 1981 { 1982 struct mpr_softc *sc; 1983 struct mpr_debug_string *string; 1984 struct sbuf *sbuf; 1985 char *buffer; 1986 size_t sz; 1987 int i, len, debug, error; 1988 1989 sc = (struct mpr_softc *)arg1; 1990 1991 error = sysctl_wire_old_buffer(req, 0); 1992 if (error != 0) 1993 return (error); 1994 1995 sbuf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 1996 debug = sc->mpr_debug; 1997 1998 sbuf_printf(sbuf, "%#x", debug); 1999 2000 sz = sizeof(mpr_debug_strings) / sizeof(mpr_debug_strings[0]); 2001 for (i = 0; i < sz; i++) { 2002 string = &mpr_debug_strings[i]; 2003 if (debug & string->flag) 2004 sbuf_printf(sbuf, ",%s", string->name); 2005 } 2006 2007 error = sbuf_finish(sbuf); 2008 sbuf_delete(sbuf); 2009 2010 if (error || req->newptr == NULL) 2011 return (error); 2012 2013 len = req->newlen - req->newidx; 2014 if (len == 0) 2015 return (0); 2016 2017 buffer = malloc(len, M_MPR, M_ZERO|M_WAITOK); 2018 error = SYSCTL_IN(req, buffer, len); 2019 2020 mpr_parse_debug(sc, buffer); 2021 2022 free(buffer, M_MPR); 2023 return (error); 2024 } 2025 2026 static void 2027 mpr_parse_debug(struct mpr_softc *sc, char *list) 2028 { 2029 struct mpr_debug_string *string; 2030 enum mpr_debug_level_combiner op; 2031 char *token, *endtoken; 2032 size_t sz; 2033 int flags, i; 2034 2035 if (list == NULL || *list == '\0') 2036 return; 2037 2038 if (*list == '+') { 2039 op = COMB_ADD; 2040 list++; 2041 } else if (*list == '-') { 2042 op = COMB_SUB; 2043 list++; 2044 } else 2045 op = COMB_NONE; 2046 if (*list == '\0') 2047 return; 2048 2049 flags = 0; 2050 sz = sizeof(mpr_debug_strings) / sizeof(mpr_debug_strings[0]); 2051 while ((token = strsep(&list, ":,")) != NULL) { 2052 /* Handle integer flags */ 2053 flags |= strtol(token, &endtoken, 0); 2054 if (token != endtoken) 2055 continue; 2056 2057 /* Handle text flags */ 2058 for (i = 0; i < sz; i++) { 2059 string = &mpr_debug_strings[i]; 2060 if (strcasecmp(token, string->name) == 0) { 2061 flags |= string->flag; 2062 break; 2063 } 2064 } 2065 } 2066 2067 switch (op) { 2068 case COMB_NONE: 2069 sc->mpr_debug = flags; 2070 break; 2071 case COMB_ADD: 2072 sc->mpr_debug |= flags; 2073 break; 2074 case COMB_SUB: 2075 sc->mpr_debug &= (~flags); 2076 break; 2077 } 2078 return; 2079 } 2080 2081 struct mpr_dumpreq_hdr { 2082 uint32_t smid; 2083 uint32_t state; 2084 uint32_t numframes; 2085 uint32_t deschi; 2086 uint32_t desclo; 2087 }; 2088 2089 static int 2090 mpr_dump_reqs(SYSCTL_HANDLER_ARGS) 2091 { 2092 struct mpr_softc *sc; 2093 struct mpr_chain *chain, *chain1; 2094 struct mpr_command *cm; 2095 struct mpr_dumpreq_hdr hdr; 2096 struct sbuf *sb; 2097 uint32_t smid, state; 2098 int i, numreqs, error = 0; 2099 2100 sc = (struct mpr_softc *)arg1; 2101 2102 if ((error = priv_check(curthread, PRIV_DRIVER)) != 0) { 2103 printf("priv check error %d\n", error); 2104 return (error); 2105 } 2106 2107 state = MPR_CM_STATE_INQUEUE; 2108 smid = 1; 2109 numreqs = sc->num_reqs; 2110 2111 if (req->newptr != NULL) 2112 return (EINVAL); 2113 2114 if (smid == 0 || smid > sc->num_reqs) 2115 return (EINVAL); 2116 if (numreqs <= 0 || (numreqs + smid > sc->num_reqs)) 2117 numreqs = sc->num_reqs; 2118 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 2119 2120 /* Best effort, no locking */ 2121 for (i = smid; i < numreqs; i++) { 2122 cm = &sc->commands[i]; 2123 if ((sc->dump_reqs_alltypes == 0) && (cm->cm_state != state)) 2124 continue; 2125 hdr.smid = i; 2126 hdr.state = cm->cm_state; 2127 hdr.numframes = 1; 2128 hdr.deschi = cm->cm_desc.Words.High; 2129 hdr.desclo = cm->cm_desc.Words.Low; 2130 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, 2131 chain1) 2132 hdr.numframes++; 2133 sbuf_bcat(sb, &hdr, sizeof(hdr)); 2134 sbuf_bcat(sb, cm->cm_req, 128); 2135 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, 2136 chain1) 2137 sbuf_bcat(sb, chain->chain, 128); 2138 } 2139 2140 error = sbuf_finish(sb); 2141 sbuf_delete(sb); 2142 return (error); 2143 } 2144 2145 int 2146 mpr_attach(struct mpr_softc *sc) 2147 { 2148 int error; 2149 2150 MPR_FUNCTRACE(sc); 2151 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 2152 2153 mtx_init(&sc->mpr_mtx, "MPR lock", NULL, MTX_DEF); 2154 callout_init_mtx(&sc->periodic, &sc->mpr_mtx, 0); 2155 callout_init_mtx(&sc->device_check_callout, &sc->mpr_mtx, 0); 2156 TAILQ_INIT(&sc->event_list); 2157 timevalclear(&sc->lastfail); 2158 2159 if ((error = mpr_transition_ready(sc)) != 0) { 2160 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 2161 "Failed to transition ready\n"); 2162 return (error); 2163 } 2164 2165 sc->facts = malloc(sizeof(MPI2_IOC_FACTS_REPLY), M_MPR, 2166 M_ZERO|M_NOWAIT); 2167 if (!sc->facts) { 2168 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 2169 "Cannot allocate memory, exit\n"); 2170 return (ENOMEM); 2171 } 2172 2173 /* 2174 * Get IOC Facts and allocate all structures based on this information. 2175 * A Diag Reset will also call mpr_iocfacts_allocate and re-read the IOC 2176 * Facts. If relevant values have changed in IOC Facts, this function 2177 * will free all of the memory based on IOC Facts and reallocate that 2178 * memory. If this fails, any allocated memory should already be freed. 2179 */ 2180 if ((error = mpr_iocfacts_allocate(sc, TRUE)) != 0) { 2181 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC Facts allocation " 2182 "failed with error %d\n", error); 2183 return (error); 2184 } 2185 2186 /* Start the periodic watchdog check on the IOC Doorbell */ 2187 mpr_periodic(sc); 2188 2189 /* 2190 * The portenable will kick off discovery events that will drive the 2191 * rest of the initialization process. The CAM/SAS module will 2192 * hold up the boot sequence until discovery is complete. 2193 */ 2194 sc->mpr_ich.ich_func = mpr_startup; 2195 sc->mpr_ich.ich_arg = sc; 2196 if (config_intrhook_establish(&sc->mpr_ich) != 0) { 2197 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 2198 "Cannot establish MPR config hook\n"); 2199 error = EINVAL; 2200 } 2201 2202 /* 2203 * Allow IR to shutdown gracefully when shutdown occurs. 2204 */ 2205 sc->shutdown_eh = EVENTHANDLER_REGISTER(shutdown_final, 2206 mprsas_ir_shutdown, sc, SHUTDOWN_PRI_DEFAULT); 2207 2208 if (sc->shutdown_eh == NULL) 2209 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 2210 "shutdown event registration failed\n"); 2211 2212 mpr_setup_sysctl(sc); 2213 2214 sc->mpr_flags |= MPR_FLAGS_ATTACH_DONE; 2215 mpr_dprint(sc, MPR_INIT, "%s exit error= %d\n", __func__, error); 2216 2217 return (error); 2218 } 2219 2220 /* Run through any late-start handlers. */ 2221 static void 2222 mpr_startup(void *arg) 2223 { 2224 struct mpr_softc *sc; 2225 2226 sc = (struct mpr_softc *)arg; 2227 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 2228 2229 mpr_lock(sc); 2230 mpr_unmask_intr(sc); 2231 2232 /* initialize device mapping tables */ 2233 mpr_base_static_config_pages(sc); 2234 mpr_mapping_initialize(sc); 2235 mprsas_startup(sc); 2236 mpr_unlock(sc); 2237 2238 mpr_dprint(sc, MPR_INIT, "disestablish config intrhook\n"); 2239 config_intrhook_disestablish(&sc->mpr_ich); 2240 sc->mpr_ich.ich_arg = NULL; 2241 2242 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 2243 } 2244 2245 /* Periodic watchdog. Is called with the driver lock already held. */ 2246 static void 2247 mpr_periodic(void *arg) 2248 { 2249 struct mpr_softc *sc; 2250 uint32_t db; 2251 2252 sc = (struct mpr_softc *)arg; 2253 if (sc->mpr_flags & MPR_FLAGS_SHUTDOWN) 2254 return; 2255 2256 db = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 2257 if ((db & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 2258 if ((db & MPI2_DOORBELL_FAULT_CODE_MASK) == 2259 IFAULT_IOP_OVER_TEMP_THRESHOLD_EXCEEDED) { 2260 panic("TEMPERATURE FAULT: STOPPING."); 2261 } 2262 mpr_dprint(sc, MPR_FAULT, "IOC Fault 0x%08x, Resetting\n", db); 2263 mpr_reinit(sc); 2264 } 2265 2266 callout_reset_sbt(&sc->periodic, MPR_PERIODIC_DELAY * SBT_1S, 0, 2267 mpr_periodic, sc, C_PREL(1)); 2268 } 2269 2270 static void 2271 mpr_log_evt_handler(struct mpr_softc *sc, uintptr_t data, 2272 MPI2_EVENT_NOTIFICATION_REPLY *event) 2273 { 2274 MPI2_EVENT_DATA_LOG_ENTRY_ADDED *entry; 2275 2276 MPR_DPRINT_EVENT(sc, generic, event); 2277 2278 switch (event->Event) { 2279 case MPI2_EVENT_LOG_DATA: 2280 mpr_dprint(sc, MPR_EVENT, "MPI2_EVENT_LOG_DATA:\n"); 2281 if (sc->mpr_debug & MPR_EVENT) 2282 hexdump(event->EventData, event->EventDataLength, NULL, 2283 0); 2284 break; 2285 case MPI2_EVENT_LOG_ENTRY_ADDED: 2286 entry = (MPI2_EVENT_DATA_LOG_ENTRY_ADDED *)event->EventData; 2287 mpr_dprint(sc, MPR_EVENT, "MPI2_EVENT_LOG_ENTRY_ADDED event " 2288 "0x%x Sequence %d:\n", entry->LogEntryQualifier, 2289 entry->LogSequence); 2290 break; 2291 default: 2292 break; 2293 } 2294 return; 2295 } 2296 2297 static int 2298 mpr_attach_log(struct mpr_softc *sc) 2299 { 2300 uint8_t events[16]; 2301 2302 bzero(events, 16); 2303 setbit(events, MPI2_EVENT_LOG_DATA); 2304 setbit(events, MPI2_EVENT_LOG_ENTRY_ADDED); 2305 2306 mpr_register_events(sc, events, mpr_log_evt_handler, NULL, 2307 &sc->mpr_log_eh); 2308 2309 return (0); 2310 } 2311 2312 static int 2313 mpr_detach_log(struct mpr_softc *sc) 2314 { 2315 2316 if (sc->mpr_log_eh != NULL) 2317 mpr_deregister_events(sc, sc->mpr_log_eh); 2318 return (0); 2319 } 2320 2321 /* 2322 * Free all of the driver resources and detach submodules. Should be called 2323 * without the lock held. 2324 */ 2325 int 2326 mpr_free(struct mpr_softc *sc) 2327 { 2328 int error; 2329 2330 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 2331 /* Turn off the watchdog */ 2332 mpr_lock(sc); 2333 sc->mpr_flags |= MPR_FLAGS_SHUTDOWN; 2334 mpr_unlock(sc); 2335 /* Lock must not be held for this */ 2336 callout_drain(&sc->periodic); 2337 callout_drain(&sc->device_check_callout); 2338 2339 if (((error = mpr_detach_log(sc)) != 0) || 2340 ((error = mpr_detach_sas(sc)) != 0)) { 2341 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "failed to detach " 2342 "subsystems, error= %d, exit\n", error); 2343 return (error); 2344 } 2345 2346 mpr_detach_user(sc); 2347 2348 /* Put the IOC back in the READY state. */ 2349 mpr_lock(sc); 2350 if ((error = mpr_transition_ready(sc)) != 0) { 2351 mpr_unlock(sc); 2352 return (error); 2353 } 2354 mpr_unlock(sc); 2355 2356 if (sc->facts != NULL) 2357 free(sc->facts, M_MPR); 2358 2359 /* 2360 * Free all buffers that are based on IOC Facts. A Diag Reset may need 2361 * to free these buffers too. 2362 */ 2363 mpr_iocfacts_free(sc); 2364 2365 if (sc->sysctl_tree != NULL) 2366 sysctl_ctx_free(&sc->sysctl_ctx); 2367 2368 /* Deregister the shutdown function */ 2369 if (sc->shutdown_eh != NULL) 2370 EVENTHANDLER_DEREGISTER(shutdown_final, sc->shutdown_eh); 2371 2372 mtx_destroy(&sc->mpr_mtx); 2373 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 2374 2375 return (0); 2376 } 2377 2378 static __inline void 2379 mpr_complete_command(struct mpr_softc *sc, struct mpr_command *cm) 2380 { 2381 MPR_FUNCTRACE(sc); 2382 2383 if (cm == NULL) { 2384 mpr_dprint(sc, MPR_ERROR, "Completing NULL command\n"); 2385 return; 2386 } 2387 2388 KASSERT(cm->cm_state == MPR_CM_STATE_INQUEUE, 2389 ("command not inqueue, state = %u\n", cm->cm_state)); 2390 cm->cm_state = MPR_CM_STATE_BUSY; 2391 if (cm->cm_flags & MPR_CM_FLAGS_POLLED) 2392 cm->cm_flags |= MPR_CM_FLAGS_COMPLETE; 2393 2394 if (cm->cm_complete != NULL) { 2395 mpr_dprint(sc, MPR_TRACE, 2396 "%s cm %p calling cm_complete %p data %p reply %p\n", 2397 __func__, cm, cm->cm_complete, cm->cm_complete_data, 2398 cm->cm_reply); 2399 cm->cm_complete(sc, cm); 2400 } 2401 2402 if (cm->cm_flags & MPR_CM_FLAGS_WAKEUP) { 2403 mpr_dprint(sc, MPR_TRACE, "waking up %p\n", cm); 2404 wakeup(cm); 2405 } 2406 2407 if (sc->io_cmds_active != 0) { 2408 sc->io_cmds_active--; 2409 } else { 2410 mpr_dprint(sc, MPR_ERROR, "Warning: io_cmds_active is " 2411 "out of sync - resynching to 0\n"); 2412 } 2413 } 2414 2415 static void 2416 mpr_sas_log_info(struct mpr_softc *sc , u32 log_info) 2417 { 2418 union loginfo_type { 2419 u32 loginfo; 2420 struct { 2421 u32 subcode:16; 2422 u32 code:8; 2423 u32 originator:4; 2424 u32 bus_type:4; 2425 } dw; 2426 }; 2427 union loginfo_type sas_loginfo; 2428 char *originator_str = NULL; 2429 2430 sas_loginfo.loginfo = log_info; 2431 if (sas_loginfo.dw.bus_type != 3 /*SAS*/) 2432 return; 2433 2434 /* each nexus loss loginfo */ 2435 if (log_info == 0x31170000) 2436 return; 2437 2438 /* eat the loginfos associated with task aborts */ 2439 if ((log_info == 30050000) || (log_info == 0x31140000) || 2440 (log_info == 0x31130000)) 2441 return; 2442 2443 switch (sas_loginfo.dw.originator) { 2444 case 0: 2445 originator_str = "IOP"; 2446 break; 2447 case 1: 2448 originator_str = "PL"; 2449 break; 2450 case 2: 2451 originator_str = "IR"; 2452 break; 2453 } 2454 2455 mpr_dprint(sc, MPR_LOG, "log_info(0x%08x): originator(%s), " 2456 "code(0x%02x), sub_code(0x%04x)\n", log_info, originator_str, 2457 sas_loginfo.dw.code, sas_loginfo.dw.subcode); 2458 } 2459 2460 static void 2461 mpr_display_reply_info(struct mpr_softc *sc, uint8_t *reply) 2462 { 2463 MPI2DefaultReply_t *mpi_reply; 2464 u16 sc_status; 2465 2466 mpi_reply = (MPI2DefaultReply_t*)reply; 2467 sc_status = le16toh(mpi_reply->IOCStatus); 2468 if (sc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) 2469 mpr_sas_log_info(sc, le32toh(mpi_reply->IOCLogInfo)); 2470 } 2471 2472 void 2473 mpr_intr(void *data) 2474 { 2475 struct mpr_softc *sc; 2476 uint32_t status; 2477 2478 sc = (struct mpr_softc *)data; 2479 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2480 2481 /* 2482 * Check interrupt status register to flush the bus. This is 2483 * needed for both INTx interrupts and driver-driven polling 2484 */ 2485 status = mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET); 2486 if ((status & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) == 0) 2487 return; 2488 2489 mpr_lock(sc); 2490 mpr_intr_locked(data); 2491 mpr_unlock(sc); 2492 return; 2493 } 2494 2495 /* 2496 * In theory, MSI/MSIX interrupts shouldn't need to read any registers on the 2497 * chip. Hopefully this theory is correct. 2498 */ 2499 void 2500 mpr_intr_msi(void *data) 2501 { 2502 struct mpr_softc *sc; 2503 2504 sc = (struct mpr_softc *)data; 2505 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2506 mpr_lock(sc); 2507 mpr_intr_locked(data); 2508 mpr_unlock(sc); 2509 return; 2510 } 2511 2512 /* 2513 * The locking is overly broad and simplistic, but easy to deal with for now. 2514 */ 2515 void 2516 mpr_intr_locked(void *data) 2517 { 2518 MPI2_REPLY_DESCRIPTORS_UNION *desc; 2519 MPI2_DIAG_RELEASE_REPLY *rel_rep; 2520 mpr_fw_diagnostic_buffer_t *pBuffer; 2521 struct mpr_softc *sc; 2522 uint64_t tdesc; 2523 struct mpr_command *cm = NULL; 2524 uint8_t flags; 2525 u_int pq; 2526 2527 sc = (struct mpr_softc *)data; 2528 2529 pq = sc->replypostindex; 2530 mpr_dprint(sc, MPR_TRACE, 2531 "%s sc %p starting with replypostindex %u\n", 2532 __func__, sc, sc->replypostindex); 2533 2534 for ( ;; ) { 2535 cm = NULL; 2536 desc = &sc->post_queue[sc->replypostindex]; 2537 2538 /* 2539 * Copy and clear out the descriptor so that any reentry will 2540 * immediately know that this descriptor has already been 2541 * looked at. There is unfortunate casting magic because the 2542 * MPI API doesn't have a cardinal 64bit type. 2543 */ 2544 tdesc = 0xffffffffffffffff; 2545 tdesc = atomic_swap_64((uint64_t *)desc, tdesc); 2546 desc = (MPI2_REPLY_DESCRIPTORS_UNION *)&tdesc; 2547 2548 flags = desc->Default.ReplyFlags & 2549 MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 2550 if ((flags == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) || 2551 (le32toh(desc->Words.High) == 0xffffffff)) 2552 break; 2553 2554 /* increment the replypostindex now, so that event handlers 2555 * and cm completion handlers which decide to do a diag 2556 * reset can zero it without it getting incremented again 2557 * afterwards, and we break out of this loop on the next 2558 * iteration since the reply post queue has been cleared to 2559 * 0xFF and all descriptors look unused (which they are). 2560 */ 2561 if (++sc->replypostindex >= sc->pqdepth) 2562 sc->replypostindex = 0; 2563 2564 switch (flags) { 2565 case MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS: 2566 case MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS: 2567 case MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS: 2568 cm = &sc->commands[le16toh(desc->SCSIIOSuccess.SMID)]; 2569 cm->cm_reply = NULL; 2570 break; 2571 case MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY: 2572 { 2573 uint32_t baddr; 2574 uint8_t *reply; 2575 2576 /* 2577 * Re-compose the reply address from the address 2578 * sent back from the chip. The ReplyFrameAddress 2579 * is the lower 32 bits of the physical address of 2580 * particular reply frame. Convert that address to 2581 * host format, and then use that to provide the 2582 * offset against the virtual address base 2583 * (sc->reply_frames). 2584 */ 2585 baddr = le32toh(desc->AddressReply.ReplyFrameAddress); 2586 reply = sc->reply_frames + 2587 (baddr - ((uint32_t)sc->reply_busaddr)); 2588 /* 2589 * Make sure the reply we got back is in a valid 2590 * range. If not, go ahead and panic here, since 2591 * we'll probably panic as soon as we deference the 2592 * reply pointer anyway. 2593 */ 2594 if ((reply < sc->reply_frames) 2595 || (reply > (sc->reply_frames + 2596 (sc->fqdepth * sc->replyframesz)))) { 2597 printf("%s: WARNING: reply %p out of range!\n", 2598 __func__, reply); 2599 printf("%s: reply_frames %p, fqdepth %d, " 2600 "frame size %d\n", __func__, 2601 sc->reply_frames, sc->fqdepth, 2602 sc->replyframesz); 2603 printf("%s: baddr %#x,\n", __func__, baddr); 2604 /* LSI-TODO. See Linux Code for Graceful exit */ 2605 panic("Reply address out of range"); 2606 } 2607 if (le16toh(desc->AddressReply.SMID) == 0) { 2608 if (((MPI2_DEFAULT_REPLY *)reply)->Function == 2609 MPI2_FUNCTION_DIAG_BUFFER_POST) { 2610 /* 2611 * If SMID is 0 for Diag Buffer Post, 2612 * this implies that the reply is due to 2613 * a release function with a status that 2614 * the buffer has been released. Set 2615 * the buffer flags accordingly. 2616 */ 2617 rel_rep = 2618 (MPI2_DIAG_RELEASE_REPLY *)reply; 2619 if ((le16toh(rel_rep->IOCStatus) & 2620 MPI2_IOCSTATUS_MASK) == 2621 MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) 2622 { 2623 pBuffer = 2624 &sc->fw_diag_buffer_list[ 2625 rel_rep->BufferType]; 2626 pBuffer->valid_data = TRUE; 2627 pBuffer->owned_by_firmware = 2628 FALSE; 2629 pBuffer->immediate = FALSE; 2630 } 2631 } else 2632 mpr_dispatch_event(sc, baddr, 2633 (MPI2_EVENT_NOTIFICATION_REPLY *) 2634 reply); 2635 } else { 2636 cm = &sc->commands[ 2637 le16toh(desc->AddressReply.SMID)]; 2638 if (cm->cm_state == MPR_CM_STATE_INQUEUE) { 2639 cm->cm_reply = reply; 2640 cm->cm_reply_data = 2641 le32toh(desc->AddressReply. 2642 ReplyFrameAddress); 2643 } else { 2644 mpr_dprint(sc, MPR_RECOVERY, 2645 "Bad state for ADDRESS_REPLY status," 2646 " ignoring state %d cm %p\n", 2647 cm->cm_state, cm); 2648 } 2649 } 2650 break; 2651 } 2652 case MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS: 2653 case MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER: 2654 case MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS: 2655 default: 2656 /* Unhandled */ 2657 mpr_dprint(sc, MPR_ERROR, "Unhandled reply 0x%x\n", 2658 desc->Default.ReplyFlags); 2659 cm = NULL; 2660 break; 2661 } 2662 2663 if (cm != NULL) { 2664 // Print Error reply frame 2665 if (cm->cm_reply) 2666 mpr_display_reply_info(sc,cm->cm_reply); 2667 mpr_complete_command(sc, cm); 2668 } 2669 } 2670 2671 if (pq != sc->replypostindex) { 2672 mpr_dprint(sc, MPR_TRACE, "%s sc %p writing postindex %d\n", 2673 __func__, sc, sc->replypostindex); 2674 mpr_regwrite(sc, MPI2_REPLY_POST_HOST_INDEX_OFFSET, 2675 sc->replypostindex); 2676 } 2677 2678 return; 2679 } 2680 2681 static void 2682 mpr_dispatch_event(struct mpr_softc *sc, uintptr_t data, 2683 MPI2_EVENT_NOTIFICATION_REPLY *reply) 2684 { 2685 struct mpr_event_handle *eh; 2686 int event, handled = 0; 2687 2688 event = le16toh(reply->Event); 2689 TAILQ_FOREACH(eh, &sc->event_list, eh_list) { 2690 if (isset(eh->mask, event)) { 2691 eh->callback(sc, data, reply); 2692 handled++; 2693 } 2694 } 2695 2696 if (handled == 0) 2697 mpr_dprint(sc, MPR_EVENT, "Unhandled event 0x%x\n", 2698 le16toh(event)); 2699 2700 /* 2701 * This is the only place that the event/reply should be freed. 2702 * Anything wanting to hold onto the event data should have 2703 * already copied it into their own storage. 2704 */ 2705 mpr_free_reply(sc, data); 2706 } 2707 2708 static void 2709 mpr_reregister_events_complete(struct mpr_softc *sc, struct mpr_command *cm) 2710 { 2711 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2712 2713 if (cm->cm_reply) 2714 MPR_DPRINT_EVENT(sc, generic, 2715 (MPI2_EVENT_NOTIFICATION_REPLY *)cm->cm_reply); 2716 2717 mpr_free_command(sc, cm); 2718 2719 /* next, send a port enable */ 2720 mprsas_startup(sc); 2721 } 2722 2723 /* 2724 * For both register_events and update_events, the caller supplies a bitmap 2725 * of events that it _wants_. These functions then turn that into a bitmask 2726 * suitable for the controller. 2727 */ 2728 int 2729 mpr_register_events(struct mpr_softc *sc, uint8_t *mask, 2730 mpr_evt_callback_t *cb, void *data, struct mpr_event_handle **handle) 2731 { 2732 struct mpr_event_handle *eh; 2733 int error = 0; 2734 2735 eh = malloc(sizeof(struct mpr_event_handle), M_MPR, M_WAITOK|M_ZERO); 2736 eh->callback = cb; 2737 eh->data = data; 2738 TAILQ_INSERT_TAIL(&sc->event_list, eh, eh_list); 2739 if (mask != NULL) 2740 error = mpr_update_events(sc, eh, mask); 2741 *handle = eh; 2742 2743 return (error); 2744 } 2745 2746 int 2747 mpr_update_events(struct mpr_softc *sc, struct mpr_event_handle *handle, 2748 uint8_t *mask) 2749 { 2750 MPI2_EVENT_NOTIFICATION_REQUEST *evtreq; 2751 MPI2_EVENT_NOTIFICATION_REPLY *reply = NULL; 2752 struct mpr_command *cm = NULL; 2753 struct mpr_event_handle *eh; 2754 int error, i; 2755 2756 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2757 2758 if ((mask != NULL) && (handle != NULL)) 2759 bcopy(mask, &handle->mask[0], 16); 2760 memset(sc->event_mask, 0xff, 16); 2761 2762 TAILQ_FOREACH(eh, &sc->event_list, eh_list) { 2763 for (i = 0; i < 16; i++) 2764 sc->event_mask[i] &= ~eh->mask[i]; 2765 } 2766 2767 if ((cm = mpr_alloc_command(sc)) == NULL) 2768 return (EBUSY); 2769 evtreq = (MPI2_EVENT_NOTIFICATION_REQUEST *)cm->cm_req; 2770 evtreq->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 2771 evtreq->MsgFlags = 0; 2772 evtreq->SASBroadcastPrimitiveMasks = 0; 2773 #ifdef MPR_DEBUG_ALL_EVENTS 2774 { 2775 u_char fullmask[sizeof(evtreq->EventMasks)]; 2776 memset(fullmask, 0x00, sizeof(fullmask)); 2777 bcopy(fullmask, (uint8_t *)&evtreq->EventMasks, sizeof(fullmask)); 2778 } 2779 #else 2780 bcopy(sc->event_mask, (uint8_t *)&evtreq->EventMasks, sizeof(sc->event_mask)); 2781 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 2782 evtreq->EventMasks[i] = htole32(evtreq->EventMasks[i]); 2783 #endif 2784 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 2785 cm->cm_data = NULL; 2786 2787 error = mpr_request_polled(sc, &cm); 2788 if (cm != NULL) 2789 reply = (MPI2_EVENT_NOTIFICATION_REPLY *)cm->cm_reply; 2790 if ((reply == NULL) || 2791 (reply->IOCStatus & MPI2_IOCSTATUS_MASK) != MPI2_IOCSTATUS_SUCCESS) 2792 error = ENXIO; 2793 2794 if (reply) 2795 MPR_DPRINT_EVENT(sc, generic, reply); 2796 2797 mpr_dprint(sc, MPR_TRACE, "%s finished error %d\n", __func__, error); 2798 2799 if (cm != NULL) 2800 mpr_free_command(sc, cm); 2801 return (error); 2802 } 2803 2804 static int 2805 mpr_reregister_events(struct mpr_softc *sc) 2806 { 2807 MPI2_EVENT_NOTIFICATION_REQUEST *evtreq; 2808 struct mpr_command *cm; 2809 struct mpr_event_handle *eh; 2810 int error, i; 2811 2812 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2813 2814 /* first, reregister events */ 2815 2816 memset(sc->event_mask, 0xff, 16); 2817 2818 TAILQ_FOREACH(eh, &sc->event_list, eh_list) { 2819 for (i = 0; i < 16; i++) 2820 sc->event_mask[i] &= ~eh->mask[i]; 2821 } 2822 2823 if ((cm = mpr_alloc_command(sc)) == NULL) 2824 return (EBUSY); 2825 evtreq = (MPI2_EVENT_NOTIFICATION_REQUEST *)cm->cm_req; 2826 evtreq->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 2827 evtreq->MsgFlags = 0; 2828 evtreq->SASBroadcastPrimitiveMasks = 0; 2829 #ifdef MPR_DEBUG_ALL_EVENTS 2830 { 2831 u_char fullmask[sizeof(evtreq->EventMasks)]; 2832 memset(fullmask, 0x00, sizeof(fullmask)); 2833 bcopy(fullmask, (uint8_t *)&evtreq->EventMasks, sizeof(fullmask)); 2834 } 2835 #else 2836 bcopy(sc->event_mask, (uint8_t *)&evtreq->EventMasks, sizeof(sc->event_mask)); 2837 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 2838 evtreq->EventMasks[i] = htole32(evtreq->EventMasks[i]); 2839 #endif 2840 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 2841 cm->cm_data = NULL; 2842 cm->cm_complete = mpr_reregister_events_complete; 2843 2844 error = mpr_map_command(sc, cm); 2845 2846 mpr_dprint(sc, MPR_TRACE, "%s finished with error %d\n", __func__, 2847 error); 2848 return (error); 2849 } 2850 2851 int 2852 mpr_deregister_events(struct mpr_softc *sc, struct mpr_event_handle *handle) 2853 { 2854 2855 TAILQ_REMOVE(&sc->event_list, handle, eh_list); 2856 free(handle, M_MPR); 2857 return (mpr_update_events(sc, NULL, NULL)); 2858 } 2859 2860 /** 2861 * mpr_build_nvme_prp - This function is called for NVMe end devices to build a 2862 * native SGL (NVMe PRP). The native SGL is built starting in the first PRP entry 2863 * of the NVMe message (PRP1). If the data buffer is small enough to be described 2864 * entirely using PRP1, then PRP2 is not used. If needed, PRP2 is used to 2865 * describe a larger data buffer. If the data buffer is too large to describe 2866 * using the two PRP entriess inside the NVMe message, then PRP1 describes the 2867 * first data memory segment, and PRP2 contains a pointer to a PRP list located 2868 * elsewhere in memory to describe the remaining data memory segments. The PRP 2869 * list will be contiguous. 2870 2871 * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP 2872 * consists of a list of PRP entries to describe a number of noncontigous 2873 * physical memory segments as a single memory buffer, just as a SGL does. Note 2874 * however, that this function is only used by the IOCTL call, so the memory 2875 * given will be guaranteed to be contiguous. There is no need to translate 2876 * non-contiguous SGL into a PRP in this case. All PRPs will describe contiguous 2877 * space that is one page size each. 2878 * 2879 * Each NVMe message contains two PRP entries. The first (PRP1) either contains 2880 * a PRP list pointer or a PRP element, depending upon the command. PRP2 contains 2881 * the second PRP element if the memory being described fits within 2 PRP 2882 * entries, or a PRP list pointer if the PRP spans more than two entries. 2883 * 2884 * A PRP list pointer contains the address of a PRP list, structured as a linear 2885 * array of PRP entries. Each PRP entry in this list describes a segment of 2886 * physical memory. 2887 * 2888 * Each 64-bit PRP entry comprises an address and an offset field. The address 2889 * always points to the beginning of a PAGE_SIZE physical memory page, and the 2890 * offset describes where within that page the memory segment begins. Only the 2891 * first element in a PRP list may contain a non-zero offest, implying that all 2892 * memory segments following the first begin at the start of a PAGE_SIZE page. 2893 * 2894 * Each PRP element normally describes a chunck of PAGE_SIZE physical memory, 2895 * with exceptions for the first and last elements in the list. If the memory 2896 * being described by the list begins at a non-zero offset within the first page, 2897 * then the first PRP element will contain a non-zero offset indicating where the 2898 * region begins within the page. The last memory segment may end before the end 2899 * of the PAGE_SIZE segment, depending upon the overall size of the memory being 2900 * described by the PRP list. 2901 * 2902 * Since PRP entries lack any indication of size, the overall data buffer length 2903 * is used to determine where the end of the data memory buffer is located, and 2904 * how many PRP entries are required to describe it. 2905 * 2906 * Returns nothing. 2907 */ 2908 void 2909 mpr_build_nvme_prp(struct mpr_softc *sc, struct mpr_command *cm, 2910 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, void *data, 2911 uint32_t data_in_sz, uint32_t data_out_sz) 2912 { 2913 int prp_size = PRP_ENTRY_SIZE; 2914 uint64_t *prp_entry, *prp1_entry, *prp2_entry; 2915 uint64_t *prp_entry_phys, *prp_page, *prp_page_phys; 2916 uint32_t offset, entry_len, page_mask_result, page_mask; 2917 bus_addr_t paddr; 2918 size_t length; 2919 struct mpr_prp_page *prp_page_info = NULL; 2920 2921 /* 2922 * Not all commands require a data transfer. If no data, just return 2923 * without constructing any PRP. 2924 */ 2925 if (!data_in_sz && !data_out_sz) 2926 return; 2927 2928 /* 2929 * Set pointers to PRP1 and PRP2, which are in the NVMe command. PRP1 is 2930 * located at a 24 byte offset from the start of the NVMe command. Then 2931 * set the current PRP entry pointer to PRP1. 2932 */ 2933 prp1_entry = (uint64_t *)(nvme_encap_request->NVMe_Command + 2934 NVME_CMD_PRP1_OFFSET); 2935 prp2_entry = (uint64_t *)(nvme_encap_request->NVMe_Command + 2936 NVME_CMD_PRP2_OFFSET); 2937 prp_entry = prp1_entry; 2938 2939 /* 2940 * For the PRP entries, use the specially allocated buffer of 2941 * contiguous memory. PRP Page allocation failures should not happen 2942 * because there should be enough PRP page buffers to account for the 2943 * possible NVMe QDepth. 2944 */ 2945 prp_page_info = mpr_alloc_prp_page(sc); 2946 KASSERT(prp_page_info != NULL, ("%s: There are no PRP Pages left to be " 2947 "used for building a native NVMe SGL.\n", __func__)); 2948 prp_page = (uint64_t *)prp_page_info->prp_page; 2949 prp_page_phys = (uint64_t *)(uintptr_t)prp_page_info->prp_page_busaddr; 2950 2951 /* 2952 * Insert the allocated PRP page into the command's PRP page list. This 2953 * will be freed when the command is freed. 2954 */ 2955 TAILQ_INSERT_TAIL(&cm->cm_prp_page_list, prp_page_info, prp_page_link); 2956 2957 /* 2958 * Check if we are within 1 entry of a page boundary we don't want our 2959 * first entry to be a PRP List entry. 2960 */ 2961 page_mask = PAGE_SIZE - 1; 2962 page_mask_result = (uintptr_t)((uint8_t *)prp_page + prp_size) & 2963 page_mask; 2964 if (!page_mask_result) 2965 { 2966 /* Bump up to next page boundary. */ 2967 prp_page = (uint64_t *)((uint8_t *)prp_page + prp_size); 2968 prp_page_phys = (uint64_t *)((uint8_t *)prp_page_phys + 2969 prp_size); 2970 } 2971 2972 /* 2973 * Set PRP physical pointer, which initially points to the current PRP 2974 * DMA memory page. 2975 */ 2976 prp_entry_phys = prp_page_phys; 2977 2978 /* Get physical address and length of the data buffer. */ 2979 paddr = (bus_addr_t)(uintptr_t)data; 2980 if (data_in_sz) 2981 length = data_in_sz; 2982 else 2983 length = data_out_sz; 2984 2985 /* Loop while the length is not zero. */ 2986 while (length) 2987 { 2988 /* 2989 * Check if we need to put a list pointer here if we are at page 2990 * boundary - prp_size (8 bytes). 2991 */ 2992 page_mask_result = (uintptr_t)((uint8_t *)prp_entry_phys + 2993 prp_size) & page_mask; 2994 if (!page_mask_result) 2995 { 2996 /* 2997 * This is the last entry in a PRP List, so we need to 2998 * put a PRP list pointer here. What this does is: 2999 * - bump the current memory pointer to the next 3000 * address, which will be the next full page. 3001 * - set the PRP Entry to point to that page. This is 3002 * now the PRP List pointer. 3003 * - bump the PRP Entry pointer the start of the next 3004 * page. Since all of this PRP memory is contiguous, 3005 * no need to get a new page - it's just the next 3006 * address. 3007 */ 3008 prp_entry_phys++; 3009 *prp_entry = 3010 htole64((uint64_t)(uintptr_t)prp_entry_phys); 3011 prp_entry++; 3012 } 3013 3014 /* Need to handle if entry will be part of a page. */ 3015 offset = (uint32_t)paddr & page_mask; 3016 entry_len = PAGE_SIZE - offset; 3017 3018 if (prp_entry == prp1_entry) 3019 { 3020 /* 3021 * Must fill in the first PRP pointer (PRP1) before 3022 * moving on. 3023 */ 3024 *prp1_entry = htole64((uint64_t)paddr); 3025 3026 /* 3027 * Now point to the second PRP entry within the 3028 * command (PRP2). 3029 */ 3030 prp_entry = prp2_entry; 3031 } 3032 else if (prp_entry == prp2_entry) 3033 { 3034 /* 3035 * Should the PRP2 entry be a PRP List pointer or just a 3036 * regular PRP pointer? If there is more than one more 3037 * page of data, must use a PRP List pointer. 3038 */ 3039 if (length > PAGE_SIZE) 3040 { 3041 /* 3042 * PRP2 will contain a PRP List pointer because 3043 * more PRP's are needed with this command. The 3044 * list will start at the beginning of the 3045 * contiguous buffer. 3046 */ 3047 *prp2_entry = 3048 htole64( 3049 (uint64_t)(uintptr_t)prp_entry_phys); 3050 3051 /* 3052 * The next PRP Entry will be the start of the 3053 * first PRP List. 3054 */ 3055 prp_entry = prp_page; 3056 } 3057 else 3058 { 3059 /* 3060 * After this, the PRP Entries are complete. 3061 * This command uses 2 PRP's and no PRP list. 3062 */ 3063 *prp2_entry = htole64((uint64_t)paddr); 3064 } 3065 } 3066 else 3067 { 3068 /* 3069 * Put entry in list and bump the addresses. 3070 * 3071 * After PRP1 and PRP2 are filled in, this will fill in 3072 * all remaining PRP entries in a PRP List, one per each 3073 * time through the loop. 3074 */ 3075 *prp_entry = htole64((uint64_t)paddr); 3076 prp_entry++; 3077 prp_entry_phys++; 3078 } 3079 3080 /* 3081 * Bump the phys address of the command's data buffer by the 3082 * entry_len. 3083 */ 3084 paddr += entry_len; 3085 3086 /* Decrement length accounting for last partial page. */ 3087 if (entry_len > length) 3088 length = 0; 3089 else 3090 length -= entry_len; 3091 } 3092 } 3093 3094 /* 3095 * mpr_check_pcie_native_sgl - This function is called for PCIe end devices to 3096 * determine if the driver needs to build a native SGL. If so, that native SGL 3097 * is built in the contiguous buffers allocated especially for PCIe SGL 3098 * creation. If the driver will not build a native SGL, return TRUE and a 3099 * normal IEEE SGL will be built. Currently this routine supports NVMe devices 3100 * only. 3101 * 3102 * Returns FALSE (0) if native SGL was built, TRUE (1) if no SGL was built. 3103 */ 3104 static int 3105 mpr_check_pcie_native_sgl(struct mpr_softc *sc, struct mpr_command *cm, 3106 bus_dma_segment_t *segs, int segs_left) 3107 { 3108 uint32_t i, sge_dwords, length, offset, entry_len; 3109 uint32_t num_entries, buff_len = 0, sges_in_segment; 3110 uint32_t page_mask, page_mask_result, *curr_buff; 3111 uint32_t *ptr_sgl, *ptr_first_sgl, first_page_offset; 3112 uint32_t first_page_data_size, end_residual; 3113 uint64_t *msg_phys; 3114 bus_addr_t paddr; 3115 int build_native_sgl = 0, first_prp_entry; 3116 int prp_size = PRP_ENTRY_SIZE; 3117 Mpi25IeeeSgeChain64_t *main_chain_element = NULL; 3118 struct mpr_prp_page *prp_page_info = NULL; 3119 3120 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 3121 3122 /* 3123 * Add up the sizes of each segment length to get the total transfer 3124 * size, which will be checked against the Maximum Data Transfer Size. 3125 * If the data transfer length exceeds the MDTS for this device, just 3126 * return 1 so a normal IEEE SGL will be built. F/W will break the I/O 3127 * up into multiple I/O's. [nvme_mdts = 0 means unlimited] 3128 */ 3129 for (i = 0; i < segs_left; i++) 3130 buff_len += htole32(segs[i].ds_len); 3131 if ((cm->cm_targ->MDTS > 0) && (buff_len > cm->cm_targ->MDTS)) 3132 return 1; 3133 3134 /* Create page_mask (to get offset within page) */ 3135 page_mask = PAGE_SIZE - 1; 3136 3137 /* 3138 * Check if the number of elements exceeds the max number that can be 3139 * put in the main message frame (H/W can only translate an SGL that 3140 * is contained entirely in the main message frame). 3141 */ 3142 sges_in_segment = (sc->reqframesz - 3143 offsetof(Mpi25SCSIIORequest_t, SGL)) / sizeof(MPI25_SGE_IO_UNION); 3144 if (segs_left > sges_in_segment) 3145 build_native_sgl = 1; 3146 else 3147 { 3148 /* 3149 * NVMe uses one PRP for each physical page (or part of physical 3150 * page). 3151 * if 4 pages or less then IEEE is OK 3152 * if > 5 pages then we need to build a native SGL 3153 * if > 4 and <= 5 pages, then check the physical address of 3154 * the first SG entry, then if this first size in the page 3155 * is >= the residual beyond 4 pages then use IEEE, 3156 * otherwise use native SGL 3157 */ 3158 if (buff_len > (PAGE_SIZE * 5)) 3159 build_native_sgl = 1; 3160 else if ((buff_len > (PAGE_SIZE * 4)) && 3161 (buff_len <= (PAGE_SIZE * 5)) ) 3162 { 3163 msg_phys = (uint64_t *)(uintptr_t)segs[0].ds_addr; 3164 first_page_offset = 3165 ((uint32_t)(uint64_t)(uintptr_t)msg_phys & 3166 page_mask); 3167 first_page_data_size = PAGE_SIZE - first_page_offset; 3168 end_residual = buff_len % PAGE_SIZE; 3169 3170 /* 3171 * If offset into first page pushes the end of the data 3172 * beyond end of the 5th page, we need the extra PRP 3173 * list. 3174 */ 3175 if (first_page_data_size < end_residual) 3176 build_native_sgl = 1; 3177 3178 /* 3179 * Check if first SG entry size is < residual beyond 4 3180 * pages. 3181 */ 3182 if (htole32(segs[0].ds_len) < 3183 (buff_len - (PAGE_SIZE * 4))) 3184 build_native_sgl = 1; 3185 } 3186 } 3187 3188 /* check if native SGL is needed */ 3189 if (!build_native_sgl) 3190 return 1; 3191 3192 /* 3193 * Native SGL is needed. 3194 * Put a chain element in main message frame that points to the first 3195 * chain buffer. 3196 * 3197 * NOTE: The ChainOffset field must be 0 when using a chain pointer to 3198 * a native SGL. 3199 */ 3200 3201 /* Set main message chain element pointer */ 3202 main_chain_element = (pMpi25IeeeSgeChain64_t)cm->cm_sge; 3203 3204 /* 3205 * For NVMe the chain element needs to be the 2nd SGL entry in the main 3206 * message. 3207 */ 3208 main_chain_element = (Mpi25IeeeSgeChain64_t *) 3209 ((uint8_t *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64)); 3210 3211 /* 3212 * For the PRP entries, use the specially allocated buffer of 3213 * contiguous memory. PRP Page allocation failures should not happen 3214 * because there should be enough PRP page buffers to account for the 3215 * possible NVMe QDepth. 3216 */ 3217 prp_page_info = mpr_alloc_prp_page(sc); 3218 KASSERT(prp_page_info != NULL, ("%s: There are no PRP Pages left to be " 3219 "used for building a native NVMe SGL.\n", __func__)); 3220 curr_buff = (uint32_t *)prp_page_info->prp_page; 3221 msg_phys = (uint64_t *)(uintptr_t)prp_page_info->prp_page_busaddr; 3222 3223 /* 3224 * Insert the allocated PRP page into the command's PRP page list. This 3225 * will be freed when the command is freed. 3226 */ 3227 TAILQ_INSERT_TAIL(&cm->cm_prp_page_list, prp_page_info, prp_page_link); 3228 3229 /* 3230 * Check if we are within 1 entry of a page boundary we don't want our 3231 * first entry to be a PRP List entry. 3232 */ 3233 page_mask_result = (uintptr_t)((uint8_t *)curr_buff + prp_size) & 3234 page_mask; 3235 if (!page_mask_result) { 3236 /* Bump up to next page boundary. */ 3237 curr_buff = (uint32_t *)((uint8_t *)curr_buff + prp_size); 3238 msg_phys = (uint64_t *)((uint8_t *)msg_phys + prp_size); 3239 } 3240 3241 /* Fill in the chain element and make it an NVMe segment type. */ 3242 main_chain_element->Address.High = 3243 htole32((uint32_t)((uint64_t)(uintptr_t)msg_phys >> 32)); 3244 main_chain_element->Address.Low = 3245 htole32((uint32_t)(uintptr_t)msg_phys); 3246 main_chain_element->NextChainOffset = 0; 3247 main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 3248 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 3249 MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP; 3250 3251 /* Set SGL pointer to start of contiguous PCIe buffer. */ 3252 ptr_sgl = curr_buff; 3253 sge_dwords = 2; 3254 num_entries = 0; 3255 3256 /* 3257 * NVMe has a very convoluted PRP format. One PRP is required for each 3258 * page or partial page. We need to split up OS SG entries if they are 3259 * longer than one page or cross a page boundary. We also have to insert 3260 * a PRP list pointer entry as the last entry in each physical page of 3261 * the PRP list. 3262 * 3263 * NOTE: The first PRP "entry" is actually placed in the first SGL entry 3264 * in the main message in IEEE 64 format. The 2nd entry in the main 3265 * message is the chain element, and the rest of the PRP entries are 3266 * built in the contiguous PCIe buffer. 3267 */ 3268 first_prp_entry = 1; 3269 ptr_first_sgl = (uint32_t *)cm->cm_sge; 3270 3271 for (i = 0; i < segs_left; i++) { 3272 /* Get physical address and length of this SG entry. */ 3273 paddr = segs[i].ds_addr; 3274 length = segs[i].ds_len; 3275 3276 /* 3277 * Check whether a given SGE buffer lies on a non-PAGED 3278 * boundary if this is not the first page. If so, this is not 3279 * expected so have FW build the SGL. 3280 */ 3281 if ((i != 0) && (((uint32_t)paddr & page_mask) != 0)) { 3282 mpr_dprint(sc, MPR_ERROR, "Unaligned SGE while " 3283 "building NVMe PRPs, low address is 0x%x\n", 3284 (uint32_t)paddr); 3285 return 1; 3286 } 3287 3288 /* Apart from last SGE, if any other SGE boundary is not page 3289 * aligned then it means that hole exists. Existence of hole 3290 * leads to data corruption. So fallback to IEEE SGEs. 3291 */ 3292 if (i != (segs_left - 1)) { 3293 if (((uint32_t)paddr + length) & page_mask) { 3294 mpr_dprint(sc, MPR_ERROR, "Unaligned SGE " 3295 "boundary while building NVMe PRPs, low " 3296 "address: 0x%x and length: %u\n", 3297 (uint32_t)paddr, length); 3298 return 1; 3299 } 3300 } 3301 3302 /* Loop while the length is not zero. */ 3303 while (length) { 3304 /* 3305 * Check if we need to put a list pointer here if we are 3306 * at page boundary - prp_size. 3307 */ 3308 page_mask_result = (uintptr_t)((uint8_t *)ptr_sgl + 3309 prp_size) & page_mask; 3310 if (!page_mask_result) { 3311 /* 3312 * Need to put a PRP list pointer here. 3313 */ 3314 msg_phys = (uint64_t *)((uint8_t *)msg_phys + 3315 prp_size); 3316 *ptr_sgl = htole32((uintptr_t)msg_phys); 3317 *(ptr_sgl+1) = htole32((uint64_t)(uintptr_t) 3318 msg_phys >> 32); 3319 ptr_sgl += sge_dwords; 3320 num_entries++; 3321 } 3322 3323 /* Need to handle if entry will be part of a page. */ 3324 offset = (uint32_t)paddr & page_mask; 3325 entry_len = PAGE_SIZE - offset; 3326 if (first_prp_entry) { 3327 /* 3328 * Put IEEE entry in first SGE in main message. 3329 * (Simple element, System addr, not end of 3330 * list.) 3331 */ 3332 *ptr_first_sgl = htole32((uint32_t)paddr); 3333 *(ptr_first_sgl + 1) = 3334 htole32((uint32_t)((uint64_t)paddr >> 32)); 3335 *(ptr_first_sgl + 2) = htole32(entry_len); 3336 *(ptr_first_sgl + 3) = 0; 3337 3338 /* No longer the first PRP entry. */ 3339 first_prp_entry = 0; 3340 } else { 3341 /* Put entry in list. */ 3342 *ptr_sgl = htole32((uint32_t)paddr); 3343 *(ptr_sgl + 1) = 3344 htole32((uint32_t)((uint64_t)paddr >> 32)); 3345 3346 /* Bump ptr_sgl, msg_phys, and num_entries. */ 3347 ptr_sgl += sge_dwords; 3348 msg_phys = (uint64_t *)((uint8_t *)msg_phys + 3349 prp_size); 3350 num_entries++; 3351 } 3352 3353 /* Bump the phys address by the entry_len. */ 3354 paddr += entry_len; 3355 3356 /* Decrement length accounting for last partial page. */ 3357 if (entry_len > length) 3358 length = 0; 3359 else 3360 length -= entry_len; 3361 } 3362 } 3363 3364 /* Set chain element Length. */ 3365 main_chain_element->Length = htole32(num_entries * prp_size); 3366 3367 /* Return 0, indicating we built a native SGL. */ 3368 return 0; 3369 } 3370 3371 /* 3372 * Add a chain element as the next SGE for the specified command. 3373 * Reset cm_sge and cm_sgesize to indicate all the available space. Chains are 3374 * only required for IEEE commands. Therefore there is no code for commands 3375 * that have the MPR_CM_FLAGS_SGE_SIMPLE flag set (and those commands 3376 * shouldn't be requesting chains). 3377 */ 3378 static int 3379 mpr_add_chain(struct mpr_command *cm, int segsleft) 3380 { 3381 struct mpr_softc *sc = cm->cm_sc; 3382 MPI2_REQUEST_HEADER *req; 3383 MPI25_IEEE_SGE_CHAIN64 *ieee_sgc; 3384 struct mpr_chain *chain; 3385 int sgc_size, current_segs, rem_segs, segs_per_frame; 3386 uint8_t next_chain_offset = 0; 3387 3388 /* 3389 * Fail if a command is requesting a chain for SIMPLE SGE's. For SAS3 3390 * only IEEE commands should be requesting chains. Return some error 3391 * code other than 0. 3392 */ 3393 if (cm->cm_flags & MPR_CM_FLAGS_SGE_SIMPLE) { 3394 mpr_dprint(sc, MPR_ERROR, "A chain element cannot be added to " 3395 "an MPI SGL.\n"); 3396 return(ENOBUFS); 3397 } 3398 3399 sgc_size = sizeof(MPI25_IEEE_SGE_CHAIN64); 3400 if (cm->cm_sglsize < sgc_size) 3401 panic("MPR: Need SGE Error Code\n"); 3402 3403 chain = mpr_alloc_chain(cm->cm_sc); 3404 if (chain == NULL) 3405 return (ENOBUFS); 3406 3407 /* 3408 * Note: a double-linked list is used to make it easier to walk for 3409 * debugging. 3410 */ 3411 TAILQ_INSERT_TAIL(&cm->cm_chain_list, chain, chain_link); 3412 3413 /* 3414 * Need to know if the number of frames left is more than 1 or not. If 3415 * more than 1 frame is required, NextChainOffset will need to be set, 3416 * which will just be the last segment of the frame. 3417 */ 3418 rem_segs = 0; 3419 if (cm->cm_sglsize < (sgc_size * segsleft)) { 3420 /* 3421 * rem_segs is the number of segment remaining after the 3422 * segments that will go into the current frame. Since it is 3423 * known that at least one more frame is required, account for 3424 * the chain element. To know if more than one more frame is 3425 * required, just check if there will be a remainder after using 3426 * the current frame (with this chain) and the next frame. If 3427 * so the NextChainOffset must be the last element of the next 3428 * frame. 3429 */ 3430 current_segs = (cm->cm_sglsize / sgc_size) - 1; 3431 rem_segs = segsleft - current_segs; 3432 segs_per_frame = sc->chain_frame_size / sgc_size; 3433 if (rem_segs > segs_per_frame) { 3434 next_chain_offset = segs_per_frame - 1; 3435 } 3436 } 3437 ieee_sgc = &((MPI25_SGE_IO_UNION *)cm->cm_sge)->IeeeChain; 3438 ieee_sgc->Length = next_chain_offset ? 3439 htole32((uint32_t)sc->chain_frame_size) : 3440 htole32((uint32_t)rem_segs * (uint32_t)sgc_size); 3441 ieee_sgc->NextChainOffset = next_chain_offset; 3442 ieee_sgc->Flags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 3443 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 3444 ieee_sgc->Address.Low = htole32(chain->chain_busaddr); 3445 ieee_sgc->Address.High = htole32(chain->chain_busaddr >> 32); 3446 cm->cm_sge = &((MPI25_SGE_IO_UNION *)chain->chain)->IeeeSimple; 3447 req = (MPI2_REQUEST_HEADER *)cm->cm_req; 3448 req->ChainOffset = (sc->chain_frame_size - sgc_size) >> 4; 3449 3450 cm->cm_sglsize = sc->chain_frame_size; 3451 return (0); 3452 } 3453 3454 /* 3455 * Add one scatter-gather element to the scatter-gather list for a command. 3456 * Maintain cm_sglsize and cm_sge as the remaining size and pointer to the 3457 * next SGE to fill in, respectively. In Gen3, the MPI SGL does not have a 3458 * chain, so don't consider any chain additions. 3459 */ 3460 int 3461 mpr_push_sge(struct mpr_command *cm, MPI2_SGE_SIMPLE64 *sge, size_t len, 3462 int segsleft) 3463 { 3464 uint32_t saved_buf_len, saved_address_low, saved_address_high; 3465 u32 sge_flags; 3466 3467 /* 3468 * case 1: >=1 more segment, no room for anything (error) 3469 * case 2: 1 more segment and enough room for it 3470 */ 3471 3472 if (cm->cm_sglsize < (segsleft * sizeof(MPI2_SGE_SIMPLE64))) { 3473 mpr_dprint(cm->cm_sc, MPR_ERROR, 3474 "%s: warning: Not enough room for MPI SGL in frame.\n", 3475 __func__); 3476 return(ENOBUFS); 3477 } 3478 3479 KASSERT(segsleft == 1, 3480 ("segsleft cannot be more than 1 for an MPI SGL; segsleft = %d\n", 3481 segsleft)); 3482 3483 /* 3484 * There is one more segment left to add for the MPI SGL and there is 3485 * enough room in the frame to add it. This is the normal case because 3486 * MPI SGL's don't have chains, otherwise something is wrong. 3487 * 3488 * If this is a bi-directional request, need to account for that 3489 * here. Save the pre-filled sge values. These will be used 3490 * either for the 2nd SGL or for a single direction SGL. If 3491 * cm_out_len is non-zero, this is a bi-directional request, so 3492 * fill in the OUT SGL first, then the IN SGL, otherwise just 3493 * fill in the IN SGL. Note that at this time, when filling in 3494 * 2 SGL's for a bi-directional request, they both use the same 3495 * DMA buffer (same cm command). 3496 */ 3497 saved_buf_len = sge->FlagsLength & 0x00FFFFFF; 3498 saved_address_low = sge->Address.Low; 3499 saved_address_high = sge->Address.High; 3500 if (cm->cm_out_len) { 3501 sge->FlagsLength = cm->cm_out_len | 3502 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 3503 MPI2_SGE_FLAGS_END_OF_BUFFER | 3504 MPI2_SGE_FLAGS_HOST_TO_IOC | 3505 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 3506 MPI2_SGE_FLAGS_SHIFT); 3507 cm->cm_sglsize -= len; 3508 /* Endian Safe code */ 3509 sge_flags = sge->FlagsLength; 3510 sge->FlagsLength = htole32(sge_flags); 3511 bcopy(sge, cm->cm_sge, len); 3512 cm->cm_sge = (MPI2_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + len); 3513 } 3514 sge->FlagsLength = saved_buf_len | 3515 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 3516 MPI2_SGE_FLAGS_END_OF_BUFFER | 3517 MPI2_SGE_FLAGS_LAST_ELEMENT | 3518 MPI2_SGE_FLAGS_END_OF_LIST | 3519 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 3520 MPI2_SGE_FLAGS_SHIFT); 3521 if (cm->cm_flags & MPR_CM_FLAGS_DATAIN) { 3522 sge->FlagsLength |= 3523 ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) << 3524 MPI2_SGE_FLAGS_SHIFT); 3525 } else { 3526 sge->FlagsLength |= 3527 ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) << 3528 MPI2_SGE_FLAGS_SHIFT); 3529 } 3530 sge->Address.Low = saved_address_low; 3531 sge->Address.High = saved_address_high; 3532 3533 cm->cm_sglsize -= len; 3534 /* Endian Safe code */ 3535 sge_flags = sge->FlagsLength; 3536 sge->FlagsLength = htole32(sge_flags); 3537 bcopy(sge, cm->cm_sge, len); 3538 cm->cm_sge = (MPI2_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + len); 3539 return (0); 3540 } 3541 3542 /* 3543 * Add one IEEE scatter-gather element (chain or simple) to the IEEE scatter- 3544 * gather list for a command. Maintain cm_sglsize and cm_sge as the 3545 * remaining size and pointer to the next SGE to fill in, respectively. 3546 */ 3547 int 3548 mpr_push_ieee_sge(struct mpr_command *cm, void *sgep, int segsleft) 3549 { 3550 MPI2_IEEE_SGE_SIMPLE64 *sge = sgep; 3551 int error, ieee_sge_size = sizeof(MPI25_SGE_IO_UNION); 3552 uint32_t saved_buf_len, saved_address_low, saved_address_high; 3553 uint32_t sge_length; 3554 3555 /* 3556 * case 1: No room for chain or segment (error). 3557 * case 2: Two or more segments left but only room for chain. 3558 * case 3: Last segment and room for it, so set flags. 3559 */ 3560 3561 /* 3562 * There should be room for at least one element, or there is a big 3563 * problem. 3564 */ 3565 if (cm->cm_sglsize < ieee_sge_size) 3566 panic("MPR: Need SGE Error Code\n"); 3567 3568 if ((segsleft >= 2) && (cm->cm_sglsize < (ieee_sge_size * 2))) { 3569 if ((error = mpr_add_chain(cm, segsleft)) != 0) 3570 return (error); 3571 } 3572 3573 if (segsleft == 1) { 3574 /* 3575 * If this is a bi-directional request, need to account for that 3576 * here. Save the pre-filled sge values. These will be used 3577 * either for the 2nd SGL or for a single direction SGL. If 3578 * cm_out_len is non-zero, this is a bi-directional request, so 3579 * fill in the OUT SGL first, then the IN SGL, otherwise just 3580 * fill in the IN SGL. Note that at this time, when filling in 3581 * 2 SGL's for a bi-directional request, they both use the same 3582 * DMA buffer (same cm command). 3583 */ 3584 saved_buf_len = sge->Length; 3585 saved_address_low = sge->Address.Low; 3586 saved_address_high = sge->Address.High; 3587 if (cm->cm_out_len) { 3588 sge->Length = cm->cm_out_len; 3589 sge->Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 3590 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 3591 cm->cm_sglsize -= ieee_sge_size; 3592 /* Endian Safe code */ 3593 sge_length = sge->Length; 3594 sge->Length = htole32(sge_length); 3595 bcopy(sgep, cm->cm_sge, ieee_sge_size); 3596 cm->cm_sge = 3597 (MPI25_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + 3598 ieee_sge_size); 3599 } 3600 sge->Length = saved_buf_len; 3601 sge->Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 3602 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 3603 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 3604 sge->Address.Low = saved_address_low; 3605 sge->Address.High = saved_address_high; 3606 } 3607 3608 cm->cm_sglsize -= ieee_sge_size; 3609 /* Endian Safe code */ 3610 sge_length = sge->Length; 3611 sge->Length = htole32(sge_length); 3612 bcopy(sgep, cm->cm_sge, ieee_sge_size); 3613 cm->cm_sge = (MPI25_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + 3614 ieee_sge_size); 3615 return (0); 3616 } 3617 3618 /* 3619 * Add one dma segment to the scatter-gather list for a command. 3620 */ 3621 int 3622 mpr_add_dmaseg(struct mpr_command *cm, vm_paddr_t pa, size_t len, u_int flags, 3623 int segsleft) 3624 { 3625 MPI2_SGE_SIMPLE64 sge; 3626 MPI2_IEEE_SGE_SIMPLE64 ieee_sge; 3627 3628 if (!(cm->cm_flags & MPR_CM_FLAGS_SGE_SIMPLE)) { 3629 ieee_sge.Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 3630 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 3631 ieee_sge.Length = len; 3632 mpr_from_u64(pa, &ieee_sge.Address); 3633 3634 return (mpr_push_ieee_sge(cm, &ieee_sge, segsleft)); 3635 } else { 3636 /* 3637 * This driver always uses 64-bit address elements for 3638 * simplicity. 3639 */ 3640 flags |= MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 3641 MPI2_SGE_FLAGS_64_BIT_ADDRESSING; 3642 /* Set Endian safe macro in mpr_push_sge */ 3643 sge.FlagsLength = len | (flags << MPI2_SGE_FLAGS_SHIFT); 3644 mpr_from_u64(pa, &sge.Address); 3645 3646 return (mpr_push_sge(cm, &sge, sizeof sge, segsleft)); 3647 } 3648 } 3649 3650 static void 3651 mpr_data_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3652 { 3653 struct mpr_softc *sc; 3654 struct mpr_command *cm; 3655 u_int i, dir, sflags; 3656 3657 cm = (struct mpr_command *)arg; 3658 sc = cm->cm_sc; 3659 3660 /* 3661 * In this case, just print out a warning and let the chip tell the 3662 * user they did the wrong thing. 3663 */ 3664 if ((cm->cm_max_segs != 0) && (nsegs > cm->cm_max_segs)) { 3665 mpr_dprint(sc, MPR_ERROR, "%s: warning: busdma returned %d " 3666 "segments, more than the %d allowed\n", __func__, nsegs, 3667 cm->cm_max_segs); 3668 } 3669 3670 /* 3671 * Set up DMA direction flags. Bi-directional requests are also handled 3672 * here. In that case, both direction flags will be set. 3673 */ 3674 sflags = 0; 3675 if (cm->cm_flags & MPR_CM_FLAGS_SMP_PASS) { 3676 /* 3677 * We have to add a special case for SMP passthrough, there 3678 * is no easy way to generically handle it. The first 3679 * S/G element is used for the command (therefore the 3680 * direction bit needs to be set). The second one is used 3681 * for the reply. We'll leave it to the caller to make 3682 * sure we only have two buffers. 3683 */ 3684 /* 3685 * Even though the busdma man page says it doesn't make 3686 * sense to have both direction flags, it does in this case. 3687 * We have one s/g element being accessed in each direction. 3688 */ 3689 dir = BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD; 3690 3691 /* 3692 * Set the direction flag on the first buffer in the SMP 3693 * passthrough request. We'll clear it for the second one. 3694 */ 3695 sflags |= MPI2_SGE_FLAGS_DIRECTION | 3696 MPI2_SGE_FLAGS_END_OF_BUFFER; 3697 } else if (cm->cm_flags & MPR_CM_FLAGS_DATAOUT) { 3698 sflags |= MPI2_SGE_FLAGS_HOST_TO_IOC; 3699 dir = BUS_DMASYNC_PREWRITE; 3700 } else 3701 dir = BUS_DMASYNC_PREREAD; 3702 3703 /* Check if a native SG list is needed for an NVMe PCIe device. */ 3704 if (cm->cm_targ && cm->cm_targ->is_nvme && 3705 mpr_check_pcie_native_sgl(sc, cm, segs, nsegs) == 0) { 3706 /* A native SG list was built, skip to end. */ 3707 goto out; 3708 } 3709 3710 for (i = 0; i < nsegs; i++) { 3711 if ((cm->cm_flags & MPR_CM_FLAGS_SMP_PASS) && (i != 0)) { 3712 sflags &= ~MPI2_SGE_FLAGS_DIRECTION; 3713 } 3714 error = mpr_add_dmaseg(cm, segs[i].ds_addr, segs[i].ds_len, 3715 sflags, nsegs - i); 3716 if (error != 0) { 3717 /* Resource shortage, roll back! */ 3718 if (ratecheck(&sc->lastfail, &mpr_chainfail_interval)) 3719 mpr_dprint(sc, MPR_INFO, "Out of chain frames, " 3720 "consider increasing hw.mpr.max_chains.\n"); 3721 cm->cm_flags |= MPR_CM_FLAGS_CHAIN_FAILED; 3722 /* 3723 * mpr_complete_command can only be called on commands 3724 * that are in the queue. Since this is an error path 3725 * which gets called before we enqueue, update the state 3726 * to meet this requirement before we complete it. 3727 */ 3728 cm->cm_state = MPR_CM_STATE_INQUEUE; 3729 mpr_complete_command(sc, cm); 3730 return; 3731 } 3732 } 3733 3734 out: 3735 bus_dmamap_sync(sc->buffer_dmat, cm->cm_dmamap, dir); 3736 mpr_enqueue_request(sc, cm); 3737 3738 return; 3739 } 3740 3741 static void 3742 mpr_data_cb2(void *arg, bus_dma_segment_t *segs, int nsegs, bus_size_t mapsize, 3743 int error) 3744 { 3745 mpr_data_cb(arg, segs, nsegs, error); 3746 } 3747 3748 /* 3749 * This is the routine to enqueue commands ansynchronously. 3750 * Note that the only error path here is from bus_dmamap_load(), which can 3751 * return EINPROGRESS if it is waiting for resources. Other than this, it's 3752 * assumed that if you have a command in-hand, then you have enough credits 3753 * to use it. 3754 */ 3755 int 3756 mpr_map_command(struct mpr_softc *sc, struct mpr_command *cm) 3757 { 3758 int error = 0; 3759 3760 if (cm->cm_flags & MPR_CM_FLAGS_USE_UIO) { 3761 error = bus_dmamap_load_uio(sc->buffer_dmat, cm->cm_dmamap, 3762 &cm->cm_uio, mpr_data_cb2, cm, 0); 3763 } else if (cm->cm_flags & MPR_CM_FLAGS_USE_CCB) { 3764 error = bus_dmamap_load_ccb(sc->buffer_dmat, cm->cm_dmamap, 3765 cm->cm_data, mpr_data_cb, cm, 0); 3766 } else if ((cm->cm_data != NULL) && (cm->cm_length != 0)) { 3767 error = bus_dmamap_load(sc->buffer_dmat, cm->cm_dmamap, 3768 cm->cm_data, cm->cm_length, mpr_data_cb, cm, 0); 3769 } else { 3770 /* Add a zero-length element as needed */ 3771 if (cm->cm_sge != NULL) 3772 mpr_add_dmaseg(cm, 0, 0, 0, 1); 3773 mpr_enqueue_request(sc, cm); 3774 } 3775 3776 return (error); 3777 } 3778 3779 /* 3780 * This is the routine to enqueue commands synchronously. An error of 3781 * EINPROGRESS from mpr_map_command() is ignored since the command will 3782 * be executed and enqueued automatically. Other errors come from msleep(). 3783 */ 3784 int 3785 mpr_wait_command(struct mpr_softc *sc, struct mpr_command **cmp, int timeout, 3786 int sleep_flag) 3787 { 3788 int error, rc; 3789 struct timeval cur_time, start_time; 3790 struct mpr_command *cm = *cmp; 3791 3792 if (sc->mpr_flags & MPR_FLAGS_DIAGRESET) 3793 return EBUSY; 3794 3795 cm->cm_complete = NULL; 3796 cm->cm_flags |= (MPR_CM_FLAGS_WAKEUP + MPR_CM_FLAGS_POLLED); 3797 error = mpr_map_command(sc, cm); 3798 if ((error != 0) && (error != EINPROGRESS)) 3799 return (error); 3800 3801 // Check for context and wait for 50 mSec at a time until time has 3802 // expired or the command has finished. If msleep can't be used, need 3803 // to poll. 3804 if (curthread->td_no_sleeping) 3805 sleep_flag = NO_SLEEP; 3806 getmicrouptime(&start_time); 3807 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) { 3808 error = msleep(cm, &sc->mpr_mtx, 0, "mprwait", timeout*hz); 3809 if (error == EWOULDBLOCK) { 3810 /* 3811 * Record the actual elapsed time in the case of a 3812 * timeout for the message below. 3813 */ 3814 getmicrouptime(&cur_time); 3815 timevalsub(&cur_time, &start_time); 3816 } 3817 } else { 3818 while ((cm->cm_flags & MPR_CM_FLAGS_COMPLETE) == 0) { 3819 mpr_intr_locked(sc); 3820 if (sleep_flag == CAN_SLEEP) 3821 pause("mprwait", hz/20); 3822 else 3823 DELAY(50000); 3824 3825 getmicrouptime(&cur_time); 3826 timevalsub(&cur_time, &start_time); 3827 if (cur_time.tv_sec > timeout) { 3828 error = EWOULDBLOCK; 3829 break; 3830 } 3831 } 3832 } 3833 3834 if (error == EWOULDBLOCK) { 3835 if (cm->cm_timeout_handler == NULL) { 3836 mpr_dprint(sc, MPR_FAULT, "Calling Reinit from %s, timeout=%d," 3837 " elapsed=%jd\n", __func__, timeout, 3838 (intmax_t)cur_time.tv_sec); 3839 rc = mpr_reinit(sc); 3840 mpr_dprint(sc, MPR_FAULT, "Reinit %s\n", (rc == 0) ? "success" : 3841 "failed"); 3842 } else 3843 cm->cm_timeout_handler(sc, cm); 3844 if (sc->mpr_flags & MPR_FLAGS_REALLOCATED) { 3845 /* 3846 * Tell the caller that we freed the command in a 3847 * reinit. 3848 */ 3849 *cmp = NULL; 3850 } 3851 error = ETIMEDOUT; 3852 } 3853 return (error); 3854 } 3855 3856 /* 3857 * This is the routine to enqueue a command synchonously and poll for 3858 * completion. Its use should be rare. 3859 */ 3860 int 3861 mpr_request_polled(struct mpr_softc *sc, struct mpr_command **cmp) 3862 { 3863 int error, rc; 3864 struct timeval cur_time, start_time; 3865 struct mpr_command *cm = *cmp; 3866 3867 error = 0; 3868 3869 cm->cm_flags |= MPR_CM_FLAGS_POLLED; 3870 cm->cm_complete = NULL; 3871 mpr_map_command(sc, cm); 3872 3873 getmicrouptime(&start_time); 3874 while ((cm->cm_flags & MPR_CM_FLAGS_COMPLETE) == 0) { 3875 mpr_intr_locked(sc); 3876 3877 if (mtx_owned(&sc->mpr_mtx)) 3878 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, 3879 "mprpoll", hz/20); 3880 else 3881 pause("mprpoll", hz/20); 3882 3883 /* 3884 * Check for real-time timeout and fail if more than 60 seconds. 3885 */ 3886 getmicrouptime(&cur_time); 3887 timevalsub(&cur_time, &start_time); 3888 if (cur_time.tv_sec > 60) { 3889 mpr_dprint(sc, MPR_FAULT, "polling failed\n"); 3890 error = ETIMEDOUT; 3891 break; 3892 } 3893 } 3894 cm->cm_state = MPR_CM_STATE_BUSY; 3895 if (error) { 3896 mpr_dprint(sc, MPR_FAULT, "Calling Reinit from %s\n", __func__); 3897 rc = mpr_reinit(sc); 3898 mpr_dprint(sc, MPR_FAULT, "Reinit %s\n", (rc == 0) ? "success" : 3899 "failed"); 3900 3901 if (sc->mpr_flags & MPR_FLAGS_REALLOCATED) { 3902 /* 3903 * Tell the caller that we freed the command in a 3904 * reinit. 3905 */ 3906 *cmp = NULL; 3907 } 3908 } 3909 return (error); 3910 } 3911 3912 /* 3913 * The MPT driver had a verbose interface for config pages. In this driver, 3914 * reduce it to much simpler terms, similar to the Linux driver. 3915 */ 3916 int 3917 mpr_read_config_page(struct mpr_softc *sc, struct mpr_config_params *params) 3918 { 3919 MPI2_CONFIG_REQUEST *req; 3920 struct mpr_command *cm; 3921 int error; 3922 3923 if (sc->mpr_flags & MPR_FLAGS_BUSY) { 3924 return (EBUSY); 3925 } 3926 3927 cm = mpr_alloc_command(sc); 3928 if (cm == NULL) { 3929 return (EBUSY); 3930 } 3931 3932 req = (MPI2_CONFIG_REQUEST *)cm->cm_req; 3933 req->Function = MPI2_FUNCTION_CONFIG; 3934 req->Action = params->action; 3935 req->SGLFlags = 0; 3936 req->ChainOffset = 0; 3937 req->PageAddress = params->page_address; 3938 if (params->hdr.Struct.PageType == MPI2_CONFIG_PAGETYPE_EXTENDED) { 3939 MPI2_CONFIG_EXTENDED_PAGE_HEADER *hdr; 3940 3941 hdr = ¶ms->hdr.Ext; 3942 req->ExtPageType = hdr->ExtPageType; 3943 req->ExtPageLength = hdr->ExtPageLength; 3944 req->Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; 3945 req->Header.PageLength = 0; /* Must be set to zero */ 3946 req->Header.PageNumber = hdr->PageNumber; 3947 req->Header.PageVersion = hdr->PageVersion; 3948 } else { 3949 MPI2_CONFIG_PAGE_HEADER *hdr; 3950 3951 hdr = ¶ms->hdr.Struct; 3952 req->Header.PageType = hdr->PageType; 3953 req->Header.PageNumber = hdr->PageNumber; 3954 req->Header.PageLength = hdr->PageLength; 3955 req->Header.PageVersion = hdr->PageVersion; 3956 } 3957 3958 cm->cm_data = params->buffer; 3959 cm->cm_length = params->length; 3960 if (cm->cm_data != NULL) { 3961 cm->cm_sge = &req->PageBufferSGE; 3962 cm->cm_sglsize = sizeof(MPI2_SGE_IO_UNION); 3963 cm->cm_flags = MPR_CM_FLAGS_SGE_SIMPLE | MPR_CM_FLAGS_DATAIN; 3964 } else 3965 cm->cm_sge = NULL; 3966 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 3967 3968 cm->cm_complete_data = params; 3969 if (params->callback != NULL) { 3970 cm->cm_complete = mpr_config_complete; 3971 return (mpr_map_command(sc, cm)); 3972 } else { 3973 error = mpr_wait_command(sc, &cm, 0, CAN_SLEEP); 3974 if (error) { 3975 mpr_dprint(sc, MPR_FAULT, 3976 "Error %d reading config page\n", error); 3977 if (cm != NULL) 3978 mpr_free_command(sc, cm); 3979 return (error); 3980 } 3981 mpr_config_complete(sc, cm); 3982 } 3983 3984 return (0); 3985 } 3986 3987 int 3988 mpr_write_config_page(struct mpr_softc *sc, struct mpr_config_params *params) 3989 { 3990 return (EINVAL); 3991 } 3992 3993 static void 3994 mpr_config_complete(struct mpr_softc *sc, struct mpr_command *cm) 3995 { 3996 MPI2_CONFIG_REPLY *reply; 3997 struct mpr_config_params *params; 3998 3999 MPR_FUNCTRACE(sc); 4000 params = cm->cm_complete_data; 4001 4002 if (cm->cm_data != NULL) { 4003 bus_dmamap_sync(sc->buffer_dmat, cm->cm_dmamap, 4004 BUS_DMASYNC_POSTREAD); 4005 bus_dmamap_unload(sc->buffer_dmat, cm->cm_dmamap); 4006 } 4007 4008 /* 4009 * XXX KDM need to do more error recovery? This results in the 4010 * device in question not getting probed. 4011 */ 4012 if ((cm->cm_flags & MPR_CM_FLAGS_ERROR_MASK) != 0) { 4013 params->status = MPI2_IOCSTATUS_BUSY; 4014 goto done; 4015 } 4016 4017 reply = (MPI2_CONFIG_REPLY *)cm->cm_reply; 4018 if (reply == NULL) { 4019 params->status = MPI2_IOCSTATUS_BUSY; 4020 goto done; 4021 } 4022 params->status = reply->IOCStatus; 4023 if (params->hdr.Struct.PageType == MPI2_CONFIG_PAGETYPE_EXTENDED) { 4024 params->hdr.Ext.ExtPageType = reply->ExtPageType; 4025 params->hdr.Ext.ExtPageLength = reply->ExtPageLength; 4026 params->hdr.Ext.PageType = reply->Header.PageType; 4027 params->hdr.Ext.PageNumber = reply->Header.PageNumber; 4028 params->hdr.Ext.PageVersion = reply->Header.PageVersion; 4029 } else { 4030 params->hdr.Struct.PageType = reply->Header.PageType; 4031 params->hdr.Struct.PageNumber = reply->Header.PageNumber; 4032 params->hdr.Struct.PageLength = reply->Header.PageLength; 4033 params->hdr.Struct.PageVersion = reply->Header.PageVersion; 4034 } 4035 4036 done: 4037 mpr_free_command(sc, cm); 4038 if (params->callback != NULL) 4039 params->callback(sc, params); 4040 4041 return; 4042 } 4043