1 /* 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020-2023, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Authors: Sumit Saxena <sumit.saxena@broadcom.com> 8 * Chandrakanth Patil <chandrakanth.patil@broadcom.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are 12 * met: 13 * 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation and/or other 18 * materials provided with the distribution. 19 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 * The views and conclusions contained in the software and documentation are 36 * those of the authors and should not be interpreted as representing 37 * official policies,either expressed or implied, of the FreeBSD Project. 38 * 39 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 40 * 41 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 42 */ 43 44 #ifndef _MPI3MRVAR_H 45 #define _MPI3MRVAR_H 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/module.h> 52 #include <sys/bus.h> 53 #include <sys/conf.h> 54 #include <sys/malloc.h> 55 #include <sys/sysctl.h> 56 #include <sys/uio.h> 57 #include <sys/selinfo.h> 58 #include <sys/poll.h> 59 60 #include <sys/lock.h> 61 #include <sys/mutex.h> 62 #include <sys/endian.h> 63 #include <sys/sysent.h> 64 #include <sys/taskqueue.h> 65 #include <sys/smp.h> 66 67 #include <machine/bus.h> 68 #include <machine/resource.h> 69 #include <sys/rman.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pci_private.h> 74 75 #include <cam/cam.h> 76 #include <cam/cam_ccb.h> 77 #include <cam/cam_debug.h> 78 #include <cam/cam_sim.h> 79 #include <cam/cam_xpt_sim.h> 80 #include <cam/cam_xpt_periph.h> 81 #include <cam/cam_periph.h> 82 #include <cam/scsi/scsi_all.h> 83 #include <cam/scsi/scsi_message.h> 84 85 #include <cam/scsi/smp_all.h> 86 #include <sys/queue.h> 87 #include <sys/kthread.h> 88 #include "mpi/mpi30_api.h" 89 90 #define MPI3MR_DRIVER_VERSION "8.6.0.2.0" 91 #define MPI3MR_DRIVER_RELDATE "17th May 2023" 92 93 #define MPI3MR_DRIVER_NAME "mpi3mr" 94 95 #define MPI3MR_NAME_LENGTH 32 96 #define IOCNAME "%s: " 97 98 #define SAS4116_CHIP_REV_A0 0 99 #define SAS4116_CHIP_REV_B0 1 100 101 #define MPI3MR_SG_DEPTH (MPI3MR_4K_PGSZ/sizeof(Mpi3SGESimple_t)) 102 #define MPI3MR_MAX_SECTORS 2048 103 #define MPI3MR_MAX_CMDS_LUN 7 104 #define MPI3MR_MAX_CDB_LENGTH 16 105 #define MPI3MR_MAX_LUN 16895 106 107 #define MPI3MR_SATA_QDEPTH 32 108 #define MPI3MR_SAS_QDEPTH 64 109 #define MPI3MR_RAID_QDEPTH 128 110 #define MPI3MR_NVME_QDEPTH 128 111 112 #define MPI3MR_4K_PGSZ 4096 113 #define MPI3MR_AREQQ_SIZE (2 * MPI3MR_4K_PGSZ) 114 #define MPI3MR_AREPQ_SIZE (4 * MPI3MR_4K_PGSZ) 115 #define MPI3MR_AREQ_FRAME_SZ 128 116 #define MPI3MR_AREP_FRAME_SZ 16 117 118 #define MPI3MR_OPREQQ_SIZE (8 * MPI3MR_4K_PGSZ) 119 #define MPI3MR_OPREPQ_SIZE (4 * MPI3MR_4K_PGSZ) 120 121 /* Operational queue management definitions */ 122 #define MPI3MR_OP_REQ_Q_QD 512 123 #define MPI3MR_OP_REP_Q_QD 1024 124 #define MPI3MR_OP_REP_Q_QD_A0 4096 125 126 #define MPI3MR_CHAINSGE_SIZE MPI3MR_4K_PGSZ 127 128 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 129 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 130 MPI3_SGE_FLAGS_END_OF_LIST) 131 132 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 133 #define MPI3MR_HOSTTAG_INITCMDS 1 134 #define MPI3MR_HOSTTAG_IOCTLCMDS 2 135 #define MPI3MR_HOSTTAG_PELABORT 3 136 #define MPI3MR_HOSTTAG_PELWAIT 4 137 #define MPI3MR_HOSTTAG_TMS 5 138 139 #define MAX_MGMT_ADAPTERS 8 140 #define MPI3MR_WAIT_BEFORE_CTRL_RESET 5 141 142 143 struct mpi3mr_mgmt_info { 144 uint16_t count; 145 struct mpi3mr_softc *sc_ptr[MAX_MGMT_ADAPTERS]; 146 int max_index; 147 }; 148 149 extern char fmt_os_ver[16]; 150 151 #define MPI3MR_OS_VERSION(raw_os_ver, fmt_os_ver) sprintf(raw_os_ver, "%d", __FreeBSD_version); \ 152 sprintf(fmt_os_ver, "%c%c.%c%c.%c%c%c",\ 153 raw_os_ver[0], raw_os_ver[1], raw_os_ver[2],\ 154 raw_os_ver[3], raw_os_ver[4], raw_os_ver[5],\ 155 raw_os_ver[6]); 156 #define MPI3MR_NUM_DEVRMCMD 1 157 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TMS + 1) 158 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 159 MPI3MR_NUM_DEVRMCMD - 1) 160 #define MPI3MR_INTERNALCMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 161 162 #define MPI3MR_NUM_EVTACKCMD 4 163 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 164 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 165 MPI3MR_NUM_EVTACKCMD - 1) 166 167 /* command/controller interaction timeout definitions in seconds */ 168 #define MPI3MR_INTADMCMD_TIMEOUT 60 169 #define MPI3MR_PORTENABLE_TIMEOUT 300 170 #define MPI3MR_ABORTTM_TIMEOUT 60 171 #define MPI3MR_RESETTM_TIMEOUT 60 172 #define MPI3MR_TSUPDATE_INTERVAL 900 173 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 174 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 175 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 176 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 177 #define MPI3MR_RESET_ACK_TIMEOUT 30 178 #define MPI3MR_MUR_TIMEOUT 120 179 180 #define MPI3MR_CMD_NOTUSED 0x8000 181 #define MPI3MR_CMD_COMPLETE 0x0001 182 #define MPI3MR_CMD_PENDING 0x0002 183 #define MPI3MR_CMD_REPLYVALID 0x0004 184 #define MPI3MR_CMD_RESET 0x0008 185 186 #define MPI3MR_NUM_EVTREPLIES 64 187 #define MPI3MR_SENSEBUF_SZ 256 188 #define MPI3MR_SENSEBUF_FACTOR 3 189 #define MPI3MR_CHAINBUF_FACTOR 3 190 191 #define MPT3SAS_HOSTPGSZ_4KEXP 12 192 193 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 194 195 /* Controller Reset related definitions */ 196 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 197 #define MPI3MR_MAX_SHUTDOWN_RETRY_COUNT 2 198 199 /* ResponseCode values */ 200 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 201 #define MPI3MR_RSP_TM_COMPLETE 0x00 202 #define MPI3MR_RSP_INVALID_FRAME 0x02 203 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04 204 #define MPI3MR_RSP_TM_FAILED 0x05 205 #define MPI3MR_RSP_TM_SUCCEEDED 0x08 206 #define MPI3MR_RSP_TM_INVALID_LUN 0x09 207 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A 208 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 209 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 210 211 /* Definitions for the controller security status*/ 212 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 213 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 214 215 #define MPI3MR_INVALID_DEVICE 0x00 216 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 217 #define MPI3MR_HARD_SECURE_DEVICE 0x08 218 #define MPI3MR_TAMPERED_DEVICE 0x0C 219 220 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 221 #define MPI3MR_DEFAULT_PGSZEXP (12) 222 #define MPI3MR_MAX_IOCTL_TRANSFER_SIZE (1024 * 1024) 223 224 #define MPI3MR_DEVRMHS_RETRYCOUNT 3 225 #define MPI3MR_PELCMDS_RETRYCOUNT 3 226 227 #define MPI3MR_PERIODIC_DELAY 1 /* 1 second heartbeat/watchdog check */ 228 229 struct completion { 230 unsigned int done; 231 struct mtx lock; 232 }; 233 234 typedef union { 235 volatile unsigned int val; 236 unsigned int val_rdonly; 237 } mpi3mr_atomic_t; 238 239 #define mpi3mr_atomic_read(v) atomic_load_acq_int(&(v)->val) 240 #define mpi3mr_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 241 #define mpi3mr_atomic_dec(v) atomic_subtract_int(&(v)->val, 1) 242 #define mpi3mr_atomic_inc(v) atomic_add_int(&(v)->val, 1) 243 #define mpi3mr_atomic_add(v, u) atomic_add_int(&(v)->val, u) 244 #define mpi3mr_atomic_sub(v, u) atomic_subtract_int(&(v)->val, u) 245 246 /* IOCTL data transfer sge*/ 247 #define MPI3MR_NUM_IOCTL_SGE 256 248 #define MPI3MR_IOCTL_SGE_SIZE (8 * 1024) 249 250 struct dma_memory_desc { 251 U32 size; 252 void *addr; 253 bus_dma_tag_t tag; 254 bus_dmamap_t dmamap; 255 bus_addr_t dma_addr; 256 }; 257 258 enum mpi3mr_iocstate { 259 MRIOC_STATE_READY = 1, 260 MRIOC_STATE_RESET, 261 MRIOC_STATE_FAULT, 262 MRIOC_STATE_BECOMING_READY, 263 MRIOC_STATE_RESET_REQUESTED, 264 MRIOC_STATE_UNRECOVERABLE, 265 MRIOC_STATE_COUNT, 266 }; 267 268 /* Init type definitions */ 269 enum mpi3mr_init_type { 270 MPI3MR_INIT_TYPE_INIT = 0, 271 MPI3MR_INIT_TYPE_RESET, 272 MPI3MR_INIT_TYPE_RESUME, 273 }; 274 275 /* Reset reason code definitions*/ 276 enum mpi3mr_reset_reason { 277 MPI3MR_RESET_FROM_BRINGUP = 1, 278 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 279 MPI3MR_RESET_FROM_IOCTL = 3, 280 MPI3MR_RESET_FROM_EH_HOS = 4, 281 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 282 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6, 283 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 284 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 285 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 286 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 287 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 288 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 289 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 290 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 291 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 292 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 293 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 294 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 295 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 296 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 297 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 298 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 299 MPI3MR_RESET_FROM_SYSFS = 23, 300 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 301 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25, 302 MPI3MR_RESET_FROM_SCSIIO_TIMEOUT = 26, 303 MPI3MR_RESET_FROM_FIRMWARE = 27, 304 MPI3MR_DEFAULT_RESET_REASON = 28, 305 MPI3MR_RESET_REASON_COUNT, 306 }; 307 308 struct mpi3mr_compimg_ver 309 { 310 U16 build_num; 311 U16 cust_id; 312 U8 ph_minor; 313 U8 ph_major; 314 U8 gen_minor; 315 U8 gen_major; 316 }; 317 318 struct mpi3mr_ioc_facts 319 { 320 U32 ioc_capabilities; 321 struct mpi3mr_compimg_ver fw_ver; 322 U32 mpi_version; 323 U16 max_reqs; 324 U16 product_id; 325 U16 op_req_sz; 326 U16 reply_sz; 327 U16 exceptions; 328 U16 max_perids; 329 U16 max_pds; 330 U16 max_sasexpanders; 331 U16 max_sasinitiators; 332 U16 max_enclosures; 333 U16 max_pcieswitches; 334 U16 max_nvme; 335 U16 max_vds; 336 U16 max_hpds; 337 U16 max_advhpds; 338 U16 max_raidpds; 339 U16 min_devhandle; 340 U16 max_devhandle; 341 U16 max_op_req_q; 342 U16 max_op_reply_q; 343 U16 shutdown_timeout; 344 U8 ioc_num; 345 U8 who_init; 346 U16 max_msix_vectors; 347 U8 personality; 348 U8 dma_mask; 349 U8 protocol_flags; 350 U8 sge_mod_mask; 351 U8 sge_mod_value; 352 U8 sge_mod_shift; 353 U8 max_dev_per_tg; 354 U16 max_io_throttle_group; 355 U16 io_throttle_data_length; 356 U16 io_throttle_low; 357 U16 io_throttle_high; 358 }; 359 360 struct mpi3mr_op_req_queue { 361 U16 ci; 362 U16 pi; 363 U16 num_reqs; 364 U8 qid; 365 U8 reply_qid; 366 U32 qsz; 367 void *q_base; 368 bus_dma_tag_t q_base_tag; 369 bus_dmamap_t q_base_dmamap; 370 bus_addr_t q_base_phys; 371 struct mtx q_lock; 372 }; 373 374 struct mpi3mr_op_reply_queue { 375 U16 ci; 376 U8 ephase; 377 U8 qid; 378 U16 num_replies; 379 U32 qsz; 380 bus_dma_tag_t q_base_tag; 381 bus_dmamap_t q_base_dmamap; 382 void *q_base; 383 bus_addr_t q_base_phys; 384 mpi3mr_atomic_t pend_ios; 385 bool in_use; 386 struct mtx q_lock; 387 }; 388 389 struct irq_info { 390 MPI3_REPLY_DESCRIPTORS_UNION *post_queue; 391 bus_dma_tag_t buffer_dmat; 392 struct resource *irq; 393 void *intrhand; 394 int irq_rid; 395 }; 396 397 struct mpi3mr_irq_context { 398 struct mpi3mr_softc *sc; 399 U16 msix_index; 400 struct mpi3mr_op_reply_queue *op_reply_q; 401 char name[MPI3MR_NAME_LENGTH]; 402 struct irq_info irq_info; 403 }; 404 405 MALLOC_DECLARE(M_MPI3MR); 406 SYSCTL_DECL(_hw_mpi3mr); 407 408 typedef struct mpi3mr_drvr_cmd DRVR_CMD; 409 typedef void (*DRVR_CMD_CALLBACK)(struct mpi3mr_softc *mrioc, DRVR_CMD *drvrcmd); 410 struct mpi3mr_drvr_cmd { 411 struct mtx lock; 412 struct completion completion; 413 void *reply; 414 U8 *sensebuf; 415 U8 iou_rc; 416 U16 state; 417 U16 dev_handle; 418 U16 ioc_status; 419 U32 ioc_loginfo; 420 U8 is_waiting; 421 U8 is_senseprst; 422 U8 retry_count; 423 U16 host_tag; 424 DRVR_CMD_CALLBACK callback; 425 }; 426 427 struct mpi3mr_cmd; 428 typedef void mpi3mr_evt_callback_t(struct mpi3mr_softc *, uintptr_t, 429 Mpi3EventNotificationReply_t *reply); 430 typedef void mpi3mr_cmd_callback_t(struct mpi3mr_softc *, 431 struct mpi3mr_cmd *cmd); 432 433 #define MPI3MR_IOVEC_COUNT 2 434 435 enum mpi3mr_data_xfer_direction { 436 MPI3MR_READ = 1, 437 MPI3MR_WRITE, 438 }; 439 440 enum mpi3mr_cmd_state { 441 MPI3MR_CMD_STATE_FREE = 1, 442 MPI3MR_CMD_STATE_BUSY, 443 MPI3MR_CMD_STATE_IN_QUEUE, 444 MPI3MR_CMD_STATE_IN_TM, 445 }; 446 447 enum mpi3mr_target_state { 448 MPI3MR_DEV_CREATED = 1, 449 MPI3MR_DEV_REMOVE_HS_STARTED = 2, 450 MPI3MR_DEV_DELETED = 3, 451 }; 452 453 struct mpi3mr_cmd { 454 TAILQ_ENTRY(mpi3mr_cmd) next; 455 struct mpi3mr_softc *sc; 456 union ccb *ccb; 457 void *data; 458 u_int length; 459 struct mpi3mr_target *targ; 460 u_int data_dir; 461 u_int state; 462 bus_dmamap_t dmamap; 463 struct scsi_sense_data *sense; 464 struct callout callout; 465 bool callout_owner; 466 U16 hosttag; 467 U8 req_qidx; 468 Mpi3SCSIIORequest_t io_request; 469 }; 470 471 struct mpi3mr_chain { 472 bus_dmamap_t buf_dmamap; 473 void *buf; 474 bus_addr_t buf_phys; 475 }; 476 477 struct mpi3mr_event_handle { 478 TAILQ_ENTRY(mpi3mr_event_handle) eh_list; 479 mpi3mr_evt_callback_t *callback; 480 void *data; 481 uint8_t mask[16]; 482 }; 483 484 struct mpi3mr_fw_event_work { 485 U16 event; 486 void *event_data; 487 TAILQ_ENTRY(mpi3mr_fw_event_work) ev_link; 488 U8 send_ack; 489 U8 process_event; 490 U32 event_context; 491 U16 event_data_size; 492 }; 493 494 /** 495 * struct delayed_dev_rmhs_node - Delayed device removal node 496 * 497 * @list: list head 498 * @handle: Device handle 499 * @iou_rc: IO Unit Control Reason Code 500 */ 501 struct delayed_dev_rmhs_node { 502 TAILQ_ENTRY(delayed_dev_rmhs_node) list; 503 U16 handle; 504 U8 iou_rc; 505 }; 506 507 /** 508 * struct delayed_evtack_node - Delayed event ack node 509 * 510 * @list: list head 511 * @event: MPI3 event ID 512 * @event_ctx: Event context 513 */ 514 struct delayed_evtack_node { 515 TAILQ_ENTRY(delayed_evtack_node) list; 516 U8 event; 517 U32 event_ctx; 518 }; 519 520 /* Reset types */ 521 enum reset_type { 522 MPI3MR_NO_RESET, 523 MPI3MR_TRIGGER_SOFT_RESET, 524 }; 525 526 struct mpi3mr_reset { 527 u_int type; 528 U32 reason; 529 int status; 530 bool ioctl_reset_snapdump; 531 }; 532 533 struct mpi3mr_softc { 534 device_t mpi3mr_dev; 535 struct cdev *mpi3mr_cdev; 536 u_int mpi3mr_flags; 537 #define MPI3MR_FLAGS_SHUTDOWN (1 << 0) 538 #define MPI3MR_FLAGS_DIAGRESET (1 << 1) 539 #define MPI3MR_FLAGS_ATTACH_DONE (1 << 2) 540 #define MPI3MR_FLAGS_PORT_ENABLE_DONE (1 << 3) 541 U8 id; 542 int cpu_count; 543 char name[MPI3MR_NAME_LENGTH]; 544 char driver_name[MPI3MR_NAME_LENGTH]; 545 int bars; 546 bus_addr_t dma_loaddr; 547 u_int mpi3mr_debug; 548 struct mpi3mr_reset reset; 549 int max_msix_vectors; 550 int msix_count; 551 bool msix_enable; 552 int io_cmds_highwater; 553 int max_chains; 554 uint32_t chain_frame_size; 555 struct sysctl_ctx_list sysctl_ctx; 556 struct sysctl_oid *sysctl_tree; 557 char fw_version[32]; 558 struct mpi3mr_chain *chains; 559 struct callout periodic; 560 struct callout device_check_callout; 561 562 struct mpi3mr_cam_softc *cam_sc; 563 struct mpi3mr_cmd **cmd_list; 564 TAILQ_HEAD(, mpi3mr_cmd) cmd_list_head; 565 struct mtx cmd_pool_lock; 566 567 struct resource *mpi3mr_regs_resource; 568 bus_space_handle_t mpi3mr_bhandle; 569 bus_space_tag_t mpi3mr_btag; 570 int mpi3mr_regs_rid; 571 572 bus_dma_tag_t mpi3mr_parent_dmat; 573 bus_dma_tag_t buffer_dmat; 574 575 int num_reqs; 576 int num_replies; 577 int num_chains; 578 579 TAILQ_HEAD(, mpi3mr_event_handle) event_list; 580 struct mpi3mr_event_handle *mpi3mr_log_eh; 581 struct intr_config_hook mpi3mr_ich; 582 583 struct mtx mpi3mr_mtx; 584 struct mtx io_lock; 585 U8 intr_enabled; 586 TAILQ_HEAD(, delayed_dev_rmhs_node) delayed_rmhs_list; 587 TAILQ_HEAD(, delayed_evtack_node) delayed_evtack_cmds_list; 588 589 U16 num_admin_reqs; 590 U32 admin_req_q_sz; 591 U16 admin_req_pi; 592 U16 admin_req_ci; 593 bus_dma_tag_t admin_req_tag; 594 bus_dmamap_t admin_req_dmamap; 595 bus_addr_t admin_req_phys; 596 U8 *admin_req; 597 struct mtx admin_req_lock; 598 599 U16 num_admin_replies; 600 U32 admin_reply_q_sz; 601 U16 admin_reply_ci; 602 U8 admin_reply_ephase; 603 bus_dma_tag_t admin_reply_tag; 604 bus_dmamap_t admin_reply_dmamap; 605 bus_addr_t admin_reply_phys; 606 U8 *admin_reply; 607 struct mtx admin_reply_lock; 608 bool admin_in_use; 609 610 U32 num_reply_bufs; 611 bus_dma_tag_t reply_buf_tag; 612 bus_dmamap_t reply_buf_dmamap; 613 bus_addr_t reply_buf_phys; 614 U8 *reply_buf; 615 bus_addr_t reply_buf_dma_max_address; 616 bus_addr_t reply_buf_dma_min_address; 617 618 U16 reply_free_q_sz; 619 bus_dma_tag_t reply_free_q_tag; 620 bus_dmamap_t reply_free_q_dmamap; 621 bus_addr_t reply_free_q_phys; 622 U64 *reply_free_q; 623 struct mtx reply_free_q_lock; 624 U32 reply_free_q_host_index; 625 626 U32 num_sense_bufs; 627 bus_dma_tag_t sense_buf_tag; 628 bus_dmamap_t sense_buf_dmamap; 629 bus_addr_t sense_buf_phys; 630 U8 *sense_buf; 631 632 U16 sense_buf_q_sz; 633 bus_dma_tag_t sense_buf_q_tag; 634 bus_dmamap_t sense_buf_q_dmamap; 635 bus_addr_t sense_buf_q_phys; 636 U64 *sense_buf_q; 637 struct mtx sense_buf_q_lock; 638 U32 sense_buf_q_host_index; 639 640 void *nvme_encap_prp_list; 641 bus_addr_t nvme_encap_prp_list_dma; 642 bus_dma_tag_t nvme_encap_prp_list_dmatag; 643 bus_dmamap_t nvme_encap_prp_list_dma_dmamap; 644 U32 nvme_encap_prp_sz; 645 646 U32 ready_timeout; 647 648 struct mpi3mr_irq_context *irq_ctx; 649 650 U16 num_queues; /* Number of request/reply queues */ 651 struct mpi3mr_op_req_queue *op_req_q; 652 struct mpi3mr_op_reply_queue *op_reply_q; 653 U16 num_hosttag_op_req_q; 654 655 struct mpi3mr_drvr_cmd init_cmds; 656 struct mpi3mr_ioc_facts facts; 657 U16 reply_sz; 658 U16 op_reply_sz; 659 660 U32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 661 662 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 663 struct workqueue_struct *fwevt_worker_thread; 664 struct mtx fwevt_lock; 665 struct mtx target_lock; 666 667 U16 max_host_ios; 668 bus_dma_tag_t chain_sgl_list_tag; 669 struct mpi3mr_chain *chain_sgl_list; 670 U16 chain_bitmap_sz; 671 void *chain_bitmap; 672 struct mtx chain_buf_lock; 673 U16 chain_buf_count; 674 675 struct mpi3mr_drvr_cmd ioctl_cmds; 676 struct mpi3mr_drvr_cmd host_tm_cmds; 677 struct mpi3mr_drvr_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 678 struct mpi3mr_drvr_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 679 680 U16 devrem_bitmap_sz; 681 void *devrem_bitmap; 682 683 U16 dev_handle_bitmap_sz; 684 void *removepend_bitmap; 685 686 U16 evtack_cmds_bitmap_sz; 687 void *evtack_cmds_bitmap; 688 689 U32 ts_update_counter; 690 U8 reset_in_progress; 691 U8 unrecoverable; 692 U8 block_ioctls; 693 U8 in_prep_ciactv_rst; 694 U16 prep_ciactv_rst_counter; 695 struct mtx reset_mutex; 696 697 U8 prepare_for_reset; 698 U16 prepare_for_reset_timeout_counter; 699 700 U16 diagsave_timeout; 701 int logging_level; 702 U16 flush_io_count; 703 704 Mpi3DriverInfoLayout_t driver_info; 705 706 U16 change_count; 707 708 U8 *log_data_buffer; 709 U16 log_data_buffer_index; 710 U16 log_data_entry_size; 711 712 U8 pel_wait_pend; 713 U8 pel_abort_requested; 714 U8 pel_class; 715 U16 pel_locale; 716 717 struct mpi3mr_drvr_cmd pel_cmds; 718 struct mpi3mr_drvr_cmd pel_abort_cmd; 719 U32 newest_seqnum; 720 void *pel_seq_number; 721 bus_addr_t pel_seq_number_dma; 722 bus_dma_tag_t pel_seq_num_dmatag; 723 bus_dmamap_t pel_seq_num_dmamap; 724 U32 pel_seq_number_sz; 725 726 struct selinfo mpi3mr_select; 727 U32 mpi3mr_poll_waiting; 728 U32 mpi3mr_aen_triggered; 729 730 U16 wait_for_port_enable; 731 U16 track_mapping_events; 732 U16 pending_map_events; 733 mpi3mr_atomic_t fw_outstanding; 734 mpi3mr_atomic_t pend_ioctls; 735 struct proc *watchdog_thread; 736 void *watchdog_chan; 737 void *tm_chan; 738 u_int8_t remove_in_progress; 739 u_int8_t watchdog_thread_active; 740 u_int8_t do_timedout_reset; 741 bool allow_ios; 742 bool secure_ctrl; 743 mpi3mr_atomic_t pend_large_data_sz; 744 745 u_int32_t io_throttle_data_length; 746 u_int32_t io_throttle_high; 747 u_int32_t io_throttle_low; 748 u_int16_t num_io_throttle_group; 749 u_int iot_enable; 750 struct mpi3mr_throttle_group_info *throttle_groups; 751 752 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE]; 753 struct dma_memory_desc ioctl_chain_sge; 754 struct dma_memory_desc ioctl_resp_sge; 755 bool ioctl_sges_allocated; 756 }; 757 758 static __inline uint64_t 759 mpi3mr_regread64(struct mpi3mr_softc *sc, uint32_t offset) 760 { 761 return bus_space_read_8(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset); 762 } 763 764 static __inline void 765 mpi3mr_regwrite64(struct mpi3mr_softc *sc, uint32_t offset, uint64_t val) 766 { 767 bus_space_write_8(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset, val); 768 } 769 770 static __inline uint32_t 771 mpi3mr_regread(struct mpi3mr_softc *sc, uint32_t offset) 772 { 773 return bus_space_read_4(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset); 774 } 775 776 static __inline void 777 mpi3mr_regwrite(struct mpi3mr_softc *sc, uint32_t offset, uint32_t val) 778 { 779 bus_space_write_4(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset, val); 780 } 781 782 #define MPI3MR_INFO (1 << 0) /* Basic info */ 783 #define MPI3MR_FAULT (1 << 1) /* Hardware faults */ 784 #define MPI3MR_EVENT (1 << 2) /* Event data from the controller */ 785 #define MPI3MR_LOG (1 << 3) /* Log data from the controller */ 786 #define MPI3MR_RECOVERY (1 << 4) /* Command error recovery tracing */ 787 #define MPI3MR_ERROR (1 << 5) /* Fatal driver/OS APIs failure */ 788 #define MPI3MR_XINFO (1 << 6) /* Additional info logs*/ 789 #define MPI3MR_TRACE (1 << 7) /* Trace functions */ 790 #define MPI3MR_IOT (1 << 8) /* IO throttling related debugs */ 791 #define MPI3MR_DEBUG_TM (1 << 9) /* Task management related debugs */ 792 #define MPI3MR_DEBUG_IOCTL (1 << 10) /* IOCTL related debugs */ 793 794 #define mpi3mr_printf(sc, args...) \ 795 device_printf((sc)->mpi3mr_dev, ##args) 796 797 #define mpi3mr_print_field(sc, msg, args...) \ 798 printf("\t" msg, ##args) 799 800 #define mpi3mr_vprintf(sc, args...) \ 801 do { \ 802 if (bootverbose) \ 803 mpi3mr_printf(sc, ##args); \ 804 } while (0) 805 806 #define mpi3mr_dprint(sc, level, msg, args...) \ 807 do { \ 808 if ((sc)->mpi3mr_debug & (level)) \ 809 device_printf((sc)->mpi3mr_dev, msg, ##args); \ 810 } while (0) 811 812 #define MPI3MR_PRINTFIELD_START(sc, tag...) \ 813 mpi3mr_printf((sc), ##tag); \ 814 mpi3mr_print_field((sc), ":\n") 815 #define MPI3MR_PRINTFIELD_END(sc, tag) \ 816 mpi3mr_printf((sc), tag "\n") 817 #define MPI3MR_PRINTFIELD(sc, facts, attr, fmt) \ 818 mpi3mr_print_field((sc), #attr ": " #fmt "\n", (facts)->attr) 819 820 #define mpi3mr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 821 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 822 #define mpi3mr_kproc_exit(arg) kproc_exit(arg) 823 824 #if defined(CAM_PRIORITY_XPT) 825 #define MPI3MR_PRIORITY_XPT CAM_PRIORITY_XPT 826 #else 827 #define MPI3MR_PRIORITY_XPT 5 828 #endif 829 830 static __inline void 831 mpi3mr_clear_bit(int b, volatile void *p) 832 { 833 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 834 } 835 836 static __inline void 837 mpi3mr_set_bit(int b, volatile void *p) 838 { 839 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 840 } 841 842 static __inline int 843 mpi3mr_test_bit(int b, volatile void *p) 844 { 845 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 846 } 847 848 static __inline int 849 mpi3mr_test_and_set_bit(int b, volatile void *p) 850 { 851 int ret = ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 852 853 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 854 return ret; 855 } 856 857 static __inline int 858 mpi3mr_find_first_zero_bit(void *p, int bit_count) 859 { 860 int i, sz, j=0; 861 U8 *loc; 862 863 sz = bit_count % 8 ? (bit_count / 8 + 1) : (bit_count / 8); 864 loc = malloc(sz, M_MPI3MR, M_NOWAIT | M_ZERO); 865 866 memcpy(loc, p, sz); 867 868 for (i = 0; i < sz; i++) { 869 j = 0; 870 while (j < 8) { 871 if (!((loc[i] >> j) & 0x1)) 872 goto out; 873 j++; 874 } 875 } 876 out: 877 free(loc, M_MPI3MR); 878 return (i + j); 879 } 880 881 #define MPI3MR_DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) 882 883 void 884 init_completion(struct completion *completion); 885 886 void 887 complete(struct completion *completion); 888 889 void wait_for_completion_timeout(struct completion *completion, 890 U32 timeout); 891 void wait_for_completion_timeout_tm(struct completion *completion, 892 U32 timeout, struct mpi3mr_softc *sc); 893 void mpi3mr_add_sg_single(void *paddr, U8 flags, U32 length, 894 bus_addr_t dma_addr); 895 void mpi3mr_enable_interrupts(struct mpi3mr_softc *sc); 896 void mpi3mr_disable_interrupts(struct mpi3mr_softc *sc); 897 void mpi3mr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 898 int mpi3mr_submit_admin_cmd(struct mpi3mr_softc *mrioc, void *admin_req, 899 U16 admin_req_sz); 900 int mpi3mr_submit_io(struct mpi3mr_softc *mrioc, 901 struct mpi3mr_op_req_queue *op_req_q, U8 *req); 902 int 903 mpi3mr_alloc_interrupts(struct mpi3mr_softc *sc, U16 setup_one); 904 905 void mpi3mr_cleanup_ioc(struct mpi3mr_softc *sc); 906 int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 reason); 907 void mpi3mr_build_zero_len_sge(void *paddr); 908 int mpi3mr_issue_event_notification(struct mpi3mr_softc *sc); 909 int 910 mpi3mr_register_events(struct mpi3mr_softc *sc); 911 void mpi3mr_process_op_reply_desc(struct mpi3mr_softc *sc, 912 Mpi3DefaultReplyDescriptor_t *reply_desc, U64 *reply_dma); 913 struct mpi3mr_cmd * 914 mpi3mr_get_command(struct mpi3mr_softc *sc); 915 void 916 mpi3mr_release_command(struct mpi3mr_cmd *cmd); 917 int 918 mpi3mr_complete_io_cmd(struct mpi3mr_softc *sc, 919 struct mpi3mr_irq_context *irq_context); 920 int 921 mpi3mr_cam_detach(struct mpi3mr_softc *sc); 922 int 923 mpi3mr_cam_attach(struct mpi3mr_softc *sc); 924 struct mpi3mr_target * 925 mpi3mr_find_target_by_per_id(struct mpi3mr_cam_softc *cam_sc, 926 uint16_t per_id); 927 struct mpi3mr_target * 928 mpi3mr_find_target_by_dev_handle(struct mpi3mr_cam_softc *cam_sc, 929 uint16_t dev_handle); 930 int mpi3mr_create_device(struct mpi3mr_softc *sc, 931 Mpi3DevicePage0_t *dev_pg0); 932 void 933 mpi3mr_unmap_request(struct mpi3mr_softc *sc, struct mpi3mr_cmd *cmd); 934 void 935 init_completion(struct completion *completion); 936 void 937 complete(struct completion *completion); 938 void wait_for_completion_timeout(struct completion *completion, 939 U32 timeout); 940 void 941 poll_for_command_completion(struct mpi3mr_softc *sc, 942 struct mpi3mr_drvr_cmd *cmd, U16 wait); 943 int 944 mpi3mr_alloc_requests(struct mpi3mr_softc *sc); 945 void 946 mpi3mr_watchdog(void *arg); 947 int mpi3mr_issue_port_enable(struct mpi3mr_softc *mrioc, U8 async); 948 void 949 mpi3mr_isr(void *privdata); 950 int 951 mpi3mr_alloc_msix_queues(struct mpi3mr_softc *sc); 952 void 953 mpi3mr_destory_mtx(struct mpi3mr_softc *sc); 954 void 955 mpi3mr_free_mem(struct mpi3mr_softc *sc); 956 void 957 mpi3mr_cleanup_interrupts(struct mpi3mr_softc *sc); 958 int mpi3mr_setup_irqs(struct mpi3mr_softc *sc); 959 void mpi3mr_cleanup_event_taskq(struct mpi3mr_softc *sc); 960 void 961 mpi3mr_hexdump(void *buf, int sz, int format); 962 int mpi3mr_soft_reset_handler(struct mpi3mr_softc *sc, 963 U32 reset_reason, bool snapdump); 964 void 965 mpi3mrsas_release_simq_reinit(struct mpi3mr_cam_softc *cam_sc); 966 void 967 mpi3mr_watchdog_thread(void *arg); 968 void mpi3mr_add_device(struct mpi3mr_softc *sc, U16 per_id); 969 int mpi3mr_remove_device(struct mpi3mr_softc *sc, U16 handle); 970 int 971 mpi3mrsas_register_events(struct mpi3mr_softc *sc); 972 int mpi3mr_process_event_ack(struct mpi3mr_softc *sc, U8 event, 973 U32 event_ctx); 974 int mpi3mr_remove_device_from_os(struct mpi3mr_softc *sc, U16 handle); 975 void mpi3mr_remove_device_from_list(struct mpi3mr_softc *sc, struct mpi3mr_target *target, 976 bool must_delete); 977 void mpi3mr_update_device(struct mpi3mr_softc *mrioc, 978 struct mpi3mr_target *tgtdev, Mpi3DevicePage0_t *dev_pg0, bool is_added); 979 void mpi3mr_app_save_logdata(struct mpi3mr_softc *sc, char *event_data, U16 event_data_size); 980 void mpi3mr_set_io_divert_for_all_vd_in_tg(struct mpi3mr_softc *sc, 981 struct mpi3mr_throttle_group_info *tg, U8 divert_value); 982 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_softc *sc); 983 void mpi3mr_poll_pend_io_completions(struct mpi3mr_softc *sc); 984 void int_to_lun(unsigned int lun, U8 *req_lun); 985 void trigger_reset_from_watchdog(struct mpi3mr_softc *sc, U8 reset_type, U32 reset_reason); 986 void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_softc *sc); 987 #endif /*MPI3MR_H_INCLUDED*/ 988