1 /*- 2 * Copyright (c) 2013-2020, Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IFC_H 29 #define MLX5_IFC_H 30 31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 32 33 enum { 34 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, 35 MLX5_EVENT_TYPE_COMP = 0x0, 36 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 37 MLX5_EVENT_TYPE_COMM_EST = 0x2, 38 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 39 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 40 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 41 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 42 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 43 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 44 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 45 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 46 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 47 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 48 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 49 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 50 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 51 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 52 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 53 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 54 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 55 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18, 56 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 57 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 58 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 59 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 60 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 61 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 62 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 63 MLX5_EVENT_TYPE_CMD = 0xa, 64 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 65 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 66 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 67 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 68 MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT = 0x27, 69 }; 70 71 enum { 72 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 73 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 74 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 75 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 76 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 77 }; 78 79 enum { 80 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 81 }; 82 83 enum { 84 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 85 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 86 }; 87 88 enum { 89 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 90 MLX5_OBJ_TYPE_MKEY = 0xff01, 91 MLX5_OBJ_TYPE_QP = 0xff02, 92 MLX5_OBJ_TYPE_PSV = 0xff03, 93 MLX5_OBJ_TYPE_RMP = 0xff04, 94 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 95 MLX5_OBJ_TYPE_RQ = 0xff06, 96 MLX5_OBJ_TYPE_SQ = 0xff07, 97 MLX5_OBJ_TYPE_TIR = 0xff08, 98 MLX5_OBJ_TYPE_TIS = 0xff09, 99 MLX5_OBJ_TYPE_DCT = 0xff0a, 100 MLX5_OBJ_TYPE_XRQ = 0xff0b, 101 MLX5_OBJ_TYPE_RQT = 0xff0e, 102 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 103 MLX5_OBJ_TYPE_CQ = 0xff10, 104 }; 105 106 enum { 107 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 108 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 109 MLX5_CMD_OP_INIT_HCA = 0x102, 110 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 111 MLX5_CMD_OP_ENABLE_HCA = 0x104, 112 MLX5_CMD_OP_DISABLE_HCA = 0x105, 113 MLX5_CMD_OP_QUERY_PAGES = 0x107, 114 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 115 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 116 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 117 MLX5_CMD_OP_SET_ISSI = 0x10b, 118 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 119 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 120 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 121 MLX5_CMD_OP_CREATE_MKEY = 0x200, 122 MLX5_CMD_OP_QUERY_MKEY = 0x201, 123 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 124 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 125 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 126 MLX5_CMD_OP_CREATE_EQ = 0x301, 127 MLX5_CMD_OP_DESTROY_EQ = 0x302, 128 MLX5_CMD_OP_QUERY_EQ = 0x303, 129 MLX5_CMD_OP_GEN_EQE = 0x304, 130 MLX5_CMD_OP_CREATE_CQ = 0x400, 131 MLX5_CMD_OP_DESTROY_CQ = 0x401, 132 MLX5_CMD_OP_QUERY_CQ = 0x402, 133 MLX5_CMD_OP_MODIFY_CQ = 0x403, 134 MLX5_CMD_OP_CREATE_QP = 0x500, 135 MLX5_CMD_OP_DESTROY_QP = 0x501, 136 MLX5_CMD_OP_RST2INIT_QP = 0x502, 137 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 138 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 139 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 140 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 141 MLX5_CMD_OP_2ERR_QP = 0x507, 142 MLX5_CMD_OP_2RST_QP = 0x50a, 143 MLX5_CMD_OP_QUERY_QP = 0x50b, 144 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 145 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 146 MLX5_CMD_OP_CREATE_PSV = 0x600, 147 MLX5_CMD_OP_DESTROY_PSV = 0x601, 148 MLX5_CMD_OP_CREATE_SRQ = 0x700, 149 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 150 MLX5_CMD_OP_QUERY_SRQ = 0x702, 151 MLX5_CMD_OP_ARM_RQ = 0x703, 152 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 153 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 154 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 155 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 156 MLX5_CMD_OP_CREATE_DCT = 0x710, 157 MLX5_CMD_OP_DESTROY_DCT = 0x711, 158 MLX5_CMD_OP_DRAIN_DCT = 0x712, 159 MLX5_CMD_OP_QUERY_DCT = 0x713, 160 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 161 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 162 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 163 MLX5_CMD_OP_CREATE_XRQ = 0x717, 164 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 165 MLX5_CMD_OP_QUERY_XRQ = 0x719, 166 MLX5_CMD_OP_ARM_XRQ = 0x71a, 167 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 168 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 169 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 170 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 171 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 172 173 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 174 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 175 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 176 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 177 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 178 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 179 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 180 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 181 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 182 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 183 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 184 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 185 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 186 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 187 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 188 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 189 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 190 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 191 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 192 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 193 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 194 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 195 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 196 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 197 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 198 MLX5_CMD_OP_ALLOC_PD = 0x800, 199 MLX5_CMD_OP_DEALLOC_PD = 0x801, 200 MLX5_CMD_OP_ALLOC_UAR = 0x802, 201 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 202 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 203 MLX5_CMD_OP_ACCESS_REG = 0x805, 204 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 205 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 206 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 207 MLX5_CMD_OP_MAD_IFC = 0x50d, 208 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 209 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 210 MLX5_CMD_OP_NOP = 0x80d, 211 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 212 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 213 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 214 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 215 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 216 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 217 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 218 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 219 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 220 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 221 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 222 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 223 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 224 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 225 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 226 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 227 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 228 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 229 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 230 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 231 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 232 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 233 MLX5_CMD_OP_CREATE_LAG = 0x840, 234 MLX5_CMD_OP_MODIFY_LAG = 0x841, 235 MLX5_CMD_OP_QUERY_LAG = 0x842, 236 MLX5_CMD_OP_DESTROY_LAG = 0x843, 237 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 238 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 239 MLX5_CMD_OP_CREATE_TIR = 0x900, 240 MLX5_CMD_OP_MODIFY_TIR = 0x901, 241 MLX5_CMD_OP_DESTROY_TIR = 0x902, 242 MLX5_CMD_OP_QUERY_TIR = 0x903, 243 MLX5_CMD_OP_CREATE_SQ = 0x904, 244 MLX5_CMD_OP_MODIFY_SQ = 0x905, 245 MLX5_CMD_OP_DESTROY_SQ = 0x906, 246 MLX5_CMD_OP_QUERY_SQ = 0x907, 247 MLX5_CMD_OP_CREATE_RQ = 0x908, 248 MLX5_CMD_OP_MODIFY_RQ = 0x909, 249 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 250 MLX5_CMD_OP_QUERY_RQ = 0x90b, 251 MLX5_CMD_OP_CREATE_RMP = 0x90c, 252 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 253 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 254 MLX5_CMD_OP_QUERY_RMP = 0x90f, 255 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 256 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 257 MLX5_CMD_OP_CREATE_TIS = 0x912, 258 MLX5_CMD_OP_MODIFY_TIS = 0x913, 259 MLX5_CMD_OP_DESTROY_TIS = 0x914, 260 MLX5_CMD_OP_QUERY_TIS = 0x915, 261 MLX5_CMD_OP_CREATE_RQT = 0x916, 262 MLX5_CMD_OP_MODIFY_RQT = 0x917, 263 MLX5_CMD_OP_DESTROY_RQT = 0x918, 264 MLX5_CMD_OP_QUERY_RQT = 0x919, 265 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 266 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 267 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 268 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 269 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 270 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 271 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 272 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 273 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 274 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 275 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 276 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 277 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 278 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 279 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 280 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 281 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 282 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 283 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 284 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 285 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 286 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 287 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 288 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 289 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 290 MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00, 291 MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01, 292 MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02, 293 MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03, 294 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 295 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 296 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 297 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 298 }; 299 300 /* Valid range for general commands that don't work over an object */ 301 enum { 302 MLX5_CMD_OP_GENERAL_START = 0xb00, 303 MLX5_CMD_OP_GENERAL_END = 0xd00, 304 }; 305 306 enum { 307 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 308 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 309 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 310 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 311 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 312 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 313 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 314 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 315 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 316 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 317 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 318 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 319 }; 320 321 enum { 322 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 323 }; 324 325 enum { 326 MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc, 327 }; 328 329 enum { 330 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 331 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 332 }; 333 334 enum { 335 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1, 336 }; 337 338 struct mlx5_ifc_flow_table_fields_supported_bits { 339 u8 outer_dmac[0x1]; 340 u8 outer_smac[0x1]; 341 u8 outer_ether_type[0x1]; 342 u8 outer_ip_version[0x1]; 343 u8 outer_first_prio[0x1]; 344 u8 outer_first_cfi[0x1]; 345 u8 outer_first_vid[0x1]; 346 u8 reserved_1[0x1]; 347 u8 outer_second_prio[0x1]; 348 u8 outer_second_cfi[0x1]; 349 u8 outer_second_vid[0x1]; 350 u8 outer_ipv6_flow_label[0x1]; 351 u8 outer_sip[0x1]; 352 u8 outer_dip[0x1]; 353 u8 outer_frag[0x1]; 354 u8 outer_ip_protocol[0x1]; 355 u8 outer_ip_ecn[0x1]; 356 u8 outer_ip_dscp[0x1]; 357 u8 outer_udp_sport[0x1]; 358 u8 outer_udp_dport[0x1]; 359 u8 outer_tcp_sport[0x1]; 360 u8 outer_tcp_dport[0x1]; 361 u8 outer_tcp_flags[0x1]; 362 u8 outer_gre_protocol[0x1]; 363 u8 outer_gre_key[0x1]; 364 u8 outer_vxlan_vni[0x1]; 365 u8 outer_geneve_vni[0x1]; 366 u8 outer_geneve_oam[0x1]; 367 u8 outer_geneve_protocol_type[0x1]; 368 u8 outer_geneve_opt_len[0x1]; 369 u8 reserved_2[0x1]; 370 u8 source_eswitch_port[0x1]; 371 372 u8 inner_dmac[0x1]; 373 u8 inner_smac[0x1]; 374 u8 inner_ether_type[0x1]; 375 u8 inner_ip_version[0x1]; 376 u8 inner_first_prio[0x1]; 377 u8 inner_first_cfi[0x1]; 378 u8 inner_first_vid[0x1]; 379 u8 reserved_4[0x1]; 380 u8 inner_second_prio[0x1]; 381 u8 inner_second_cfi[0x1]; 382 u8 inner_second_vid[0x1]; 383 u8 inner_ipv6_flow_label[0x1]; 384 u8 inner_sip[0x1]; 385 u8 inner_dip[0x1]; 386 u8 inner_frag[0x1]; 387 u8 inner_ip_protocol[0x1]; 388 u8 inner_ip_ecn[0x1]; 389 u8 inner_ip_dscp[0x1]; 390 u8 inner_udp_sport[0x1]; 391 u8 inner_udp_dport[0x1]; 392 u8 inner_tcp_sport[0x1]; 393 u8 inner_tcp_dport[0x1]; 394 u8 inner_tcp_flags[0x1]; 395 u8 reserved_5[0x9]; 396 397 u8 reserved_6[0x1a]; 398 u8 bth_dst_qp[0x1]; 399 u8 reserved_7[0x4]; 400 u8 source_sqn[0x1]; 401 402 u8 reserved_8[0x20]; 403 }; 404 405 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 406 u8 ingress_general_high[0x20]; 407 408 u8 ingress_general_low[0x20]; 409 410 u8 ingress_policy_engine_high[0x20]; 411 412 u8 ingress_policy_engine_low[0x20]; 413 414 u8 ingress_vlan_membership_high[0x20]; 415 416 u8 ingress_vlan_membership_low[0x20]; 417 418 u8 ingress_tag_frame_type_high[0x20]; 419 420 u8 ingress_tag_frame_type_low[0x20]; 421 422 u8 egress_vlan_membership_high[0x20]; 423 424 u8 egress_vlan_membership_low[0x20]; 425 426 u8 loopback_filter_high[0x20]; 427 428 u8 loopback_filter_low[0x20]; 429 430 u8 egress_general_high[0x20]; 431 432 u8 egress_general_low[0x20]; 433 434 u8 reserved_at_1c0[0x40]; 435 436 u8 egress_hoq_high[0x20]; 437 438 u8 egress_hoq_low[0x20]; 439 440 u8 port_isolation_high[0x20]; 441 442 u8 port_isolation_low[0x20]; 443 444 u8 egress_policy_engine_high[0x20]; 445 446 u8 egress_policy_engine_low[0x20]; 447 448 u8 ingress_tx_link_down_high[0x20]; 449 450 u8 ingress_tx_link_down_low[0x20]; 451 452 u8 egress_stp_filter_high[0x20]; 453 454 u8 egress_stp_filter_low[0x20]; 455 456 u8 egress_hoq_stall_high[0x20]; 457 458 u8 egress_hoq_stall_low[0x20]; 459 460 u8 reserved_at_340[0x440]; 461 }; 462 struct mlx5_ifc_flow_table_prop_layout_bits { 463 u8 ft_support[0x1]; 464 u8 flow_tag[0x1]; 465 u8 flow_counter[0x1]; 466 u8 flow_modify_en[0x1]; 467 u8 modify_root[0x1]; 468 u8 identified_miss_table[0x1]; 469 u8 flow_table_modify[0x1]; 470 u8 encap[0x1]; 471 u8 decap[0x1]; 472 u8 reset_root_to_default[0x1]; 473 u8 reserved_at_a[0x16]; 474 475 u8 reserved_at_20[0x2]; 476 u8 log_max_ft_size[0x6]; 477 u8 reserved_at_28[0x10]; 478 u8 max_ft_level[0x8]; 479 480 u8 reserved_at_40[0x20]; 481 482 u8 reserved_at_60[0x18]; 483 u8 log_max_ft_num[0x8]; 484 485 u8 reserved_at_80[0x10]; 486 u8 log_max_flow_counter[0x8]; 487 u8 log_max_destination[0x8]; 488 489 u8 reserved_at_a0[0x18]; 490 u8 log_max_flow[0x8]; 491 492 u8 reserved_at_c0[0x40]; 493 494 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 495 496 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 497 }; 498 499 struct mlx5_ifc_odp_per_transport_service_cap_bits { 500 u8 send[0x1]; 501 u8 receive[0x1]; 502 u8 write[0x1]; 503 u8 read[0x1]; 504 u8 atomic[0x1]; 505 u8 srq_receive[0x1]; 506 u8 reserved_0[0x1a]; 507 }; 508 509 struct mlx5_ifc_flow_counter_list_bits { 510 u8 reserved_0[0x10]; 511 u8 flow_counter_id[0x10]; 512 513 u8 reserved_1[0x20]; 514 }; 515 516 enum { 517 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 518 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 519 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 520 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 521 }; 522 523 struct mlx5_ifc_dest_format_struct_bits { 524 u8 destination_type[0x8]; 525 u8 destination_id[0x18]; 526 527 u8 reserved_0[0x20]; 528 }; 529 530 struct mlx5_ifc_ipv4_layout_bits { 531 u8 reserved_at_0[0x60]; 532 533 u8 ipv4[0x20]; 534 }; 535 536 struct mlx5_ifc_ipv6_layout_bits { 537 u8 ipv6[16][0x8]; 538 }; 539 540 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 541 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 542 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 543 u8 reserved_at_0[0x80]; 544 }; 545 546 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 547 u8 smac_47_16[0x20]; 548 549 u8 smac_15_0[0x10]; 550 u8 ethertype[0x10]; 551 552 u8 dmac_47_16[0x20]; 553 554 u8 dmac_15_0[0x10]; 555 u8 first_prio[0x3]; 556 u8 first_cfi[0x1]; 557 u8 first_vid[0xc]; 558 559 u8 ip_protocol[0x8]; 560 u8 ip_dscp[0x6]; 561 u8 ip_ecn[0x2]; 562 u8 cvlan_tag[0x1]; 563 u8 svlan_tag[0x1]; 564 u8 frag[0x1]; 565 u8 ip_version[0x4]; 566 u8 tcp_flags[0x9]; 567 568 u8 tcp_sport[0x10]; 569 u8 tcp_dport[0x10]; 570 571 u8 reserved_2[0x20]; 572 573 u8 udp_sport[0x10]; 574 u8 udp_dport[0x10]; 575 576 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 577 578 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 579 }; 580 581 struct mlx5_ifc_fte_match_set_misc_bits { 582 u8 reserved_0[0x8]; 583 u8 source_sqn[0x18]; 584 585 u8 reserved_1[0x10]; 586 u8 source_port[0x10]; 587 588 u8 outer_second_prio[0x3]; 589 u8 outer_second_cfi[0x1]; 590 u8 outer_second_vid[0xc]; 591 u8 inner_second_prio[0x3]; 592 u8 inner_second_cfi[0x1]; 593 u8 inner_second_vid[0xc]; 594 595 u8 outer_second_vlan_tag[0x1]; 596 u8 inner_second_vlan_tag[0x1]; 597 u8 reserved_2[0xe]; 598 u8 gre_protocol[0x10]; 599 600 u8 gre_key_h[0x18]; 601 u8 gre_key_l[0x8]; 602 603 u8 vxlan_vni[0x18]; 604 u8 reserved_3[0x8]; 605 606 u8 geneve_vni[0x18]; 607 u8 reserved4[0x7]; 608 u8 geneve_oam[0x1]; 609 610 u8 reserved_5[0xc]; 611 u8 outer_ipv6_flow_label[0x14]; 612 613 u8 reserved_6[0xc]; 614 u8 inner_ipv6_flow_label[0x14]; 615 616 u8 reserved_7[0xa]; 617 u8 geneve_opt_len[0x6]; 618 u8 geneve_protocol_type[0x10]; 619 620 u8 reserved_8[0x8]; 621 u8 bth_dst_qp[0x18]; 622 623 u8 reserved_9[0xa0]; 624 }; 625 626 struct mlx5_ifc_cmd_pas_bits { 627 u8 pa_h[0x20]; 628 629 u8 pa_l[0x14]; 630 u8 reserved_0[0xc]; 631 }; 632 633 struct mlx5_ifc_uint64_bits { 634 u8 hi[0x20]; 635 636 u8 lo[0x20]; 637 }; 638 639 struct mlx5_ifc_application_prio_entry_bits { 640 u8 reserved_0[0x8]; 641 u8 priority[0x3]; 642 u8 reserved_1[0x2]; 643 u8 sel[0x3]; 644 u8 protocol_id[0x10]; 645 }; 646 647 struct mlx5_ifc_nodnic_ring_doorbell_bits { 648 u8 reserved_0[0x8]; 649 u8 ring_pi[0x10]; 650 u8 reserved_1[0x8]; 651 }; 652 653 enum { 654 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 655 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 656 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 657 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 658 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 659 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 660 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 661 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 662 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 663 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 664 }; 665 666 struct mlx5_ifc_ads_bits { 667 u8 fl[0x1]; 668 u8 free_ar[0x1]; 669 u8 reserved_0[0xe]; 670 u8 pkey_index[0x10]; 671 672 u8 reserved_1[0x8]; 673 u8 grh[0x1]; 674 u8 mlid[0x7]; 675 u8 rlid[0x10]; 676 677 u8 ack_timeout[0x5]; 678 u8 reserved_2[0x3]; 679 u8 src_addr_index[0x8]; 680 u8 log_rtm[0x4]; 681 u8 stat_rate[0x4]; 682 u8 hop_limit[0x8]; 683 684 u8 reserved_3[0x4]; 685 u8 tclass[0x8]; 686 u8 flow_label[0x14]; 687 688 u8 rgid_rip[16][0x8]; 689 690 u8 reserved_4[0x4]; 691 u8 f_dscp[0x1]; 692 u8 f_ecn[0x1]; 693 u8 reserved_5[0x1]; 694 u8 f_eth_prio[0x1]; 695 u8 ecn[0x2]; 696 u8 dscp[0x6]; 697 u8 udp_sport[0x10]; 698 699 u8 dei_cfi[0x1]; 700 u8 eth_prio[0x3]; 701 u8 sl[0x4]; 702 u8 port[0x8]; 703 u8 rmac_47_32[0x10]; 704 705 u8 rmac_31_0[0x20]; 706 }; 707 708 struct mlx5_ifc_diagnostic_counter_cap_bits { 709 u8 sync[0x1]; 710 u8 reserved_0[0xf]; 711 u8 counter_id[0x10]; 712 }; 713 714 struct mlx5_ifc_debug_cap_bits { 715 u8 reserved_0[0x18]; 716 u8 log_max_samples[0x8]; 717 718 u8 single[0x1]; 719 u8 repetitive[0x1]; 720 u8 health_mon_rx_activity[0x1]; 721 u8 reserved_1[0x15]; 722 u8 log_min_sample_period[0x8]; 723 724 u8 reserved_2[0x1c0]; 725 726 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 727 }; 728 729 struct mlx5_ifc_qos_cap_bits { 730 u8 packet_pacing[0x1]; 731 u8 esw_scheduling[0x1]; 732 u8 esw_bw_share[0x1]; 733 u8 esw_rate_limit[0x1]; 734 u8 hll[0x1]; 735 u8 packet_pacing_burst_bound[0x1]; 736 u8 packet_pacing_typical_size[0x1]; 737 u8 reserved_at_7[0x19]; 738 739 u8 reserved_at_20[0xA]; 740 u8 qos_remap_pp[0x1]; 741 u8 reserved_at_2b[0x15]; 742 743 u8 packet_pacing_max_rate[0x20]; 744 745 u8 packet_pacing_min_rate[0x20]; 746 747 u8 reserved_at_80[0x10]; 748 u8 packet_pacing_rate_table_size[0x10]; 749 750 u8 esw_element_type[0x10]; 751 u8 esw_tsar_type[0x10]; 752 753 u8 reserved_at_c0[0x10]; 754 u8 max_qos_para_vport[0x10]; 755 756 u8 max_tsar_bw_share[0x20]; 757 758 u8 reserved_at_100[0x700]; 759 }; 760 761 struct mlx5_ifc_snapshot_cap_bits { 762 u8 reserved_0[0x1d]; 763 u8 suspend_qp_uc[0x1]; 764 u8 suspend_qp_ud[0x1]; 765 u8 suspend_qp_rc[0x1]; 766 767 u8 reserved_1[0x1c]; 768 u8 restore_pd[0x1]; 769 u8 restore_uar[0x1]; 770 u8 restore_mkey[0x1]; 771 u8 restore_qp[0x1]; 772 773 u8 reserved_2[0x1e]; 774 u8 named_mkey[0x1]; 775 u8 named_qp[0x1]; 776 777 u8 reserved_3[0x7a0]; 778 }; 779 780 struct mlx5_ifc_e_switch_cap_bits { 781 u8 vport_svlan_strip[0x1]; 782 u8 vport_cvlan_strip[0x1]; 783 u8 vport_svlan_insert[0x1]; 784 u8 vport_cvlan_insert_if_not_exist[0x1]; 785 u8 vport_cvlan_insert_overwrite[0x1]; 786 787 u8 reserved_0[0x19]; 788 789 u8 nic_vport_node_guid_modify[0x1]; 790 u8 nic_vport_port_guid_modify[0x1]; 791 792 u8 reserved_1[0x7e0]; 793 }; 794 795 struct mlx5_ifc_flow_table_eswitch_cap_bits { 796 u8 reserved_0[0x200]; 797 798 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 799 800 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 801 802 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 803 804 u8 reserved_1[0x7800]; 805 }; 806 807 struct mlx5_ifc_flow_table_nic_cap_bits { 808 u8 nic_rx_multi_path_tirs[0x1]; 809 u8 nic_rx_multi_path_tirs_fts[0x1]; 810 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 811 u8 reserved_at_3[0x1fd]; 812 813 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 814 815 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 816 817 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 818 819 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 820 821 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 822 823 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 824 825 u8 reserved_1[0x7200]; 826 }; 827 828 struct mlx5_ifc_pddr_module_info_bits { 829 u8 cable_technology[0x8]; 830 u8 cable_breakout[0x8]; 831 u8 ext_ethernet_compliance_code[0x8]; 832 u8 ethernet_compliance_code[0x8]; 833 834 u8 cable_type[0x4]; 835 u8 cable_vendor[0x4]; 836 u8 cable_length[0x8]; 837 u8 cable_identifier[0x8]; 838 u8 cable_power_class[0x8]; 839 840 u8 reserved_at_40[0x8]; 841 u8 cable_rx_amp[0x8]; 842 u8 cable_rx_emphasis[0x8]; 843 u8 cable_tx_equalization[0x8]; 844 845 u8 reserved_at_60[0x8]; 846 u8 cable_attenuation_12g[0x8]; 847 u8 cable_attenuation_7g[0x8]; 848 u8 cable_attenuation_5g[0x8]; 849 850 u8 reserved_at_80[0x8]; 851 u8 rx_cdr_cap[0x4]; 852 u8 tx_cdr_cap[0x4]; 853 u8 reserved_at_90[0x4]; 854 u8 rx_cdr_state[0x4]; 855 u8 reserved_at_98[0x4]; 856 u8 tx_cdr_state[0x4]; 857 858 u8 vendor_name[16][0x8]; 859 860 u8 vendor_pn[16][0x8]; 861 862 u8 vendor_rev[0x20]; 863 864 u8 fw_version[0x20]; 865 866 u8 vendor_sn[16][0x8]; 867 868 u8 temperature[0x10]; 869 u8 voltage[0x10]; 870 871 u8 rx_power_lane0[0x10]; 872 u8 rx_power_lane1[0x10]; 873 874 u8 rx_power_lane2[0x10]; 875 u8 rx_power_lane3[0x10]; 876 877 u8 reserved_at_2c0[0x40]; 878 879 u8 tx_power_lane0[0x10]; 880 u8 tx_power_lane1[0x10]; 881 882 u8 tx_power_lane2[0x10]; 883 u8 tx_power_lane3[0x10]; 884 885 u8 reserved_at_340[0x40]; 886 887 u8 tx_bias_lane0[0x10]; 888 u8 tx_bias_lane1[0x10]; 889 890 u8 tx_bias_lane2[0x10]; 891 u8 tx_bias_lane3[0x10]; 892 893 u8 reserved_at_3c0[0x40]; 894 895 u8 temperature_high_th[0x10]; 896 u8 temperature_low_th[0x10]; 897 898 u8 voltage_high_th[0x10]; 899 u8 voltage_low_th[0x10]; 900 901 u8 rx_power_high_th[0x10]; 902 u8 rx_power_low_th[0x10]; 903 904 u8 tx_power_high_th[0x10]; 905 u8 tx_power_low_th[0x10]; 906 907 u8 tx_bias_high_th[0x10]; 908 u8 tx_bias_low_th[0x10]; 909 910 u8 reserved_at_4a0[0x10]; 911 u8 wavelength[0x10]; 912 913 u8 reserved_at_4c0[0x300]; 914 }; 915 916 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 917 u8 csum_cap[0x1]; 918 u8 vlan_cap[0x1]; 919 u8 lro_cap[0x1]; 920 u8 lro_psh_flag[0x1]; 921 u8 lro_time_stamp[0x1]; 922 u8 lro_max_msg_sz_mode[0x2]; 923 u8 wqe_vlan_insert[0x1]; 924 u8 self_lb_en_modifiable[0x1]; 925 u8 self_lb_mc[0x1]; 926 u8 self_lb_uc[0x1]; 927 u8 max_lso_cap[0x5]; 928 u8 multi_pkt_send_wqe[0x2]; 929 u8 wqe_inline_mode[0x2]; 930 u8 rss_ind_tbl_cap[0x4]; 931 u8 reg_umr_sq[0x1]; 932 u8 scatter_fcs[0x1]; 933 u8 enhanced_multi_pkt_send_wqe[0x1]; 934 u8 tunnel_lso_const_out_ip_id[0x1]; 935 u8 tunnel_lro_gre[0x1]; 936 u8 tunnel_lro_vxlan[0x1]; 937 u8 tunnel_statless_gre[0x1]; 938 u8 tunnel_stateless_vxlan[0x1]; 939 940 u8 swp[0x1]; 941 u8 swp_csum[0x1]; 942 u8 swp_lso[0x1]; 943 u8 reserved_2[0x1b]; 944 u8 max_geneve_opt_len[0x1]; 945 u8 tunnel_stateless_geneve_rx[0x1]; 946 947 u8 reserved_3[0x10]; 948 u8 lro_min_mss_size[0x10]; 949 950 u8 reserved_4[0x120]; 951 952 u8 lro_timer_supported_periods[4][0x20]; 953 954 u8 reserved_5[0x600]; 955 }; 956 957 enum { 958 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 959 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 960 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 961 }; 962 963 enum { 964 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 965 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 966 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 967 }; 968 969 struct mlx5_ifc_roce_cap_bits { 970 u8 roce_apm[0x1]; 971 u8 rts2rts_primary_eth_prio[0x1]; 972 u8 roce_rx_allow_untagged[0x1]; 973 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 974 u8 reserved_at_4[0x1a]; 975 u8 qp_ts_format[0x2]; 976 977 u8 reserved_1[0x60]; 978 979 u8 reserved_2[0xc]; 980 u8 l3_type[0x4]; 981 u8 reserved_3[0x8]; 982 u8 roce_version[0x8]; 983 984 u8 reserved_4[0x10]; 985 u8 r_roce_dest_udp_port[0x10]; 986 987 u8 r_roce_max_src_udp_port[0x10]; 988 u8 r_roce_min_src_udp_port[0x10]; 989 990 u8 reserved_5[0x10]; 991 u8 roce_address_table_size[0x10]; 992 993 u8 reserved_6[0x700]; 994 }; 995 996 struct mlx5_ifc_device_event_cap_bits { 997 u8 user_affiliated_events[4][0x40]; 998 999 u8 user_unaffiliated_events[4][0x40]; 1000 }; 1001 1002 enum { 1003 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 1004 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1005 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1006 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1007 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1008 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1009 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1010 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1011 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1012 }; 1013 1014 enum { 1015 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1016 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1017 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1018 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1019 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1020 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1021 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1022 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1023 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1024 }; 1025 1026 struct mlx5_ifc_atomic_caps_bits { 1027 u8 reserved_0[0x40]; 1028 1029 u8 atomic_req_8B_endianess_mode[0x2]; 1030 u8 reserved_1[0x4]; 1031 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 1032 1033 u8 reserved_2[0x19]; 1034 1035 u8 reserved_3[0x20]; 1036 1037 u8 reserved_4[0x10]; 1038 u8 atomic_operations[0x10]; 1039 1040 u8 reserved_5[0x10]; 1041 u8 atomic_size_qp[0x10]; 1042 1043 u8 reserved_6[0x10]; 1044 u8 atomic_size_dc[0x10]; 1045 1046 u8 reserved_7[0x720]; 1047 }; 1048 1049 struct mlx5_ifc_odp_cap_bits { 1050 u8 reserved_0[0x40]; 1051 1052 u8 sig[0x1]; 1053 u8 reserved_1[0x1f]; 1054 1055 u8 reserved_2[0x20]; 1056 1057 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1058 1059 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1060 1061 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1062 1063 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1064 1065 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1066 1067 u8 reserved_3[0x6e0]; 1068 }; 1069 1070 enum { 1071 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1072 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1073 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1074 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1075 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1076 }; 1077 1078 enum { 1079 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1080 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1081 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1082 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1083 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1084 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1085 }; 1086 1087 enum { 1088 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1089 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1090 }; 1091 1092 enum { 1093 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1094 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1095 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1096 }; 1097 1098 enum { 1099 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1100 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1101 }; 1102 1103 enum { 1104 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1105 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1106 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1107 }; 1108 1109 enum { 1110 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1111 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1112 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1113 }; 1114 1115 struct mlx5_ifc_cmd_hca_cap_bits { 1116 u8 reserved_0[0x80]; 1117 1118 u8 log_max_srq_sz[0x8]; 1119 u8 log_max_qp_sz[0x8]; 1120 u8 event_cap[0x1]; 1121 u8 reserved_1[0xa]; 1122 u8 log_max_qp[0x5]; 1123 1124 u8 reserved_2[0xb]; 1125 u8 log_max_srq[0x5]; 1126 u8 reserved_3[0x10]; 1127 1128 u8 reserved_4[0x8]; 1129 u8 log_max_cq_sz[0x8]; 1130 u8 relaxed_ordering_write_umr[0x1]; 1131 u8 relaxed_ordering_read_umr[0x1]; 1132 u8 reserved_5[0x9]; 1133 u8 log_max_cq[0x5]; 1134 1135 u8 log_max_eq_sz[0x8]; 1136 u8 relaxed_ordering_write[0x1]; 1137 u8 relaxed_ordering_read[0x1]; 1138 u8 log_max_mkey[0x6]; 1139 u8 reserved_7[0xb]; 1140 u8 fast_teardown[0x1]; 1141 u8 log_max_eq[0x4]; 1142 1143 u8 max_indirection[0x8]; 1144 u8 reserved_8[0x1]; 1145 u8 log_max_mrw_sz[0x7]; 1146 u8 force_teardown[0x1]; 1147 u8 reserved_9[0x1]; 1148 u8 log_max_bsf_list_size[0x6]; 1149 u8 reserved_10[0x2]; 1150 u8 log_max_klm_list_size[0x6]; 1151 1152 u8 reserved_11[0xa]; 1153 u8 log_max_ra_req_dc[0x6]; 1154 u8 reserved_12[0xa]; 1155 u8 log_max_ra_res_dc[0x6]; 1156 1157 u8 reserved_13[0xa]; 1158 u8 log_max_ra_req_qp[0x6]; 1159 u8 reserved_14[0xa]; 1160 u8 log_max_ra_res_qp[0x6]; 1161 1162 u8 pad_cap[0x1]; 1163 u8 cc_query_allowed[0x1]; 1164 u8 cc_modify_allowed[0x1]; 1165 u8 start_pad[0x1]; 1166 u8 cache_line_128byte[0x1]; 1167 u8 reserved_at_165[0xa]; 1168 u8 qcam_reg[0x1]; 1169 u8 gid_table_size[0x10]; 1170 1171 u8 out_of_seq_cnt[0x1]; 1172 u8 vport_counters[0x1]; 1173 u8 retransmission_q_counters[0x1]; 1174 u8 debug[0x1]; 1175 u8 modify_rq_counters_set_id[0x1]; 1176 u8 rq_delay_drop[0x1]; 1177 u8 max_qp_cnt[0xa]; 1178 u8 pkey_table_size[0x10]; 1179 1180 u8 vport_group_manager[0x1]; 1181 u8 vhca_group_manager[0x1]; 1182 u8 ib_virt[0x1]; 1183 u8 eth_virt[0x1]; 1184 u8 reserved_17[0x1]; 1185 u8 ets[0x1]; 1186 u8 nic_flow_table[0x1]; 1187 u8 eswitch_flow_table[0x1]; 1188 u8 reserved_18[0x1]; 1189 u8 mcam_reg[0x1]; 1190 u8 pcam_reg[0x1]; 1191 u8 local_ca_ack_delay[0x5]; 1192 u8 port_module_event[0x1]; 1193 u8 reserved_19[0x5]; 1194 u8 port_type[0x2]; 1195 u8 num_ports[0x8]; 1196 1197 u8 snapshot[0x1]; 1198 u8 reserved_20[0x2]; 1199 u8 log_max_msg[0x5]; 1200 u8 reserved_21[0x4]; 1201 u8 max_tc[0x4]; 1202 u8 temp_warn_event[0x1]; 1203 u8 dcbx[0x1]; 1204 u8 general_notification_event[0x1]; 1205 u8 reserved_at_1d3[0x2]; 1206 u8 fpga[0x1]; 1207 u8 rol_s[0x1]; 1208 u8 rol_g[0x1]; 1209 u8 reserved_23[0x1]; 1210 u8 wol_s[0x1]; 1211 u8 wol_g[0x1]; 1212 u8 wol_a[0x1]; 1213 u8 wol_b[0x1]; 1214 u8 wol_m[0x1]; 1215 u8 wol_u[0x1]; 1216 u8 wol_p[0x1]; 1217 1218 u8 stat_rate_support[0x10]; 1219 u8 reserved_24[0xc]; 1220 u8 cqe_version[0x4]; 1221 1222 u8 compact_address_vector[0x1]; 1223 u8 striding_rq[0x1]; 1224 u8 reserved_25[0x1]; 1225 u8 ipoib_enhanced_offloads[0x1]; 1226 u8 ipoib_ipoib_offloads[0x1]; 1227 u8 reserved_26[0x8]; 1228 u8 dc_connect_qp[0x1]; 1229 u8 dc_cnak_trace[0x1]; 1230 u8 drain_sigerr[0x1]; 1231 u8 cmdif_checksum[0x2]; 1232 u8 sigerr_cqe[0x1]; 1233 u8 reserved_27[0x1]; 1234 u8 wq_signature[0x1]; 1235 u8 sctr_data_cqe[0x1]; 1236 u8 reserved_28[0x1]; 1237 u8 sho[0x1]; 1238 u8 tph[0x1]; 1239 u8 rf[0x1]; 1240 u8 dct[0x1]; 1241 u8 qos[0x1]; 1242 u8 eth_net_offloads[0x1]; 1243 u8 roce[0x1]; 1244 u8 atomic[0x1]; 1245 u8 reserved_30[0x1]; 1246 1247 u8 cq_oi[0x1]; 1248 u8 cq_resize[0x1]; 1249 u8 cq_moderation[0x1]; 1250 u8 cq_period_mode_modify[0x1]; 1251 u8 cq_invalidate[0x1]; 1252 u8 reserved_at_225[0x1]; 1253 u8 cq_eq_remap[0x1]; 1254 u8 pg[0x1]; 1255 u8 block_lb_mc[0x1]; 1256 u8 exponential_backoff[0x1]; 1257 u8 scqe_break_moderation[0x1]; 1258 u8 cq_period_start_from_cqe[0x1]; 1259 u8 cd[0x1]; 1260 u8 atm[0x1]; 1261 u8 apm[0x1]; 1262 u8 imaicl[0x1]; 1263 u8 reserved_32[0x6]; 1264 u8 qkv[0x1]; 1265 u8 pkv[0x1]; 1266 u8 set_deth_sqpn[0x1]; 1267 u8 reserved_33[0x3]; 1268 u8 xrc[0x1]; 1269 u8 ud[0x1]; 1270 u8 uc[0x1]; 1271 u8 rc[0x1]; 1272 1273 u8 uar_4k[0x1]; 1274 u8 reserved_at_241[0x9]; 1275 u8 uar_sz[0x6]; 1276 u8 reserved_35[0x8]; 1277 u8 log_pg_sz[0x8]; 1278 1279 u8 bf[0x1]; 1280 u8 driver_version[0x1]; 1281 u8 pad_tx_eth_packet[0x1]; 1282 u8 reserved_36[0x8]; 1283 u8 log_bf_reg_size[0x5]; 1284 u8 reserved_37[0x10]; 1285 1286 u8 num_of_diagnostic_counters[0x10]; 1287 u8 max_wqe_sz_sq[0x10]; 1288 1289 u8 reserved_38[0x10]; 1290 u8 max_wqe_sz_rq[0x10]; 1291 1292 u8 reserved_39[0x10]; 1293 u8 max_wqe_sz_sq_dc[0x10]; 1294 1295 u8 reserved_40[0x7]; 1296 u8 max_qp_mcg[0x19]; 1297 1298 u8 reserved_41[0x18]; 1299 u8 log_max_mcg[0x8]; 1300 1301 u8 reserved_42[0x3]; 1302 u8 log_max_transport_domain[0x5]; 1303 u8 reserved_43[0x3]; 1304 u8 log_max_pd[0x5]; 1305 u8 reserved_44[0xb]; 1306 u8 log_max_xrcd[0x5]; 1307 1308 u8 nic_receive_steering_discard[0x1]; 1309 u8 reserved_45[0x7]; 1310 u8 log_max_flow_counter_bulk[0x8]; 1311 u8 max_flow_counter[0x10]; 1312 1313 u8 reserved_46[0x3]; 1314 u8 log_max_rq[0x5]; 1315 u8 reserved_47[0x3]; 1316 u8 log_max_sq[0x5]; 1317 u8 reserved_48[0x3]; 1318 u8 log_max_tir[0x5]; 1319 u8 reserved_49[0x3]; 1320 u8 log_max_tis[0x5]; 1321 1322 u8 basic_cyclic_rcv_wqe[0x1]; 1323 u8 reserved_50[0x2]; 1324 u8 log_max_rmp[0x5]; 1325 u8 reserved_51[0x3]; 1326 u8 log_max_rqt[0x5]; 1327 u8 reserved_52[0x3]; 1328 u8 log_max_rqt_size[0x5]; 1329 u8 reserved_53[0x3]; 1330 u8 log_max_tis_per_sq[0x5]; 1331 1332 u8 reserved_54[0x3]; 1333 u8 log_max_stride_sz_rq[0x5]; 1334 u8 reserved_55[0x3]; 1335 u8 log_min_stride_sz_rq[0x5]; 1336 u8 reserved_56[0x3]; 1337 u8 log_max_stride_sz_sq[0x5]; 1338 u8 reserved_57[0x3]; 1339 u8 log_min_stride_sz_sq[0x5]; 1340 1341 u8 reserved_58[0x1b]; 1342 u8 log_max_wq_sz[0x5]; 1343 1344 u8 nic_vport_change_event[0x1]; 1345 u8 disable_local_lb_uc[0x1]; 1346 u8 disable_local_lb_mc[0x1]; 1347 u8 reserved_59[0x8]; 1348 u8 log_max_vlan_list[0x5]; 1349 u8 reserved_60[0x3]; 1350 u8 log_max_current_mc_list[0x5]; 1351 u8 reserved_61[0x3]; 1352 u8 log_max_current_uc_list[0x5]; 1353 1354 u8 general_obj_types[0x40]; 1355 1356 u8 sq_ts_format[0x2]; 1357 u8 rq_ts_format[0x2]; 1358 u8 reserved_at_444[0x4]; 1359 u8 create_qp_start_hint[0x18]; 1360 1361 u8 reserved_at_460[0x3]; 1362 u8 log_max_uctx[0x5]; 1363 u8 reserved_at_468[0x3]; 1364 u8 log_max_umem[0x5]; 1365 u8 max_num_eqs[0x10]; 1366 1367 u8 reserved_at_480[0x1]; 1368 u8 tls_tx[0x1]; 1369 u8 tls_rx[0x1]; 1370 u8 log_max_l2_table[0x5]; 1371 u8 reserved_64[0x8]; 1372 u8 log_uar_page_sz[0x10]; 1373 1374 u8 reserved_65[0x20]; 1375 1376 u8 device_frequency_mhz[0x20]; 1377 1378 u8 device_frequency_khz[0x20]; 1379 1380 u8 reserved_at_500[0x20]; 1381 u8 num_of_uars_per_page[0x20]; 1382 u8 reserved_at_540[0x40]; 1383 1384 u8 log_max_atomic_size_qp[0x8]; 1385 u8 reserved_67[0x10]; 1386 u8 log_max_atomic_size_dc[0x8]; 1387 1388 u8 reserved_at_5a0[0x13]; 1389 u8 log_max_dek[0x5]; 1390 u8 reserved_at_5b8[0x4]; 1391 u8 mini_cqe_resp_stride_index[0x1]; 1392 u8 cqe_128_always[0x1]; 1393 u8 cqe_compression_128b[0x1]; 1394 1395 u8 cqe_compression[0x1]; 1396 1397 u8 cqe_compression_timeout[0x10]; 1398 u8 cqe_compression_max_num[0x10]; 1399 1400 u8 reserved_5e0[0xc0]; 1401 1402 u8 uctx_cap[0x20]; 1403 1404 u8 reserved_6c0[0xc0]; 1405 1406 u8 vhca_tunnel_commands[0x40]; 1407 u8 reserved_at_7c0[0x40]; 1408 }; 1409 1410 enum mlx5_flow_destination_type { 1411 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1412 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1413 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1414 }; 1415 1416 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1417 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1418 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1419 u8 reserved_0[0x40]; 1420 }; 1421 1422 struct mlx5_ifc_fte_match_param_bits { 1423 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1424 1425 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1426 1427 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1428 1429 u8 reserved_0[0xa00]; 1430 }; 1431 1432 enum { 1433 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1434 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1435 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1436 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1437 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1438 }; 1439 1440 struct mlx5_ifc_rx_hash_field_select_bits { 1441 u8 l3_prot_type[0x1]; 1442 u8 l4_prot_type[0x1]; 1443 u8 selected_fields[0x1e]; 1444 }; 1445 1446 struct mlx5_ifc_tls_capabilities_bits { 1447 u8 tls_1_2_aes_gcm_128[0x1]; 1448 u8 tls_1_3_aes_gcm_128[0x1]; 1449 u8 tls_1_2_aes_gcm_256[0x1]; 1450 u8 tls_1_3_aes_gcm_256[0x1]; 1451 u8 reserved_at_4[0x1c]; 1452 1453 u8 reserved_at_20[0x7e0]; 1454 }; 1455 1456 enum { 1457 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1458 MLX5_WQ_TYPE_CYCLIC = 0x1, 1459 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1460 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1461 }; 1462 1463 enum rq_type { 1464 RQ_TYPE_NONE, 1465 RQ_TYPE_STRIDE, 1466 }; 1467 1468 enum { 1469 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1470 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1471 }; 1472 1473 struct mlx5_ifc_wq_bits { 1474 u8 wq_type[0x4]; 1475 u8 wq_signature[0x1]; 1476 u8 end_padding_mode[0x2]; 1477 u8 cd_slave[0x1]; 1478 u8 reserved_0[0x18]; 1479 1480 u8 hds_skip_first_sge[0x1]; 1481 u8 log2_hds_buf_size[0x3]; 1482 u8 reserved_1[0x7]; 1483 u8 page_offset[0x5]; 1484 u8 lwm[0x10]; 1485 1486 u8 reserved_2[0x8]; 1487 u8 pd[0x18]; 1488 1489 u8 reserved_3[0x8]; 1490 u8 uar_page[0x18]; 1491 1492 u8 dbr_addr[0x40]; 1493 1494 u8 hw_counter[0x20]; 1495 1496 u8 sw_counter[0x20]; 1497 1498 u8 reserved_4[0xc]; 1499 u8 log_wq_stride[0x4]; 1500 u8 reserved_5[0x3]; 1501 u8 log_wq_pg_sz[0x5]; 1502 u8 reserved_6[0x3]; 1503 u8 log_wq_sz[0x5]; 1504 1505 u8 dbr_umem_valid[0x1]; 1506 u8 wq_umem_valid[0x1]; 1507 u8 reserved_7[0x13]; 1508 u8 single_wqe_log_num_of_strides[0x3]; 1509 u8 two_byte_shift_en[0x1]; 1510 u8 reserved_8[0x4]; 1511 u8 single_stride_log_num_of_bytes[0x3]; 1512 1513 u8 reserved_9[0x4c0]; 1514 1515 struct mlx5_ifc_cmd_pas_bits pas[0]; 1516 }; 1517 1518 struct mlx5_ifc_rq_num_bits { 1519 u8 reserved_0[0x8]; 1520 u8 rq_num[0x18]; 1521 }; 1522 1523 struct mlx5_ifc_mac_address_layout_bits { 1524 u8 reserved_0[0x10]; 1525 u8 mac_addr_47_32[0x10]; 1526 1527 u8 mac_addr_31_0[0x20]; 1528 }; 1529 1530 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1531 u8 reserved_0[0xa0]; 1532 1533 u8 min_time_between_cnps[0x20]; 1534 1535 u8 reserved_1[0x12]; 1536 u8 cnp_dscp[0x6]; 1537 u8 reserved_2[0x4]; 1538 u8 cnp_prio_mode[0x1]; 1539 u8 cnp_802p_prio[0x3]; 1540 1541 u8 reserved_3[0x720]; 1542 }; 1543 1544 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1545 u8 reserved_0[0x60]; 1546 1547 u8 reserved_1[0x4]; 1548 u8 clamp_tgt_rate[0x1]; 1549 u8 reserved_2[0x3]; 1550 u8 clamp_tgt_rate_after_time_inc[0x1]; 1551 u8 reserved_3[0x17]; 1552 1553 u8 reserved_4[0x20]; 1554 1555 u8 rpg_time_reset[0x20]; 1556 1557 u8 rpg_byte_reset[0x20]; 1558 1559 u8 rpg_threshold[0x20]; 1560 1561 u8 rpg_max_rate[0x20]; 1562 1563 u8 rpg_ai_rate[0x20]; 1564 1565 u8 rpg_hai_rate[0x20]; 1566 1567 u8 rpg_gd[0x20]; 1568 1569 u8 rpg_min_dec_fac[0x20]; 1570 1571 u8 rpg_min_rate[0x20]; 1572 1573 u8 reserved_5[0xe0]; 1574 1575 u8 rate_to_set_on_first_cnp[0x20]; 1576 1577 u8 dce_tcp_g[0x20]; 1578 1579 u8 dce_tcp_rtt[0x20]; 1580 1581 u8 rate_reduce_monitor_period[0x20]; 1582 1583 u8 reserved_6[0x20]; 1584 1585 u8 initial_alpha_value[0x20]; 1586 1587 u8 reserved_7[0x4a0]; 1588 }; 1589 1590 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1591 u8 reserved_0[0x80]; 1592 1593 u8 rppp_max_rps[0x20]; 1594 1595 u8 rpg_time_reset[0x20]; 1596 1597 u8 rpg_byte_reset[0x20]; 1598 1599 u8 rpg_threshold[0x20]; 1600 1601 u8 rpg_max_rate[0x20]; 1602 1603 u8 rpg_ai_rate[0x20]; 1604 1605 u8 rpg_hai_rate[0x20]; 1606 1607 u8 rpg_gd[0x20]; 1608 1609 u8 rpg_min_dec_fac[0x20]; 1610 1611 u8 rpg_min_rate[0x20]; 1612 1613 u8 reserved_1[0x640]; 1614 }; 1615 1616 enum { 1617 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1618 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1619 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1620 }; 1621 1622 struct mlx5_ifc_resize_field_select_bits { 1623 u8 resize_field_select[0x20]; 1624 }; 1625 1626 enum { 1627 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1628 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1629 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1630 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1631 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1632 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1633 }; 1634 1635 struct mlx5_ifc_modify_field_select_bits { 1636 u8 modify_field_select[0x20]; 1637 }; 1638 1639 struct mlx5_ifc_field_select_r_roce_np_bits { 1640 u8 field_select_r_roce_np[0x20]; 1641 }; 1642 1643 enum { 1644 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1645 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1646 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1647 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1648 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1649 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1650 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1651 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1652 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1653 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1654 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1655 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1656 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1657 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1658 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1659 }; 1660 1661 struct mlx5_ifc_field_select_r_roce_rp_bits { 1662 u8 field_select_r_roce_rp[0x20]; 1663 }; 1664 1665 enum { 1666 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1667 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1668 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1669 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1670 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1671 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1672 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1673 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1674 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1675 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1676 }; 1677 1678 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1679 u8 field_select_8021qaurp[0x20]; 1680 }; 1681 1682 struct mlx5_ifc_pptb_reg_bits { 1683 u8 reserved_at_0[0x2]; 1684 u8 mm[0x2]; 1685 u8 reserved_at_4[0x4]; 1686 u8 local_port[0x8]; 1687 u8 reserved_at_10[0x6]; 1688 u8 cm[0x1]; 1689 u8 um[0x1]; 1690 u8 pm[0x8]; 1691 1692 u8 prio_x_buff[0x20]; 1693 1694 u8 pm_msb[0x8]; 1695 u8 reserved_at_48[0x10]; 1696 u8 ctrl_buff[0x4]; 1697 u8 untagged_buff[0x4]; 1698 }; 1699 1700 struct mlx5_ifc_dcbx_app_reg_bits { 1701 u8 reserved_0[0x8]; 1702 u8 port_number[0x8]; 1703 u8 reserved_1[0x10]; 1704 1705 u8 reserved_2[0x1a]; 1706 u8 num_app_prio[0x6]; 1707 1708 u8 reserved_3[0x40]; 1709 1710 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1711 }; 1712 1713 struct mlx5_ifc_dcbx_param_reg_bits { 1714 u8 dcbx_cee_cap[0x1]; 1715 u8 dcbx_ieee_cap[0x1]; 1716 u8 dcbx_standby_cap[0x1]; 1717 u8 reserved_0[0x5]; 1718 u8 port_number[0x8]; 1719 u8 reserved_1[0xa]; 1720 u8 max_application_table_size[0x6]; 1721 1722 u8 reserved_2[0x15]; 1723 u8 version_oper[0x3]; 1724 u8 reserved_3[0x5]; 1725 u8 version_admin[0x3]; 1726 1727 u8 willing_admin[0x1]; 1728 u8 reserved_4[0x3]; 1729 u8 pfc_cap_oper[0x4]; 1730 u8 reserved_5[0x4]; 1731 u8 pfc_cap_admin[0x4]; 1732 u8 reserved_6[0x4]; 1733 u8 num_of_tc_oper[0x4]; 1734 u8 reserved_7[0x4]; 1735 u8 num_of_tc_admin[0x4]; 1736 1737 u8 remote_willing[0x1]; 1738 u8 reserved_8[0x3]; 1739 u8 remote_pfc_cap[0x4]; 1740 u8 reserved_9[0x14]; 1741 u8 remote_num_of_tc[0x4]; 1742 1743 u8 reserved_10[0x18]; 1744 u8 error[0x8]; 1745 1746 u8 reserved_11[0x160]; 1747 }; 1748 1749 struct mlx5_ifc_qhll_bits { 1750 u8 reserved_at_0[0x8]; 1751 u8 local_port[0x8]; 1752 u8 reserved_at_10[0x10]; 1753 1754 u8 reserved_at_20[0x1b]; 1755 u8 hll_time[0x5]; 1756 1757 u8 stall_en[0x1]; 1758 u8 reserved_at_41[0x1c]; 1759 u8 stall_cnt[0x3]; 1760 }; 1761 1762 struct mlx5_ifc_qetcr_reg_bits { 1763 u8 operation_type[0x2]; 1764 u8 cap_local_admin[0x1]; 1765 u8 cap_remote_admin[0x1]; 1766 u8 reserved_0[0x4]; 1767 u8 port_number[0x8]; 1768 u8 reserved_1[0x10]; 1769 1770 u8 reserved_2[0x20]; 1771 1772 u8 tc[8][0x40]; 1773 1774 u8 global_configuration[0x40]; 1775 }; 1776 1777 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1778 u8 queue_address_63_32[0x20]; 1779 1780 u8 queue_address_31_12[0x14]; 1781 u8 reserved_0[0x6]; 1782 u8 log_size[0x6]; 1783 1784 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1785 1786 u8 reserved_1[0x8]; 1787 u8 queue_number[0x18]; 1788 1789 u8 q_key[0x20]; 1790 1791 u8 reserved_2[0x10]; 1792 u8 pkey_index[0x10]; 1793 1794 u8 reserved_3[0x40]; 1795 }; 1796 1797 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1798 u8 reserved_0[0x8]; 1799 u8 cq_ci[0x10]; 1800 u8 reserved_1[0x8]; 1801 }; 1802 1803 enum { 1804 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1805 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1806 }; 1807 1808 enum { 1809 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1810 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1811 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1812 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1813 }; 1814 1815 struct mlx5_ifc_nodnic_event_word_bits { 1816 u8 driver_reset_needed[0x1]; 1817 u8 port_management_change_event[0x1]; 1818 u8 reserved_0[0x19]; 1819 u8 link_type[0x1]; 1820 u8 port_state[0x4]; 1821 }; 1822 1823 struct mlx5_ifc_nic_vport_change_event_bits { 1824 u8 reserved_0[0x10]; 1825 u8 vport_num[0x10]; 1826 1827 u8 reserved_1[0xc0]; 1828 }; 1829 1830 struct mlx5_ifc_pages_req_event_bits { 1831 u8 reserved_0[0x10]; 1832 u8 function_id[0x10]; 1833 1834 u8 num_pages[0x20]; 1835 1836 u8 reserved_1[0xa0]; 1837 }; 1838 1839 struct mlx5_ifc_cmd_inter_comp_event_bits { 1840 u8 command_completion_vector[0x20]; 1841 1842 u8 reserved_0[0xc0]; 1843 }; 1844 1845 struct mlx5_ifc_stall_vl_event_bits { 1846 u8 reserved_0[0x18]; 1847 u8 port_num[0x1]; 1848 u8 reserved_1[0x3]; 1849 u8 vl[0x4]; 1850 1851 u8 reserved_2[0xa0]; 1852 }; 1853 1854 struct mlx5_ifc_db_bf_congestion_event_bits { 1855 u8 event_subtype[0x8]; 1856 u8 reserved_0[0x8]; 1857 u8 congestion_level[0x8]; 1858 u8 reserved_1[0x8]; 1859 1860 u8 reserved_2[0xa0]; 1861 }; 1862 1863 struct mlx5_ifc_gpio_event_bits { 1864 u8 reserved_0[0x60]; 1865 1866 u8 gpio_event_hi[0x20]; 1867 1868 u8 gpio_event_lo[0x20]; 1869 1870 u8 reserved_1[0x40]; 1871 }; 1872 1873 struct mlx5_ifc_port_state_change_event_bits { 1874 u8 reserved_0[0x40]; 1875 1876 u8 port_num[0x4]; 1877 u8 reserved_1[0x1c]; 1878 1879 u8 reserved_2[0x80]; 1880 }; 1881 1882 struct mlx5_ifc_dropped_packet_logged_bits { 1883 u8 reserved_0[0xe0]; 1884 }; 1885 1886 enum { 1887 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1888 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1889 }; 1890 1891 struct mlx5_ifc_cq_error_bits { 1892 u8 reserved_0[0x8]; 1893 u8 cqn[0x18]; 1894 1895 u8 reserved_1[0x20]; 1896 1897 u8 reserved_2[0x18]; 1898 u8 syndrome[0x8]; 1899 1900 u8 reserved_3[0x80]; 1901 }; 1902 1903 struct mlx5_ifc_rdma_page_fault_event_bits { 1904 u8 bytes_commited[0x20]; 1905 1906 u8 r_key[0x20]; 1907 1908 u8 reserved_0[0x10]; 1909 u8 packet_len[0x10]; 1910 1911 u8 rdma_op_len[0x20]; 1912 1913 u8 rdma_va[0x40]; 1914 1915 u8 reserved_1[0x5]; 1916 u8 rdma[0x1]; 1917 u8 write[0x1]; 1918 u8 requestor[0x1]; 1919 u8 qp_number[0x18]; 1920 }; 1921 1922 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1923 u8 bytes_committed[0x20]; 1924 1925 u8 reserved_0[0x10]; 1926 u8 wqe_index[0x10]; 1927 1928 u8 reserved_1[0x10]; 1929 u8 len[0x10]; 1930 1931 u8 reserved_2[0x60]; 1932 1933 u8 reserved_3[0x5]; 1934 u8 rdma[0x1]; 1935 u8 write_read[0x1]; 1936 u8 requestor[0x1]; 1937 u8 qpn[0x18]; 1938 }; 1939 1940 enum { 1941 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1942 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1943 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1944 }; 1945 1946 struct mlx5_ifc_qp_events_bits { 1947 u8 reserved_0[0xa0]; 1948 1949 u8 type[0x8]; 1950 u8 reserved_1[0x18]; 1951 1952 u8 reserved_2[0x8]; 1953 u8 qpn_rqn_sqn[0x18]; 1954 }; 1955 1956 struct mlx5_ifc_dct_events_bits { 1957 u8 reserved_0[0xc0]; 1958 1959 u8 reserved_1[0x8]; 1960 u8 dct_number[0x18]; 1961 }; 1962 1963 struct mlx5_ifc_comp_event_bits { 1964 u8 reserved_0[0xc0]; 1965 1966 u8 reserved_1[0x8]; 1967 u8 cq_number[0x18]; 1968 }; 1969 1970 struct mlx5_ifc_fw_version_bits { 1971 u8 major[0x10]; 1972 u8 reserved_0[0x10]; 1973 1974 u8 minor[0x10]; 1975 u8 subminor[0x10]; 1976 1977 u8 second[0x8]; 1978 u8 minute[0x8]; 1979 u8 hour[0x8]; 1980 u8 reserved_1[0x8]; 1981 1982 u8 year[0x10]; 1983 u8 month[0x8]; 1984 u8 day[0x8]; 1985 }; 1986 1987 enum { 1988 MLX5_QPC_STATE_RST = 0x0, 1989 MLX5_QPC_STATE_INIT = 0x1, 1990 MLX5_QPC_STATE_RTR = 0x2, 1991 MLX5_QPC_STATE_RTS = 0x3, 1992 MLX5_QPC_STATE_SQER = 0x4, 1993 MLX5_QPC_STATE_SQD = 0x5, 1994 MLX5_QPC_STATE_ERR = 0x6, 1995 MLX5_QPC_STATE_SUSPENDED = 0x9, 1996 }; 1997 1998 enum { 1999 MLX5_QPC_ST_RC = 0x0, 2000 MLX5_QPC_ST_UC = 0x1, 2001 MLX5_QPC_ST_UD = 0x2, 2002 MLX5_QPC_ST_XRC = 0x3, 2003 MLX5_QPC_ST_DCI = 0x5, 2004 MLX5_QPC_ST_QP0 = 0x7, 2005 MLX5_QPC_ST_QP1 = 0x8, 2006 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2007 MLX5_QPC_ST_REG_UMR = 0xc, 2008 }; 2009 2010 enum { 2011 MLX5_QP_PM_ARMED = 0x0, 2012 MLX5_QP_PM_REARM = 0x1, 2013 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2014 MLX5_QP_PM_MIGRATED = 0x3, 2015 }; 2016 2017 enum { 2018 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2019 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2020 }; 2021 2022 enum { 2023 MLX5_QPC_MTU_256_BYTES = 0x1, 2024 MLX5_QPC_MTU_512_BYTES = 0x2, 2025 MLX5_QPC_MTU_1K_BYTES = 0x3, 2026 MLX5_QPC_MTU_2K_BYTES = 0x4, 2027 MLX5_QPC_MTU_4K_BYTES = 0x5, 2028 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2029 }; 2030 2031 enum { 2032 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2033 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2034 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2035 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2036 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2037 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2038 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2039 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2040 }; 2041 2042 enum { 2043 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2044 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2045 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2046 }; 2047 2048 enum { 2049 MLX5_QPC_CS_RES_DISABLE = 0x0, 2050 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2051 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2052 }; 2053 2054 enum { 2055 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2056 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2057 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2058 }; 2059 2060 struct mlx5_ifc_qpc_bits { 2061 u8 state[0x4]; 2062 u8 lag_tx_port_affinity[0x4]; 2063 u8 st[0x8]; 2064 u8 reserved_1[0x3]; 2065 u8 pm_state[0x2]; 2066 u8 reserved_2[0x7]; 2067 u8 end_padding_mode[0x2]; 2068 u8 reserved_3[0x2]; 2069 2070 u8 wq_signature[0x1]; 2071 u8 block_lb_mc[0x1]; 2072 u8 atomic_like_write_en[0x1]; 2073 u8 latency_sensitive[0x1]; 2074 u8 reserved_4[0x1]; 2075 u8 drain_sigerr[0x1]; 2076 u8 reserved_5[0x2]; 2077 u8 pd[0x18]; 2078 2079 u8 mtu[0x3]; 2080 u8 log_msg_max[0x5]; 2081 u8 reserved_6[0x1]; 2082 u8 log_rq_size[0x4]; 2083 u8 log_rq_stride[0x3]; 2084 u8 no_sq[0x1]; 2085 u8 log_sq_size[0x4]; 2086 u8 reserved_at_55[0x3]; 2087 u8 ts_format[0x2]; 2088 u8 reserved_at_5a[0x1]; 2089 u8 rlky[0x1]; 2090 u8 ulp_stateless_offload_mode[0x4]; 2091 2092 u8 counter_set_id[0x8]; 2093 u8 uar_page[0x18]; 2094 2095 u8 reserved_8[0x8]; 2096 u8 user_index[0x18]; 2097 2098 u8 reserved_9[0x3]; 2099 u8 log_page_size[0x5]; 2100 u8 remote_qpn[0x18]; 2101 2102 struct mlx5_ifc_ads_bits primary_address_path; 2103 2104 struct mlx5_ifc_ads_bits secondary_address_path; 2105 2106 u8 log_ack_req_freq[0x4]; 2107 u8 reserved_10[0x4]; 2108 u8 log_sra_max[0x3]; 2109 u8 reserved_11[0x2]; 2110 u8 retry_count[0x3]; 2111 u8 rnr_retry[0x3]; 2112 u8 reserved_12[0x1]; 2113 u8 fre[0x1]; 2114 u8 cur_rnr_retry[0x3]; 2115 u8 cur_retry_count[0x3]; 2116 u8 reserved_13[0x5]; 2117 2118 u8 reserved_14[0x20]; 2119 2120 u8 reserved_15[0x8]; 2121 u8 next_send_psn[0x18]; 2122 2123 u8 reserved_16[0x8]; 2124 u8 cqn_snd[0x18]; 2125 2126 u8 reserved_at_400[0x8]; 2127 2128 u8 deth_sqpn[0x18]; 2129 u8 reserved_17[0x20]; 2130 2131 u8 reserved_18[0x8]; 2132 u8 last_acked_psn[0x18]; 2133 2134 u8 reserved_19[0x8]; 2135 u8 ssn[0x18]; 2136 2137 u8 reserved_20[0x8]; 2138 u8 log_rra_max[0x3]; 2139 u8 reserved_21[0x1]; 2140 u8 atomic_mode[0x4]; 2141 u8 rre[0x1]; 2142 u8 rwe[0x1]; 2143 u8 rae[0x1]; 2144 u8 reserved_22[0x1]; 2145 u8 page_offset[0x6]; 2146 u8 reserved_23[0x3]; 2147 u8 cd_slave_receive[0x1]; 2148 u8 cd_slave_send[0x1]; 2149 u8 cd_master[0x1]; 2150 2151 u8 reserved_24[0x3]; 2152 u8 min_rnr_nak[0x5]; 2153 u8 next_rcv_psn[0x18]; 2154 2155 u8 reserved_25[0x8]; 2156 u8 xrcd[0x18]; 2157 2158 u8 reserved_26[0x8]; 2159 u8 cqn_rcv[0x18]; 2160 2161 u8 dbr_addr[0x40]; 2162 2163 u8 q_key[0x20]; 2164 2165 u8 reserved_27[0x5]; 2166 u8 rq_type[0x3]; 2167 u8 srqn_rmpn[0x18]; 2168 2169 u8 reserved_28[0x8]; 2170 u8 rmsn[0x18]; 2171 2172 u8 hw_sq_wqebb_counter[0x10]; 2173 u8 sw_sq_wqebb_counter[0x10]; 2174 2175 u8 hw_rq_counter[0x20]; 2176 2177 u8 sw_rq_counter[0x20]; 2178 2179 u8 reserved_29[0x20]; 2180 2181 u8 reserved_30[0xf]; 2182 u8 cgs[0x1]; 2183 u8 cs_req[0x8]; 2184 u8 cs_res[0x8]; 2185 2186 u8 dc_access_key[0x40]; 2187 2188 u8 reserved_at_680[0x3]; 2189 u8 dbr_umem_valid[0x1]; 2190 2191 u8 reserved_at_684[0xbc]; 2192 }; 2193 2194 struct mlx5_ifc_roce_addr_layout_bits { 2195 u8 source_l3_address[16][0x8]; 2196 2197 u8 reserved_0[0x3]; 2198 u8 vlan_valid[0x1]; 2199 u8 vlan_id[0xc]; 2200 u8 source_mac_47_32[0x10]; 2201 2202 u8 source_mac_31_0[0x20]; 2203 2204 u8 reserved_1[0x14]; 2205 u8 roce_l3_type[0x4]; 2206 u8 roce_version[0x8]; 2207 2208 u8 reserved_2[0x20]; 2209 }; 2210 2211 struct mlx5_ifc_rdbc_bits { 2212 u8 reserved_0[0x1c]; 2213 u8 type[0x4]; 2214 2215 u8 reserved_1[0x20]; 2216 2217 u8 reserved_2[0x8]; 2218 u8 psn[0x18]; 2219 2220 u8 rkey[0x20]; 2221 2222 u8 address[0x40]; 2223 2224 u8 byte_count[0x20]; 2225 2226 u8 reserved_3[0x20]; 2227 2228 u8 atomic_resp[32][0x8]; 2229 }; 2230 2231 enum { 2232 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2233 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2234 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2235 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2236 }; 2237 2238 struct mlx5_ifc_flow_context_bits { 2239 u8 reserved_0[0x20]; 2240 2241 u8 group_id[0x20]; 2242 2243 u8 reserved_1[0x8]; 2244 u8 flow_tag[0x18]; 2245 2246 u8 reserved_2[0x10]; 2247 u8 action[0x10]; 2248 2249 u8 reserved_3[0x8]; 2250 u8 destination_list_size[0x18]; 2251 2252 u8 reserved_4[0x8]; 2253 u8 flow_counter_list_size[0x18]; 2254 2255 u8 reserved_5[0x140]; 2256 2257 struct mlx5_ifc_fte_match_param_bits match_value; 2258 2259 u8 reserved_6[0x600]; 2260 2261 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2262 }; 2263 2264 enum { 2265 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2266 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2267 }; 2268 2269 struct mlx5_ifc_xrc_srqc_bits { 2270 u8 state[0x4]; 2271 u8 log_xrc_srq_size[0x4]; 2272 u8 reserved_0[0x18]; 2273 2274 u8 wq_signature[0x1]; 2275 u8 cont_srq[0x1]; 2276 u8 reserved_1[0x1]; 2277 u8 rlky[0x1]; 2278 u8 basic_cyclic_rcv_wqe[0x1]; 2279 u8 log_rq_stride[0x3]; 2280 u8 xrcd[0x18]; 2281 2282 u8 page_offset[0x6]; 2283 u8 reserved_at_46[0x1]; 2284 u8 dbr_umem_valid[0x1]; 2285 u8 cqn[0x18]; 2286 2287 u8 reserved_3[0x20]; 2288 2289 u8 reserved_4[0x2]; 2290 u8 log_page_size[0x6]; 2291 u8 user_index[0x18]; 2292 2293 u8 reserved_5[0x20]; 2294 2295 u8 reserved_6[0x8]; 2296 u8 pd[0x18]; 2297 2298 u8 lwm[0x10]; 2299 u8 wqe_cnt[0x10]; 2300 2301 u8 reserved_7[0x40]; 2302 2303 u8 db_record_addr_h[0x20]; 2304 2305 u8 db_record_addr_l[0x1e]; 2306 u8 reserved_8[0x2]; 2307 2308 u8 reserved_9[0x80]; 2309 }; 2310 2311 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2312 u8 counter_error_queues[0x20]; 2313 2314 u8 total_error_queues[0x20]; 2315 2316 u8 send_queue_priority_update_flow[0x20]; 2317 2318 u8 reserved_at_60[0x20]; 2319 2320 u8 nic_receive_steering_discard[0x40]; 2321 2322 u8 receive_discard_vport_down[0x40]; 2323 2324 u8 transmit_discard_vport_down[0x40]; 2325 2326 u8 reserved_at_140[0xec0]; 2327 }; 2328 2329 struct mlx5_ifc_traffic_counter_bits { 2330 u8 packets[0x40]; 2331 2332 u8 octets[0x40]; 2333 }; 2334 2335 struct mlx5_ifc_tisc_bits { 2336 u8 strict_lag_tx_port_affinity[0x1]; 2337 u8 tls_en[0x1]; 2338 u8 reserved_at_2[0x2]; 2339 u8 lag_tx_port_affinity[0x04]; 2340 2341 u8 reserved_at_8[0x4]; 2342 u8 prio[0x4]; 2343 u8 reserved_1[0x10]; 2344 2345 u8 reserved_2[0x100]; 2346 2347 u8 reserved_3[0x8]; 2348 u8 transport_domain[0x18]; 2349 2350 u8 reserved_4[0x8]; 2351 u8 underlay_qpn[0x18]; 2352 2353 u8 reserved_5[0x8]; 2354 u8 pd[0x18]; 2355 2356 u8 reserved_6[0x380]; 2357 }; 2358 2359 enum { 2360 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2361 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2362 }; 2363 2364 enum { 2365 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2366 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2367 }; 2368 2369 enum { 2370 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2371 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2372 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2373 }; 2374 2375 enum { 2376 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2377 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2378 }; 2379 2380 struct mlx5_ifc_tirc_bits { 2381 u8 reserved_0[0x20]; 2382 2383 u8 disp_type[0x4]; 2384 u8 tls_en[0x1]; 2385 u8 reserved_at_25[0x1b]; 2386 2387 u8 reserved_2[0x40]; 2388 2389 u8 reserved_3[0x4]; 2390 u8 lro_timeout_period_usecs[0x10]; 2391 u8 lro_enable_mask[0x4]; 2392 u8 lro_max_msg_sz[0x8]; 2393 2394 u8 reserved_4[0x40]; 2395 2396 u8 reserved_5[0x8]; 2397 u8 inline_rqn[0x18]; 2398 2399 u8 rx_hash_symmetric[0x1]; 2400 u8 reserved_6[0x1]; 2401 u8 tunneled_offload_en[0x1]; 2402 u8 reserved_7[0x5]; 2403 u8 indirect_table[0x18]; 2404 2405 u8 rx_hash_fn[0x4]; 2406 u8 reserved_8[0x2]; 2407 u8 self_lb_en[0x2]; 2408 u8 transport_domain[0x18]; 2409 2410 u8 rx_hash_toeplitz_key[10][0x20]; 2411 2412 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2413 2414 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2415 2416 u8 reserved_9[0x4c0]; 2417 }; 2418 2419 enum { 2420 MLX5_SRQC_STATE_GOOD = 0x0, 2421 MLX5_SRQC_STATE_ERROR = 0x1, 2422 }; 2423 2424 struct mlx5_ifc_srqc_bits { 2425 u8 state[0x4]; 2426 u8 log_srq_size[0x4]; 2427 u8 reserved_0[0x18]; 2428 2429 u8 wq_signature[0x1]; 2430 u8 cont_srq[0x1]; 2431 u8 reserved_1[0x1]; 2432 u8 rlky[0x1]; 2433 u8 reserved_2[0x1]; 2434 u8 log_rq_stride[0x3]; 2435 u8 xrcd[0x18]; 2436 2437 u8 page_offset[0x6]; 2438 u8 reserved_3[0x2]; 2439 u8 cqn[0x18]; 2440 2441 u8 reserved_4[0x20]; 2442 2443 u8 reserved_5[0x2]; 2444 u8 log_page_size[0x6]; 2445 u8 reserved_6[0x18]; 2446 2447 u8 reserved_7[0x20]; 2448 2449 u8 reserved_8[0x8]; 2450 u8 pd[0x18]; 2451 2452 u8 lwm[0x10]; 2453 u8 wqe_cnt[0x10]; 2454 2455 u8 reserved_9[0x40]; 2456 2457 u8 dbr_addr[0x40]; 2458 2459 u8 reserved_10[0x80]; 2460 }; 2461 2462 enum { 2463 MLX5_SQC_STATE_RST = 0x0, 2464 MLX5_SQC_STATE_RDY = 0x1, 2465 MLX5_SQC_STATE_ERR = 0x3, 2466 }; 2467 2468 enum { 2469 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2470 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2471 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2472 }; 2473 2474 struct mlx5_ifc_sqc_bits { 2475 u8 rlkey[0x1]; 2476 u8 cd_master[0x1]; 2477 u8 fre[0x1]; 2478 u8 flush_in_error_en[0x1]; 2479 u8 allow_multi_pkt_send_wqe[0x1]; 2480 u8 min_wqe_inline_mode[0x3]; 2481 u8 state[0x4]; 2482 u8 reg_umr[0x1]; 2483 u8 allow_swp[0x1]; 2484 u8 reserved_at_e[0x4]; 2485 u8 qos_remap_en[0x1]; 2486 u8 reserved_at_d[0x7]; 2487 u8 ts_format[0x2]; 2488 u8 reserved_at_1c[0x4]; 2489 2490 u8 reserved_1[0x8]; 2491 u8 user_index[0x18]; 2492 2493 u8 reserved_2[0x8]; 2494 u8 cqn[0x18]; 2495 2496 u8 reserved_3[0x80]; 2497 2498 u8 qos_para_vport_number[0x10]; 2499 u8 packet_pacing_rate_limit_index[0x10]; 2500 2501 u8 tis_lst_sz[0x10]; 2502 u8 qos_queue_group_id[0x10]; 2503 2504 u8 reserved_4[0x8]; 2505 u8 queue_handle[0x18]; 2506 2507 u8 reserved_5[0x20]; 2508 2509 u8 reserved_6[0x8]; 2510 u8 tis_num_0[0x18]; 2511 2512 struct mlx5_ifc_wq_bits wq; 2513 }; 2514 2515 struct mlx5_ifc_query_pp_rate_limit_in_bits { 2516 u8 opcode[0x10]; 2517 u8 uid[0x10]; 2518 2519 u8 reserved1[0x10]; 2520 u8 op_mod[0x10]; 2521 2522 u8 reserved2[0x10]; 2523 u8 rate_limit_index[0x10]; 2524 2525 u8 reserved_3[0x20]; 2526 }; 2527 2528 struct mlx5_ifc_pp_context_bits { 2529 u8 rate_limit[0x20]; 2530 2531 u8 burst_upper_bound[0x20]; 2532 2533 u8 reserved_1[0xc]; 2534 u8 rate_mode[0x4]; 2535 u8 typical_packet_size[0x10]; 2536 2537 u8 reserved_2[0x8]; 2538 u8 qos_handle[0x18]; 2539 2540 u8 reserved_3[0x40]; 2541 }; 2542 2543 struct mlx5_ifc_query_pp_rate_limit_out_bits { 2544 u8 status[0x8]; 2545 u8 reserved_1[0x18]; 2546 2547 u8 syndrome[0x20]; 2548 2549 u8 reserved_2[0x40]; 2550 2551 struct mlx5_ifc_pp_context_bits pp_context; 2552 }; 2553 2554 enum { 2555 MLX5_TSAR_TYPE_DWRR = 0, 2556 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2557 MLX5_TSAR_TYPE_ETS = 2 2558 }; 2559 2560 struct mlx5_ifc_tsar_element_attributes_bits { 2561 u8 reserved_0[0x8]; 2562 u8 tsar_type[0x8]; 2563 u8 reserved_1[0x10]; 2564 }; 2565 2566 struct mlx5_ifc_vport_element_attributes_bits { 2567 u8 reserved_0[0x10]; 2568 u8 vport_number[0x10]; 2569 }; 2570 2571 struct mlx5_ifc_vport_tc_element_attributes_bits { 2572 u8 traffic_class[0x10]; 2573 u8 vport_number[0x10]; 2574 }; 2575 2576 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2577 u8 reserved_0[0x0C]; 2578 u8 traffic_class[0x04]; 2579 u8 qos_para_vport_number[0x10]; 2580 }; 2581 2582 enum { 2583 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2584 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2585 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2586 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2587 }; 2588 2589 struct mlx5_ifc_scheduling_context_bits { 2590 u8 element_type[0x8]; 2591 u8 reserved_at_8[0x18]; 2592 2593 u8 element_attributes[0x20]; 2594 2595 u8 parent_element_id[0x20]; 2596 2597 u8 reserved_at_60[0x40]; 2598 2599 u8 bw_share[0x20]; 2600 2601 u8 max_average_bw[0x20]; 2602 2603 u8 reserved_at_e0[0x120]; 2604 }; 2605 2606 struct mlx5_ifc_rqtc_bits { 2607 u8 reserved_0[0xa0]; 2608 2609 u8 reserved_1[0x10]; 2610 u8 rqt_max_size[0x10]; 2611 2612 u8 reserved_2[0x10]; 2613 u8 rqt_actual_size[0x10]; 2614 2615 u8 reserved_3[0x6a0]; 2616 2617 struct mlx5_ifc_rq_num_bits rq_num[0]; 2618 }; 2619 2620 enum { 2621 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2622 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2623 }; 2624 2625 enum { 2626 MLX5_RQC_STATE_RST = 0x0, 2627 MLX5_RQC_STATE_RDY = 0x1, 2628 MLX5_RQC_STATE_ERR = 0x3, 2629 }; 2630 2631 enum { 2632 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2633 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2634 }; 2635 2636 enum { 2637 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2638 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2639 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2640 }; 2641 2642 struct mlx5_ifc_rqc_bits { 2643 u8 rlkey[0x1]; 2644 u8 delay_drop_en[0x1]; 2645 u8 scatter_fcs[0x1]; 2646 u8 vlan_strip_disable[0x1]; 2647 u8 mem_rq_type[0x4]; 2648 u8 state[0x4]; 2649 u8 reserved_1[0x1]; 2650 u8 flush_in_error_en[0x1]; 2651 u8 reserved_at_e[0xc]; 2652 u8 ts_format[0x2]; 2653 u8 reserved_at_1c[0x4]; 2654 2655 u8 reserved_3[0x8]; 2656 u8 user_index[0x18]; 2657 2658 u8 reserved_4[0x8]; 2659 u8 cqn[0x18]; 2660 2661 u8 counter_set_id[0x8]; 2662 u8 reserved_5[0x18]; 2663 2664 u8 reserved_6[0x8]; 2665 u8 rmpn[0x18]; 2666 2667 u8 reserved_7[0xe0]; 2668 2669 struct mlx5_ifc_wq_bits wq; 2670 }; 2671 2672 enum { 2673 MLX5_RMPC_STATE_RDY = 0x1, 2674 MLX5_RMPC_STATE_ERR = 0x3, 2675 }; 2676 2677 struct mlx5_ifc_rmpc_bits { 2678 u8 reserved_0[0x8]; 2679 u8 state[0x4]; 2680 u8 reserved_1[0x14]; 2681 2682 u8 basic_cyclic_rcv_wqe[0x1]; 2683 u8 reserved_2[0x1f]; 2684 2685 u8 reserved_3[0x140]; 2686 2687 struct mlx5_ifc_wq_bits wq; 2688 }; 2689 2690 enum { 2691 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2692 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2693 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2694 }; 2695 2696 struct mlx5_ifc_nic_vport_context_bits { 2697 u8 reserved_0[0x5]; 2698 u8 min_wqe_inline_mode[0x3]; 2699 u8 reserved_1[0x15]; 2700 u8 disable_mc_local_lb[0x1]; 2701 u8 disable_uc_local_lb[0x1]; 2702 u8 roce_en[0x1]; 2703 2704 u8 arm_change_event[0x1]; 2705 u8 reserved_2[0x1a]; 2706 u8 event_on_mtu[0x1]; 2707 u8 event_on_promisc_change[0x1]; 2708 u8 event_on_vlan_change[0x1]; 2709 u8 event_on_mc_address_change[0x1]; 2710 u8 event_on_uc_address_change[0x1]; 2711 2712 u8 reserved_3[0xe0]; 2713 2714 u8 reserved_4[0x10]; 2715 u8 mtu[0x10]; 2716 2717 u8 system_image_guid[0x40]; 2718 2719 u8 port_guid[0x40]; 2720 2721 u8 node_guid[0x40]; 2722 2723 u8 reserved_5[0x140]; 2724 2725 u8 qkey_violation_counter[0x10]; 2726 u8 reserved_6[0x10]; 2727 2728 u8 reserved_7[0x420]; 2729 2730 u8 promisc_uc[0x1]; 2731 u8 promisc_mc[0x1]; 2732 u8 promisc_all[0x1]; 2733 u8 reserved_8[0x2]; 2734 u8 allowed_list_type[0x3]; 2735 u8 reserved_9[0xc]; 2736 u8 allowed_list_size[0xc]; 2737 2738 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2739 2740 u8 reserved_10[0x20]; 2741 2742 u8 current_uc_mac_address[0][0x40]; 2743 }; 2744 2745 enum { 2746 MLX5_ACCESS_MODE_PA = 0x0, 2747 MLX5_ACCESS_MODE_MTT = 0x1, 2748 MLX5_ACCESS_MODE_KLM = 0x2, 2749 MLX5_ACCESS_MODE_KSM = 0x3, 2750 MLX5_ACCESS_MODE_SW_ICM = 0x4, 2751 MLX5_ACCESS_MODE_MEMIC = 0x5, 2752 }; 2753 2754 struct mlx5_ifc_mkc_bits { 2755 u8 reserved_at_0[0x1]; 2756 u8 free[0x1]; 2757 u8 reserved_at_2[0x1]; 2758 u8 access_mode_4_2[0x3]; 2759 u8 reserved_at_6[0x7]; 2760 u8 relaxed_ordering_write[0x1]; 2761 u8 reserved_at_e[0x1]; 2762 u8 small_fence_on_rdma_read_response[0x1]; 2763 u8 umr_en[0x1]; 2764 u8 a[0x1]; 2765 u8 rw[0x1]; 2766 u8 rr[0x1]; 2767 u8 lw[0x1]; 2768 u8 lr[0x1]; 2769 u8 access_mode[0x2]; 2770 u8 reserved_2[0x8]; 2771 2772 u8 qpn[0x18]; 2773 u8 mkey_7_0[0x8]; 2774 2775 u8 reserved_3[0x20]; 2776 2777 u8 length64[0x1]; 2778 u8 bsf_en[0x1]; 2779 u8 sync_umr[0x1]; 2780 u8 reserved_4[0x2]; 2781 u8 expected_sigerr_count[0x1]; 2782 u8 reserved_5[0x1]; 2783 u8 en_rinval[0x1]; 2784 u8 pd[0x18]; 2785 2786 u8 start_addr[0x40]; 2787 2788 u8 len[0x40]; 2789 2790 u8 bsf_octword_size[0x20]; 2791 2792 u8 reserved_6[0x80]; 2793 2794 u8 translations_octword_size[0x20]; 2795 2796 u8 reserved_at_1c0[0x19]; 2797 u8 relaxed_ordering_read[0x1]; 2798 u8 reserved_at_1d9[0x1]; 2799 u8 log_page_size[0x5]; 2800 2801 u8 reserved_8[0x20]; 2802 }; 2803 2804 struct mlx5_ifc_pkey_bits { 2805 u8 reserved_0[0x10]; 2806 u8 pkey[0x10]; 2807 }; 2808 2809 struct mlx5_ifc_array128_auto_bits { 2810 u8 array128_auto[16][0x8]; 2811 }; 2812 2813 enum { 2814 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2815 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2816 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2817 }; 2818 2819 enum { 2820 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2821 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2822 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2823 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2824 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2825 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2826 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2827 }; 2828 2829 enum { 2830 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2831 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2832 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2833 }; 2834 2835 enum { 2836 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2837 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2838 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2839 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2840 }; 2841 2842 enum { 2843 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2844 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2845 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2846 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2847 }; 2848 2849 struct mlx5_ifc_hca_vport_context_bits { 2850 u8 field_select[0x20]; 2851 2852 u8 reserved_0[0xe0]; 2853 2854 u8 sm_virt_aware[0x1]; 2855 u8 has_smi[0x1]; 2856 u8 has_raw[0x1]; 2857 u8 grh_required[0x1]; 2858 u8 reserved_1[0x1]; 2859 u8 min_wqe_inline_mode[0x3]; 2860 u8 reserved_2[0x8]; 2861 u8 port_physical_state[0x4]; 2862 u8 vport_state_policy[0x4]; 2863 u8 port_state[0x4]; 2864 u8 vport_state[0x4]; 2865 2866 u8 reserved_3[0x20]; 2867 2868 u8 system_image_guid[0x40]; 2869 2870 u8 port_guid[0x40]; 2871 2872 u8 node_guid[0x40]; 2873 2874 u8 cap_mask1[0x20]; 2875 2876 u8 cap_mask1_field_select[0x20]; 2877 2878 u8 cap_mask2[0x20]; 2879 2880 u8 cap_mask2_field_select[0x20]; 2881 2882 u8 reserved_4[0x80]; 2883 2884 u8 lid[0x10]; 2885 u8 reserved_5[0x4]; 2886 u8 init_type_reply[0x4]; 2887 u8 lmc[0x3]; 2888 u8 subnet_timeout[0x5]; 2889 2890 u8 sm_lid[0x10]; 2891 u8 sm_sl[0x4]; 2892 u8 reserved_6[0xc]; 2893 2894 u8 qkey_violation_counter[0x10]; 2895 u8 pkey_violation_counter[0x10]; 2896 2897 u8 reserved_7[0xca0]; 2898 }; 2899 2900 union mlx5_ifc_hca_cap_union_bits { 2901 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2902 struct mlx5_ifc_odp_cap_bits odp_cap; 2903 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2904 struct mlx5_ifc_roce_cap_bits roce_cap; 2905 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2906 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2907 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2908 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2909 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2910 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2911 struct mlx5_ifc_qos_cap_bits qos_cap; 2912 struct mlx5_ifc_tls_capabilities_bits tls_capabilities; 2913 u8 reserved_0[0x8000]; 2914 }; 2915 2916 enum { 2917 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2918 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2919 }; 2920 2921 struct mlx5_ifc_flow_table_context_bits { 2922 u8 encap_en[0x1]; 2923 u8 decap_en[0x1]; 2924 u8 reserved_at_2[0x2]; 2925 u8 table_miss_action[0x4]; 2926 u8 level[0x8]; 2927 u8 reserved_at_10[0x8]; 2928 u8 log_size[0x8]; 2929 2930 u8 reserved_at_20[0x8]; 2931 u8 table_miss_id[0x18]; 2932 2933 u8 reserved_at_40[0x8]; 2934 u8 lag_master_next_table_id[0x18]; 2935 2936 u8 reserved_at_60[0xe0]; 2937 }; 2938 2939 struct mlx5_ifc_esw_vport_context_bits { 2940 u8 reserved_0[0x3]; 2941 u8 vport_svlan_strip[0x1]; 2942 u8 vport_cvlan_strip[0x1]; 2943 u8 vport_svlan_insert[0x1]; 2944 u8 vport_cvlan_insert[0x2]; 2945 u8 reserved_1[0x18]; 2946 2947 u8 reserved_2[0x20]; 2948 2949 u8 svlan_cfi[0x1]; 2950 u8 svlan_pcp[0x3]; 2951 u8 svlan_id[0xc]; 2952 u8 cvlan_cfi[0x1]; 2953 u8 cvlan_pcp[0x3]; 2954 u8 cvlan_id[0xc]; 2955 2956 u8 reserved_3[0x7a0]; 2957 }; 2958 2959 enum { 2960 MLX5_EQC_STATUS_OK = 0x0, 2961 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2962 }; 2963 2964 enum { 2965 MLX5_EQ_STATE_ARMED = 0x9, 2966 MLX5_EQ_STATE_FIRED = 0xa, 2967 }; 2968 2969 struct mlx5_ifc_eqc_bits { 2970 u8 status[0x4]; 2971 u8 reserved_0[0x9]; 2972 u8 ec[0x1]; 2973 u8 oi[0x1]; 2974 u8 reserved_1[0x5]; 2975 u8 st[0x4]; 2976 u8 reserved_2[0x8]; 2977 2978 u8 reserved_3[0x20]; 2979 2980 u8 reserved_4[0x14]; 2981 u8 page_offset[0x6]; 2982 u8 reserved_5[0x6]; 2983 2984 u8 reserved_6[0x3]; 2985 u8 log_eq_size[0x5]; 2986 u8 uar_page[0x18]; 2987 2988 u8 reserved_7[0x20]; 2989 2990 u8 reserved_8[0x18]; 2991 u8 intr[0x8]; 2992 2993 u8 reserved_9[0x3]; 2994 u8 log_page_size[0x5]; 2995 u8 reserved_10[0x18]; 2996 2997 u8 reserved_11[0x60]; 2998 2999 u8 reserved_12[0x8]; 3000 u8 consumer_counter[0x18]; 3001 3002 u8 reserved_13[0x8]; 3003 u8 producer_counter[0x18]; 3004 3005 u8 reserved_14[0x80]; 3006 }; 3007 3008 enum { 3009 MLX5_DCTC_STATE_ACTIVE = 0x0, 3010 MLX5_DCTC_STATE_DRAINING = 0x1, 3011 MLX5_DCTC_STATE_DRAINED = 0x2, 3012 }; 3013 3014 enum { 3015 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3016 MLX5_DCTC_CS_RES_NA = 0x1, 3017 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3018 }; 3019 3020 enum { 3021 MLX5_DCTC_MTU_256_BYTES = 0x1, 3022 MLX5_DCTC_MTU_512_BYTES = 0x2, 3023 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3024 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3025 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3026 }; 3027 3028 struct mlx5_ifc_dctc_bits { 3029 u8 reserved_0[0x4]; 3030 u8 state[0x4]; 3031 u8 reserved_1[0x18]; 3032 3033 u8 reserved_2[0x8]; 3034 u8 user_index[0x18]; 3035 3036 u8 reserved_3[0x8]; 3037 u8 cqn[0x18]; 3038 3039 u8 counter_set_id[0x8]; 3040 u8 atomic_mode[0x4]; 3041 u8 rre[0x1]; 3042 u8 rwe[0x1]; 3043 u8 rae[0x1]; 3044 u8 atomic_like_write_en[0x1]; 3045 u8 latency_sensitive[0x1]; 3046 u8 rlky[0x1]; 3047 u8 reserved_4[0xe]; 3048 3049 u8 reserved_5[0x8]; 3050 u8 cs_res[0x8]; 3051 u8 reserved_6[0x3]; 3052 u8 min_rnr_nak[0x5]; 3053 u8 reserved_7[0x8]; 3054 3055 u8 reserved_8[0x8]; 3056 u8 srqn[0x18]; 3057 3058 u8 reserved_9[0x8]; 3059 u8 pd[0x18]; 3060 3061 u8 tclass[0x8]; 3062 u8 reserved_10[0x4]; 3063 u8 flow_label[0x14]; 3064 3065 u8 dc_access_key[0x40]; 3066 3067 u8 reserved_11[0x5]; 3068 u8 mtu[0x3]; 3069 u8 port[0x8]; 3070 u8 pkey_index[0x10]; 3071 3072 u8 reserved_12[0x8]; 3073 u8 my_addr_index[0x8]; 3074 u8 reserved_13[0x8]; 3075 u8 hop_limit[0x8]; 3076 3077 u8 dc_access_key_violation_count[0x20]; 3078 3079 u8 reserved_14[0x14]; 3080 u8 dei_cfi[0x1]; 3081 u8 eth_prio[0x3]; 3082 u8 ecn[0x2]; 3083 u8 dscp[0x6]; 3084 3085 u8 reserved_15[0x40]; 3086 }; 3087 3088 enum { 3089 MLX5_CQC_STATUS_OK = 0x0, 3090 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3091 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3092 }; 3093 3094 enum { 3095 CQE_SIZE_64 = 0x0, 3096 CQE_SIZE_128 = 0x1, 3097 }; 3098 3099 enum { 3100 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3101 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3102 }; 3103 3104 enum { 3105 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 3106 MLX5_CQ_STATE_ARMED = 0x9, 3107 MLX5_CQ_STATE_FIRED = 0xa, 3108 }; 3109 3110 struct mlx5_ifc_cqc_bits { 3111 u8 status[0x4]; 3112 u8 reserved_at_4[0x2]; 3113 u8 dbr_umem_valid[0x1]; 3114 u8 reserved_at_7[0x1]; 3115 u8 cqe_sz[0x3]; 3116 u8 cc[0x1]; 3117 u8 reserved_1[0x1]; 3118 u8 scqe_break_moderation_en[0x1]; 3119 u8 oi[0x1]; 3120 u8 cq_period_mode[0x2]; 3121 u8 cqe_compression_en[0x1]; 3122 u8 mini_cqe_res_format[0x2]; 3123 u8 st[0x4]; 3124 u8 reserved_2[0x8]; 3125 3126 u8 reserved_3[0x20]; 3127 3128 u8 reserved_4[0x14]; 3129 u8 page_offset[0x6]; 3130 u8 reserved_5[0x6]; 3131 3132 u8 reserved_6[0x3]; 3133 u8 log_cq_size[0x5]; 3134 u8 uar_page[0x18]; 3135 3136 u8 reserved_7[0x4]; 3137 u8 cq_period[0xc]; 3138 u8 cq_max_count[0x10]; 3139 3140 u8 reserved_8[0x18]; 3141 u8 c_eqn[0x8]; 3142 3143 u8 reserved_9[0x3]; 3144 u8 log_page_size[0x5]; 3145 u8 reserved_10[0x18]; 3146 3147 u8 reserved_11[0x20]; 3148 3149 u8 reserved_12[0x8]; 3150 u8 last_notified_index[0x18]; 3151 3152 u8 reserved_13[0x8]; 3153 u8 last_solicit_index[0x18]; 3154 3155 u8 reserved_14[0x8]; 3156 u8 consumer_counter[0x18]; 3157 3158 u8 reserved_15[0x8]; 3159 u8 producer_counter[0x18]; 3160 3161 u8 reserved_16[0x40]; 3162 3163 u8 dbr_addr[0x40]; 3164 }; 3165 3166 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3167 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3168 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3169 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3170 u8 reserved_0[0x800]; 3171 }; 3172 3173 struct mlx5_ifc_query_adapter_param_block_bits { 3174 u8 reserved_0[0xc0]; 3175 3176 u8 reserved_1[0x8]; 3177 u8 ieee_vendor_id[0x18]; 3178 3179 u8 reserved_2[0x10]; 3180 u8 vsd_vendor_id[0x10]; 3181 3182 u8 vsd[208][0x8]; 3183 3184 u8 vsd_contd_psid[16][0x8]; 3185 }; 3186 3187 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3188 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3189 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3190 u8 reserved_0[0x20]; 3191 }; 3192 3193 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3194 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3195 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3196 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3197 u8 reserved_0[0x20]; 3198 }; 3199 3200 struct mlx5_ifc_bufferx_reg_bits { 3201 u8 reserved_0[0x6]; 3202 u8 lossy[0x1]; 3203 u8 epsb[0x1]; 3204 u8 reserved_1[0xc]; 3205 u8 size[0xc]; 3206 3207 u8 xoff_threshold[0x10]; 3208 u8 xon_threshold[0x10]; 3209 }; 3210 3211 struct mlx5_ifc_config_item_bits { 3212 u8 valid[0x2]; 3213 u8 reserved_0[0x2]; 3214 u8 header_type[0x2]; 3215 u8 reserved_1[0x2]; 3216 u8 default_location[0x1]; 3217 u8 reserved_2[0x7]; 3218 u8 version[0x4]; 3219 u8 reserved_3[0x3]; 3220 u8 length[0x9]; 3221 3222 u8 type[0x20]; 3223 3224 u8 reserved_4[0x10]; 3225 u8 crc16[0x10]; 3226 }; 3227 3228 enum { 3229 MLX5_XRQC_STATE_GOOD = 0x0, 3230 MLX5_XRQC_STATE_ERROR = 0x1, 3231 }; 3232 3233 enum { 3234 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3235 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3236 }; 3237 3238 enum { 3239 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3240 }; 3241 3242 struct mlx5_ifc_tag_matching_topology_context_bits { 3243 u8 log_matching_list_sz[0x4]; 3244 u8 reserved_at_4[0xc]; 3245 u8 append_next_index[0x10]; 3246 3247 u8 sw_phase_cnt[0x10]; 3248 u8 hw_phase_cnt[0x10]; 3249 3250 u8 reserved_at_40[0x40]; 3251 }; 3252 3253 struct mlx5_ifc_xrqc_bits { 3254 u8 state[0x4]; 3255 u8 rlkey[0x1]; 3256 u8 reserved_at_5[0xf]; 3257 u8 topology[0x4]; 3258 u8 reserved_at_18[0x4]; 3259 u8 offload[0x4]; 3260 3261 u8 reserved_at_20[0x8]; 3262 u8 user_index[0x18]; 3263 3264 u8 reserved_at_40[0x8]; 3265 u8 cqn[0x18]; 3266 3267 u8 reserved_at_60[0xa0]; 3268 3269 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3270 3271 u8 reserved_at_180[0x280]; 3272 3273 struct mlx5_ifc_wq_bits wq; 3274 }; 3275 3276 struct mlx5_ifc_nodnic_port_config_reg_bits { 3277 struct mlx5_ifc_nodnic_event_word_bits event; 3278 3279 u8 network_en[0x1]; 3280 u8 dma_en[0x1]; 3281 u8 promisc_en[0x1]; 3282 u8 promisc_multicast_en[0x1]; 3283 u8 reserved_0[0x17]; 3284 u8 receive_filter_en[0x5]; 3285 3286 u8 reserved_1[0x10]; 3287 u8 mac_47_32[0x10]; 3288 3289 u8 mac_31_0[0x20]; 3290 3291 u8 receive_filters_mgid_mac[64][0x8]; 3292 3293 u8 gid[16][0x8]; 3294 3295 u8 reserved_2[0x10]; 3296 u8 lid[0x10]; 3297 3298 u8 reserved_3[0xc]; 3299 u8 sm_sl[0x4]; 3300 u8 sm_lid[0x10]; 3301 3302 u8 completion_address_63_32[0x20]; 3303 3304 u8 completion_address_31_12[0x14]; 3305 u8 reserved_4[0x6]; 3306 u8 log_cq_size[0x6]; 3307 3308 u8 working_buffer_address_63_32[0x20]; 3309 3310 u8 working_buffer_address_31_12[0x14]; 3311 u8 reserved_5[0xc]; 3312 3313 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3314 3315 u8 pkey_index[0x10]; 3316 u8 pkey[0x10]; 3317 3318 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3319 3320 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3321 3322 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3323 3324 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3325 3326 u8 reserved_6[0x400]; 3327 }; 3328 3329 union mlx5_ifc_event_auto_bits { 3330 struct mlx5_ifc_comp_event_bits comp_event; 3331 struct mlx5_ifc_dct_events_bits dct_events; 3332 struct mlx5_ifc_qp_events_bits qp_events; 3333 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3334 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3335 struct mlx5_ifc_cq_error_bits cq_error; 3336 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3337 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3338 struct mlx5_ifc_gpio_event_bits gpio_event; 3339 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3340 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3341 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3342 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3343 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3344 u8 reserved_0[0xe0]; 3345 }; 3346 3347 struct mlx5_ifc_health_buffer_bits { 3348 u8 reserved_0[0x100]; 3349 3350 u8 assert_existptr[0x20]; 3351 3352 u8 assert_callra[0x20]; 3353 3354 u8 reserved_1[0x40]; 3355 3356 u8 fw_version[0x20]; 3357 3358 u8 hw_id[0x20]; 3359 3360 u8 reserved_2[0x20]; 3361 3362 u8 irisc_index[0x8]; 3363 u8 synd[0x8]; 3364 u8 ext_synd[0x10]; 3365 }; 3366 3367 struct mlx5_ifc_register_loopback_control_bits { 3368 u8 no_lb[0x1]; 3369 u8 reserved_0[0x7]; 3370 u8 port[0x8]; 3371 u8 reserved_1[0x10]; 3372 3373 u8 reserved_2[0x60]; 3374 }; 3375 3376 struct mlx5_ifc_lrh_bits { 3377 u8 vl[4]; 3378 u8 lver[4]; 3379 u8 sl[4]; 3380 u8 reserved2[2]; 3381 u8 lnh[2]; 3382 u8 dlid[16]; 3383 u8 reserved5[5]; 3384 u8 pkt_len[11]; 3385 u8 slid[16]; 3386 }; 3387 3388 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3389 u8 reserved_0[0x40]; 3390 3391 u8 reserved_1[0x10]; 3392 u8 rol_mode[0x8]; 3393 u8 wol_mode[0x8]; 3394 }; 3395 3396 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3397 u8 reserved_0[0x40]; 3398 3399 u8 rol_mode_valid[0x1]; 3400 u8 wol_mode_valid[0x1]; 3401 u8 reserved_1[0xe]; 3402 u8 rol_mode[0x8]; 3403 u8 wol_mode[0x8]; 3404 3405 u8 reserved_2[0x7a0]; 3406 }; 3407 3408 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3409 u8 virtual_mac_en[0x1]; 3410 u8 mac_aux_v[0x1]; 3411 u8 reserved_0[0x1e]; 3412 3413 u8 reserved_1[0x40]; 3414 3415 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3416 3417 u8 reserved_2[0x760]; 3418 }; 3419 3420 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3421 u8 virtual_mac_en[0x1]; 3422 u8 mac_aux_v[0x1]; 3423 u8 reserved_0[0x1e]; 3424 3425 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3426 3427 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3428 3429 u8 reserved_1[0x760]; 3430 }; 3431 3432 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3433 struct mlx5_ifc_fw_version_bits fw_version; 3434 3435 u8 reserved_0[0x10]; 3436 u8 hash_signature[0x10]; 3437 3438 u8 psid[16][0x8]; 3439 3440 u8 reserved_1[0x6e0]; 3441 }; 3442 3443 struct mlx5_ifc_icmd_query_cap_in_bits { 3444 u8 reserved_0[0x10]; 3445 u8 capability_group[0x10]; 3446 }; 3447 3448 struct mlx5_ifc_icmd_query_cap_general_bits { 3449 u8 nv_access[0x1]; 3450 u8 fw_info_psid[0x1]; 3451 u8 reserved_0[0x1e]; 3452 3453 u8 reserved_1[0x16]; 3454 u8 rol_s[0x1]; 3455 u8 rol_g[0x1]; 3456 u8 reserved_2[0x1]; 3457 u8 wol_s[0x1]; 3458 u8 wol_g[0x1]; 3459 u8 wol_a[0x1]; 3460 u8 wol_b[0x1]; 3461 u8 wol_m[0x1]; 3462 u8 wol_u[0x1]; 3463 u8 wol_p[0x1]; 3464 }; 3465 3466 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3467 u8 status[0x8]; 3468 u8 reserved_0[0x18]; 3469 3470 u8 reserved_1[0x7e0]; 3471 }; 3472 3473 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3474 u8 status[0x8]; 3475 u8 reserved_0[0x18]; 3476 3477 u8 reserved_1[0x7e0]; 3478 }; 3479 3480 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3481 u8 address_hi[0x20]; 3482 3483 u8 address_lo[0x20]; 3484 3485 u8 reserved_0[0x7c0]; 3486 }; 3487 3488 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3489 u8 reserved_0[0x20]; 3490 3491 u8 address_hi[0x20]; 3492 3493 u8 address_lo[0x20]; 3494 3495 u8 reserved_1[0x7a0]; 3496 }; 3497 3498 struct mlx5_ifc_icmd_access_reg_out_bits { 3499 u8 reserved_0[0x11]; 3500 u8 status[0x7]; 3501 u8 reserved_1[0x8]; 3502 3503 u8 register_id[0x10]; 3504 u8 reserved_2[0x10]; 3505 3506 u8 reserved_3[0x40]; 3507 3508 u8 reserved_4[0x5]; 3509 u8 len[0xb]; 3510 u8 reserved_5[0x10]; 3511 3512 u8 register_data[0][0x20]; 3513 }; 3514 3515 enum { 3516 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3517 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3518 }; 3519 3520 struct mlx5_ifc_icmd_access_reg_in_bits { 3521 u8 constant_1[0x5]; 3522 u8 constant_2[0xb]; 3523 u8 reserved_0[0x10]; 3524 3525 u8 register_id[0x10]; 3526 u8 reserved_1[0x1]; 3527 u8 method[0x7]; 3528 u8 constant_3[0x8]; 3529 3530 u8 reserved_2[0x40]; 3531 3532 u8 constant_4[0x5]; 3533 u8 len[0xb]; 3534 u8 reserved_3[0x10]; 3535 3536 u8 register_data[0][0x20]; 3537 }; 3538 3539 enum { 3540 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3541 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3542 }; 3543 3544 struct mlx5_ifc_teardown_hca_out_bits { 3545 u8 status[0x8]; 3546 u8 reserved_0[0x18]; 3547 3548 u8 syndrome[0x20]; 3549 3550 u8 reserved_1[0x3f]; 3551 3552 u8 state[0x1]; 3553 }; 3554 3555 enum { 3556 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3557 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3558 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3559 }; 3560 3561 struct mlx5_ifc_teardown_hca_in_bits { 3562 u8 opcode[0x10]; 3563 u8 reserved_0[0x10]; 3564 3565 u8 reserved_1[0x10]; 3566 u8 op_mod[0x10]; 3567 3568 u8 reserved_2[0x10]; 3569 u8 profile[0x10]; 3570 3571 u8 reserved_3[0x20]; 3572 }; 3573 3574 struct mlx5_ifc_set_delay_drop_params_out_bits { 3575 u8 status[0x8]; 3576 u8 reserved_at_8[0x18]; 3577 3578 u8 syndrome[0x20]; 3579 3580 u8 reserved_at_40[0x40]; 3581 }; 3582 3583 struct mlx5_ifc_set_delay_drop_params_in_bits { 3584 u8 opcode[0x10]; 3585 u8 reserved_at_10[0x10]; 3586 3587 u8 reserved_at_20[0x10]; 3588 u8 op_mod[0x10]; 3589 3590 u8 reserved_at_40[0x20]; 3591 3592 u8 reserved_at_60[0x10]; 3593 u8 delay_drop_timeout[0x10]; 3594 }; 3595 3596 struct mlx5_ifc_query_delay_drop_params_out_bits { 3597 u8 status[0x8]; 3598 u8 reserved_at_8[0x18]; 3599 3600 u8 syndrome[0x20]; 3601 3602 u8 reserved_at_40[0x20]; 3603 3604 u8 reserved_at_60[0x10]; 3605 u8 delay_drop_timeout[0x10]; 3606 }; 3607 3608 struct mlx5_ifc_query_delay_drop_params_in_bits { 3609 u8 opcode[0x10]; 3610 u8 reserved_at_10[0x10]; 3611 3612 u8 reserved_at_20[0x10]; 3613 u8 op_mod[0x10]; 3614 3615 u8 reserved_at_40[0x40]; 3616 }; 3617 3618 struct mlx5_ifc_suspend_qp_out_bits { 3619 u8 status[0x8]; 3620 u8 reserved_0[0x18]; 3621 3622 u8 syndrome[0x20]; 3623 3624 u8 reserved_1[0x40]; 3625 }; 3626 3627 struct mlx5_ifc_suspend_qp_in_bits { 3628 u8 opcode[0x10]; 3629 u8 reserved_0[0x10]; 3630 3631 u8 reserved_1[0x10]; 3632 u8 op_mod[0x10]; 3633 3634 u8 reserved_2[0x8]; 3635 u8 qpn[0x18]; 3636 3637 u8 reserved_3[0x20]; 3638 }; 3639 3640 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3641 u8 status[0x8]; 3642 u8 reserved_0[0x18]; 3643 3644 u8 syndrome[0x20]; 3645 3646 u8 reserved_1[0x40]; 3647 }; 3648 3649 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3650 u8 opcode[0x10]; 3651 u8 uid[0x10]; 3652 3653 u8 reserved_1[0x10]; 3654 u8 op_mod[0x10]; 3655 3656 u8 reserved_2[0x8]; 3657 u8 qpn[0x18]; 3658 3659 u8 reserved_3[0x20]; 3660 3661 u8 opt_param_mask[0x20]; 3662 3663 u8 reserved_4[0x20]; 3664 3665 struct mlx5_ifc_qpc_bits qpc; 3666 3667 u8 reserved_5[0x80]; 3668 }; 3669 3670 struct mlx5_ifc_sqd2rts_qp_out_bits { 3671 u8 status[0x8]; 3672 u8 reserved_0[0x18]; 3673 3674 u8 syndrome[0x20]; 3675 3676 u8 reserved_1[0x40]; 3677 }; 3678 3679 struct mlx5_ifc_sqd2rts_qp_in_bits { 3680 u8 opcode[0x10]; 3681 u8 uid[0x10]; 3682 3683 u8 reserved_1[0x10]; 3684 u8 op_mod[0x10]; 3685 3686 u8 reserved_2[0x8]; 3687 u8 qpn[0x18]; 3688 3689 u8 reserved_3[0x20]; 3690 3691 u8 opt_param_mask[0x20]; 3692 3693 u8 reserved_4[0x20]; 3694 3695 struct mlx5_ifc_qpc_bits qpc; 3696 3697 u8 reserved_5[0x80]; 3698 }; 3699 3700 struct mlx5_ifc_set_wol_rol_out_bits { 3701 u8 status[0x8]; 3702 u8 reserved_0[0x18]; 3703 3704 u8 syndrome[0x20]; 3705 3706 u8 reserved_1[0x40]; 3707 }; 3708 3709 struct mlx5_ifc_set_wol_rol_in_bits { 3710 u8 opcode[0x10]; 3711 u8 reserved_0[0x10]; 3712 3713 u8 reserved_1[0x10]; 3714 u8 op_mod[0x10]; 3715 3716 u8 rol_mode_valid[0x1]; 3717 u8 wol_mode_valid[0x1]; 3718 u8 reserved_2[0xe]; 3719 u8 rol_mode[0x8]; 3720 u8 wol_mode[0x8]; 3721 3722 u8 reserved_3[0x20]; 3723 }; 3724 3725 struct mlx5_ifc_set_roce_address_out_bits { 3726 u8 status[0x8]; 3727 u8 reserved_0[0x18]; 3728 3729 u8 syndrome[0x20]; 3730 3731 u8 reserved_1[0x40]; 3732 }; 3733 3734 struct mlx5_ifc_set_roce_address_in_bits { 3735 u8 opcode[0x10]; 3736 u8 reserved_0[0x10]; 3737 3738 u8 reserved_1[0x10]; 3739 u8 op_mod[0x10]; 3740 3741 u8 roce_address_index[0x10]; 3742 u8 reserved_2[0x10]; 3743 3744 u8 reserved_3[0x20]; 3745 3746 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3747 }; 3748 3749 struct mlx5_ifc_set_rdb_out_bits { 3750 u8 status[0x8]; 3751 u8 reserved_0[0x18]; 3752 3753 u8 syndrome[0x20]; 3754 3755 u8 reserved_1[0x40]; 3756 }; 3757 3758 struct mlx5_ifc_set_rdb_in_bits { 3759 u8 opcode[0x10]; 3760 u8 reserved_0[0x10]; 3761 3762 u8 reserved_1[0x10]; 3763 u8 op_mod[0x10]; 3764 3765 u8 reserved_2[0x8]; 3766 u8 qpn[0x18]; 3767 3768 u8 reserved_3[0x18]; 3769 u8 rdb_list_size[0x8]; 3770 3771 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3772 }; 3773 3774 struct mlx5_ifc_set_mad_demux_out_bits { 3775 u8 status[0x8]; 3776 u8 reserved_0[0x18]; 3777 3778 u8 syndrome[0x20]; 3779 3780 u8 reserved_1[0x40]; 3781 }; 3782 3783 enum { 3784 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3785 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3786 }; 3787 3788 struct mlx5_ifc_set_mad_demux_in_bits { 3789 u8 opcode[0x10]; 3790 u8 reserved_0[0x10]; 3791 3792 u8 reserved_1[0x10]; 3793 u8 op_mod[0x10]; 3794 3795 u8 reserved_2[0x20]; 3796 3797 u8 reserved_3[0x6]; 3798 u8 demux_mode[0x2]; 3799 u8 reserved_4[0x18]; 3800 }; 3801 3802 struct mlx5_ifc_set_l2_table_entry_out_bits { 3803 u8 status[0x8]; 3804 u8 reserved_0[0x18]; 3805 3806 u8 syndrome[0x20]; 3807 3808 u8 reserved_1[0x40]; 3809 }; 3810 3811 struct mlx5_ifc_set_l2_table_entry_in_bits { 3812 u8 opcode[0x10]; 3813 u8 reserved_0[0x10]; 3814 3815 u8 reserved_1[0x10]; 3816 u8 op_mod[0x10]; 3817 3818 u8 reserved_2[0x60]; 3819 3820 u8 reserved_3[0x8]; 3821 u8 table_index[0x18]; 3822 3823 u8 reserved_4[0x20]; 3824 3825 u8 reserved_5[0x13]; 3826 u8 vlan_valid[0x1]; 3827 u8 vlan[0xc]; 3828 3829 struct mlx5_ifc_mac_address_layout_bits mac_address; 3830 3831 u8 reserved_6[0xc0]; 3832 }; 3833 3834 struct mlx5_ifc_set_issi_out_bits { 3835 u8 status[0x8]; 3836 u8 reserved_0[0x18]; 3837 3838 u8 syndrome[0x20]; 3839 3840 u8 reserved_1[0x40]; 3841 }; 3842 3843 struct mlx5_ifc_set_issi_in_bits { 3844 u8 opcode[0x10]; 3845 u8 reserved_0[0x10]; 3846 3847 u8 reserved_1[0x10]; 3848 u8 op_mod[0x10]; 3849 3850 u8 reserved_2[0x10]; 3851 u8 current_issi[0x10]; 3852 3853 u8 reserved_3[0x20]; 3854 }; 3855 3856 struct mlx5_ifc_set_hca_cap_out_bits { 3857 u8 status[0x8]; 3858 u8 reserved_0[0x18]; 3859 3860 u8 syndrome[0x20]; 3861 3862 u8 reserved_1[0x40]; 3863 }; 3864 3865 struct mlx5_ifc_set_hca_cap_in_bits { 3866 u8 opcode[0x10]; 3867 u8 reserved_0[0x10]; 3868 3869 u8 reserved_1[0x10]; 3870 u8 op_mod[0x10]; 3871 3872 u8 reserved_2[0x40]; 3873 3874 union mlx5_ifc_hca_cap_union_bits capability; 3875 }; 3876 3877 enum { 3878 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3879 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3880 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3881 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3882 }; 3883 3884 struct mlx5_ifc_set_flow_table_root_out_bits { 3885 u8 status[0x8]; 3886 u8 reserved_0[0x18]; 3887 3888 u8 syndrome[0x20]; 3889 3890 u8 reserved_1[0x40]; 3891 }; 3892 3893 struct mlx5_ifc_set_flow_table_root_in_bits { 3894 u8 opcode[0x10]; 3895 u8 reserved_0[0x10]; 3896 3897 u8 reserved_1[0x10]; 3898 u8 op_mod[0x10]; 3899 3900 u8 other_vport[0x1]; 3901 u8 reserved_2[0xf]; 3902 u8 vport_number[0x10]; 3903 3904 u8 reserved_3[0x20]; 3905 3906 u8 table_type[0x8]; 3907 u8 reserved_4[0x18]; 3908 3909 u8 reserved_5[0x8]; 3910 u8 table_id[0x18]; 3911 3912 u8 reserved_6[0x8]; 3913 u8 underlay_qpn[0x18]; 3914 3915 u8 reserved_7[0x120]; 3916 }; 3917 3918 struct mlx5_ifc_set_fte_out_bits { 3919 u8 status[0x8]; 3920 u8 reserved_0[0x18]; 3921 3922 u8 syndrome[0x20]; 3923 3924 u8 reserved_1[0x40]; 3925 }; 3926 3927 struct mlx5_ifc_set_fte_in_bits { 3928 u8 opcode[0x10]; 3929 u8 reserved_0[0x10]; 3930 3931 u8 reserved_1[0x10]; 3932 u8 op_mod[0x10]; 3933 3934 u8 other_vport[0x1]; 3935 u8 reserved_2[0xf]; 3936 u8 vport_number[0x10]; 3937 3938 u8 reserved_3[0x20]; 3939 3940 u8 table_type[0x8]; 3941 u8 reserved_4[0x18]; 3942 3943 u8 reserved_5[0x8]; 3944 u8 table_id[0x18]; 3945 3946 u8 reserved_6[0x18]; 3947 u8 modify_enable_mask[0x8]; 3948 3949 u8 reserved_7[0x20]; 3950 3951 u8 flow_index[0x20]; 3952 3953 u8 reserved_8[0xe0]; 3954 3955 struct mlx5_ifc_flow_context_bits flow_context; 3956 }; 3957 3958 struct mlx5_ifc_set_driver_version_out_bits { 3959 u8 status[0x8]; 3960 u8 reserved_0[0x18]; 3961 3962 u8 syndrome[0x20]; 3963 3964 u8 reserved_1[0x40]; 3965 }; 3966 3967 struct mlx5_ifc_set_driver_version_in_bits { 3968 u8 opcode[0x10]; 3969 u8 reserved_0[0x10]; 3970 3971 u8 reserved_1[0x10]; 3972 u8 op_mod[0x10]; 3973 3974 u8 reserved_2[0x40]; 3975 3976 u8 driver_version[64][0x8]; 3977 }; 3978 3979 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3980 u8 status[0x8]; 3981 u8 reserved_0[0x18]; 3982 3983 u8 syndrome[0x20]; 3984 3985 u8 reserved_1[0x40]; 3986 }; 3987 3988 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3989 u8 opcode[0x10]; 3990 u8 reserved_0[0x10]; 3991 3992 u8 reserved_1[0x10]; 3993 u8 op_mod[0x10]; 3994 3995 u8 enable[0x1]; 3996 u8 reserved_2[0x1f]; 3997 3998 u8 reserved_3[0x160]; 3999 4000 struct mlx5_ifc_cmd_pas_bits pas; 4001 }; 4002 4003 struct mlx5_ifc_set_burst_size_out_bits { 4004 u8 status[0x8]; 4005 u8 reserved_0[0x18]; 4006 4007 u8 syndrome[0x20]; 4008 4009 u8 reserved_1[0x40]; 4010 }; 4011 4012 struct mlx5_ifc_set_burst_size_in_bits { 4013 u8 opcode[0x10]; 4014 u8 reserved_0[0x10]; 4015 4016 u8 reserved_1[0x10]; 4017 u8 op_mod[0x10]; 4018 4019 u8 reserved_2[0x20]; 4020 4021 u8 reserved_3[0x9]; 4022 u8 device_burst_size[0x17]; 4023 }; 4024 4025 struct mlx5_ifc_rts2rts_qp_out_bits { 4026 u8 status[0x8]; 4027 u8 reserved_0[0x18]; 4028 4029 u8 syndrome[0x20]; 4030 4031 u8 reserved_1[0x40]; 4032 }; 4033 4034 struct mlx5_ifc_rts2rts_qp_in_bits { 4035 u8 opcode[0x10]; 4036 u8 uid[0x10]; 4037 4038 u8 reserved_1[0x10]; 4039 u8 op_mod[0x10]; 4040 4041 u8 reserved_2[0x8]; 4042 u8 qpn[0x18]; 4043 4044 u8 reserved_3[0x20]; 4045 4046 u8 opt_param_mask[0x20]; 4047 4048 u8 reserved_4[0x20]; 4049 4050 struct mlx5_ifc_qpc_bits qpc; 4051 4052 u8 reserved_5[0x80]; 4053 }; 4054 4055 struct mlx5_ifc_rtr2rts_qp_out_bits { 4056 u8 status[0x8]; 4057 u8 reserved_0[0x18]; 4058 4059 u8 syndrome[0x20]; 4060 4061 u8 reserved_1[0x40]; 4062 }; 4063 4064 struct mlx5_ifc_rtr2rts_qp_in_bits { 4065 u8 opcode[0x10]; 4066 u8 uid[0x10]; 4067 4068 u8 reserved_1[0x10]; 4069 u8 op_mod[0x10]; 4070 4071 u8 reserved_2[0x8]; 4072 u8 qpn[0x18]; 4073 4074 u8 reserved_3[0x20]; 4075 4076 u8 opt_param_mask[0x20]; 4077 4078 u8 reserved_4[0x20]; 4079 4080 struct mlx5_ifc_qpc_bits qpc; 4081 4082 u8 reserved_5[0x80]; 4083 }; 4084 4085 struct mlx5_ifc_rst2init_qp_out_bits { 4086 u8 status[0x8]; 4087 u8 reserved_0[0x18]; 4088 4089 u8 syndrome[0x20]; 4090 4091 u8 reserved_1[0x40]; 4092 }; 4093 4094 struct mlx5_ifc_rst2init_qp_in_bits { 4095 u8 opcode[0x10]; 4096 u8 uid[0x10]; 4097 4098 u8 reserved_1[0x10]; 4099 u8 op_mod[0x10]; 4100 4101 u8 reserved_2[0x8]; 4102 u8 qpn[0x18]; 4103 4104 u8 reserved_3[0x20]; 4105 4106 u8 opt_param_mask[0x20]; 4107 4108 u8 reserved_4[0x20]; 4109 4110 struct mlx5_ifc_qpc_bits qpc; 4111 4112 u8 reserved_5[0x80]; 4113 }; 4114 4115 struct mlx5_ifc_query_xrq_out_bits { 4116 u8 status[0x8]; 4117 u8 reserved_at_8[0x18]; 4118 4119 u8 syndrome[0x20]; 4120 4121 u8 reserved_at_40[0x40]; 4122 4123 struct mlx5_ifc_xrqc_bits xrq_context; 4124 }; 4125 4126 struct mlx5_ifc_query_xrq_in_bits { 4127 u8 opcode[0x10]; 4128 u8 reserved_at_10[0x10]; 4129 4130 u8 reserved_at_20[0x10]; 4131 u8 op_mod[0x10]; 4132 4133 u8 reserved_at_40[0x8]; 4134 u8 xrqn[0x18]; 4135 4136 u8 reserved_at_60[0x20]; 4137 }; 4138 4139 struct mlx5_ifc_resume_qp_out_bits { 4140 u8 status[0x8]; 4141 u8 reserved_0[0x18]; 4142 4143 u8 syndrome[0x20]; 4144 4145 u8 reserved_1[0x40]; 4146 }; 4147 4148 struct mlx5_ifc_resume_qp_in_bits { 4149 u8 opcode[0x10]; 4150 u8 reserved_0[0x10]; 4151 4152 u8 reserved_1[0x10]; 4153 u8 op_mod[0x10]; 4154 4155 u8 reserved_2[0x8]; 4156 u8 qpn[0x18]; 4157 4158 u8 reserved_3[0x20]; 4159 }; 4160 4161 struct mlx5_ifc_query_xrc_srq_out_bits { 4162 u8 status[0x8]; 4163 u8 reserved_0[0x18]; 4164 4165 u8 syndrome[0x20]; 4166 4167 u8 reserved_1[0x40]; 4168 4169 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4170 4171 u8 reserved_2[0x600]; 4172 4173 u8 pas[0][0x40]; 4174 }; 4175 4176 struct mlx5_ifc_query_xrc_srq_in_bits { 4177 u8 opcode[0x10]; 4178 u8 uid[0x10]; 4179 4180 u8 reserved_1[0x10]; 4181 u8 op_mod[0x10]; 4182 4183 u8 reserved_2[0x8]; 4184 u8 xrc_srqn[0x18]; 4185 4186 u8 reserved_3[0x20]; 4187 }; 4188 4189 struct mlx5_ifc_query_wol_rol_out_bits { 4190 u8 status[0x8]; 4191 u8 reserved_0[0x18]; 4192 4193 u8 syndrome[0x20]; 4194 4195 u8 reserved_1[0x10]; 4196 u8 rol_mode[0x8]; 4197 u8 wol_mode[0x8]; 4198 4199 u8 reserved_2[0x20]; 4200 }; 4201 4202 struct mlx5_ifc_query_wol_rol_in_bits { 4203 u8 opcode[0x10]; 4204 u8 reserved_0[0x10]; 4205 4206 u8 reserved_1[0x10]; 4207 u8 op_mod[0x10]; 4208 4209 u8 reserved_2[0x40]; 4210 }; 4211 4212 enum { 4213 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4214 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4215 }; 4216 4217 struct mlx5_ifc_query_vport_state_out_bits { 4218 u8 status[0x8]; 4219 u8 reserved_0[0x18]; 4220 4221 u8 syndrome[0x20]; 4222 4223 u8 reserved_1[0x20]; 4224 4225 u8 reserved_2[0x18]; 4226 u8 admin_state[0x4]; 4227 u8 state[0x4]; 4228 }; 4229 4230 enum { 4231 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 4232 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 4233 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 4234 }; 4235 4236 struct mlx5_ifc_query_vport_state_in_bits { 4237 u8 opcode[0x10]; 4238 u8 reserved_0[0x10]; 4239 4240 u8 reserved_1[0x10]; 4241 u8 op_mod[0x10]; 4242 4243 u8 other_vport[0x1]; 4244 u8 reserved_2[0xf]; 4245 u8 vport_number[0x10]; 4246 4247 u8 reserved_3[0x20]; 4248 }; 4249 4250 struct mlx5_ifc_query_vnic_env_out_bits { 4251 u8 status[0x8]; 4252 u8 reserved_at_8[0x18]; 4253 4254 u8 syndrome[0x20]; 4255 4256 u8 reserved_at_40[0x40]; 4257 4258 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4259 }; 4260 4261 enum { 4262 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4263 }; 4264 4265 struct mlx5_ifc_query_vnic_env_in_bits { 4266 u8 opcode[0x10]; 4267 u8 reserved_at_10[0x10]; 4268 4269 u8 reserved_at_20[0x10]; 4270 u8 op_mod[0x10]; 4271 4272 u8 other_vport[0x1]; 4273 u8 reserved_at_41[0xf]; 4274 u8 vport_number[0x10]; 4275 4276 u8 reserved_at_60[0x20]; 4277 }; 4278 4279 struct mlx5_ifc_query_vport_counter_out_bits { 4280 u8 status[0x8]; 4281 u8 reserved_0[0x18]; 4282 4283 u8 syndrome[0x20]; 4284 4285 u8 reserved_1[0x40]; 4286 4287 struct mlx5_ifc_traffic_counter_bits received_errors; 4288 4289 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4290 4291 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4292 4293 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4294 4295 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4296 4297 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4298 4299 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4300 4301 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4302 4303 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4304 4305 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4306 4307 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4308 4309 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4310 4311 u8 reserved_2[0xa00]; 4312 }; 4313 4314 enum { 4315 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4316 }; 4317 4318 struct mlx5_ifc_query_vport_counter_in_bits { 4319 u8 opcode[0x10]; 4320 u8 reserved_0[0x10]; 4321 4322 u8 reserved_1[0x10]; 4323 u8 op_mod[0x10]; 4324 4325 u8 other_vport[0x1]; 4326 u8 reserved_2[0xb]; 4327 u8 port_num[0x4]; 4328 u8 vport_number[0x10]; 4329 4330 u8 reserved_3[0x60]; 4331 4332 u8 clear[0x1]; 4333 u8 reserved_4[0x1f]; 4334 4335 u8 reserved_5[0x20]; 4336 }; 4337 4338 struct mlx5_ifc_query_tis_out_bits { 4339 u8 status[0x8]; 4340 u8 reserved_0[0x18]; 4341 4342 u8 syndrome[0x20]; 4343 4344 u8 reserved_1[0x40]; 4345 4346 struct mlx5_ifc_tisc_bits tis_context; 4347 }; 4348 4349 struct mlx5_ifc_query_tis_in_bits { 4350 u8 opcode[0x10]; 4351 u8 reserved_0[0x10]; 4352 4353 u8 reserved_1[0x10]; 4354 u8 op_mod[0x10]; 4355 4356 u8 reserved_2[0x8]; 4357 u8 tisn[0x18]; 4358 4359 u8 reserved_3[0x20]; 4360 }; 4361 4362 struct mlx5_ifc_query_tir_out_bits { 4363 u8 status[0x8]; 4364 u8 reserved_0[0x18]; 4365 4366 u8 syndrome[0x20]; 4367 4368 u8 reserved_1[0xc0]; 4369 4370 struct mlx5_ifc_tirc_bits tir_context; 4371 }; 4372 4373 struct mlx5_ifc_query_tir_in_bits { 4374 u8 opcode[0x10]; 4375 u8 reserved_0[0x10]; 4376 4377 u8 reserved_1[0x10]; 4378 u8 op_mod[0x10]; 4379 4380 u8 reserved_2[0x8]; 4381 u8 tirn[0x18]; 4382 4383 u8 reserved_3[0x20]; 4384 }; 4385 4386 struct mlx5_ifc_query_srq_out_bits { 4387 u8 status[0x8]; 4388 u8 reserved_0[0x18]; 4389 4390 u8 syndrome[0x20]; 4391 4392 u8 reserved_1[0x40]; 4393 4394 struct mlx5_ifc_srqc_bits srq_context_entry; 4395 4396 u8 reserved_2[0x600]; 4397 4398 u8 pas[0][0x40]; 4399 }; 4400 4401 struct mlx5_ifc_query_srq_in_bits { 4402 u8 opcode[0x10]; 4403 u8 reserved_0[0x10]; 4404 4405 u8 reserved_1[0x10]; 4406 u8 op_mod[0x10]; 4407 4408 u8 reserved_2[0x8]; 4409 u8 srqn[0x18]; 4410 4411 u8 reserved_3[0x20]; 4412 }; 4413 4414 struct mlx5_ifc_query_sq_out_bits { 4415 u8 status[0x8]; 4416 u8 reserved_0[0x18]; 4417 4418 u8 syndrome[0x20]; 4419 4420 u8 reserved_1[0xc0]; 4421 4422 struct mlx5_ifc_sqc_bits sq_context; 4423 }; 4424 4425 struct mlx5_ifc_query_sq_in_bits { 4426 u8 opcode[0x10]; 4427 u8 reserved_0[0x10]; 4428 4429 u8 reserved_1[0x10]; 4430 u8 op_mod[0x10]; 4431 4432 u8 reserved_2[0x8]; 4433 u8 sqn[0x18]; 4434 4435 u8 reserved_3[0x20]; 4436 }; 4437 4438 struct mlx5_ifc_query_special_contexts_out_bits { 4439 u8 status[0x8]; 4440 u8 reserved_0[0x18]; 4441 4442 u8 syndrome[0x20]; 4443 4444 u8 dump_fill_mkey[0x20]; 4445 4446 u8 resd_lkey[0x20]; 4447 }; 4448 4449 struct mlx5_ifc_query_special_contexts_in_bits { 4450 u8 opcode[0x10]; 4451 u8 reserved_0[0x10]; 4452 4453 u8 reserved_1[0x10]; 4454 u8 op_mod[0x10]; 4455 4456 u8 reserved_2[0x40]; 4457 }; 4458 4459 struct mlx5_ifc_query_scheduling_element_out_bits { 4460 u8 status[0x8]; 4461 u8 reserved_at_8[0x18]; 4462 4463 u8 syndrome[0x20]; 4464 4465 u8 reserved_at_40[0xc0]; 4466 4467 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4468 4469 u8 reserved_at_300[0x100]; 4470 }; 4471 4472 enum { 4473 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4474 }; 4475 4476 struct mlx5_ifc_query_scheduling_element_in_bits { 4477 u8 opcode[0x10]; 4478 u8 reserved_at_10[0x10]; 4479 4480 u8 reserved_at_20[0x10]; 4481 u8 op_mod[0x10]; 4482 4483 u8 scheduling_hierarchy[0x8]; 4484 u8 reserved_at_48[0x18]; 4485 4486 u8 scheduling_element_id[0x20]; 4487 4488 u8 reserved_at_80[0x180]; 4489 }; 4490 4491 struct mlx5_ifc_query_rqt_out_bits { 4492 u8 status[0x8]; 4493 u8 reserved_0[0x18]; 4494 4495 u8 syndrome[0x20]; 4496 4497 u8 reserved_1[0xc0]; 4498 4499 struct mlx5_ifc_rqtc_bits rqt_context; 4500 }; 4501 4502 struct mlx5_ifc_query_rqt_in_bits { 4503 u8 opcode[0x10]; 4504 u8 reserved_0[0x10]; 4505 4506 u8 reserved_1[0x10]; 4507 u8 op_mod[0x10]; 4508 4509 u8 reserved_2[0x8]; 4510 u8 rqtn[0x18]; 4511 4512 u8 reserved_3[0x20]; 4513 }; 4514 4515 struct mlx5_ifc_query_rq_out_bits { 4516 u8 status[0x8]; 4517 u8 reserved_0[0x18]; 4518 4519 u8 syndrome[0x20]; 4520 4521 u8 reserved_1[0xc0]; 4522 4523 struct mlx5_ifc_rqc_bits rq_context; 4524 }; 4525 4526 struct mlx5_ifc_query_rq_in_bits { 4527 u8 opcode[0x10]; 4528 u8 reserved_0[0x10]; 4529 4530 u8 reserved_1[0x10]; 4531 u8 op_mod[0x10]; 4532 4533 u8 reserved_2[0x8]; 4534 u8 rqn[0x18]; 4535 4536 u8 reserved_3[0x20]; 4537 }; 4538 4539 struct mlx5_ifc_query_roce_address_out_bits { 4540 u8 status[0x8]; 4541 u8 reserved_0[0x18]; 4542 4543 u8 syndrome[0x20]; 4544 4545 u8 reserved_1[0x40]; 4546 4547 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4548 }; 4549 4550 struct mlx5_ifc_query_roce_address_in_bits { 4551 u8 opcode[0x10]; 4552 u8 reserved_0[0x10]; 4553 4554 u8 reserved_1[0x10]; 4555 u8 op_mod[0x10]; 4556 4557 u8 roce_address_index[0x10]; 4558 u8 reserved_2[0x10]; 4559 4560 u8 reserved_3[0x20]; 4561 }; 4562 4563 struct mlx5_ifc_query_rmp_out_bits { 4564 u8 status[0x8]; 4565 u8 reserved_0[0x18]; 4566 4567 u8 syndrome[0x20]; 4568 4569 u8 reserved_1[0xc0]; 4570 4571 struct mlx5_ifc_rmpc_bits rmp_context; 4572 }; 4573 4574 struct mlx5_ifc_query_rmp_in_bits { 4575 u8 opcode[0x10]; 4576 u8 reserved_0[0x10]; 4577 4578 u8 reserved_1[0x10]; 4579 u8 op_mod[0x10]; 4580 4581 u8 reserved_2[0x8]; 4582 u8 rmpn[0x18]; 4583 4584 u8 reserved_3[0x20]; 4585 }; 4586 4587 struct mlx5_ifc_query_rdb_out_bits { 4588 u8 status[0x8]; 4589 u8 reserved_0[0x18]; 4590 4591 u8 syndrome[0x20]; 4592 4593 u8 reserved_1[0x20]; 4594 4595 u8 reserved_2[0x18]; 4596 u8 rdb_list_size[0x8]; 4597 4598 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4599 }; 4600 4601 struct mlx5_ifc_query_rdb_in_bits { 4602 u8 opcode[0x10]; 4603 u8 reserved_0[0x10]; 4604 4605 u8 reserved_1[0x10]; 4606 u8 op_mod[0x10]; 4607 4608 u8 reserved_2[0x8]; 4609 u8 qpn[0x18]; 4610 4611 u8 reserved_3[0x20]; 4612 }; 4613 4614 struct mlx5_ifc_query_qp_out_bits { 4615 u8 status[0x8]; 4616 u8 reserved_0[0x18]; 4617 4618 u8 syndrome[0x20]; 4619 4620 u8 reserved_1[0x40]; 4621 4622 u8 opt_param_mask[0x20]; 4623 4624 u8 reserved_2[0x20]; 4625 4626 struct mlx5_ifc_qpc_bits qpc; 4627 4628 u8 reserved_3[0x80]; 4629 4630 u8 pas[0][0x40]; 4631 }; 4632 4633 struct mlx5_ifc_query_qp_in_bits { 4634 u8 opcode[0x10]; 4635 u8 reserved_0[0x10]; 4636 4637 u8 reserved_1[0x10]; 4638 u8 op_mod[0x10]; 4639 4640 u8 reserved_2[0x8]; 4641 u8 qpn[0x18]; 4642 4643 u8 reserved_3[0x20]; 4644 }; 4645 4646 struct mlx5_ifc_query_q_counter_out_bits { 4647 u8 status[0x8]; 4648 u8 reserved_0[0x18]; 4649 4650 u8 syndrome[0x20]; 4651 4652 u8 reserved_1[0x40]; 4653 4654 u8 rx_write_requests[0x20]; 4655 4656 u8 reserved_2[0x20]; 4657 4658 u8 rx_read_requests[0x20]; 4659 4660 u8 reserved_3[0x20]; 4661 4662 u8 rx_atomic_requests[0x20]; 4663 4664 u8 reserved_4[0x20]; 4665 4666 u8 rx_dct_connect[0x20]; 4667 4668 u8 reserved_5[0x20]; 4669 4670 u8 out_of_buffer[0x20]; 4671 4672 u8 reserved_7[0x20]; 4673 4674 u8 out_of_sequence[0x20]; 4675 4676 u8 reserved_8[0x20]; 4677 4678 u8 duplicate_request[0x20]; 4679 4680 u8 reserved_9[0x20]; 4681 4682 u8 rnr_nak_retry_err[0x20]; 4683 4684 u8 reserved_10[0x20]; 4685 4686 u8 packet_seq_err[0x20]; 4687 4688 u8 reserved_11[0x20]; 4689 4690 u8 implied_nak_seq_err[0x20]; 4691 4692 u8 reserved_12[0x20]; 4693 4694 u8 local_ack_timeout_err[0x20]; 4695 4696 u8 reserved_13[0x20]; 4697 4698 u8 resp_rnr_nak[0x20]; 4699 4700 u8 reserved_14[0x20]; 4701 4702 u8 req_rnr_retries_exceeded[0x20]; 4703 4704 u8 reserved_15[0x460]; 4705 }; 4706 4707 struct mlx5_ifc_query_q_counter_in_bits { 4708 u8 opcode[0x10]; 4709 u8 reserved_0[0x10]; 4710 4711 u8 reserved_1[0x10]; 4712 u8 op_mod[0x10]; 4713 4714 u8 reserved_2[0x80]; 4715 4716 u8 clear[0x1]; 4717 u8 reserved_3[0x1f]; 4718 4719 u8 reserved_4[0x18]; 4720 u8 counter_set_id[0x8]; 4721 }; 4722 4723 struct mlx5_ifc_query_pages_out_bits { 4724 u8 status[0x8]; 4725 u8 reserved_0[0x18]; 4726 4727 u8 syndrome[0x20]; 4728 4729 u8 reserved_1[0x10]; 4730 u8 function_id[0x10]; 4731 4732 u8 num_pages[0x20]; 4733 }; 4734 4735 enum { 4736 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4737 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4738 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4739 }; 4740 4741 struct mlx5_ifc_query_pages_in_bits { 4742 u8 opcode[0x10]; 4743 u8 reserved_0[0x10]; 4744 4745 u8 reserved_1[0x10]; 4746 u8 op_mod[0x10]; 4747 4748 u8 reserved_2[0x10]; 4749 u8 function_id[0x10]; 4750 4751 u8 reserved_3[0x20]; 4752 }; 4753 4754 struct mlx5_ifc_query_nic_vport_context_out_bits { 4755 u8 status[0x8]; 4756 u8 reserved_0[0x18]; 4757 4758 u8 syndrome[0x20]; 4759 4760 u8 reserved_1[0x40]; 4761 4762 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4763 }; 4764 4765 struct mlx5_ifc_query_nic_vport_context_in_bits { 4766 u8 opcode[0x10]; 4767 u8 reserved_0[0x10]; 4768 4769 u8 reserved_1[0x10]; 4770 u8 op_mod[0x10]; 4771 4772 u8 other_vport[0x1]; 4773 u8 reserved_2[0xf]; 4774 u8 vport_number[0x10]; 4775 4776 u8 reserved_3[0x5]; 4777 u8 allowed_list_type[0x3]; 4778 u8 reserved_4[0x18]; 4779 }; 4780 4781 struct mlx5_ifc_query_mkey_out_bits { 4782 u8 status[0x8]; 4783 u8 reserved_0[0x18]; 4784 4785 u8 syndrome[0x20]; 4786 4787 u8 reserved_1[0x40]; 4788 4789 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4790 4791 u8 reserved_2[0x600]; 4792 4793 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4794 4795 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4796 }; 4797 4798 struct mlx5_ifc_query_mkey_in_bits { 4799 u8 opcode[0x10]; 4800 u8 reserved_0[0x10]; 4801 4802 u8 reserved_1[0x10]; 4803 u8 op_mod[0x10]; 4804 4805 u8 reserved_2[0x8]; 4806 u8 mkey_index[0x18]; 4807 4808 u8 pg_access[0x1]; 4809 u8 reserved_3[0x1f]; 4810 }; 4811 4812 struct mlx5_ifc_query_mad_demux_out_bits { 4813 u8 status[0x8]; 4814 u8 reserved_0[0x18]; 4815 4816 u8 syndrome[0x20]; 4817 4818 u8 reserved_1[0x40]; 4819 4820 u8 mad_dumux_parameters_block[0x20]; 4821 }; 4822 4823 struct mlx5_ifc_query_mad_demux_in_bits { 4824 u8 opcode[0x10]; 4825 u8 reserved_0[0x10]; 4826 4827 u8 reserved_1[0x10]; 4828 u8 op_mod[0x10]; 4829 4830 u8 reserved_2[0x40]; 4831 }; 4832 4833 struct mlx5_ifc_query_l2_table_entry_out_bits { 4834 u8 status[0x8]; 4835 u8 reserved_0[0x18]; 4836 4837 u8 syndrome[0x20]; 4838 4839 u8 reserved_1[0xa0]; 4840 4841 u8 reserved_2[0x13]; 4842 u8 vlan_valid[0x1]; 4843 u8 vlan[0xc]; 4844 4845 struct mlx5_ifc_mac_address_layout_bits mac_address; 4846 4847 u8 reserved_3[0xc0]; 4848 }; 4849 4850 struct mlx5_ifc_query_l2_table_entry_in_bits { 4851 u8 opcode[0x10]; 4852 u8 reserved_0[0x10]; 4853 4854 u8 reserved_1[0x10]; 4855 u8 op_mod[0x10]; 4856 4857 u8 reserved_2[0x60]; 4858 4859 u8 reserved_3[0x8]; 4860 u8 table_index[0x18]; 4861 4862 u8 reserved_4[0x140]; 4863 }; 4864 4865 struct mlx5_ifc_query_issi_out_bits { 4866 u8 status[0x8]; 4867 u8 reserved_0[0x18]; 4868 4869 u8 syndrome[0x20]; 4870 4871 u8 reserved_1[0x10]; 4872 u8 current_issi[0x10]; 4873 4874 u8 reserved_2[0xa0]; 4875 4876 u8 supported_issi_reserved[76][0x8]; 4877 u8 supported_issi_dw0[0x20]; 4878 }; 4879 4880 struct mlx5_ifc_query_issi_in_bits { 4881 u8 opcode[0x10]; 4882 u8 reserved_0[0x10]; 4883 4884 u8 reserved_1[0x10]; 4885 u8 op_mod[0x10]; 4886 4887 u8 reserved_2[0x40]; 4888 }; 4889 4890 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4891 u8 status[0x8]; 4892 u8 reserved_0[0x18]; 4893 4894 u8 syndrome[0x20]; 4895 4896 u8 reserved_1[0x40]; 4897 4898 struct mlx5_ifc_pkey_bits pkey[0]; 4899 }; 4900 4901 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4902 u8 opcode[0x10]; 4903 u8 reserved_0[0x10]; 4904 4905 u8 reserved_1[0x10]; 4906 u8 op_mod[0x10]; 4907 4908 u8 other_vport[0x1]; 4909 u8 reserved_2[0xb]; 4910 u8 port_num[0x4]; 4911 u8 vport_number[0x10]; 4912 4913 u8 reserved_3[0x10]; 4914 u8 pkey_index[0x10]; 4915 }; 4916 4917 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4918 u8 status[0x8]; 4919 u8 reserved_0[0x18]; 4920 4921 u8 syndrome[0x20]; 4922 4923 u8 reserved_1[0x20]; 4924 4925 u8 gids_num[0x10]; 4926 u8 reserved_2[0x10]; 4927 4928 struct mlx5_ifc_array128_auto_bits gid[0]; 4929 }; 4930 4931 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4932 u8 opcode[0x10]; 4933 u8 reserved_0[0x10]; 4934 4935 u8 reserved_1[0x10]; 4936 u8 op_mod[0x10]; 4937 4938 u8 other_vport[0x1]; 4939 u8 reserved_2[0xb]; 4940 u8 port_num[0x4]; 4941 u8 vport_number[0x10]; 4942 4943 u8 reserved_3[0x10]; 4944 u8 gid_index[0x10]; 4945 }; 4946 4947 struct mlx5_ifc_query_hca_vport_context_out_bits { 4948 u8 status[0x8]; 4949 u8 reserved_0[0x18]; 4950 4951 u8 syndrome[0x20]; 4952 4953 u8 reserved_1[0x40]; 4954 4955 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4956 }; 4957 4958 struct mlx5_ifc_query_hca_vport_context_in_bits { 4959 u8 opcode[0x10]; 4960 u8 reserved_0[0x10]; 4961 4962 u8 reserved_1[0x10]; 4963 u8 op_mod[0x10]; 4964 4965 u8 other_vport[0x1]; 4966 u8 reserved_2[0xb]; 4967 u8 port_num[0x4]; 4968 u8 vport_number[0x10]; 4969 4970 u8 reserved_3[0x20]; 4971 }; 4972 4973 struct mlx5_ifc_query_hca_cap_out_bits { 4974 u8 status[0x8]; 4975 u8 reserved_0[0x18]; 4976 4977 u8 syndrome[0x20]; 4978 4979 u8 reserved_1[0x40]; 4980 4981 union mlx5_ifc_hca_cap_union_bits capability; 4982 }; 4983 4984 struct mlx5_ifc_query_hca_cap_in_bits { 4985 u8 opcode[0x10]; 4986 u8 reserved_0[0x10]; 4987 4988 u8 reserved_1[0x10]; 4989 u8 op_mod[0x10]; 4990 4991 u8 reserved_2[0x40]; 4992 }; 4993 4994 struct mlx5_ifc_query_flow_table_out_bits { 4995 u8 status[0x8]; 4996 u8 reserved_at_8[0x18]; 4997 4998 u8 syndrome[0x20]; 4999 5000 u8 reserved_at_40[0x80]; 5001 5002 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5003 }; 5004 5005 struct mlx5_ifc_query_flow_table_in_bits { 5006 u8 opcode[0x10]; 5007 u8 reserved_0[0x10]; 5008 5009 u8 reserved_1[0x10]; 5010 u8 op_mod[0x10]; 5011 5012 u8 other_vport[0x1]; 5013 u8 reserved_2[0xf]; 5014 u8 vport_number[0x10]; 5015 5016 u8 reserved_3[0x20]; 5017 5018 u8 table_type[0x8]; 5019 u8 reserved_4[0x18]; 5020 5021 u8 reserved_5[0x8]; 5022 u8 table_id[0x18]; 5023 5024 u8 reserved_6[0x140]; 5025 }; 5026 5027 struct mlx5_ifc_query_fte_out_bits { 5028 u8 status[0x8]; 5029 u8 reserved_0[0x18]; 5030 5031 u8 syndrome[0x20]; 5032 5033 u8 reserved_1[0x1c0]; 5034 5035 struct mlx5_ifc_flow_context_bits flow_context; 5036 }; 5037 5038 struct mlx5_ifc_query_fte_in_bits { 5039 u8 opcode[0x10]; 5040 u8 reserved_0[0x10]; 5041 5042 u8 reserved_1[0x10]; 5043 u8 op_mod[0x10]; 5044 5045 u8 other_vport[0x1]; 5046 u8 reserved_2[0xf]; 5047 u8 vport_number[0x10]; 5048 5049 u8 reserved_3[0x20]; 5050 5051 u8 table_type[0x8]; 5052 u8 reserved_4[0x18]; 5053 5054 u8 reserved_5[0x8]; 5055 u8 table_id[0x18]; 5056 5057 u8 reserved_6[0x40]; 5058 5059 u8 flow_index[0x20]; 5060 5061 u8 reserved_7[0xe0]; 5062 }; 5063 5064 enum { 5065 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5066 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5067 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5068 }; 5069 5070 struct mlx5_ifc_query_flow_group_out_bits { 5071 u8 status[0x8]; 5072 u8 reserved_0[0x18]; 5073 5074 u8 syndrome[0x20]; 5075 5076 u8 reserved_1[0xa0]; 5077 5078 u8 start_flow_index[0x20]; 5079 5080 u8 reserved_2[0x20]; 5081 5082 u8 end_flow_index[0x20]; 5083 5084 u8 reserved_3[0xa0]; 5085 5086 u8 reserved_4[0x18]; 5087 u8 match_criteria_enable[0x8]; 5088 5089 struct mlx5_ifc_fte_match_param_bits match_criteria; 5090 5091 u8 reserved_5[0xe00]; 5092 }; 5093 5094 struct mlx5_ifc_query_flow_group_in_bits { 5095 u8 opcode[0x10]; 5096 u8 reserved_0[0x10]; 5097 5098 u8 reserved_1[0x10]; 5099 u8 op_mod[0x10]; 5100 5101 u8 other_vport[0x1]; 5102 u8 reserved_2[0xf]; 5103 u8 vport_number[0x10]; 5104 5105 u8 reserved_3[0x20]; 5106 5107 u8 table_type[0x8]; 5108 u8 reserved_4[0x18]; 5109 5110 u8 reserved_5[0x8]; 5111 u8 table_id[0x18]; 5112 5113 u8 group_id[0x20]; 5114 5115 u8 reserved_6[0x120]; 5116 }; 5117 5118 struct mlx5_ifc_query_flow_counter_out_bits { 5119 u8 status[0x8]; 5120 u8 reserved_at_8[0x18]; 5121 5122 u8 syndrome[0x20]; 5123 5124 u8 reserved_at_40[0x40]; 5125 5126 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 5127 }; 5128 5129 struct mlx5_ifc_query_flow_counter_in_bits { 5130 u8 opcode[0x10]; 5131 u8 reserved_at_10[0x10]; 5132 5133 u8 reserved_at_20[0x10]; 5134 u8 op_mod[0x10]; 5135 5136 u8 reserved_at_40[0x80]; 5137 5138 u8 clear[0x1]; 5139 u8 reserved_at_c1[0xf]; 5140 u8 num_of_counters[0x10]; 5141 5142 u8 reserved_at_e0[0x10]; 5143 u8 flow_counter_id[0x10]; 5144 }; 5145 5146 struct mlx5_ifc_query_esw_vport_context_out_bits { 5147 u8 status[0x8]; 5148 u8 reserved_0[0x18]; 5149 5150 u8 syndrome[0x20]; 5151 5152 u8 reserved_1[0x40]; 5153 5154 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5155 }; 5156 5157 struct mlx5_ifc_query_esw_vport_context_in_bits { 5158 u8 opcode[0x10]; 5159 u8 reserved_0[0x10]; 5160 5161 u8 reserved_1[0x10]; 5162 u8 op_mod[0x10]; 5163 5164 u8 other_vport[0x1]; 5165 u8 reserved_2[0xf]; 5166 u8 vport_number[0x10]; 5167 5168 u8 reserved_3[0x20]; 5169 }; 5170 5171 struct mlx5_ifc_query_eq_out_bits { 5172 u8 status[0x8]; 5173 u8 reserved_0[0x18]; 5174 5175 u8 syndrome[0x20]; 5176 5177 u8 reserved_1[0x40]; 5178 5179 struct mlx5_ifc_eqc_bits eq_context_entry; 5180 5181 u8 reserved_2[0x40]; 5182 5183 u8 event_bitmask[0x40]; 5184 5185 u8 reserved_3[0x580]; 5186 5187 u8 pas[0][0x40]; 5188 }; 5189 5190 struct mlx5_ifc_query_eq_in_bits { 5191 u8 opcode[0x10]; 5192 u8 reserved_0[0x10]; 5193 5194 u8 reserved_1[0x10]; 5195 u8 op_mod[0x10]; 5196 5197 u8 reserved_2[0x18]; 5198 u8 eq_number[0x8]; 5199 5200 u8 reserved_3[0x20]; 5201 }; 5202 5203 struct mlx5_ifc_query_dct_out_bits { 5204 u8 status[0x8]; 5205 u8 reserved_0[0x18]; 5206 5207 u8 syndrome[0x20]; 5208 5209 u8 reserved_1[0x40]; 5210 5211 struct mlx5_ifc_dctc_bits dct_context_entry; 5212 5213 u8 reserved_2[0x180]; 5214 }; 5215 5216 struct mlx5_ifc_query_dct_in_bits { 5217 u8 opcode[0x10]; 5218 u8 reserved_0[0x10]; 5219 5220 u8 reserved_1[0x10]; 5221 u8 op_mod[0x10]; 5222 5223 u8 reserved_2[0x8]; 5224 u8 dctn[0x18]; 5225 5226 u8 reserved_3[0x20]; 5227 }; 5228 5229 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 5230 u8 status[0x8]; 5231 u8 reserved_0[0x18]; 5232 5233 u8 syndrome[0x20]; 5234 5235 u8 enable[0x1]; 5236 u8 reserved_1[0x1f]; 5237 5238 u8 reserved_2[0x160]; 5239 5240 struct mlx5_ifc_cmd_pas_bits pas; 5241 }; 5242 5243 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 5244 u8 opcode[0x10]; 5245 u8 reserved_0[0x10]; 5246 5247 u8 reserved_1[0x10]; 5248 u8 op_mod[0x10]; 5249 5250 u8 reserved_2[0x40]; 5251 }; 5252 5253 struct mlx5_ifc_packet_reformat_context_in_bits { 5254 u8 reserved_at_0[0x5]; 5255 u8 reformat_type[0x3]; 5256 u8 reserved_at_8[0xe]; 5257 u8 reformat_data_size[0xa]; 5258 5259 u8 reserved_at_20[0x10]; 5260 u8 reformat_data[2][0x8]; 5261 5262 u8 more_reformat_data[0][0x8]; 5263 }; 5264 5265 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5266 u8 status[0x8]; 5267 u8 reserved_at_8[0x18]; 5268 5269 u8 syndrome[0x20]; 5270 5271 u8 reserved_at_40[0xa0]; 5272 5273 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 5274 }; 5275 5276 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5277 u8 opcode[0x10]; 5278 u8 reserved_at_10[0x10]; 5279 5280 u8 reserved_at_20[0x10]; 5281 u8 op_mod[0x10]; 5282 5283 u8 packet_reformat_id[0x20]; 5284 5285 u8 reserved_at_60[0xa0]; 5286 }; 5287 5288 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5289 u8 status[0x8]; 5290 u8 reserved_at_8[0x18]; 5291 5292 u8 syndrome[0x20]; 5293 5294 u8 packet_reformat_id[0x20]; 5295 5296 u8 reserved_at_60[0x20]; 5297 }; 5298 5299 enum mlx5_reformat_ctx_type { 5300 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5301 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5302 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5303 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5304 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5305 }; 5306 5307 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5308 u8 opcode[0x10]; 5309 u8 reserved_at_10[0x10]; 5310 5311 u8 reserved_at_20[0x10]; 5312 u8 op_mod[0x10]; 5313 5314 u8 reserved_at_40[0xa0]; 5315 5316 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5317 }; 5318 5319 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5320 u8 status[0x8]; 5321 u8 reserved_at_8[0x18]; 5322 5323 u8 syndrome[0x20]; 5324 5325 u8 reserved_at_40[0x40]; 5326 }; 5327 5328 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5329 u8 opcode[0x10]; 5330 u8 reserved_at_10[0x10]; 5331 5332 u8 reserved_20[0x10]; 5333 u8 op_mod[0x10]; 5334 5335 u8 packet_reformat_id[0x20]; 5336 5337 u8 reserved_60[0x20]; 5338 }; 5339 5340 struct mlx5_ifc_query_cq_out_bits { 5341 u8 status[0x8]; 5342 u8 reserved_0[0x18]; 5343 5344 u8 syndrome[0x20]; 5345 5346 u8 reserved_1[0x40]; 5347 5348 struct mlx5_ifc_cqc_bits cq_context; 5349 5350 u8 reserved_2[0x600]; 5351 5352 u8 pas[0][0x40]; 5353 }; 5354 5355 struct mlx5_ifc_query_cq_in_bits { 5356 u8 opcode[0x10]; 5357 u8 reserved_0[0x10]; 5358 5359 u8 reserved_1[0x10]; 5360 u8 op_mod[0x10]; 5361 5362 u8 reserved_2[0x8]; 5363 u8 cqn[0x18]; 5364 5365 u8 reserved_3[0x20]; 5366 }; 5367 5368 struct mlx5_ifc_query_cong_status_out_bits { 5369 u8 status[0x8]; 5370 u8 reserved_0[0x18]; 5371 5372 u8 syndrome[0x20]; 5373 5374 u8 reserved_1[0x20]; 5375 5376 u8 enable[0x1]; 5377 u8 tag_enable[0x1]; 5378 u8 reserved_2[0x1e]; 5379 }; 5380 5381 struct mlx5_ifc_query_cong_status_in_bits { 5382 u8 opcode[0x10]; 5383 u8 reserved_0[0x10]; 5384 5385 u8 reserved_1[0x10]; 5386 u8 op_mod[0x10]; 5387 5388 u8 reserved_2[0x18]; 5389 u8 priority[0x4]; 5390 u8 cong_protocol[0x4]; 5391 5392 u8 reserved_3[0x20]; 5393 }; 5394 5395 struct mlx5_ifc_query_cong_statistics_out_bits { 5396 u8 status[0x8]; 5397 u8 reserved_0[0x18]; 5398 5399 u8 syndrome[0x20]; 5400 5401 u8 reserved_1[0x40]; 5402 5403 u8 rp_cur_flows[0x20]; 5404 5405 u8 sum_flows[0x20]; 5406 5407 u8 rp_cnp_ignored_high[0x20]; 5408 5409 u8 rp_cnp_ignored_low[0x20]; 5410 5411 u8 rp_cnp_handled_high[0x20]; 5412 5413 u8 rp_cnp_handled_low[0x20]; 5414 5415 u8 reserved_2[0x100]; 5416 5417 u8 time_stamp_high[0x20]; 5418 5419 u8 time_stamp_low[0x20]; 5420 5421 u8 accumulators_period[0x20]; 5422 5423 u8 np_ecn_marked_roce_packets_high[0x20]; 5424 5425 u8 np_ecn_marked_roce_packets_low[0x20]; 5426 5427 u8 np_cnp_sent_high[0x20]; 5428 5429 u8 np_cnp_sent_low[0x20]; 5430 5431 u8 reserved_3[0x560]; 5432 }; 5433 5434 struct mlx5_ifc_query_cong_statistics_in_bits { 5435 u8 opcode[0x10]; 5436 u8 reserved_0[0x10]; 5437 5438 u8 reserved_1[0x10]; 5439 u8 op_mod[0x10]; 5440 5441 u8 clear[0x1]; 5442 u8 reserved_2[0x1f]; 5443 5444 u8 reserved_3[0x20]; 5445 }; 5446 5447 struct mlx5_ifc_query_cong_params_out_bits { 5448 u8 status[0x8]; 5449 u8 reserved_0[0x18]; 5450 5451 u8 syndrome[0x20]; 5452 5453 u8 reserved_1[0x40]; 5454 5455 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5456 }; 5457 5458 struct mlx5_ifc_query_cong_params_in_bits { 5459 u8 opcode[0x10]; 5460 u8 reserved_0[0x10]; 5461 5462 u8 reserved_1[0x10]; 5463 u8 op_mod[0x10]; 5464 5465 u8 reserved_2[0x1c]; 5466 u8 cong_protocol[0x4]; 5467 5468 u8 reserved_3[0x20]; 5469 }; 5470 5471 struct mlx5_ifc_query_burst_size_out_bits { 5472 u8 status[0x8]; 5473 u8 reserved_0[0x18]; 5474 5475 u8 syndrome[0x20]; 5476 5477 u8 reserved_1[0x20]; 5478 5479 u8 reserved_2[0x9]; 5480 u8 device_burst_size[0x17]; 5481 }; 5482 5483 struct mlx5_ifc_query_burst_size_in_bits { 5484 u8 opcode[0x10]; 5485 u8 reserved_0[0x10]; 5486 5487 u8 reserved_1[0x10]; 5488 u8 op_mod[0x10]; 5489 5490 u8 reserved_2[0x40]; 5491 }; 5492 5493 struct mlx5_ifc_query_adapter_out_bits { 5494 u8 status[0x8]; 5495 u8 reserved_0[0x18]; 5496 5497 u8 syndrome[0x20]; 5498 5499 u8 reserved_1[0x40]; 5500 5501 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5502 }; 5503 5504 struct mlx5_ifc_query_adapter_in_bits { 5505 u8 opcode[0x10]; 5506 u8 reserved_0[0x10]; 5507 5508 u8 reserved_1[0x10]; 5509 u8 op_mod[0x10]; 5510 5511 u8 reserved_2[0x40]; 5512 }; 5513 5514 struct mlx5_ifc_qp_2rst_out_bits { 5515 u8 status[0x8]; 5516 u8 reserved_0[0x18]; 5517 5518 u8 syndrome[0x20]; 5519 5520 u8 reserved_1[0x40]; 5521 }; 5522 5523 struct mlx5_ifc_qp_2rst_in_bits { 5524 u8 opcode[0x10]; 5525 u8 uid[0x10]; 5526 5527 u8 reserved_1[0x10]; 5528 u8 op_mod[0x10]; 5529 5530 u8 reserved_2[0x8]; 5531 u8 qpn[0x18]; 5532 5533 u8 reserved_3[0x20]; 5534 }; 5535 5536 struct mlx5_ifc_qp_2err_out_bits { 5537 u8 status[0x8]; 5538 u8 reserved_0[0x18]; 5539 5540 u8 syndrome[0x20]; 5541 5542 u8 reserved_1[0x40]; 5543 }; 5544 5545 struct mlx5_ifc_qp_2err_in_bits { 5546 u8 opcode[0x10]; 5547 u8 uid[0x10]; 5548 5549 u8 reserved_1[0x10]; 5550 u8 op_mod[0x10]; 5551 5552 u8 reserved_2[0x8]; 5553 u8 qpn[0x18]; 5554 5555 u8 reserved_3[0x20]; 5556 }; 5557 5558 struct mlx5_ifc_para_vport_element_bits { 5559 u8 reserved_at_0[0xc]; 5560 u8 traffic_class[0x4]; 5561 u8 qos_para_vport_number[0x10]; 5562 }; 5563 5564 struct mlx5_ifc_page_fault_resume_out_bits { 5565 u8 status[0x8]; 5566 u8 reserved_0[0x18]; 5567 5568 u8 syndrome[0x20]; 5569 5570 u8 reserved_1[0x40]; 5571 }; 5572 5573 struct mlx5_ifc_page_fault_resume_in_bits { 5574 u8 opcode[0x10]; 5575 u8 reserved_0[0x10]; 5576 5577 u8 reserved_1[0x10]; 5578 u8 op_mod[0x10]; 5579 5580 u8 error[0x1]; 5581 u8 reserved_2[0x4]; 5582 u8 rdma[0x1]; 5583 u8 read_write[0x1]; 5584 u8 req_res[0x1]; 5585 u8 qpn[0x18]; 5586 5587 u8 reserved_3[0x20]; 5588 }; 5589 5590 struct mlx5_ifc_nop_out_bits { 5591 u8 status[0x8]; 5592 u8 reserved_0[0x18]; 5593 5594 u8 syndrome[0x20]; 5595 5596 u8 reserved_1[0x40]; 5597 }; 5598 5599 struct mlx5_ifc_nop_in_bits { 5600 u8 opcode[0x10]; 5601 u8 reserved_0[0x10]; 5602 5603 u8 reserved_1[0x10]; 5604 u8 op_mod[0x10]; 5605 5606 u8 reserved_2[0x40]; 5607 }; 5608 5609 struct mlx5_ifc_modify_vport_state_out_bits { 5610 u8 status[0x8]; 5611 u8 reserved_0[0x18]; 5612 5613 u8 syndrome[0x20]; 5614 5615 u8 reserved_1[0x40]; 5616 }; 5617 5618 enum { 5619 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5620 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5621 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5622 }; 5623 5624 enum { 5625 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5626 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5627 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5628 }; 5629 5630 struct mlx5_ifc_modify_vport_state_in_bits { 5631 u8 opcode[0x10]; 5632 u8 reserved_0[0x10]; 5633 5634 u8 reserved_1[0x10]; 5635 u8 op_mod[0x10]; 5636 5637 u8 other_vport[0x1]; 5638 u8 reserved_2[0xf]; 5639 u8 vport_number[0x10]; 5640 5641 u8 reserved_3[0x18]; 5642 u8 admin_state[0x4]; 5643 u8 reserved_4[0x4]; 5644 }; 5645 5646 struct mlx5_ifc_modify_tis_out_bits { 5647 u8 status[0x8]; 5648 u8 reserved_0[0x18]; 5649 5650 u8 syndrome[0x20]; 5651 5652 u8 reserved_1[0x40]; 5653 }; 5654 5655 struct mlx5_ifc_modify_tis_bitmask_bits { 5656 u8 reserved_at_0[0x20]; 5657 5658 u8 reserved_at_20[0x1d]; 5659 u8 lag_tx_port_affinity[0x1]; 5660 u8 strict_lag_tx_port_affinity[0x1]; 5661 u8 prio[0x1]; 5662 }; 5663 5664 struct mlx5_ifc_modify_tis_in_bits { 5665 u8 opcode[0x10]; 5666 u8 uid[0x10]; 5667 5668 u8 reserved_1[0x10]; 5669 u8 op_mod[0x10]; 5670 5671 u8 reserved_2[0x8]; 5672 u8 tisn[0x18]; 5673 5674 u8 reserved_3[0x20]; 5675 5676 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5677 5678 u8 reserved_4[0x40]; 5679 5680 struct mlx5_ifc_tisc_bits ctx; 5681 }; 5682 5683 struct mlx5_ifc_modify_tir_out_bits { 5684 u8 status[0x8]; 5685 u8 reserved_0[0x18]; 5686 5687 u8 syndrome[0x20]; 5688 5689 u8 reserved_1[0x40]; 5690 }; 5691 5692 enum 5693 { 5694 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5695 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5696 }; 5697 5698 struct mlx5_ifc_modify_tir_in_bits { 5699 u8 opcode[0x10]; 5700 u8 uid[0x10]; 5701 5702 u8 reserved_1[0x10]; 5703 u8 op_mod[0x10]; 5704 5705 u8 reserved_2[0x8]; 5706 u8 tirn[0x18]; 5707 5708 u8 reserved_3[0x20]; 5709 5710 u8 modify_bitmask[0x40]; 5711 5712 u8 reserved_4[0x40]; 5713 5714 struct mlx5_ifc_tirc_bits tir_context; 5715 }; 5716 5717 struct mlx5_ifc_modify_sq_out_bits { 5718 u8 status[0x8]; 5719 u8 reserved_0[0x18]; 5720 5721 u8 syndrome[0x20]; 5722 5723 u8 reserved_1[0x40]; 5724 }; 5725 5726 struct mlx5_ifc_modify_sq_in_bits { 5727 u8 opcode[0x10]; 5728 u8 uid[0x10]; 5729 5730 u8 reserved_1[0x10]; 5731 u8 op_mod[0x10]; 5732 5733 u8 sq_state[0x4]; 5734 u8 reserved_2[0x4]; 5735 u8 sqn[0x18]; 5736 5737 u8 reserved_3[0x20]; 5738 5739 u8 modify_bitmask[0x40]; 5740 5741 u8 reserved_4[0x40]; 5742 5743 struct mlx5_ifc_sqc_bits ctx; 5744 }; 5745 5746 struct mlx5_ifc_modify_scheduling_element_out_bits { 5747 u8 status[0x8]; 5748 u8 reserved_at_8[0x18]; 5749 5750 u8 syndrome[0x20]; 5751 5752 u8 reserved_at_40[0x1c0]; 5753 }; 5754 5755 enum { 5756 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5757 }; 5758 5759 enum { 5760 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5761 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5762 }; 5763 5764 struct mlx5_ifc_modify_scheduling_element_in_bits { 5765 u8 opcode[0x10]; 5766 u8 reserved_at_10[0x10]; 5767 5768 u8 reserved_at_20[0x10]; 5769 u8 op_mod[0x10]; 5770 5771 u8 scheduling_hierarchy[0x8]; 5772 u8 reserved_at_48[0x18]; 5773 5774 u8 scheduling_element_id[0x20]; 5775 5776 u8 reserved_at_80[0x20]; 5777 5778 u8 modify_bitmask[0x20]; 5779 5780 u8 reserved_at_c0[0x40]; 5781 5782 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5783 5784 u8 reserved_at_300[0x100]; 5785 }; 5786 5787 struct mlx5_ifc_modify_rqt_out_bits { 5788 u8 status[0x8]; 5789 u8 reserved_0[0x18]; 5790 5791 u8 syndrome[0x20]; 5792 5793 u8 reserved_1[0x40]; 5794 }; 5795 5796 struct mlx5_ifc_rqt_bitmask_bits { 5797 u8 reserved_at_0[0x20]; 5798 5799 u8 reserved_at_20[0x1f]; 5800 u8 rqn_list[0x1]; 5801 }; 5802 5803 5804 struct mlx5_ifc_modify_rqt_in_bits { 5805 u8 opcode[0x10]; 5806 u8 uid[0x10]; 5807 5808 u8 reserved_1[0x10]; 5809 u8 op_mod[0x10]; 5810 5811 u8 reserved_2[0x8]; 5812 u8 rqtn[0x18]; 5813 5814 u8 reserved_3[0x20]; 5815 5816 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5817 5818 u8 reserved_4[0x40]; 5819 5820 struct mlx5_ifc_rqtc_bits ctx; 5821 }; 5822 5823 struct mlx5_ifc_modify_rq_out_bits { 5824 u8 status[0x8]; 5825 u8 reserved_0[0x18]; 5826 5827 u8 syndrome[0x20]; 5828 5829 u8 reserved_1[0x40]; 5830 }; 5831 5832 enum { 5833 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5834 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5835 }; 5836 5837 struct mlx5_ifc_modify_rq_in_bits { 5838 u8 opcode[0x10]; 5839 u8 uid[0x10]; 5840 5841 u8 reserved_1[0x10]; 5842 u8 op_mod[0x10]; 5843 5844 u8 rq_state[0x4]; 5845 u8 reserved_2[0x4]; 5846 u8 rqn[0x18]; 5847 5848 u8 reserved_3[0x20]; 5849 5850 u8 modify_bitmask[0x40]; 5851 5852 u8 reserved_4[0x40]; 5853 5854 struct mlx5_ifc_rqc_bits ctx; 5855 }; 5856 5857 struct mlx5_ifc_modify_rmp_out_bits { 5858 u8 status[0x8]; 5859 u8 reserved_0[0x18]; 5860 5861 u8 syndrome[0x20]; 5862 5863 u8 reserved_1[0x40]; 5864 }; 5865 5866 struct mlx5_ifc_rmp_bitmask_bits { 5867 u8 reserved[0x20]; 5868 5869 u8 reserved1[0x1f]; 5870 u8 lwm[0x1]; 5871 }; 5872 5873 struct mlx5_ifc_modify_rmp_in_bits { 5874 u8 opcode[0x10]; 5875 u8 uid[0x10]; 5876 5877 u8 reserved_1[0x10]; 5878 u8 op_mod[0x10]; 5879 5880 u8 rmp_state[0x4]; 5881 u8 reserved_2[0x4]; 5882 u8 rmpn[0x18]; 5883 5884 u8 reserved_3[0x20]; 5885 5886 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5887 5888 u8 reserved_4[0x40]; 5889 5890 struct mlx5_ifc_rmpc_bits ctx; 5891 }; 5892 5893 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5894 u8 status[0x8]; 5895 u8 reserved_0[0x18]; 5896 5897 u8 syndrome[0x20]; 5898 5899 u8 reserved_1[0x40]; 5900 }; 5901 5902 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5903 u8 reserved_0[0x14]; 5904 u8 disable_uc_local_lb[0x1]; 5905 u8 disable_mc_local_lb[0x1]; 5906 u8 node_guid[0x1]; 5907 u8 port_guid[0x1]; 5908 u8 min_wqe_inline_mode[0x1]; 5909 u8 mtu[0x1]; 5910 u8 change_event[0x1]; 5911 u8 promisc[0x1]; 5912 u8 permanent_address[0x1]; 5913 u8 addresses_list[0x1]; 5914 u8 roce_en[0x1]; 5915 u8 reserved_1[0x1]; 5916 }; 5917 5918 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5919 u8 opcode[0x10]; 5920 u8 reserved_0[0x10]; 5921 5922 u8 reserved_1[0x10]; 5923 u8 op_mod[0x10]; 5924 5925 u8 other_vport[0x1]; 5926 u8 reserved_2[0xf]; 5927 u8 vport_number[0x10]; 5928 5929 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5930 5931 u8 reserved_3[0x780]; 5932 5933 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5934 }; 5935 5936 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5937 u8 status[0x8]; 5938 u8 reserved_0[0x18]; 5939 5940 u8 syndrome[0x20]; 5941 5942 u8 reserved_1[0x40]; 5943 }; 5944 5945 struct mlx5_ifc_grh_bits { 5946 u8 ip_version[4]; 5947 u8 traffic_class[8]; 5948 u8 flow_label[20]; 5949 u8 payload_length[16]; 5950 u8 next_header[8]; 5951 u8 hop_limit[8]; 5952 u8 sgid[128]; 5953 u8 dgid[128]; 5954 }; 5955 5956 struct mlx5_ifc_bth_bits { 5957 u8 opcode[8]; 5958 u8 se[1]; 5959 u8 migreq[1]; 5960 u8 pad_count[2]; 5961 u8 tver[4]; 5962 u8 p_key[16]; 5963 u8 reserved8[8]; 5964 u8 dest_qp[24]; 5965 u8 ack_req[1]; 5966 u8 reserved7[7]; 5967 u8 psn[24]; 5968 }; 5969 5970 struct mlx5_ifc_aeth_bits { 5971 u8 syndrome[8]; 5972 u8 msn[24]; 5973 }; 5974 5975 struct mlx5_ifc_dceth_bits { 5976 u8 reserved0[8]; 5977 u8 session_id[24]; 5978 u8 reserved1[8]; 5979 u8 dci_dct[24]; 5980 }; 5981 5982 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5983 u8 opcode[0x10]; 5984 u8 reserved_0[0x10]; 5985 5986 u8 reserved_1[0x10]; 5987 u8 op_mod[0x10]; 5988 5989 u8 other_vport[0x1]; 5990 u8 reserved_2[0xb]; 5991 u8 port_num[0x4]; 5992 u8 vport_number[0x10]; 5993 5994 u8 reserved_3[0x20]; 5995 5996 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5997 }; 5998 5999 struct mlx5_ifc_modify_flow_table_out_bits { 6000 u8 status[0x8]; 6001 u8 reserved_at_8[0x18]; 6002 6003 u8 syndrome[0x20]; 6004 6005 u8 reserved_at_40[0x40]; 6006 }; 6007 6008 enum { 6009 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 6010 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 6011 }; 6012 6013 struct mlx5_ifc_modify_flow_table_in_bits { 6014 u8 opcode[0x10]; 6015 u8 reserved_at_10[0x10]; 6016 6017 u8 reserved_at_20[0x10]; 6018 u8 op_mod[0x10]; 6019 6020 u8 other_vport[0x1]; 6021 u8 reserved_at_41[0xf]; 6022 u8 vport_number[0x10]; 6023 6024 u8 reserved_at_60[0x10]; 6025 u8 modify_field_select[0x10]; 6026 6027 u8 table_type[0x8]; 6028 u8 reserved_at_88[0x18]; 6029 6030 u8 reserved_at_a0[0x8]; 6031 u8 table_id[0x18]; 6032 6033 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6034 }; 6035 6036 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6037 u8 status[0x8]; 6038 u8 reserved_0[0x18]; 6039 6040 u8 syndrome[0x20]; 6041 6042 u8 reserved_1[0x40]; 6043 }; 6044 6045 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6046 u8 reserved[0x1c]; 6047 u8 vport_cvlan_insert[0x1]; 6048 u8 vport_svlan_insert[0x1]; 6049 u8 vport_cvlan_strip[0x1]; 6050 u8 vport_svlan_strip[0x1]; 6051 }; 6052 6053 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6054 u8 opcode[0x10]; 6055 u8 reserved_0[0x10]; 6056 6057 u8 reserved_1[0x10]; 6058 u8 op_mod[0x10]; 6059 6060 u8 other_vport[0x1]; 6061 u8 reserved_2[0xf]; 6062 u8 vport_number[0x10]; 6063 6064 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6065 6066 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6067 }; 6068 6069 struct mlx5_ifc_modify_cq_out_bits { 6070 u8 status[0x8]; 6071 u8 reserved_0[0x18]; 6072 6073 u8 syndrome[0x20]; 6074 6075 u8 reserved_1[0x40]; 6076 }; 6077 6078 enum { 6079 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6080 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6081 }; 6082 6083 struct mlx5_ifc_modify_cq_in_bits { 6084 u8 opcode[0x10]; 6085 u8 uid[0x10]; 6086 6087 u8 reserved_1[0x10]; 6088 u8 op_mod[0x10]; 6089 6090 u8 reserved_2[0x8]; 6091 u8 cqn[0x18]; 6092 6093 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6094 6095 struct mlx5_ifc_cqc_bits cq_context; 6096 6097 u8 reserved_at_280[0x60]; 6098 6099 u8 cq_umem_valid[0x1]; 6100 u8 reserved_at_2e1[0x1f]; 6101 6102 u8 reserved_at_300[0x580]; 6103 6104 u8 pas[0][0x40]; 6105 }; 6106 6107 struct mlx5_ifc_modify_cong_status_out_bits { 6108 u8 status[0x8]; 6109 u8 reserved_0[0x18]; 6110 6111 u8 syndrome[0x20]; 6112 6113 u8 reserved_1[0x40]; 6114 }; 6115 6116 struct mlx5_ifc_modify_cong_status_in_bits { 6117 u8 opcode[0x10]; 6118 u8 reserved_0[0x10]; 6119 6120 u8 reserved_1[0x10]; 6121 u8 op_mod[0x10]; 6122 6123 u8 reserved_2[0x18]; 6124 u8 priority[0x4]; 6125 u8 cong_protocol[0x4]; 6126 6127 u8 enable[0x1]; 6128 u8 tag_enable[0x1]; 6129 u8 reserved_3[0x1e]; 6130 }; 6131 6132 struct mlx5_ifc_modify_cong_params_out_bits { 6133 u8 status[0x8]; 6134 u8 reserved_0[0x18]; 6135 6136 u8 syndrome[0x20]; 6137 6138 u8 reserved_1[0x40]; 6139 }; 6140 6141 struct mlx5_ifc_modify_cong_params_in_bits { 6142 u8 opcode[0x10]; 6143 u8 reserved_0[0x10]; 6144 6145 u8 reserved_1[0x10]; 6146 u8 op_mod[0x10]; 6147 6148 u8 reserved_2[0x1c]; 6149 u8 cong_protocol[0x4]; 6150 6151 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6152 6153 u8 reserved_3[0x80]; 6154 6155 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6156 }; 6157 6158 struct mlx5_ifc_manage_pages_out_bits { 6159 u8 status[0x8]; 6160 u8 reserved_0[0x18]; 6161 6162 u8 syndrome[0x20]; 6163 6164 u8 output_num_entries[0x20]; 6165 6166 u8 reserved_1[0x20]; 6167 6168 u8 pas[0][0x40]; 6169 }; 6170 6171 enum { 6172 MLX5_PAGES_CANT_GIVE = 0x0, 6173 MLX5_PAGES_GIVE = 0x1, 6174 MLX5_PAGES_TAKE = 0x2, 6175 }; 6176 6177 struct mlx5_ifc_manage_pages_in_bits { 6178 u8 opcode[0x10]; 6179 u8 reserved_0[0x10]; 6180 6181 u8 reserved_1[0x10]; 6182 u8 op_mod[0x10]; 6183 6184 u8 reserved_2[0x10]; 6185 u8 function_id[0x10]; 6186 6187 u8 input_num_entries[0x20]; 6188 6189 u8 pas[0][0x40]; 6190 }; 6191 6192 struct mlx5_ifc_mad_ifc_out_bits { 6193 u8 status[0x8]; 6194 u8 reserved_0[0x18]; 6195 6196 u8 syndrome[0x20]; 6197 6198 u8 reserved_1[0x40]; 6199 6200 u8 response_mad_packet[256][0x8]; 6201 }; 6202 6203 struct mlx5_ifc_mad_ifc_in_bits { 6204 u8 opcode[0x10]; 6205 u8 reserved_0[0x10]; 6206 6207 u8 reserved_1[0x10]; 6208 u8 op_mod[0x10]; 6209 6210 u8 remote_lid[0x10]; 6211 u8 reserved_2[0x8]; 6212 u8 port[0x8]; 6213 6214 u8 reserved_3[0x20]; 6215 6216 u8 mad[256][0x8]; 6217 }; 6218 6219 struct mlx5_ifc_init_hca_out_bits { 6220 u8 status[0x8]; 6221 u8 reserved_0[0x18]; 6222 6223 u8 syndrome[0x20]; 6224 6225 u8 reserved_1[0x40]; 6226 }; 6227 6228 enum { 6229 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 6230 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 6231 }; 6232 6233 struct mlx5_ifc_init_hca_in_bits { 6234 u8 opcode[0x10]; 6235 u8 reserved_0[0x10]; 6236 6237 u8 reserved_1[0x10]; 6238 u8 op_mod[0x10]; 6239 6240 u8 reserved_2[0x40]; 6241 }; 6242 6243 struct mlx5_ifc_init2rtr_qp_out_bits { 6244 u8 status[0x8]; 6245 u8 reserved_0[0x18]; 6246 6247 u8 syndrome[0x20]; 6248 6249 u8 reserved_1[0x40]; 6250 }; 6251 6252 struct mlx5_ifc_init2rtr_qp_in_bits { 6253 u8 opcode[0x10]; 6254 u8 uid[0x10]; 6255 6256 u8 reserved_1[0x10]; 6257 u8 op_mod[0x10]; 6258 6259 u8 reserved_2[0x8]; 6260 u8 qpn[0x18]; 6261 6262 u8 reserved_3[0x20]; 6263 6264 u8 opt_param_mask[0x20]; 6265 6266 u8 reserved_4[0x20]; 6267 6268 struct mlx5_ifc_qpc_bits qpc; 6269 6270 u8 reserved_5[0x80]; 6271 }; 6272 6273 struct mlx5_ifc_init2init_qp_out_bits { 6274 u8 status[0x8]; 6275 u8 reserved_0[0x18]; 6276 6277 u8 syndrome[0x20]; 6278 6279 u8 reserved_1[0x40]; 6280 }; 6281 6282 struct mlx5_ifc_init2init_qp_in_bits { 6283 u8 opcode[0x10]; 6284 u8 uid[0x10]; 6285 6286 u8 reserved_1[0x10]; 6287 u8 op_mod[0x10]; 6288 6289 u8 reserved_2[0x8]; 6290 u8 qpn[0x18]; 6291 6292 u8 reserved_3[0x20]; 6293 6294 u8 opt_param_mask[0x20]; 6295 6296 u8 reserved_4[0x20]; 6297 6298 struct mlx5_ifc_qpc_bits qpc; 6299 6300 u8 reserved_5[0x80]; 6301 }; 6302 6303 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6304 u8 status[0x8]; 6305 u8 reserved_0[0x18]; 6306 6307 u8 syndrome[0x20]; 6308 6309 u8 reserved_1[0x40]; 6310 6311 u8 packet_headers_log[128][0x8]; 6312 6313 u8 packet_syndrome[64][0x8]; 6314 }; 6315 6316 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6317 u8 opcode[0x10]; 6318 u8 reserved_0[0x10]; 6319 6320 u8 reserved_1[0x10]; 6321 u8 op_mod[0x10]; 6322 6323 u8 reserved_2[0x40]; 6324 }; 6325 6326 struct mlx5_ifc_encryption_key_obj_bits { 6327 u8 modify_field_select[0x40]; 6328 6329 u8 reserved_at_40[0x14]; 6330 u8 key_size[0x4]; 6331 u8 reserved_at_58[0x4]; 6332 u8 key_type[0x4]; 6333 6334 u8 reserved_at_60[0x8]; 6335 u8 pd[0x18]; 6336 6337 u8 reserved_at_80[0x180]; 6338 6339 u8 key[8][0x20]; 6340 6341 u8 reserved_at_300[0x500]; 6342 }; 6343 6344 struct mlx5_ifc_gen_eqe_in_bits { 6345 u8 opcode[0x10]; 6346 u8 reserved_0[0x10]; 6347 6348 u8 reserved_1[0x10]; 6349 u8 op_mod[0x10]; 6350 6351 u8 reserved_2[0x18]; 6352 u8 eq_number[0x8]; 6353 6354 u8 reserved_3[0x20]; 6355 6356 u8 eqe[64][0x8]; 6357 }; 6358 6359 struct mlx5_ifc_gen_eq_out_bits { 6360 u8 status[0x8]; 6361 u8 reserved_0[0x18]; 6362 6363 u8 syndrome[0x20]; 6364 6365 u8 reserved_1[0x40]; 6366 }; 6367 6368 struct mlx5_ifc_enable_hca_out_bits { 6369 u8 status[0x8]; 6370 u8 reserved_0[0x18]; 6371 6372 u8 syndrome[0x20]; 6373 6374 u8 reserved_1[0x20]; 6375 }; 6376 6377 struct mlx5_ifc_enable_hca_in_bits { 6378 u8 opcode[0x10]; 6379 u8 reserved_0[0x10]; 6380 6381 u8 reserved_1[0x10]; 6382 u8 op_mod[0x10]; 6383 6384 u8 reserved_2[0x10]; 6385 u8 function_id[0x10]; 6386 6387 u8 reserved_3[0x20]; 6388 }; 6389 6390 struct mlx5_ifc_drain_dct_out_bits { 6391 u8 status[0x8]; 6392 u8 reserved_0[0x18]; 6393 6394 u8 syndrome[0x20]; 6395 6396 u8 reserved_1[0x40]; 6397 }; 6398 6399 struct mlx5_ifc_drain_dct_in_bits { 6400 u8 opcode[0x10]; 6401 u8 uid[0x10]; 6402 6403 u8 reserved_1[0x10]; 6404 u8 op_mod[0x10]; 6405 6406 u8 reserved_2[0x8]; 6407 u8 dctn[0x18]; 6408 6409 u8 reserved_3[0x20]; 6410 }; 6411 6412 struct mlx5_ifc_disable_hca_out_bits { 6413 u8 status[0x8]; 6414 u8 reserved_0[0x18]; 6415 6416 u8 syndrome[0x20]; 6417 6418 u8 reserved_1[0x20]; 6419 }; 6420 6421 struct mlx5_ifc_disable_hca_in_bits { 6422 u8 opcode[0x10]; 6423 u8 reserved_0[0x10]; 6424 6425 u8 reserved_1[0x10]; 6426 u8 op_mod[0x10]; 6427 6428 u8 reserved_2[0x10]; 6429 u8 function_id[0x10]; 6430 6431 u8 reserved_3[0x20]; 6432 }; 6433 6434 struct mlx5_ifc_detach_from_mcg_out_bits { 6435 u8 status[0x8]; 6436 u8 reserved_0[0x18]; 6437 6438 u8 syndrome[0x20]; 6439 6440 u8 reserved_1[0x40]; 6441 }; 6442 6443 struct mlx5_ifc_detach_from_mcg_in_bits { 6444 u8 opcode[0x10]; 6445 u8 uid[0x10]; 6446 6447 u8 reserved_1[0x10]; 6448 u8 op_mod[0x10]; 6449 6450 u8 reserved_2[0x8]; 6451 u8 qpn[0x18]; 6452 6453 u8 reserved_3[0x20]; 6454 6455 u8 multicast_gid[16][0x8]; 6456 }; 6457 6458 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6459 u8 status[0x8]; 6460 u8 reserved_0[0x18]; 6461 6462 u8 syndrome[0x20]; 6463 6464 u8 reserved_1[0x40]; 6465 }; 6466 6467 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6468 u8 opcode[0x10]; 6469 u8 uid[0x10]; 6470 6471 u8 reserved_1[0x10]; 6472 u8 op_mod[0x10]; 6473 6474 u8 reserved_2[0x8]; 6475 u8 xrc_srqn[0x18]; 6476 6477 u8 reserved_3[0x20]; 6478 }; 6479 6480 struct mlx5_ifc_destroy_tis_out_bits { 6481 u8 status[0x8]; 6482 u8 reserved_0[0x18]; 6483 6484 u8 syndrome[0x20]; 6485 6486 u8 reserved_1[0x40]; 6487 }; 6488 6489 struct mlx5_ifc_destroy_tis_in_bits { 6490 u8 opcode[0x10]; 6491 u8 uid[0x10]; 6492 6493 u8 reserved_1[0x10]; 6494 u8 op_mod[0x10]; 6495 6496 u8 reserved_2[0x8]; 6497 u8 tisn[0x18]; 6498 6499 u8 reserved_3[0x20]; 6500 }; 6501 6502 struct mlx5_ifc_destroy_tir_out_bits { 6503 u8 status[0x8]; 6504 u8 reserved_0[0x18]; 6505 6506 u8 syndrome[0x20]; 6507 6508 u8 reserved_1[0x40]; 6509 }; 6510 6511 struct mlx5_ifc_destroy_tir_in_bits { 6512 u8 opcode[0x10]; 6513 u8 uid[0x10]; 6514 6515 u8 reserved_1[0x10]; 6516 u8 op_mod[0x10]; 6517 6518 u8 reserved_2[0x8]; 6519 u8 tirn[0x18]; 6520 6521 u8 reserved_3[0x20]; 6522 }; 6523 6524 struct mlx5_ifc_destroy_srq_out_bits { 6525 u8 status[0x8]; 6526 u8 reserved_0[0x18]; 6527 6528 u8 syndrome[0x20]; 6529 6530 u8 reserved_1[0x40]; 6531 }; 6532 6533 struct mlx5_ifc_destroy_srq_in_bits { 6534 u8 opcode[0x10]; 6535 u8 uid[0x10]; 6536 6537 u8 reserved_1[0x10]; 6538 u8 op_mod[0x10]; 6539 6540 u8 reserved_2[0x8]; 6541 u8 srqn[0x18]; 6542 6543 u8 reserved_3[0x20]; 6544 }; 6545 6546 struct mlx5_ifc_destroy_sq_out_bits { 6547 u8 status[0x8]; 6548 u8 reserved_0[0x18]; 6549 6550 u8 syndrome[0x20]; 6551 6552 u8 reserved_1[0x40]; 6553 }; 6554 6555 struct mlx5_ifc_destroy_sq_in_bits { 6556 u8 opcode[0x10]; 6557 u8 uid[0x10]; 6558 6559 u8 reserved_1[0x10]; 6560 u8 op_mod[0x10]; 6561 6562 u8 reserved_2[0x8]; 6563 u8 sqn[0x18]; 6564 6565 u8 reserved_3[0x20]; 6566 }; 6567 6568 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6569 u8 status[0x8]; 6570 u8 reserved_at_8[0x18]; 6571 6572 u8 syndrome[0x20]; 6573 6574 u8 reserved_at_40[0x1c0]; 6575 }; 6576 6577 enum { 6578 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6579 }; 6580 6581 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6582 u8 opcode[0x10]; 6583 u8 reserved_at_10[0x10]; 6584 6585 u8 reserved_at_20[0x10]; 6586 u8 op_mod[0x10]; 6587 6588 u8 scheduling_hierarchy[0x8]; 6589 u8 reserved_at_48[0x18]; 6590 6591 u8 scheduling_element_id[0x20]; 6592 6593 u8 reserved_at_80[0x180]; 6594 }; 6595 6596 struct mlx5_ifc_destroy_rqt_out_bits { 6597 u8 status[0x8]; 6598 u8 reserved_0[0x18]; 6599 6600 u8 syndrome[0x20]; 6601 6602 u8 reserved_1[0x40]; 6603 }; 6604 6605 struct mlx5_ifc_destroy_rqt_in_bits { 6606 u8 opcode[0x10]; 6607 u8 uid[0x10]; 6608 6609 u8 reserved_1[0x10]; 6610 u8 op_mod[0x10]; 6611 6612 u8 reserved_2[0x8]; 6613 u8 rqtn[0x18]; 6614 6615 u8 reserved_3[0x20]; 6616 }; 6617 6618 struct mlx5_ifc_destroy_rq_out_bits { 6619 u8 status[0x8]; 6620 u8 reserved_0[0x18]; 6621 6622 u8 syndrome[0x20]; 6623 6624 u8 reserved_1[0x40]; 6625 }; 6626 6627 struct mlx5_ifc_destroy_rq_in_bits { 6628 u8 opcode[0x10]; 6629 u8 uid[0x10]; 6630 6631 u8 reserved_1[0x10]; 6632 u8 op_mod[0x10]; 6633 6634 u8 reserved_2[0x8]; 6635 u8 rqn[0x18]; 6636 6637 u8 reserved_3[0x20]; 6638 }; 6639 6640 struct mlx5_ifc_destroy_rmp_out_bits { 6641 u8 status[0x8]; 6642 u8 reserved_0[0x18]; 6643 6644 u8 syndrome[0x20]; 6645 6646 u8 reserved_1[0x40]; 6647 }; 6648 6649 struct mlx5_ifc_destroy_rmp_in_bits { 6650 u8 opcode[0x10]; 6651 u8 reserved_0[0x10]; 6652 6653 u8 reserved_1[0x10]; 6654 u8 op_mod[0x10]; 6655 6656 u8 reserved_2[0x8]; 6657 u8 rmpn[0x18]; 6658 6659 u8 reserved_3[0x20]; 6660 }; 6661 6662 struct mlx5_ifc_destroy_qp_out_bits { 6663 u8 status[0x8]; 6664 u8 reserved_0[0x18]; 6665 6666 u8 syndrome[0x20]; 6667 6668 u8 reserved_1[0x40]; 6669 }; 6670 6671 struct mlx5_ifc_destroy_qp_in_bits { 6672 u8 opcode[0x10]; 6673 u8 uid[0x10]; 6674 6675 u8 reserved_1[0x10]; 6676 u8 op_mod[0x10]; 6677 6678 u8 reserved_2[0x8]; 6679 u8 qpn[0x18]; 6680 6681 u8 reserved_3[0x20]; 6682 }; 6683 6684 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6685 u8 status[0x8]; 6686 u8 reserved_at_8[0x18]; 6687 6688 u8 syndrome[0x20]; 6689 6690 u8 reserved_at_40[0x1c0]; 6691 }; 6692 6693 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6694 u8 opcode[0x10]; 6695 u8 reserved_at_10[0x10]; 6696 6697 u8 reserved_at_20[0x10]; 6698 u8 op_mod[0x10]; 6699 6700 u8 reserved_at_40[0x20]; 6701 6702 u8 reserved_at_60[0x10]; 6703 u8 qos_para_vport_number[0x10]; 6704 6705 u8 reserved_at_80[0x180]; 6706 }; 6707 6708 struct mlx5_ifc_destroy_psv_out_bits { 6709 u8 status[0x8]; 6710 u8 reserved_0[0x18]; 6711 6712 u8 syndrome[0x20]; 6713 6714 u8 reserved_1[0x40]; 6715 }; 6716 6717 struct mlx5_ifc_destroy_psv_in_bits { 6718 u8 opcode[0x10]; 6719 u8 reserved_0[0x10]; 6720 6721 u8 reserved_1[0x10]; 6722 u8 op_mod[0x10]; 6723 6724 u8 reserved_2[0x8]; 6725 u8 psvn[0x18]; 6726 6727 u8 reserved_3[0x20]; 6728 }; 6729 6730 struct mlx5_ifc_destroy_mkey_out_bits { 6731 u8 status[0x8]; 6732 u8 reserved_0[0x18]; 6733 6734 u8 syndrome[0x20]; 6735 6736 u8 reserved_1[0x40]; 6737 }; 6738 6739 struct mlx5_ifc_destroy_mkey_in_bits { 6740 u8 opcode[0x10]; 6741 u8 reserved_0[0x10]; 6742 6743 u8 reserved_1[0x10]; 6744 u8 op_mod[0x10]; 6745 6746 u8 reserved_2[0x8]; 6747 u8 mkey_index[0x18]; 6748 6749 u8 reserved_3[0x20]; 6750 }; 6751 6752 struct mlx5_ifc_destroy_flow_table_out_bits { 6753 u8 status[0x8]; 6754 u8 reserved_0[0x18]; 6755 6756 u8 syndrome[0x20]; 6757 6758 u8 reserved_1[0x40]; 6759 }; 6760 6761 struct mlx5_ifc_destroy_flow_table_in_bits { 6762 u8 opcode[0x10]; 6763 u8 reserved_0[0x10]; 6764 6765 u8 reserved_1[0x10]; 6766 u8 op_mod[0x10]; 6767 6768 u8 other_vport[0x1]; 6769 u8 reserved_2[0xf]; 6770 u8 vport_number[0x10]; 6771 6772 u8 reserved_3[0x20]; 6773 6774 u8 table_type[0x8]; 6775 u8 reserved_4[0x18]; 6776 6777 u8 reserved_5[0x8]; 6778 u8 table_id[0x18]; 6779 6780 u8 reserved_6[0x140]; 6781 }; 6782 6783 struct mlx5_ifc_destroy_flow_group_out_bits { 6784 u8 status[0x8]; 6785 u8 reserved_0[0x18]; 6786 6787 u8 syndrome[0x20]; 6788 6789 u8 reserved_1[0x40]; 6790 }; 6791 6792 struct mlx5_ifc_destroy_flow_group_in_bits { 6793 u8 opcode[0x10]; 6794 u8 reserved_0[0x10]; 6795 6796 u8 reserved_1[0x10]; 6797 u8 op_mod[0x10]; 6798 6799 u8 other_vport[0x1]; 6800 u8 reserved_2[0xf]; 6801 u8 vport_number[0x10]; 6802 6803 u8 reserved_3[0x20]; 6804 6805 u8 table_type[0x8]; 6806 u8 reserved_4[0x18]; 6807 6808 u8 reserved_5[0x8]; 6809 u8 table_id[0x18]; 6810 6811 u8 group_id[0x20]; 6812 6813 u8 reserved_6[0x120]; 6814 }; 6815 6816 struct mlx5_ifc_destroy_encryption_key_out_bits { 6817 u8 status[0x8]; 6818 u8 reserved_at_8[0x18]; 6819 6820 u8 syndrome[0x20]; 6821 6822 u8 reserved_at_40[0x40]; 6823 }; 6824 6825 struct mlx5_ifc_destroy_encryption_key_in_bits { 6826 u8 opcode[0x10]; 6827 u8 reserved_at_10[0x10]; 6828 6829 u8 reserved_at_20[0x10]; 6830 u8 obj_type[0x10]; 6831 6832 u8 obj_id[0x20]; 6833 6834 u8 reserved_at_60[0x20]; 6835 }; 6836 6837 struct mlx5_ifc_destroy_eq_out_bits { 6838 u8 status[0x8]; 6839 u8 reserved_0[0x18]; 6840 6841 u8 syndrome[0x20]; 6842 6843 u8 reserved_1[0x40]; 6844 }; 6845 6846 struct mlx5_ifc_destroy_eq_in_bits { 6847 u8 opcode[0x10]; 6848 u8 reserved_0[0x10]; 6849 6850 u8 reserved_1[0x10]; 6851 u8 op_mod[0x10]; 6852 6853 u8 reserved_2[0x18]; 6854 u8 eq_number[0x8]; 6855 6856 u8 reserved_3[0x20]; 6857 }; 6858 6859 struct mlx5_ifc_destroy_dct_out_bits { 6860 u8 status[0x8]; 6861 u8 reserved_0[0x18]; 6862 6863 u8 syndrome[0x20]; 6864 6865 u8 reserved_1[0x40]; 6866 }; 6867 6868 struct mlx5_ifc_destroy_dct_in_bits { 6869 u8 opcode[0x10]; 6870 u8 uid[0x10]; 6871 6872 u8 reserved_1[0x10]; 6873 u8 op_mod[0x10]; 6874 6875 u8 reserved_2[0x8]; 6876 u8 dctn[0x18]; 6877 6878 u8 reserved_3[0x20]; 6879 }; 6880 6881 struct mlx5_ifc_destroy_cq_out_bits { 6882 u8 status[0x8]; 6883 u8 reserved_0[0x18]; 6884 6885 u8 syndrome[0x20]; 6886 6887 u8 reserved_1[0x40]; 6888 }; 6889 6890 struct mlx5_ifc_destroy_cq_in_bits { 6891 u8 opcode[0x10]; 6892 u8 uid[0x10]; 6893 6894 u8 reserved_1[0x10]; 6895 u8 op_mod[0x10]; 6896 6897 u8 reserved_2[0x8]; 6898 u8 cqn[0x18]; 6899 6900 u8 reserved_3[0x20]; 6901 }; 6902 6903 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6904 u8 status[0x8]; 6905 u8 reserved_0[0x18]; 6906 6907 u8 syndrome[0x20]; 6908 6909 u8 reserved_1[0x40]; 6910 }; 6911 6912 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6913 u8 opcode[0x10]; 6914 u8 reserved_0[0x10]; 6915 6916 u8 reserved_1[0x10]; 6917 u8 op_mod[0x10]; 6918 6919 u8 reserved_2[0x20]; 6920 6921 u8 reserved_3[0x10]; 6922 u8 vxlan_udp_port[0x10]; 6923 }; 6924 6925 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6926 u8 status[0x8]; 6927 u8 reserved_0[0x18]; 6928 6929 u8 syndrome[0x20]; 6930 6931 u8 reserved_1[0x40]; 6932 }; 6933 6934 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6935 u8 opcode[0x10]; 6936 u8 reserved_0[0x10]; 6937 6938 u8 reserved_1[0x10]; 6939 u8 op_mod[0x10]; 6940 6941 u8 reserved_2[0x60]; 6942 6943 u8 reserved_3[0x8]; 6944 u8 table_index[0x18]; 6945 6946 u8 reserved_4[0x140]; 6947 }; 6948 6949 struct mlx5_ifc_delete_fte_out_bits { 6950 u8 status[0x8]; 6951 u8 reserved_0[0x18]; 6952 6953 u8 syndrome[0x20]; 6954 6955 u8 reserved_1[0x40]; 6956 }; 6957 6958 struct mlx5_ifc_delete_fte_in_bits { 6959 u8 opcode[0x10]; 6960 u8 reserved_0[0x10]; 6961 6962 u8 reserved_1[0x10]; 6963 u8 op_mod[0x10]; 6964 6965 u8 other_vport[0x1]; 6966 u8 reserved_2[0xf]; 6967 u8 vport_number[0x10]; 6968 6969 u8 reserved_3[0x20]; 6970 6971 u8 table_type[0x8]; 6972 u8 reserved_4[0x18]; 6973 6974 u8 reserved_5[0x8]; 6975 u8 table_id[0x18]; 6976 6977 u8 reserved_6[0x40]; 6978 6979 u8 flow_index[0x20]; 6980 6981 u8 reserved_7[0xe0]; 6982 }; 6983 6984 struct mlx5_ifc_dealloc_xrcd_out_bits { 6985 u8 status[0x8]; 6986 u8 reserved_0[0x18]; 6987 6988 u8 syndrome[0x20]; 6989 6990 u8 reserved_1[0x40]; 6991 }; 6992 6993 struct mlx5_ifc_dealloc_xrcd_in_bits { 6994 u8 opcode[0x10]; 6995 u8 uid[0x10]; 6996 6997 u8 reserved_1[0x10]; 6998 u8 op_mod[0x10]; 6999 7000 u8 reserved_2[0x8]; 7001 u8 xrcd[0x18]; 7002 7003 u8 reserved_3[0x20]; 7004 }; 7005 7006 struct mlx5_ifc_dealloc_uar_out_bits { 7007 u8 status[0x8]; 7008 u8 reserved_0[0x18]; 7009 7010 u8 syndrome[0x20]; 7011 7012 u8 reserved_1[0x40]; 7013 }; 7014 7015 struct mlx5_ifc_dealloc_uar_in_bits { 7016 u8 opcode[0x10]; 7017 u8 reserved_0[0x10]; 7018 7019 u8 reserved_1[0x10]; 7020 u8 op_mod[0x10]; 7021 7022 u8 reserved_2[0x8]; 7023 u8 uar[0x18]; 7024 7025 u8 reserved_3[0x20]; 7026 }; 7027 7028 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7029 u8 status[0x8]; 7030 u8 reserved_0[0x18]; 7031 7032 u8 syndrome[0x20]; 7033 7034 u8 reserved_1[0x40]; 7035 }; 7036 7037 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7038 u8 opcode[0x10]; 7039 u8 uid[0x10]; 7040 7041 u8 reserved_1[0x10]; 7042 u8 op_mod[0x10]; 7043 7044 u8 reserved_2[0x8]; 7045 u8 transport_domain[0x18]; 7046 7047 u8 reserved_3[0x20]; 7048 }; 7049 7050 struct mlx5_ifc_dealloc_q_counter_out_bits { 7051 u8 status[0x8]; 7052 u8 reserved_0[0x18]; 7053 7054 u8 syndrome[0x20]; 7055 7056 u8 reserved_1[0x40]; 7057 }; 7058 7059 struct mlx5_ifc_counter_id_bits { 7060 u8 reserved[0x10]; 7061 u8 counter_id[0x10]; 7062 }; 7063 7064 struct mlx5_ifc_diagnostic_params_context_bits { 7065 u8 num_of_counters[0x10]; 7066 u8 reserved_2[0x8]; 7067 u8 log_num_of_samples[0x8]; 7068 7069 u8 single[0x1]; 7070 u8 repetitive[0x1]; 7071 u8 sync[0x1]; 7072 u8 clear[0x1]; 7073 u8 on_demand[0x1]; 7074 u8 enable[0x1]; 7075 u8 reserved_3[0x12]; 7076 u8 log_sample_period[0x8]; 7077 7078 u8 reserved_4[0x80]; 7079 7080 struct mlx5_ifc_counter_id_bits counter_id[0]; 7081 }; 7082 7083 struct mlx5_ifc_set_diagnostic_params_in_bits { 7084 u8 opcode[0x10]; 7085 u8 reserved_0[0x10]; 7086 7087 u8 reserved_1[0x10]; 7088 u8 op_mod[0x10]; 7089 7090 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 7091 }; 7092 7093 struct mlx5_ifc_set_diagnostic_params_out_bits { 7094 u8 status[0x8]; 7095 u8 reserved_0[0x18]; 7096 7097 u8 syndrome[0x20]; 7098 7099 u8 reserved_1[0x40]; 7100 }; 7101 7102 struct mlx5_ifc_query_diagnostic_counters_in_bits { 7103 u8 opcode[0x10]; 7104 u8 reserved_0[0x10]; 7105 7106 u8 reserved_1[0x10]; 7107 u8 op_mod[0x10]; 7108 7109 u8 num_of_samples[0x10]; 7110 u8 sample_index[0x10]; 7111 7112 u8 reserved_2[0x20]; 7113 }; 7114 7115 struct mlx5_ifc_diagnostic_counter_bits { 7116 u8 counter_id[0x10]; 7117 u8 sample_id[0x10]; 7118 7119 u8 time_stamp_31_0[0x20]; 7120 7121 u8 counter_value_h[0x20]; 7122 7123 u8 counter_value_l[0x20]; 7124 }; 7125 7126 struct mlx5_ifc_query_diagnostic_counters_out_bits { 7127 u8 status[0x8]; 7128 u8 reserved_0[0x18]; 7129 7130 u8 syndrome[0x20]; 7131 7132 u8 reserved_1[0x40]; 7133 7134 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 7135 }; 7136 7137 struct mlx5_ifc_dealloc_q_counter_in_bits { 7138 u8 opcode[0x10]; 7139 u8 reserved_0[0x10]; 7140 7141 u8 reserved_1[0x10]; 7142 u8 op_mod[0x10]; 7143 7144 u8 reserved_2[0x18]; 7145 u8 counter_set_id[0x8]; 7146 7147 u8 reserved_3[0x20]; 7148 }; 7149 7150 struct mlx5_ifc_dealloc_pd_out_bits { 7151 u8 status[0x8]; 7152 u8 reserved_0[0x18]; 7153 7154 u8 syndrome[0x20]; 7155 7156 u8 reserved_1[0x40]; 7157 }; 7158 7159 struct mlx5_ifc_dealloc_pd_in_bits { 7160 u8 opcode[0x10]; 7161 u8 uid[0x10]; 7162 7163 u8 reserved_1[0x10]; 7164 u8 op_mod[0x10]; 7165 7166 u8 reserved_2[0x8]; 7167 u8 pd[0x18]; 7168 7169 u8 reserved_3[0x20]; 7170 }; 7171 7172 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7173 u8 status[0x8]; 7174 u8 reserved_0[0x18]; 7175 7176 u8 syndrome[0x20]; 7177 7178 u8 reserved_1[0x40]; 7179 }; 7180 7181 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7182 u8 opcode[0x10]; 7183 u8 reserved_0[0x10]; 7184 7185 u8 reserved_1[0x10]; 7186 u8 op_mod[0x10]; 7187 7188 u8 reserved_2[0x10]; 7189 u8 flow_counter_id[0x10]; 7190 7191 u8 reserved_3[0x20]; 7192 }; 7193 7194 struct mlx5_ifc_create_xrq_out_bits { 7195 u8 status[0x8]; 7196 u8 reserved_at_8[0x18]; 7197 7198 u8 syndrome[0x20]; 7199 7200 u8 reserved_at_40[0x8]; 7201 u8 xrqn[0x18]; 7202 7203 u8 reserved_at_60[0x20]; 7204 }; 7205 7206 struct mlx5_ifc_create_xrq_in_bits { 7207 u8 opcode[0x10]; 7208 u8 uid[0x10]; 7209 7210 u8 reserved_at_20[0x10]; 7211 u8 op_mod[0x10]; 7212 7213 u8 reserved_at_40[0x40]; 7214 7215 struct mlx5_ifc_xrqc_bits xrq_context; 7216 }; 7217 7218 struct mlx5_ifc_deactivate_tracer_out_bits { 7219 u8 status[0x8]; 7220 u8 reserved_0[0x18]; 7221 7222 u8 syndrome[0x20]; 7223 7224 u8 reserved_1[0x40]; 7225 }; 7226 7227 struct mlx5_ifc_deactivate_tracer_in_bits { 7228 u8 opcode[0x10]; 7229 u8 reserved_0[0x10]; 7230 7231 u8 reserved_1[0x10]; 7232 u8 op_mod[0x10]; 7233 7234 u8 mkey[0x20]; 7235 7236 u8 reserved_2[0x20]; 7237 }; 7238 7239 struct mlx5_ifc_create_xrc_srq_out_bits { 7240 u8 status[0x8]; 7241 u8 reserved_0[0x18]; 7242 7243 u8 syndrome[0x20]; 7244 7245 u8 reserved_1[0x8]; 7246 u8 xrc_srqn[0x18]; 7247 7248 u8 reserved_2[0x20]; 7249 }; 7250 7251 struct mlx5_ifc_create_xrc_srq_in_bits { 7252 u8 opcode[0x10]; 7253 u8 uid[0x10]; 7254 7255 u8 reserved_1[0x10]; 7256 u8 op_mod[0x10]; 7257 7258 u8 reserved_2[0x40]; 7259 7260 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7261 7262 u8 reserved_at_280[0x60]; 7263 7264 u8 xrc_srq_umem_valid[0x1]; 7265 u8 reserved_at_2e1[0x1f]; 7266 7267 u8 reserved_at_300[0x580]; 7268 7269 u8 pas[0][0x40]; 7270 }; 7271 7272 struct mlx5_ifc_create_tis_out_bits { 7273 u8 status[0x8]; 7274 u8 reserved_0[0x18]; 7275 7276 u8 syndrome[0x20]; 7277 7278 u8 reserved_1[0x8]; 7279 u8 tisn[0x18]; 7280 7281 u8 reserved_2[0x20]; 7282 }; 7283 7284 struct mlx5_ifc_create_tis_in_bits { 7285 u8 opcode[0x10]; 7286 u8 uid[0x10]; 7287 7288 u8 reserved_1[0x10]; 7289 u8 op_mod[0x10]; 7290 7291 u8 reserved_2[0xc0]; 7292 7293 struct mlx5_ifc_tisc_bits ctx; 7294 }; 7295 7296 struct mlx5_ifc_create_tir_out_bits { 7297 u8 status[0x8]; 7298 u8 reserved_0[0x18]; 7299 7300 u8 syndrome[0x20]; 7301 7302 u8 reserved_1[0x8]; 7303 u8 tirn[0x18]; 7304 7305 u8 reserved_2[0x20]; 7306 }; 7307 7308 struct mlx5_ifc_create_tir_in_bits { 7309 u8 opcode[0x10]; 7310 u8 uid[0x10]; 7311 7312 u8 reserved_1[0x10]; 7313 u8 op_mod[0x10]; 7314 7315 u8 reserved_2[0xc0]; 7316 7317 struct mlx5_ifc_tirc_bits tir_context; 7318 }; 7319 7320 struct mlx5_ifc_create_srq_out_bits { 7321 u8 status[0x8]; 7322 u8 reserved_0[0x18]; 7323 7324 u8 syndrome[0x20]; 7325 7326 u8 reserved_1[0x8]; 7327 u8 srqn[0x18]; 7328 7329 u8 reserved_2[0x20]; 7330 }; 7331 7332 struct mlx5_ifc_create_srq_in_bits { 7333 u8 opcode[0x10]; 7334 u8 uid[0x10]; 7335 7336 u8 reserved_1[0x10]; 7337 u8 op_mod[0x10]; 7338 7339 u8 reserved_2[0x40]; 7340 7341 struct mlx5_ifc_srqc_bits srq_context_entry; 7342 7343 u8 reserved_3[0x600]; 7344 7345 u8 pas[0][0x40]; 7346 }; 7347 7348 struct mlx5_ifc_create_sq_out_bits { 7349 u8 status[0x8]; 7350 u8 reserved_0[0x18]; 7351 7352 u8 syndrome[0x20]; 7353 7354 u8 reserved_1[0x8]; 7355 u8 sqn[0x18]; 7356 7357 u8 reserved_2[0x20]; 7358 }; 7359 7360 struct mlx5_ifc_create_sq_in_bits { 7361 u8 opcode[0x10]; 7362 u8 uid[0x10]; 7363 7364 u8 reserved_1[0x10]; 7365 u8 op_mod[0x10]; 7366 7367 u8 reserved_2[0xc0]; 7368 7369 struct mlx5_ifc_sqc_bits ctx; 7370 }; 7371 7372 struct mlx5_ifc_create_scheduling_element_out_bits { 7373 u8 status[0x8]; 7374 u8 reserved_at_8[0x18]; 7375 7376 u8 syndrome[0x20]; 7377 7378 u8 reserved_at_40[0x40]; 7379 7380 u8 scheduling_element_id[0x20]; 7381 7382 u8 reserved_at_a0[0x160]; 7383 }; 7384 7385 enum { 7386 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 7387 }; 7388 7389 struct mlx5_ifc_create_scheduling_element_in_bits { 7390 u8 opcode[0x10]; 7391 u8 reserved_at_10[0x10]; 7392 7393 u8 reserved_at_20[0x10]; 7394 u8 op_mod[0x10]; 7395 7396 u8 scheduling_hierarchy[0x8]; 7397 u8 reserved_at_48[0x18]; 7398 7399 u8 reserved_at_60[0xa0]; 7400 7401 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7402 7403 u8 reserved_at_300[0x100]; 7404 }; 7405 7406 struct mlx5_ifc_create_rqt_out_bits { 7407 u8 status[0x8]; 7408 u8 reserved_0[0x18]; 7409 7410 u8 syndrome[0x20]; 7411 7412 u8 reserved_1[0x8]; 7413 u8 rqtn[0x18]; 7414 7415 u8 reserved_2[0x20]; 7416 }; 7417 7418 struct mlx5_ifc_create_rqt_in_bits { 7419 u8 opcode[0x10]; 7420 u8 uid[0x10]; 7421 7422 u8 reserved_1[0x10]; 7423 u8 op_mod[0x10]; 7424 7425 u8 reserved_2[0xc0]; 7426 7427 struct mlx5_ifc_rqtc_bits rqt_context; 7428 }; 7429 7430 struct mlx5_ifc_create_rq_out_bits { 7431 u8 status[0x8]; 7432 u8 reserved_0[0x18]; 7433 7434 u8 syndrome[0x20]; 7435 7436 u8 reserved_1[0x8]; 7437 u8 rqn[0x18]; 7438 7439 u8 reserved_2[0x20]; 7440 }; 7441 7442 struct mlx5_ifc_create_rq_in_bits { 7443 u8 opcode[0x10]; 7444 u8 uid[0x10]; 7445 7446 u8 reserved_1[0x10]; 7447 u8 op_mod[0x10]; 7448 7449 u8 reserved_2[0xc0]; 7450 7451 struct mlx5_ifc_rqc_bits ctx; 7452 }; 7453 7454 struct mlx5_ifc_create_rmp_out_bits { 7455 u8 status[0x8]; 7456 u8 reserved_0[0x18]; 7457 7458 u8 syndrome[0x20]; 7459 7460 u8 reserved_1[0x8]; 7461 u8 rmpn[0x18]; 7462 7463 u8 reserved_2[0x20]; 7464 }; 7465 7466 struct mlx5_ifc_create_rmp_in_bits { 7467 u8 opcode[0x10]; 7468 u8 uid[0x10]; 7469 7470 u8 reserved_1[0x10]; 7471 u8 op_mod[0x10]; 7472 7473 u8 reserved_2[0xc0]; 7474 7475 struct mlx5_ifc_rmpc_bits ctx; 7476 }; 7477 7478 struct mlx5_ifc_create_qp_out_bits { 7479 u8 status[0x8]; 7480 u8 reserved_0[0x18]; 7481 7482 u8 syndrome[0x20]; 7483 7484 u8 reserved_1[0x8]; 7485 u8 qpn[0x18]; 7486 7487 u8 reserved_2[0x20]; 7488 }; 7489 7490 struct mlx5_ifc_create_qp_in_bits { 7491 u8 opcode[0x10]; 7492 u8 uid[0x10]; 7493 7494 u8 reserved_1[0x10]; 7495 u8 op_mod[0x10]; 7496 7497 u8 reserved_2[0x8]; 7498 u8 input_qpn[0x18]; 7499 7500 u8 reserved_3[0x20]; 7501 7502 u8 opt_param_mask[0x20]; 7503 7504 u8 reserved_4[0x20]; 7505 7506 struct mlx5_ifc_qpc_bits qpc; 7507 7508 u8 reserved_at_800[0x60]; 7509 7510 u8 wq_umem_valid[0x1]; 7511 u8 reserved_at_861[0x1f]; 7512 7513 u8 pas[0][0x40]; 7514 }; 7515 7516 struct mlx5_ifc_create_qos_para_vport_out_bits { 7517 u8 status[0x8]; 7518 u8 reserved_at_8[0x18]; 7519 7520 u8 syndrome[0x20]; 7521 7522 u8 reserved_at_40[0x20]; 7523 7524 u8 reserved_at_60[0x10]; 7525 u8 qos_para_vport_number[0x10]; 7526 7527 u8 reserved_at_80[0x180]; 7528 }; 7529 7530 struct mlx5_ifc_create_qos_para_vport_in_bits { 7531 u8 opcode[0x10]; 7532 u8 reserved_at_10[0x10]; 7533 7534 u8 reserved_at_20[0x10]; 7535 u8 op_mod[0x10]; 7536 7537 u8 reserved_at_40[0x1c0]; 7538 }; 7539 7540 struct mlx5_ifc_create_psv_out_bits { 7541 u8 status[0x8]; 7542 u8 reserved_0[0x18]; 7543 7544 u8 syndrome[0x20]; 7545 7546 u8 reserved_1[0x40]; 7547 7548 u8 reserved_2[0x8]; 7549 u8 psv0_index[0x18]; 7550 7551 u8 reserved_3[0x8]; 7552 u8 psv1_index[0x18]; 7553 7554 u8 reserved_4[0x8]; 7555 u8 psv2_index[0x18]; 7556 7557 u8 reserved_5[0x8]; 7558 u8 psv3_index[0x18]; 7559 }; 7560 7561 struct mlx5_ifc_create_psv_in_bits { 7562 u8 opcode[0x10]; 7563 u8 reserved_0[0x10]; 7564 7565 u8 reserved_1[0x10]; 7566 u8 op_mod[0x10]; 7567 7568 u8 num_psv[0x4]; 7569 u8 reserved_2[0x4]; 7570 u8 pd[0x18]; 7571 7572 u8 reserved_3[0x20]; 7573 }; 7574 7575 struct mlx5_ifc_create_mkey_out_bits { 7576 u8 status[0x8]; 7577 u8 reserved_0[0x18]; 7578 7579 u8 syndrome[0x20]; 7580 7581 u8 reserved_1[0x8]; 7582 u8 mkey_index[0x18]; 7583 7584 u8 reserved_2[0x20]; 7585 }; 7586 7587 struct mlx5_ifc_create_mkey_in_bits { 7588 u8 opcode[0x10]; 7589 u8 reserved_0[0x10]; 7590 7591 u8 reserved_1[0x10]; 7592 u8 op_mod[0x10]; 7593 7594 u8 reserved_2[0x20]; 7595 7596 u8 pg_access[0x1]; 7597 u8 mkey_umem_valid[0x1]; 7598 u8 reserved_at_62[0x1e]; 7599 7600 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7601 7602 u8 reserved_4[0x80]; 7603 7604 u8 translations_octword_actual_size[0x20]; 7605 7606 u8 reserved_5[0x560]; 7607 7608 u8 klm_pas_mtt[0][0x20]; 7609 }; 7610 7611 struct mlx5_ifc_create_flow_table_out_bits { 7612 u8 status[0x8]; 7613 u8 reserved_0[0x18]; 7614 7615 u8 syndrome[0x20]; 7616 7617 u8 reserved_1[0x8]; 7618 u8 table_id[0x18]; 7619 7620 u8 reserved_2[0x20]; 7621 }; 7622 7623 struct mlx5_ifc_create_flow_table_in_bits { 7624 u8 opcode[0x10]; 7625 u8 reserved_at_10[0x10]; 7626 7627 u8 reserved_at_20[0x10]; 7628 u8 op_mod[0x10]; 7629 7630 u8 other_vport[0x1]; 7631 u8 reserved_at_41[0xf]; 7632 u8 vport_number[0x10]; 7633 7634 u8 reserved_at_60[0x20]; 7635 7636 u8 table_type[0x8]; 7637 u8 reserved_at_88[0x18]; 7638 7639 u8 reserved_at_a0[0x20]; 7640 7641 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7642 }; 7643 7644 struct mlx5_ifc_create_flow_group_out_bits { 7645 u8 status[0x8]; 7646 u8 reserved_0[0x18]; 7647 7648 u8 syndrome[0x20]; 7649 7650 u8 reserved_1[0x8]; 7651 u8 group_id[0x18]; 7652 7653 u8 reserved_2[0x20]; 7654 }; 7655 7656 enum { 7657 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7658 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7659 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7660 }; 7661 7662 struct mlx5_ifc_create_flow_group_in_bits { 7663 u8 opcode[0x10]; 7664 u8 reserved_0[0x10]; 7665 7666 u8 reserved_1[0x10]; 7667 u8 op_mod[0x10]; 7668 7669 u8 other_vport[0x1]; 7670 u8 reserved_2[0xf]; 7671 u8 vport_number[0x10]; 7672 7673 u8 reserved_3[0x20]; 7674 7675 u8 table_type[0x8]; 7676 u8 reserved_4[0x18]; 7677 7678 u8 reserved_5[0x8]; 7679 u8 table_id[0x18]; 7680 7681 u8 reserved_6[0x20]; 7682 7683 u8 start_flow_index[0x20]; 7684 7685 u8 reserved_7[0x20]; 7686 7687 u8 end_flow_index[0x20]; 7688 7689 u8 reserved_8[0xa0]; 7690 7691 u8 reserved_9[0x18]; 7692 u8 match_criteria_enable[0x8]; 7693 7694 struct mlx5_ifc_fte_match_param_bits match_criteria; 7695 7696 u8 reserved_10[0xe00]; 7697 }; 7698 7699 struct mlx5_ifc_create_encryption_key_out_bits { 7700 u8 status[0x8]; 7701 u8 reserved_at_8[0x18]; 7702 7703 u8 syndrome[0x20]; 7704 7705 u8 obj_id[0x20]; 7706 7707 u8 reserved_at_60[0x20]; 7708 }; 7709 7710 struct mlx5_ifc_create_encryption_key_in_bits { 7711 u8 opcode[0x10]; 7712 u8 reserved_at_10[0x10]; 7713 7714 u8 reserved_at_20[0x10]; 7715 u8 obj_type[0x10]; 7716 7717 u8 reserved_at_40[0x40]; 7718 7719 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 7720 }; 7721 7722 struct mlx5_ifc_create_eq_out_bits { 7723 u8 status[0x8]; 7724 u8 reserved_0[0x18]; 7725 7726 u8 syndrome[0x20]; 7727 7728 u8 reserved_1[0x18]; 7729 u8 eq_number[0x8]; 7730 7731 u8 reserved_2[0x20]; 7732 }; 7733 7734 struct mlx5_ifc_create_eq_in_bits { 7735 u8 opcode[0x10]; 7736 u8 reserved_0[0x10]; 7737 7738 u8 reserved_1[0x10]; 7739 u8 op_mod[0x10]; 7740 7741 u8 reserved_2[0x40]; 7742 7743 struct mlx5_ifc_eqc_bits eq_context_entry; 7744 7745 u8 reserved_3[0x40]; 7746 7747 u8 event_bitmask[0x40]; 7748 7749 u8 reserved_4[0x580]; 7750 7751 u8 pas[0][0x40]; 7752 }; 7753 7754 struct mlx5_ifc_create_dct_out_bits { 7755 u8 status[0x8]; 7756 u8 reserved_0[0x18]; 7757 7758 u8 syndrome[0x20]; 7759 7760 u8 reserved_1[0x8]; 7761 u8 dctn[0x18]; 7762 7763 u8 reserved_2[0x20]; 7764 }; 7765 7766 struct mlx5_ifc_create_dct_in_bits { 7767 u8 opcode[0x10]; 7768 u8 uid[0x10]; 7769 7770 u8 reserved_1[0x10]; 7771 u8 op_mod[0x10]; 7772 7773 u8 reserved_2[0x40]; 7774 7775 struct mlx5_ifc_dctc_bits dct_context_entry; 7776 7777 u8 reserved_3[0x180]; 7778 }; 7779 7780 struct mlx5_ifc_create_cq_out_bits { 7781 u8 status[0x8]; 7782 u8 reserved_0[0x18]; 7783 7784 u8 syndrome[0x20]; 7785 7786 u8 reserved_1[0x8]; 7787 u8 cqn[0x18]; 7788 7789 u8 reserved_2[0x20]; 7790 }; 7791 7792 struct mlx5_ifc_create_cq_in_bits { 7793 u8 opcode[0x10]; 7794 u8 uid[0x10]; 7795 7796 u8 reserved_1[0x10]; 7797 u8 op_mod[0x10]; 7798 7799 u8 reserved_2[0x40]; 7800 7801 struct mlx5_ifc_cqc_bits cq_context; 7802 7803 u8 reserved_at_280[0x60]; 7804 7805 u8 cq_umem_valid[0x1]; 7806 u8 reserved_at_2e1[0x59f]; 7807 7808 u8 pas[0][0x40]; 7809 }; 7810 7811 struct mlx5_ifc_config_int_moderation_out_bits { 7812 u8 status[0x8]; 7813 u8 reserved_0[0x18]; 7814 7815 u8 syndrome[0x20]; 7816 7817 u8 reserved_1[0x4]; 7818 u8 min_delay[0xc]; 7819 u8 int_vector[0x10]; 7820 7821 u8 reserved_2[0x20]; 7822 }; 7823 7824 enum { 7825 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7826 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7827 }; 7828 7829 struct mlx5_ifc_config_int_moderation_in_bits { 7830 u8 opcode[0x10]; 7831 u8 reserved_0[0x10]; 7832 7833 u8 reserved_1[0x10]; 7834 u8 op_mod[0x10]; 7835 7836 u8 reserved_2[0x4]; 7837 u8 min_delay[0xc]; 7838 u8 int_vector[0x10]; 7839 7840 u8 reserved_3[0x20]; 7841 }; 7842 7843 struct mlx5_ifc_attach_to_mcg_out_bits { 7844 u8 status[0x8]; 7845 u8 reserved_0[0x18]; 7846 7847 u8 syndrome[0x20]; 7848 7849 u8 reserved_1[0x40]; 7850 }; 7851 7852 struct mlx5_ifc_attach_to_mcg_in_bits { 7853 u8 opcode[0x10]; 7854 u8 uid[0x10]; 7855 7856 u8 reserved_1[0x10]; 7857 u8 op_mod[0x10]; 7858 7859 u8 reserved_2[0x8]; 7860 u8 qpn[0x18]; 7861 7862 u8 reserved_3[0x20]; 7863 7864 u8 multicast_gid[16][0x8]; 7865 }; 7866 7867 struct mlx5_ifc_arm_xrq_out_bits { 7868 u8 status[0x8]; 7869 u8 reserved_at_8[0x18]; 7870 7871 u8 syndrome[0x20]; 7872 7873 u8 reserved_at_40[0x40]; 7874 }; 7875 7876 struct mlx5_ifc_arm_xrq_in_bits { 7877 u8 opcode[0x10]; 7878 u8 reserved_at_10[0x10]; 7879 7880 u8 reserved_at_20[0x10]; 7881 u8 op_mod[0x10]; 7882 7883 u8 reserved_at_40[0x8]; 7884 u8 xrqn[0x18]; 7885 7886 u8 reserved_at_60[0x10]; 7887 u8 lwm[0x10]; 7888 }; 7889 7890 struct mlx5_ifc_arm_xrc_srq_out_bits { 7891 u8 status[0x8]; 7892 u8 reserved_0[0x18]; 7893 7894 u8 syndrome[0x20]; 7895 7896 u8 reserved_1[0x40]; 7897 }; 7898 7899 enum { 7900 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7901 }; 7902 7903 struct mlx5_ifc_arm_xrc_srq_in_bits { 7904 u8 opcode[0x10]; 7905 u8 uid[0x10]; 7906 7907 u8 reserved_1[0x10]; 7908 u8 op_mod[0x10]; 7909 7910 u8 reserved_2[0x8]; 7911 u8 xrc_srqn[0x18]; 7912 7913 u8 reserved_3[0x10]; 7914 u8 lwm[0x10]; 7915 }; 7916 7917 struct mlx5_ifc_arm_rq_out_bits { 7918 u8 status[0x8]; 7919 u8 reserved_0[0x18]; 7920 7921 u8 syndrome[0x20]; 7922 7923 u8 reserved_1[0x40]; 7924 }; 7925 7926 enum { 7927 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7928 }; 7929 7930 struct mlx5_ifc_arm_rq_in_bits { 7931 u8 opcode[0x10]; 7932 u8 uid[0x10]; 7933 7934 u8 reserved_1[0x10]; 7935 u8 op_mod[0x10]; 7936 7937 u8 reserved_2[0x8]; 7938 u8 srq_number[0x18]; 7939 7940 u8 reserved_3[0x10]; 7941 u8 lwm[0x10]; 7942 }; 7943 7944 struct mlx5_ifc_arm_dct_out_bits { 7945 u8 status[0x8]; 7946 u8 reserved_0[0x18]; 7947 7948 u8 syndrome[0x20]; 7949 7950 u8 reserved_1[0x40]; 7951 }; 7952 7953 struct mlx5_ifc_arm_dct_in_bits { 7954 u8 opcode[0x10]; 7955 u8 reserved_0[0x10]; 7956 7957 u8 reserved_1[0x10]; 7958 u8 op_mod[0x10]; 7959 7960 u8 reserved_2[0x8]; 7961 u8 dctn[0x18]; 7962 7963 u8 reserved_3[0x20]; 7964 }; 7965 7966 struct mlx5_ifc_alloc_xrcd_out_bits { 7967 u8 status[0x8]; 7968 u8 reserved_0[0x18]; 7969 7970 u8 syndrome[0x20]; 7971 7972 u8 reserved_1[0x8]; 7973 u8 xrcd[0x18]; 7974 7975 u8 reserved_2[0x20]; 7976 }; 7977 7978 struct mlx5_ifc_alloc_xrcd_in_bits { 7979 u8 opcode[0x10]; 7980 u8 uid[0x10]; 7981 7982 u8 reserved_1[0x10]; 7983 u8 op_mod[0x10]; 7984 7985 u8 reserved_2[0x40]; 7986 }; 7987 7988 struct mlx5_ifc_alloc_uar_out_bits { 7989 u8 status[0x8]; 7990 u8 reserved_0[0x18]; 7991 7992 u8 syndrome[0x20]; 7993 7994 u8 reserved_1[0x8]; 7995 u8 uar[0x18]; 7996 7997 u8 reserved_2[0x20]; 7998 }; 7999 8000 struct mlx5_ifc_alloc_uar_in_bits { 8001 u8 opcode[0x10]; 8002 u8 reserved_0[0x10]; 8003 8004 u8 reserved_1[0x10]; 8005 u8 op_mod[0x10]; 8006 8007 u8 reserved_2[0x40]; 8008 }; 8009 8010 struct mlx5_ifc_alloc_transport_domain_out_bits { 8011 u8 status[0x8]; 8012 u8 reserved_0[0x18]; 8013 8014 u8 syndrome[0x20]; 8015 8016 u8 reserved_1[0x8]; 8017 u8 transport_domain[0x18]; 8018 8019 u8 reserved_2[0x20]; 8020 }; 8021 8022 struct mlx5_ifc_alloc_transport_domain_in_bits { 8023 u8 opcode[0x10]; 8024 u8 uid[0x10]; 8025 8026 u8 reserved_1[0x10]; 8027 u8 op_mod[0x10]; 8028 8029 u8 reserved_2[0x40]; 8030 }; 8031 8032 struct mlx5_ifc_alloc_q_counter_out_bits { 8033 u8 status[0x8]; 8034 u8 reserved_0[0x18]; 8035 8036 u8 syndrome[0x20]; 8037 8038 u8 reserved_1[0x18]; 8039 u8 counter_set_id[0x8]; 8040 8041 u8 reserved_2[0x20]; 8042 }; 8043 8044 struct mlx5_ifc_alloc_q_counter_in_bits { 8045 u8 opcode[0x10]; 8046 u8 uid[0x10]; 8047 8048 u8 reserved_1[0x10]; 8049 u8 op_mod[0x10]; 8050 8051 u8 reserved_2[0x40]; 8052 }; 8053 8054 struct mlx5_ifc_alloc_pd_out_bits { 8055 u8 status[0x8]; 8056 u8 reserved_0[0x18]; 8057 8058 u8 syndrome[0x20]; 8059 8060 u8 reserved_1[0x8]; 8061 u8 pd[0x18]; 8062 8063 u8 reserved_2[0x20]; 8064 }; 8065 8066 struct mlx5_ifc_alloc_pd_in_bits { 8067 u8 opcode[0x10]; 8068 u8 uid[0x10]; 8069 8070 u8 reserved_1[0x10]; 8071 u8 op_mod[0x10]; 8072 8073 u8 reserved_2[0x40]; 8074 }; 8075 8076 struct mlx5_ifc_alloc_flow_counter_out_bits { 8077 u8 status[0x8]; 8078 u8 reserved_at_8[0x18]; 8079 8080 u8 syndrome[0x20]; 8081 8082 u8 flow_counter_id[0x20]; 8083 8084 u8 reserved_at_60[0x20]; 8085 }; 8086 8087 struct mlx5_ifc_alloc_flow_counter_in_bits { 8088 u8 opcode[0x10]; 8089 u8 reserved_at_10[0x10]; 8090 8091 u8 reserved_at_20[0x10]; 8092 u8 op_mod[0x10]; 8093 8094 u8 reserved_at_40[0x38]; 8095 u8 flow_counter_bulk[0x8]; 8096 }; 8097 8098 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8099 u8 status[0x8]; 8100 u8 reserved_0[0x18]; 8101 8102 u8 syndrome[0x20]; 8103 8104 u8 reserved_1[0x40]; 8105 }; 8106 8107 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8108 u8 opcode[0x10]; 8109 u8 reserved_0[0x10]; 8110 8111 u8 reserved_1[0x10]; 8112 u8 op_mod[0x10]; 8113 8114 u8 reserved_2[0x20]; 8115 8116 u8 reserved_3[0x10]; 8117 u8 vxlan_udp_port[0x10]; 8118 }; 8119 8120 struct mlx5_ifc_activate_tracer_out_bits { 8121 u8 status[0x8]; 8122 u8 reserved_0[0x18]; 8123 8124 u8 syndrome[0x20]; 8125 8126 u8 reserved_1[0x40]; 8127 }; 8128 8129 struct mlx5_ifc_activate_tracer_in_bits { 8130 u8 opcode[0x10]; 8131 u8 reserved_0[0x10]; 8132 8133 u8 reserved_1[0x10]; 8134 u8 op_mod[0x10]; 8135 8136 u8 mkey[0x20]; 8137 8138 u8 reserved_2[0x20]; 8139 }; 8140 8141 struct mlx5_ifc_set_rate_limit_out_bits { 8142 u8 status[0x8]; 8143 u8 reserved_at_8[0x18]; 8144 8145 u8 syndrome[0x20]; 8146 8147 u8 reserved_at_40[0x40]; 8148 }; 8149 8150 struct mlx5_ifc_set_rate_limit_in_bits { 8151 u8 opcode[0x10]; 8152 u8 uid[0x10]; 8153 8154 u8 reserved_at_20[0x10]; 8155 u8 op_mod[0x10]; 8156 8157 u8 reserved_at_40[0x10]; 8158 u8 rate_limit_index[0x10]; 8159 8160 u8 reserved_at_60[0x20]; 8161 8162 u8 rate_limit[0x20]; 8163 8164 u8 burst_upper_bound[0x20]; 8165 8166 u8 reserved_at_c0[0x10]; 8167 u8 typical_packet_size[0x10]; 8168 8169 u8 reserved_at_e0[0x120]; 8170 }; 8171 8172 struct mlx5_ifc_access_register_out_bits { 8173 u8 status[0x8]; 8174 u8 reserved_0[0x18]; 8175 8176 u8 syndrome[0x20]; 8177 8178 u8 reserved_1[0x40]; 8179 8180 u8 register_data[0][0x20]; 8181 }; 8182 8183 enum { 8184 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8185 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8186 }; 8187 8188 struct mlx5_ifc_access_register_in_bits { 8189 u8 opcode[0x10]; 8190 u8 reserved_0[0x10]; 8191 8192 u8 reserved_1[0x10]; 8193 u8 op_mod[0x10]; 8194 8195 u8 reserved_2[0x10]; 8196 u8 register_id[0x10]; 8197 8198 u8 argument[0x20]; 8199 8200 u8 register_data[0][0x20]; 8201 }; 8202 8203 struct mlx5_ifc_sltp_reg_bits { 8204 u8 status[0x4]; 8205 u8 version[0x4]; 8206 u8 local_port[0x8]; 8207 u8 pnat[0x2]; 8208 u8 reserved_0[0x2]; 8209 u8 lane[0x4]; 8210 u8 reserved_1[0x8]; 8211 8212 u8 reserved_2[0x20]; 8213 8214 u8 reserved_3[0x7]; 8215 u8 polarity[0x1]; 8216 u8 ob_tap0[0x8]; 8217 u8 ob_tap1[0x8]; 8218 u8 ob_tap2[0x8]; 8219 8220 u8 reserved_4[0xc]; 8221 u8 ob_preemp_mode[0x4]; 8222 u8 ob_reg[0x8]; 8223 u8 ob_bias[0x8]; 8224 8225 u8 reserved_5[0x20]; 8226 }; 8227 8228 struct mlx5_ifc_slrp_reg_bits { 8229 u8 status[0x4]; 8230 u8 version[0x4]; 8231 u8 local_port[0x8]; 8232 u8 pnat[0x2]; 8233 u8 reserved_0[0x2]; 8234 u8 lane[0x4]; 8235 u8 reserved_1[0x8]; 8236 8237 u8 ib_sel[0x2]; 8238 u8 reserved_2[0x11]; 8239 u8 dp_sel[0x1]; 8240 u8 dp90sel[0x4]; 8241 u8 mix90phase[0x8]; 8242 8243 u8 ffe_tap0[0x8]; 8244 u8 ffe_tap1[0x8]; 8245 u8 ffe_tap2[0x8]; 8246 u8 ffe_tap3[0x8]; 8247 8248 u8 ffe_tap4[0x8]; 8249 u8 ffe_tap5[0x8]; 8250 u8 ffe_tap6[0x8]; 8251 u8 ffe_tap7[0x8]; 8252 8253 u8 ffe_tap8[0x8]; 8254 u8 mixerbias_tap_amp[0x8]; 8255 u8 reserved_3[0x7]; 8256 u8 ffe_tap_en[0x9]; 8257 8258 u8 ffe_tap_offset0[0x8]; 8259 u8 ffe_tap_offset1[0x8]; 8260 u8 slicer_offset0[0x10]; 8261 8262 u8 mixer_offset0[0x10]; 8263 u8 mixer_offset1[0x10]; 8264 8265 u8 mixerbgn_inp[0x8]; 8266 u8 mixerbgn_inn[0x8]; 8267 u8 mixerbgn_refp[0x8]; 8268 u8 mixerbgn_refn[0x8]; 8269 8270 u8 sel_slicer_lctrl_h[0x1]; 8271 u8 sel_slicer_lctrl_l[0x1]; 8272 u8 reserved_4[0x1]; 8273 u8 ref_mixer_vreg[0x5]; 8274 u8 slicer_gctrl[0x8]; 8275 u8 lctrl_input[0x8]; 8276 u8 mixer_offset_cm1[0x8]; 8277 8278 u8 common_mode[0x6]; 8279 u8 reserved_5[0x1]; 8280 u8 mixer_offset_cm0[0x9]; 8281 u8 reserved_6[0x7]; 8282 u8 slicer_offset_cm[0x9]; 8283 }; 8284 8285 struct mlx5_ifc_slrg_reg_bits { 8286 u8 status[0x4]; 8287 u8 version[0x4]; 8288 u8 local_port[0x8]; 8289 u8 pnat[0x2]; 8290 u8 reserved_0[0x2]; 8291 u8 lane[0x4]; 8292 u8 reserved_1[0x8]; 8293 8294 u8 time_to_link_up[0x10]; 8295 u8 reserved_2[0xc]; 8296 u8 grade_lane_speed[0x4]; 8297 8298 u8 grade_version[0x8]; 8299 u8 grade[0x18]; 8300 8301 u8 reserved_3[0x4]; 8302 u8 height_grade_type[0x4]; 8303 u8 height_grade[0x18]; 8304 8305 u8 height_dz[0x10]; 8306 u8 height_dv[0x10]; 8307 8308 u8 reserved_4[0x10]; 8309 u8 height_sigma[0x10]; 8310 8311 u8 reserved_5[0x20]; 8312 8313 u8 reserved_6[0x4]; 8314 u8 phase_grade_type[0x4]; 8315 u8 phase_grade[0x18]; 8316 8317 u8 reserved_7[0x8]; 8318 u8 phase_eo_pos[0x8]; 8319 u8 reserved_8[0x8]; 8320 u8 phase_eo_neg[0x8]; 8321 8322 u8 ffe_set_tested[0x10]; 8323 u8 test_errors_per_lane[0x10]; 8324 }; 8325 8326 struct mlx5_ifc_pvlc_reg_bits { 8327 u8 reserved_0[0x8]; 8328 u8 local_port[0x8]; 8329 u8 reserved_1[0x10]; 8330 8331 u8 reserved_2[0x1c]; 8332 u8 vl_hw_cap[0x4]; 8333 8334 u8 reserved_3[0x1c]; 8335 u8 vl_admin[0x4]; 8336 8337 u8 reserved_4[0x1c]; 8338 u8 vl_operational[0x4]; 8339 }; 8340 8341 struct mlx5_ifc_pude_reg_bits { 8342 u8 swid[0x8]; 8343 u8 local_port[0x8]; 8344 u8 reserved_0[0x4]; 8345 u8 admin_status[0x4]; 8346 u8 reserved_1[0x4]; 8347 u8 oper_status[0x4]; 8348 8349 u8 reserved_2[0x60]; 8350 }; 8351 8352 enum { 8353 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 8354 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 8355 }; 8356 8357 struct mlx5_ifc_ptys_reg_bits { 8358 u8 reserved_0[0x1]; 8359 u8 an_disable_admin[0x1]; 8360 u8 an_disable_cap[0x1]; 8361 u8 reserved_1[0x4]; 8362 u8 force_tx_aba_param[0x1]; 8363 u8 local_port[0x8]; 8364 u8 reserved_2[0xd]; 8365 u8 proto_mask[0x3]; 8366 8367 u8 an_status[0x4]; 8368 u8 reserved_3[0xc]; 8369 u8 data_rate_oper[0x10]; 8370 8371 u8 ext_eth_proto_capability[0x20]; 8372 8373 u8 eth_proto_capability[0x20]; 8374 8375 u8 ib_link_width_capability[0x10]; 8376 u8 ib_proto_capability[0x10]; 8377 8378 u8 ext_eth_proto_admin[0x20]; 8379 8380 u8 eth_proto_admin[0x20]; 8381 8382 u8 ib_link_width_admin[0x10]; 8383 u8 ib_proto_admin[0x10]; 8384 8385 u8 ext_eth_proto_oper[0x20]; 8386 8387 u8 eth_proto_oper[0x20]; 8388 8389 u8 ib_link_width_oper[0x10]; 8390 u8 ib_proto_oper[0x10]; 8391 8392 u8 reserved_4[0x1c]; 8393 u8 connector_type[0x4]; 8394 8395 u8 eth_proto_lp_advertise[0x20]; 8396 8397 u8 reserved_5[0x60]; 8398 }; 8399 8400 struct mlx5_ifc_ptas_reg_bits { 8401 u8 reserved_0[0x20]; 8402 8403 u8 algorithm_options[0x10]; 8404 u8 reserved_1[0x4]; 8405 u8 repetitions_mode[0x4]; 8406 u8 num_of_repetitions[0x8]; 8407 8408 u8 grade_version[0x8]; 8409 u8 height_grade_type[0x4]; 8410 u8 phase_grade_type[0x4]; 8411 u8 height_grade_weight[0x8]; 8412 u8 phase_grade_weight[0x8]; 8413 8414 u8 gisim_measure_bits[0x10]; 8415 u8 adaptive_tap_measure_bits[0x10]; 8416 8417 u8 ber_bath_high_error_threshold[0x10]; 8418 u8 ber_bath_mid_error_threshold[0x10]; 8419 8420 u8 ber_bath_low_error_threshold[0x10]; 8421 u8 one_ratio_high_threshold[0x10]; 8422 8423 u8 one_ratio_high_mid_threshold[0x10]; 8424 u8 one_ratio_low_mid_threshold[0x10]; 8425 8426 u8 one_ratio_low_threshold[0x10]; 8427 u8 ndeo_error_threshold[0x10]; 8428 8429 u8 mixer_offset_step_size[0x10]; 8430 u8 reserved_2[0x8]; 8431 u8 mix90_phase_for_voltage_bath[0x8]; 8432 8433 u8 mixer_offset_start[0x10]; 8434 u8 mixer_offset_end[0x10]; 8435 8436 u8 reserved_3[0x15]; 8437 u8 ber_test_time[0xb]; 8438 }; 8439 8440 struct mlx5_ifc_pspa_reg_bits { 8441 u8 swid[0x8]; 8442 u8 local_port[0x8]; 8443 u8 sub_port[0x8]; 8444 u8 reserved_0[0x8]; 8445 8446 u8 reserved_1[0x20]; 8447 }; 8448 8449 struct mlx5_ifc_ppsc_reg_bits { 8450 u8 reserved_0[0x8]; 8451 u8 local_port[0x8]; 8452 u8 reserved_1[0x10]; 8453 8454 u8 reserved_2[0x60]; 8455 8456 u8 reserved_3[0x1c]; 8457 u8 wrps_admin[0x4]; 8458 8459 u8 reserved_4[0x1c]; 8460 u8 wrps_status[0x4]; 8461 8462 u8 up_th_vld[0x1]; 8463 u8 down_th_vld[0x1]; 8464 u8 reserved_5[0x6]; 8465 u8 up_threshold[0x8]; 8466 u8 reserved_6[0x8]; 8467 u8 down_threshold[0x8]; 8468 8469 u8 reserved_7[0x20]; 8470 8471 u8 reserved_8[0x1c]; 8472 u8 srps_admin[0x4]; 8473 8474 u8 reserved_9[0x60]; 8475 }; 8476 8477 struct mlx5_ifc_pplr_reg_bits { 8478 u8 reserved_0[0x8]; 8479 u8 local_port[0x8]; 8480 u8 reserved_1[0x10]; 8481 8482 u8 reserved_2[0x8]; 8483 u8 lb_cap[0x8]; 8484 u8 reserved_3[0x8]; 8485 u8 lb_en[0x8]; 8486 }; 8487 8488 struct mlx5_ifc_pplm_reg_bits { 8489 u8 reserved_at_0[0x8]; 8490 u8 local_port[0x8]; 8491 u8 reserved_at_10[0x10]; 8492 8493 u8 reserved_at_20[0x20]; 8494 8495 u8 port_profile_mode[0x8]; 8496 u8 static_port_profile[0x8]; 8497 u8 active_port_profile[0x8]; 8498 u8 reserved_at_58[0x8]; 8499 8500 u8 retransmission_active[0x8]; 8501 u8 fec_mode_active[0x18]; 8502 8503 u8 rs_fec_correction_bypass_cap[0x4]; 8504 u8 reserved_at_84[0x8]; 8505 u8 fec_override_cap_56g[0x4]; 8506 u8 fec_override_cap_100g[0x4]; 8507 u8 fec_override_cap_50g[0x4]; 8508 u8 fec_override_cap_25g[0x4]; 8509 u8 fec_override_cap_10g_40g[0x4]; 8510 8511 u8 rs_fec_correction_bypass_admin[0x4]; 8512 u8 reserved_at_a4[0x8]; 8513 u8 fec_override_admin_56g[0x4]; 8514 u8 fec_override_admin_100g[0x4]; 8515 u8 fec_override_admin_50g[0x4]; 8516 u8 fec_override_admin_25g[0x4]; 8517 u8 fec_override_admin_10g_40g[0x4]; 8518 8519 u8 fec_override_cap_400g_8x[0x10]; 8520 u8 fec_override_cap_200g_4x[0x10]; 8521 u8 fec_override_cap_100g_2x[0x10]; 8522 u8 fec_override_cap_50g_1x[0x10]; 8523 8524 u8 fec_override_admin_400g_8x[0x10]; 8525 u8 fec_override_admin_200g_4x[0x10]; 8526 u8 fec_override_admin_100g_2x[0x10]; 8527 u8 fec_override_admin_50g_1x[0x10]; 8528 8529 u8 reserved_at_140[0x140]; 8530 }; 8531 8532 struct mlx5_ifc_ppll_reg_bits { 8533 u8 num_pll_groups[0x8]; 8534 u8 pll_group[0x8]; 8535 u8 reserved_0[0x4]; 8536 u8 num_plls[0x4]; 8537 u8 reserved_1[0x8]; 8538 8539 u8 reserved_2[0x1f]; 8540 u8 ae[0x1]; 8541 8542 u8 pll_status[4][0x40]; 8543 }; 8544 8545 struct mlx5_ifc_ppad_reg_bits { 8546 u8 reserved_0[0x3]; 8547 u8 single_mac[0x1]; 8548 u8 reserved_1[0x4]; 8549 u8 local_port[0x8]; 8550 u8 mac_47_32[0x10]; 8551 8552 u8 mac_31_0[0x20]; 8553 8554 u8 reserved_2[0x40]; 8555 }; 8556 8557 struct mlx5_ifc_pmtu_reg_bits { 8558 u8 reserved_0[0x8]; 8559 u8 local_port[0x8]; 8560 u8 reserved_1[0x10]; 8561 8562 u8 max_mtu[0x10]; 8563 u8 reserved_2[0x10]; 8564 8565 u8 admin_mtu[0x10]; 8566 u8 reserved_3[0x10]; 8567 8568 u8 oper_mtu[0x10]; 8569 u8 reserved_4[0x10]; 8570 }; 8571 8572 struct mlx5_ifc_pmpr_reg_bits { 8573 u8 reserved_0[0x8]; 8574 u8 module[0x8]; 8575 u8 reserved_1[0x10]; 8576 8577 u8 reserved_2[0x18]; 8578 u8 attenuation_5g[0x8]; 8579 8580 u8 reserved_3[0x18]; 8581 u8 attenuation_7g[0x8]; 8582 8583 u8 reserved_4[0x18]; 8584 u8 attenuation_12g[0x8]; 8585 }; 8586 8587 struct mlx5_ifc_pmpe_reg_bits { 8588 u8 reserved_0[0x8]; 8589 u8 module[0x8]; 8590 u8 reserved_1[0xc]; 8591 u8 module_status[0x4]; 8592 8593 u8 reserved_2[0x14]; 8594 u8 error_type[0x4]; 8595 u8 reserved_3[0x8]; 8596 8597 u8 reserved_4[0x40]; 8598 }; 8599 8600 struct mlx5_ifc_pmpc_reg_bits { 8601 u8 module_state_updated[32][0x8]; 8602 }; 8603 8604 struct mlx5_ifc_pmlpn_reg_bits { 8605 u8 reserved_0[0x4]; 8606 u8 mlpn_status[0x4]; 8607 u8 local_port[0x8]; 8608 u8 reserved_1[0x10]; 8609 8610 u8 e[0x1]; 8611 u8 reserved_2[0x1f]; 8612 }; 8613 8614 struct mlx5_ifc_pmlp_reg_bits { 8615 u8 rxtx[0x1]; 8616 u8 reserved_0[0x7]; 8617 u8 local_port[0x8]; 8618 u8 reserved_1[0x8]; 8619 u8 width[0x8]; 8620 8621 u8 lane0_module_mapping[0x20]; 8622 8623 u8 lane1_module_mapping[0x20]; 8624 8625 u8 lane2_module_mapping[0x20]; 8626 8627 u8 lane3_module_mapping[0x20]; 8628 8629 u8 reserved_2[0x160]; 8630 }; 8631 8632 struct mlx5_ifc_pmaos_reg_bits { 8633 u8 reserved_0[0x8]; 8634 u8 module[0x8]; 8635 u8 reserved_1[0x4]; 8636 u8 admin_status[0x4]; 8637 u8 reserved_2[0x4]; 8638 u8 oper_status[0x4]; 8639 8640 u8 ase[0x1]; 8641 u8 ee[0x1]; 8642 u8 reserved_3[0x12]; 8643 u8 error_type[0x4]; 8644 u8 reserved_4[0x6]; 8645 u8 e[0x2]; 8646 8647 u8 reserved_5[0x40]; 8648 }; 8649 8650 struct mlx5_ifc_plpc_reg_bits { 8651 u8 reserved_0[0x4]; 8652 u8 profile_id[0xc]; 8653 u8 reserved_1[0x4]; 8654 u8 proto_mask[0x4]; 8655 u8 reserved_2[0x8]; 8656 8657 u8 reserved_3[0x10]; 8658 u8 lane_speed[0x10]; 8659 8660 u8 reserved_4[0x17]; 8661 u8 lpbf[0x1]; 8662 u8 fec_mode_policy[0x8]; 8663 8664 u8 retransmission_capability[0x8]; 8665 u8 fec_mode_capability[0x18]; 8666 8667 u8 retransmission_support_admin[0x8]; 8668 u8 fec_mode_support_admin[0x18]; 8669 8670 u8 retransmission_request_admin[0x8]; 8671 u8 fec_mode_request_admin[0x18]; 8672 8673 u8 reserved_5[0x80]; 8674 }; 8675 8676 struct mlx5_ifc_pll_status_data_bits { 8677 u8 reserved_0[0x1]; 8678 u8 lock_cal[0x1]; 8679 u8 lock_status[0x2]; 8680 u8 reserved_1[0x2]; 8681 u8 algo_f_ctrl[0xa]; 8682 u8 analog_algo_num_var[0x6]; 8683 u8 f_ctrl_measure[0xa]; 8684 8685 u8 reserved_2[0x2]; 8686 u8 analog_var[0x6]; 8687 u8 reserved_3[0x2]; 8688 u8 high_var[0x6]; 8689 u8 reserved_4[0x2]; 8690 u8 low_var[0x6]; 8691 u8 reserved_5[0x2]; 8692 u8 mid_val[0x6]; 8693 }; 8694 8695 struct mlx5_ifc_plib_reg_bits { 8696 u8 reserved_0[0x8]; 8697 u8 local_port[0x8]; 8698 u8 reserved_1[0x8]; 8699 u8 ib_port[0x8]; 8700 8701 u8 reserved_2[0x60]; 8702 }; 8703 8704 struct mlx5_ifc_plbf_reg_bits { 8705 u8 reserved_0[0x8]; 8706 u8 local_port[0x8]; 8707 u8 reserved_1[0xd]; 8708 u8 lbf_mode[0x3]; 8709 8710 u8 reserved_2[0x20]; 8711 }; 8712 8713 struct mlx5_ifc_pipg_reg_bits { 8714 u8 reserved_0[0x8]; 8715 u8 local_port[0x8]; 8716 u8 reserved_1[0x10]; 8717 8718 u8 dic[0x1]; 8719 u8 reserved_2[0x19]; 8720 u8 ipg[0x4]; 8721 u8 reserved_3[0x2]; 8722 }; 8723 8724 struct mlx5_ifc_pifr_reg_bits { 8725 u8 reserved_0[0x8]; 8726 u8 local_port[0x8]; 8727 u8 reserved_1[0x10]; 8728 8729 u8 reserved_2[0xe0]; 8730 8731 u8 port_filter[8][0x20]; 8732 8733 u8 port_filter_update_en[8][0x20]; 8734 }; 8735 8736 struct mlx5_ifc_phys_layer_cntrs_bits { 8737 u8 time_since_last_clear_high[0x20]; 8738 8739 u8 time_since_last_clear_low[0x20]; 8740 8741 u8 symbol_errors_high[0x20]; 8742 8743 u8 symbol_errors_low[0x20]; 8744 8745 u8 sync_headers_errors_high[0x20]; 8746 8747 u8 sync_headers_errors_low[0x20]; 8748 8749 u8 edpl_bip_errors_lane0_high[0x20]; 8750 8751 u8 edpl_bip_errors_lane0_low[0x20]; 8752 8753 u8 edpl_bip_errors_lane1_high[0x20]; 8754 8755 u8 edpl_bip_errors_lane1_low[0x20]; 8756 8757 u8 edpl_bip_errors_lane2_high[0x20]; 8758 8759 u8 edpl_bip_errors_lane2_low[0x20]; 8760 8761 u8 edpl_bip_errors_lane3_high[0x20]; 8762 8763 u8 edpl_bip_errors_lane3_low[0x20]; 8764 8765 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8766 8767 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8768 8769 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8770 8771 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8772 8773 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8774 8775 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8776 8777 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8778 8779 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8780 8781 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8782 8783 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8784 8785 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8786 8787 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8788 8789 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8790 8791 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8792 8793 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8794 8795 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8796 8797 u8 rs_fec_corrected_blocks_high[0x20]; 8798 8799 u8 rs_fec_corrected_blocks_low[0x20]; 8800 8801 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8802 8803 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8804 8805 u8 rs_fec_no_errors_blocks_high[0x20]; 8806 8807 u8 rs_fec_no_errors_blocks_low[0x20]; 8808 8809 u8 rs_fec_single_error_blocks_high[0x20]; 8810 8811 u8 rs_fec_single_error_blocks_low[0x20]; 8812 8813 u8 rs_fec_corrected_symbols_total_high[0x20]; 8814 8815 u8 rs_fec_corrected_symbols_total_low[0x20]; 8816 8817 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8818 8819 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8820 8821 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8822 8823 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8824 8825 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8826 8827 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8828 8829 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8830 8831 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8832 8833 u8 link_down_events[0x20]; 8834 8835 u8 successful_recovery_events[0x20]; 8836 8837 u8 reserved_0[0x180]; 8838 }; 8839 8840 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8841 u8 symbol_error_counter[0x10]; 8842 8843 u8 link_error_recovery_counter[0x8]; 8844 8845 u8 link_downed_counter[0x8]; 8846 8847 u8 port_rcv_errors[0x10]; 8848 8849 u8 port_rcv_remote_physical_errors[0x10]; 8850 8851 u8 port_rcv_switch_relay_errors[0x10]; 8852 8853 u8 port_xmit_discards[0x10]; 8854 8855 u8 port_xmit_constraint_errors[0x8]; 8856 8857 u8 port_rcv_constraint_errors[0x8]; 8858 8859 u8 reserved_at_70[0x8]; 8860 8861 u8 link_overrun_errors[0x8]; 8862 8863 u8 reserved_at_80[0x10]; 8864 8865 u8 vl_15_dropped[0x10]; 8866 8867 u8 reserved_at_a0[0xa0]; 8868 }; 8869 8870 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8871 u8 time_since_last_clear_high[0x20]; 8872 8873 u8 time_since_last_clear_low[0x20]; 8874 8875 u8 phy_received_bits_high[0x20]; 8876 8877 u8 phy_received_bits_low[0x20]; 8878 8879 u8 phy_symbol_errors_high[0x20]; 8880 8881 u8 phy_symbol_errors_low[0x20]; 8882 8883 u8 phy_corrected_bits_high[0x20]; 8884 8885 u8 phy_corrected_bits_low[0x20]; 8886 8887 u8 phy_corrected_bits_lane0_high[0x20]; 8888 8889 u8 phy_corrected_bits_lane0_low[0x20]; 8890 8891 u8 phy_corrected_bits_lane1_high[0x20]; 8892 8893 u8 phy_corrected_bits_lane1_low[0x20]; 8894 8895 u8 phy_corrected_bits_lane2_high[0x20]; 8896 8897 u8 phy_corrected_bits_lane2_low[0x20]; 8898 8899 u8 phy_corrected_bits_lane3_high[0x20]; 8900 8901 u8 phy_corrected_bits_lane3_low[0x20]; 8902 8903 u8 reserved_at_200[0x5c0]; 8904 }; 8905 8906 struct mlx5_ifc_infiniband_port_cntrs_bits { 8907 u8 symbol_error_counter[0x10]; 8908 u8 link_error_recovery_counter[0x8]; 8909 u8 link_downed_counter[0x8]; 8910 8911 u8 port_rcv_errors[0x10]; 8912 u8 port_rcv_remote_physical_errors[0x10]; 8913 8914 u8 port_rcv_switch_relay_errors[0x10]; 8915 u8 port_xmit_discards[0x10]; 8916 8917 u8 port_xmit_constraint_errors[0x8]; 8918 u8 port_rcv_constraint_errors[0x8]; 8919 u8 reserved_0[0x8]; 8920 u8 local_link_integrity_errors[0x4]; 8921 u8 excessive_buffer_overrun_errors[0x4]; 8922 8923 u8 reserved_1[0x10]; 8924 u8 vl_15_dropped[0x10]; 8925 8926 u8 port_xmit_data[0x20]; 8927 8928 u8 port_rcv_data[0x20]; 8929 8930 u8 port_xmit_pkts[0x20]; 8931 8932 u8 port_rcv_pkts[0x20]; 8933 8934 u8 port_xmit_wait[0x20]; 8935 8936 u8 reserved_2[0x680]; 8937 }; 8938 8939 struct mlx5_ifc_phrr_reg_bits { 8940 u8 clr[0x1]; 8941 u8 reserved_0[0x7]; 8942 u8 local_port[0x8]; 8943 u8 reserved_1[0x10]; 8944 8945 u8 hist_group[0x8]; 8946 u8 reserved_2[0x10]; 8947 u8 hist_id[0x8]; 8948 8949 u8 reserved_3[0x40]; 8950 8951 u8 time_since_last_clear_high[0x20]; 8952 8953 u8 time_since_last_clear_low[0x20]; 8954 8955 u8 bin[10][0x20]; 8956 }; 8957 8958 struct mlx5_ifc_phbr_for_prio_reg_bits { 8959 u8 reserved_0[0x18]; 8960 u8 prio[0x8]; 8961 }; 8962 8963 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8964 u8 reserved_0[0x18]; 8965 u8 tclass[0x8]; 8966 }; 8967 8968 struct mlx5_ifc_phbr_binding_reg_bits { 8969 u8 opcode[0x4]; 8970 u8 reserved_0[0x4]; 8971 u8 local_port[0x8]; 8972 u8 pnat[0x2]; 8973 u8 reserved_1[0xe]; 8974 8975 u8 hist_group[0x8]; 8976 u8 reserved_2[0x10]; 8977 u8 hist_id[0x8]; 8978 8979 u8 reserved_3[0x10]; 8980 u8 hist_type[0x10]; 8981 8982 u8 hist_parameters[0x20]; 8983 8984 u8 hist_min_value[0x20]; 8985 8986 u8 hist_max_value[0x20]; 8987 8988 u8 sample_time[0x20]; 8989 }; 8990 8991 enum { 8992 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8993 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8994 }; 8995 8996 struct mlx5_ifc_pfcc_reg_bits { 8997 u8 dcbx_operation_type[0x2]; 8998 u8 cap_local_admin[0x1]; 8999 u8 cap_remote_admin[0x1]; 9000 u8 reserved_0[0x4]; 9001 u8 local_port[0x8]; 9002 u8 pnat[0x2]; 9003 u8 reserved_1[0xc]; 9004 u8 shl_cap[0x1]; 9005 u8 shl_opr[0x1]; 9006 9007 u8 ppan[0x4]; 9008 u8 reserved_2[0x4]; 9009 u8 prio_mask_tx[0x8]; 9010 u8 reserved_3[0x8]; 9011 u8 prio_mask_rx[0x8]; 9012 9013 u8 pptx[0x1]; 9014 u8 aptx[0x1]; 9015 u8 reserved_4[0x6]; 9016 u8 pfctx[0x8]; 9017 u8 reserved_5[0x8]; 9018 u8 cbftx[0x8]; 9019 9020 u8 pprx[0x1]; 9021 u8 aprx[0x1]; 9022 u8 reserved_6[0x6]; 9023 u8 pfcrx[0x8]; 9024 u8 reserved_7[0x8]; 9025 u8 cbfrx[0x8]; 9026 9027 u8 device_stall_minor_watermark[0x10]; 9028 u8 device_stall_critical_watermark[0x10]; 9029 9030 u8 reserved_8[0x60]; 9031 }; 9032 9033 struct mlx5_ifc_pelc_reg_bits { 9034 u8 op[0x4]; 9035 u8 reserved_0[0x4]; 9036 u8 local_port[0x8]; 9037 u8 reserved_1[0x10]; 9038 9039 u8 op_admin[0x8]; 9040 u8 op_capability[0x8]; 9041 u8 op_request[0x8]; 9042 u8 op_active[0x8]; 9043 9044 u8 admin[0x40]; 9045 9046 u8 capability[0x40]; 9047 9048 u8 request[0x40]; 9049 9050 u8 active[0x40]; 9051 9052 u8 reserved_2[0x80]; 9053 }; 9054 9055 struct mlx5_ifc_peir_reg_bits { 9056 u8 reserved_0[0x8]; 9057 u8 local_port[0x8]; 9058 u8 reserved_1[0x10]; 9059 9060 u8 reserved_2[0xc]; 9061 u8 error_count[0x4]; 9062 u8 reserved_3[0x10]; 9063 9064 u8 reserved_4[0xc]; 9065 u8 lane[0x4]; 9066 u8 reserved_5[0x8]; 9067 u8 error_type[0x8]; 9068 }; 9069 9070 struct mlx5_ifc_qcam_access_reg_cap_mask { 9071 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9072 u8 qpdpm[0x1]; 9073 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9074 u8 qdpm[0x1]; 9075 u8 qpts[0x1]; 9076 u8 qcap[0x1]; 9077 u8 qcam_access_reg_cap_mask_0[0x1]; 9078 }; 9079 9080 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9081 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9082 u8 qpts_trust_both[0x1]; 9083 }; 9084 9085 struct mlx5_ifc_qcam_reg_bits { 9086 u8 reserved_at_0[0x8]; 9087 u8 feature_group[0x8]; 9088 u8 reserved_at_10[0x8]; 9089 u8 access_reg_group[0x8]; 9090 u8 reserved_at_20[0x20]; 9091 9092 union { 9093 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9094 u8 reserved_at_0[0x80]; 9095 } qos_access_reg_cap_mask; 9096 9097 u8 reserved_at_c0[0x80]; 9098 9099 union { 9100 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9101 u8 reserved_at_0[0x80]; 9102 } qos_feature_cap_mask; 9103 9104 u8 reserved_at_1c0[0x80]; 9105 }; 9106 9107 struct mlx5_ifc_pcam_enhanced_features_bits { 9108 u8 reserved_at_0[0x6d]; 9109 u8 rx_icrc_encapsulated_counter[0x1]; 9110 u8 reserved_at_6e[0x4]; 9111 u8 ptys_extended_ethernet[0x1]; 9112 u8 reserved_at_73[0x3]; 9113 u8 pfcc_mask[0x1]; 9114 u8 reserved_at_77[0x3]; 9115 u8 per_lane_error_counters[0x1]; 9116 u8 rx_buffer_fullness_counters[0x1]; 9117 u8 ptys_connector_type[0x1]; 9118 u8 reserved_at_7d[0x1]; 9119 u8 ppcnt_discard_group[0x1]; 9120 u8 ppcnt_statistical_group[0x1]; 9121 }; 9122 9123 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9124 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9125 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9126 9127 u8 reserved_at_40[0xe]; 9128 u8 pddr[0x1]; 9129 u8 reserved_at_4f[0xd]; 9130 9131 u8 pplm[0x1]; 9132 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9133 9134 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9135 u8 pbmc[0x1]; 9136 u8 pptb[0x1]; 9137 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9138 u8 ppcnt[0x1]; 9139 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9140 }; 9141 9142 struct mlx5_ifc_pcam_reg_bits { 9143 u8 reserved_at_0[0x8]; 9144 u8 feature_group[0x8]; 9145 u8 reserved_at_10[0x8]; 9146 u8 access_reg_group[0x8]; 9147 9148 u8 reserved_at_20[0x20]; 9149 9150 union { 9151 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9152 u8 reserved_at_0[0x80]; 9153 } port_access_reg_cap_mask; 9154 9155 u8 reserved_at_c0[0x80]; 9156 9157 union { 9158 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9159 u8 reserved_at_0[0x80]; 9160 } feature_cap_mask; 9161 9162 u8 reserved_at_1c0[0xc0]; 9163 }; 9164 9165 struct mlx5_ifc_mcam_enhanced_features_bits { 9166 u8 reserved_at_0[0x6e]; 9167 u8 pcie_status_and_power[0x1]; 9168 u8 reserved_at_111[0x10]; 9169 u8 pcie_performance_group[0x1]; 9170 }; 9171 9172 struct mlx5_ifc_mcam_access_reg_bits { 9173 u8 reserved_at_0[0x1c]; 9174 u8 mcda[0x1]; 9175 u8 mcc[0x1]; 9176 u8 mcqi[0x1]; 9177 u8 reserved_at_1f[0x1]; 9178 9179 u8 regs_95_to_64[0x20]; 9180 u8 regs_63_to_32[0x20]; 9181 u8 regs_31_to_0[0x20]; 9182 }; 9183 9184 struct mlx5_ifc_mcam_reg_bits { 9185 u8 reserved_at_0[0x8]; 9186 u8 feature_group[0x8]; 9187 u8 reserved_at_10[0x8]; 9188 u8 access_reg_group[0x8]; 9189 9190 u8 reserved_at_20[0x20]; 9191 9192 union { 9193 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9194 u8 reserved_at_0[0x80]; 9195 } mng_access_reg_cap_mask; 9196 9197 u8 reserved_at_c0[0x80]; 9198 9199 union { 9200 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9201 u8 reserved_at_0[0x80]; 9202 } mng_feature_cap_mask; 9203 9204 u8 reserved_at_1c0[0x80]; 9205 }; 9206 9207 struct mlx5_ifc_pcap_reg_bits { 9208 u8 reserved_0[0x8]; 9209 u8 local_port[0x8]; 9210 u8 reserved_1[0x10]; 9211 9212 u8 port_capability_mask[4][0x20]; 9213 }; 9214 9215 struct mlx5_ifc_pbmc_reg_bits { 9216 u8 reserved_at_0[0x8]; 9217 u8 local_port[0x8]; 9218 u8 reserved_at_10[0x10]; 9219 9220 u8 xoff_timer_value[0x10]; 9221 u8 xoff_refresh[0x10]; 9222 9223 u8 reserved_at_40[0x9]; 9224 u8 fullness_threshold[0x7]; 9225 u8 port_buffer_size[0x10]; 9226 9227 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9228 9229 u8 reserved_at_2e0[0x80]; 9230 }; 9231 9232 struct mlx5_ifc_paos_reg_bits { 9233 u8 swid[0x8]; 9234 u8 local_port[0x8]; 9235 u8 reserved_0[0x4]; 9236 u8 admin_status[0x4]; 9237 u8 reserved_1[0x4]; 9238 u8 oper_status[0x4]; 9239 9240 u8 ase[0x1]; 9241 u8 ee[0x1]; 9242 u8 reserved_2[0x1c]; 9243 u8 e[0x2]; 9244 9245 u8 reserved_3[0x40]; 9246 }; 9247 9248 struct mlx5_ifc_pamp_reg_bits { 9249 u8 reserved_0[0x8]; 9250 u8 opamp_group[0x8]; 9251 u8 reserved_1[0xc]; 9252 u8 opamp_group_type[0x4]; 9253 9254 u8 start_index[0x10]; 9255 u8 reserved_2[0x4]; 9256 u8 num_of_indices[0xc]; 9257 9258 u8 index_data[18][0x10]; 9259 }; 9260 9261 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 9262 u8 llr_rx_cells_high[0x20]; 9263 9264 u8 llr_rx_cells_low[0x20]; 9265 9266 u8 llr_rx_error_high[0x20]; 9267 9268 u8 llr_rx_error_low[0x20]; 9269 9270 u8 llr_rx_crc_error_high[0x20]; 9271 9272 u8 llr_rx_crc_error_low[0x20]; 9273 9274 u8 llr_tx_cells_high[0x20]; 9275 9276 u8 llr_tx_cells_low[0x20]; 9277 9278 u8 llr_tx_ret_cells_high[0x20]; 9279 9280 u8 llr_tx_ret_cells_low[0x20]; 9281 9282 u8 llr_tx_ret_events_high[0x20]; 9283 9284 u8 llr_tx_ret_events_low[0x20]; 9285 9286 u8 reserved_0[0x640]; 9287 }; 9288 9289 struct mlx5_ifc_mtmp_reg_bits { 9290 u8 i[0x1]; 9291 u8 reserved_at_1[0x18]; 9292 u8 sensor_index[0x7]; 9293 9294 u8 reserved_at_20[0x10]; 9295 u8 temperature[0x10]; 9296 9297 u8 mte[0x1]; 9298 u8 mtr[0x1]; 9299 u8 reserved_at_42[0x0e]; 9300 u8 max_temperature[0x10]; 9301 9302 u8 tee[0x2]; 9303 u8 reserved_at_62[0x0e]; 9304 u8 temperature_threshold_hi[0x10]; 9305 9306 u8 reserved_at_80[0x10]; 9307 u8 temperature_threshold_lo[0x10]; 9308 9309 u8 reserved_at_100[0x20]; 9310 9311 u8 sensor_name[0x40]; 9312 }; 9313 9314 struct mlx5_ifc_lane_2_module_mapping_bits { 9315 u8 reserved_0[0x6]; 9316 u8 rx_lane[0x2]; 9317 u8 reserved_1[0x6]; 9318 u8 tx_lane[0x2]; 9319 u8 reserved_2[0x8]; 9320 u8 module[0x8]; 9321 }; 9322 9323 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 9324 u8 transmit_queue_high[0x20]; 9325 9326 u8 transmit_queue_low[0x20]; 9327 9328 u8 reserved_0[0x780]; 9329 }; 9330 9331 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 9332 u8 no_buffer_discard_uc_high[0x20]; 9333 9334 u8 no_buffer_discard_uc_low[0x20]; 9335 9336 u8 wred_discard_high[0x20]; 9337 9338 u8 wred_discard_low[0x20]; 9339 9340 u8 reserved_0[0x740]; 9341 }; 9342 9343 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 9344 u8 rx_octets_high[0x20]; 9345 9346 u8 rx_octets_low[0x20]; 9347 9348 u8 reserved_0[0xc0]; 9349 9350 u8 rx_frames_high[0x20]; 9351 9352 u8 rx_frames_low[0x20]; 9353 9354 u8 tx_octets_high[0x20]; 9355 9356 u8 tx_octets_low[0x20]; 9357 9358 u8 reserved_1[0xc0]; 9359 9360 u8 tx_frames_high[0x20]; 9361 9362 u8 tx_frames_low[0x20]; 9363 9364 u8 rx_pause_high[0x20]; 9365 9366 u8 rx_pause_low[0x20]; 9367 9368 u8 rx_pause_duration_high[0x20]; 9369 9370 u8 rx_pause_duration_low[0x20]; 9371 9372 u8 tx_pause_high[0x20]; 9373 9374 u8 tx_pause_low[0x20]; 9375 9376 u8 tx_pause_duration_high[0x20]; 9377 9378 u8 tx_pause_duration_low[0x20]; 9379 9380 u8 rx_pause_transition_high[0x20]; 9381 9382 u8 rx_pause_transition_low[0x20]; 9383 9384 u8 rx_discards_high[0x20]; 9385 9386 u8 rx_discards_low[0x20]; 9387 9388 u8 device_stall_minor_watermark_cnt_high[0x20]; 9389 9390 u8 device_stall_minor_watermark_cnt_low[0x20]; 9391 9392 u8 device_stall_critical_watermark_cnt_high[0x20]; 9393 9394 u8 device_stall_critical_watermark_cnt_low[0x20]; 9395 9396 u8 reserved_2[0x340]; 9397 }; 9398 9399 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 9400 u8 port_transmit_wait_high[0x20]; 9401 9402 u8 port_transmit_wait_low[0x20]; 9403 9404 u8 ecn_marked_high[0x20]; 9405 9406 u8 ecn_marked_low[0x20]; 9407 9408 u8 no_buffer_discard_mc_high[0x20]; 9409 9410 u8 no_buffer_discard_mc_low[0x20]; 9411 9412 u8 rx_ebp_high[0x20]; 9413 9414 u8 rx_ebp_low[0x20]; 9415 9416 u8 tx_ebp_high[0x20]; 9417 9418 u8 tx_ebp_low[0x20]; 9419 9420 u8 rx_buffer_almost_full_high[0x20]; 9421 9422 u8 rx_buffer_almost_full_low[0x20]; 9423 9424 u8 rx_buffer_full_high[0x20]; 9425 9426 u8 rx_buffer_full_low[0x20]; 9427 9428 u8 rx_icrc_encapsulated_high[0x20]; 9429 9430 u8 rx_icrc_encapsulated_low[0x20]; 9431 9432 u8 reserved_0[0x80]; 9433 9434 u8 tx_stats_pkts64octets_high[0x20]; 9435 9436 u8 tx_stats_pkts64octets_low[0x20]; 9437 9438 u8 tx_stats_pkts65to127octets_high[0x20]; 9439 9440 u8 tx_stats_pkts65to127octets_low[0x20]; 9441 9442 u8 tx_stats_pkts128to255octets_high[0x20]; 9443 9444 u8 tx_stats_pkts128to255octets_low[0x20]; 9445 9446 u8 tx_stats_pkts256to511octets_high[0x20]; 9447 9448 u8 tx_stats_pkts256to511octets_low[0x20]; 9449 9450 u8 tx_stats_pkts512to1023octets_high[0x20]; 9451 9452 u8 tx_stats_pkts512to1023octets_low[0x20]; 9453 9454 u8 tx_stats_pkts1024to1518octets_high[0x20]; 9455 9456 u8 tx_stats_pkts1024to1518octets_low[0x20]; 9457 9458 u8 tx_stats_pkts1519to2047octets_high[0x20]; 9459 9460 u8 tx_stats_pkts1519to2047octets_low[0x20]; 9461 9462 u8 tx_stats_pkts2048to4095octets_high[0x20]; 9463 9464 u8 tx_stats_pkts2048to4095octets_low[0x20]; 9465 9466 u8 tx_stats_pkts4096to8191octets_high[0x20]; 9467 9468 u8 tx_stats_pkts4096to8191octets_low[0x20]; 9469 9470 u8 tx_stats_pkts8192to10239octets_high[0x20]; 9471 9472 u8 tx_stats_pkts8192to10239octets_low[0x20]; 9473 9474 u8 reserved_1[0x2C0]; 9475 }; 9476 9477 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 9478 u8 a_frames_transmitted_ok_high[0x20]; 9479 9480 u8 a_frames_transmitted_ok_low[0x20]; 9481 9482 u8 a_frames_received_ok_high[0x20]; 9483 9484 u8 a_frames_received_ok_low[0x20]; 9485 9486 u8 a_frame_check_sequence_errors_high[0x20]; 9487 9488 u8 a_frame_check_sequence_errors_low[0x20]; 9489 9490 u8 a_alignment_errors_high[0x20]; 9491 9492 u8 a_alignment_errors_low[0x20]; 9493 9494 u8 a_octets_transmitted_ok_high[0x20]; 9495 9496 u8 a_octets_transmitted_ok_low[0x20]; 9497 9498 u8 a_octets_received_ok_high[0x20]; 9499 9500 u8 a_octets_received_ok_low[0x20]; 9501 9502 u8 a_multicast_frames_xmitted_ok_high[0x20]; 9503 9504 u8 a_multicast_frames_xmitted_ok_low[0x20]; 9505 9506 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 9507 9508 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 9509 9510 u8 a_multicast_frames_received_ok_high[0x20]; 9511 9512 u8 a_multicast_frames_received_ok_low[0x20]; 9513 9514 u8 a_broadcast_frames_recieved_ok_high[0x20]; 9515 9516 u8 a_broadcast_frames_recieved_ok_low[0x20]; 9517 9518 u8 a_in_range_length_errors_high[0x20]; 9519 9520 u8 a_in_range_length_errors_low[0x20]; 9521 9522 u8 a_out_of_range_length_field_high[0x20]; 9523 9524 u8 a_out_of_range_length_field_low[0x20]; 9525 9526 u8 a_frame_too_long_errors_high[0x20]; 9527 9528 u8 a_frame_too_long_errors_low[0x20]; 9529 9530 u8 a_symbol_error_during_carrier_high[0x20]; 9531 9532 u8 a_symbol_error_during_carrier_low[0x20]; 9533 9534 u8 a_mac_control_frames_transmitted_high[0x20]; 9535 9536 u8 a_mac_control_frames_transmitted_low[0x20]; 9537 9538 u8 a_mac_control_frames_received_high[0x20]; 9539 9540 u8 a_mac_control_frames_received_low[0x20]; 9541 9542 u8 a_unsupported_opcodes_received_high[0x20]; 9543 9544 u8 a_unsupported_opcodes_received_low[0x20]; 9545 9546 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 9547 9548 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 9549 9550 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 9551 9552 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 9553 9554 u8 reserved_0[0x300]; 9555 }; 9556 9557 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 9558 u8 dot3stats_alignment_errors_high[0x20]; 9559 9560 u8 dot3stats_alignment_errors_low[0x20]; 9561 9562 u8 dot3stats_fcs_errors_high[0x20]; 9563 9564 u8 dot3stats_fcs_errors_low[0x20]; 9565 9566 u8 dot3stats_single_collision_frames_high[0x20]; 9567 9568 u8 dot3stats_single_collision_frames_low[0x20]; 9569 9570 u8 dot3stats_multiple_collision_frames_high[0x20]; 9571 9572 u8 dot3stats_multiple_collision_frames_low[0x20]; 9573 9574 u8 dot3stats_sqe_test_errors_high[0x20]; 9575 9576 u8 dot3stats_sqe_test_errors_low[0x20]; 9577 9578 u8 dot3stats_deferred_transmissions_high[0x20]; 9579 9580 u8 dot3stats_deferred_transmissions_low[0x20]; 9581 9582 u8 dot3stats_late_collisions_high[0x20]; 9583 9584 u8 dot3stats_late_collisions_low[0x20]; 9585 9586 u8 dot3stats_excessive_collisions_high[0x20]; 9587 9588 u8 dot3stats_excessive_collisions_low[0x20]; 9589 9590 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 9591 9592 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 9593 9594 u8 dot3stats_carrier_sense_errors_high[0x20]; 9595 9596 u8 dot3stats_carrier_sense_errors_low[0x20]; 9597 9598 u8 dot3stats_frame_too_longs_high[0x20]; 9599 9600 u8 dot3stats_frame_too_longs_low[0x20]; 9601 9602 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 9603 9604 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 9605 9606 u8 dot3stats_symbol_errors_high[0x20]; 9607 9608 u8 dot3stats_symbol_errors_low[0x20]; 9609 9610 u8 dot3control_in_unknown_opcodes_high[0x20]; 9611 9612 u8 dot3control_in_unknown_opcodes_low[0x20]; 9613 9614 u8 dot3in_pause_frames_high[0x20]; 9615 9616 u8 dot3in_pause_frames_low[0x20]; 9617 9618 u8 dot3out_pause_frames_high[0x20]; 9619 9620 u8 dot3out_pause_frames_low[0x20]; 9621 9622 u8 reserved_0[0x3c0]; 9623 }; 9624 9625 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 9626 u8 if_in_octets_high[0x20]; 9627 9628 u8 if_in_octets_low[0x20]; 9629 9630 u8 if_in_ucast_pkts_high[0x20]; 9631 9632 u8 if_in_ucast_pkts_low[0x20]; 9633 9634 u8 if_in_discards_high[0x20]; 9635 9636 u8 if_in_discards_low[0x20]; 9637 9638 u8 if_in_errors_high[0x20]; 9639 9640 u8 if_in_errors_low[0x20]; 9641 9642 u8 if_in_unknown_protos_high[0x20]; 9643 9644 u8 if_in_unknown_protos_low[0x20]; 9645 9646 u8 if_out_octets_high[0x20]; 9647 9648 u8 if_out_octets_low[0x20]; 9649 9650 u8 if_out_ucast_pkts_high[0x20]; 9651 9652 u8 if_out_ucast_pkts_low[0x20]; 9653 9654 u8 if_out_discards_high[0x20]; 9655 9656 u8 if_out_discards_low[0x20]; 9657 9658 u8 if_out_errors_high[0x20]; 9659 9660 u8 if_out_errors_low[0x20]; 9661 9662 u8 if_in_multicast_pkts_high[0x20]; 9663 9664 u8 if_in_multicast_pkts_low[0x20]; 9665 9666 u8 if_in_broadcast_pkts_high[0x20]; 9667 9668 u8 if_in_broadcast_pkts_low[0x20]; 9669 9670 u8 if_out_multicast_pkts_high[0x20]; 9671 9672 u8 if_out_multicast_pkts_low[0x20]; 9673 9674 u8 if_out_broadcast_pkts_high[0x20]; 9675 9676 u8 if_out_broadcast_pkts_low[0x20]; 9677 9678 u8 reserved_0[0x480]; 9679 }; 9680 9681 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 9682 u8 ether_stats_drop_events_high[0x20]; 9683 9684 u8 ether_stats_drop_events_low[0x20]; 9685 9686 u8 ether_stats_octets_high[0x20]; 9687 9688 u8 ether_stats_octets_low[0x20]; 9689 9690 u8 ether_stats_pkts_high[0x20]; 9691 9692 u8 ether_stats_pkts_low[0x20]; 9693 9694 u8 ether_stats_broadcast_pkts_high[0x20]; 9695 9696 u8 ether_stats_broadcast_pkts_low[0x20]; 9697 9698 u8 ether_stats_multicast_pkts_high[0x20]; 9699 9700 u8 ether_stats_multicast_pkts_low[0x20]; 9701 9702 u8 ether_stats_crc_align_errors_high[0x20]; 9703 9704 u8 ether_stats_crc_align_errors_low[0x20]; 9705 9706 u8 ether_stats_undersize_pkts_high[0x20]; 9707 9708 u8 ether_stats_undersize_pkts_low[0x20]; 9709 9710 u8 ether_stats_oversize_pkts_high[0x20]; 9711 9712 u8 ether_stats_oversize_pkts_low[0x20]; 9713 9714 u8 ether_stats_fragments_high[0x20]; 9715 9716 u8 ether_stats_fragments_low[0x20]; 9717 9718 u8 ether_stats_jabbers_high[0x20]; 9719 9720 u8 ether_stats_jabbers_low[0x20]; 9721 9722 u8 ether_stats_collisions_high[0x20]; 9723 9724 u8 ether_stats_collisions_low[0x20]; 9725 9726 u8 ether_stats_pkts64octets_high[0x20]; 9727 9728 u8 ether_stats_pkts64octets_low[0x20]; 9729 9730 u8 ether_stats_pkts65to127octets_high[0x20]; 9731 9732 u8 ether_stats_pkts65to127octets_low[0x20]; 9733 9734 u8 ether_stats_pkts128to255octets_high[0x20]; 9735 9736 u8 ether_stats_pkts128to255octets_low[0x20]; 9737 9738 u8 ether_stats_pkts256to511octets_high[0x20]; 9739 9740 u8 ether_stats_pkts256to511octets_low[0x20]; 9741 9742 u8 ether_stats_pkts512to1023octets_high[0x20]; 9743 9744 u8 ether_stats_pkts512to1023octets_low[0x20]; 9745 9746 u8 ether_stats_pkts1024to1518octets_high[0x20]; 9747 9748 u8 ether_stats_pkts1024to1518octets_low[0x20]; 9749 9750 u8 ether_stats_pkts1519to2047octets_high[0x20]; 9751 9752 u8 ether_stats_pkts1519to2047octets_low[0x20]; 9753 9754 u8 ether_stats_pkts2048to4095octets_high[0x20]; 9755 9756 u8 ether_stats_pkts2048to4095octets_low[0x20]; 9757 9758 u8 ether_stats_pkts4096to8191octets_high[0x20]; 9759 9760 u8 ether_stats_pkts4096to8191octets_low[0x20]; 9761 9762 u8 ether_stats_pkts8192to10239octets_high[0x20]; 9763 9764 u8 ether_stats_pkts8192to10239octets_low[0x20]; 9765 9766 u8 reserved_0[0x280]; 9767 }; 9768 9769 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 9770 u8 symbol_error_counter[0x10]; 9771 u8 link_error_recovery_counter[0x8]; 9772 u8 link_downed_counter[0x8]; 9773 9774 u8 port_rcv_errors[0x10]; 9775 u8 port_rcv_remote_physical_errors[0x10]; 9776 9777 u8 port_rcv_switch_relay_errors[0x10]; 9778 u8 port_xmit_discards[0x10]; 9779 9780 u8 port_xmit_constraint_errors[0x8]; 9781 u8 port_rcv_constraint_errors[0x8]; 9782 u8 reserved_0[0x8]; 9783 u8 local_link_integrity_errors[0x4]; 9784 u8 excessive_buffer_overrun_errors[0x4]; 9785 9786 u8 reserved_1[0x10]; 9787 u8 vl_15_dropped[0x10]; 9788 9789 u8 port_xmit_data[0x20]; 9790 9791 u8 port_rcv_data[0x20]; 9792 9793 u8 port_xmit_pkts[0x20]; 9794 9795 u8 port_rcv_pkts[0x20]; 9796 9797 u8 port_xmit_wait[0x20]; 9798 9799 u8 reserved_2[0x680]; 9800 }; 9801 9802 struct mlx5_ifc_trc_tlb_reg_bits { 9803 u8 reserved_0[0x80]; 9804 9805 u8 tlb_addr[0][0x40]; 9806 }; 9807 9808 struct mlx5_ifc_trc_read_fifo_reg_bits { 9809 u8 reserved_0[0x10]; 9810 u8 requested_event_num[0x10]; 9811 9812 u8 reserved_1[0x20]; 9813 9814 u8 reserved_2[0x10]; 9815 u8 acual_event_num[0x10]; 9816 9817 u8 reserved_3[0x20]; 9818 9819 u8 event[0][0x40]; 9820 }; 9821 9822 struct mlx5_ifc_trc_lock_reg_bits { 9823 u8 reserved_0[0x1f]; 9824 u8 lock[0x1]; 9825 9826 u8 reserved_1[0x60]; 9827 }; 9828 9829 struct mlx5_ifc_trc_filter_reg_bits { 9830 u8 status[0x1]; 9831 u8 reserved_0[0xf]; 9832 u8 filter_index[0x10]; 9833 9834 u8 reserved_1[0x20]; 9835 9836 u8 filter_val[0x20]; 9837 9838 u8 reserved_2[0x1a0]; 9839 }; 9840 9841 struct mlx5_ifc_trc_event_reg_bits { 9842 u8 status[0x1]; 9843 u8 reserved_0[0xf]; 9844 u8 event_index[0x10]; 9845 9846 u8 reserved_1[0x20]; 9847 9848 u8 event_id[0x20]; 9849 9850 u8 event_selector_val[0x10]; 9851 u8 event_selector_size[0x10]; 9852 9853 u8 reserved_2[0x180]; 9854 }; 9855 9856 struct mlx5_ifc_trc_conf_reg_bits { 9857 u8 limit_en[0x1]; 9858 u8 reserved_0[0x3]; 9859 u8 dump_mode[0x4]; 9860 u8 reserved_1[0x15]; 9861 u8 state[0x3]; 9862 9863 u8 reserved_2[0x20]; 9864 9865 u8 limit_event_index[0x20]; 9866 9867 u8 mkey[0x20]; 9868 9869 u8 fifo_ready_ev_num[0x20]; 9870 9871 u8 reserved_3[0x160]; 9872 }; 9873 9874 struct mlx5_ifc_trc_cap_reg_bits { 9875 u8 reserved_0[0x18]; 9876 u8 dump_mode[0x8]; 9877 9878 u8 reserved_1[0x20]; 9879 9880 u8 num_of_events[0x10]; 9881 u8 num_of_filters[0x10]; 9882 9883 u8 fifo_size[0x20]; 9884 9885 u8 tlb_size[0x10]; 9886 u8 event_size[0x10]; 9887 9888 u8 reserved_2[0x160]; 9889 }; 9890 9891 struct mlx5_ifc_set_node_in_bits { 9892 u8 node_description[64][0x8]; 9893 }; 9894 9895 struct mlx5_ifc_register_power_settings_bits { 9896 u8 reserved_0[0x18]; 9897 u8 power_settings_level[0x8]; 9898 9899 u8 reserved_1[0x60]; 9900 }; 9901 9902 struct mlx5_ifc_register_host_endianess_bits { 9903 u8 he[0x1]; 9904 u8 reserved_0[0x1f]; 9905 9906 u8 reserved_1[0x60]; 9907 }; 9908 9909 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9910 u8 physical_address[0x40]; 9911 }; 9912 9913 struct mlx5_ifc_qtct_reg_bits { 9914 u8 operation_type[0x2]; 9915 u8 cap_local_admin[0x1]; 9916 u8 cap_remote_admin[0x1]; 9917 u8 reserved_0[0x4]; 9918 u8 port_number[0x8]; 9919 u8 reserved_1[0xd]; 9920 u8 prio[0x3]; 9921 9922 u8 reserved_2[0x1d]; 9923 u8 tclass[0x3]; 9924 }; 9925 9926 struct mlx5_ifc_qpdp_reg_bits { 9927 u8 reserved_0[0x8]; 9928 u8 port_number[0x8]; 9929 u8 reserved_1[0x10]; 9930 9931 u8 reserved_2[0x1d]; 9932 u8 pprio[0x3]; 9933 }; 9934 9935 struct mlx5_ifc_port_info_ro_fields_param_bits { 9936 u8 reserved_0[0x8]; 9937 u8 port[0x8]; 9938 u8 max_gid[0x10]; 9939 9940 u8 reserved_1[0x20]; 9941 9942 u8 port_guid[0x40]; 9943 }; 9944 9945 struct mlx5_ifc_nvqc_reg_bits { 9946 u8 type[0x20]; 9947 9948 u8 reserved_0[0x18]; 9949 u8 version[0x4]; 9950 u8 reserved_1[0x2]; 9951 u8 support_wr[0x1]; 9952 u8 support_rd[0x1]; 9953 }; 9954 9955 struct mlx5_ifc_nvia_reg_bits { 9956 u8 reserved_0[0x1d]; 9957 u8 target[0x3]; 9958 9959 u8 reserved_1[0x20]; 9960 }; 9961 9962 struct mlx5_ifc_nvdi_reg_bits { 9963 struct mlx5_ifc_config_item_bits configuration_item_header; 9964 }; 9965 9966 struct mlx5_ifc_nvda_reg_bits { 9967 struct mlx5_ifc_config_item_bits configuration_item_header; 9968 9969 u8 configuration_item_data[0x20]; 9970 }; 9971 9972 struct mlx5_ifc_node_info_ro_fields_param_bits { 9973 u8 system_image_guid[0x40]; 9974 9975 u8 reserved_0[0x40]; 9976 9977 u8 node_guid[0x40]; 9978 9979 u8 reserved_1[0x10]; 9980 u8 max_pkey[0x10]; 9981 9982 u8 reserved_2[0x20]; 9983 }; 9984 9985 struct mlx5_ifc_ets_tcn_config_reg_bits { 9986 u8 g[0x1]; 9987 u8 b[0x1]; 9988 u8 r[0x1]; 9989 u8 reserved_0[0x9]; 9990 u8 group[0x4]; 9991 u8 reserved_1[0x9]; 9992 u8 bw_allocation[0x7]; 9993 9994 u8 reserved_2[0xc]; 9995 u8 max_bw_units[0x4]; 9996 u8 reserved_3[0x8]; 9997 u8 max_bw_value[0x8]; 9998 }; 9999 10000 struct mlx5_ifc_ets_global_config_reg_bits { 10001 u8 reserved_0[0x2]; 10002 u8 r[0x1]; 10003 u8 reserved_1[0x1d]; 10004 10005 u8 reserved_2[0xc]; 10006 u8 max_bw_units[0x4]; 10007 u8 reserved_3[0x8]; 10008 u8 max_bw_value[0x8]; 10009 }; 10010 10011 struct mlx5_ifc_qetc_reg_bits { 10012 u8 reserved_at_0[0x8]; 10013 u8 port_number[0x8]; 10014 u8 reserved_at_10[0x30]; 10015 10016 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10017 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10018 }; 10019 10020 struct mlx5_ifc_nodnic_mac_filters_bits { 10021 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 10022 10023 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 10024 10025 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 10026 10027 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 10028 10029 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 10030 10031 u8 reserved_0[0xc0]; 10032 }; 10033 10034 struct mlx5_ifc_nodnic_gid_filters_bits { 10035 u8 mgid_filter0[16][0x8]; 10036 10037 u8 mgid_filter1[16][0x8]; 10038 10039 u8 mgid_filter2[16][0x8]; 10040 10041 u8 mgid_filter3[16][0x8]; 10042 }; 10043 10044 enum { 10045 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 10046 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 10047 }; 10048 10049 enum { 10050 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 10051 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 10052 }; 10053 10054 struct mlx5_ifc_nodnic_config_reg_bits { 10055 u8 no_dram_nic_revision[0x8]; 10056 u8 hardware_format[0x8]; 10057 u8 support_receive_filter[0x1]; 10058 u8 support_promisc_filter[0x1]; 10059 u8 support_promisc_multicast_filter[0x1]; 10060 u8 reserved_0[0x2]; 10061 u8 log_working_buffer_size[0x3]; 10062 u8 log_pkey_table_size[0x4]; 10063 u8 reserved_1[0x3]; 10064 u8 num_ports[0x1]; 10065 10066 u8 reserved_2[0x2]; 10067 u8 log_max_ring_size[0x6]; 10068 u8 reserved_3[0x18]; 10069 10070 u8 lkey[0x20]; 10071 10072 u8 cqe_format[0x4]; 10073 u8 reserved_4[0x1c]; 10074 10075 u8 node_guid[0x40]; 10076 10077 u8 reserved_5[0x740]; 10078 10079 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 10080 10081 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 10082 }; 10083 10084 struct mlx5_ifc_vlan_layout_bits { 10085 u8 reserved_0[0x14]; 10086 u8 vlan[0xc]; 10087 10088 u8 reserved_1[0x20]; 10089 }; 10090 10091 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10092 u8 reserved_0[0x20]; 10093 10094 u8 mkey[0x20]; 10095 10096 u8 addressh_63_32[0x20]; 10097 10098 u8 addressl_31_0[0x20]; 10099 }; 10100 10101 struct mlx5_ifc_ud_adrs_vector_bits { 10102 u8 dc_key[0x40]; 10103 10104 u8 ext[0x1]; 10105 u8 reserved_0[0x7]; 10106 u8 destination_qp_dct[0x18]; 10107 10108 u8 static_rate[0x4]; 10109 u8 sl_eth_prio[0x4]; 10110 u8 fl[0x1]; 10111 u8 mlid[0x7]; 10112 u8 rlid_udp_sport[0x10]; 10113 10114 u8 reserved_1[0x20]; 10115 10116 u8 rmac_47_16[0x20]; 10117 10118 u8 rmac_15_0[0x10]; 10119 u8 tclass[0x8]; 10120 u8 hop_limit[0x8]; 10121 10122 u8 reserved_2[0x1]; 10123 u8 grh[0x1]; 10124 u8 reserved_3[0x2]; 10125 u8 src_addr_index[0x8]; 10126 u8 flow_label[0x14]; 10127 10128 u8 rgid_rip[16][0x8]; 10129 }; 10130 10131 struct mlx5_ifc_port_module_event_bits { 10132 u8 reserved_0[0x8]; 10133 u8 module[0x8]; 10134 u8 reserved_1[0xc]; 10135 u8 module_status[0x4]; 10136 10137 u8 reserved_2[0x14]; 10138 u8 error_type[0x4]; 10139 u8 reserved_3[0x8]; 10140 10141 u8 reserved_4[0xa0]; 10142 }; 10143 10144 struct mlx5_ifc_icmd_control_bits { 10145 u8 opcode[0x10]; 10146 u8 status[0x8]; 10147 u8 reserved_0[0x7]; 10148 u8 busy[0x1]; 10149 }; 10150 10151 struct mlx5_ifc_eqe_bits { 10152 u8 reserved_0[0x8]; 10153 u8 event_type[0x8]; 10154 u8 reserved_1[0x8]; 10155 u8 event_sub_type[0x8]; 10156 10157 u8 reserved_2[0xe0]; 10158 10159 union mlx5_ifc_event_auto_bits event_data; 10160 10161 u8 reserved_3[0x10]; 10162 u8 signature[0x8]; 10163 u8 reserved_4[0x7]; 10164 u8 owner[0x1]; 10165 }; 10166 10167 enum { 10168 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10169 }; 10170 10171 struct mlx5_ifc_cmd_queue_entry_bits { 10172 u8 type[0x8]; 10173 u8 reserved_0[0x18]; 10174 10175 u8 input_length[0x20]; 10176 10177 u8 input_mailbox_pointer_63_32[0x20]; 10178 10179 u8 input_mailbox_pointer_31_9[0x17]; 10180 u8 reserved_1[0x9]; 10181 10182 u8 command_input_inline_data[16][0x8]; 10183 10184 u8 command_output_inline_data[16][0x8]; 10185 10186 u8 output_mailbox_pointer_63_32[0x20]; 10187 10188 u8 output_mailbox_pointer_31_9[0x17]; 10189 u8 reserved_2[0x9]; 10190 10191 u8 output_length[0x20]; 10192 10193 u8 token[0x8]; 10194 u8 signature[0x8]; 10195 u8 reserved_3[0x8]; 10196 u8 status[0x7]; 10197 u8 ownership[0x1]; 10198 }; 10199 10200 struct mlx5_ifc_cmd_out_bits { 10201 u8 status[0x8]; 10202 u8 reserved_0[0x18]; 10203 10204 u8 syndrome[0x20]; 10205 10206 u8 command_output[0x20]; 10207 }; 10208 10209 struct mlx5_ifc_cmd_in_bits { 10210 u8 opcode[0x10]; 10211 u8 reserved_0[0x10]; 10212 10213 u8 reserved_1[0x10]; 10214 u8 op_mod[0x10]; 10215 10216 u8 command[0][0x20]; 10217 }; 10218 10219 struct mlx5_ifc_cmd_if_box_bits { 10220 u8 mailbox_data[512][0x8]; 10221 10222 u8 reserved_0[0x180]; 10223 10224 u8 next_pointer_63_32[0x20]; 10225 10226 u8 next_pointer_31_10[0x16]; 10227 u8 reserved_1[0xa]; 10228 10229 u8 block_number[0x20]; 10230 10231 u8 reserved_2[0x8]; 10232 u8 token[0x8]; 10233 u8 ctrl_signature[0x8]; 10234 u8 signature[0x8]; 10235 }; 10236 10237 struct mlx5_ifc_mtt_bits { 10238 u8 ptag_63_32[0x20]; 10239 10240 u8 ptag_31_8[0x18]; 10241 u8 reserved_0[0x6]; 10242 u8 wr_en[0x1]; 10243 u8 rd_en[0x1]; 10244 }; 10245 10246 struct mlx5_ifc_tls_progress_params_bits { 10247 u8 valid[0x1]; 10248 u8 reserved_at_1[0x7]; 10249 u8 pd[0x18]; 10250 10251 u8 next_record_tcp_sn[0x20]; 10252 10253 u8 hw_resync_tcp_sn[0x20]; 10254 10255 u8 record_tracker_state[0x2]; 10256 u8 auth_state[0x2]; 10257 u8 reserved_at_64[0x4]; 10258 u8 hw_offset_record_number[0x18]; 10259 }; 10260 10261 struct mlx5_ifc_tls_static_params_bits { 10262 u8 const_2[0x2]; 10263 u8 tls_version[0x4]; 10264 u8 const_1[0x2]; 10265 u8 reserved_at_8[0x14]; 10266 u8 encryption_standard[0x4]; 10267 10268 u8 reserved_at_20[0x20]; 10269 10270 u8 initial_record_number[0x40]; 10271 10272 u8 resync_tcp_sn[0x20]; 10273 10274 u8 gcm_iv[0x20]; 10275 10276 u8 implicit_iv[0x40]; 10277 10278 u8 reserved_at_100[0x8]; 10279 u8 dek_index[0x18]; 10280 10281 u8 reserved_at_120[0xe0]; 10282 }; 10283 10284 /* Vendor Specific Capabilities, VSC */ 10285 enum { 10286 MLX5_VSC_DOMAIN_ICMD = 0x1, 10287 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 10288 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7, 10289 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 10290 }; 10291 10292 struct mlx5_ifc_vendor_specific_cap_bits { 10293 u8 type[0x8]; 10294 u8 length[0x8]; 10295 u8 next_pointer[0x8]; 10296 u8 capability_id[0x8]; 10297 10298 u8 status[0x3]; 10299 u8 reserved_0[0xd]; 10300 u8 space[0x10]; 10301 10302 u8 counter[0x20]; 10303 10304 u8 semaphore[0x20]; 10305 10306 u8 flag[0x1]; 10307 u8 reserved_1[0x1]; 10308 u8 address[0x1e]; 10309 10310 u8 data[0x20]; 10311 }; 10312 10313 struct mlx5_ifc_vsc_space_bits { 10314 u8 status[0x3]; 10315 u8 reserved0[0xd]; 10316 u8 space[0x10]; 10317 }; 10318 10319 struct mlx5_ifc_vsc_addr_bits { 10320 u8 flag[0x1]; 10321 u8 reserved0[0x1]; 10322 u8 address[0x1e]; 10323 }; 10324 10325 enum { 10326 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10327 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10328 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10329 }; 10330 10331 enum { 10332 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10333 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10334 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10335 }; 10336 10337 enum { 10338 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 10339 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 10340 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 10341 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 10342 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 10343 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 10344 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 10345 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 10346 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 10347 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 10348 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 10349 }; 10350 10351 struct mlx5_ifc_initial_seg_bits { 10352 u8 fw_rev_minor[0x10]; 10353 u8 fw_rev_major[0x10]; 10354 10355 u8 cmd_interface_rev[0x10]; 10356 u8 fw_rev_subminor[0x10]; 10357 10358 u8 reserved_0[0x40]; 10359 10360 u8 cmdq_phy_addr_63_32[0x20]; 10361 10362 u8 cmdq_phy_addr_31_12[0x14]; 10363 u8 reserved_1[0x2]; 10364 u8 nic_interface[0x2]; 10365 u8 log_cmdq_size[0x4]; 10366 u8 log_cmdq_stride[0x4]; 10367 10368 u8 command_doorbell_vector[0x20]; 10369 10370 u8 reserved_2[0xf00]; 10371 10372 u8 initializing[0x1]; 10373 u8 reserved_3[0x4]; 10374 u8 nic_interface_supported[0x3]; 10375 u8 reserved_4[0x18]; 10376 10377 struct mlx5_ifc_health_buffer_bits health_buffer; 10378 10379 u8 no_dram_nic_offset[0x20]; 10380 10381 u8 reserved_5[0x6de0]; 10382 10383 u8 internal_timer_h[0x20]; 10384 10385 u8 internal_timer_l[0x20]; 10386 10387 u8 reserved_6[0x20]; 10388 10389 u8 reserved_7[0x1f]; 10390 u8 clear_int[0x1]; 10391 10392 u8 health_syndrome[0x8]; 10393 u8 health_counter[0x18]; 10394 10395 u8 reserved_8[0x17fc0]; 10396 }; 10397 10398 union mlx5_ifc_icmd_interface_document_bits { 10399 struct mlx5_ifc_fw_version_bits fw_version; 10400 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 10401 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 10402 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 10403 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 10404 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 10405 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 10406 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 10407 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 10408 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 10409 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 10410 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 10411 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 10412 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 10413 u8 reserved_0[0x42c0]; 10414 }; 10415 10416 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 10417 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10418 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10419 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10420 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10421 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10422 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10423 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10424 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10425 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 10426 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 10427 u8 reserved_0[0x7c0]; 10428 }; 10429 10430 struct mlx5_ifc_ppcnt_reg_bits { 10431 u8 swid[0x8]; 10432 u8 local_port[0x8]; 10433 u8 pnat[0x2]; 10434 u8 reserved_0[0x8]; 10435 u8 grp[0x6]; 10436 10437 u8 clr[0x1]; 10438 u8 reserved_1[0x1c]; 10439 u8 prio_tc[0x3]; 10440 10441 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10442 }; 10443 10444 struct mlx5_ifc_pcie_lanes_counters_bits { 10445 u8 life_time_counter_high[0x20]; 10446 10447 u8 life_time_counter_low[0x20]; 10448 10449 u8 error_counter_lane0[0x20]; 10450 10451 u8 error_counter_lane1[0x20]; 10452 10453 u8 error_counter_lane2[0x20]; 10454 10455 u8 error_counter_lane3[0x20]; 10456 10457 u8 error_counter_lane4[0x20]; 10458 10459 u8 error_counter_lane5[0x20]; 10460 10461 u8 error_counter_lane6[0x20]; 10462 10463 u8 error_counter_lane7[0x20]; 10464 10465 u8 error_counter_lane8[0x20]; 10466 10467 u8 error_counter_lane9[0x20]; 10468 10469 u8 error_counter_lane10[0x20]; 10470 10471 u8 error_counter_lane11[0x20]; 10472 10473 u8 error_counter_lane12[0x20]; 10474 10475 u8 error_counter_lane13[0x20]; 10476 10477 u8 error_counter_lane14[0x20]; 10478 10479 u8 error_counter_lane15[0x20]; 10480 10481 u8 reserved_at_240[0x580]; 10482 }; 10483 10484 struct mlx5_ifc_pcie_lanes_counters_ext_bits { 10485 u8 reserved_at_0[0x40]; 10486 10487 u8 error_counter_lane0[0x20]; 10488 10489 u8 error_counter_lane1[0x20]; 10490 10491 u8 error_counter_lane2[0x20]; 10492 10493 u8 error_counter_lane3[0x20]; 10494 10495 u8 error_counter_lane4[0x20]; 10496 10497 u8 error_counter_lane5[0x20]; 10498 10499 u8 error_counter_lane6[0x20]; 10500 10501 u8 error_counter_lane7[0x20]; 10502 10503 u8 error_counter_lane8[0x20]; 10504 10505 u8 error_counter_lane9[0x20]; 10506 10507 u8 error_counter_lane10[0x20]; 10508 10509 u8 error_counter_lane11[0x20]; 10510 10511 u8 error_counter_lane12[0x20]; 10512 10513 u8 error_counter_lane13[0x20]; 10514 10515 u8 error_counter_lane14[0x20]; 10516 10517 u8 error_counter_lane15[0x20]; 10518 10519 u8 reserved_at_240[0x580]; 10520 }; 10521 10522 struct mlx5_ifc_pcie_perf_counters_bits { 10523 u8 life_time_counter_high[0x20]; 10524 10525 u8 life_time_counter_low[0x20]; 10526 10527 u8 rx_errors[0x20]; 10528 10529 u8 tx_errors[0x20]; 10530 10531 u8 l0_to_recovery_eieos[0x20]; 10532 10533 u8 l0_to_recovery_ts[0x20]; 10534 10535 u8 l0_to_recovery_framing[0x20]; 10536 10537 u8 l0_to_recovery_retrain[0x20]; 10538 10539 u8 crc_error_dllp[0x20]; 10540 10541 u8 crc_error_tlp[0x20]; 10542 10543 u8 tx_overflow_buffer_pkt[0x40]; 10544 10545 u8 outbound_stalled_reads[0x20]; 10546 10547 u8 outbound_stalled_writes[0x20]; 10548 10549 u8 outbound_stalled_reads_events[0x20]; 10550 10551 u8 outbound_stalled_writes_events[0x20]; 10552 10553 u8 tx_overflow_buffer_marked_pkt[0x40]; 10554 10555 u8 reserved_at_240[0x580]; 10556 }; 10557 10558 struct mlx5_ifc_pcie_perf_counters_ext_bits { 10559 u8 reserved_at_0[0x40]; 10560 10561 u8 rx_errors[0x20]; 10562 10563 u8 tx_errors[0x20]; 10564 10565 u8 reserved_at_80[0xc0]; 10566 10567 u8 tx_overflow_buffer_pkt[0x40]; 10568 10569 u8 outbound_stalled_reads[0x20]; 10570 10571 u8 outbound_stalled_writes[0x20]; 10572 10573 u8 outbound_stalled_reads_events[0x20]; 10574 10575 u8 outbound_stalled_writes_events[0x20]; 10576 10577 u8 tx_overflow_buffer_marked_pkt[0x40]; 10578 10579 u8 reserved_at_240[0x580]; 10580 }; 10581 10582 struct mlx5_ifc_pcie_timers_states_bits { 10583 u8 life_time_counter_high[0x20]; 10584 10585 u8 life_time_counter_low[0x20]; 10586 10587 u8 time_to_boot_image_start[0x20]; 10588 10589 u8 time_to_link_image[0x20]; 10590 10591 u8 calibration_time[0x20]; 10592 10593 u8 time_to_first_perst[0x20]; 10594 10595 u8 time_to_detect_state[0x20]; 10596 10597 u8 time_to_l0[0x20]; 10598 10599 u8 time_to_crs_en[0x20]; 10600 10601 u8 time_to_plastic_image_start[0x20]; 10602 10603 u8 time_to_iron_image_start[0x20]; 10604 10605 u8 perst_handler[0x20]; 10606 10607 u8 times_in_l1[0x20]; 10608 10609 u8 times_in_l23[0x20]; 10610 10611 u8 dl_down[0x20]; 10612 10613 u8 config_cycle1usec[0x20]; 10614 10615 u8 config_cycle2to7usec[0x20]; 10616 10617 u8 config_cycle8to15usec[0x20]; 10618 10619 u8 config_cycle16to63usec[0x20]; 10620 10621 u8 config_cycle64usec[0x20]; 10622 10623 u8 correctable_err_msg_sent[0x20]; 10624 10625 u8 non_fatal_err_msg_sent[0x20]; 10626 10627 u8 fatal_err_msg_sent[0x20]; 10628 10629 u8 reserved_at_2e0[0x4e0]; 10630 }; 10631 10632 struct mlx5_ifc_pcie_timers_states_ext_bits { 10633 u8 reserved_at_0[0x40]; 10634 10635 u8 time_to_boot_image_start[0x20]; 10636 10637 u8 time_to_link_image[0x20]; 10638 10639 u8 calibration_time[0x20]; 10640 10641 u8 time_to_first_perst[0x20]; 10642 10643 u8 time_to_detect_state[0x20]; 10644 10645 u8 time_to_l0[0x20]; 10646 10647 u8 time_to_crs_en[0x20]; 10648 10649 u8 time_to_plastic_image_start[0x20]; 10650 10651 u8 time_to_iron_image_start[0x20]; 10652 10653 u8 perst_handler[0x20]; 10654 10655 u8 times_in_l1[0x20]; 10656 10657 u8 times_in_l23[0x20]; 10658 10659 u8 dl_down[0x20]; 10660 10661 u8 config_cycle1usec[0x20]; 10662 10663 u8 config_cycle2to7usec[0x20]; 10664 10665 u8 config_cycle8to15usec[0x20]; 10666 10667 u8 config_cycle16to63usec[0x20]; 10668 10669 u8 config_cycle64usec[0x20]; 10670 10671 u8 correctable_err_msg_sent[0x20]; 10672 10673 u8 non_fatal_err_msg_sent[0x20]; 10674 10675 u8 fatal_err_msg_sent[0x20]; 10676 10677 u8 reserved_at_2e0[0x4e0]; 10678 }; 10679 10680 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits { 10681 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters; 10682 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters; 10683 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states; 10684 u8 reserved_at_0[0x7c0]; 10685 }; 10686 10687 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits { 10688 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext; 10689 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext; 10690 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext; 10691 u8 reserved_at_0[0x7c0]; 10692 }; 10693 10694 struct mlx5_ifc_mpcnt_reg_bits { 10695 u8 reserved_at_0[0x2]; 10696 u8 depth[0x6]; 10697 u8 pcie_index[0x8]; 10698 u8 node[0x8]; 10699 u8 reserved_at_18[0x2]; 10700 u8 grp[0x6]; 10701 10702 u8 clr[0x1]; 10703 u8 reserved_at_21[0x1f]; 10704 10705 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set; 10706 }; 10707 10708 struct mlx5_ifc_mpcnt_reg_ext_bits { 10709 u8 reserved_at_0[0x2]; 10710 u8 depth[0x6]; 10711 u8 pcie_index[0x8]; 10712 u8 node[0x8]; 10713 u8 reserved_at_18[0x2]; 10714 u8 grp[0x6]; 10715 10716 u8 clr[0x1]; 10717 u8 reserved_at_21[0x1f]; 10718 10719 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set; 10720 }; 10721 10722 struct mlx5_ifc_monitor_opcodes_layout_bits { 10723 u8 reserved_at_0[0x10]; 10724 u8 monitor_opcode[0x10]; 10725 }; 10726 10727 union mlx5_ifc_pddr_status_opcode_bits { 10728 struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes; 10729 u8 reserved_at_0[0x20]; 10730 }; 10731 10732 struct mlx5_ifc_troubleshooting_info_page_layout_bits { 10733 u8 reserved_at_0[0x10]; 10734 u8 group_opcode[0x10]; 10735 10736 union mlx5_ifc_pddr_status_opcode_bits status_opcode; 10737 10738 u8 user_feedback_data[0x10]; 10739 u8 user_feedback_index[0x10]; 10740 10741 u8 status_message[0x760]; 10742 }; 10743 10744 union mlx5_ifc_pddr_page_data_bits { 10745 struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page; 10746 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 10747 u8 reserved_at_0[0x7c0]; 10748 }; 10749 10750 struct mlx5_ifc_pddr_reg_bits { 10751 u8 reserved_at_0[0x8]; 10752 u8 local_port[0x8]; 10753 u8 pnat[0x2]; 10754 u8 reserved_at_12[0xe]; 10755 10756 u8 reserved_at_20[0x18]; 10757 u8 page_select[0x8]; 10758 10759 union mlx5_ifc_pddr_page_data_bits page_data; 10760 }; 10761 10762 enum { 10763 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050, 10764 MLX5_MPEIN_PWR_STATUS_INVALID = 0, 10765 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1, 10766 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2, 10767 }; 10768 10769 struct mlx5_ifc_mpein_reg_bits { 10770 u8 reserved_at_0[0x2]; 10771 u8 depth[0x6]; 10772 u8 pcie_index[0x8]; 10773 u8 node[0x8]; 10774 u8 reserved_at_18[0x8]; 10775 10776 u8 capability_mask[0x20]; 10777 10778 u8 reserved_at_40[0x8]; 10779 u8 link_width_enabled[0x8]; 10780 u8 link_speed_enabled[0x10]; 10781 10782 u8 lane0_physical_position[0x8]; 10783 u8 link_width_active[0x8]; 10784 u8 link_speed_active[0x10]; 10785 10786 u8 num_of_pfs[0x10]; 10787 u8 num_of_vfs[0x10]; 10788 10789 u8 bdf0[0x10]; 10790 u8 reserved_at_b0[0x10]; 10791 10792 u8 max_read_request_size[0x4]; 10793 u8 max_payload_size[0x4]; 10794 u8 reserved_at_c8[0x5]; 10795 u8 pwr_status[0x3]; 10796 u8 port_type[0x4]; 10797 u8 reserved_at_d4[0xb]; 10798 u8 lane_reversal[0x1]; 10799 10800 u8 reserved_at_e0[0x14]; 10801 u8 pci_power[0xc]; 10802 10803 u8 reserved_at_100[0x20]; 10804 10805 u8 device_status[0x10]; 10806 u8 port_state[0x8]; 10807 u8 reserved_at_138[0x8]; 10808 10809 u8 reserved_at_140[0x10]; 10810 u8 receiver_detect_result[0x10]; 10811 10812 u8 reserved_at_160[0x20]; 10813 }; 10814 10815 struct mlx5_ifc_mpein_reg_ext_bits { 10816 u8 reserved_at_0[0x2]; 10817 u8 depth[0x6]; 10818 u8 pcie_index[0x8]; 10819 u8 node[0x8]; 10820 u8 reserved_at_18[0x8]; 10821 10822 u8 reserved_at_20[0x20]; 10823 10824 u8 reserved_at_40[0x8]; 10825 u8 link_width_enabled[0x8]; 10826 u8 link_speed_enabled[0x10]; 10827 10828 u8 lane0_physical_position[0x8]; 10829 u8 link_width_active[0x8]; 10830 u8 link_speed_active[0x10]; 10831 10832 u8 num_of_pfs[0x10]; 10833 u8 num_of_vfs[0x10]; 10834 10835 u8 bdf0[0x10]; 10836 u8 reserved_at_b0[0x10]; 10837 10838 u8 max_read_request_size[0x4]; 10839 u8 max_payload_size[0x4]; 10840 u8 reserved_at_c8[0x5]; 10841 u8 pwr_status[0x3]; 10842 u8 port_type[0x4]; 10843 u8 reserved_at_d4[0xb]; 10844 u8 lane_reversal[0x1]; 10845 }; 10846 10847 struct mlx5_ifc_mcqi_cap_bits { 10848 u8 supported_info_bitmask[0x20]; 10849 10850 u8 component_size[0x20]; 10851 10852 u8 max_component_size[0x20]; 10853 10854 u8 log_mcda_word_size[0x4]; 10855 u8 reserved_at_64[0xc]; 10856 u8 mcda_max_write_size[0x10]; 10857 10858 u8 rd_en[0x1]; 10859 u8 reserved_at_81[0x1]; 10860 u8 match_chip_id[0x1]; 10861 u8 match_psid[0x1]; 10862 u8 check_user_timestamp[0x1]; 10863 u8 match_base_guid_mac[0x1]; 10864 u8 reserved_at_86[0x1a]; 10865 }; 10866 10867 struct mlx5_ifc_mcqi_reg_bits { 10868 u8 read_pending_component[0x1]; 10869 u8 reserved_at_1[0xf]; 10870 u8 component_index[0x10]; 10871 10872 u8 reserved_at_20[0x20]; 10873 10874 u8 reserved_at_40[0x1b]; 10875 u8 info_type[0x5]; 10876 10877 u8 info_size[0x20]; 10878 10879 u8 offset[0x20]; 10880 10881 u8 reserved_at_a0[0x10]; 10882 u8 data_size[0x10]; 10883 10884 u8 data[0][0x20]; 10885 }; 10886 10887 struct mlx5_ifc_mcc_reg_bits { 10888 u8 reserved_at_0[0x4]; 10889 u8 time_elapsed_since_last_cmd[0xc]; 10890 u8 reserved_at_10[0x8]; 10891 u8 instruction[0x8]; 10892 10893 u8 reserved_at_20[0x10]; 10894 u8 component_index[0x10]; 10895 10896 u8 reserved_at_40[0x8]; 10897 u8 update_handle[0x18]; 10898 10899 u8 handle_owner_type[0x4]; 10900 u8 handle_owner_host_id[0x4]; 10901 u8 reserved_at_68[0x1]; 10902 u8 control_progress[0x7]; 10903 u8 error_code[0x8]; 10904 u8 reserved_at_78[0x4]; 10905 u8 control_state[0x4]; 10906 10907 u8 component_size[0x20]; 10908 10909 u8 reserved_at_a0[0x60]; 10910 }; 10911 10912 struct mlx5_ifc_mcda_reg_bits { 10913 u8 reserved_at_0[0x8]; 10914 u8 update_handle[0x18]; 10915 10916 u8 offset[0x20]; 10917 10918 u8 reserved_at_40[0x10]; 10919 u8 size[0x10]; 10920 10921 u8 reserved_at_60[0x20]; 10922 10923 u8 data[0][0x20]; 10924 }; 10925 10926 union mlx5_ifc_ports_control_registers_document_bits { 10927 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 10928 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10929 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10930 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10931 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10932 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10933 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10934 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10935 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10936 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 10937 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 10938 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10939 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 10940 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10941 struct mlx5_ifc_paos_reg_bits paos_reg; 10942 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 10943 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10944 struct mlx5_ifc_peir_reg_bits peir_reg; 10945 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10946 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10947 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 10948 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 10949 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 10950 struct mlx5_ifc_phrr_reg_bits phrr_reg; 10951 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10952 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10953 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10954 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10955 struct mlx5_ifc_plib_reg_bits plib_reg; 10956 struct mlx5_ifc_pll_status_data_bits pll_status_data; 10957 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10958 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10959 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10960 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10961 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10962 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10963 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10964 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10965 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10966 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10967 struct mlx5_ifc_ppll_reg_bits ppll_reg; 10968 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10969 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10970 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10971 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10972 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10973 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10974 struct mlx5_ifc_pude_reg_bits pude_reg; 10975 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10976 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10977 struct mlx5_ifc_slrp_reg_bits slrp_reg; 10978 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10979 u8 reserved_0[0x7880]; 10980 }; 10981 10982 union mlx5_ifc_debug_enhancements_document_bits { 10983 struct mlx5_ifc_health_buffer_bits health_buffer; 10984 u8 reserved_0[0x200]; 10985 }; 10986 10987 union mlx5_ifc_no_dram_nic_document_bits { 10988 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 10989 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 10990 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 10991 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 10992 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 10993 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 10994 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 10995 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 10996 u8 reserved_0[0x3160]; 10997 }; 10998 10999 union mlx5_ifc_uplink_pci_interface_document_bits { 11000 struct mlx5_ifc_initial_seg_bits initial_seg; 11001 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 11002 u8 reserved_0[0x20120]; 11003 }; 11004 11005 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11006 u8 e[0x1]; 11007 u8 reserved_at_01[0x0b]; 11008 u8 prio[0x04]; 11009 }; 11010 11011 struct mlx5_ifc_qpdpm_reg_bits { 11012 u8 reserved_at_0[0x8]; 11013 u8 local_port[0x8]; 11014 u8 reserved_at_10[0x10]; 11015 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11016 }; 11017 11018 struct mlx5_ifc_qpts_reg_bits { 11019 u8 reserved_at_0[0x8]; 11020 u8 local_port[0x8]; 11021 u8 reserved_at_10[0x2d]; 11022 u8 trust_state[0x3]; 11023 }; 11024 11025 struct mlx5_ifc_mfrl_reg_bits { 11026 u8 reserved_at_0[0x38]; 11027 u8 reset_level[0x8]; 11028 }; 11029 11030 enum { 11031 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009, 11032 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109, 11033 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a, 11034 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b, 11035 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f, 11036 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b, 11037 MLX5_MAX_TEMPERATURE = 16, 11038 }; 11039 11040 struct mlx5_ifc_mtbr_temp_record_bits { 11041 u8 max_temperature[0x10]; 11042 u8 temperature[0x10]; 11043 }; 11044 11045 struct mlx5_ifc_mtbr_reg_bits { 11046 u8 reserved_at_0[0x14]; 11047 u8 base_sensor_index[0xc]; 11048 11049 u8 reserved_at_20[0x18]; 11050 u8 num_rec[0x8]; 11051 11052 u8 reserved_at_40[0x40]; 11053 11054 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 11055 }; 11056 11057 struct mlx5_ifc_mtbr_reg_ext_bits { 11058 u8 reserved_at_0[0x14]; 11059 u8 base_sensor_index[0xc]; 11060 11061 u8 reserved_at_20[0x18]; 11062 u8 num_rec[0x8]; 11063 11064 u8 reserved_at_40[0x40]; 11065 11066 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 11067 }; 11068 11069 struct mlx5_ifc_mtcap_bits { 11070 u8 reserved_at_0[0x19]; 11071 u8 sensor_count[0x7]; 11072 11073 u8 reserved_at_20[0x19]; 11074 u8 internal_sensor_count[0x7]; 11075 11076 u8 sensor_map[0x40]; 11077 }; 11078 11079 struct mlx5_ifc_mtcap_ext_bits { 11080 u8 reserved_at_0[0x19]; 11081 u8 sensor_count[0x7]; 11082 11083 u8 reserved_at_20[0x20]; 11084 11085 u8 sensor_map[0x40]; 11086 }; 11087 11088 struct mlx5_ifc_mtecr_bits { 11089 u8 reserved_at_0[0x4]; 11090 u8 last_sensor[0xc]; 11091 u8 reserved_at_10[0x4]; 11092 u8 sensor_count[0xc]; 11093 11094 u8 reserved_at_20[0x19]; 11095 u8 internal_sensor_count[0x7]; 11096 11097 u8 sensor_map_0[0x20]; 11098 11099 u8 reserved_at_60[0x2a0]; 11100 }; 11101 11102 struct mlx5_ifc_mtecr_ext_bits { 11103 u8 reserved_at_0[0x4]; 11104 u8 last_sensor[0xc]; 11105 u8 reserved_at_10[0x4]; 11106 u8 sensor_count[0xc]; 11107 11108 u8 reserved_at_20[0x20]; 11109 11110 u8 sensor_map_0[0x20]; 11111 11112 u8 reserved_at_60[0x2a0]; 11113 }; 11114 11115 struct mlx5_ifc_mtewe_bits { 11116 u8 reserved_at_0[0x4]; 11117 u8 last_sensor[0xc]; 11118 u8 reserved_at_10[0x4]; 11119 u8 sensor_count[0xc]; 11120 11121 u8 sensor_warning_0[0x20]; 11122 11123 u8 reserved_at_40[0x2a0]; 11124 }; 11125 11126 struct mlx5_ifc_mtewe_ext_bits { 11127 u8 reserved_at_0[0x4]; 11128 u8 last_sensor[0xc]; 11129 u8 reserved_at_10[0x4]; 11130 u8 sensor_count[0xc]; 11131 11132 u8 sensor_warning_0[0x20]; 11133 11134 u8 reserved_at_40[0x2a0]; 11135 }; 11136 11137 struct mlx5_ifc_mtmp_bits { 11138 u8 reserved_at_0[0x14]; 11139 u8 sensor_index[0xc]; 11140 11141 u8 reserved_at_20[0x10]; 11142 u8 temperature[0x10]; 11143 11144 u8 mte[0x1]; 11145 u8 mtr[0x1]; 11146 u8 reserved_at_42[0xe]; 11147 u8 max_temperature[0x10]; 11148 11149 u8 tee[0x2]; 11150 u8 reserved_at_62[0xe]; 11151 u8 temperature_threshold_hi[0x10]; 11152 11153 u8 reserved_at_80[0x10]; 11154 u8 temperature_threshold_lo[0x10]; 11155 11156 u8 reserved_at_a0[0x20]; 11157 11158 u8 sensor_name_hi[0x20]; 11159 11160 u8 sensor_name_lo[0x20]; 11161 }; 11162 11163 struct mlx5_ifc_mtmp_ext_bits { 11164 u8 reserved_at_0[0x14]; 11165 u8 sensor_index[0xc]; 11166 11167 u8 reserved_at_20[0x10]; 11168 u8 temperature[0x10]; 11169 11170 u8 mte[0x1]; 11171 u8 mtr[0x1]; 11172 u8 reserved_at_42[0xe]; 11173 u8 max_temperature[0x10]; 11174 11175 u8 tee[0x2]; 11176 u8 reserved_at_62[0xe]; 11177 u8 temperature_threshold_hi[0x10]; 11178 11179 u8 reserved_at_80[0x10]; 11180 u8 temperature_threshold_lo[0x10]; 11181 11182 u8 reserved_at_a0[0x20]; 11183 11184 u8 sensor_name_hi[0x20]; 11185 11186 u8 sensor_name_lo[0x20]; 11187 }; 11188 11189 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 11190 u8 opcode[0x10]; 11191 u8 uid[0x10]; 11192 11193 u8 vhca_tunnel_id[0x10]; 11194 u8 obj_type[0x10]; 11195 11196 u8 obj_id[0x20]; 11197 11198 u8 reserved_at_60[0x20]; 11199 }; 11200 11201 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 11202 u8 status[0x8]; 11203 u8 reserved_at_8[0x18]; 11204 11205 u8 syndrome[0x20]; 11206 11207 u8 obj_id[0x20]; 11208 11209 u8 reserved_at_60[0x20]; 11210 }; 11211 11212 struct mlx5_ifc_umem_bits { 11213 u8 reserved_at_0[0x80]; 11214 11215 u8 reserved_at_80[0x1b]; 11216 u8 log_page_size[0x5]; 11217 11218 u8 page_offset[0x20]; 11219 11220 u8 num_of_mtt[0x40]; 11221 11222 struct mlx5_ifc_mtt_bits mtt[0]; 11223 }; 11224 11225 struct mlx5_ifc_uctx_bits { 11226 u8 cap[0x20]; 11227 11228 u8 reserved_at_20[0x160]; 11229 }; 11230 11231 struct mlx5_ifc_create_umem_in_bits { 11232 u8 opcode[0x10]; 11233 u8 uid[0x10]; 11234 11235 u8 reserved_at_20[0x10]; 11236 u8 op_mod[0x10]; 11237 11238 u8 reserved_at_40[0x40]; 11239 11240 struct mlx5_ifc_umem_bits umem; 11241 }; 11242 11243 struct mlx5_ifc_create_uctx_in_bits { 11244 u8 opcode[0x10]; 11245 u8 reserved_at_10[0x10]; 11246 11247 u8 reserved_at_20[0x10]; 11248 u8 op_mod[0x10]; 11249 11250 u8 reserved_at_40[0x40]; 11251 11252 struct mlx5_ifc_uctx_bits uctx; 11253 }; 11254 11255 struct mlx5_ifc_destroy_uctx_in_bits { 11256 u8 opcode[0x10]; 11257 u8 reserved_at_10[0x10]; 11258 11259 u8 reserved_at_20[0x10]; 11260 u8 op_mod[0x10]; 11261 11262 u8 reserved_at_40[0x10]; 11263 u8 uid[0x10]; 11264 11265 u8 reserved_at_60[0x20]; 11266 }; 11267 11268 struct mlx5_ifc_mtrc_string_db_param_bits { 11269 u8 string_db_base_address[0x20]; 11270 11271 u8 reserved_at_20[0x8]; 11272 u8 string_db_size[0x18]; 11273 }; 11274 11275 struct mlx5_ifc_mtrc_cap_bits { 11276 u8 trace_owner[0x1]; 11277 u8 trace_to_memory[0x1]; 11278 u8 reserved_at_2[0x4]; 11279 u8 trc_ver[0x2]; 11280 u8 reserved_at_8[0x14]; 11281 u8 num_string_db[0x4]; 11282 11283 u8 first_string_trace[0x8]; 11284 u8 num_string_trace[0x8]; 11285 u8 reserved_at_30[0x28]; 11286 11287 u8 log_max_trace_buffer_size[0x8]; 11288 11289 u8 reserved_at_60[0x20]; 11290 11291 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11292 11293 u8 reserved_at_280[0x180]; 11294 }; 11295 11296 struct mlx5_ifc_mtrc_conf_bits { 11297 u8 reserved_at_0[0x1c]; 11298 u8 trace_mode[0x4]; 11299 u8 reserved_at_20[0x18]; 11300 u8 log_trace_buffer_size[0x8]; 11301 u8 trace_mkey[0x20]; 11302 u8 reserved_at_60[0x3a0]; 11303 }; 11304 11305 struct mlx5_ifc_mtrc_stdb_bits { 11306 u8 string_db_index[0x4]; 11307 u8 reserved_at_4[0x4]; 11308 u8 read_size[0x18]; 11309 u8 start_offset[0x20]; 11310 u8 string_db_data[0]; 11311 }; 11312 11313 struct mlx5_ifc_mtrc_ctrl_bits { 11314 u8 trace_status[0x2]; 11315 u8 reserved_at_2[0x2]; 11316 u8 arm_event[0x1]; 11317 u8 reserved_at_5[0xb]; 11318 u8 modify_field_select[0x10]; 11319 u8 reserved_at_20[0x2b]; 11320 u8 current_timestamp52_32[0x15]; 11321 u8 current_timestamp31_0[0x20]; 11322 u8 reserved_at_80[0x180]; 11323 }; 11324 11325 struct mlx5_ifc_affiliated_event_header_bits { 11326 u8 reserved_at_0[0x10]; 11327 u8 obj_type[0x10]; 11328 11329 u8 obj_id[0x20]; 11330 }; 11331 11332 #endif /* MLX5_IFC_H */ 11333