1 /*- 2 * Copyright (c) 2013-2021, Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/module.h> 29 #include <rdma/ib_umem.h> 30 #include <rdma/ib_cache.h> 31 #include <rdma/ib_user_verbs.h> 32 #include <rdma/uverbs_ioctl.h> 33 #include "mlx5_ib.h" 34 35 /* not supported currently */ 36 static int wq_signature; 37 38 enum { 39 MLX5_IB_ACK_REQ_FREQ = 8, 40 }; 41 42 enum { 43 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 44 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 45 MLX5_IB_LINK_TYPE_IB = 0, 46 MLX5_IB_LINK_TYPE_ETH = 1 47 }; 48 49 enum { 50 MLX5_IB_SQ_STRIDE = 6, 51 }; 52 53 static const u32 mlx5_ib_opcode[] = { 54 [IB_WR_SEND] = MLX5_OPCODE_SEND, 55 [IB_WR_LSO] = MLX5_OPCODE_LSO, 56 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 57 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 58 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 59 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 60 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 61 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 62 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 63 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 64 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 65 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 66 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 67 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 68 }; 69 70 struct mlx5_wqe_eth_pad { 71 u8 rsvd0[16]; 72 }; 73 74 enum raw_qp_set_mask_map { 75 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 76 }; 77 78 struct mlx5_modify_raw_qp_param { 79 u16 operation; 80 81 u32 set_mask; /* raw_qp_set_mask_map */ 82 u8 rq_q_ctr_id; 83 }; 84 85 static void get_cqs(enum ib_qp_type qp_type, 86 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 87 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 88 89 static int is_qp0(enum ib_qp_type qp_type) 90 { 91 return qp_type == IB_QPT_SMI; 92 } 93 94 static int is_sqp(enum ib_qp_type qp_type) 95 { 96 return is_qp0(qp_type) || is_qp1(qp_type); 97 } 98 99 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 100 { 101 return mlx5_buf_offset(&qp->buf, offset); 102 } 103 104 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 105 { 106 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 107 } 108 109 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 110 { 111 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 112 } 113 114 /** 115 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 116 * 117 * @qp: QP to copy from. 118 * @send: copy from the send queue when non-zero, use the receive queue 119 * otherwise. 120 * @wqe_index: index to start copying from. For send work queues, the 121 * wqe_index is in units of MLX5_SEND_WQE_BB. 122 * For receive work queue, it is the number of work queue 123 * element in the queue. 124 * @buffer: destination buffer. 125 * @length: maximum number of bytes to copy. 126 * 127 * Copies at least a single WQE, but may copy more data. 128 * 129 * Return: the number of bytes copied, or an error code. 130 */ 131 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 132 void *buffer, u32 length, 133 struct mlx5_ib_qp_base *base) 134 { 135 struct ib_device *ibdev = qp->ibqp.device; 136 struct mlx5_ib_dev *dev = to_mdev(ibdev); 137 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 138 size_t offset; 139 size_t wq_end; 140 struct ib_umem *umem = base->ubuffer.umem; 141 u32 first_copy_length; 142 int wqe_length; 143 int ret; 144 145 if (wq->wqe_cnt == 0) { 146 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 147 qp->ibqp.qp_type); 148 return -EINVAL; 149 } 150 151 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 152 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 153 154 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 155 return -EINVAL; 156 157 if (offset > umem->length || 158 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 159 return -EINVAL; 160 161 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 162 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 163 if (ret) 164 return ret; 165 166 if (send) { 167 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 168 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 169 170 wqe_length = ds * MLX5_WQE_DS_UNITS; 171 } else { 172 wqe_length = 1 << wq->wqe_shift; 173 } 174 175 if (wqe_length <= first_copy_length) 176 return first_copy_length; 177 178 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 179 wqe_length - first_copy_length); 180 if (ret) 181 return ret; 182 183 return wqe_length; 184 } 185 186 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 187 { 188 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 189 struct ib_event event; 190 191 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 192 /* This event is only valid for trans_qps */ 193 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 194 } 195 196 if (ibqp->event_handler) { 197 event.device = ibqp->device; 198 event.element.qp = ibqp; 199 switch (type) { 200 case MLX5_EVENT_TYPE_PATH_MIG: 201 event.event = IB_EVENT_PATH_MIG; 202 break; 203 case MLX5_EVENT_TYPE_COMM_EST: 204 event.event = IB_EVENT_COMM_EST; 205 break; 206 case MLX5_EVENT_TYPE_SQ_DRAINED: 207 event.event = IB_EVENT_SQ_DRAINED; 208 break; 209 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 210 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 211 break; 212 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 213 event.event = IB_EVENT_QP_FATAL; 214 break; 215 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 216 event.event = IB_EVENT_PATH_MIG_ERR; 217 break; 218 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 219 event.event = IB_EVENT_QP_REQ_ERR; 220 break; 221 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 222 event.event = IB_EVENT_QP_ACCESS_ERR; 223 break; 224 default: 225 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 226 return; 227 } 228 229 ibqp->event_handler(&event, ibqp->qp_context); 230 } 231 } 232 233 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 234 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 235 { 236 int wqe_size; 237 int wq_size; 238 239 /* Sanity check RQ size before proceeding */ 240 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 241 return -EINVAL; 242 243 if (!has_rq) { 244 qp->rq.max_gs = 0; 245 qp->rq.wqe_cnt = 0; 246 qp->rq.wqe_shift = 0; 247 cap->max_recv_wr = 0; 248 cap->max_recv_sge = 0; 249 } else { 250 if (ucmd) { 251 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 252 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 253 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 254 qp->rq.max_post = qp->rq.wqe_cnt; 255 } else { 256 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 257 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 258 wqe_size = roundup_pow_of_two(wqe_size); 259 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 260 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 261 qp->rq.wqe_cnt = wq_size / wqe_size; 262 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 263 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 264 wqe_size, 265 MLX5_CAP_GEN(dev->mdev, 266 max_wqe_sz_rq)); 267 return -EINVAL; 268 } 269 qp->rq.wqe_shift = ilog2(wqe_size); 270 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 271 qp->rq.max_post = qp->rq.wqe_cnt; 272 } 273 } 274 275 return 0; 276 } 277 278 static int sq_overhead(struct ib_qp_init_attr *attr) 279 { 280 int size = 0; 281 282 switch (attr->qp_type) { 283 case IB_QPT_XRC_INI: 284 size += sizeof(struct mlx5_wqe_xrc_seg); 285 /* fall through */ 286 case IB_QPT_RC: 287 size += sizeof(struct mlx5_wqe_ctrl_seg) + 288 max(sizeof(struct mlx5_wqe_atomic_seg) + 289 sizeof(struct mlx5_wqe_raddr_seg), 290 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 291 sizeof(struct mlx5_mkey_seg)); 292 break; 293 294 case IB_QPT_XRC_TGT: 295 return 0; 296 297 case IB_QPT_UC: 298 size += sizeof(struct mlx5_wqe_ctrl_seg) + 299 max(sizeof(struct mlx5_wqe_raddr_seg), 300 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 301 sizeof(struct mlx5_mkey_seg)); 302 break; 303 304 case IB_QPT_UD: 305 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 306 size += sizeof(struct mlx5_wqe_eth_pad) + 307 sizeof(struct mlx5_wqe_eth_seg); 308 /* fall through */ 309 case IB_QPT_SMI: 310 case MLX5_IB_QPT_HW_GSI: 311 size += sizeof(struct mlx5_wqe_ctrl_seg) + 312 sizeof(struct mlx5_wqe_datagram_seg); 313 break; 314 315 case MLX5_IB_QPT_REG_UMR: 316 size += sizeof(struct mlx5_wqe_ctrl_seg) + 317 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 318 sizeof(struct mlx5_mkey_seg); 319 break; 320 321 default: 322 return -EINVAL; 323 } 324 325 return size; 326 } 327 328 static int calc_send_wqe(struct ib_qp_init_attr *attr) 329 { 330 int inl_size = 0; 331 int size; 332 333 size = sq_overhead(attr); 334 if (size < 0) 335 return size; 336 337 if (attr->cap.max_inline_data) { 338 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 339 attr->cap.max_inline_data; 340 } 341 342 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 343 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 344 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 345 return MLX5_SIG_WQE_SIZE; 346 else 347 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 348 } 349 350 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 351 { 352 int max_sge; 353 354 if (attr->qp_type == IB_QPT_RC) 355 max_sge = (min_t(int, wqe_size, 512) - 356 sizeof(struct mlx5_wqe_ctrl_seg) - 357 sizeof(struct mlx5_wqe_raddr_seg)) / 358 sizeof(struct mlx5_wqe_data_seg); 359 else if (attr->qp_type == IB_QPT_XRC_INI) 360 max_sge = (min_t(int, wqe_size, 512) - 361 sizeof(struct mlx5_wqe_ctrl_seg) - 362 sizeof(struct mlx5_wqe_xrc_seg) - 363 sizeof(struct mlx5_wqe_raddr_seg)) / 364 sizeof(struct mlx5_wqe_data_seg); 365 else 366 max_sge = (wqe_size - sq_overhead(attr)) / 367 sizeof(struct mlx5_wqe_data_seg); 368 369 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 370 sizeof(struct mlx5_wqe_data_seg)); 371 } 372 373 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 374 struct mlx5_ib_qp *qp) 375 { 376 int wqe_size; 377 int wq_size; 378 379 if (!attr->cap.max_send_wr) 380 return 0; 381 382 wqe_size = calc_send_wqe(attr); 383 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 384 if (wqe_size < 0) 385 return wqe_size; 386 387 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 388 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 389 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 390 return -EINVAL; 391 } 392 393 qp->max_inline_data = wqe_size - sq_overhead(attr) - 394 sizeof(struct mlx5_wqe_inline_seg); 395 attr->cap.max_inline_data = qp->max_inline_data; 396 397 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 398 qp->signature_en = true; 399 400 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 401 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 402 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 403 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 404 qp->sq.wqe_cnt, 405 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 406 return -ENOMEM; 407 } 408 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 409 qp->sq.max_gs = get_send_sge(attr, wqe_size); 410 if (qp->sq.max_gs < attr->cap.max_send_sge) 411 return -ENOMEM; 412 413 attr->cap.max_send_sge = qp->sq.max_gs; 414 qp->sq.max_post = wq_size / wqe_size; 415 attr->cap.max_send_wr = qp->sq.max_post; 416 417 return wq_size; 418 } 419 420 static int set_user_buf_size(struct mlx5_ib_dev *dev, 421 struct mlx5_ib_qp *qp, 422 struct mlx5_ib_create_qp *ucmd, 423 struct mlx5_ib_qp_base *base, 424 struct ib_qp_init_attr *attr) 425 { 426 int desc_sz = 1 << qp->sq.wqe_shift; 427 428 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 429 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 430 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 431 return -EINVAL; 432 } 433 434 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 435 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 436 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 437 return -EINVAL; 438 } 439 440 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 441 442 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 443 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 444 qp->sq.wqe_cnt, 445 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 446 return -EINVAL; 447 } 448 449 if (attr->qp_type == IB_QPT_RAW_PACKET) { 450 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 451 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 452 } else { 453 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 454 (qp->sq.wqe_cnt << 6); 455 } 456 457 return 0; 458 } 459 460 static int qp_has_rq(struct ib_qp_init_attr *attr) 461 { 462 if (attr->qp_type == IB_QPT_XRC_INI || 463 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 464 attr->qp_type == MLX5_IB_QPT_REG_UMR || 465 !attr->cap.max_recv_wr) 466 return 0; 467 468 return 1; 469 } 470 471 enum { 472 /* this is the first blue flame register in the array of bfregs assigned 473 * to a processes. Since we do not use it for blue flame but rather 474 * regular 64 bit doorbells, we do not need a lock for maintaiing 475 * "odd/even" order 476 */ 477 NUM_NON_BLUE_FLAME_BFREGS = 1, 478 }; 479 480 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 481 { 482 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 483 } 484 485 static int num_med_bfreg(struct mlx5_ib_dev *dev, 486 struct mlx5_bfreg_info *bfregi) 487 { 488 int n; 489 490 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 491 NUM_NON_BLUE_FLAME_BFREGS; 492 493 return n >= 0 ? n : 0; 494 } 495 496 static int first_med_bfreg(struct mlx5_ib_dev *dev, 497 struct mlx5_bfreg_info *bfregi) 498 { 499 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 500 } 501 502 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 503 struct mlx5_bfreg_info *bfregi) 504 { 505 int med; 506 507 med = num_med_bfreg(dev, bfregi); 508 return ++med; 509 } 510 511 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 512 struct mlx5_bfreg_info *bfregi) 513 { 514 int i; 515 516 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 517 if (!bfregi->count[i]) { 518 bfregi->count[i]++; 519 return i; 520 } 521 } 522 523 return -ENOMEM; 524 } 525 526 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 527 struct mlx5_bfreg_info *bfregi) 528 { 529 int minidx = first_med_bfreg(dev, bfregi); 530 int i; 531 532 if (minidx < 0) 533 return minidx; 534 535 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 536 if (bfregi->count[i] < bfregi->count[minidx]) 537 minidx = i; 538 if (!bfregi->count[minidx]) 539 break; 540 } 541 542 bfregi->count[minidx]++; 543 return minidx; 544 } 545 546 static int alloc_bfreg(struct mlx5_ib_dev *dev, 547 struct mlx5_bfreg_info *bfregi) 548 { 549 int bfregn = -ENOMEM; 550 551 if (bfregi->lib_uar_dyn) 552 return -EINVAL; 553 554 mutex_lock(&bfregi->lock); 555 if (bfregi->ver >= 2) { 556 bfregn = alloc_high_class_bfreg(dev, bfregi); 557 if (bfregn < 0) 558 bfregn = alloc_med_class_bfreg(dev, bfregi); 559 } 560 561 if (bfregn < 0) { 562 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 563 bfregn = 0; 564 bfregi->count[bfregn]++; 565 } 566 mutex_unlock(&bfregi->lock); 567 568 return bfregn; 569 } 570 571 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 572 { 573 mutex_lock(&bfregi->lock); 574 bfregi->count[bfregn]--; 575 mutex_unlock(&bfregi->lock); 576 } 577 578 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 579 { 580 switch (state) { 581 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 582 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 583 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 584 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 585 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 586 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 587 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 588 default: return -1; 589 } 590 } 591 592 static int to_mlx5_st(enum ib_qp_type type) 593 { 594 switch (type) { 595 case IB_QPT_RC: return MLX5_QP_ST_RC; 596 case IB_QPT_UC: return MLX5_QP_ST_UC; 597 case IB_QPT_UD: return MLX5_QP_ST_UD; 598 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 599 case IB_QPT_XRC_INI: 600 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 601 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 602 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 603 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 604 case IB_QPT_RAW_PACKET: 605 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 606 case IB_QPT_MAX: 607 default: return -EINVAL; 608 } 609 } 610 611 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 612 struct mlx5_ib_cq *recv_cq); 613 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 614 struct mlx5_ib_cq *recv_cq); 615 616 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 617 struct mlx5_bfreg_info *bfregi, u32 bfregn, 618 bool dyn_bfreg) 619 { 620 unsigned int bfregs_per_sys_page; 621 u32 index_of_sys_page; 622 u32 offset; 623 624 if (bfregi->lib_uar_dyn) 625 return -EINVAL; 626 627 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 628 MLX5_NON_FP_BFREGS_PER_UAR; 629 index_of_sys_page = bfregn / bfregs_per_sys_page; 630 631 if (dyn_bfreg) { 632 index_of_sys_page += bfregi->num_static_sys_pages; 633 634 if (index_of_sys_page >= bfregi->num_sys_pages) 635 return -EINVAL; 636 637 if (bfregn > bfregi->num_dyn_bfregs || 638 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 639 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 640 return -EINVAL; 641 } 642 } 643 644 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 645 return bfregi->sys_pages[index_of_sys_page] + offset; 646 } 647 648 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 649 struct ib_pd *pd, 650 unsigned long addr, size_t size, 651 struct ib_umem **umem, 652 int *npages, int *page_shift, int *ncont, 653 u32 *offset) 654 { 655 int err; 656 657 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 658 if (IS_ERR(*umem)) { 659 mlx5_ib_dbg(dev, "umem_get failed\n"); 660 return PTR_ERR(*umem); 661 } 662 663 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 664 665 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 666 if (err) { 667 mlx5_ib_warn(dev, "bad offset\n"); 668 goto err_umem; 669 } 670 671 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 672 addr, size, *npages, *page_shift, *ncont, *offset); 673 674 return 0; 675 676 err_umem: 677 ib_umem_release(*umem); 678 *umem = NULL; 679 680 return err; 681 } 682 683 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq, 684 struct ib_udata *udata) 685 { 686 struct mlx5_ib_ucontext *context = 687 rdma_udata_to_drv_context( 688 udata, 689 struct mlx5_ib_ucontext, 690 ibucontext); 691 692 mlx5_ib_db_unmap_user(context, &rwq->db); 693 if (rwq->umem) 694 ib_umem_release(rwq->umem); 695 } 696 697 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 698 struct mlx5_ib_rwq *rwq, 699 struct mlx5_ib_create_wq *ucmd) 700 { 701 struct mlx5_ib_ucontext *context; 702 int page_shift = 0; 703 int npages; 704 u32 offset = 0; 705 int ncont = 0; 706 int err; 707 708 if (!ucmd->buf_addr) 709 return -EINVAL; 710 711 context = to_mucontext(pd->uobject->context); 712 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 713 rwq->buf_size, 0, 0); 714 if (IS_ERR(rwq->umem)) { 715 mlx5_ib_dbg(dev, "umem_get failed\n"); 716 err = PTR_ERR(rwq->umem); 717 return err; 718 } 719 720 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 721 &ncont, NULL); 722 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 723 &rwq->rq_page_offset); 724 if (err) { 725 mlx5_ib_warn(dev, "bad offset\n"); 726 goto err_umem; 727 } 728 729 rwq->rq_num_pas = ncont; 730 rwq->page_shift = page_shift; 731 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 732 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 733 734 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 735 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 736 npages, page_shift, ncont, offset); 737 738 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 739 if (err) { 740 mlx5_ib_dbg(dev, "map failed\n"); 741 goto err_umem; 742 } 743 744 rwq->create_type = MLX5_WQ_USER; 745 return 0; 746 747 err_umem: 748 ib_umem_release(rwq->umem); 749 return err; 750 } 751 752 static int adjust_bfregn(struct mlx5_ib_dev *dev, 753 struct mlx5_bfreg_info *bfregi, int bfregn) 754 { 755 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 756 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 757 } 758 759 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 760 struct mlx5_ib_qp *qp, struct ib_udata *udata, 761 struct ib_qp_init_attr *attr, 762 u32 **in, 763 struct mlx5_ib_create_qp_resp *resp, int *inlen, 764 struct mlx5_ib_qp_base *base) 765 { 766 struct mlx5_ib_ucontext *context; 767 struct mlx5_ib_create_qp ucmd; 768 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 769 int page_shift = 0; 770 int uar_index = 0; 771 int npages; 772 u32 offset = 0; 773 int bfregn; 774 int ncont = 0; 775 __be64 *pas; 776 void *qpc; 777 int err; 778 u16 uid; 779 u32 uar_flags; 780 781 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 782 if (err) { 783 mlx5_ib_dbg(dev, "copy failed\n"); 784 return err; 785 } 786 787 context = to_mucontext(pd->uobject->context); 788 uar_flags = ucmd.flags & (MLX5_QP_FLAG_UAR_PAGE_INDEX | 789 MLX5_QP_FLAG_BFREG_INDEX); 790 switch (uar_flags) { 791 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 792 uar_index = ucmd.bfreg_index; 793 bfregn = MLX5_IB_INVALID_BFREG; 794 break; 795 case MLX5_QP_FLAG_BFREG_INDEX: 796 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 797 ucmd.bfreg_index, true); 798 if (uar_index < 0) 799 return uar_index; 800 bfregn = MLX5_IB_INVALID_BFREG; 801 break; 802 case 0: 803 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 804 return -EINVAL; 805 bfregn = alloc_bfreg(dev, &context->bfregi); 806 if (bfregn < 0) 807 return bfregn; 808 break; 809 default: 810 return -EINVAL; 811 } 812 813 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 814 if (bfregn != MLX5_IB_INVALID_BFREG) 815 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 816 false); 817 818 qp->rq.offset = 0; 819 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 820 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 821 822 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 823 if (err) 824 goto err_bfreg; 825 826 if (ucmd.buf_addr && ubuffer->buf_size) { 827 ubuffer->buf_addr = ucmd.buf_addr; 828 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 829 ubuffer->buf_size, 830 &ubuffer->umem, &npages, &page_shift, 831 &ncont, &offset); 832 if (err) 833 goto err_bfreg; 834 } else { 835 ubuffer->umem = NULL; 836 } 837 838 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 839 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 840 *in = mlx5_vzalloc(*inlen); 841 if (!*in) { 842 err = -ENOMEM; 843 goto err_umem; 844 } 845 846 uid = (attr->qp_type != IB_QPT_XRC_TGT && 847 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 848 MLX5_SET(create_qp_in, *in, uid, uid); 849 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 850 if (ubuffer->umem) 851 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 852 853 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 854 855 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 856 MLX5_SET(qpc, qpc, page_offset, offset); 857 858 MLX5_SET(qpc, qpc, uar_page, uar_index); 859 if (bfregn != MLX5_IB_INVALID_BFREG) 860 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 861 else 862 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 863 qp->bfregn = bfregn; 864 865 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 866 if (err) { 867 mlx5_ib_dbg(dev, "map failed\n"); 868 goto err_free; 869 } 870 871 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 872 if (err) { 873 mlx5_ib_dbg(dev, "copy failed\n"); 874 goto err_unmap; 875 } 876 qp->create_type = MLX5_QP_USER; 877 878 return 0; 879 880 err_unmap: 881 mlx5_ib_db_unmap_user(context, &qp->db); 882 883 err_free: 884 kvfree(*in); 885 886 err_umem: 887 if (ubuffer->umem) 888 ib_umem_release(ubuffer->umem); 889 890 err_bfreg: 891 if (bfregn != MLX5_IB_INVALID_BFREG) 892 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 893 return err; 894 } 895 896 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, struct mlx5_ib_qp *qp, 897 struct mlx5_ib_qp_base *base, 898 struct ib_udata *udata) 899 { 900 struct mlx5_ib_ucontext *context = 901 rdma_udata_to_drv_context( 902 udata, 903 struct mlx5_ib_ucontext, 904 ibucontext); 905 906 mlx5_ib_db_unmap_user(context, &qp->db); 907 if (base->ubuffer.umem) 908 ib_umem_release(base->ubuffer.umem); 909 910 /* 911 * Free only the BFREGs which are handled by the kernel. 912 * BFREGs of UARs allocated dynamically are handled by user. 913 */ 914 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 915 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 916 } 917 918 static int create_kernel_qp(struct mlx5_ib_dev *dev, 919 struct ib_qp_init_attr *init_attr, 920 struct mlx5_ib_qp *qp, 921 u32 **in, int *inlen, 922 struct mlx5_ib_qp_base *base) 923 { 924 int uar_index; 925 void *qpc; 926 int err; 927 928 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 929 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 930 IB_QP_CREATE_IPOIB_UD_LSO | 931 MLX5_IB_QP_CREATE_SQPN_QP1 | 932 MLX5_IB_QP_CREATE_WC_TEST)) 933 return -EINVAL; 934 935 spin_lock_init(&qp->bf.lock32); 936 937 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 938 qp->bf.bfreg = &dev->fp_bfreg; 939 else if (init_attr->create_flags & MLX5_IB_QP_CREATE_WC_TEST) 940 qp->bf.bfreg = &dev->wc_bfreg; 941 else 942 qp->bf.bfreg = &dev->bfreg; 943 944 /* We need to divide by two since each register is comprised of 945 * two buffers of identical size, namely odd and even 946 */ 947 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 948 uar_index = qp->bf.bfreg->index; 949 950 err = calc_sq_size(dev, init_attr, qp); 951 if (err < 0) { 952 mlx5_ib_dbg(dev, "err %d\n", err); 953 return err; 954 } 955 956 qp->rq.offset = 0; 957 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 958 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 959 960 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, 961 2 * PAGE_SIZE, &qp->buf); 962 if (err) { 963 mlx5_ib_dbg(dev, "err %d\n", err); 964 return err; 965 } 966 967 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 968 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 969 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 970 *in = mlx5_vzalloc(*inlen); 971 if (!*in) { 972 err = -ENOMEM; 973 goto err_buf; 974 } 975 976 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 977 MLX5_SET(qpc, qpc, uar_page, uar_index); 978 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 979 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 980 981 /* Set "fast registration enabled" for all kernel QPs */ 982 MLX5_SET(qpc, qpc, fre, 1); 983 MLX5_SET(qpc, qpc, rlky, 1); 984 985 if (init_attr->create_flags & MLX5_IB_QP_CREATE_SQPN_QP1) { 986 MLX5_SET(qpc, qpc, deth_sqpn, 1); 987 qp->flags |= MLX5_IB_QP_SQPN_QP1; 988 } 989 990 mlx5_fill_page_array(&qp->buf, 991 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 992 993 err = mlx5_db_alloc(dev->mdev, &qp->db); 994 if (err) { 995 mlx5_ib_dbg(dev, "err %d\n", err); 996 goto err_free; 997 } 998 999 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 1000 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 1001 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 1002 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 1003 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1004 1005 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1006 !qp->sq.w_list || !qp->sq.wqe_head) { 1007 err = -ENOMEM; 1008 goto err_wrid; 1009 } 1010 qp->create_type = MLX5_QP_KERNEL; 1011 1012 return 0; 1013 1014 err_wrid: 1015 kfree(qp->sq.wqe_head); 1016 kfree(qp->sq.w_list); 1017 kfree(qp->sq.wrid); 1018 kfree(qp->sq.wr_data); 1019 kfree(qp->rq.wrid); 1020 mlx5_db_free(dev->mdev, &qp->db); 1021 1022 err_free: 1023 kvfree(*in); 1024 1025 err_buf: 1026 mlx5_buf_free(dev->mdev, &qp->buf); 1027 return err; 1028 } 1029 1030 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1031 { 1032 kfree(qp->sq.wqe_head); 1033 kfree(qp->sq.w_list); 1034 kfree(qp->sq.wrid); 1035 kfree(qp->sq.wr_data); 1036 kfree(qp->rq.wrid); 1037 mlx5_db_free(dev->mdev, &qp->db); 1038 mlx5_buf_free(dev->mdev, &qp->buf); 1039 } 1040 1041 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1042 { 1043 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1044 (attr->qp_type == IB_QPT_XRC_INI)) 1045 return MLX5_SRQ_RQ; 1046 else if (!qp->has_rq) 1047 return MLX5_ZERO_LEN_RQ; 1048 else 1049 return MLX5_NON_ZERO_RQ; 1050 } 1051 1052 static int is_connected(enum ib_qp_type qp_type) 1053 { 1054 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1055 return 1; 1056 1057 return 0; 1058 } 1059 1060 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1061 struct mlx5_ib_sq *sq, u32 tdn, 1062 struct ib_pd *pd) 1063 { 1064 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1065 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1066 1067 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1068 MLX5_SET(tisc, tisc, transport_domain, tdn); 1069 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1070 } 1071 1072 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1073 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1074 { 1075 mlx5_core_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1076 } 1077 1078 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1079 struct mlx5_ib_sq *sq, void *qpin, 1080 struct ib_pd *pd) 1081 { 1082 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1083 __be64 *pas; 1084 void *in; 1085 void *sqc; 1086 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1087 void *wq; 1088 int inlen; 1089 int err; 1090 int page_shift = 0; 1091 int npages; 1092 int ncont = 0; 1093 u32 offset = 0; 1094 u8 ts_format; 1095 1096 ts_format = mlx5_get_sq_default_ts(dev->mdev); 1097 1098 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1099 &sq->ubuffer.umem, &npages, &page_shift, 1100 &ncont, &offset); 1101 if (err) 1102 return err; 1103 1104 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1105 in = mlx5_vzalloc(inlen); 1106 if (!in) { 1107 err = -ENOMEM; 1108 goto err_umem; 1109 } 1110 1111 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1112 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1113 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1114 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1115 MLX5_SET(sqc, sqc, ts_format, ts_format); 1116 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1117 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1118 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1119 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1120 1121 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1122 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1123 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1124 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1125 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1126 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1127 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1128 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1129 MLX5_SET(wq, wq, page_offset, offset); 1130 1131 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1132 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1133 1134 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1135 1136 kvfree(in); 1137 1138 if (err) 1139 goto err_umem; 1140 1141 return 0; 1142 1143 err_umem: 1144 ib_umem_release(sq->ubuffer.umem); 1145 sq->ubuffer.umem = NULL; 1146 1147 return err; 1148 } 1149 1150 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1151 struct mlx5_ib_sq *sq) 1152 { 1153 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1154 ib_umem_release(sq->ubuffer.umem); 1155 } 1156 1157 static int get_rq_pas_size(void *qpc) 1158 { 1159 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1160 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1161 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1162 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1163 u32 po_quanta = 1 << (log_page_size - 6); 1164 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1165 u32 page_size = 1 << log_page_size; 1166 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1167 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1168 1169 return rq_num_pas * sizeof(u64); 1170 } 1171 1172 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1173 struct mlx5_ib_rq *rq, void *qpin, 1174 struct ib_pd *pd) 1175 { 1176 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1177 __be64 *pas; 1178 __be64 *qp_pas; 1179 void *in; 1180 void *rqc; 1181 void *wq; 1182 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1183 int inlen; 1184 int err; 1185 u32 rq_pas_size = get_rq_pas_size(qpc); 1186 u8 ts_format; 1187 1188 ts_format = mlx5_get_rq_default_ts(dev->mdev); 1189 1190 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1191 in = mlx5_vzalloc(inlen); 1192 if (!in) 1193 return -ENOMEM; 1194 1195 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1196 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1197 MLX5_SET(rqc, rqc, vlan_strip_disable, 1); 1198 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE); 1199 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1200 MLX5_SET(rqc, rqc, ts_format, ts_format); 1201 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1202 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1203 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1204 1205 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1206 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1207 1208 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1209 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1210 MLX5_SET(wq, wq, end_padding_mode, 1211 MLX5_GET(qpc, qpc, end_padding_mode)); 1212 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1213 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1214 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1215 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1216 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1217 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1218 1219 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1220 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1221 memcpy(pas, qp_pas, rq_pas_size); 1222 1223 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1224 1225 kvfree(in); 1226 1227 return err; 1228 } 1229 1230 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1231 struct mlx5_ib_rq *rq) 1232 { 1233 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1234 } 1235 1236 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1237 struct mlx5_ib_rq *rq, u32 tdn, 1238 struct ib_pd *pd) 1239 { 1240 u32 *in; 1241 void *tirc; 1242 int inlen; 1243 int err; 1244 1245 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1246 in = mlx5_vzalloc(inlen); 1247 if (!in) 1248 return -ENOMEM; 1249 1250 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1251 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 1252 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1253 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1254 MLX5_SET(tirc, tirc, transport_domain, tdn); 1255 1256 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1257 1258 kvfree(in); 1259 1260 return err; 1261 } 1262 1263 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1264 struct mlx5_ib_rq *rq, 1265 struct ib_pd *pd) 1266 { 1267 mlx5_core_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1268 } 1269 1270 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1271 u32 *in, 1272 struct ib_pd *pd) 1273 { 1274 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1275 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1276 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1277 struct ib_uobject *uobj = pd->uobject; 1278 struct ib_ucontext *ucontext = uobj->context; 1279 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1280 int err; 1281 u32 tdn = mucontext->tdn; 1282 1283 if (qp->sq.wqe_cnt) { 1284 err = create_raw_packet_qp_tis(dev, sq, tdn, pd); 1285 if (err) 1286 return err; 1287 1288 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1289 if (err) 1290 goto err_destroy_tis; 1291 1292 sq->base.container_mibqp = qp; 1293 } 1294 1295 if (qp->rq.wqe_cnt) { 1296 rq->base.container_mibqp = qp; 1297 1298 err = create_raw_packet_qp_rq(dev, rq, in, pd); 1299 if (err) 1300 goto err_destroy_sq; 1301 1302 1303 err = create_raw_packet_qp_tir(dev, rq, tdn, pd); 1304 if (err) 1305 goto err_destroy_rq; 1306 } 1307 1308 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1309 rq->base.mqp.qpn; 1310 1311 return 0; 1312 1313 err_destroy_rq: 1314 destroy_raw_packet_qp_rq(dev, rq); 1315 err_destroy_sq: 1316 if (!qp->sq.wqe_cnt) 1317 return err; 1318 destroy_raw_packet_qp_sq(dev, sq); 1319 err_destroy_tis: 1320 destroy_raw_packet_qp_tis(dev, sq, pd); 1321 1322 return err; 1323 } 1324 1325 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1326 struct mlx5_ib_qp *qp) 1327 { 1328 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1329 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1330 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1331 1332 if (qp->rq.wqe_cnt) { 1333 destroy_raw_packet_qp_tir(dev, rq, qp->ibqp.pd); 1334 destroy_raw_packet_qp_rq(dev, rq); 1335 } 1336 1337 if (qp->sq.wqe_cnt) { 1338 destroy_raw_packet_qp_sq(dev, sq); 1339 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1340 } 1341 } 1342 1343 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1344 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1345 { 1346 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1347 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1348 1349 sq->sq = &qp->sq; 1350 rq->rq = &qp->rq; 1351 sq->doorbell = &qp->db; 1352 rq->doorbell = &qp->db; 1353 } 1354 1355 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1356 { 1357 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1358 to_mpd(qp->ibqp.pd)->uid); 1359 } 1360 1361 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1362 struct ib_pd *pd, 1363 struct ib_qp_init_attr *init_attr, 1364 struct ib_udata *udata) 1365 { 1366 struct ib_uobject *uobj = pd->uobject; 1367 struct ib_ucontext *ucontext = uobj->context; 1368 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1369 struct mlx5_ib_create_qp_resp resp = {}; 1370 int inlen; 1371 int err; 1372 u32 *in; 1373 void *tirc; 1374 void *hfso; 1375 u32 selected_fields = 0; 1376 size_t min_resp_len; 1377 u32 tdn = mucontext->tdn; 1378 struct mlx5_ib_create_qp_rss ucmd = {}; 1379 size_t required_cmd_sz; 1380 1381 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1382 return -EOPNOTSUPP; 1383 1384 if (init_attr->create_flags || init_attr->send_cq) 1385 return -EINVAL; 1386 1387 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1388 if (udata->outlen < min_resp_len) 1389 return -EINVAL; 1390 1391 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1); 1392 if (udata->inlen < required_cmd_sz) { 1393 mlx5_ib_dbg(dev, "invalid inlen\n"); 1394 return -EINVAL; 1395 } 1396 1397 if (udata->inlen > sizeof(ucmd) && 1398 !ib_is_udata_cleared(udata, sizeof(ucmd), 1399 udata->inlen - sizeof(ucmd))) { 1400 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1401 return -EOPNOTSUPP; 1402 } 1403 1404 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1405 mlx5_ib_dbg(dev, "copy failed\n"); 1406 return -EFAULT; 1407 } 1408 1409 if (ucmd.comp_mask) { 1410 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1411 return -EOPNOTSUPP; 1412 } 1413 1414 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) { 1415 mlx5_ib_dbg(dev, "invalid reserved\n"); 1416 return -EOPNOTSUPP; 1417 } 1418 1419 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1420 if (err) { 1421 mlx5_ib_dbg(dev, "copy failed\n"); 1422 return -EINVAL; 1423 } 1424 1425 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1426 in = mlx5_vzalloc(inlen); 1427 if (!in) 1428 return -ENOMEM; 1429 1430 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1431 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 1432 MLX5_SET(tirc, tirc, disp_type, 1433 MLX5_TIRC_DISP_TYPE_INDIRECT); 1434 MLX5_SET(tirc, tirc, indirect_table, 1435 init_attr->rwq_ind_tbl->ind_tbl_num); 1436 MLX5_SET(tirc, tirc, transport_domain, tdn); 1437 1438 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1439 switch (ucmd.rx_hash_function) { 1440 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1441 { 1442 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1443 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1444 1445 if (len != ucmd.rx_key_len) { 1446 err = -EINVAL; 1447 goto err; 1448 } 1449 1450 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FUNC_TOEPLITZ); 1451 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1452 memcpy(rss_key, ucmd.rx_hash_key, len); 1453 break; 1454 } 1455 default: 1456 err = -EOPNOTSUPP; 1457 goto err; 1458 } 1459 1460 if (!ucmd.rx_hash_fields_mask) { 1461 /* special case when this TIR serves as steering entry without hashing */ 1462 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1463 goto create_tir; 1464 err = -EINVAL; 1465 goto err; 1466 } 1467 1468 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1469 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1470 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1471 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1472 err = -EINVAL; 1473 goto err; 1474 } 1475 1476 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1477 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1478 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1479 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1480 MLX5_L3_PROT_TYPE_IPV4); 1481 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1482 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1483 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1484 MLX5_L3_PROT_TYPE_IPV6); 1485 1486 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1487 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1488 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1489 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1490 err = -EINVAL; 1491 goto err; 1492 } 1493 1494 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1495 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1496 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1497 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1498 MLX5_L4_PROT_TYPE_TCP); 1499 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1500 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1501 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1502 MLX5_L4_PROT_TYPE_UDP); 1503 1504 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1505 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1506 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1507 1508 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1509 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1510 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1511 1512 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1513 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1514 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1515 1516 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1517 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1518 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1519 1520 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1521 1522 create_tir: 1523 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1524 1525 if (err) 1526 goto err; 1527 1528 kvfree(in); 1529 /* qpn is reserved for that QP */ 1530 qp->trans_qp.base.mqp.qpn = 0; 1531 qp->flags |= MLX5_IB_QP_RSS; 1532 return 0; 1533 1534 err: 1535 kvfree(in); 1536 return err; 1537 } 1538 1539 static int atomic_size_to_mode(int size_mask) 1540 { 1541 /* driver does not support atomic_size > 256B 1542 * and does not know how to translate bigger sizes 1543 */ 1544 int supported_size_mask = size_mask & 0x1ff; 1545 int log_max_size; 1546 1547 if (!supported_size_mask) 1548 return -EOPNOTSUPP; 1549 1550 log_max_size = __fls(supported_size_mask); 1551 1552 if (log_max_size > 3) 1553 return log_max_size; 1554 1555 return MLX5_ATOMIC_MODE_8B; 1556 } 1557 1558 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1559 enum ib_qp_type qp_type) 1560 { 1561 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1562 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1563 int atomic_mode = -EOPNOTSUPP; 1564 int atomic_size_mask; 1565 1566 if (!atomic) 1567 return -EOPNOTSUPP; 1568 1569 if (qp_type == MLX5_IB_QPT_DCT) 1570 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1571 else 1572 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1573 1574 if ((atomic_operations & MLX5_ATOMIC_OPS_MASKED_CMP_SWAP) || 1575 (atomic_operations & MLX5_ATOMIC_OPS_MASKED_FETCH_ADD)) 1576 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1577 1578 if (atomic_mode <= 0 && 1579 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1580 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1581 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1582 1583 return atomic_mode; 1584 } 1585 1586 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1587 struct ib_qp_init_attr *init_attr, 1588 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1589 { 1590 struct mlx5_ib_resources *devr = &dev->devr; 1591 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1592 struct mlx5_core_dev *mdev = dev->mdev; 1593 struct mlx5_ib_create_qp_resp resp; 1594 struct mlx5_ib_cq *send_cq; 1595 struct mlx5_ib_cq *recv_cq; 1596 unsigned long flags; 1597 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1598 struct mlx5_ib_create_qp ucmd; 1599 struct mlx5_ib_qp_base *base; 1600 void *qpc; 1601 u32 *in; 1602 int err; 1603 1604 base = init_attr->qp_type == IB_QPT_RAW_PACKET ? 1605 &qp->raw_packet_qp.rq.base : 1606 &qp->trans_qp.base; 1607 1608 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1609 mlx5_ib_odp_create_qp(qp); 1610 1611 mutex_init(&qp->mutex); 1612 spin_lock_init(&qp->sq.lock); 1613 spin_lock_init(&qp->rq.lock); 1614 1615 if (init_attr->rwq_ind_tbl) { 1616 if (!udata) 1617 return -ENOSYS; 1618 1619 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1620 return err; 1621 } 1622 1623 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1624 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1625 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1626 return -EINVAL; 1627 } else { 1628 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1629 } 1630 } 1631 1632 if (init_attr->create_flags & 1633 (IB_QP_CREATE_CROSS_CHANNEL | 1634 IB_QP_CREATE_MANAGED_SEND | 1635 IB_QP_CREATE_MANAGED_RECV)) { 1636 if (!MLX5_CAP_GEN(mdev, cd)) { 1637 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1638 return -EINVAL; 1639 } 1640 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1641 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1642 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1643 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1644 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1645 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1646 } 1647 1648 if (init_attr->qp_type == IB_QPT_UD && 1649 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1650 if (!MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 1651 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1652 return -EOPNOTSUPP; 1653 } 1654 1655 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1656 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1657 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1658 return -EOPNOTSUPP; 1659 } 1660 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1661 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1662 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1663 return -EOPNOTSUPP; 1664 } 1665 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1666 } 1667 1668 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1669 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1670 1671 if (pd && pd->uobject) { 1672 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1673 mlx5_ib_dbg(dev, "copy failed\n"); 1674 return -EFAULT; 1675 } 1676 1677 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1678 &ucmd, udata->inlen, &uidx); 1679 if (err) 1680 return err; 1681 1682 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1683 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1684 } else { 1685 qp->wq_sig = !!wq_signature; 1686 } 1687 1688 qp->has_rq = qp_has_rq(init_attr); 1689 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1690 qp, (pd && pd->uobject) ? &ucmd : NULL); 1691 if (err) { 1692 mlx5_ib_dbg(dev, "err %d\n", err); 1693 return err; 1694 } 1695 1696 if (pd) { 1697 if (pd->uobject) { 1698 __u32 max_wqes = 1699 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1700 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1701 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1702 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1703 mlx5_ib_dbg(dev, "invalid rq params\n"); 1704 return -EINVAL; 1705 } 1706 if (ucmd.sq_wqe_count > max_wqes) { 1707 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1708 ucmd.sq_wqe_count, max_wqes); 1709 return -EINVAL; 1710 } 1711 if (init_attr->create_flags & 1712 MLX5_IB_QP_CREATE_SQPN_QP1) { 1713 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1714 return -EINVAL; 1715 } 1716 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1717 &resp, &inlen, base); 1718 if (err) 1719 mlx5_ib_dbg(dev, "err %d\n", err); 1720 } else { 1721 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1722 base); 1723 if (err) 1724 mlx5_ib_dbg(dev, "err %d\n", err); 1725 } 1726 1727 if (err) 1728 return err; 1729 } else { 1730 in = mlx5_vzalloc(inlen); 1731 if (!in) 1732 return -ENOMEM; 1733 1734 qp->create_type = MLX5_QP_EMPTY; 1735 } 1736 1737 if (is_sqp(init_attr->qp_type)) 1738 qp->port = init_attr->port_num; 1739 1740 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1741 1742 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type)); 1743 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1744 1745 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1746 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1747 else 1748 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1749 1750 1751 if (qp->wq_sig) 1752 MLX5_SET(qpc, qpc, wq_signature, 1); 1753 1754 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1755 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1756 1757 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1758 MLX5_SET(qpc, qpc, cd_master, 1); 1759 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1760 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1761 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1762 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1763 1764 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1765 int rcqe_sz; 1766 int scqe_sz; 1767 1768 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1769 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1770 1771 if (rcqe_sz == 128) 1772 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1773 else 1774 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1775 1776 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1777 if (scqe_sz == 128) 1778 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1779 else 1780 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1781 } 1782 } 1783 1784 if (qp->rq.wqe_cnt) { 1785 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1786 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1787 } 1788 1789 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1790 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1791 1792 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1793 1794 if (qp->sq.wqe_cnt) 1795 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1796 else 1797 MLX5_SET(qpc, qpc, no_sq, 1); 1798 1799 /* Set default resources */ 1800 switch (init_attr->qp_type) { 1801 case IB_QPT_XRC_TGT: 1802 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1803 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1804 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn); 1805 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1806 break; 1807 case IB_QPT_XRC_INI: 1808 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1809 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1810 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn); 1811 break; 1812 default: 1813 if (init_attr->srq) { 1814 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1815 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(init_attr->srq)->msrq.srqn); 1816 } else { 1817 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1818 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s1)->msrq.srqn); 1819 } 1820 } 1821 1822 if (init_attr->send_cq) 1823 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1824 1825 if (init_attr->recv_cq) 1826 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1827 1828 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1829 1830 /* 0xffffff means we ask to work with cqe version 0 */ 1831 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1832 MLX5_SET(qpc, qpc, user_index, uidx); 1833 1834 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1835 if (init_attr->qp_type == IB_QPT_UD && 1836 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1837 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1838 qp->flags |= MLX5_IB_QP_LSO; 1839 } 1840 1841 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1842 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1843 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1844 err = create_raw_packet_qp(dev, qp, in, pd); 1845 } else { 1846 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1847 } 1848 1849 if (err) { 1850 mlx5_ib_dbg(dev, "create qp failed\n"); 1851 goto err_create; 1852 } 1853 1854 kvfree(in); 1855 1856 base->container_mibqp = qp; 1857 base->mqp.event = mlx5_ib_qp_event; 1858 1859 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1860 &send_cq, &recv_cq); 1861 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1862 mlx5_ib_lock_cqs(send_cq, recv_cq); 1863 /* Maintain device to QPs access, needed for further handling via reset 1864 * flow 1865 */ 1866 list_add_tail(&qp->qps_list, &dev->qp_list); 1867 /* Maintain CQ to QPs access, needed for further handling via reset flow 1868 */ 1869 if (send_cq) 1870 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1871 if (recv_cq) 1872 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1873 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1874 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1875 1876 return 0; 1877 1878 err_create: 1879 if (qp->create_type == MLX5_QP_USER) 1880 destroy_qp_user(dev, pd, qp, base, udata); 1881 else if (qp->create_type == MLX5_QP_KERNEL) 1882 destroy_qp_kernel(dev, qp); 1883 1884 kvfree(in); 1885 return err; 1886 } 1887 1888 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1889 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1890 { 1891 if (send_cq) { 1892 if (recv_cq) { 1893 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1894 spin_lock(&send_cq->lock); 1895 spin_lock_nested(&recv_cq->lock, 1896 SINGLE_DEPTH_NESTING); 1897 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1898 spin_lock(&send_cq->lock); 1899 __acquire(&recv_cq->lock); 1900 } else { 1901 spin_lock(&recv_cq->lock); 1902 spin_lock_nested(&send_cq->lock, 1903 SINGLE_DEPTH_NESTING); 1904 } 1905 } else { 1906 spin_lock(&send_cq->lock); 1907 __acquire(&recv_cq->lock); 1908 } 1909 } else if (recv_cq) { 1910 spin_lock(&recv_cq->lock); 1911 __acquire(&send_cq->lock); 1912 } else { 1913 __acquire(&send_cq->lock); 1914 __acquire(&recv_cq->lock); 1915 } 1916 } 1917 1918 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1919 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1920 { 1921 if (send_cq) { 1922 if (recv_cq) { 1923 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1924 spin_unlock(&recv_cq->lock); 1925 spin_unlock(&send_cq->lock); 1926 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1927 __release(&recv_cq->lock); 1928 spin_unlock(&send_cq->lock); 1929 } else { 1930 spin_unlock(&send_cq->lock); 1931 spin_unlock(&recv_cq->lock); 1932 } 1933 } else { 1934 __release(&recv_cq->lock); 1935 spin_unlock(&send_cq->lock); 1936 } 1937 } else if (recv_cq) { 1938 __release(&send_cq->lock); 1939 spin_unlock(&recv_cq->lock); 1940 } else { 1941 __release(&recv_cq->lock); 1942 __release(&send_cq->lock); 1943 } 1944 } 1945 1946 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1947 { 1948 return to_mpd(qp->ibqp.pd); 1949 } 1950 1951 static void get_cqs(enum ib_qp_type qp_type, 1952 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 1953 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1954 { 1955 switch (qp_type) { 1956 case IB_QPT_XRC_TGT: 1957 *send_cq = NULL; 1958 *recv_cq = NULL; 1959 break; 1960 case MLX5_IB_QPT_REG_UMR: 1961 case IB_QPT_XRC_INI: 1962 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1963 *recv_cq = NULL; 1964 break; 1965 1966 case IB_QPT_SMI: 1967 case MLX5_IB_QPT_HW_GSI: 1968 case IB_QPT_RC: 1969 case IB_QPT_UC: 1970 case IB_QPT_UD: 1971 case IB_QPT_RAW_IPV6: 1972 case IB_QPT_RAW_ETHERTYPE: 1973 case IB_QPT_RAW_PACKET: 1974 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1975 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 1976 break; 1977 1978 case IB_QPT_MAX: 1979 default: 1980 *send_cq = NULL; 1981 *recv_cq = NULL; 1982 break; 1983 } 1984 } 1985 1986 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1987 const struct mlx5_modify_raw_qp_param *raw_qp_param, 1988 u8 lag_tx_affinity); 1989 1990 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1991 struct ib_udata *udata) 1992 { 1993 struct mlx5_ib_cq *send_cq, *recv_cq; 1994 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 1995 unsigned long flags; 1996 int err; 1997 1998 if (qp->ibqp.rwq_ind_tbl) { 1999 destroy_rss_raw_qp_tir(dev, qp); 2000 return; 2001 } 2002 2003 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ? 2004 &qp->raw_packet_qp.rq.base : 2005 &qp->trans_qp.base; 2006 2007 if (qp->state != IB_QPS_RESET) { 2008 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) { 2009 mlx5_ib_qp_disable_pagefaults(qp); 2010 err = mlx5_core_qp_modify(dev->mdev, 2011 MLX5_CMD_OP_2RST_QP, 0, 2012 NULL, &base->mqp); 2013 } else { 2014 struct mlx5_modify_raw_qp_param raw_qp_param = { 2015 .operation = MLX5_CMD_OP_2RST_QP 2016 }; 2017 2018 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2019 } 2020 if (err) 2021 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2022 base->mqp.qpn); 2023 } 2024 2025 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2026 &send_cq, &recv_cq); 2027 2028 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2029 mlx5_ib_lock_cqs(send_cq, recv_cq); 2030 /* del from lists under both locks above to protect reset flow paths */ 2031 list_del(&qp->qps_list); 2032 if (send_cq) 2033 list_del(&qp->cq_send_list); 2034 2035 if (recv_cq) 2036 list_del(&qp->cq_recv_list); 2037 2038 if (qp->create_type == MLX5_QP_KERNEL) { 2039 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2040 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2041 if (send_cq != recv_cq) 2042 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2043 NULL); 2044 } 2045 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2046 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2047 2048 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 2049 destroy_raw_packet_qp(dev, qp); 2050 } else { 2051 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2052 if (err) 2053 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2054 base->mqp.qpn); 2055 } 2056 2057 if (qp->create_type == MLX5_QP_KERNEL) 2058 destroy_qp_kernel(dev, qp); 2059 else if (qp->create_type == MLX5_QP_USER) 2060 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata); 2061 } 2062 2063 static const char *ib_qp_type_str(enum ib_qp_type type) 2064 { 2065 switch (type) { 2066 case IB_QPT_SMI: 2067 return "IB_QPT_SMI"; 2068 case IB_QPT_GSI: 2069 return "IB_QPT_GSI"; 2070 case IB_QPT_RC: 2071 return "IB_QPT_RC"; 2072 case IB_QPT_UC: 2073 return "IB_QPT_UC"; 2074 case IB_QPT_UD: 2075 return "IB_QPT_UD"; 2076 case IB_QPT_RAW_IPV6: 2077 return "IB_QPT_RAW_IPV6"; 2078 case IB_QPT_RAW_ETHERTYPE: 2079 return "IB_QPT_RAW_ETHERTYPE"; 2080 case IB_QPT_XRC_INI: 2081 return "IB_QPT_XRC_INI"; 2082 case IB_QPT_XRC_TGT: 2083 return "IB_QPT_XRC_TGT"; 2084 case IB_QPT_RAW_PACKET: 2085 return "IB_QPT_RAW_PACKET"; 2086 case MLX5_IB_QPT_REG_UMR: 2087 return "MLX5_IB_QPT_REG_UMR"; 2088 case IB_QPT_MAX: 2089 default: 2090 return "Invalid QP type"; 2091 } 2092 } 2093 2094 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2095 struct ib_qp_init_attr *init_attr, 2096 struct ib_udata *udata) 2097 { 2098 struct mlx5_ib_dev *dev; 2099 struct mlx5_ib_qp *qp; 2100 u16 xrcdn = 0; 2101 int err; 2102 2103 if (pd) { 2104 dev = to_mdev(pd->device); 2105 2106 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2107 if (!pd->uobject) { 2108 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2109 return ERR_PTR(-EINVAL); 2110 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2111 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2112 return ERR_PTR(-EINVAL); 2113 } 2114 } 2115 } else { 2116 /* being cautious here */ 2117 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2118 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2119 pr_warn("%s: no PD for transport %s\n", __func__, 2120 ib_qp_type_str(init_attr->qp_type)); 2121 return ERR_PTR(-EINVAL); 2122 } 2123 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2124 } 2125 2126 switch (init_attr->qp_type) { 2127 case IB_QPT_XRC_TGT: 2128 case IB_QPT_XRC_INI: 2129 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2130 mlx5_ib_dbg(dev, "XRC not supported\n"); 2131 return ERR_PTR(-ENOSYS); 2132 } 2133 init_attr->recv_cq = NULL; 2134 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2135 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2136 init_attr->send_cq = NULL; 2137 } 2138 2139 /* fall through */ 2140 case IB_QPT_RAW_PACKET: 2141 case IB_QPT_RC: 2142 case IB_QPT_UC: 2143 case IB_QPT_UD: 2144 case IB_QPT_SMI: 2145 case MLX5_IB_QPT_HW_GSI: 2146 case MLX5_IB_QPT_REG_UMR: 2147 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2148 if (!qp) 2149 return ERR_PTR(-ENOMEM); 2150 2151 err = create_qp_common(dev, pd, init_attr, udata, qp); 2152 if (err) { 2153 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2154 kfree(qp); 2155 return ERR_PTR(err); 2156 } 2157 2158 if (is_qp0(init_attr->qp_type)) 2159 qp->ibqp.qp_num = 0; 2160 else if (is_qp1(init_attr->qp_type)) 2161 qp->ibqp.qp_num = 1; 2162 else 2163 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2164 2165 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2166 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2167 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2168 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2169 2170 qp->trans_qp.xrcdn = xrcdn; 2171 2172 break; 2173 2174 case IB_QPT_GSI: 2175 return mlx5_ib_gsi_create_qp(pd, init_attr); 2176 2177 case IB_QPT_RAW_IPV6: 2178 case IB_QPT_RAW_ETHERTYPE: 2179 case IB_QPT_MAX: 2180 default: 2181 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2182 init_attr->qp_type); 2183 /* Don't support raw QPs */ 2184 return ERR_PTR(-EINVAL); 2185 } 2186 2187 return &qp->ibqp; 2188 } 2189 2190 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 2191 { 2192 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2193 struct mlx5_ib_qp *mqp = to_mqp(qp); 2194 2195 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2196 return mlx5_ib_gsi_destroy_qp(qp); 2197 2198 destroy_qp_common(dev, mqp, udata); 2199 2200 kfree(mqp); 2201 2202 return 0; 2203 } 2204 2205 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, 2206 const struct ib_qp_attr *attr, 2207 int attr_mask, __be32 *hw_access_flags_be) 2208 { 2209 u8 dest_rd_atomic; 2210 u32 access_flags, hw_access_flags = 0; 2211 2212 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 2213 2214 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2215 dest_rd_atomic = attr->max_dest_rd_atomic; 2216 else 2217 dest_rd_atomic = qp->trans_qp.resp_depth; 2218 2219 if (attr_mask & IB_QP_ACCESS_FLAGS) 2220 access_flags = attr->qp_access_flags; 2221 else 2222 access_flags = qp->trans_qp.atomic_rd_en; 2223 2224 if (!dest_rd_atomic) 2225 access_flags &= IB_ACCESS_REMOTE_WRITE; 2226 2227 if (access_flags & IB_ACCESS_REMOTE_READ) 2228 hw_access_flags |= MLX5_QP_BIT_RRE; 2229 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 2230 int atomic_mode; 2231 2232 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 2233 if (atomic_mode < 0) 2234 return -EOPNOTSUPP; 2235 2236 hw_access_flags |= MLX5_QP_BIT_RAE; 2237 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFF; 2238 } 2239 2240 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2241 hw_access_flags |= MLX5_QP_BIT_RWE; 2242 2243 *hw_access_flags_be = cpu_to_be32(hw_access_flags); 2244 2245 return 0; 2246 } 2247 2248 enum { 2249 MLX5_PATH_FLAG_FL = 1 << 0, 2250 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2251 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2252 }; 2253 2254 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2255 { 2256 if (rate == IB_RATE_PORT_CURRENT) { 2257 return 0; 2258 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) { 2259 return -EINVAL; 2260 } else { 2261 while (rate != IB_RATE_2_5_GBPS && 2262 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2263 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2264 --rate; 2265 } 2266 2267 return rate + MLX5_STAT_RATE_OFFSET; 2268 } 2269 2270 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2271 struct mlx5_ib_sq *sq, u8 sl, 2272 struct ib_pd *pd) 2273 { 2274 void *in; 2275 void *tisc; 2276 int inlen; 2277 int err; 2278 2279 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2280 in = mlx5_vzalloc(inlen); 2281 if (!in) 2282 return -ENOMEM; 2283 2284 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2285 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2286 2287 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2288 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2289 2290 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2291 2292 kvfree(in); 2293 2294 return err; 2295 } 2296 2297 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2298 struct mlx5_ib_sq *sq, u8 tx_affinity, 2299 struct ib_pd *pd) 2300 { 2301 void *in; 2302 void *tisc; 2303 int inlen; 2304 int err; 2305 2306 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2307 in = mlx5_vzalloc(inlen); 2308 if (!in) 2309 return -ENOMEM; 2310 2311 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2312 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2313 2314 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2315 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2316 2317 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2318 2319 kvfree(in); 2320 2321 return err; 2322 } 2323 2324 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2325 const struct ib_ah_attr *ah, 2326 struct mlx5_qp_path *path, u8 port, int attr_mask, 2327 u32 path_flags, const struct ib_qp_attr *attr, 2328 bool alt) 2329 { 2330 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port); 2331 int err; 2332 enum ib_gid_type gid_type; 2333 2334 if (attr_mask & IB_QP_PKEY_INDEX) 2335 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2336 attr->pkey_index); 2337 2338 if (ah->ah_flags & IB_AH_GRH) { 2339 if (ah->grh.sgid_index >= 2340 dev->mdev->port_caps[port - 1].gid_table_len) { 2341 pr_err("sgid_index (%u) too large. max is %d\n", 2342 ah->grh.sgid_index, 2343 dev->mdev->port_caps[port - 1].gid_table_len); 2344 return -EINVAL; 2345 } 2346 } 2347 2348 if (ll == IB_LINK_LAYER_ETHERNET) { 2349 if (!(ah->ah_flags & IB_AH_GRH)) 2350 return -EINVAL; 2351 err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index, 2352 &gid_type); 2353 if (err) 2354 return err; 2355 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac)); 2356 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2357 ah->grh.sgid_index); 2358 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4; 2359 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2360 path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f; 2361 } else { 2362 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2363 path->fl_free_ar |= 2364 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2365 path->rlid = cpu_to_be16(ah->dlid); 2366 path->grh_mlid = ah->src_path_bits & 0x7f; 2367 if (ah->ah_flags & IB_AH_GRH) 2368 path->grh_mlid |= 1 << 7; 2369 path->dci_cfi_prio_sl = ah->sl & 0xf; 2370 } 2371 2372 if (ah->ah_flags & IB_AH_GRH) { 2373 path->mgid_index = ah->grh.sgid_index; 2374 path->hop_limit = ah->grh.hop_limit; 2375 path->tclass_flowlabel = 2376 cpu_to_be32((ah->grh.traffic_class << 20) | 2377 (ah->grh.flow_label)); 2378 memcpy(path->rgid, ah->grh.dgid.raw, 16); 2379 } 2380 2381 err = ib_rate_to_mlx5(dev, ah->static_rate); 2382 if (err < 0) 2383 return err; 2384 path->static_rate = err; 2385 path->port = port; 2386 2387 if (attr_mask & IB_QP_TIMEOUT) 2388 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2389 2390 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2391 return modify_raw_packet_eth_prio(dev->mdev, 2392 &qp->raw_packet_qp.sq, 2393 ah->sl & 0xf, qp->ibqp.pd); 2394 2395 return 0; 2396 } 2397 2398 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2399 [MLX5_QP_STATE_INIT] = { 2400 [MLX5_QP_STATE_INIT] = { 2401 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2402 MLX5_QP_OPTPAR_RAE | 2403 MLX5_QP_OPTPAR_RWE | 2404 MLX5_QP_OPTPAR_PKEY_INDEX | 2405 MLX5_QP_OPTPAR_PRI_PORT, 2406 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2407 MLX5_QP_OPTPAR_PKEY_INDEX | 2408 MLX5_QP_OPTPAR_PRI_PORT, 2409 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2410 MLX5_QP_OPTPAR_Q_KEY | 2411 MLX5_QP_OPTPAR_PRI_PORT, 2412 }, 2413 [MLX5_QP_STATE_RTR] = { 2414 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2415 MLX5_QP_OPTPAR_RRE | 2416 MLX5_QP_OPTPAR_RAE | 2417 MLX5_QP_OPTPAR_RWE | 2418 MLX5_QP_OPTPAR_PKEY_INDEX, 2419 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2420 MLX5_QP_OPTPAR_RWE | 2421 MLX5_QP_OPTPAR_PKEY_INDEX, 2422 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2423 MLX5_QP_OPTPAR_Q_KEY, 2424 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2425 MLX5_QP_OPTPAR_Q_KEY, 2426 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2427 MLX5_QP_OPTPAR_RRE | 2428 MLX5_QP_OPTPAR_RAE | 2429 MLX5_QP_OPTPAR_RWE | 2430 MLX5_QP_OPTPAR_PKEY_INDEX, 2431 }, 2432 }, 2433 [MLX5_QP_STATE_RTR] = { 2434 [MLX5_QP_STATE_RTS] = { 2435 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2436 MLX5_QP_OPTPAR_RRE | 2437 MLX5_QP_OPTPAR_RAE | 2438 MLX5_QP_OPTPAR_RWE | 2439 MLX5_QP_OPTPAR_PM_STATE | 2440 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2441 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2442 MLX5_QP_OPTPAR_RWE | 2443 MLX5_QP_OPTPAR_PM_STATE, 2444 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2445 }, 2446 }, 2447 [MLX5_QP_STATE_RTS] = { 2448 [MLX5_QP_STATE_RTS] = { 2449 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2450 MLX5_QP_OPTPAR_RAE | 2451 MLX5_QP_OPTPAR_RWE | 2452 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2453 MLX5_QP_OPTPAR_PM_STATE | 2454 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2455 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2456 MLX5_QP_OPTPAR_PM_STATE | 2457 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2458 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2459 MLX5_QP_OPTPAR_SRQN | 2460 MLX5_QP_OPTPAR_CQN_RCV, 2461 }, 2462 }, 2463 [MLX5_QP_STATE_SQER] = { 2464 [MLX5_QP_STATE_RTS] = { 2465 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2466 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2467 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2468 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2469 MLX5_QP_OPTPAR_RWE | 2470 MLX5_QP_OPTPAR_RAE | 2471 MLX5_QP_OPTPAR_RRE, 2472 }, 2473 }, 2474 }; 2475 2476 static int ib_nr_to_mlx5_nr(int ib_mask) 2477 { 2478 switch (ib_mask) { 2479 case IB_QP_STATE: 2480 return 0; 2481 case IB_QP_CUR_STATE: 2482 return 0; 2483 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2484 return 0; 2485 case IB_QP_ACCESS_FLAGS: 2486 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2487 MLX5_QP_OPTPAR_RAE; 2488 case IB_QP_PKEY_INDEX: 2489 return MLX5_QP_OPTPAR_PKEY_INDEX; 2490 case IB_QP_PORT: 2491 return MLX5_QP_OPTPAR_PRI_PORT; 2492 case IB_QP_QKEY: 2493 return MLX5_QP_OPTPAR_Q_KEY; 2494 case IB_QP_AV: 2495 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2496 MLX5_QP_OPTPAR_PRI_PORT; 2497 case IB_QP_PATH_MTU: 2498 return 0; 2499 case IB_QP_TIMEOUT: 2500 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2501 case IB_QP_RETRY_CNT: 2502 return MLX5_QP_OPTPAR_RETRY_COUNT; 2503 case IB_QP_RNR_RETRY: 2504 return MLX5_QP_OPTPAR_RNR_RETRY; 2505 case IB_QP_RQ_PSN: 2506 return 0; 2507 case IB_QP_MAX_QP_RD_ATOMIC: 2508 return MLX5_QP_OPTPAR_SRA_MAX; 2509 case IB_QP_ALT_PATH: 2510 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2511 case IB_QP_MIN_RNR_TIMER: 2512 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2513 case IB_QP_SQ_PSN: 2514 return 0; 2515 case IB_QP_MAX_DEST_RD_ATOMIC: 2516 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2517 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2518 case IB_QP_PATH_MIG_STATE: 2519 return MLX5_QP_OPTPAR_PM_STATE; 2520 case IB_QP_CAP: 2521 return 0; 2522 case IB_QP_DEST_QPN: 2523 return 0; 2524 } 2525 return 0; 2526 } 2527 2528 static int ib_mask_to_mlx5_opt(int ib_mask) 2529 { 2530 int result = 0; 2531 int i; 2532 2533 for (i = 0; i < 8 * sizeof(int); i++) { 2534 if ((1 << i) & ib_mask) 2535 result |= ib_nr_to_mlx5_nr(1 << i); 2536 } 2537 2538 return result; 2539 } 2540 2541 static int modify_raw_packet_qp_rq( 2542 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 2543 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 2544 { 2545 void *in; 2546 void *rqc; 2547 int inlen; 2548 int err; 2549 2550 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2551 in = mlx5_vzalloc(inlen); 2552 if (!in) 2553 return -ENOMEM; 2554 2555 MLX5_SET(modify_rq_in, in, rqn, rq->base.mqp.qpn); 2556 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2557 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 2558 2559 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2560 MLX5_SET(rqc, rqc, state, new_state); 2561 2562 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2563 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counters_set_id)) { 2564 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2565 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID); 2566 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2567 } else 2568 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2569 dev->ib_dev.name); 2570 } 2571 2572 err = mlx5_core_modify_rq(dev->mdev, in, inlen); 2573 if (err) 2574 goto out; 2575 2576 rq->state = new_state; 2577 2578 out: 2579 kvfree(in); 2580 return err; 2581 } 2582 2583 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2584 struct mlx5_ib_sq *sq, int new_state, 2585 struct ib_pd *pd) 2586 { 2587 void *in; 2588 void *sqc; 2589 int inlen; 2590 int err; 2591 2592 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2593 in = mlx5_vzalloc(inlen); 2594 if (!in) 2595 return -ENOMEM; 2596 2597 MLX5_SET(modify_sq_in, in, sqn, sq->base.mqp.qpn); 2598 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 2599 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2600 2601 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2602 MLX5_SET(sqc, sqc, state, new_state); 2603 2604 err = mlx5_core_modify_sq(dev, in, inlen); 2605 if (err) 2606 goto out; 2607 2608 sq->state = new_state; 2609 2610 out: 2611 kvfree(in); 2612 return err; 2613 } 2614 2615 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2616 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2617 u8 tx_affinity) 2618 { 2619 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2620 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2621 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2622 int modify_rq = !!qp->rq.wqe_cnt; 2623 int modify_sq = !!qp->sq.wqe_cnt; 2624 int rq_state; 2625 int sq_state; 2626 int err; 2627 2628 switch (raw_qp_param->operation) { 2629 case MLX5_CMD_OP_RST2INIT_QP: 2630 rq_state = MLX5_RQC_STATE_RDY; 2631 sq_state = MLX5_SQC_STATE_RDY; 2632 break; 2633 case MLX5_CMD_OP_2ERR_QP: 2634 rq_state = MLX5_RQC_STATE_ERR; 2635 sq_state = MLX5_SQC_STATE_ERR; 2636 break; 2637 case MLX5_CMD_OP_2RST_QP: 2638 rq_state = MLX5_RQC_STATE_RST; 2639 sq_state = MLX5_SQC_STATE_RST; 2640 break; 2641 case MLX5_CMD_OP_RTR2RTS_QP: 2642 case MLX5_CMD_OP_RTS2RTS_QP: 2643 return raw_qp_param->set_mask ? -EINVAL : 0; 2644 case MLX5_CMD_OP_INIT2INIT_QP: 2645 case MLX5_CMD_OP_INIT2RTR_QP: 2646 if (raw_qp_param->set_mask) 2647 return -EINVAL; 2648 else 2649 return 0; 2650 default: 2651 WARN_ON(1); 2652 return -EINVAL; 2653 } 2654 2655 if (modify_rq) { 2656 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 2657 qp->ibqp.pd); 2658 if (err) 2659 return err; 2660 } 2661 2662 if (modify_sq) { 2663 if (tx_affinity) { 2664 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2665 tx_affinity, 2666 qp->ibqp.pd); 2667 if (err) 2668 return err; 2669 } 2670 2671 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, qp->ibqp.pd); 2672 } 2673 2674 return 0; 2675 } 2676 2677 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2678 const struct ib_qp_attr *attr, int attr_mask, 2679 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2680 { 2681 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2682 [MLX5_QP_STATE_RST] = { 2683 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2684 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2685 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2686 }, 2687 [MLX5_QP_STATE_INIT] = { 2688 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2689 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2690 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2691 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2692 }, 2693 [MLX5_QP_STATE_RTR] = { 2694 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2695 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2696 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2697 }, 2698 [MLX5_QP_STATE_RTS] = { 2699 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2700 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2701 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2702 }, 2703 [MLX5_QP_STATE_SQD] = { 2704 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2705 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2706 }, 2707 [MLX5_QP_STATE_SQER] = { 2708 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2709 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2710 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2711 }, 2712 [MLX5_QP_STATE_ERR] = { 2713 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2714 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2715 } 2716 }; 2717 2718 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2719 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2720 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2721 struct mlx5_ib_cq *send_cq, *recv_cq; 2722 struct mlx5_qp_context *context; 2723 struct mlx5_ib_pd *pd; 2724 struct mlx5_ib_port *mibport = NULL; 2725 enum mlx5_qp_state mlx5_cur, mlx5_new; 2726 enum mlx5_qp_optpar optpar; 2727 int sqd_event; 2728 int mlx5_st; 2729 int err; 2730 u16 op; 2731 2732 context = kzalloc(sizeof(*context), GFP_KERNEL); 2733 if (!context) 2734 return -ENOMEM; 2735 2736 err = to_mlx5_st(ibqp->qp_type); 2737 if (err < 0) { 2738 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2739 goto out; 2740 } 2741 2742 context->flags = cpu_to_be32(err << 16); 2743 2744 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2745 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2746 } else { 2747 switch (attr->path_mig_state) { 2748 case IB_MIG_MIGRATED: 2749 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2750 break; 2751 case IB_MIG_REARM: 2752 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2753 break; 2754 case IB_MIG_ARMED: 2755 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2756 break; 2757 } 2758 } 2759 2760 if (is_sqp(ibqp->qp_type)) { 2761 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2762 } else if (ibqp->qp_type == IB_QPT_UD || 2763 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2764 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2765 } else if (attr_mask & IB_QP_PATH_MTU) { 2766 if (attr->path_mtu < IB_MTU_256 || 2767 attr->path_mtu > IB_MTU_4096) { 2768 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2769 err = -EINVAL; 2770 goto out; 2771 } 2772 context->mtu_msgmax = (attr->path_mtu << 5) | 2773 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2774 } 2775 2776 if (attr_mask & IB_QP_DEST_QPN) 2777 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2778 2779 if (attr_mask & IB_QP_PKEY_INDEX) 2780 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 2781 2782 /* todo implement counter_index functionality */ 2783 2784 if (is_sqp(ibqp->qp_type)) 2785 context->pri_path.port = qp->port; 2786 2787 if (attr_mask & IB_QP_PORT) 2788 context->pri_path.port = attr->port_num; 2789 2790 if (attr_mask & IB_QP_AV) { 2791 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2792 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2793 attr_mask, 0, attr, false); 2794 if (err) 2795 goto out; 2796 } 2797 2798 if (attr_mask & IB_QP_TIMEOUT) 2799 context->pri_path.ackto_lt |= attr->timeout << 3; 2800 2801 if (attr_mask & IB_QP_ALT_PATH) { 2802 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2803 &context->alt_path, 2804 attr->alt_port_num, 2805 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 2806 0, attr, true); 2807 if (err) 2808 goto out; 2809 } 2810 2811 pd = get_pd(qp); 2812 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2813 &send_cq, &recv_cq); 2814 2815 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2816 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2817 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2818 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2819 2820 if (attr_mask & IB_QP_RNR_RETRY) 2821 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2822 2823 if (attr_mask & IB_QP_RETRY_CNT) 2824 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2825 2826 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2827 if (attr->max_rd_atomic) 2828 context->params1 |= 2829 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2830 } 2831 2832 if (attr_mask & IB_QP_SQ_PSN) 2833 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2834 2835 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2836 if (attr->max_dest_rd_atomic) 2837 context->params2 |= 2838 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2839 } 2840 2841 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2842 __be32 access_flags; 2843 2844 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); 2845 if (err) 2846 goto out; 2847 2848 context->params2 |= access_flags; 2849 } 2850 2851 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2852 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2853 2854 if (attr_mask & IB_QP_RQ_PSN) 2855 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2856 2857 if (attr_mask & IB_QP_QKEY) 2858 context->qkey = cpu_to_be32(attr->qkey); 2859 2860 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2861 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2862 2863 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2864 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2865 sqd_event = 1; 2866 else 2867 sqd_event = 0; 2868 2869 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2870 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 2871 qp->port) - 1; 2872 mibport = &dev->port[port_num]; 2873 context->qp_counter_set_usr_page |= 2874 cpu_to_be32((u32)(mibport->q_cnt_id) << 24); 2875 } 2876 2877 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2878 context->sq_crq_size |= cpu_to_be16(1 << 4); 2879 2880 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 2881 context->deth_sqpn = cpu_to_be32(1); 2882 2883 mlx5_cur = to_mlx5_state(cur_state); 2884 mlx5_new = to_mlx5_state(new_state); 2885 mlx5_st = to_mlx5_st(ibqp->qp_type); 2886 if (mlx5_st < 0) 2887 goto out; 2888 2889 /* If moving to a reset or error state, we must disable page faults on 2890 * this QP and flush all current page faults. Otherwise a stale page 2891 * fault may attempt to work on this QP after it is reset and moved 2892 * again to RTS, and may cause the driver and the device to get out of 2893 * sync. */ 2894 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2895 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) && 2896 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2897 mlx5_ib_qp_disable_pagefaults(qp); 2898 2899 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2900 !optab[mlx5_cur][mlx5_new]) 2901 goto out; 2902 2903 op = optab[mlx5_cur][mlx5_new]; 2904 optpar = ib_mask_to_mlx5_opt(attr_mask); 2905 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2906 2907 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 2908 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 2909 2910 raw_qp_param.operation = op; 2911 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2912 raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id; 2913 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 2914 } 2915 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2916 } else { 2917 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 2918 &base->mqp); 2919 } 2920 2921 if (err) 2922 goto out; 2923 2924 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT && 2925 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2926 mlx5_ib_qp_enable_pagefaults(qp); 2927 2928 qp->state = new_state; 2929 2930 if (attr_mask & IB_QP_ACCESS_FLAGS) 2931 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2932 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2933 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2934 if (attr_mask & IB_QP_PORT) 2935 qp->port = attr->port_num; 2936 if (attr_mask & IB_QP_ALT_PATH) 2937 qp->trans_qp.alt_port = attr->alt_port_num; 2938 2939 /* 2940 * If we moved a kernel QP to RESET, clean up all old CQ 2941 * entries and reinitialize the QP. 2942 */ 2943 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2944 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2945 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2946 if (send_cq != recv_cq) 2947 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2948 2949 qp->rq.head = 0; 2950 qp->rq.tail = 0; 2951 qp->sq.head = 0; 2952 qp->sq.tail = 0; 2953 qp->sq.cur_post = 0; 2954 qp->sq.last_poll = 0; 2955 qp->db.db[MLX5_RCV_DBR] = 0; 2956 qp->db.db[MLX5_SND_DBR] = 0; 2957 } 2958 2959 out: 2960 kfree(context); 2961 return err; 2962 } 2963 2964 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2965 int attr_mask, struct ib_udata *udata) 2966 { 2967 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2968 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2969 enum ib_qp_type qp_type; 2970 enum ib_qp_state cur_state, new_state; 2971 int err = -EINVAL; 2972 int port; 2973 2974 if (ibqp->rwq_ind_tbl) 2975 return -ENOSYS; 2976 2977 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 2978 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 2979 2980 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 2981 IB_QPT_GSI : ibqp->qp_type; 2982 2983 mutex_lock(&qp->mutex); 2984 2985 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2986 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2987 2988 if (qp_type != MLX5_IB_QPT_REG_UMR && 2989 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask)) { 2990 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 2991 cur_state, new_state, ibqp->qp_type, attr_mask); 2992 goto out; 2993 } 2994 2995 if ((attr_mask & IB_QP_PORT) && 2996 (attr->port_num == 0 || 2997 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) { 2998 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 2999 attr->port_num, dev->num_ports); 3000 goto out; 3001 } 3002 3003 if (attr_mask & IB_QP_PKEY_INDEX) { 3004 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3005 if (attr->pkey_index >= 3006 dev->mdev->port_caps[port - 1].pkey_table_len) { 3007 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3008 attr->pkey_index); 3009 goto out; 3010 } 3011 } 3012 3013 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3014 attr->max_rd_atomic > 3015 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3016 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3017 attr->max_rd_atomic); 3018 goto out; 3019 } 3020 3021 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3022 attr->max_dest_rd_atomic > 3023 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3024 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3025 attr->max_dest_rd_atomic); 3026 goto out; 3027 } 3028 3029 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3030 err = 0; 3031 goto out; 3032 } 3033 3034 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 3035 3036 out: 3037 mutex_unlock(&qp->mutex); 3038 return err; 3039 } 3040 3041 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3042 { 3043 struct mlx5_ib_cq *cq; 3044 unsigned cur; 3045 3046 cur = wq->head - wq->tail; 3047 if (likely(cur + nreq < wq->max_post)) 3048 return 0; 3049 3050 cq = to_mcq(ib_cq); 3051 spin_lock(&cq->lock); 3052 cur = wq->head - wq->tail; 3053 spin_unlock(&cq->lock); 3054 3055 return cur + nreq >= wq->max_post; 3056 } 3057 3058 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3059 u64 remote_addr, u32 rkey) 3060 { 3061 rseg->raddr = cpu_to_be64(remote_addr); 3062 rseg->rkey = cpu_to_be32(rkey); 3063 rseg->reserved = 0; 3064 } 3065 3066 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3067 const struct ib_send_wr *wr, void *qend, 3068 struct mlx5_ib_qp *qp, int *size) 3069 { 3070 void *seg = eseg; 3071 3072 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3073 3074 if (wr->send_flags & IB_SEND_IP_CSUM) 3075 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3076 MLX5_ETH_WQE_L4_CSUM; 3077 3078 seg += sizeof(struct mlx5_wqe_eth_seg); 3079 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3080 3081 if (wr->opcode == IB_WR_LSO) { 3082 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3083 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start); 3084 u64 left, leftlen, copysz; 3085 void *pdata = ud_wr->header; 3086 3087 left = ud_wr->hlen; 3088 eseg->mss = cpu_to_be16(ud_wr->mss); 3089 eseg->inline_hdr_sz = cpu_to_be16(left); 3090 3091 /* 3092 * check if there is space till the end of queue, if yes, 3093 * copy all in one shot, otherwise copy till the end of queue, 3094 * rollback and than the copy the left 3095 */ 3096 leftlen = qend - (void *)eseg->inline_hdr_start; 3097 copysz = min_t(u64, leftlen, left); 3098 3099 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3100 3101 if (likely(copysz > size_of_inl_hdr_start)) { 3102 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3103 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3104 } 3105 3106 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3107 seg = mlx5_get_send_wqe(qp, 0); 3108 left -= copysz; 3109 pdata += copysz; 3110 memcpy(seg, pdata, left); 3111 seg += ALIGN(left, 16); 3112 *size += ALIGN(left, 16) / 16; 3113 } 3114 } 3115 3116 return seg; 3117 } 3118 3119 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3120 const struct ib_send_wr *wr) 3121 { 3122 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3123 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3124 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3125 } 3126 3127 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3128 { 3129 dseg->byte_count = cpu_to_be32(sg->length); 3130 dseg->lkey = cpu_to_be32(sg->lkey); 3131 dseg->addr = cpu_to_be64(sg->addr); 3132 } 3133 3134 static __be16 get_klm_octo(int npages) 3135 { 3136 return cpu_to_be16(ALIGN(npages, 8) / 2); 3137 } 3138 3139 static __be64 frwr_mkey_mask(void) 3140 { 3141 u64 result; 3142 3143 result = MLX5_MKEY_MASK_LEN | 3144 MLX5_MKEY_MASK_PAGE_SIZE | 3145 MLX5_MKEY_MASK_START_ADDR | 3146 MLX5_MKEY_MASK_EN_RINVAL | 3147 MLX5_MKEY_MASK_KEY | 3148 MLX5_MKEY_MASK_LR | 3149 MLX5_MKEY_MASK_LW | 3150 MLX5_MKEY_MASK_RR | 3151 MLX5_MKEY_MASK_RW | 3152 MLX5_MKEY_MASK_A | 3153 MLX5_MKEY_MASK_SMALL_FENCE | 3154 MLX5_MKEY_MASK_FREE; 3155 3156 return cpu_to_be64(result); 3157 } 3158 3159 static __be64 sig_mkey_mask(void) 3160 { 3161 u64 result; 3162 3163 result = MLX5_MKEY_MASK_LEN | 3164 MLX5_MKEY_MASK_PAGE_SIZE | 3165 MLX5_MKEY_MASK_START_ADDR | 3166 MLX5_MKEY_MASK_EN_SIGERR | 3167 MLX5_MKEY_MASK_EN_RINVAL | 3168 MLX5_MKEY_MASK_KEY | 3169 MLX5_MKEY_MASK_LR | 3170 MLX5_MKEY_MASK_LW | 3171 MLX5_MKEY_MASK_RR | 3172 MLX5_MKEY_MASK_RW | 3173 MLX5_MKEY_MASK_SMALL_FENCE | 3174 MLX5_MKEY_MASK_FREE | 3175 MLX5_MKEY_MASK_BSF_EN; 3176 3177 return cpu_to_be64(result); 3178 } 3179 3180 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3181 struct mlx5_ib_mr *mr) 3182 { 3183 int ndescs = mr->ndescs; 3184 3185 memset(umr, 0, sizeof(*umr)); 3186 3187 if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 3188 /* KLMs take twice the size of MTTs */ 3189 ndescs *= 2; 3190 3191 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3192 umr->klm_octowords = get_klm_octo(ndescs); 3193 umr->mkey_mask = frwr_mkey_mask(); 3194 } 3195 3196 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3197 { 3198 memset(umr, 0, sizeof(*umr)); 3199 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3200 umr->flags = 1 << 7; 3201 } 3202 3203 static __be64 get_umr_reg_mr_mask(void) 3204 { 3205 u64 result; 3206 3207 result = MLX5_MKEY_MASK_LEN | 3208 MLX5_MKEY_MASK_PAGE_SIZE | 3209 MLX5_MKEY_MASK_START_ADDR | 3210 MLX5_MKEY_MASK_PD | 3211 MLX5_MKEY_MASK_LR | 3212 MLX5_MKEY_MASK_LW | 3213 MLX5_MKEY_MASK_KEY | 3214 MLX5_MKEY_MASK_RR | 3215 MLX5_MKEY_MASK_RW | 3216 MLX5_MKEY_MASK_A | 3217 MLX5_MKEY_MASK_FREE; 3218 3219 return cpu_to_be64(result); 3220 } 3221 3222 static __be64 get_umr_unreg_mr_mask(void) 3223 { 3224 u64 result; 3225 3226 result = MLX5_MKEY_MASK_FREE; 3227 3228 return cpu_to_be64(result); 3229 } 3230 3231 static __be64 get_umr_update_mtt_mask(void) 3232 { 3233 u64 result; 3234 3235 result = MLX5_MKEY_MASK_FREE; 3236 3237 return cpu_to_be64(result); 3238 } 3239 3240 static __be64 get_umr_update_translation_mask(void) 3241 { 3242 u64 result; 3243 3244 result = MLX5_MKEY_MASK_LEN | 3245 MLX5_MKEY_MASK_PAGE_SIZE | 3246 MLX5_MKEY_MASK_START_ADDR | 3247 MLX5_MKEY_MASK_KEY | 3248 MLX5_MKEY_MASK_FREE; 3249 3250 return cpu_to_be64(result); 3251 } 3252 3253 static __be64 get_umr_update_access_mask(void) 3254 { 3255 u64 result; 3256 3257 result = MLX5_MKEY_MASK_LW | 3258 MLX5_MKEY_MASK_RR | 3259 MLX5_MKEY_MASK_RW | 3260 MLX5_MKEY_MASK_A | 3261 MLX5_MKEY_MASK_KEY | 3262 MLX5_MKEY_MASK_FREE; 3263 3264 return cpu_to_be64(result); 3265 } 3266 3267 static __be64 get_umr_update_pd_mask(void) 3268 { 3269 u64 result; 3270 3271 result = MLX5_MKEY_MASK_PD | 3272 MLX5_MKEY_MASK_KEY | 3273 MLX5_MKEY_MASK_FREE; 3274 3275 return cpu_to_be64(result); 3276 } 3277 3278 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3279 const struct ib_send_wr *wr) 3280 { 3281 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 3282 3283 memset(umr, 0, sizeof(*umr)); 3284 3285 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3286 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3287 else 3288 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3289 3290 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) { 3291 umr->klm_octowords = get_klm_octo(umrwr->npages); 3292 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) { 3293 umr->mkey_mask = get_umr_update_mtt_mask(); 3294 umr->bsf_octowords = get_klm_octo(umrwr->target.offset); 3295 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3296 } 3297 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3298 umr->mkey_mask |= get_umr_update_translation_mask(); 3299 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS) 3300 umr->mkey_mask |= get_umr_update_access_mask(); 3301 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD) 3302 umr->mkey_mask |= get_umr_update_pd_mask(); 3303 if (!umr->mkey_mask) 3304 umr->mkey_mask = get_umr_reg_mr_mask(); 3305 } else { 3306 umr->mkey_mask = get_umr_unreg_mr_mask(); 3307 } 3308 3309 if (!wr->num_sge) 3310 umr->flags |= MLX5_UMR_INLINE; 3311 } 3312 3313 static u8 get_umr_flags(int acc) 3314 { 3315 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3316 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3317 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3318 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3319 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3320 } 3321 3322 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3323 struct mlx5_ib_mr *mr, 3324 u32 key, int access) 3325 { 3326 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3327 3328 memset(seg, 0, sizeof(*seg)); 3329 3330 if (mr->access_mode == MLX5_ACCESS_MODE_MTT) 3331 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3332 else if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 3333 /* KLMs take twice the size of MTTs */ 3334 ndescs *= 2; 3335 3336 seg->flags = get_umr_flags(access) | mr->access_mode; 3337 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3338 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3339 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3340 seg->len = cpu_to_be64(mr->ibmr.length); 3341 seg->xlt_oct_size = cpu_to_be32(ndescs); 3342 } 3343 3344 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3345 { 3346 memset(seg, 0, sizeof(*seg)); 3347 seg->status = MLX5_MKEY_STATUS_FREE; 3348 } 3349 3350 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, const struct ib_send_wr *wr) 3351 { 3352 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 3353 3354 memset(seg, 0, sizeof(*seg)); 3355 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) { 3356 seg->status = MLX5_MKEY_STATUS_FREE; 3357 return; 3358 } 3359 3360 seg->flags = convert_access(umrwr->access_flags); 3361 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) { 3362 if (umrwr->pd) 3363 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3364 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr); 3365 } 3366 seg->len = cpu_to_be64(umrwr->length); 3367 seg->log2_page_size = umrwr->page_shift; 3368 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3369 mlx5_mkey_variant(umrwr->mkey)); 3370 } 3371 3372 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3373 struct mlx5_ib_mr *mr, 3374 struct mlx5_ib_pd *pd) 3375 { 3376 int bcount = mr->desc_size * mr->ndescs; 3377 3378 dseg->addr = cpu_to_be64(mr->desc_map); 3379 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3380 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3381 } 3382 3383 static __be32 send_ieth(const struct ib_send_wr *wr) 3384 { 3385 switch (wr->opcode) { 3386 case IB_WR_SEND_WITH_IMM: 3387 case IB_WR_RDMA_WRITE_WITH_IMM: 3388 return wr->ex.imm_data; 3389 3390 case IB_WR_SEND_WITH_INV: 3391 return cpu_to_be32(wr->ex.invalidate_rkey); 3392 3393 default: 3394 return 0; 3395 } 3396 } 3397 3398 static u8 calc_sig(void *wqe, int size) 3399 { 3400 u8 *p = wqe; 3401 u8 res = 0; 3402 int i; 3403 3404 for (i = 0; i < size; i++) 3405 res ^= p[i]; 3406 3407 return ~res; 3408 } 3409 3410 static u8 wq_sig(void *wqe) 3411 { 3412 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3413 } 3414 3415 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, 3416 void *wqe, int *sz) 3417 { 3418 struct mlx5_wqe_inline_seg *seg; 3419 void *qend = qp->sq.qend; 3420 void *addr; 3421 int inl = 0; 3422 int copy; 3423 int len; 3424 int i; 3425 3426 seg = wqe; 3427 wqe += sizeof(*seg); 3428 for (i = 0; i < wr->num_sge; i++) { 3429 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3430 len = wr->sg_list[i].length; 3431 inl += len; 3432 3433 if (unlikely(inl > qp->max_inline_data)) 3434 return -ENOMEM; 3435 3436 if (unlikely(wqe + len > qend)) { 3437 copy = qend - wqe; 3438 memcpy(wqe, addr, copy); 3439 addr += copy; 3440 len -= copy; 3441 wqe = mlx5_get_send_wqe(qp, 0); 3442 } 3443 memcpy(wqe, addr, len); 3444 wqe += len; 3445 } 3446 3447 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3448 3449 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3450 3451 return 0; 3452 } 3453 3454 static u16 prot_field_size(enum ib_signature_type type) 3455 { 3456 switch (type) { 3457 case IB_SIG_TYPE_T10_DIF: 3458 return MLX5_DIF_SIZE; 3459 default: 3460 return 0; 3461 } 3462 } 3463 3464 static u8 bs_selector(int block_size) 3465 { 3466 switch (block_size) { 3467 case 512: return 0x1; 3468 case 520: return 0x2; 3469 case 4096: return 0x3; 3470 case 4160: return 0x4; 3471 case 1073741824: return 0x5; 3472 default: return 0; 3473 } 3474 } 3475 3476 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3477 struct mlx5_bsf_inl *inl) 3478 { 3479 /* Valid inline section and allow BSF refresh */ 3480 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3481 MLX5_BSF_REFRESH_DIF); 3482 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3483 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3484 /* repeating block */ 3485 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3486 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3487 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3488 3489 if (domain->sig.dif.ref_remap) 3490 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3491 3492 if (domain->sig.dif.app_escape) { 3493 if (domain->sig.dif.ref_escape) 3494 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3495 else 3496 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3497 } 3498 3499 inl->dif_app_bitmask_check = 3500 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3501 } 3502 3503 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3504 struct ib_sig_attrs *sig_attrs, 3505 struct mlx5_bsf *bsf, u32 data_size) 3506 { 3507 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3508 struct mlx5_bsf_basic *basic = &bsf->basic; 3509 struct ib_sig_domain *mem = &sig_attrs->mem; 3510 struct ib_sig_domain *wire = &sig_attrs->wire; 3511 3512 memset(bsf, 0, sizeof(*bsf)); 3513 3514 /* Basic + Extended + Inline */ 3515 basic->bsf_size_sbs = 1 << 7; 3516 /* Input domain check byte mask */ 3517 basic->check_byte_mask = sig_attrs->check_mask; 3518 basic->raw_data_size = cpu_to_be32(data_size); 3519 3520 /* Memory domain */ 3521 switch (sig_attrs->mem.sig_type) { 3522 case IB_SIG_TYPE_NONE: 3523 break; 3524 case IB_SIG_TYPE_T10_DIF: 3525 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3526 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3527 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3528 break; 3529 default: 3530 return -EINVAL; 3531 } 3532 3533 /* Wire domain */ 3534 switch (sig_attrs->wire.sig_type) { 3535 case IB_SIG_TYPE_NONE: 3536 break; 3537 case IB_SIG_TYPE_T10_DIF: 3538 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3539 mem->sig_type == wire->sig_type) { 3540 /* Same block structure */ 3541 basic->bsf_size_sbs |= 1 << 4; 3542 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3543 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3544 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3545 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3546 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3547 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3548 } else 3549 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3550 3551 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3552 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3553 break; 3554 default: 3555 return -EINVAL; 3556 } 3557 3558 return 0; 3559 } 3560 3561 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr, 3562 struct mlx5_ib_qp *qp, void **seg, int *size) 3563 { 3564 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3565 struct ib_mr *sig_mr = wr->sig_mr; 3566 struct mlx5_bsf *bsf; 3567 u32 data_len = wr->wr.sg_list->length; 3568 u32 data_key = wr->wr.sg_list->lkey; 3569 u64 data_va = wr->wr.sg_list->addr; 3570 int ret; 3571 int wqe_size; 3572 3573 if (!wr->prot || 3574 (data_key == wr->prot->lkey && 3575 data_va == wr->prot->addr && 3576 data_len == wr->prot->length)) { 3577 /** 3578 * Source domain doesn't contain signature information 3579 * or data and protection are interleaved in memory. 3580 * So need construct: 3581 * ------------------ 3582 * | data_klm | 3583 * ------------------ 3584 * | BSF | 3585 * ------------------ 3586 **/ 3587 struct mlx5_klm *data_klm = *seg; 3588 3589 data_klm->bcount = cpu_to_be32(data_len); 3590 data_klm->key = cpu_to_be32(data_key); 3591 data_klm->va = cpu_to_be64(data_va); 3592 wqe_size = ALIGN(sizeof(*data_klm), 64); 3593 } else { 3594 /** 3595 * Source domain contains signature information 3596 * So need construct a strided block format: 3597 * --------------------------- 3598 * | stride_block_ctrl | 3599 * --------------------------- 3600 * | data_klm | 3601 * --------------------------- 3602 * | prot_klm | 3603 * --------------------------- 3604 * | BSF | 3605 * --------------------------- 3606 **/ 3607 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3608 struct mlx5_stride_block_entry *data_sentry; 3609 struct mlx5_stride_block_entry *prot_sentry; 3610 u32 prot_key = wr->prot->lkey; 3611 u64 prot_va = wr->prot->addr; 3612 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3613 int prot_size; 3614 3615 sblock_ctrl = *seg; 3616 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3617 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3618 3619 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3620 if (!prot_size) { 3621 pr_err("Bad block size given: %u\n", block_size); 3622 return -EINVAL; 3623 } 3624 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3625 prot_size); 3626 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3627 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3628 sblock_ctrl->num_entries = cpu_to_be16(2); 3629 3630 data_sentry->bcount = cpu_to_be16(block_size); 3631 data_sentry->key = cpu_to_be32(data_key); 3632 data_sentry->va = cpu_to_be64(data_va); 3633 data_sentry->stride = cpu_to_be16(block_size); 3634 3635 prot_sentry->bcount = cpu_to_be16(prot_size); 3636 prot_sentry->key = cpu_to_be32(prot_key); 3637 prot_sentry->va = cpu_to_be64(prot_va); 3638 prot_sentry->stride = cpu_to_be16(prot_size); 3639 3640 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3641 sizeof(*prot_sentry), 64); 3642 } 3643 3644 *seg += wqe_size; 3645 *size += wqe_size / 16; 3646 if (unlikely((*seg == qp->sq.qend))) 3647 *seg = mlx5_get_send_wqe(qp, 0); 3648 3649 bsf = *seg; 3650 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 3651 if (ret) 3652 return -EINVAL; 3653 3654 *seg += sizeof(*bsf); 3655 *size += sizeof(*bsf) / 16; 3656 if (unlikely((*seg == qp->sq.qend))) 3657 *seg = mlx5_get_send_wqe(qp, 0); 3658 3659 return 0; 3660 } 3661 3662 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 3663 const struct ib_sig_handover_wr *wr, u32 nelements, 3664 u32 length, u32 pdn) 3665 { 3666 struct ib_mr *sig_mr = wr->sig_mr; 3667 u32 sig_key = sig_mr->rkey; 3668 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 3669 3670 memset(seg, 0, sizeof(*seg)); 3671 3672 seg->flags = get_umr_flags(wr->access_flags) | 3673 MLX5_ACCESS_MODE_KLM; 3674 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 3675 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 3676 MLX5_MKEY_BSF_EN | pdn); 3677 seg->len = cpu_to_be64(length); 3678 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements))); 3679 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 3680 } 3681 3682 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3683 u32 nelements) 3684 { 3685 memset(umr, 0, sizeof(*umr)); 3686 3687 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 3688 umr->klm_octowords = get_klm_octo(nelements); 3689 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 3690 umr->mkey_mask = sig_mkey_mask(); 3691 } 3692 3693 3694 static int set_sig_umr_wr(const struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 3695 void **seg, int *size) 3696 { 3697 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 3698 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 3699 u32 pdn = get_pd(qp)->pdn; 3700 u32 klm_oct_size; 3701 int region_len, ret; 3702 3703 if (unlikely(wr->wr.num_sge != 1) || 3704 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 3705 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 3706 unlikely(!sig_mr->sig->sig_status_checked)) 3707 return -EINVAL; 3708 3709 /* length of the protected region, data + protection */ 3710 region_len = wr->wr.sg_list->length; 3711 if (wr->prot && 3712 (wr->prot->lkey != wr->wr.sg_list->lkey || 3713 wr->prot->addr != wr->wr.sg_list->addr || 3714 wr->prot->length != wr->wr.sg_list->length)) 3715 region_len += wr->prot->length; 3716 3717 /** 3718 * KLM octoword size - if protection was provided 3719 * then we use strided block format (3 octowords), 3720 * else we use single KLM (1 octoword) 3721 **/ 3722 klm_oct_size = wr->prot ? 3 : 1; 3723 3724 set_sig_umr_segment(*seg, klm_oct_size); 3725 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3726 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3727 if (unlikely((*seg == qp->sq.qend))) 3728 *seg = mlx5_get_send_wqe(qp, 0); 3729 3730 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn); 3731 *seg += sizeof(struct mlx5_mkey_seg); 3732 *size += sizeof(struct mlx5_mkey_seg) / 16; 3733 if (unlikely((*seg == qp->sq.qend))) 3734 *seg = mlx5_get_send_wqe(qp, 0); 3735 3736 ret = set_sig_data_segment(wr, qp, seg, size); 3737 if (ret) 3738 return ret; 3739 3740 sig_mr->sig->sig_status_checked = false; 3741 return 0; 3742 } 3743 3744 static int set_psv_wr(struct ib_sig_domain *domain, 3745 u32 psv_idx, void **seg, int *size) 3746 { 3747 struct mlx5_seg_set_psv *psv_seg = *seg; 3748 3749 memset(psv_seg, 0, sizeof(*psv_seg)); 3750 psv_seg->psv_num = cpu_to_be32(psv_idx); 3751 switch (domain->sig_type) { 3752 case IB_SIG_TYPE_NONE: 3753 break; 3754 case IB_SIG_TYPE_T10_DIF: 3755 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3756 domain->sig.dif.app_tag); 3757 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3758 break; 3759 default: 3760 pr_err("Bad signature type given.\n"); 3761 return 1; 3762 } 3763 3764 *seg += sizeof(*psv_seg); 3765 *size += sizeof(*psv_seg) / 16; 3766 3767 return 0; 3768 } 3769 3770 static int set_reg_wr(struct mlx5_ib_qp *qp, 3771 const struct ib_reg_wr *wr, 3772 void **seg, int *size) 3773 { 3774 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3775 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3776 3777 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3778 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3779 "Invalid IB_SEND_INLINE send flag\n"); 3780 return -EINVAL; 3781 } 3782 3783 set_reg_umr_seg(*seg, mr); 3784 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3785 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3786 if (unlikely((*seg == qp->sq.qend))) 3787 *seg = mlx5_get_send_wqe(qp, 0); 3788 3789 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3790 *seg += sizeof(struct mlx5_mkey_seg); 3791 *size += sizeof(struct mlx5_mkey_seg) / 16; 3792 if (unlikely((*seg == qp->sq.qend))) 3793 *seg = mlx5_get_send_wqe(qp, 0); 3794 3795 set_reg_data_seg(*seg, mr, pd); 3796 *seg += sizeof(struct mlx5_wqe_data_seg); 3797 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3798 3799 return 0; 3800 } 3801 3802 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3803 { 3804 set_linv_umr_seg(*seg); 3805 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3806 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3807 if (unlikely((*seg == qp->sq.qend))) 3808 *seg = mlx5_get_send_wqe(qp, 0); 3809 set_linv_mkey_seg(*seg); 3810 *seg += sizeof(struct mlx5_mkey_seg); 3811 *size += sizeof(struct mlx5_mkey_seg) / 16; 3812 if (unlikely((*seg == qp->sq.qend))) 3813 *seg = mlx5_get_send_wqe(qp, 0); 3814 } 3815 3816 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3817 { 3818 __be32 *p = NULL; 3819 int tidx = idx; 3820 int i, j; 3821 3822 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3823 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3824 if ((i & 0xf) == 0) { 3825 void *buf = mlx5_get_send_wqe(qp, tidx); 3826 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3827 p = buf; 3828 j = 0; 3829 } 3830 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3831 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3832 be32_to_cpu(p[j + 3])); 3833 } 3834 } 3835 3836 static u8 get_fence(u8 fence, const struct ib_send_wr *wr) 3837 { 3838 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 3839 wr->send_flags & IB_SEND_FENCE)) 3840 return MLX5_FENCE_MODE_STRONG_ORDERING; 3841 3842 if (unlikely(fence)) { 3843 if (wr->send_flags & IB_SEND_FENCE) 3844 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 3845 else 3846 return fence; 3847 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) { 3848 return MLX5_FENCE_MODE_FENCE; 3849 } 3850 3851 return 0; 3852 } 3853 3854 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3855 struct mlx5_wqe_ctrl_seg **ctrl, 3856 const struct ib_send_wr *wr, unsigned *idx, 3857 int *size, int nreq, int send_flags) 3858 { 3859 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 3860 return -ENOMEM; 3861 3862 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3863 *seg = mlx5_get_send_wqe(qp, *idx); 3864 *ctrl = *seg; 3865 *(uint32_t *)(*seg + 8) = 0; 3866 (*ctrl)->imm = send_ieth(wr); 3867 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3868 (send_flags & IB_SEND_SIGNALED ? 3869 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3870 (send_flags & IB_SEND_SOLICITED ? 3871 MLX5_WQE_CTRL_SOLICITED : 0); 3872 3873 *seg += sizeof(**ctrl); 3874 *size = sizeof(**ctrl) / 16; 3875 3876 return 0; 3877 } 3878 3879 static void finish_wqe(struct mlx5_ib_qp *qp, 3880 struct mlx5_wqe_ctrl_seg *ctrl, 3881 u8 size, unsigned idx, u64 wr_id, 3882 int nreq, u8 fence, u8 next_fence, 3883 u32 mlx5_opcode) 3884 { 3885 u8 opmod = 0; 3886 3887 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3888 mlx5_opcode | ((u32)opmod << 24)); 3889 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3890 ctrl->fm_ce_se |= fence; 3891 qp->fm_cache = next_fence; 3892 if (unlikely(qp->wq_sig)) 3893 ctrl->signature = wq_sig(ctrl); 3894 3895 qp->sq.wrid[idx] = wr_id; 3896 qp->sq.w_list[idx].opcode = mlx5_opcode; 3897 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3898 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3899 qp->sq.w_list[idx].next = qp->sq.cur_post; 3900 } 3901 3902 3903 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3904 const struct ib_send_wr **bad_wr) 3905 { 3906 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3907 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3908 struct mlx5_core_dev *mdev = dev->mdev; 3909 struct mlx5_ib_qp *qp; 3910 struct mlx5_ib_mr *mr; 3911 struct mlx5_wqe_data_seg *dpseg; 3912 struct mlx5_wqe_xrc_seg *xrc; 3913 struct mlx5_bf *bf; 3914 int uninitialized_var(size); 3915 void *qend; 3916 unsigned long flags; 3917 unsigned idx; 3918 int err = 0; 3919 int inl = 0; 3920 int num_sge; 3921 void *seg; 3922 int nreq; 3923 int i; 3924 u8 next_fence = 0; 3925 u8 fence; 3926 3927 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3928 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 3929 3930 qp = to_mqp(ibqp); 3931 bf = &qp->bf; 3932 qend = qp->sq.qend; 3933 3934 spin_lock_irqsave(&qp->sq.lock, flags); 3935 3936 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 3937 err = -EIO; 3938 *bad_wr = wr; 3939 nreq = 0; 3940 goto out; 3941 } 3942 3943 for (nreq = 0; wr; nreq++, wr = wr->next) { 3944 if (unlikely(wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3945 mlx5_ib_warn(dev, "\n"); 3946 err = -EINVAL; 3947 *bad_wr = wr; 3948 goto out; 3949 } 3950 3951 fence = qp->fm_cache; 3952 num_sge = wr->num_sge; 3953 if (unlikely(num_sge > qp->sq.max_gs)) { 3954 mlx5_ib_warn(dev, "\n"); 3955 err = -EINVAL; 3956 *bad_wr = wr; 3957 goto out; 3958 } 3959 3960 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq, wr->send_flags); 3961 if (err) { 3962 mlx5_ib_warn(dev, "\n"); 3963 err = -ENOMEM; 3964 *bad_wr = wr; 3965 goto out; 3966 } 3967 3968 switch (ibqp->qp_type) { 3969 case IB_QPT_XRC_INI: 3970 xrc = seg; 3971 seg += sizeof(*xrc); 3972 size += sizeof(*xrc) / 16; 3973 /* fall through */ 3974 case IB_QPT_RC: 3975 switch (wr->opcode) { 3976 case IB_WR_RDMA_READ: 3977 case IB_WR_RDMA_WRITE: 3978 case IB_WR_RDMA_WRITE_WITH_IMM: 3979 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3980 rdma_wr(wr)->rkey); 3981 seg += sizeof(struct mlx5_wqe_raddr_seg); 3982 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3983 break; 3984 3985 case IB_WR_ATOMIC_CMP_AND_SWP: 3986 case IB_WR_ATOMIC_FETCH_AND_ADD: 3987 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3988 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3989 err = -ENOSYS; 3990 *bad_wr = wr; 3991 goto out; 3992 3993 case IB_WR_LOCAL_INV: 3994 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3995 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 3996 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 3997 set_linv_wr(qp, &seg, &size); 3998 num_sge = 0; 3999 break; 4000 4001 case IB_WR_REG_MR: 4002 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4003 qp->sq.wr_data[idx] = IB_WR_REG_MR; 4004 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 4005 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 4006 if (err) { 4007 *bad_wr = wr; 4008 goto out; 4009 } 4010 num_sge = 0; 4011 break; 4012 4013 case IB_WR_REG_SIG_MR: 4014 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4015 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4016 4017 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4018 err = set_sig_umr_wr(wr, qp, &seg, &size); 4019 if (err) { 4020 mlx5_ib_warn(dev, "\n"); 4021 *bad_wr = wr; 4022 goto out; 4023 } 4024 4025 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4026 nreq, get_fence(fence, wr), 4027 next_fence, MLX5_OPCODE_UMR); 4028 /* 4029 * SET_PSV WQEs are not signaled and solicited 4030 * on error 4031 */ 4032 err = begin_wqe(qp, &seg, &ctrl, wr, 4033 &idx, &size, nreq, IB_SEND_SOLICITED); 4034 if (err) { 4035 mlx5_ib_warn(dev, "\n"); 4036 err = -ENOMEM; 4037 *bad_wr = wr; 4038 goto out; 4039 } 4040 4041 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4042 mr->sig->psv_memory.psv_idx, &seg, 4043 &size); 4044 if (err) { 4045 mlx5_ib_warn(dev, "\n"); 4046 *bad_wr = wr; 4047 goto out; 4048 } 4049 4050 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4051 nreq, get_fence(fence, wr), 4052 next_fence, MLX5_OPCODE_SET_PSV); 4053 err = begin_wqe(qp, &seg, &ctrl, wr, 4054 &idx, &size, nreq, wr->send_flags); 4055 if (err) { 4056 mlx5_ib_warn(dev, "\n"); 4057 err = -ENOMEM; 4058 *bad_wr = wr; 4059 goto out; 4060 } 4061 4062 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4063 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4064 mr->sig->psv_wire.psv_idx, &seg, 4065 &size); 4066 if (err) { 4067 mlx5_ib_warn(dev, "\n"); 4068 *bad_wr = wr; 4069 goto out; 4070 } 4071 4072 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4073 nreq, get_fence(fence, wr), 4074 next_fence, MLX5_OPCODE_SET_PSV); 4075 num_sge = 0; 4076 goto skip_psv; 4077 4078 default: 4079 break; 4080 } 4081 break; 4082 4083 case IB_QPT_UC: 4084 switch (wr->opcode) { 4085 case IB_WR_RDMA_WRITE: 4086 case IB_WR_RDMA_WRITE_WITH_IMM: 4087 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4088 rdma_wr(wr)->rkey); 4089 seg += sizeof(struct mlx5_wqe_raddr_seg); 4090 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4091 break; 4092 4093 default: 4094 break; 4095 } 4096 break; 4097 4098 case IB_QPT_SMI: 4099 case MLX5_IB_QPT_HW_GSI: 4100 set_datagram_seg(seg, wr); 4101 seg += sizeof(struct mlx5_wqe_datagram_seg); 4102 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4103 if (unlikely((seg == qend))) 4104 seg = mlx5_get_send_wqe(qp, 0); 4105 break; 4106 case IB_QPT_UD: 4107 set_datagram_seg(seg, wr); 4108 seg += sizeof(struct mlx5_wqe_datagram_seg); 4109 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4110 4111 if (unlikely((seg == qend))) 4112 seg = mlx5_get_send_wqe(qp, 0); 4113 4114 /* handle qp that supports ud offload */ 4115 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4116 struct mlx5_wqe_eth_pad *pad; 4117 4118 pad = seg; 4119 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4120 seg += sizeof(struct mlx5_wqe_eth_pad); 4121 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4122 4123 seg = set_eth_seg(seg, wr, qend, qp, &size); 4124 4125 if (unlikely((seg == qend))) 4126 seg = mlx5_get_send_wqe(qp, 0); 4127 } 4128 break; 4129 case MLX5_IB_QPT_REG_UMR: 4130 if (wr->opcode != MLX5_IB_WR_UMR) { 4131 err = -EINVAL; 4132 mlx5_ib_warn(dev, "bad opcode\n"); 4133 goto out; 4134 } 4135 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4136 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4137 set_reg_umr_segment(seg, wr); 4138 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4139 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4140 if (unlikely((seg == qend))) 4141 seg = mlx5_get_send_wqe(qp, 0); 4142 set_reg_mkey_segment(seg, wr); 4143 seg += sizeof(struct mlx5_mkey_seg); 4144 size += sizeof(struct mlx5_mkey_seg) / 16; 4145 if (unlikely((seg == qend))) 4146 seg = mlx5_get_send_wqe(qp, 0); 4147 break; 4148 4149 default: 4150 break; 4151 } 4152 4153 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4154 int uninitialized_var(sz); 4155 4156 err = set_data_inl_seg(qp, wr, seg, &sz); 4157 if (unlikely(err)) { 4158 mlx5_ib_warn(dev, "\n"); 4159 *bad_wr = wr; 4160 goto out; 4161 } 4162 inl = 1; 4163 size += sz; 4164 } else { 4165 dpseg = seg; 4166 for (i = 0; i < num_sge; i++) { 4167 if (unlikely(dpseg == qend)) { 4168 seg = mlx5_get_send_wqe(qp, 0); 4169 dpseg = seg; 4170 } 4171 if (likely(wr->sg_list[i].length)) { 4172 set_data_ptr_seg(dpseg, wr->sg_list + i); 4173 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4174 dpseg++; 4175 } 4176 } 4177 } 4178 4179 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4180 get_fence(fence, wr), next_fence, 4181 mlx5_ib_opcode[wr->opcode]); 4182 skip_psv: 4183 if (0) 4184 dump_wqe(qp, idx, size); 4185 } 4186 4187 out: 4188 if (likely(nreq)) { 4189 qp->sq.head += nreq; 4190 4191 /* Make sure that descriptors are written before 4192 * updating doorbell record and ringing the doorbell 4193 */ 4194 wmb(); 4195 4196 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4197 4198 /* Make sure doorbell record is visible to the HCA before 4199 * we hit doorbell */ 4200 wmb(); 4201 4202 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, 4203 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 4204 /* Make sure doorbells don't leak out of SQ spinlock 4205 * and reach the HCA out of order. 4206 */ 4207 bf->offset ^= bf->buf_size; 4208 } 4209 4210 spin_unlock_irqrestore(&qp->sq.lock, flags); 4211 4212 return err; 4213 } 4214 4215 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4216 { 4217 sig->signature = calc_sig(sig, size); 4218 } 4219 4220 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 4221 const struct ib_recv_wr **bad_wr) 4222 { 4223 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4224 struct mlx5_wqe_data_seg *scat; 4225 struct mlx5_rwqe_sig *sig; 4226 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4227 struct mlx5_core_dev *mdev = dev->mdev; 4228 unsigned long flags; 4229 int err = 0; 4230 int nreq; 4231 int ind; 4232 int i; 4233 4234 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4235 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4236 4237 spin_lock_irqsave(&qp->rq.lock, flags); 4238 4239 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4240 err = -EIO; 4241 *bad_wr = wr; 4242 nreq = 0; 4243 goto out; 4244 } 4245 4246 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4247 4248 for (nreq = 0; wr; nreq++, wr = wr->next) { 4249 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4250 err = -ENOMEM; 4251 *bad_wr = wr; 4252 goto out; 4253 } 4254 4255 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4256 err = -EINVAL; 4257 *bad_wr = wr; 4258 goto out; 4259 } 4260 4261 scat = get_recv_wqe(qp, ind); 4262 if (qp->wq_sig) 4263 scat++; 4264 4265 for (i = 0; i < wr->num_sge; i++) 4266 set_data_ptr_seg(scat + i, wr->sg_list + i); 4267 4268 if (i < qp->rq.max_gs) { 4269 scat[i].byte_count = 0; 4270 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4271 scat[i].addr = 0; 4272 } 4273 4274 if (qp->wq_sig) { 4275 sig = (struct mlx5_rwqe_sig *)scat; 4276 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4277 } 4278 4279 qp->rq.wrid[ind] = wr->wr_id; 4280 4281 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4282 } 4283 4284 out: 4285 if (likely(nreq)) { 4286 qp->rq.head += nreq; 4287 4288 /* Make sure that descriptors are written before 4289 * doorbell record. 4290 */ 4291 wmb(); 4292 4293 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4294 } 4295 4296 spin_unlock_irqrestore(&qp->rq.lock, flags); 4297 4298 return err; 4299 } 4300 4301 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4302 { 4303 switch (mlx5_state) { 4304 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4305 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4306 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4307 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4308 case MLX5_QP_STATE_SQ_DRAINING: 4309 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4310 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4311 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4312 default: return -1; 4313 } 4314 } 4315 4316 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4317 { 4318 switch (mlx5_mig_state) { 4319 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4320 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4321 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4322 default: return -1; 4323 } 4324 } 4325 4326 static int to_ib_qp_access_flags(int mlx5_flags) 4327 { 4328 int ib_flags = 0; 4329 4330 if (mlx5_flags & MLX5_QP_BIT_RRE) 4331 ib_flags |= IB_ACCESS_REMOTE_READ; 4332 if (mlx5_flags & MLX5_QP_BIT_RWE) 4333 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4334 if (mlx5_flags & MLX5_QP_BIT_RAE) 4335 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4336 4337 return ib_flags; 4338 } 4339 4340 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 4341 struct mlx5_qp_path *path) 4342 { 4343 struct mlx5_core_dev *dev = ibdev->mdev; 4344 4345 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 4346 ib_ah_attr->port_num = path->port; 4347 4348 if (ib_ah_attr->port_num == 0 || 4349 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports)) 4350 return; 4351 4352 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf; 4353 4354 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 4355 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 4356 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 4357 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 4358 if (ib_ah_attr->ah_flags) { 4359 ib_ah_attr->grh.sgid_index = path->mgid_index; 4360 ib_ah_attr->grh.hop_limit = path->hop_limit; 4361 ib_ah_attr->grh.traffic_class = 4362 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 4363 ib_ah_attr->grh.flow_label = 4364 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 4365 memcpy(ib_ah_attr->grh.dgid.raw, 4366 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 4367 } 4368 } 4369 4370 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4371 struct mlx5_ib_sq *sq, 4372 u8 *sq_state) 4373 { 4374 void *out; 4375 void *sqc; 4376 int inlen; 4377 int err; 4378 4379 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 4380 out = mlx5_vzalloc(inlen); 4381 if (!out) 4382 return -ENOMEM; 4383 4384 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 4385 if (err) 4386 goto out; 4387 4388 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 4389 *sq_state = MLX5_GET(sqc, sqc, state); 4390 sq->state = *sq_state; 4391 4392 out: 4393 kvfree(out); 4394 return err; 4395 } 4396 4397 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4398 struct mlx5_ib_rq *rq, 4399 u8 *rq_state) 4400 { 4401 void *out; 4402 void *rqc; 4403 int inlen; 4404 int err; 4405 4406 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4407 out = mlx5_vzalloc(inlen); 4408 if (!out) 4409 return -ENOMEM; 4410 4411 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4412 if (err) 4413 goto out; 4414 4415 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4416 *rq_state = MLX5_GET(rqc, rqc, state); 4417 rq->state = *rq_state; 4418 4419 out: 4420 kvfree(out); 4421 return err; 4422 } 4423 4424 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4425 struct mlx5_ib_qp *qp, u8 *qp_state) 4426 { 4427 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4428 [MLX5_RQC_STATE_RST] = { 4429 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4430 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4431 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4432 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4433 }, 4434 [MLX5_RQC_STATE_RDY] = { 4435 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4436 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4437 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4438 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4439 }, 4440 [MLX5_RQC_STATE_ERR] = { 4441 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4442 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4443 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4444 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4445 }, 4446 [MLX5_RQ_STATE_NA] = { 4447 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4448 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4449 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4450 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4451 }, 4452 }; 4453 4454 *qp_state = sqrq_trans[rq_state][sq_state]; 4455 4456 if (*qp_state == MLX5_QP_STATE_BAD) { 4457 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4458 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4459 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4460 return -EINVAL; 4461 } 4462 4463 if (*qp_state == MLX5_QP_STATE) 4464 *qp_state = qp->state; 4465 4466 return 0; 4467 } 4468 4469 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4470 struct mlx5_ib_qp *qp, 4471 u8 *raw_packet_qp_state) 4472 { 4473 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4474 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4475 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4476 int err; 4477 u8 sq_state = MLX5_SQ_STATE_NA; 4478 u8 rq_state = MLX5_RQ_STATE_NA; 4479 4480 if (qp->sq.wqe_cnt) { 4481 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4482 if (err) 4483 return err; 4484 } 4485 4486 if (qp->rq.wqe_cnt) { 4487 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4488 if (err) 4489 return err; 4490 } 4491 4492 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4493 raw_packet_qp_state); 4494 } 4495 4496 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4497 struct ib_qp_attr *qp_attr) 4498 { 4499 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4500 struct mlx5_qp_context *context; 4501 int mlx5_state; 4502 u32 *outb; 4503 int err = 0; 4504 4505 outb = kzalloc(outlen, GFP_KERNEL); 4506 if (!outb) 4507 return -ENOMEM; 4508 4509 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4510 outlen); 4511 if (err) 4512 goto out; 4513 4514 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4515 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4516 4517 mlx5_state = be32_to_cpu(context->flags) >> 28; 4518 4519 qp->state = to_ib_qp_state(mlx5_state); 4520 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4521 qp_attr->path_mig_state = 4522 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4523 qp_attr->qkey = be32_to_cpu(context->qkey); 4524 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4525 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4526 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4527 qp_attr->qp_access_flags = 4528 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4529 4530 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4531 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4532 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4533 qp_attr->alt_pkey_index = 4534 be16_to_cpu(context->alt_path.pkey_index); 4535 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 4536 } 4537 4538 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4539 qp_attr->port_num = context->pri_path.port; 4540 4541 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4542 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4543 4544 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4545 4546 qp_attr->max_dest_rd_atomic = 4547 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4548 qp_attr->min_rnr_timer = 4549 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4550 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4551 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4552 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4553 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4554 4555 out: 4556 kfree(outb); 4557 return err; 4558 } 4559 4560 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4561 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4562 { 4563 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4564 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4565 int err = 0; 4566 u8 raw_packet_qp_state; 4567 4568 if (ibqp->rwq_ind_tbl) 4569 return -ENOSYS; 4570 4571 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4572 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4573 qp_init_attr); 4574 4575 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4576 /* 4577 * Wait for any outstanding page faults, in case the user frees memory 4578 * based upon this query's result. 4579 */ 4580 flush_workqueue(mlx5_ib_page_fault_wq); 4581 #endif 4582 4583 mutex_lock(&qp->mutex); 4584 4585 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 4586 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4587 if (err) 4588 goto out; 4589 qp->state = raw_packet_qp_state; 4590 qp_attr->port_num = 1; 4591 } else { 4592 err = query_qp_attr(dev, qp, qp_attr); 4593 if (err) 4594 goto out; 4595 } 4596 4597 qp_attr->qp_state = qp->state; 4598 qp_attr->cur_qp_state = qp_attr->qp_state; 4599 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4600 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4601 4602 if (!ibqp->uobject) { 4603 qp_attr->cap.max_send_wr = qp->sq.max_post; 4604 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4605 qp_init_attr->qp_context = ibqp->qp_context; 4606 } else { 4607 qp_attr->cap.max_send_wr = 0; 4608 qp_attr->cap.max_send_sge = 0; 4609 } 4610 4611 qp_init_attr->qp_type = ibqp->qp_type; 4612 qp_init_attr->recv_cq = ibqp->recv_cq; 4613 qp_init_attr->send_cq = ibqp->send_cq; 4614 qp_init_attr->srq = ibqp->srq; 4615 qp_attr->cap.max_inline_data = qp->max_inline_data; 4616 4617 qp_init_attr->cap = qp_attr->cap; 4618 4619 qp_init_attr->create_flags = 0; 4620 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4621 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4622 4623 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 4624 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 4625 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 4626 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 4627 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 4628 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 4629 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 4630 qp_init_attr->create_flags |= MLX5_IB_QP_CREATE_SQPN_QP1; 4631 4632 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4633 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4634 4635 out: 4636 mutex_unlock(&qp->mutex); 4637 return err; 4638 } 4639 4640 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4641 struct ib_udata *udata) 4642 { 4643 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4644 struct mlx5_ib_xrcd *xrcd; 4645 int err; 4646 4647 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4648 return ERR_PTR(-ENOSYS); 4649 4650 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4651 if (!xrcd) 4652 return ERR_PTR(-ENOMEM); 4653 4654 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 4655 if (err) { 4656 kfree(xrcd); 4657 return ERR_PTR(-ENOMEM); 4658 } 4659 4660 return &xrcd->ibxrcd; 4661 } 4662 4663 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 4664 { 4665 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4666 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4667 int err; 4668 4669 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 4670 if (err) 4671 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4672 4673 kfree(xrcd); 4674 return 0; 4675 } 4676 4677 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4678 { 4679 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4680 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4681 struct ib_event event; 4682 4683 if (rwq->ibwq.event_handler) { 4684 event.device = rwq->ibwq.device; 4685 event.element.wq = &rwq->ibwq; 4686 switch (type) { 4687 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4688 event.event = IB_EVENT_WQ_FATAL; 4689 break; 4690 default: 4691 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4692 return; 4693 } 4694 4695 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4696 } 4697 } 4698 4699 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4700 struct ib_wq_init_attr *init_attr) 4701 { 4702 struct mlx5_ib_dev *dev; 4703 __be64 *rq_pas0; 4704 void *in; 4705 void *rqc; 4706 void *wq; 4707 int inlen; 4708 int err; 4709 4710 dev = to_mdev(pd->device); 4711 4712 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4713 in = mlx5_vzalloc(inlen); 4714 if (!in) 4715 return -ENOMEM; 4716 4717 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 4718 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4719 MLX5_SET(rqc, rqc, mem_rq_type, 4720 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE); 4721 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4722 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4723 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4724 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4725 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4726 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 4727 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4728 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4729 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4730 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4731 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4732 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4733 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4734 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4735 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4736 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4737 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 4738 kvfree(in); 4739 return err; 4740 } 4741 4742 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4743 struct ib_wq_init_attr *wq_init_attr, 4744 struct mlx5_ib_create_wq *ucmd, 4745 struct mlx5_ib_rwq *rwq) 4746 { 4747 /* Sanity check RQ size before proceeding */ 4748 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4749 return -EINVAL; 4750 4751 if (!ucmd->rq_wqe_count) 4752 return -EINVAL; 4753 4754 rwq->wqe_count = ucmd->rq_wqe_count; 4755 rwq->wqe_shift = ucmd->rq_wqe_shift; 4756 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 4757 rwq->log_rq_stride = rwq->wqe_shift; 4758 rwq->log_rq_size = ilog2(rwq->wqe_count); 4759 return 0; 4760 } 4761 4762 static int prepare_user_rq(struct ib_pd *pd, 4763 struct ib_wq_init_attr *init_attr, 4764 struct ib_udata *udata, 4765 struct mlx5_ib_rwq *rwq) 4766 { 4767 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4768 struct mlx5_ib_create_wq ucmd = {}; 4769 int err; 4770 size_t required_cmd_sz; 4771 4772 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4773 if (udata->inlen < required_cmd_sz) { 4774 mlx5_ib_dbg(dev, "invalid inlen\n"); 4775 return -EINVAL; 4776 } 4777 4778 if (udata->inlen > sizeof(ucmd) && 4779 !ib_is_udata_cleared(udata, sizeof(ucmd), 4780 udata->inlen - sizeof(ucmd))) { 4781 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4782 return -EOPNOTSUPP; 4783 } 4784 4785 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4786 mlx5_ib_dbg(dev, "copy failed\n"); 4787 return -EFAULT; 4788 } 4789 4790 if (ucmd.comp_mask) { 4791 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4792 return -EOPNOTSUPP; 4793 } 4794 4795 if (ucmd.reserved) { 4796 mlx5_ib_dbg(dev, "invalid reserved\n"); 4797 return -EOPNOTSUPP; 4798 } 4799 4800 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4801 if (err) { 4802 mlx5_ib_dbg(dev, "err %d\n", err); 4803 return err; 4804 } 4805 4806 err = create_user_rq(dev, pd, rwq, &ucmd); 4807 if (err) { 4808 mlx5_ib_dbg(dev, "err %d\n", err); 4809 if (err) 4810 return err; 4811 } 4812 4813 rwq->user_index = ucmd.user_index; 4814 return 0; 4815 } 4816 4817 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 4818 struct ib_wq_init_attr *init_attr, 4819 struct ib_udata *udata) 4820 { 4821 struct mlx5_ib_dev *dev; 4822 struct mlx5_ib_rwq *rwq; 4823 struct mlx5_ib_create_wq_resp resp = {}; 4824 size_t min_resp_len; 4825 int err; 4826 4827 if (!udata) 4828 return ERR_PTR(-ENOSYS); 4829 4830 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4831 if (udata->outlen && udata->outlen < min_resp_len) 4832 return ERR_PTR(-EINVAL); 4833 4834 dev = to_mdev(pd->device); 4835 switch (init_attr->wq_type) { 4836 case IB_WQT_RQ: 4837 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 4838 if (!rwq) 4839 return ERR_PTR(-ENOMEM); 4840 err = prepare_user_rq(pd, init_attr, udata, rwq); 4841 if (err) 4842 goto err; 4843 err = create_rq(rwq, pd, init_attr); 4844 if (err) 4845 goto err_user_rq; 4846 break; 4847 default: 4848 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 4849 init_attr->wq_type); 4850 return ERR_PTR(-EINVAL); 4851 } 4852 4853 rwq->ibwq.wq_num = rwq->core_qp.qpn; 4854 rwq->ibwq.state = IB_WQS_RESET; 4855 if (udata->outlen) { 4856 resp.response_length = offsetof(typeof(resp), response_length) + 4857 sizeof(resp.response_length); 4858 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4859 if (err) 4860 goto err_copy; 4861 } 4862 4863 rwq->core_qp.event = mlx5_ib_wq_event; 4864 rwq->ibwq.event_handler = init_attr->event_handler; 4865 return &rwq->ibwq; 4866 4867 err_copy: 4868 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4869 err_user_rq: 4870 destroy_user_rq(pd, rwq, udata); 4871 err: 4872 kfree(rwq); 4873 return ERR_PTR(err); 4874 } 4875 4876 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 4877 { 4878 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4879 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4880 4881 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4882 destroy_user_rq(wq->pd, rwq, udata); 4883 kfree(rwq); 4884 } 4885 4886 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 4887 struct ib_rwq_ind_table_init_attr *init_attr, 4888 struct ib_udata *udata) 4889 { 4890 struct mlx5_ib_dev *dev = to_mdev(device); 4891 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 4892 int sz = 1 << init_attr->log_ind_tbl_size; 4893 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 4894 size_t min_resp_len; 4895 int inlen; 4896 int err; 4897 int i; 4898 u32 *in; 4899 void *rqtc; 4900 4901 if (udata->inlen > 0 && 4902 !ib_is_udata_cleared(udata, 0, 4903 udata->inlen)) 4904 return ERR_PTR(-EOPNOTSUPP); 4905 4906 if (init_attr->log_ind_tbl_size > 4907 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 4908 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 4909 init_attr->log_ind_tbl_size, 4910 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 4911 return ERR_PTR(-EINVAL); 4912 } 4913 4914 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4915 if (udata->outlen && udata->outlen < min_resp_len) 4916 return ERR_PTR(-EINVAL); 4917 4918 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 4919 if (!rwq_ind_tbl) 4920 return ERR_PTR(-ENOMEM); 4921 4922 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 4923 in = mlx5_vzalloc(inlen); 4924 if (!in) { 4925 err = -ENOMEM; 4926 goto err; 4927 } 4928 4929 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 4930 4931 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 4932 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 4933 4934 for (i = 0; i < sz; i++) 4935 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 4936 4937 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 4938 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 4939 4940 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 4941 kvfree(in); 4942 4943 if (err) 4944 goto err; 4945 4946 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 4947 if (udata->outlen) { 4948 resp.response_length = offsetof(typeof(resp), response_length) + 4949 sizeof(resp.response_length); 4950 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4951 if (err) 4952 goto err_copy; 4953 } 4954 4955 return &rwq_ind_tbl->ib_rwq_ind_tbl; 4956 4957 err_copy: 4958 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 4959 err: 4960 kfree(rwq_ind_tbl); 4961 return ERR_PTR(err); 4962 } 4963 4964 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4965 { 4966 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 4967 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 4968 4969 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 4970 4971 kfree(rwq_ind_tbl); 4972 return 0; 4973 } 4974 4975 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 4976 u32 wq_attr_mask, struct ib_udata *udata) 4977 { 4978 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4979 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4980 struct mlx5_ib_modify_wq ucmd = {}; 4981 size_t required_cmd_sz; 4982 int curr_wq_state; 4983 int wq_state; 4984 int inlen; 4985 int err; 4986 void *rqc; 4987 void *in; 4988 4989 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4990 if (udata->inlen < required_cmd_sz) 4991 return -EINVAL; 4992 4993 if (udata->inlen > sizeof(ucmd) && 4994 !ib_is_udata_cleared(udata, sizeof(ucmd), 4995 udata->inlen - sizeof(ucmd))) 4996 return -EOPNOTSUPP; 4997 4998 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4999 return -EFAULT; 5000 5001 if (ucmd.comp_mask || ucmd.reserved) 5002 return -EOPNOTSUPP; 5003 5004 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5005 in = mlx5_vzalloc(inlen); 5006 if (!in) 5007 return -ENOMEM; 5008 5009 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5010 5011 MLX5_SET(modify_rq_in, in, rqn, rwq->core_qp.qpn); 5012 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5013 wq_attr->curr_wq_state : wq->state; 5014 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5015 wq_attr->wq_state : curr_wq_state; 5016 if (curr_wq_state == IB_WQS_ERR) 5017 curr_wq_state = MLX5_RQC_STATE_ERR; 5018 if (wq_state == IB_WQS_ERR) 5019 wq_state = MLX5_RQC_STATE_ERR; 5020 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5021 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5022 MLX5_SET(rqc, rqc, state, wq_state); 5023 5024 err = mlx5_core_modify_rq(dev->mdev, in, inlen); 5025 kvfree(in); 5026 if (!err) 5027 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5028 5029 return err; 5030 } 5031