1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_arp.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/rgephyreg.h> 56 57 #include "miibus_if.h" 58 59 #include <machine/bus.h> 60 #include <pci/if_rlreg.h> 61 62 static int rgephy_probe(device_t); 63 static int rgephy_attach(device_t); 64 65 struct rgephy_softc { 66 struct mii_softc mii_sc; 67 int mii_model; 68 int mii_revision; 69 }; 70 71 static device_method_t rgephy_methods[] = { 72 /* device interface */ 73 DEVMETHOD(device_probe, rgephy_probe), 74 DEVMETHOD(device_attach, rgephy_attach), 75 DEVMETHOD(device_detach, mii_phy_detach), 76 DEVMETHOD(device_shutdown, bus_generic_shutdown), 77 { 0, 0 } 78 }; 79 80 static devclass_t rgephy_devclass; 81 82 static driver_t rgephy_driver = { 83 "rgephy", 84 rgephy_methods, 85 sizeof(struct rgephy_softc) 86 }; 87 88 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 89 90 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 91 static void rgephy_status(struct mii_softc *); 92 static int rgephy_mii_phy_auto(struct mii_softc *); 93 static void rgephy_reset(struct mii_softc *); 94 static void rgephy_loop(struct mii_softc *); 95 static void rgephy_load_dspcode(struct mii_softc *); 96 97 static const struct mii_phydesc rgephys[] = { 98 MII_PHY_DESC(xxREALTEK, RTL8169S), 99 MII_PHY_END 100 }; 101 102 static int 103 rgephy_probe(device_t dev) 104 { 105 106 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); 107 } 108 109 static int 110 rgephy_attach(device_t dev) 111 { 112 struct rgephy_softc *rsc; 113 struct mii_softc *sc; 114 struct mii_attach_args *ma; 115 struct mii_data *mii; 116 const char *sep = ""; 117 118 rsc = device_get_softc(dev); 119 sc = &rsc->mii_sc; 120 ma = device_get_ivars(dev); 121 sc->mii_dev = device_get_parent(dev); 122 mii = ma->mii_data; 123 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 124 125 sc->mii_flags = miibus_get_flags(dev); 126 sc->mii_inst = mii->mii_instance++; 127 sc->mii_phy = ma->mii_phyno; 128 sc->mii_service = rgephy_service; 129 sc->mii_pdata = mii; 130 131 rsc->mii_model = MII_MODEL(ma->mii_id2); 132 rsc->mii_revision = MII_REV(ma->mii_id2); 133 134 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 135 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 136 137 #if 0 138 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 139 MII_MEDIA_100_TX); 140 #endif 141 142 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 143 sc->mii_capabilities &= ~BMSR_ANEG; 144 if (sc->mii_capabilities & BMSR_EXTSTAT) 145 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 146 147 device_printf(dev, " "); 148 mii_phy_add_media(sc); 149 /* RTL8169S do not report auto-sense; add manually. */ 150 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 151 sep = ", "; 152 PRINT("auto"); 153 printf("\n"); 154 #undef ADD 155 #undef PRINT 156 157 rgephy_reset(sc); 158 MIIBUS_MEDIAINIT(sc->mii_dev); 159 return (0); 160 } 161 162 static int 163 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 164 { 165 struct rgephy_softc *rsc; 166 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 167 int reg, speed, gig, anar; 168 169 rsc = (struct rgephy_softc *)sc; 170 171 switch (cmd) { 172 case MII_POLLSTAT: 173 break; 174 175 case MII_MEDIACHG: 176 /* 177 * If the interface is not up, don't do anything. 178 */ 179 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 180 break; 181 182 rgephy_reset(sc); /* XXX hardware bug work-around */ 183 184 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 185 anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 186 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 187 188 switch (IFM_SUBTYPE(ife->ifm_media)) { 189 case IFM_AUTO: 190 #ifdef foo 191 /* 192 * If we're already in auto mode, just return. 193 */ 194 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 195 return (0); 196 #endif 197 (void) rgephy_mii_phy_auto(sc); 198 break; 199 case IFM_1000_T: 200 speed = RGEPHY_S1000; 201 goto setit; 202 case IFM_100_TX: 203 speed = RGEPHY_S100; 204 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 205 goto setit; 206 case IFM_10_T: 207 speed = RGEPHY_S10; 208 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 209 setit: 210 rgephy_loop(sc); 211 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 212 speed |= RGEPHY_BMCR_FDX; 213 gig = RGEPHY_1000CTL_AFD; 214 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 215 } else { 216 gig = RGEPHY_1000CTL_AHD; 217 anar &= 218 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 219 } 220 221 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 222 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 223 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 224 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 225 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 226 break; 227 } 228 229 /* 230 * When setting the link manually, one side must 231 * be the master and the other the slave. However 232 * ifmedia doesn't give us a good way to specify 233 * this, so we fake it by using one of the LINK 234 * flags. If LINK0 is set, we program the PHY to 235 * be a master, otherwise it's a slave. 236 */ 237 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 238 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 239 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 240 } else { 241 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 242 gig|RGEPHY_1000CTL_MSE); 243 } 244 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 245 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 246 break; 247 case IFM_NONE: 248 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 249 break; 250 case IFM_100_T4: 251 default: 252 return (EINVAL); 253 } 254 break; 255 256 case MII_TICK: 257 /* 258 * Is the interface even up? 259 */ 260 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 261 return (0); 262 263 /* 264 * Only used for autonegotiation. 265 */ 266 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 267 sc->mii_ticks = 0; 268 break; 269 } 270 271 /* 272 * Check to see if we have link. If we do, we don't 273 * need to restart the autonegotiation process. Read 274 * the BMSR twice in case it's latched. 275 */ 276 if (rsc->mii_revision >= 2) { 277 /* RTL8211B(L) */ 278 reg = PHY_READ(sc, RGEPHY_MII_SSR); 279 if (reg & RGEPHY_SSR_LINK) { 280 sc->mii_ticks = 0; 281 break; 282 } 283 } else { 284 reg = PHY_READ(sc, RL_GMEDIASTAT); 285 if (reg & RL_GMEDIASTAT_LINK) { 286 sc->mii_ticks = 0; 287 break; 288 } 289 } 290 291 /* Announce link loss right after it happens. */ 292 if (sc->mii_ticks++ == 0) 293 break; 294 295 /* Only retry autonegotiation every mii_anegticks seconds. */ 296 if (sc->mii_ticks <= sc->mii_anegticks) 297 return (0); 298 299 sc->mii_ticks = 0; 300 rgephy_mii_phy_auto(sc); 301 break; 302 } 303 304 /* Update the media status. */ 305 rgephy_status(sc); 306 307 /* 308 * Callback if something changed. Note that we need to poke 309 * the DSP on the RealTek PHYs if the media changes. 310 * 311 */ 312 if (sc->mii_media_active != mii->mii_media_active || 313 sc->mii_media_status != mii->mii_media_status || 314 cmd == MII_MEDIACHG) { 315 rgephy_load_dspcode(sc); 316 } 317 mii_phy_update(sc, cmd); 318 return (0); 319 } 320 321 static void 322 rgephy_status(struct mii_softc *sc) 323 { 324 struct rgephy_softc *rsc; 325 struct mii_data *mii = sc->mii_pdata; 326 int bmsr, bmcr; 327 uint16_t ssr; 328 329 mii->mii_media_status = IFM_AVALID; 330 mii->mii_media_active = IFM_ETHER; 331 332 rsc = (struct rgephy_softc *)sc; 333 if (rsc->mii_revision >= 2) { 334 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 335 if (ssr & RGEPHY_SSR_LINK) 336 mii->mii_media_status |= IFM_ACTIVE; 337 } else { 338 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 339 if (bmsr & RL_GMEDIASTAT_LINK) 340 mii->mii_media_status |= IFM_ACTIVE; 341 } 342 343 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 344 345 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 346 if (bmcr & RGEPHY_BMCR_ISO) { 347 mii->mii_media_active |= IFM_NONE; 348 mii->mii_media_status = 0; 349 return; 350 } 351 352 if (bmcr & RGEPHY_BMCR_LOOP) 353 mii->mii_media_active |= IFM_LOOP; 354 355 if (bmcr & RGEPHY_BMCR_AUTOEN) { 356 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 357 /* Erg, still trying, I guess... */ 358 mii->mii_media_active |= IFM_NONE; 359 return; 360 } 361 } 362 363 if (rsc->mii_revision >= 2) { 364 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 365 switch (ssr & RGEPHY_SSR_SPD_MASK) { 366 case RGEPHY_SSR_S1000: 367 mii->mii_media_active |= IFM_1000_T; 368 break; 369 case RGEPHY_SSR_S100: 370 mii->mii_media_active |= IFM_100_TX; 371 break; 372 case RGEPHY_SSR_S10: 373 mii->mii_media_active |= IFM_10_T; 374 break; 375 default: 376 mii->mii_media_active |= IFM_NONE; 377 break; 378 } 379 if (ssr & RGEPHY_SSR_FDX) 380 mii->mii_media_active |= IFM_FDX; 381 else 382 mii->mii_media_active |= IFM_HDX; 383 } else { 384 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 385 if (bmsr & RL_GMEDIASTAT_1000MBPS) 386 mii->mii_media_active |= IFM_1000_T; 387 else if (bmsr & RL_GMEDIASTAT_100MBPS) 388 mii->mii_media_active |= IFM_100_TX; 389 else if (bmsr & RL_GMEDIASTAT_10MBPS) 390 mii->mii_media_active |= IFM_10_T; 391 else 392 mii->mii_media_active |= IFM_NONE; 393 if (bmsr & RL_GMEDIASTAT_FDX) 394 mii->mii_media_active |= IFM_FDX; 395 else 396 mii->mii_media_active |= IFM_HDX; 397 } 398 } 399 400 static int 401 rgephy_mii_phy_auto(struct mii_softc *mii) 402 { 403 404 rgephy_loop(mii); 405 rgephy_reset(mii); 406 407 PHY_WRITE(mii, RGEPHY_MII_ANAR, 408 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 409 DELAY(1000); 410 PHY_WRITE(mii, RGEPHY_MII_1000CTL, 411 RGEPHY_1000CTL_AHD|RGEPHY_1000CTL_AFD); 412 DELAY(1000); 413 PHY_WRITE(mii, RGEPHY_MII_BMCR, 414 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 415 DELAY(100); 416 417 return (EJUSTRETURN); 418 } 419 420 static void 421 rgephy_loop(struct mii_softc *sc) 422 { 423 struct rgephy_softc *rsc; 424 int i; 425 426 rsc = (struct rgephy_softc *)sc; 427 if (rsc->mii_revision < 2) { 428 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 429 DELAY(1000); 430 } 431 432 for (i = 0; i < 15000; i++) { 433 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { 434 #if 0 435 device_printf(sc->mii_dev, "looped %d\n", i); 436 #endif 437 break; 438 } 439 DELAY(10); 440 } 441 } 442 443 #define PHY_SETBIT(x, y, z) \ 444 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 445 #define PHY_CLRBIT(x, y, z) \ 446 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 447 448 /* 449 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 450 * existing revisions of the 8169S/8110S chips need to be tuned in 451 * order to reliably negotiate a 1000Mbps link. This is only needed 452 * for rev 0 and rev 1 of the PHY. Later versions work without 453 * any fixups. 454 */ 455 static void 456 rgephy_load_dspcode(struct mii_softc *sc) 457 { 458 struct rgephy_softc *rsc; 459 int val; 460 461 rsc = (struct rgephy_softc *)sc; 462 if (rsc->mii_revision >= 2) 463 return; 464 465 PHY_WRITE(sc, 31, 0x0001); 466 PHY_WRITE(sc, 21, 0x1000); 467 PHY_WRITE(sc, 24, 0x65C7); 468 PHY_CLRBIT(sc, 4, 0x0800); 469 val = PHY_READ(sc, 4) & 0xFFF; 470 PHY_WRITE(sc, 4, val); 471 PHY_WRITE(sc, 3, 0x00A1); 472 PHY_WRITE(sc, 2, 0x0008); 473 PHY_WRITE(sc, 1, 0x1020); 474 PHY_WRITE(sc, 0, 0x1000); 475 PHY_SETBIT(sc, 4, 0x0800); 476 PHY_CLRBIT(sc, 4, 0x0800); 477 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 478 PHY_WRITE(sc, 4, val); 479 PHY_WRITE(sc, 3, 0xFF41); 480 PHY_WRITE(sc, 2, 0xDE60); 481 PHY_WRITE(sc, 1, 0x0140); 482 PHY_WRITE(sc, 0, 0x0077); 483 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 484 PHY_WRITE(sc, 4, val); 485 PHY_WRITE(sc, 3, 0xDF01); 486 PHY_WRITE(sc, 2, 0xDF20); 487 PHY_WRITE(sc, 1, 0xFF95); 488 PHY_WRITE(sc, 0, 0xFA00); 489 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 490 PHY_WRITE(sc, 4, val); 491 PHY_WRITE(sc, 3, 0xFF41); 492 PHY_WRITE(sc, 2, 0xDE20); 493 PHY_WRITE(sc, 1, 0x0140); 494 PHY_WRITE(sc, 0, 0x00BB); 495 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 496 PHY_WRITE(sc, 4, val); 497 PHY_WRITE(sc, 3, 0xDF01); 498 PHY_WRITE(sc, 2, 0xDF20); 499 PHY_WRITE(sc, 1, 0xFF95); 500 PHY_WRITE(sc, 0, 0xBF00); 501 PHY_SETBIT(sc, 4, 0x0800); 502 PHY_CLRBIT(sc, 4, 0x0800); 503 PHY_WRITE(sc, 31, 0x0000); 504 505 DELAY(40); 506 } 507 508 static void 509 rgephy_reset(struct mii_softc *sc) 510 { 511 struct rgephy_softc *rsc; 512 uint16_t ssr; 513 514 rsc = (struct rgephy_softc *)sc; 515 if (rsc->mii_revision == 3) { 516 /* RTL8211C(L) */ 517 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 518 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 519 ssr &= ~RGEPHY_SSR_ALDPS; 520 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 521 } 522 } 523 524 mii_phy_reset(sc); 525 DELAY(1000); 526 rgephy_load_dspcode(sc); 527 } 528