1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2000 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 37 #ifndef _DEV_MII_BRGPHYREG_H_ 38 #define _DEV_MII_BRGPHYREG_H_ 39 40 /* 41 * Broadcom BCM5400 registers 42 */ 43 44 #define BRGPHY_MII_BMCR 0x00 45 #define BRGPHY_BMCR_RESET 0x8000 46 #define BRGPHY_BMCR_LOOP 0x4000 47 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */ 48 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ 49 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */ 50 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */ 51 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ 52 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */ 53 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */ 54 #define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ 55 56 #define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */ 57 #define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */ 58 #define BRGPHY_S10 0 /* 10mbps */ 59 60 #define BRGPHY_MII_BMSR 0x01 61 #define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ 62 #define BRGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ 63 #define BRGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ 64 #define BRGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occurred */ 65 #define BRGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ 66 #define BRGPHY_BMSR_LINK 0x0004 /* Link status */ 67 #define BRGPHY_BMSR_JABBER 0x0002 /* Jabber detected */ 68 #define BRGPHY_BMSR_EXT 0x0001 /* Extended capability */ 69 70 #define BRGPHY_MII_ANAR 0x04 71 #define BRGPHY_ANAR_NP 0x8000 /* Next page */ 72 #define BRGPHY_ANAR_RF 0x2000 /* Remote fault */ 73 #define BRGPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */ 74 #define BRGPHY_ANAR_PC 0x0400 /* Pause capable */ 75 #define BRGPHY_ANAR_SEL 0x001F /* Selector field, 00001=Ethernet */ 76 77 #define BRGPHY_MII_ANLPAR 0x05 78 #define BRGPHY_ANLPAR_NP 0x8000 /* Next page */ 79 #define BRGPHY_ANLPAR_RF 0x2000 /* Remote fault */ 80 #define BRGPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */ 81 #define BRGPHY_ANLPAR_PC 0x0400 /* Pause capable */ 82 #define BRGPHY_ANLPAR_SEL 0x001F /* Selector field, 00001=Ethernet */ 83 84 #define BRGPHY_SEL_TYPE 0x0001 /* Ethernet */ 85 86 #define BRGPHY_MII_ANER 0x06 87 #define BRGPHY_ANER_PDF 0x0010 /* Parallel detection fault */ 88 #define BRGPHY_ANER_LPNP 0x0008 /* Link partner can next page */ 89 #define BRGPHY_ANER_NP 0x0004 /* Local PHY can next page */ 90 #define BRGPHY_ANER_RX 0x0002 /* Next page received */ 91 #define BRGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */ 92 93 #define BRGPHY_MII_NEXTP 0x07 /* Next page */ 94 95 #define BRGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */ 96 97 #define BRGPHY_MII_1000CTL 0x09 /* 1000baseT control */ 98 #define BRGPHY_1000CTL_TST 0xE000 /* Test modes */ 99 #define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */ 100 #define BRGPHY_1000CTL_MSC 0x0800 /* Master/Slave configuration */ 101 #define BRGPHY_1000CTL_RD 0x0400 /* Repeater/DTE */ 102 #define BRGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */ 103 #define BRGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */ 104 105 #define BRGPHY_MII_1000STS 0x0A /* 1000baseT status */ 106 #define BRGPHY_1000STS_MSF 0x8000 /* Master/slave fault */ 107 #define BRGPHY_1000STS_MSR 0x4000 /* Master/slave result */ 108 #define BRGPHY_1000STS_LRS 0x2000 /* Local receiver status */ 109 #define BRGPHY_1000STS_RRS 0x1000 /* Remote receiver status */ 110 #define BRGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */ 111 #define BRGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */ 112 #define BRGPHY_1000STS_IEC 0x00FF /* Idle error count */ 113 114 #define BRGPHY_MII_EXTSTS 0x0F /* Extended status */ 115 #define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */ 116 #define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */ 117 #define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */ 118 #define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ 119 120 #define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */ 121 #define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */ 122 #define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */ 123 #define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* TX output disabled */ 124 #define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */ 125 #define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */ 126 #define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */ 127 #define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */ 128 #define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */ 129 #define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */ 130 #define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */ 131 #define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */ 132 #define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */ 133 #define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */ 134 #define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */ 135 #define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */ 136 #define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */ 137 138 #define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */ 139 #define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */ 140 #define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */ 141 #define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */ 142 #define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */ 143 #define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */ 144 #define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */ 145 #define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */ 146 #define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */ 147 #define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */ 148 #define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */ 149 #define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */ 150 #define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */ 151 #define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */ 152 #define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */ 153 154 #define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */ 155 156 #define BRGPHY_MII_FCERRCNT 0x13 /* False carrier sense counter */ 157 #define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */ 158 159 #define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */ 160 #define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */ 161 #define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */ 162 163 #define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */ 164 165 #define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */ 166 #define BRGPHY_MII_EPHY_PTEST 0x17 /* 5906 PHY register */ 167 168 #define BRGPHY_DSP_TAP_NUMBER_MASK 0x00 169 #define BRGPHY_DSP_AGC_A 0x00 170 #define BRGPHY_DSP_AGC_B 0x01 171 #define BRGPHY_DSP_MSE_PAIR_STATUS 0x02 172 #define BRGPHY_DSP_SOFT_DECISION 0x03 173 #define BRGPHY_DSP_PHASE_REG 0x04 174 #define BRGPHY_DSP_SKEW 0x05 175 #define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06 176 #define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07 177 #define BRGPHY_DSP_LAST_ECHO 0x08 178 #define BRGPHY_DSP_FREQUENCY 0x09 179 #define BRGPHY_DSP_PLL_BANDWIDTH 0x0A 180 #define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B 181 182 #define BRGPHYDSP_FILTER_DCOFFSET 0x0C00 183 #define BRGPHY_DSP_FILTER_FEXT3 0x0B00 184 #define BRGPHY_DSP_FILTER_FEXT2 0x0A00 185 #define BRGPHY_DSP_FILTER_FEXT1 0x0900 186 #define BRGPHY_DSP_FILTER_FEXT0 0x0800 187 #define BRGPHY_DSP_FILTER_NEXT3 0x0700 188 #define BRGPHY_DSP_FILTER_NEXT2 0x0600 189 #define BRGPHY_DSP_FILTER_NEXT1 0x0500 190 #define BRGPHY_DSP_FILTER_NEXT0 0x0400 191 #define BRGPHY_DSP_FILTER_ECHO 0x0300 192 #define BRGPHY_DSP_FILTER_DFE 0x0200 193 #define BRGPHY_DSP_FILTER_FFE 0x0100 194 195 #define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000 196 197 #define BRGPHY_DSP_SEL_CH_0 0x0000 198 #define BRGPHY_DSP_SEL_CH_1 0x2000 199 #define BRGPHY_DSP_SEL_CH_2 0x4000 200 #define BRGPHY_DSP_SEL_CH_3 0x6000 201 202 #define BRGPHY_MII_AUXCTL 0x18 /* AUX control */ 203 #define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */ 204 #define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */ 205 #define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */ 206 #define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */ 207 #define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */ 208 #define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */ 209 210 #define BRGPHY_MII_AUXSTS 0x19 /* AUX status */ 211 #define BRGPHY_AUXSTS_ACOMP 0x8000 /* Autoneg complete */ 212 #define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */ 213 #define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */ 214 #define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */ 215 #define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */ 216 #define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */ 217 #define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */ 218 #define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */ 219 #define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* Link partner autoneg ability */ 220 #define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* Link partner next page ability */ 221 #define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */ 222 #define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */ 223 #define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */ 224 225 #define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */ 226 #define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */ 227 #define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */ 228 #define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */ 229 #define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */ 230 #define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */ 231 #define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */ 232 233 #define BRGPHY_MII_ISR 0x1A /* Interrupt status */ 234 #define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */ 235 #define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */ 236 #define BRGPHY_ISR_HCT 0x1000 /* Counter above 32K */ 237 #define BRGPHY_ISR_LCT 0x0800 /* All counter below 128 */ 238 #define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */ 239 #define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */ 240 #define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */ 241 #define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 242 #define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 243 #define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */ 244 #define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */ 245 #define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */ 246 #define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */ 247 #define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */ 248 #define BRGPHY_ISR_CRCERR 0x0001 /* CRC error */ 249 250 #define BRGPHY_MII_IMR 0x1B /* Interrupt mask */ 251 #define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */ 252 #define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */ 253 #define BRGPHY_IMR_HCT 0x1000 /* Counter above 32K */ 254 #define BRGPHY_IMR_LCT 0x0800 /* All counter below 128 */ 255 #define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */ 256 #define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */ 257 #define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */ 258 #define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 259 #define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 260 #define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */ 261 #define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */ 262 #define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */ 263 #define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */ 264 #define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */ 265 #define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */ 266 267 /*******************************************************/ 268 /* Begin: Shared SerDes PHY register definitions */ 269 /*******************************************************/ 270 271 /* SerDes autoneg is different from copper */ 272 #define BRGPHY_SERDES_ANAR 0x04 273 #define BRGPHY_SERDES_ANAR_FDX 0x0020 274 #define BRGPHY_SERDES_ANAR_HDX 0x0040 275 #define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7) 276 #define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7) 277 #define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7) 278 #define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7) 279 280 #define BRGPHY_SERDES_ANLPAR 0x05 281 #define BRGPHY_SERDES_ANLPAR_FDX 0x0020 282 #define BRGPHY_SERDES_ANLPAR_HDX 0x0040 283 #define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7) 284 #define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7) 285 #define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7) 286 #define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7) 287 288 /*******************************************************/ 289 /* End: Shared SerDes PHY register definitions */ 290 /*******************************************************/ 291 292 /*******************************************************/ 293 /* Begin: PHY register values for the 5706 PHY */ 294 /*******************************************************/ 295 296 /* 297 * Aux control shadow register, bits 0-2 select function (0x00 to 298 * 0x07). 299 */ 300 #define BRGPHY_AUXCTL_SHADOW_MISC 0x07 301 #define BRGPHY_AUXCTL_MISC_DATA_MASK 0x7ff8 302 #define BRGPHY_AUXCTL_MISC_READ_SHIFT 12 303 #define BRGPHY_AUXCTL_MISC_WRITE_EN 0x8000 304 #define BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN 0x0200 305 #define BRGPHY_AUXCTL_MISC_WIRESPEED_EN 0x0010 306 307 /* 308 * Shadow register 0x1C, bit 15 is write enable, 309 * bits 14-10 select function (0x00 to 0x1F). 310 */ 311 #define BRGPHY_MII_SHADOW_1C 0x1C 312 #define BRGPHY_SHADOW_1C_WRITE_EN 0x8000 313 #define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00 314 #define BRGPHY_SHADOW_1C_DATA_MASK 0x03FF 315 316 /* Shadow 0x1C Clock Alignment Control Register (select value 0x03) */ 317 #define BRGPHY_SHADOW_1C_CLK_CTRL (0x03 << 10) 318 #define BRGPHY_SHADOW_1C_GTXCLK_EN 0x0200 319 320 /* Shadow 0x1C Mode Control Register (select value 0x1F) */ 321 #define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10) 322 /* When set, Regs 0-0x0F are 1000X, else 1000T */ 323 #define BRGPHY_SHADOW_1C_ENA_1000X 0x0001 324 325 #define BRGPHY_MII_TEST1 0x1E 326 #define BRGPHY_TEST1_TRIM_EN 0x0010 327 #define BRGPHY_TEST1_CRC_EN 0x8000 328 329 #define BRGPHY_MII_TEST2 0x1F 330 331 /*******************************************************/ 332 /* End: PHY register values for the 5706 PHY */ 333 /*******************************************************/ 334 335 /*******************************************************/ 336 /* Begin: PHY register values for the 5708S SerDes PHY */ 337 /*******************************************************/ 338 339 /* Autoneg Next Page Transmit 1 Regiser */ 340 #define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B 341 #define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001 342 343 /* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */ 344 #define BRGPHY_5708S_BLOCK_ADDR 0x1f 345 #define BRGPHY_5708S_DIG_PG0 0x0000 346 #define BRGPHY_5708S_DIG3_PG2 0x0002 347 #define BRGPHY_5708S_TX_MISC_PG5 0x0005 348 349 /* 5708S SerDes "Digital" Registers (page 0) */ 350 #define BRGPHY_5708S_PG0_1000X_CTL1 0x10 351 #define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010 352 #define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001 353 354 #define BRGPHY_5708S_PG0_1000X_STAT1 0x14 355 #define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002 356 #define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004 357 #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018 358 #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3) 359 #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3) 360 #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3) 361 #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3) 362 363 #define BRGPHY_5708S_PG0_1000X_CTL2 0x11 364 #define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001 365 366 /* 5708S SerDes "Digital 3" Registers (page 2) */ 367 #define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10 368 #define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001 369 370 /* 5708S SerDes "TX Misc" Registers (page 5) */ 371 #define BRGPHY_5708S_PG5_2500STATUS1 0x10 372 #define BRGPHY_5708S_PG5_TXACTL1 0x15 373 #define BRGPHY_5708S_PG5_TXACTL3 0x17 374 375 /*******************************************************/ 376 /* End: PHY register values for the 5708S SerDes PHY */ 377 /*******************************************************/ 378 379 /*******************************************************/ 380 /* Begin: PHY register values for the 5709S SerDes PHY */ 381 /*******************************************************/ 382 383 /* 5709S SerDes "General Purpose Status" Registers */ 384 #define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120 385 #define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B 386 #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00 387 #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000 388 #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100 389 #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200 390 #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300 391 #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00 392 #define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008 393 #define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004 394 #define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001 395 396 /* 5709S SerDes "SerDes Digital" Registers */ 397 #define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300 398 #define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010 399 #define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010 400 #define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001 401 402 /* 5709S SerDes "Over 1G" Registers */ 403 #define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320 404 #define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19 405 406 /* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */ 407 #define BRGPHY_BLOCK_ADDR_MRBE 0x8350 408 #define BRGPHY_MRBE_MSG_PG5_NP 0x10 409 #define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001 410 #define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0002 411 412 /* 5709S SerDes "IEEE Clause 73 User B0" Registers */ 413 #define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370 414 #define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12 415 #define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000 416 #define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000 417 #define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000 418 419 /* 5709S SerDes "IEEE Clause 73 User B0" Registers */ 420 #define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0 421 422 /* 5709S SerDes "Combo IEEE 0" Registers */ 423 #define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0 424 425 #define BRGPHY_ADDR_EXT 0x1E 426 #define BRGPHY_BLOCK_ADDR 0x1F 427 428 #define BRGPHY_ADDR_EXT_AN_MMD 0x3800 429 430 /*******************************************************/ 431 /* End: PHY register values for the 5709S SerDes PHY */ 432 /*******************************************************/ 433 434 #define BRGPHY_INTRS \ 435 ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG) 436 437 #endif /* _DEV_BRGPHY_MIIREG_H_ */ 438