xref: /freebsd/sys/dev/mii/brgphy.c (revision fb2971ccd2bab42f5406f919812ceb8e014773ea)
1 /*-
2  * Copyright (c) 2000
3  *	Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *	This product includes software developed by Bill Paul.
16  * 4. Neither the name of the author nor the names of any co-contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30  * THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35 
36 /*
37  * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
38  */
39 
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/bus.h>
46 
47 #include <net/if.h>
48 #include <net/ethernet.h>
49 #include <net/if_media.h>
50 
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
53 #include "miidevs.h"
54 
55 #include <dev/mii/brgphyreg.h>
56 #include <net/if_arp.h>
57 #include <machine/bus.h>
58 #include <dev/bge/if_bgereg.h>
59 #include <dev/bce/if_bcereg.h>
60 
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
63 
64 #include "miibus_if.h"
65 
66 static int brgphy_probe(device_t);
67 static int brgphy_attach(device_t);
68 
69 struct brgphy_softc {
70 	struct mii_softc mii_sc;
71 	int mii_oui;
72 	int mii_model;
73 	int mii_rev;
74 	int serdes_flags;	/* Keeps track of the serdes type used */
75 #define BRGPHY_5706S		0x0001
76 #define BRGPHY_5708S		0x0002
77 #define BRGPHY_NOANWAIT		0x0004
78 #define BRGPHY_5709S		0x0008
79 	int bce_phy_flags;	/* PHY flags transferred from the MAC driver */
80 };
81 
82 static device_method_t brgphy_methods[] = {
83 	/* device interface */
84 	DEVMETHOD(device_probe,		brgphy_probe),
85 	DEVMETHOD(device_attach,	brgphy_attach),
86 	DEVMETHOD(device_detach,	mii_phy_detach),
87 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
88 	{ 0, 0 }
89 };
90 
91 static devclass_t brgphy_devclass;
92 
93 static driver_t brgphy_driver = {
94 	"brgphy",
95 	brgphy_methods,
96 	sizeof(struct brgphy_softc)
97 };
98 
99 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
100 
101 static int	brgphy_service(struct mii_softc *, struct mii_data *, int);
102 static void	brgphy_setmedia(struct mii_softc *, int, int);
103 static void	brgphy_status(struct mii_softc *);
104 static void	brgphy_mii_phy_auto(struct mii_softc *);
105 static void	brgphy_reset(struct mii_softc *);
106 static void	brgphy_enable_loopback(struct mii_softc *);
107 static void	bcm5401_load_dspcode(struct mii_softc *);
108 static void	bcm5411_load_dspcode(struct mii_softc *);
109 static void	bcm54k2_load_dspcode(struct mii_softc *);
110 static void	brgphy_fixup_5704_a0_bug(struct mii_softc *);
111 static void	brgphy_fixup_adc_bug(struct mii_softc *);
112 static void	brgphy_fixup_adjust_trim(struct mii_softc *);
113 static void	brgphy_fixup_ber_bug(struct mii_softc *);
114 static void	brgphy_fixup_crc_bug(struct mii_softc *);
115 static void	brgphy_fixup_jitter_bug(struct mii_softc *);
116 static void	brgphy_ethernet_wirespeed(struct mii_softc *);
117 static void	brgphy_jumbo_settings(struct mii_softc *, u_long);
118 
119 static const struct mii_phydesc brgphys[] = {
120 	MII_PHY_DESC(xxBROADCOM, BCM5400),
121 	MII_PHY_DESC(xxBROADCOM, BCM5401),
122 	MII_PHY_DESC(xxBROADCOM, BCM5411),
123 	MII_PHY_DESC(xxBROADCOM, BCM54K2),
124 	MII_PHY_DESC(xxBROADCOM, BCM5701),
125 	MII_PHY_DESC(xxBROADCOM, BCM5703),
126 	MII_PHY_DESC(xxBROADCOM, BCM5704),
127 	MII_PHY_DESC(xxBROADCOM, BCM5705),
128 	MII_PHY_DESC(xxBROADCOM, BCM5706),
129 	MII_PHY_DESC(xxBROADCOM, BCM5714),
130 	MII_PHY_DESC(xxBROADCOM, BCM5750),
131 	MII_PHY_DESC(xxBROADCOM, BCM5752),
132 	MII_PHY_DESC(xxBROADCOM, BCM5754),
133 	MII_PHY_DESC(xxBROADCOM, BCM5780),
134 	MII_PHY_DESC(xxBROADCOM, BCM5708C),
135 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5482S),
136 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755),
137 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787),
138 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S),
139 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX),
140 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722),
141 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784),
142 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C),
143 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761),
144 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S),
145 	MII_PHY_DESC(xxBROADCOM_ALT2, BCM5717C),
146 	MII_PHY_DESC(BROADCOM2, BCM5906),
147 	MII_PHY_END
148 };
149 
150 #define HS21_PRODUCT_ID	"IBM eServer BladeCenter HS21"
151 #define HS21_BCM_CHIPID	0x57081021
152 
153 static int
154 detect_hs21(struct bce_softc *bce_sc)
155 {
156 	char *sysenv;
157 
158 	if (bce_sc->bce_chipid != HS21_BCM_CHIPID)
159 		return (0);
160 	sysenv = getenv("smbios.system.product");
161 	if (sysenv == NULL)
162 		return (0);
163 	if (strncmp(sysenv, HS21_PRODUCT_ID, strlen(HS21_PRODUCT_ID)) != 0)
164 		return (0);
165 	return (1);
166 }
167 
168 /* Search for our PHY in the list of known PHYs */
169 static int
170 brgphy_probe(device_t dev)
171 {
172 	return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
173 }
174 
175 /* Attach the PHY to the MII bus */
176 static int
177 brgphy_attach(device_t dev)
178 {
179 	struct brgphy_softc *bsc;
180 	struct bge_softc *bge_sc = NULL;
181 	struct bce_softc *bce_sc = NULL;
182 	struct mii_softc *sc;
183 	struct mii_attach_args *ma;
184 	struct mii_data *mii;
185 	struct ifnet *ifp;
186 	int fast_ether;
187 
188 	bsc = device_get_softc(dev);
189 	sc = &bsc->mii_sc;
190 	ma = device_get_ivars(dev);
191 	sc->mii_dev = device_get_parent(dev);
192 	mii = ma->mii_data;
193 	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
194 
195 	/* Initialize mii_softc structure */
196 	sc->mii_flags = miibus_get_flags(dev);
197 	sc->mii_inst = mii->mii_instance++;
198 	sc->mii_phy = ma->mii_phyno;
199 	sc->mii_service = brgphy_service;
200 	sc->mii_pdata = mii;
201 
202 	/*
203 	 * At least some variants wedge when isolating, at least some also
204 	 * don't support loopback.
205 	 */
206 	sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
207 	sc->mii_anegticks = MII_ANEGTICKS_GIGE;
208 
209 	/* Initialize brgphy_softc structure */
210 	bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
211 	bsc->mii_model = MII_MODEL(ma->mii_id2);
212 	bsc->mii_rev = MII_REV(ma->mii_id2);
213 	bsc->serdes_flags = 0;
214 
215 	fast_ether = 0;
216 
217 	if (bootverbose)
218 		device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
219 		    bsc->mii_oui, bsc->mii_model, bsc->mii_rev);
220 
221 	/* Handle any special cases based on the PHY ID */
222 	switch (bsc->mii_oui) {
223 	case MII_OUI_BROADCOM:
224 	case MII_OUI_BROADCOM2:
225 		break;
226 	case MII_OUI_xxBROADCOM:
227 		switch (bsc->mii_model) {
228 		case MII_MODEL_xxBROADCOM_BCM5706:
229 		case MII_MODEL_xxBROADCOM_BCM5714:
230 			/*
231 			 * The 5464 PHY used in the 5706 supports both copper
232 			 * and fiber interfaces over GMII.  Need to check the
233 			 * shadow registers to see which mode is actually
234 			 * in effect, and therefore whether we have 5706C or
235 			 * 5706S.
236 			 */
237 			PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
238 				BRGPHY_SHADOW_1C_MODE_CTRL);
239 			if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
240 				BRGPHY_SHADOW_1C_ENA_1000X) {
241 				bsc->serdes_flags |= BRGPHY_5706S;
242 				sc->mii_flags |= MIIF_HAVEFIBER;
243 			}
244 			break;
245 		} break;
246 	case MII_OUI_xxBROADCOM_ALT1:
247 		switch (bsc->mii_model) {
248 		case MII_MODEL_xxBROADCOM_ALT1_BCM5708S:
249 			bsc->serdes_flags |= BRGPHY_5708S;
250 			sc->mii_flags |= MIIF_HAVEFIBER;
251 			break;
252 		case MII_MODEL_xxBROADCOM_ALT1_BCM5709S:
253 			bsc->serdes_flags |= BRGPHY_5709S;
254 			sc->mii_flags |= MIIF_HAVEFIBER;
255 			break;
256 		}
257 		break;
258 	case MII_OUI_xxBROADCOM_ALT2:
259 		/* No special handling yet. */
260 		break;
261 	default:
262 		device_printf(dev, "Unrecognized OUI for PHY!\n");
263 	}
264 
265 	ifp = sc->mii_pdata->mii_ifp;
266 
267 	/* Find the MAC driver associated with this PHY. */
268 	if (strcmp(ifp->if_dname, "bge") == 0)	{
269 		bge_sc = ifp->if_softc;
270 	} else if (strcmp(ifp->if_dname, "bce") == 0) {
271 		bce_sc = ifp->if_softc;
272 	}
273 
274 	/* Todo: Need to add additional controllers such as 5906 & 5787F */
275 	/* The 590x chips are 10/100 only. */
276 	if (bge_sc &&
277 	    pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
278 	    (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
279 	    pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2 ||
280 	    pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906 ||
281 	    pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906M)) {
282 		fast_ether = 1;
283 		sc->mii_anegticks = MII_ANEGTICKS;
284 	}
285 
286 	brgphy_reset(sc);
287 
288 	/* Read the PHY's capabilities. */
289 	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
290 	if (sc->mii_capabilities & BMSR_EXTSTAT)
291 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
292 	device_printf(dev, " ");
293 
294 #define	ADD(m, c)	ifmedia_add(&mii->mii_media, (m), (c), NULL)
295 
296 	/* Add the supported media types */
297 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
298 		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
299 			BRGPHY_S10);
300 		printf("10baseT, ");
301 		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
302 			BRGPHY_S10 | BRGPHY_BMCR_FDX);
303 		printf("10baseT-FDX, ");
304 		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
305 			BRGPHY_S100);
306 		printf("100baseTX, ");
307 		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
308 			BRGPHY_S100 | BRGPHY_BMCR_FDX);
309 		printf("100baseTX-FDX, ");
310 		if (fast_ether == 0) {
311 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
312 				BRGPHY_S1000);
313 			printf("1000baseT, ");
314 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst),
315 				BRGPHY_S1000 | BRGPHY_BMCR_FDX);
316 			printf("1000baseT-FDX, ");
317 		}
318 	} else {
319 		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
320 			BRGPHY_S1000 | BRGPHY_BMCR_FDX);
321 		printf("1000baseSX-FDX, ");
322 		/* 2.5G support is a software enabled feature on the 5708S and 5709S. */
323 		if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
324 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
325 			printf("2500baseSX-FDX, ");
326 		} else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
327 		    (detect_hs21(bce_sc) != 0)) {
328 			/*
329 			 * There appears to be certain silicon revision
330 			 * in IBM HS21 blades that is having issues with
331 			 * this driver wating for the auto-negotiation to
332 			 * complete. This happens with a specific chip id
333 			 * only and when the 1000baseSX-FDX is the only
334 			 * mode. Workaround this issue since it's unlikely
335 			 * to be ever addressed.
336 			 */
337 			printf("auto-neg workaround, ");
338 			bsc->serdes_flags |= BRGPHY_NOANWAIT;
339 		}
340 	}
341 
342 	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
343 	printf("auto\n");
344 
345 #undef ADD
346 	MIIBUS_MEDIAINIT(sc->mii_dev);
347 	return (0);
348 }
349 
350 static int
351 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
352 {
353 	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
354 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
355 	int val;
356 
357 	switch (cmd) {
358 	case MII_POLLSTAT:
359 		break;
360 	case MII_MEDIACHG:
361 		/* If the interface is not up, don't do anything. */
362 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
363 			break;
364 
365 		/* Todo: Why is this here?  Is it really needed? */
366 		brgphy_reset(sc);	/* XXX hardware bug work-around */
367 
368 		switch (IFM_SUBTYPE(ife->ifm_media)) {
369 		case IFM_AUTO:
370 			brgphy_mii_phy_auto(sc);
371 			break;
372 		case IFM_2500_SX:
373 		case IFM_1000_SX:
374 		case IFM_1000_T:
375 		case IFM_100_TX:
376 		case IFM_10_T:
377 			brgphy_setmedia(sc, ife->ifm_media,
378 			    mii->mii_ifp->if_flags & IFF_LINK0);
379 			break;
380 		default:
381 			return (EINVAL);
382 		}
383 		break;
384 	case MII_TICK:
385 		/* Bail if the interface isn't up. */
386 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
387 			return (0);
388 
389 
390 		/* Bail if autoneg isn't in process. */
391 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
392 			sc->mii_ticks = 0;
393 			break;
394 		}
395 
396 		/*
397 		 * Check to see if we have link.  If we do, we don't
398 		 * need to restart the autonegotiation process.
399 		 */
400 		val	= PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
401 		if (val & BMSR_LINK) {
402 			sc->mii_ticks = 0;	/* Reset autoneg timer. */
403 			break;
404 		}
405 
406 		/* Announce link loss right after it happens. */
407 		if (sc->mii_ticks++ == 0)
408 			break;
409 
410 		/* Only retry autonegotiation every mii_anegticks seconds. */
411 		if (sc->mii_ticks <= sc->mii_anegticks)
412 			break;
413 
414 
415 		/* Retry autonegotiation */
416 		sc->mii_ticks = 0;
417 		brgphy_mii_phy_auto(sc);
418 		break;
419 	}
420 
421 	/* Update the media status. */
422 	brgphy_status(sc);
423 
424 	/*
425 	 * Callback if something changed. Note that we need to poke
426 	 * the DSP on the Broadcom PHYs if the media changes.
427 	 */
428 	if (sc->mii_media_active != mii->mii_media_active ||
429 	    sc->mii_media_status != mii->mii_media_status ||
430 	    cmd == MII_MEDIACHG) {
431 		switch (bsc->mii_oui) {
432 		case MII_OUI_BROADCOM:
433 			break;
434 		case MII_OUI_xxBROADCOM:
435 			switch (bsc->mii_model) {
436 			case MII_MODEL_xxBROADCOM_BCM5400:
437 				bcm5401_load_dspcode(sc);
438 				break;
439 			case MII_MODEL_xxBROADCOM_BCM5401:
440 				if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
441 					bcm5401_load_dspcode(sc);
442 				break;
443 			case MII_MODEL_xxBROADCOM_BCM5411:
444 				bcm5411_load_dspcode(sc);
445 				break;
446 			case MII_MODEL_xxBROADCOM_BCM54K2:
447 				bcm54k2_load_dspcode(sc);
448 				break;
449 			}
450 			break;
451 		case MII_OUI_xxBROADCOM_ALT1:
452 			break;
453 		}
454 	}
455 	mii_phy_update(sc, cmd);
456 	return (0);
457 }
458 
459 
460 /****************************************************************************/
461 /* Sets the PHY link speed.                                                 */
462 /*                                                                          */
463 /* Returns:                                                                 */
464 /*   None                                                                   */
465 /****************************************************************************/
466 static void
467 brgphy_setmedia(struct mii_softc *sc, int media, int master)
468 {
469 	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
470 	int bmcr = 0, gig;
471 
472 	/* Calculate the value for the BMCR register. */
473 	switch (IFM_SUBTYPE(media)) {
474 	case IFM_2500_SX:
475 		break;
476 	case IFM_1000_SX:
477 	case IFM_1000_T:
478 		bmcr = BRGPHY_S1000;
479 		break;
480 	case IFM_100_TX:
481 		bmcr = BRGPHY_S100;
482 		break;
483 	case IFM_10_T:
484 	default:
485 		bmcr = BRGPHY_S10;
486 		break;
487 	}
488 
489 	/* Calculate duplex settings for 1000BasetT/1000BaseX. */
490 	if ((media & IFM_GMASK) == IFM_FDX) {
491 		bmcr |= BRGPHY_BMCR_FDX;
492 		gig = BRGPHY_1000CTL_AFD;
493 	} else {
494 		gig = BRGPHY_1000CTL_AHD;
495 	}
496 
497 	/* Force loopback to disconnect PHY for Ethernet medium. */
498 	brgphy_enable_loopback(sc);
499 
500 	/* Disable 1000BaseT advertisements. */
501 	PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
502 	/* Disable 10/100 advertisements. */
503 	PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
504 	/* Write forced link speed. */
505 	PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
506 
507 	/* If 10/100 only then configuration is complete. */
508 	if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX))
509 		goto brgphy_setmedia_exit;
510 
511 	/* Set duplex speed advertisement for 1000BaseT/1000BaseX. */
512 	PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
513 	/* Restart auto-negotiation for 1000BaseT/1000BaseX. */
514 	PHY_WRITE(sc, BRGPHY_MII_BMCR,
515 	    bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
516 
517 	/* If not 5701 PHY then configuration is complete. */
518 	if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
519 		goto brgphy_setmedia_exit;
520 
521 	/*
522 	 * When setting the link manually, one side must be the master and
523 	 * the other the slave. However ifmedia doesn't give us a good way
524 	 * to specify this, so we fake it by using one of the LINK flags.
525 	 * If LINK0 is set, we program the PHY to be a master, otherwise
526 	 * it's a slave.
527 	 */
528 	if (master) {
529 		PHY_WRITE(sc, BRGPHY_MII_1000CTL,
530 		    gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC);
531 	} else {
532 		PHY_WRITE(sc, BRGPHY_MII_1000CTL,
533 		    gig | BRGPHY_1000CTL_MSE);
534 	}
535 
536 brgphy_setmedia_exit:
537 	return;
538 }
539 
540 /****************************************************************************/
541 /* Set the media status based on the PHY settings.                          */
542 /* IFM_FLAG0 = 0 (RX flow control disabled) | 1 (enabled)                   */
543 /* IFM_FLAG1 = 0 (TX flow control disabled) | 1 (enabled)                   */
544 /*                                                                          */
545 /* Returns:                                                                 */
546 /*   None                                                                   */
547 /****************************************************************************/
548 static void
549 brgphy_status(struct mii_softc *sc)
550 {
551 	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
552 	struct mii_data *mii = sc->mii_pdata;
553 	int aux, bmcr, bmsr, anar, anlpar, xstat, val;
554 
555 
556 	mii->mii_media_status = IFM_AVALID;
557 	mii->mii_media_active = IFM_ETHER;
558 
559 	bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
560 	bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
561 	anar = PHY_READ(sc, BRGPHY_MII_ANAR);
562 	anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR);
563 
564 	/* Loopback is enabled. */
565 	if (bmcr & BRGPHY_BMCR_LOOP) {
566 
567 		mii->mii_media_active |= IFM_LOOP;
568 	}
569 
570 	/* Autoneg is still in progress. */
571 	if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
572 	    (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
573 	    (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
574 		/* Erg, still trying, I guess... */
575 		mii->mii_media_active |= IFM_NONE;
576 		goto brgphy_status_exit;
577 	}
578 
579 	/* Autoneg is enabled and complete, link should be up. */
580 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
581 		aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
582 
583 		/* If copper link is up, get the negotiated speed/duplex. */
584 		if (aux & BRGPHY_AUXSTS_LINK) {
585 			mii->mii_media_status |= IFM_ACTIVE;
586 			switch (aux & BRGPHY_AUXSTS_AN_RES) {
587 			case BRGPHY_RES_1000FD:
588 				mii->mii_media_active |= IFM_1000_T | IFM_FDX; 	break;
589 			case BRGPHY_RES_1000HD:
590 				mii->mii_media_active |= IFM_1000_T | IFM_HDX; 	break;
591 			case BRGPHY_RES_100FD:
592 				mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
593 			case BRGPHY_RES_100T4:
594 				mii->mii_media_active |= IFM_100_T4; break;
595 			case BRGPHY_RES_100HD:
596 				mii->mii_media_active |= IFM_100_TX | IFM_HDX; 	break;
597 			case BRGPHY_RES_10FD:
598 				mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
599 			case BRGPHY_RES_10HD:
600 				mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
601 			default:
602 				mii->mii_media_active |= IFM_NONE; break;
603 			}
604 		}
605 	} else {
606 		/* If serdes link is up, get the negotiated speed/duplex. */
607 		if (bmsr & BRGPHY_BMSR_LINK) {
608 			mii->mii_media_status |= IFM_ACTIVE;
609 		}
610 
611 		/* Check the link speed/duplex based on the PHY type. */
612 		if (bsc->serdes_flags & BRGPHY_5706S) {
613 			mii->mii_media_active |= IFM_1000_SX;
614 
615 			/* If autoneg enabled, read negotiated duplex settings */
616 			if (bmcr & BRGPHY_BMCR_AUTOEN) {
617 				val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
618 				if (val & BRGPHY_SERDES_ANAR_FDX)
619 					mii->mii_media_active |= IFM_FDX;
620 				else
621 					mii->mii_media_active |= IFM_HDX;
622 			}
623 
624 		} else if (bsc->serdes_flags & BRGPHY_5708S) {
625 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
626 			xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
627 
628 			/* Check for MRBE auto-negotiated speed results. */
629 			switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
630 			case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
631 				mii->mii_media_active |= IFM_10_FL; break;
632 			case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
633 				mii->mii_media_active |= IFM_100_FX; break;
634 			case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
635 				mii->mii_media_active |= IFM_1000_SX; break;
636 			case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
637 				mii->mii_media_active |= IFM_2500_SX; break;
638 			}
639 
640 			/* Check for MRBE auto-negotiated duplex results. */
641 			if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
642 				mii->mii_media_active |= IFM_FDX;
643 			else
644 				mii->mii_media_active |= IFM_HDX;
645 
646 		} else if (bsc->serdes_flags & BRGPHY_5709S) {
647 
648 			/* Select GP Status Block of the AN MMD, get autoneg results. */
649 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
650 			xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
651 
652 			/* Restore IEEE0 block (assumed in all brgphy(4) code). */
653 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
654 
655 			/* Check for MRBE auto-negotiated speed results. */
656 			switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
657 				case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
658 					mii->mii_media_active |= IFM_10_FL; break;
659 				case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
660 					mii->mii_media_active |= IFM_100_FX; break;
661 				case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
662 					mii->mii_media_active |= IFM_1000_SX; break;
663 				case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
664 					mii->mii_media_active |= IFM_2500_SX; break;
665 			}
666 
667 			/* Check for MRBE auto-negotiated duplex results. */
668 			if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
669 				mii->mii_media_active |= IFM_FDX;
670 			else
671 				mii->mii_media_active |= IFM_HDX;
672 		}
673 
674 	}
675 
676 	/* Todo: Change bge to use these settings. */
677 
678 	/* Fetch flow control settings from the copper PHY. */
679 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
680 		/* Set FLAG0 if RX is enabled and FLAG1 if TX is enabled */
681 		if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) {
682 			mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
683 		} else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) &&
684 		    (anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
685 			mii->mii_media_active |= IFM_FLAG1;
686 		} else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) &&
687 		    !(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
688 			mii->mii_media_active |= IFM_FLAG0;
689 		}
690 	}
691 
692 	/* Todo: Add support for fiber settings too. */
693 
694 
695 brgphy_status_exit:
696 	return;
697 }
698 
699 static void
700 brgphy_mii_phy_auto(struct mii_softc *sc)
701 {
702 	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
703 	int ktcr = 0;
704 
705 	brgphy_reset(sc);
706 
707 	/* Enable flow control in the advertisement register. */
708 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
709 		/* Pause capability advertisement (pause capable & asymmetric) */
710 		PHY_WRITE(sc, BRGPHY_MII_ANAR,
711 	    	BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA |
712 	    	BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC);
713 	} else {
714 		PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX |
715 			BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE);
716 	}
717 
718 	/* Enable speed in the 1000baseT control register */
719 	ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
720 	if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
721 		ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
722 	PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
723 	ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
724 
725 	/* Start autonegotiation */
726 	PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
727 	PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
728 
729 }
730 
731 
732 /* Enable loopback to force the link down. */
733 static void
734 brgphy_enable_loopback(struct mii_softc *sc)
735 {
736 	int i;
737 
738 	PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
739 	for (i = 0; i < 15000; i++) {
740 		if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
741 			break;
742 		DELAY(10);
743 	}
744 }
745 
746 /* Turn off tap power management on 5401. */
747 static void
748 bcm5401_load_dspcode(struct mii_softc *sc)
749 {
750 	static const struct {
751 		int		reg;
752 		uint16_t	val;
753 	} dspcode[] = {
754 		{ BRGPHY_MII_AUXCTL,		0x0c20 },
755 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0012 },
756 		{ BRGPHY_MII_DSP_RW_PORT,	0x1804 },
757 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0013 },
758 		{ BRGPHY_MII_DSP_RW_PORT,	0x1204 },
759 		{ BRGPHY_MII_DSP_ADDR_REG,	0x8006 },
760 		{ BRGPHY_MII_DSP_RW_PORT,	0x0132 },
761 		{ BRGPHY_MII_DSP_ADDR_REG,	0x8006 },
762 		{ BRGPHY_MII_DSP_RW_PORT,	0x0232 },
763 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
764 		{ BRGPHY_MII_DSP_RW_PORT,	0x0a20 },
765 		{ 0,				0 },
766 	};
767 	int i;
768 
769 	for (i = 0; dspcode[i].reg != 0; i++)
770 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
771 	DELAY(40);
772 }
773 
774 static void
775 bcm5411_load_dspcode(struct mii_softc *sc)
776 {
777 	static const struct {
778 		int		reg;
779 		uint16_t	val;
780 	} dspcode[] = {
781 		{ 0x1c,				0x8c23 },
782 		{ 0x1c,				0x8ca3 },
783 		{ 0x1c,				0x8c23 },
784 		{ 0,				0 },
785 	};
786 	int i;
787 
788 	for (i = 0; dspcode[i].reg != 0; i++)
789 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
790 }
791 
792 void
793 bcm54k2_load_dspcode(struct mii_softc *sc)
794 {
795 	static const struct {
796 		int		reg;
797 		uint16_t	val;
798 	} dspcode[] = {
799 		{ 4,				0x01e1 },
800 		{ 9,				0x0300 },
801 		{ 0,				0 },
802 	};
803 	int i;
804 
805 	for (i = 0; dspcode[i].reg != 0; i++)
806 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
807 
808 }
809 
810 static void
811 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
812 {
813 	static const struct {
814 		int		reg;
815 		uint16_t	val;
816 	} dspcode[] = {
817 		{ 0x1c,				0x8d68 },
818 		{ 0x1c,				0x8d68 },
819 		{ 0,				0 },
820 	};
821 	int i;
822 
823 	for (i = 0; dspcode[i].reg != 0; i++)
824 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
825 }
826 
827 static void
828 brgphy_fixup_adc_bug(struct mii_softc *sc)
829 {
830 	static const struct {
831 		int		reg;
832 		uint16_t	val;
833 	} dspcode[] = {
834 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
835 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
836 		{ BRGPHY_MII_DSP_RW_PORT,	0x2aaa },
837 		{ 0,				0 },
838 	};
839 	int i;
840 
841 	for (i = 0; dspcode[i].reg != 0; i++)
842 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
843 }
844 
845 static void
846 brgphy_fixup_adjust_trim(struct mii_softc *sc)
847 {
848 	static const struct {
849 		int		reg;
850 		uint16_t	val;
851 	} dspcode[] = {
852 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
853 		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
854 		{ BRGPHY_MII_DSP_RW_PORT,	0x110b },
855 		{ BRGPHY_MII_TEST1,			0x0014 },
856 		{ BRGPHY_MII_AUXCTL,		0x0400 },
857 		{ 0,				0 },
858 	};
859 	int i;
860 
861 	for (i = 0; dspcode[i].reg != 0; i++)
862 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
863 }
864 
865 static void
866 brgphy_fixup_ber_bug(struct mii_softc *sc)
867 {
868 	static const struct {
869 		int		reg;
870 		uint16_t	val;
871 	} dspcode[] = {
872 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
873 		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
874 		{ BRGPHY_MII_DSP_RW_PORT,	0x310b },
875 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
876 		{ BRGPHY_MII_DSP_RW_PORT,	0x9506 },
877 		{ BRGPHY_MII_DSP_ADDR_REG,	0x401f },
878 		{ BRGPHY_MII_DSP_RW_PORT,	0x14e2 },
879 		{ BRGPHY_MII_AUXCTL,		0x0400 },
880 		{ 0,				0 },
881 	};
882 	int i;
883 
884 	for (i = 0; dspcode[i].reg != 0; i++)
885 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
886 }
887 
888 static void
889 brgphy_fixup_crc_bug(struct mii_softc *sc)
890 {
891 	static const struct {
892 		int		reg;
893 		uint16_t	val;
894 	} dspcode[] = {
895 		{ BRGPHY_MII_DSP_RW_PORT,	0x0a75 },
896 		{ 0x1c,				0x8c68 },
897 		{ 0x1c,				0x8d68 },
898 		{ 0x1c,				0x8c68 },
899 		{ 0,				0 },
900 	};
901 	int i;
902 
903 	for (i = 0; dspcode[i].reg != 0; i++)
904 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
905 }
906 
907 static void
908 brgphy_fixup_jitter_bug(struct mii_softc *sc)
909 {
910 	static const struct {
911 		int		reg;
912 		uint16_t	val;
913 	} dspcode[] = {
914 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
915 		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
916 		{ BRGPHY_MII_DSP_RW_PORT,	0x010b },
917 		{ BRGPHY_MII_AUXCTL,		0x0400 },
918 		{ 0,				0 },
919 	};
920 	int i;
921 
922 	for (i = 0; dspcode[i].reg != 0; i++)
923 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
924 }
925 
926 
927 static void
928 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
929 {
930 	uint32_t val;
931 
932 	PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
933 	val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
934 	val &= ~(1 << 8);
935 	PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
936 
937 }
938 
939 
940 static void
941 brgphy_ethernet_wirespeed(struct mii_softc *sc)
942 {
943 	uint32_t	val;
944 
945 	/* Enable Ethernet@WireSpeed. */
946 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
947 	val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
948 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
949 }
950 
951 
952 static void
953 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
954 {
955 	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
956 	uint32_t	val;
957 
958 	/* Set or clear jumbo frame settings in the PHY. */
959 	if (mtu > ETHER_MAX_LEN) {
960 		if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
961 			/* BCM5401 PHY cannot read-modify-write. */
962 			PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
963 		} else {
964 			PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
965 			val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
966 			PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
967 			    val | BRGPHY_AUXCTL_LONG_PKT);
968 		}
969 
970 		val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
971 		PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
972 		    val | BRGPHY_PHY_EXTCTL_HIGH_LA);
973 	} else {
974 		PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
975 		val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
976 		PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
977 		    val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
978 
979 		val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
980 		PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
981 			val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
982 	}
983 }
984 
985 static void
986 brgphy_reset(struct mii_softc *sc)
987 {
988 	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
989 	struct bge_softc *bge_sc = NULL;
990 	struct bce_softc *bce_sc = NULL;
991 	struct ifnet *ifp;
992     int val;
993 
994 	/* Perform a standard PHY reset. */
995 	mii_phy_reset(sc);
996 
997 	/* Handle any PHY specific procedures following the reset. */
998 	switch (bsc->mii_oui) {
999 	case MII_OUI_BROADCOM:
1000 		break;
1001 	case MII_OUI_xxBROADCOM:
1002 		switch (bsc->mii_model) {
1003 		case MII_MODEL_xxBROADCOM_BCM5400:
1004 			bcm5401_load_dspcode(sc);
1005 			break;
1006 		case MII_MODEL_xxBROADCOM_BCM5401:
1007 			if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
1008 				bcm5401_load_dspcode(sc);
1009 			break;
1010 		case MII_MODEL_xxBROADCOM_BCM5411:
1011 			bcm5411_load_dspcode(sc);
1012 			break;
1013 		case MII_MODEL_xxBROADCOM_BCM54K2:
1014 			bcm54k2_load_dspcode(sc);
1015 			break;
1016 		}
1017 		break;
1018 	case MII_OUI_xxBROADCOM_ALT1:
1019 	case MII_OUI_xxBROADCOM_ALT2:
1020 		break;
1021 	}
1022 
1023 	ifp = sc->mii_pdata->mii_ifp;
1024 
1025 	/* Find the driver associated with this PHY. */
1026 	if (strcmp(ifp->if_dname, "bge") == 0)	{
1027 		bge_sc = ifp->if_softc;
1028 	} else if (strcmp(ifp->if_dname, "bce") == 0) {
1029 		bce_sc = ifp->if_softc;
1030 	}
1031 
1032 	/* Handle any bge (NetXtreme/NetLink) workarounds. */
1033 	if (bge_sc) {
1034 		/* Fix up various bugs */
1035 		if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
1036 			brgphy_fixup_5704_a0_bug(sc);
1037 		if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
1038 			brgphy_fixup_adc_bug(sc);
1039 		if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
1040 			brgphy_fixup_adjust_trim(sc);
1041 		if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
1042 			brgphy_fixup_ber_bug(sc);
1043 		if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
1044 			brgphy_fixup_crc_bug(sc);
1045 		if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
1046 			brgphy_fixup_jitter_bug(sc);
1047 
1048 		brgphy_jumbo_settings(sc, ifp->if_mtu);
1049 
1050 		if (bge_sc->bge_phy_flags & BGE_PHY_WIRESPEED)
1051 			brgphy_ethernet_wirespeed(sc);
1052 
1053 		/* Enable Link LED on Dell boxes */
1054 		if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
1055 			PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
1056 			    PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
1057 			    ~BRGPHY_PHY_EXTCTL_3_LED);
1058 		}
1059 
1060 		/* Adjust output voltage (From Linux driver) */
1061 		if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
1062 			PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
1063 
1064 	/* Handle any bce (NetXtreme II) workarounds. */
1065 	} else if (bce_sc) {
1066 
1067 		if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
1068 			(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1069 
1070 			/* Store autoneg capabilities/results in digital block (Page 0) */
1071 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
1072 			PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
1073 				BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
1074 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
1075 
1076 			/* Enable fiber mode and autodetection */
1077 			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
1078 				PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
1079 				BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
1080 				BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
1081 
1082 			/* Enable parallel detection */
1083 			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1084 				PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1085 				BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1086 
1087 			/* Advertise 2.5G support through next page during autoneg */
1088 			if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1089 				PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1090 					PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1091 					BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1092 
1093 			/* Increase TX signal amplitude */
1094 			if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1095 			    (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1096 			    (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1097 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1098 					BRGPHY_5708S_TX_MISC_PG5);
1099 				PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1100 					PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1101 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1102 					BRGPHY_5708S_DIG_PG0);
1103 			}
1104 
1105 			/* Backplanes use special driver/pre-driver/pre-emphasis values. */
1106 			if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1107 				(bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1108 					PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1109 						BRGPHY_5708S_TX_MISC_PG5);
1110 					PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1111 						bce_sc->bce_port_hw_cfg &
1112 						BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1113 					PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1114 						BRGPHY_5708S_DIG_PG0);
1115 			}
1116 		} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1117 			(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1118 
1119 			/* Select the SerDes Digital block of the AN MMD. */
1120 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1121 			val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1122 			val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1123 			val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1124 			PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1125 
1126 			/* Select the Over 1G block of the AN MMD. */
1127 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1128 
1129 			/* Enable autoneg "Next Page" to advertise 2.5G support. */
1130 			val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1131 			if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1132 				val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1133 			else
1134 				val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1135 			PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1136 
1137 			/* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1138 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1139 
1140 			/* Enable MRBE speed autoneg. */
1141 			val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1142 			val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1143 			    BRGPHY_MRBE_MSG_PG5_NP_T2;
1144 			PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1145 
1146 			/* Select the Clause 73 User B0 block of the AN MMD. */
1147 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1148 
1149 			/* Enable MRBE speed autoneg. */
1150 			PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1151 			    BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1152 			    BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1153 			    BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1154 
1155 			/* Restore IEEE0 block (assumed in all brgphy(4) code). */
1156 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1157 
1158         } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1159 			if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1160 				(BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1161 				brgphy_fixup_disable_early_dac(sc);
1162 
1163 			brgphy_jumbo_settings(sc, ifp->if_mtu);
1164 			brgphy_ethernet_wirespeed(sc);
1165 		} else {
1166 			brgphy_fixup_ber_bug(sc);
1167 			brgphy_jumbo_settings(sc, ifp->if_mtu);
1168 			brgphy_ethernet_wirespeed(sc);
1169 		}
1170 
1171 	}
1172 }
1173