1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 The FreeBSD Foundation, Inc. 5 * 6 * This driver was written by Gerald ND Aryeetey <gndaryee@uwaterloo.ca> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 #ifndef _IF_MGB_H_ 33 #define _IF_MGB_H_ 34 35 #define MGB_MICROCHIP_VENDOR_ID 0x1055 36 #define MGB_LAN7430_DEVICE_ID 0x7430 37 #define MGB_LAN7431_DEVICE_ID 0x7431 38 39 #define MGB_TIMEOUT (500) 40 41 /** Control/Status Registers **/ 42 #define MGB_BAR 0 /* PCI Base Address */ 43 44 /** Reset **/ 45 #define MGB_HW_CFG 0x10 /** H/W Configuration Register **/ 46 #define MGB_LITE_RESET 0x2 47 48 /** MAC **/ 49 #define MGB_MAC_CR 0x0100 /** MAC Crontrol Register **/ 50 #define MGB_MAC_ADD_ENBL 0x1000 /* Automatic Duplex Detection */ 51 #define MGB_MAC_ASD_ENBL 0x0800 /* Automatic Speed Detection */ 52 53 #define MGB_MAC_ADDR_BASE_L 0x11C /** MAC address lower 4 bytes (read) register **/ 54 #define MGB_MAC_ADDR_BASE_H 0x118 /** MAC address upper 2 bytes (read) register **/ 55 56 #define MGB_MAC_TX 0x0104 57 #define MGB_MAC_RX 0x0108 58 #define MGB_MAC_ENBL (1 << 0) 59 #define MGB_MAC_DSBL (1 << 1) 60 61 /** MAC Statistics **/ 62 #define MGB_MAC_STAT_RX_FCS_ERR_CNT 0x1200 63 #define MGB_MAC_STAT_RX_ALIGN_ERR_CNT 0x1204 64 #define MGB_MAC_STAT_RX_FRAG_ERR_CNT 0x1208 65 #define MGB_MAC_STAT_RX_JABBER_ERR_CNT 0x120C 66 #define MGB_MAC_STAT_RX_UNDER_ERR_CNT 0x1210 67 #define MGB_MAC_STAT_RX_OVER_ERR_CNT 0x1214 68 #define MGB_MAC_STAT_RX_DROPPED_CNT 0x1218 69 #define MGB_MAC_STAT_RX_BROADCAST_CNT1 0x1220 70 #define MGB_MAC_STAT_RX_BROADCAST_CNT 0x122C 71 #define MGB_MAC_STAT_RX_FRAME_CNT 0x1254 72 #define MGB_MAC_STAT_RX_DROPPED_CNT 0x1218 73 #define MGB_MAC_STAT_RX_BROADCAST_CNT1 0x1220 74 #define MGB_MAC_STAT_RX_BROADCAST_CNT 0x122C 75 #define MGB_MAC_STAT_RX_FRAME_CNT 0x1254 76 /* etc. */ 77 78 /** Receive Filtering Engine **/ 79 #define MGB_RFE_CTL 0x508 80 #define MGB_RFE_ALLOW_BROADCAST (1 << 10) 81 #define MGB_RFE_ALLOW_MULTICAST (1 << 9) 82 #define MGB_RFE_ALLOW_UNICAST (1 << 8) 83 #define MGB_RFE_ALLOW_PERFECT_FILTER (1 << 1) 84 85 /** PHY Reset (via power management control) **/ 86 #define MGB_PMT_CTL 0x14 /** Power Management Control Register **/ 87 #define MGB_PHY_RESET 0x10 88 #define MGB_PHY_READY 0x80 89 90 /** FIFO Controller **/ 91 #define MGB_FCT_TX_CTL 0xC4 92 #define MGB_FCT_RX_CTL 0xAC 93 #define MGB_FCT_ENBL(_channel) (1 << (28 + (_channel))) 94 #define MGB_FCT_DSBL(_channel) (1 << (24 + (_channel))) 95 #define MGB_FCT_RESET(_channel) (1 << (20 + (_channel))) 96 97 /** DMA Controller **/ 98 #define MGB_DMAC_CMD 0xC0C 99 #define MGB_DMAC_RESET (1 << 31) 100 #define MGB_DMAC_TX_START 16 101 #define MGB_DMAC_RX_START 0 102 #define MGB_DMAC_CMD_VAL(s, o, ch) (1 << ((s) + (o) + (ch))) 103 #define MGB_DMAC_CMD_RESET(_s, _ch) MGB_DMAC_CMD_VAL(_s, 8, _ch) 104 #define MGB_DMAC_CMD_START(_s, _ch) MGB_DMAC_CMD_VAL(_s, 4, _ch) 105 #define MGB_DMAC_CMD_STOP( _s, _ch) MGB_DMAC_CMD_VAL(_s, 0, _ch) 106 #define MGB_DMAC_STATE(_start, _stop) \ 107 (((_start) ? 2 : 0) | ((_stop) ? 1 : 0)) 108 #define MGB_DMAC_STATE_INITIAL MGB_DMAC_STATE(0, 0) 109 #define MGB_DMAC_STATE_STARTED MGB_DMAC_STATE(1, 0) 110 #define MGB_DMAC_STATE_STOP_PENDING MGB_DMAC_STATE(1, 1) 111 #define MGB_DMAC_STATE_STOPPED MGB_DMAC_STATE(0, 1) 112 #define MGB_DMAC_CMD_STATE(sc, _s, _ch) \ 113 (MGB_DMAC_STATE( \ 114 CSR_READ_REG(sc, MGB_DMAC_CMD) & MGB_DMAC_CMD_START(_s, _ch), \ 115 CSR_READ_REG(sc, MGB_DMAC_CMD) & MGB_DMAC_CMD_STOP(_s, _ch))) 116 #define MGB_DMAC_STATE_IS_INITIAL(sc, _s, _ch) \ 117 (MGB_DMAC_CMD_STATE(sc, _s, _ch) == MGB_DMAC_STATE_INITIAL) 118 119 #define MGB_DMAC_INTR_STS 0xC10 120 #define MGB_DMAC_INTR_ENBL_SET 0xC14 121 #define MGB_DMAC_INTR_ENBL_CLR 0xC18 122 #define MGB_DMAC_TX_INTR_ENBL(_ch) (1 << (_ch)) 123 #define MGB_DMAC_RX_INTR_ENBL(_ch) (1 << (16 + (_ch))) 124 125 /** DMA Rings **/ 126 /** 127 * Page size is 256 bytes 128 * 129 * Ring size, however, these could be tunable (for RX & TX) 130 * to be a multiple of 4 (max is 65532) 131 * 132 **/ 133 /* In linux driver these numbers are 50 and 65 for tx and rx .... */ 134 #define MGB_DMA_RING_SIZE 16 /* in programming guide, this number is 100 */ 135 #define MGB_DMA_MAXSEGS 32 136 #define MGB_DMA_REG(reg, _channel) ((reg) | ((_channel) << 6)) 137 #define MGB_DMA_RING_LIST_SIZE \ 138 (sizeof(struct mgb_ring_desc) * MGB_DMA_RING_SIZE) 139 #define MGB_DMA_RING_INFO_SIZE \ 140 (sizeof(uint32_t) + MGB_DMA_RING_LIST_SIZE) 141 142 #define MGB_DMA_TX_CONFIG0(_channel) MGB_DMA_REG(0x0D40, _channel) 143 #define MGB_DMA_TX_CONFIG1(_channel) MGB_DMA_REG(0x0D44, _channel) 144 #define MGB_DMA_TX_BASE_H(_channel) MGB_DMA_REG(0x0D48, _channel) 145 #define MGB_DMA_TX_BASE_L(_channel) MGB_DMA_REG(0x0D4C, _channel) 146 #define MGB_DMA_TX_HEAD_WB_H(_channel) MGB_DMA_REG(0x0D50, _channel) /* head Writeback */ 147 #define MGB_DMA_TX_HEAD_WB_L(_channel) MGB_DMA_REG(0x0D54, _channel) 148 #define MGB_DMA_TX_HEAD(_channel) MGB_DMA_REG(0x0D58, _channel) 149 #define MGB_DMA_TX_TAIL(_channel) MGB_DMA_REG(0x0D5C, _channel) 150 151 #define MGB_DMA_RX_CONFIG0(_channel) MGB_DMA_REG(0x0C40, _channel) 152 #define MGB_DMA_RX_CONFIG1(_channel) MGB_DMA_REG(0x0C44, _channel) 153 #define MGB_DMA_RX_BASE_H(_channel) MGB_DMA_REG(0x0C48, _channel) 154 #define MGB_DMA_RX_BASE_L(_channel) MGB_DMA_REG(0x0C4C, _channel) 155 #define MGB_DMA_RX_HEAD_WB_H(_channel) MGB_DMA_REG(0x0C50, _channel) /* head Writeback */ 156 #define MGB_DMA_RX_HEAD_WB_L(_channel) MGB_DMA_REG(0x0C54, _channel) 157 #define MGB_DMA_RX_HEAD(_channel) MGB_DMA_REG(0x0C58, _channel) 158 #define MGB_DMA_RX_TAIL(_channel) MGB_DMA_REG(0x0C5C, _channel) 159 160 #define MGB_DMA_RING_LEN_MASK 0xFFFF 161 #define MGB_DMA_IOC_ENBL 0x10000000 162 #define MGB_DMA_HEAD_WB_LS_ENBL 0x20000000 163 #define MGB_DMA_HEAD_WB_ENBL (1 << 5) 164 #define MGB_DMA_RING_PAD_MASK 0x03000000 165 #define MGB_DMA_RING_PAD_0 0x00000000 166 #define MGB_DMA_RING_PAD_2 0x02000000 167 168 #define MGB_DESC_CTL_OWN (1 << 15) 169 #define MGB_DESC_CTL_FCS (1 << 17) 170 #define MGB_DESC_CTL_IOC (1 << 26) 171 #define MGB_TX_DESC_CTL_LS (1 << 28) 172 #define MGB_TX_DESC_CTL_FS (1 << 29) 173 #define MGB_RX_DESC_CTL_LS (1 << 30) 174 #define MGB_RX_DESC_CTL_FS (1 << 31) 175 #define MGB_DESC_CTL_BUFLEN_MASK (0x0000FFFF) 176 #define MGB_DESC_STS_BUFLEN_MASK (0x00003FFF) 177 #define MGB_DESC_FRAME_LEN_MASK (0x3FFF0000) 178 #define MGB_DESC_GET_FRAME_LEN(_desc) \ 179 (((_desc)->ctl & MGB_DESC_FRAME_LEN_MASK) >> 16) 180 181 #define MGB_NEXT_RING_IDX(_idx) (((_idx) + 1) % MGB_DMA_RING_SIZE) 182 #define MGB_RING_SPACE(_sc) \ 183 ((((_sc)->tx_ring_data.last_head - (_sc)->tx_ring_data.last_tail - 1) \ 184 + MGB_DMA_RING_SIZE ) % MGB_DMA_RING_SIZE ) 185 186 /** PHY **/ 187 #define MGB_MII_ACCESS 0x120 188 #define MGB_MII_DATA 0x124 189 #define MGB_MII_PHY_ADDR_MASK 0x1F 190 #define MGB_MII_PHY_ADDR_SHIFT 11 191 #define MGB_MII_REG_ADDR_MASK 0x1F 192 #define MGB_MII_REG_ADDR_SHIFT 6 193 #define MGB_MII_READ 0x0 194 #define MGB_MII_WRITE 0x2 195 #define MGB_MII_BUSY 0x1 196 197 /** Interrupt registers **/ 198 #define MGB_INTR_STS 0x780 199 #define MGB_INTR_SET 0x784 /* This triggers a particular interrupt */ 200 #define MGB_INTR_ENBL_SET 0x788 201 #define MGB_INTR_STS_ANY (0x1) 202 #define MGB_INTR_STS_RX(_channel) (1 << (24 + (_channel))) 203 #define MGB_INTR_STS_RX_ANY (0xF << 24) 204 #define MGB_INTR_STS_TX(_channel) (1 << (16 + (_channel))) 205 #define MGB_INTR_STS_TX_ANY (0xF << 16) 206 #define MGB_INTR_STS_TEST (1 << 9) 207 #define MGB_INTR_ENBL_CLR 0x78C 208 209 #define MGB_INTR_VEC_ENBL_SET 0x794 210 #define MGB_INTR_VEC_ENBL_CLR 0x798 211 #define MGB_INTR_VEC_ENBL_AUTO_CLR 0x79C 212 #define MGB_INTR_VEC_RX_MAP 0x7A0 213 #define MGB_INTR_VEC_TX_MAP 0x7A4 214 #define MGB_INTR_VEC_OTHER_MAP 0x7A8 215 #define MGB_INTR_VEC_MAP(_vsts, _ch) ((_vsts) << ((_ch) << 2)) 216 #define MGB_INTR_VEC_STS(_v) (1 << (_v)) 217 #define MGB_INTR_RX_VEC_STS(_qid) MGB_INTR_VEC_STS((_qid) + 1) 218 219 220 #define MGB_STS_OK ( 0 ) 221 #define MGB_STS_TIMEOUT (-1 ) 222 223 #define CSR_READ_BYTE(sc, reg) \ 224 bus_read_1((sc)->regs, reg) 225 226 #define CSR_WRITE_BYTE(sc, reg, val) \ 227 bus_write_1((sc)->regs, reg, val) 228 229 #define CSR_UPDATE_BYTE(sc, reg, val) \ 230 CSR_WRITE_BYTE(sc, reg, CSR_READ_BYTE(sc, reg) | (val)) 231 232 #define CSR_READ_REG(sc, reg) \ 233 bus_read_4((sc)->regs, reg) 234 235 #define CSR_WRITE_REG(sc, reg, val) \ 236 bus_write_4((sc)->regs, reg, val) 237 238 #define CSR_CLEAR_REG(sc, reg, bits) \ 239 CSR_WRITE_REG(sc, reg, CSR_READ_REG(sc, reg) & ~(bits)) 240 241 #define CSR_UPDATE_REG(sc, reg, val) \ 242 CSR_WRITE_REG(sc, reg, CSR_READ_REG(sc, reg) | (val)) 243 244 #define CSR_READ_2_BYTES(sc, reg) \ 245 bus_read_2((sc)->regs, reg) 246 247 #define CSR_READ_REG_BYTES(sc, reg, dest, cnt) \ 248 bus_read_region_1((sc)->regs, reg, dest, cnt) 249 250 #define CSR_TRANSLATE_ADDR_LOW32(addr) ((uint64_t) (addr) & 0xFFFFFFFF) 251 #define CSR_TRANSLATE_ADDR_HIGH32(addr) ((uint64_t) (addr) >> 32) 252 253 struct mgb_irq { 254 struct resource *res; 255 void *handler; 256 }; 257 258 enum mgb_dmac_cmd { DMAC_RESET, DMAC_START, DMAC_STOP }; 259 enum mgb_fct_cmd { FCT_RESET, FCT_ENABLE, FCT_DISABLE }; 260 261 struct mgb_ring_desc_addr { 262 uint32_t low; 263 uint32_t high; 264 } __packed; 265 266 /* TODO: With descriptor bit information 267 * this could be done without masks etc. 268 * (using bitwise structs like vmx, 269 * would have to separate rx/tx ring desc 270 * definitions) 271 */ 272 struct mgb_ring_desc { 273 uint32_t ctl; /* data0 */ 274 struct mgb_ring_desc_addr addr; /* data(1|2) */ 275 uint32_t sts; /* data3 */ 276 } __packed; 277 278 #if 0 279 struct mgb_ring_info { 280 uint32_t head_wb; 281 struct mgb_ring_desc *ring; 282 } 283 #endif 284 #define MGB_HEAD_WB_PTR(_ring_info_ptr) \ 285 ((uint32_t *)(_ring_info_ptr)) 286 287 #define MGB_RING_PTR(_ring_info_ptr) \ 288 ((struct mgb_ring_desc *)(MGB_HEAD_WB_PTR(_ring_info_ptr) + 1)) 289 290 struct mgb_ring_data { 291 uint32_t *head_wb; 292 struct mgb_ring_desc *ring; 293 294 bus_addr_t head_wb_bus_addr; 295 bus_addr_t ring_bus_addr; 296 297 uint32_t last_head; 298 uint32_t last_tail; 299 }; 300 301 struct mgb_softc { 302 if_ctx_t ctx; 303 device_t dev; 304 305 struct resource *regs; 306 307 struct resource *pba; 308 struct if_irq admin_irq; 309 struct if_irq rx_irq; 310 311 bool isr_test_flag; 312 313 device_t miibus; 314 int link_state; 315 int baudrate; 316 317 int if_flags; 318 int ethaddr; 319 int flags; 320 321 struct mtx mtx; 322 struct callout watchdog; 323 int timer; 324 325 326 bus_dma_tag_t dma_parent_tag; 327 struct mgb_ring_data rx_ring_data; 328 struct mgb_ring_data tx_ring_data; 329 330 }; 331 332 #endif /* _IF_MGB_H_ */ 333