1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/mbuf.h> 38 #include <sys/rman.h> 39 #include <sys/module.h> 40 #include <sys/proc.h> 41 #include <sys/queue.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/ethernet.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 #include <net/if_vlan_var.h> 55 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/ip.h> 59 #include <netinet/tcp.h> 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 67 #include <machine/atomic.h> 68 #include <machine/bus.h> 69 #include <machine/in_cksum.h> 70 71 #include <dev/jme/if_jmereg.h> 72 #include <dev/jme/if_jmevar.h> 73 74 /* "device miibus" required. See GENERIC if you get errors here. */ 75 #include "miibus_if.h" 76 77 /* Define the following to disable printing Rx errors. */ 78 #undef JME_SHOW_ERRORS 79 80 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 81 82 MODULE_DEPEND(jme, pci, 1, 1, 1); 83 MODULE_DEPEND(jme, ether, 1, 1, 1); 84 MODULE_DEPEND(jme, miibus, 1, 1, 1); 85 86 /* Tunables. */ 87 static int msi_disable = 0; 88 static int msix_disable = 0; 89 TUNABLE_INT("hw.jme.msi_disable", &msi_disable); 90 TUNABLE_INT("hw.jme.msix_disable", &msix_disable); 91 92 /* 93 * Devices supported by this driver. 94 */ 95 static struct jme_dev { 96 uint16_t jme_vendorid; 97 uint16_t jme_deviceid; 98 const char *jme_name; 99 } jme_devs[] = { 100 { VENDORID_JMICRON, DEVICEID_JMC250, 101 "JMicron Inc, JMC250 Gigabit Ethernet" }, 102 { VENDORID_JMICRON, DEVICEID_JMC260, 103 "JMicron Inc, JMC260 Fast Ethernet" }, 104 }; 105 106 static int jme_miibus_readreg(device_t, int, int); 107 static int jme_miibus_writereg(device_t, int, int, int); 108 static void jme_miibus_statchg(device_t); 109 static void jme_mediastatus(struct ifnet *, struct ifmediareq *); 110 static int jme_mediachange(struct ifnet *); 111 static int jme_probe(device_t); 112 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 113 static int jme_eeprom_macaddr(struct jme_softc *); 114 static void jme_reg_macaddr(struct jme_softc *); 115 static void jme_map_intr_vector(struct jme_softc *); 116 static int jme_attach(device_t); 117 static int jme_detach(device_t); 118 static void jme_sysctl_node(struct jme_softc *); 119 static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int); 120 static int jme_dma_alloc(struct jme_softc *); 121 static void jme_dma_free(struct jme_softc *); 122 static int jme_shutdown(device_t); 123 static void jme_setlinkspeed(struct jme_softc *); 124 static void jme_setwol(struct jme_softc *); 125 static int jme_suspend(device_t); 126 static int jme_resume(device_t); 127 static int jme_encap(struct jme_softc *, struct mbuf **); 128 static void jme_tx_task(void *, int); 129 static void jme_start(struct ifnet *); 130 static void jme_watchdog(struct jme_softc *); 131 static int jme_ioctl(struct ifnet *, u_long, caddr_t); 132 static void jme_mac_config(struct jme_softc *); 133 static void jme_link_task(void *, int); 134 static int jme_intr(void *); 135 static void jme_int_task(void *, int); 136 static void jme_txeof(struct jme_softc *); 137 static __inline void jme_discard_rxbuf(struct jme_softc *, int); 138 static void jme_rxeof(struct jme_softc *); 139 static int jme_rxintr(struct jme_softc *, int); 140 static void jme_tick(void *); 141 static void jme_reset(struct jme_softc *); 142 static void jme_init(void *); 143 static void jme_init_locked(struct jme_softc *); 144 static void jme_stop(struct jme_softc *); 145 static void jme_stop_tx(struct jme_softc *); 146 static void jme_stop_rx(struct jme_softc *); 147 static int jme_init_rx_ring(struct jme_softc *); 148 static void jme_init_tx_ring(struct jme_softc *); 149 static void jme_init_ssb(struct jme_softc *); 150 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *); 151 static void jme_set_vlan(struct jme_softc *); 152 static void jme_set_filter(struct jme_softc *); 153 static void jme_stats_clear(struct jme_softc *); 154 static void jme_stats_save(struct jme_softc *); 155 static void jme_stats_update(struct jme_softc *); 156 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 157 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS); 158 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 159 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS); 160 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 161 static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS); 162 163 164 static device_method_t jme_methods[] = { 165 /* Device interface. */ 166 DEVMETHOD(device_probe, jme_probe), 167 DEVMETHOD(device_attach, jme_attach), 168 DEVMETHOD(device_detach, jme_detach), 169 DEVMETHOD(device_shutdown, jme_shutdown), 170 DEVMETHOD(device_suspend, jme_suspend), 171 DEVMETHOD(device_resume, jme_resume), 172 173 /* MII interface. */ 174 DEVMETHOD(miibus_readreg, jme_miibus_readreg), 175 DEVMETHOD(miibus_writereg, jme_miibus_writereg), 176 DEVMETHOD(miibus_statchg, jme_miibus_statchg), 177 178 { NULL, NULL } 179 }; 180 181 static driver_t jme_driver = { 182 "jme", 183 jme_methods, 184 sizeof(struct jme_softc) 185 }; 186 187 static devclass_t jme_devclass; 188 189 DRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0); 190 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0); 191 192 static struct resource_spec jme_res_spec_mem[] = { 193 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 194 { -1, 0, 0 } 195 }; 196 197 static struct resource_spec jme_irq_spec_legacy[] = { 198 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 199 { -1, 0, 0 } 200 }; 201 202 static struct resource_spec jme_irq_spec_msi[] = { 203 { SYS_RES_IRQ, 1, RF_ACTIVE }, 204 { SYS_RES_IRQ, 2, RF_ACTIVE }, 205 { SYS_RES_IRQ, 3, RF_ACTIVE }, 206 { SYS_RES_IRQ, 4, RF_ACTIVE }, 207 { SYS_RES_IRQ, 5, RF_ACTIVE }, 208 { SYS_RES_IRQ, 6, RF_ACTIVE }, 209 { SYS_RES_IRQ, 7, RF_ACTIVE }, 210 { SYS_RES_IRQ, 8, RF_ACTIVE }, 211 { -1, 0, 0 } 212 }; 213 214 /* 215 * Read a PHY register on the MII of the JMC250. 216 */ 217 static int 218 jme_miibus_readreg(device_t dev, int phy, int reg) 219 { 220 struct jme_softc *sc; 221 uint32_t val; 222 int i; 223 224 sc = device_get_softc(dev); 225 226 /* For FPGA version, PHY address 0 should be ignored. */ 227 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 228 if (phy == 0) 229 return (0); 230 } else { 231 if (sc->jme_phyaddr != phy) 232 return (0); 233 } 234 235 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 236 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 237 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 238 DELAY(1); 239 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 240 break; 241 } 242 243 if (i == 0) { 244 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg); 245 return (0); 246 } 247 248 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 249 } 250 251 /* 252 * Write a PHY register on the MII of the JMC250. 253 */ 254 static int 255 jme_miibus_writereg(device_t dev, int phy, int reg, int val) 256 { 257 struct jme_softc *sc; 258 int i; 259 260 sc = device_get_softc(dev); 261 262 /* For FPGA version, PHY address 0 should be ignored. */ 263 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 264 if (phy == 0) 265 return (0); 266 } else { 267 if (sc->jme_phyaddr != phy) 268 return (0); 269 } 270 271 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 272 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 273 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 274 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 275 DELAY(1); 276 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 277 break; 278 } 279 280 if (i == 0) 281 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg); 282 283 return (0); 284 } 285 286 /* 287 * Callback from MII layer when media changes. 288 */ 289 static void 290 jme_miibus_statchg(device_t dev) 291 { 292 struct jme_softc *sc; 293 294 sc = device_get_softc(dev); 295 taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task); 296 } 297 298 /* 299 * Get the current interface media status. 300 */ 301 static void 302 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 303 { 304 struct jme_softc *sc; 305 struct mii_data *mii; 306 307 sc = ifp->if_softc; 308 JME_LOCK(sc); 309 if ((ifp->if_flags & IFF_UP) == 0) { 310 JME_UNLOCK(sc); 311 return; 312 } 313 mii = device_get_softc(sc->jme_miibus); 314 315 mii_pollstat(mii); 316 ifmr->ifm_status = mii->mii_media_status; 317 ifmr->ifm_active = mii->mii_media_active; 318 JME_UNLOCK(sc); 319 } 320 321 /* 322 * Set hardware to newly-selected media. 323 */ 324 static int 325 jme_mediachange(struct ifnet *ifp) 326 { 327 struct jme_softc *sc; 328 struct mii_data *mii; 329 struct mii_softc *miisc; 330 int error; 331 332 sc = ifp->if_softc; 333 JME_LOCK(sc); 334 mii = device_get_softc(sc->jme_miibus); 335 if (mii->mii_instance != 0) { 336 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 337 mii_phy_reset(miisc); 338 } 339 error = mii_mediachg(mii); 340 JME_UNLOCK(sc); 341 342 return (error); 343 } 344 345 static int 346 jme_probe(device_t dev) 347 { 348 struct jme_dev *sp; 349 int i; 350 uint16_t vendor, devid; 351 352 vendor = pci_get_vendor(dev); 353 devid = pci_get_device(dev); 354 sp = jme_devs; 355 for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]); 356 i++, sp++) { 357 if (vendor == sp->jme_vendorid && 358 devid == sp->jme_deviceid) { 359 device_set_desc(dev, sp->jme_name); 360 return (BUS_PROBE_DEFAULT); 361 } 362 } 363 364 return (ENXIO); 365 } 366 367 static int 368 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 369 { 370 uint32_t reg; 371 int i; 372 373 *val = 0; 374 for (i = JME_TIMEOUT; i > 0; i--) { 375 reg = CSR_READ_4(sc, JME_SMBCSR); 376 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 377 break; 378 DELAY(1); 379 } 380 381 if (i == 0) { 382 device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 383 return (ETIMEDOUT); 384 } 385 386 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 387 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 388 for (i = JME_TIMEOUT; i > 0; i--) { 389 DELAY(1); 390 reg = CSR_READ_4(sc, JME_SMBINTF); 391 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 392 break; 393 } 394 395 if (i == 0) { 396 device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 397 return (ETIMEDOUT); 398 } 399 400 reg = CSR_READ_4(sc, JME_SMBINTF); 401 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 402 403 return (0); 404 } 405 406 static int 407 jme_eeprom_macaddr(struct jme_softc *sc) 408 { 409 uint8_t eaddr[ETHER_ADDR_LEN]; 410 uint8_t fup, reg, val; 411 uint32_t offset; 412 int match; 413 414 offset = 0; 415 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 416 fup != JME_EEPROM_SIG0) 417 return (ENOENT); 418 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 419 fup != JME_EEPROM_SIG1) 420 return (ENOENT); 421 match = 0; 422 do { 423 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 424 break; 425 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 426 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 427 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 428 break; 429 if (reg >= JME_PAR0 && 430 reg < JME_PAR0 + ETHER_ADDR_LEN) { 431 if (jme_eeprom_read_byte(sc, offset + 2, 432 &val) != 0) 433 break; 434 eaddr[reg - JME_PAR0] = val; 435 match++; 436 } 437 } 438 /* Check for the end of EEPROM descriptor. */ 439 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 440 break; 441 /* Try next eeprom descriptor. */ 442 offset += JME_EEPROM_DESC_BYTES; 443 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 444 445 if (match == ETHER_ADDR_LEN) { 446 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN); 447 return (0); 448 } 449 450 return (ENOENT); 451 } 452 453 static void 454 jme_reg_macaddr(struct jme_softc *sc) 455 { 456 uint32_t par0, par1; 457 458 /* Read station address. */ 459 par0 = CSR_READ_4(sc, JME_PAR0); 460 par1 = CSR_READ_4(sc, JME_PAR1); 461 par1 &= 0xFFFF; 462 if ((par0 == 0 && par1 == 0) || 463 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) { 464 device_printf(sc->jme_dev, 465 "Failed to retrieve Ethernet address.\n"); 466 } else { 467 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF; 468 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF; 469 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF; 470 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF; 471 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF; 472 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF; 473 } 474 } 475 476 static void 477 jme_map_intr_vector(struct jme_softc *sc) 478 { 479 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES]; 480 481 bzero(map, sizeof(map)); 482 483 /* Map Tx interrupts source to MSI/MSIX vector 2. */ 484 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] = 485 MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP); 486 map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |= 487 MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP); 488 map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |= 489 MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP); 490 map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |= 491 MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP); 492 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 493 MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP); 494 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 495 MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP); 496 map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |= 497 MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP); 498 map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |= 499 MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP); 500 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |= 501 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL); 502 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |= 503 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO); 504 505 /* Map Rx interrupts source to MSI/MSIX vector 1. */ 506 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] = 507 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP); 508 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] = 509 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP); 510 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] = 511 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP); 512 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] = 513 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP); 514 map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] = 515 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY); 516 map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] = 517 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY); 518 map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] = 519 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY); 520 map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] = 521 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY); 522 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] = 523 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL); 524 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] = 525 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL); 526 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] = 527 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL); 528 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] = 529 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL); 530 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] = 531 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO); 532 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] = 533 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO); 534 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] = 535 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO); 536 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] = 537 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO); 538 539 /* Map all other interrupts source to MSI/MSIX vector 0. */ 540 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); 541 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); 542 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); 543 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); 544 } 545 546 static int 547 jme_attach(device_t dev) 548 { 549 struct jme_softc *sc; 550 struct ifnet *ifp; 551 struct mii_softc *miisc; 552 struct mii_data *mii; 553 uint32_t reg; 554 uint16_t burst; 555 int error, i, msic, msixc, pmc; 556 557 error = 0; 558 sc = device_get_softc(dev); 559 sc->jme_dev = dev; 560 561 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 562 MTX_DEF); 563 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0); 564 TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc); 565 TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc); 566 567 /* 568 * Map the device. JMC250 supports both memory mapped and I/O 569 * register space access. Because I/O register access should 570 * use different BARs to access registers it's waste of time 571 * to use I/O register spce access. JMC250 uses 16K to map 572 * entire memory space. 573 */ 574 pci_enable_busmaster(dev); 575 sc->jme_res_spec = jme_res_spec_mem; 576 sc->jme_irq_spec = jme_irq_spec_legacy; 577 error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res); 578 if (error != 0) { 579 device_printf(dev, "cannot allocate memory resources.\n"); 580 goto fail; 581 } 582 583 /* Allocate IRQ resources. */ 584 msixc = pci_msix_count(dev); 585 msic = pci_msi_count(dev); 586 if (bootverbose) { 587 device_printf(dev, "MSIX count : %d\n", msixc); 588 device_printf(dev, "MSI count : %d\n", msic); 589 } 590 591 /* Prefer MSIX over MSI. */ 592 if (msix_disable == 0 || msi_disable == 0) { 593 if (msix_disable == 0 && msixc == JME_MSIX_MESSAGES && 594 pci_alloc_msix(dev, &msixc) == 0) { 595 if (msic == JME_MSIX_MESSAGES) { 596 device_printf(dev, "Using %d MSIX messages.\n", 597 msixc); 598 sc->jme_flags |= JME_FLAG_MSIX; 599 sc->jme_irq_spec = jme_irq_spec_msi; 600 } else 601 pci_release_msi(dev); 602 } 603 if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 && 604 msic == JME_MSI_MESSAGES && 605 pci_alloc_msi(dev, &msic) == 0) { 606 if (msic == JME_MSI_MESSAGES) { 607 device_printf(dev, "Using %d MSI messages.\n", 608 msic); 609 sc->jme_flags |= JME_FLAG_MSI; 610 sc->jme_irq_spec = jme_irq_spec_msi; 611 } else 612 pci_release_msi(dev); 613 } 614 /* Map interrupt vector 0, 1 and 2. */ 615 if ((sc->jme_flags & JME_FLAG_MSI) != 0 || 616 (sc->jme_flags & JME_FLAG_MSIX) != 0) 617 jme_map_intr_vector(sc); 618 } 619 620 error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq); 621 if (error != 0) { 622 device_printf(dev, "cannot allocate IRQ resources.\n"); 623 goto fail; 624 } 625 626 sc->jme_rev = pci_get_device(dev); 627 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) { 628 sc->jme_flags |= JME_FLAG_FASTETH; 629 sc->jme_flags |= JME_FLAG_NOJUMBO; 630 } 631 reg = CSR_READ_4(sc, JME_CHIPMODE); 632 sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 633 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 634 CHIPMODE_NOT_FPGA) 635 sc->jme_flags |= JME_FLAG_FPGA; 636 if (bootverbose) { 637 device_printf(dev, "PCI device revision : 0x%04x\n", 638 sc->jme_rev); 639 device_printf(dev, "Chip revision : 0x%02x\n", 640 sc->jme_chip_rev); 641 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) 642 device_printf(dev, "FPGA revision : 0x%04x\n", 643 (reg & CHIPMODE_FPGA_REV_MASK) >> 644 CHIPMODE_FPGA_REV_SHIFT); 645 } 646 if (sc->jme_chip_rev == 0xFF) { 647 device_printf(dev, "Unknown chip revision : 0x%02x\n", 648 sc->jme_rev); 649 error = ENXIO; 650 goto fail; 651 } 652 653 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) { 654 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 && 655 CHIPMODE_REVFM(sc->jme_chip_rev) == 2) 656 sc->jme_flags |= JME_FLAG_DMA32BIT; 657 sc->jme_flags |= JME_FLAG_TXCLK; 658 sc->jme_flags |= JME_FLAG_HWMIB; 659 } 660 661 /* Reset the ethernet controller. */ 662 jme_reset(sc); 663 664 /* Get station address. */ 665 reg = CSR_READ_4(sc, JME_SMBCSR); 666 if ((reg & SMBCSR_EEPROM_PRESENT) != 0) 667 error = jme_eeprom_macaddr(sc); 668 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) { 669 if (error != 0 && (bootverbose)) 670 device_printf(sc->jme_dev, 671 "ethernet hardware address not found in EEPROM.\n"); 672 jme_reg_macaddr(sc); 673 } 674 675 /* 676 * Save PHY address. 677 * Integrated JR0211 has fixed PHY address whereas FPGA version 678 * requires PHY probing to get correct PHY address. 679 */ 680 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 681 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 682 GPREG0_PHY_ADDR_MASK; 683 if (bootverbose) 684 device_printf(dev, "PHY is at address %d.\n", 685 sc->jme_phyaddr); 686 } else 687 sc->jme_phyaddr = 0; 688 689 /* Set max allowable DMA size. */ 690 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 691 sc->jme_flags |= JME_FLAG_PCIE; 692 burst = pci_read_config(dev, i + 0x08, 2); 693 if (bootverbose) { 694 device_printf(dev, "Read request size : %d bytes.\n", 695 128 << ((burst >> 12) & 0x07)); 696 device_printf(dev, "TLP payload size : %d bytes.\n", 697 128 << ((burst >> 5) & 0x07)); 698 } 699 switch ((burst >> 12) & 0x07) { 700 case 0: 701 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 702 break; 703 case 1: 704 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 705 break; 706 default: 707 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 708 break; 709 } 710 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 711 } else { 712 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 713 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 714 } 715 /* Create coalescing sysctl node. */ 716 jme_sysctl_node(sc); 717 if ((error = jme_dma_alloc(sc) != 0)) 718 goto fail; 719 720 ifp = sc->jme_ifp = if_alloc(IFT_ETHER); 721 if (ifp == NULL) { 722 device_printf(dev, "cannot allocate ifnet structure.\n"); 723 error = ENXIO; 724 goto fail; 725 } 726 727 ifp->if_softc = sc; 728 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 729 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 730 ifp->if_ioctl = jme_ioctl; 731 ifp->if_start = jme_start; 732 ifp->if_init = jme_init; 733 ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1; 734 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 735 IFQ_SET_READY(&ifp->if_snd); 736 /* JMC250 supports Tx/Rx checksum offload as well as TSO. */ 737 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 738 ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO; 739 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 740 sc->jme_flags |= JME_FLAG_PMCAP; 741 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 742 } 743 ifp->if_capenable = ifp->if_capabilities; 744 745 /* Set up MII bus. */ 746 if ((error = mii_phy_probe(dev, &sc->jme_miibus, jme_mediachange, 747 jme_mediastatus)) != 0) { 748 device_printf(dev, "no PHY found!\n"); 749 goto fail; 750 } 751 752 /* 753 * Force PHY to FPGA mode. 754 */ 755 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 756 mii = device_get_softc(sc->jme_miibus); 757 if (mii->mii_instance != 0) { 758 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 759 if (miisc->mii_phy != 0) { 760 sc->jme_phyaddr = miisc->mii_phy; 761 break; 762 } 763 } 764 if (sc->jme_phyaddr != 0) { 765 device_printf(sc->jme_dev, 766 "FPGA PHY is at %d\n", sc->jme_phyaddr); 767 /* vendor magic. */ 768 jme_miibus_writereg(dev, sc->jme_phyaddr, 27, 769 0x0004); 770 } 771 } 772 } 773 774 ether_ifattach(ifp, sc->jme_eaddr); 775 776 /* VLAN capability setup */ 777 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 778 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 779 ifp->if_capenable = ifp->if_capabilities; 780 781 /* Tell the upper layer(s) we support long frames. */ 782 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 783 784 /* Create local taskq. */ 785 TASK_INIT(&sc->jme_tx_task, 1, jme_tx_task, ifp); 786 sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK, 787 taskqueue_thread_enqueue, &sc->jme_tq); 788 if (sc->jme_tq == NULL) { 789 device_printf(dev, "could not create taskqueue.\n"); 790 ether_ifdetach(ifp); 791 error = ENXIO; 792 goto fail; 793 } 794 taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq", 795 device_get_nameunit(sc->jme_dev)); 796 797 if ((sc->jme_flags & JME_FLAG_MSIX) != 0) 798 msic = JME_MSIX_MESSAGES; 799 else if ((sc->jme_flags & JME_FLAG_MSI) != 0) 800 msic = JME_MSI_MESSAGES; 801 else 802 msic = 1; 803 for (i = 0; i < msic; i++) { 804 error = bus_setup_intr(dev, sc->jme_irq[i], 805 INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc, 806 &sc->jme_intrhand[i]); 807 if (error != 0) 808 break; 809 } 810 811 if (error != 0) { 812 device_printf(dev, "could not set up interrupt handler.\n"); 813 taskqueue_free(sc->jme_tq); 814 sc->jme_tq = NULL; 815 ether_ifdetach(ifp); 816 goto fail; 817 } 818 819 fail: 820 if (error != 0) 821 jme_detach(dev); 822 823 return (error); 824 } 825 826 static int 827 jme_detach(device_t dev) 828 { 829 struct jme_softc *sc; 830 struct ifnet *ifp; 831 int i, msic; 832 833 sc = device_get_softc(dev); 834 835 ifp = sc->jme_ifp; 836 if (device_is_attached(dev)) { 837 JME_LOCK(sc); 838 sc->jme_flags |= JME_FLAG_DETACH; 839 jme_stop(sc); 840 JME_UNLOCK(sc); 841 callout_drain(&sc->jme_tick_ch); 842 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 843 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task); 844 taskqueue_drain(taskqueue_swi, &sc->jme_link_task); 845 ether_ifdetach(ifp); 846 } 847 848 if (sc->jme_tq != NULL) { 849 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 850 taskqueue_free(sc->jme_tq); 851 sc->jme_tq = NULL; 852 } 853 854 if (sc->jme_miibus != NULL) { 855 device_delete_child(dev, sc->jme_miibus); 856 sc->jme_miibus = NULL; 857 } 858 bus_generic_detach(dev); 859 jme_dma_free(sc); 860 861 if (ifp != NULL) { 862 if_free(ifp); 863 sc->jme_ifp = NULL; 864 } 865 866 msic = 1; 867 if ((sc->jme_flags & JME_FLAG_MSIX) != 0) 868 msic = JME_MSIX_MESSAGES; 869 else if ((sc->jme_flags & JME_FLAG_MSI) != 0) 870 msic = JME_MSI_MESSAGES; 871 else 872 msic = 1; 873 for (i = 0; i < msic; i++) { 874 if (sc->jme_intrhand[i] != NULL) { 875 bus_teardown_intr(dev, sc->jme_irq[i], 876 sc->jme_intrhand[i]); 877 sc->jme_intrhand[i] = NULL; 878 } 879 } 880 881 bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq); 882 if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0) 883 pci_release_msi(dev); 884 bus_release_resources(dev, sc->jme_res_spec, sc->jme_res); 885 mtx_destroy(&sc->jme_mtx); 886 887 return (0); 888 } 889 890 #define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 891 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 892 893 static void 894 jme_sysctl_node(struct jme_softc *sc) 895 { 896 struct sysctl_ctx_list *ctx; 897 struct sysctl_oid_list *child, *parent; 898 struct sysctl_oid *tree; 899 struct jme_hw_stats *stats; 900 int error; 901 902 stats = &sc->jme_stats; 903 ctx = device_get_sysctl_ctx(sc->jme_dev); 904 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)); 905 906 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to", 907 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 0, 908 sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout"); 909 910 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt", 911 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 0, 912 sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet"); 913 914 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to", 915 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 0, 916 sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout"); 917 918 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt", 919 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 0, 920 sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet"); 921 922 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 923 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 0, 924 sysctl_hw_jme_proc_limit, "I", 925 "max number of Rx events to process"); 926 927 /* Pull in device tunables. */ 928 sc->jme_process_limit = JME_PROC_DEFAULT; 929 error = resource_int_value(device_get_name(sc->jme_dev), 930 device_get_unit(sc->jme_dev), "process_limit", 931 &sc->jme_process_limit); 932 if (error == 0) { 933 if (sc->jme_process_limit < JME_PROC_MIN || 934 sc->jme_process_limit > JME_PROC_MAX) { 935 device_printf(sc->jme_dev, 936 "process_limit value out of range; " 937 "using default: %d\n", JME_PROC_DEFAULT); 938 sc->jme_process_limit = JME_PROC_DEFAULT; 939 } 940 } 941 942 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 943 error = resource_int_value(device_get_name(sc->jme_dev), 944 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to); 945 if (error == 0) { 946 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN || 947 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) { 948 device_printf(sc->jme_dev, 949 "tx_coal_to value out of range; " 950 "using default: %d\n", PCCTX_COAL_TO_DEFAULT); 951 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 952 } 953 } 954 955 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 956 error = resource_int_value(device_get_name(sc->jme_dev), 957 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to); 958 if (error == 0) { 959 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN || 960 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) { 961 device_printf(sc->jme_dev, 962 "tx_coal_pkt value out of range; " 963 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT); 964 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 965 } 966 } 967 968 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 969 error = resource_int_value(device_get_name(sc->jme_dev), 970 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to); 971 if (error == 0) { 972 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN || 973 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) { 974 device_printf(sc->jme_dev, 975 "rx_coal_to value out of range; " 976 "using default: %d\n", PCCRX_COAL_TO_DEFAULT); 977 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 978 } 979 } 980 981 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 982 error = resource_int_value(device_get_name(sc->jme_dev), 983 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to); 984 if (error == 0) { 985 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN || 986 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) { 987 device_printf(sc->jme_dev, 988 "tx_coal_pkt value out of range; " 989 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT); 990 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 991 } 992 } 993 994 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 995 return; 996 997 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 998 NULL, "JME statistics"); 999 parent = SYSCTL_CHILDREN(tree); 1000 1001 /* Rx statistics. */ 1002 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1003 NULL, "Rx MAC statistics"); 1004 child = SYSCTL_CHILDREN(tree); 1005 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1006 &stats->rx_good_frames, "Good frames"); 1007 JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1008 &stats->rx_crc_errs, "CRC errors"); 1009 JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs", 1010 &stats->rx_mii_errs, "MII errors"); 1011 JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1012 &stats->rx_fifo_oflows, "FIFO overflows"); 1013 JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty", 1014 &stats->rx_desc_empty, "Descriptor empty"); 1015 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1016 &stats->rx_bad_frames, "Bad frames"); 1017 1018 /* Tx statistics. */ 1019 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1020 NULL, "Tx MAC statistics"); 1021 child = SYSCTL_CHILDREN(tree); 1022 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1023 &stats->tx_good_frames, "Good frames"); 1024 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1025 &stats->tx_bad_frames, "Bad frames"); 1026 } 1027 1028 #undef JME_SYSCTL_STAT_ADD32 1029 1030 struct jme_dmamap_arg { 1031 bus_addr_t jme_busaddr; 1032 }; 1033 1034 static void 1035 jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1036 { 1037 struct jme_dmamap_arg *ctx; 1038 1039 if (error != 0) 1040 return; 1041 1042 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1043 1044 ctx = (struct jme_dmamap_arg *)arg; 1045 ctx->jme_busaddr = segs[0].ds_addr; 1046 } 1047 1048 static int 1049 jme_dma_alloc(struct jme_softc *sc) 1050 { 1051 struct jme_dmamap_arg ctx; 1052 struct jme_txdesc *txd; 1053 struct jme_rxdesc *rxd; 1054 bus_addr_t lowaddr, rx_ring_end, tx_ring_end; 1055 int error, i; 1056 1057 lowaddr = BUS_SPACE_MAXADDR; 1058 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1059 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1060 1061 again: 1062 /* Create parent ring tag. */ 1063 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1064 1, 0, /* algnmnt, boundary */ 1065 lowaddr, /* lowaddr */ 1066 BUS_SPACE_MAXADDR, /* highaddr */ 1067 NULL, NULL, /* filter, filterarg */ 1068 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1069 0, /* nsegments */ 1070 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1071 0, /* flags */ 1072 NULL, NULL, /* lockfunc, lockarg */ 1073 &sc->jme_cdata.jme_ring_tag); 1074 if (error != 0) { 1075 device_printf(sc->jme_dev, 1076 "could not create parent ring DMA tag.\n"); 1077 goto fail; 1078 } 1079 /* Create tag for Tx ring. */ 1080 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1081 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 1082 BUS_SPACE_MAXADDR, /* lowaddr */ 1083 BUS_SPACE_MAXADDR, /* highaddr */ 1084 NULL, NULL, /* filter, filterarg */ 1085 JME_TX_RING_SIZE, /* maxsize */ 1086 1, /* nsegments */ 1087 JME_TX_RING_SIZE, /* maxsegsize */ 1088 0, /* flags */ 1089 NULL, NULL, /* lockfunc, lockarg */ 1090 &sc->jme_cdata.jme_tx_ring_tag); 1091 if (error != 0) { 1092 device_printf(sc->jme_dev, 1093 "could not allocate Tx ring DMA tag.\n"); 1094 goto fail; 1095 } 1096 1097 /* Create tag for Rx ring. */ 1098 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1099 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 1100 lowaddr, /* lowaddr */ 1101 BUS_SPACE_MAXADDR, /* highaddr */ 1102 NULL, NULL, /* filter, filterarg */ 1103 JME_RX_RING_SIZE, /* maxsize */ 1104 1, /* nsegments */ 1105 JME_RX_RING_SIZE, /* maxsegsize */ 1106 0, /* flags */ 1107 NULL, NULL, /* lockfunc, lockarg */ 1108 &sc->jme_cdata.jme_rx_ring_tag); 1109 if (error != 0) { 1110 device_printf(sc->jme_dev, 1111 "could not allocate Rx ring DMA tag.\n"); 1112 goto fail; 1113 } 1114 1115 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1116 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag, 1117 (void **)&sc->jme_rdata.jme_tx_ring, 1118 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1119 &sc->jme_cdata.jme_tx_ring_map); 1120 if (error != 0) { 1121 device_printf(sc->jme_dev, 1122 "could not allocate DMA'able memory for Tx ring.\n"); 1123 goto fail; 1124 } 1125 1126 ctx.jme_busaddr = 0; 1127 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag, 1128 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring, 1129 JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1130 if (error != 0 || ctx.jme_busaddr == 0) { 1131 device_printf(sc->jme_dev, 1132 "could not load DMA'able memory for Tx ring.\n"); 1133 goto fail; 1134 } 1135 sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr; 1136 1137 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1138 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag, 1139 (void **)&sc->jme_rdata.jme_rx_ring, 1140 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1141 &sc->jme_cdata.jme_rx_ring_map); 1142 if (error != 0) { 1143 device_printf(sc->jme_dev, 1144 "could not allocate DMA'able memory for Rx ring.\n"); 1145 goto fail; 1146 } 1147 1148 ctx.jme_busaddr = 0; 1149 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag, 1150 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring, 1151 JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1152 if (error != 0 || ctx.jme_busaddr == 0) { 1153 device_printf(sc->jme_dev, 1154 "could not load DMA'able memory for Rx ring.\n"); 1155 goto fail; 1156 } 1157 sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr; 1158 1159 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1160 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 1161 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr + 1162 JME_TX_RING_SIZE; 1163 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr + 1164 JME_RX_RING_SIZE; 1165 if ((JME_ADDR_HI(tx_ring_end) != 1166 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) || 1167 (JME_ADDR_HI(rx_ring_end) != 1168 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) { 1169 device_printf(sc->jme_dev, "4GB boundary crossed, " 1170 "switching to 32bit DMA address mode.\n"); 1171 jme_dma_free(sc); 1172 /* Limit DMA address space to 32bit and try again. */ 1173 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1174 goto again; 1175 } 1176 } 1177 1178 lowaddr = BUS_SPACE_MAXADDR; 1179 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1180 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1181 /* Create parent buffer tag. */ 1182 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1183 1, 0, /* algnmnt, boundary */ 1184 lowaddr, /* lowaddr */ 1185 BUS_SPACE_MAXADDR, /* highaddr */ 1186 NULL, NULL, /* filter, filterarg */ 1187 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1188 0, /* nsegments */ 1189 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1190 0, /* flags */ 1191 NULL, NULL, /* lockfunc, lockarg */ 1192 &sc->jme_cdata.jme_buffer_tag); 1193 if (error != 0) { 1194 device_printf(sc->jme_dev, 1195 "could not create parent buffer DMA tag.\n"); 1196 goto fail; 1197 } 1198 1199 /* Create shadow status block tag. */ 1200 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1201 JME_SSB_ALIGN, 0, /* algnmnt, boundary */ 1202 BUS_SPACE_MAXADDR, /* lowaddr */ 1203 BUS_SPACE_MAXADDR, /* highaddr */ 1204 NULL, NULL, /* filter, filterarg */ 1205 JME_SSB_SIZE, /* maxsize */ 1206 1, /* nsegments */ 1207 JME_SSB_SIZE, /* maxsegsize */ 1208 0, /* flags */ 1209 NULL, NULL, /* lockfunc, lockarg */ 1210 &sc->jme_cdata.jme_ssb_tag); 1211 if (error != 0) { 1212 device_printf(sc->jme_dev, 1213 "could not create shared status block DMA tag.\n"); 1214 goto fail; 1215 } 1216 1217 /* Create tag for Tx buffers. */ 1218 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1219 1, 0, /* algnmnt, boundary */ 1220 BUS_SPACE_MAXADDR, /* lowaddr */ 1221 BUS_SPACE_MAXADDR, /* highaddr */ 1222 NULL, NULL, /* filter, filterarg */ 1223 JME_TSO_MAXSIZE, /* maxsize */ 1224 JME_MAXTXSEGS, /* nsegments */ 1225 JME_TSO_MAXSEGSIZE, /* maxsegsize */ 1226 0, /* flags */ 1227 NULL, NULL, /* lockfunc, lockarg */ 1228 &sc->jme_cdata.jme_tx_tag); 1229 if (error != 0) { 1230 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1231 goto fail; 1232 } 1233 1234 /* Create tag for Rx buffers. */ 1235 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1236 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 1237 BUS_SPACE_MAXADDR, /* lowaddr */ 1238 BUS_SPACE_MAXADDR, /* highaddr */ 1239 NULL, NULL, /* filter, filterarg */ 1240 MCLBYTES, /* maxsize */ 1241 1, /* nsegments */ 1242 MCLBYTES, /* maxsegsize */ 1243 0, /* flags */ 1244 NULL, NULL, /* lockfunc, lockarg */ 1245 &sc->jme_cdata.jme_rx_tag); 1246 if (error != 0) { 1247 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n"); 1248 goto fail; 1249 } 1250 1251 /* 1252 * Allocate DMA'able memory and load the DMA map for shared 1253 * status block. 1254 */ 1255 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag, 1256 (void **)&sc->jme_rdata.jme_ssb_block, 1257 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1258 &sc->jme_cdata.jme_ssb_map); 1259 if (error != 0) { 1260 device_printf(sc->jme_dev, "could not allocate DMA'able " 1261 "memory for shared status block.\n"); 1262 goto fail; 1263 } 1264 1265 ctx.jme_busaddr = 0; 1266 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag, 1267 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block, 1268 JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1269 if (error != 0 || ctx.jme_busaddr == 0) { 1270 device_printf(sc->jme_dev, "could not load DMA'able memory " 1271 "for shared status block.\n"); 1272 goto fail; 1273 } 1274 sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr; 1275 1276 /* Create DMA maps for Tx buffers. */ 1277 for (i = 0; i < JME_TX_RING_CNT; i++) { 1278 txd = &sc->jme_cdata.jme_txdesc[i]; 1279 txd->tx_m = NULL; 1280 txd->tx_dmamap = NULL; 1281 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0, 1282 &txd->tx_dmamap); 1283 if (error != 0) { 1284 device_printf(sc->jme_dev, 1285 "could not create Tx dmamap.\n"); 1286 goto fail; 1287 } 1288 } 1289 /* Create DMA maps for Rx buffers. */ 1290 if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1291 &sc->jme_cdata.jme_rx_sparemap)) != 0) { 1292 device_printf(sc->jme_dev, 1293 "could not create spare Rx dmamap.\n"); 1294 goto fail; 1295 } 1296 for (i = 0; i < JME_RX_RING_CNT; i++) { 1297 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1298 rxd->rx_m = NULL; 1299 rxd->rx_dmamap = NULL; 1300 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1301 &rxd->rx_dmamap); 1302 if (error != 0) { 1303 device_printf(sc->jme_dev, 1304 "could not create Rx dmamap.\n"); 1305 goto fail; 1306 } 1307 } 1308 1309 fail: 1310 return (error); 1311 } 1312 1313 static void 1314 jme_dma_free(struct jme_softc *sc) 1315 { 1316 struct jme_txdesc *txd; 1317 struct jme_rxdesc *rxd; 1318 int i; 1319 1320 /* Tx ring */ 1321 if (sc->jme_cdata.jme_tx_ring_tag != NULL) { 1322 if (sc->jme_cdata.jme_tx_ring_map) 1323 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag, 1324 sc->jme_cdata.jme_tx_ring_map); 1325 if (sc->jme_cdata.jme_tx_ring_map && 1326 sc->jme_rdata.jme_tx_ring) 1327 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag, 1328 sc->jme_rdata.jme_tx_ring, 1329 sc->jme_cdata.jme_tx_ring_map); 1330 sc->jme_rdata.jme_tx_ring = NULL; 1331 sc->jme_cdata.jme_tx_ring_map = NULL; 1332 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag); 1333 sc->jme_cdata.jme_tx_ring_tag = NULL; 1334 } 1335 /* Rx ring */ 1336 if (sc->jme_cdata.jme_rx_ring_tag != NULL) { 1337 if (sc->jme_cdata.jme_rx_ring_map) 1338 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag, 1339 sc->jme_cdata.jme_rx_ring_map); 1340 if (sc->jme_cdata.jme_rx_ring_map && 1341 sc->jme_rdata.jme_rx_ring) 1342 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag, 1343 sc->jme_rdata.jme_rx_ring, 1344 sc->jme_cdata.jme_rx_ring_map); 1345 sc->jme_rdata.jme_rx_ring = NULL; 1346 sc->jme_cdata.jme_rx_ring_map = NULL; 1347 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag); 1348 sc->jme_cdata.jme_rx_ring_tag = NULL; 1349 } 1350 /* Tx buffers */ 1351 if (sc->jme_cdata.jme_tx_tag != NULL) { 1352 for (i = 0; i < JME_TX_RING_CNT; i++) { 1353 txd = &sc->jme_cdata.jme_txdesc[i]; 1354 if (txd->tx_dmamap != NULL) { 1355 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag, 1356 txd->tx_dmamap); 1357 txd->tx_dmamap = NULL; 1358 } 1359 } 1360 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag); 1361 sc->jme_cdata.jme_tx_tag = NULL; 1362 } 1363 /* Rx buffers */ 1364 if (sc->jme_cdata.jme_rx_tag != NULL) { 1365 for (i = 0; i < JME_RX_RING_CNT; i++) { 1366 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1367 if (rxd->rx_dmamap != NULL) { 1368 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1369 rxd->rx_dmamap); 1370 rxd->rx_dmamap = NULL; 1371 } 1372 } 1373 if (sc->jme_cdata.jme_rx_sparemap != NULL) { 1374 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1375 sc->jme_cdata.jme_rx_sparemap); 1376 sc->jme_cdata.jme_rx_sparemap = NULL; 1377 } 1378 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag); 1379 sc->jme_cdata.jme_rx_tag = NULL; 1380 } 1381 1382 /* Shared status block. */ 1383 if (sc->jme_cdata.jme_ssb_tag != NULL) { 1384 if (sc->jme_cdata.jme_ssb_map) 1385 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1386 sc->jme_cdata.jme_ssb_map); 1387 if (sc->jme_cdata.jme_ssb_map && sc->jme_rdata.jme_ssb_block) 1388 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1389 sc->jme_rdata.jme_ssb_block, 1390 sc->jme_cdata.jme_ssb_map); 1391 sc->jme_rdata.jme_ssb_block = NULL; 1392 sc->jme_cdata.jme_ssb_map = NULL; 1393 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1394 sc->jme_cdata.jme_ssb_tag = NULL; 1395 } 1396 1397 if (sc->jme_cdata.jme_buffer_tag != NULL) { 1398 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1399 sc->jme_cdata.jme_buffer_tag = NULL; 1400 } 1401 if (sc->jme_cdata.jme_ring_tag != NULL) { 1402 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1403 sc->jme_cdata.jme_ring_tag = NULL; 1404 } 1405 } 1406 1407 /* 1408 * Make sure the interface is stopped at reboot time. 1409 */ 1410 static int 1411 jme_shutdown(device_t dev) 1412 { 1413 1414 return (jme_suspend(dev)); 1415 } 1416 1417 /* 1418 * Unlike other ethernet controllers, JMC250 requires 1419 * explicit resetting link speed to 10/100Mbps as gigabit 1420 * link will cunsume more power than 375mA. 1421 * Note, we reset the link speed to 10/100Mbps with 1422 * auto-negotiation but we don't know whether that operation 1423 * would succeed or not as we have no control after powering 1424 * off. If the renegotiation fail WOL may not work. Running 1425 * at 1Gbps draws more power than 375mA at 3.3V which is 1426 * specified in PCI specification and that would result in 1427 * complete shutdowning power to ethernet controller. 1428 * 1429 * TODO 1430 * Save current negotiated media speed/duplex/flow-control 1431 * to softc and restore the same link again after resuming. 1432 * PHY handling such as power down/resetting to 100Mbps 1433 * may be better handled in suspend method in phy driver. 1434 */ 1435 static void 1436 jme_setlinkspeed(struct jme_softc *sc) 1437 { 1438 struct mii_data *mii; 1439 int aneg, i; 1440 1441 JME_LOCK_ASSERT(sc); 1442 1443 mii = device_get_softc(sc->jme_miibus); 1444 mii_pollstat(mii); 1445 aneg = 0; 1446 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1447 switch IFM_SUBTYPE(mii->mii_media_active) { 1448 case IFM_10_T: 1449 case IFM_100_TX: 1450 return; 1451 case IFM_1000_T: 1452 aneg++; 1453 default: 1454 break; 1455 } 1456 } 1457 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1458 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1459 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1460 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1461 BMCR_AUTOEN | BMCR_STARTNEG); 1462 DELAY(1000); 1463 if (aneg != 0) { 1464 /* Poll link state until jme(4) get a 10/100 link. */ 1465 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1466 mii_pollstat(mii); 1467 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1468 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1469 case IFM_10_T: 1470 case IFM_100_TX: 1471 jme_mac_config(sc); 1472 return; 1473 default: 1474 break; 1475 } 1476 } 1477 JME_UNLOCK(sc); 1478 pause("jmelnk", hz); 1479 JME_LOCK(sc); 1480 } 1481 if (i == MII_ANEGTICKS_GIGE) 1482 device_printf(sc->jme_dev, "establishing link failed, " 1483 "WOL may not work!"); 1484 } 1485 /* 1486 * No link, force MAC to have 100Mbps, full-duplex link. 1487 * This is the last resort and may/may not work. 1488 */ 1489 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1490 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1491 jme_mac_config(sc); 1492 } 1493 1494 static void 1495 jme_setwol(struct jme_softc *sc) 1496 { 1497 struct ifnet *ifp; 1498 uint32_t gpr, pmcs; 1499 uint16_t pmstat; 1500 int pmc; 1501 1502 JME_LOCK_ASSERT(sc); 1503 1504 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1505 /* Remove Tx MAC/offload clock to save more power. */ 1506 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1507 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1508 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1509 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1510 /* No PME capability, PHY power down. */ 1511 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1512 MII_BMCR, BMCR_PDOWN); 1513 return; 1514 } 1515 1516 ifp = sc->jme_ifp; 1517 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1518 pmcs = CSR_READ_4(sc, JME_PMCS); 1519 pmcs &= ~PMCS_WOL_ENB_MASK; 1520 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1521 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1522 /* Enable PME message. */ 1523 gpr |= GPREG0_PME_ENB; 1524 /* For gigabit controllers, reset link speed to 10/100. */ 1525 if ((sc->jme_flags & JME_FLAG_FASTETH) == 0) 1526 jme_setlinkspeed(sc); 1527 } 1528 1529 CSR_WRITE_4(sc, JME_PMCS, pmcs); 1530 CSR_WRITE_4(sc, JME_GPREG0, gpr); 1531 /* Remove Tx MAC/offload clock to save more power. */ 1532 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1533 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1534 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1535 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1536 /* Request PME. */ 1537 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1538 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1539 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1540 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1541 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1542 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1543 /* No WOL, PHY power down. */ 1544 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1545 MII_BMCR, BMCR_PDOWN); 1546 } 1547 } 1548 1549 static int 1550 jme_suspend(device_t dev) 1551 { 1552 struct jme_softc *sc; 1553 1554 sc = device_get_softc(dev); 1555 1556 JME_LOCK(sc); 1557 jme_stop(sc); 1558 jme_setwol(sc); 1559 JME_UNLOCK(sc); 1560 1561 return (0); 1562 } 1563 1564 static int 1565 jme_resume(device_t dev) 1566 { 1567 struct jme_softc *sc; 1568 struct ifnet *ifp; 1569 uint16_t pmstat; 1570 int pmc; 1571 1572 sc = device_get_softc(dev); 1573 1574 JME_LOCK(sc); 1575 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1576 pmstat = pci_read_config(sc->jme_dev, 1577 pmc + PCIR_POWER_STATUS, 2); 1578 /* Disable PME clear PME status. */ 1579 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1580 pci_write_config(sc->jme_dev, 1581 pmc + PCIR_POWER_STATUS, pmstat, 2); 1582 } 1583 ifp = sc->jme_ifp; 1584 if ((ifp->if_flags & IFF_UP) != 0) { 1585 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1586 jme_init_locked(sc); 1587 } 1588 1589 JME_UNLOCK(sc); 1590 1591 return (0); 1592 } 1593 1594 static int 1595 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1596 { 1597 struct jme_txdesc *txd; 1598 struct jme_desc *desc; 1599 struct mbuf *m; 1600 bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1601 int error, i, nsegs, prod; 1602 uint32_t cflags, tso_segsz; 1603 1604 JME_LOCK_ASSERT(sc); 1605 1606 M_ASSERTPKTHDR((*m_head)); 1607 1608 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1609 /* 1610 * Due to the adherence to NDIS specification JMC250 1611 * assumes upper stack computed TCP pseudo checksum 1612 * without including payload length. This breaks 1613 * checksum offload for TSO case so recompute TCP 1614 * pseudo checksum for JMC250. Hopefully this wouldn't 1615 * be much burden on modern CPUs. 1616 */ 1617 struct ether_header *eh; 1618 struct ip *ip; 1619 struct tcphdr *tcp; 1620 uint32_t ip_off, poff; 1621 1622 if (M_WRITABLE(*m_head) == 0) { 1623 /* Get a writable copy. */ 1624 m = m_dup(*m_head, M_DONTWAIT); 1625 m_freem(*m_head); 1626 if (m == NULL) { 1627 *m_head = NULL; 1628 return (ENOBUFS); 1629 } 1630 *m_head = m; 1631 } 1632 ip_off = sizeof(struct ether_header); 1633 m = m_pullup(*m_head, ip_off); 1634 if (m == NULL) { 1635 *m_head = NULL; 1636 return (ENOBUFS); 1637 } 1638 eh = mtod(m, struct ether_header *); 1639 /* Check the existence of VLAN tag. */ 1640 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1641 ip_off = sizeof(struct ether_vlan_header); 1642 m = m_pullup(m, ip_off); 1643 if (m == NULL) { 1644 *m_head = NULL; 1645 return (ENOBUFS); 1646 } 1647 } 1648 m = m_pullup(m, ip_off + sizeof(struct ip)); 1649 if (m == NULL) { 1650 *m_head = NULL; 1651 return (ENOBUFS); 1652 } 1653 ip = (struct ip *)(mtod(m, char *) + ip_off); 1654 poff = ip_off + (ip->ip_hl << 2); 1655 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1656 if (m == NULL) { 1657 *m_head = NULL; 1658 return (ENOBUFS); 1659 } 1660 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1661 /* 1662 * Reset IP checksum and recompute TCP pseudo 1663 * checksum that NDIS specification requires. 1664 */ 1665 ip->ip_sum = 0; 1666 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1667 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1668 ip->ip_dst.s_addr, 1669 htons((tcp->th_off << 2) + IPPROTO_TCP)); 1670 /* No need to TSO, force IP checksum offload. */ 1671 (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO; 1672 (*m_head)->m_pkthdr.csum_flags |= CSUM_IP; 1673 } else 1674 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1675 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1676 *m_head = m; 1677 } 1678 1679 prod = sc->jme_cdata.jme_tx_prod; 1680 txd = &sc->jme_cdata.jme_txdesc[prod]; 1681 1682 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1683 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1684 if (error == EFBIG) { 1685 m = m_collapse(*m_head, M_DONTWAIT, JME_MAXTXSEGS); 1686 if (m == NULL) { 1687 m_freem(*m_head); 1688 *m_head = NULL; 1689 return (ENOMEM); 1690 } 1691 *m_head = m; 1692 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1693 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1694 if (error != 0) { 1695 m_freem(*m_head); 1696 *m_head = NULL; 1697 return (error); 1698 } 1699 } else if (error != 0) 1700 return (error); 1701 if (nsegs == 0) { 1702 m_freem(*m_head); 1703 *m_head = NULL; 1704 return (EIO); 1705 } 1706 1707 /* 1708 * Check descriptor overrun. Leave one free descriptor. 1709 * Since we always use 64bit address mode for transmitting, 1710 * each Tx request requires one more dummy descriptor. 1711 */ 1712 if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) { 1713 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 1714 return (ENOBUFS); 1715 } 1716 1717 m = *m_head; 1718 cflags = 0; 1719 tso_segsz = 0; 1720 /* Configure checksum offload and TSO. */ 1721 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1722 tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz << 1723 JME_TD_MSS_SHIFT; 1724 cflags |= JME_TD_TSO; 1725 } else { 1726 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1727 cflags |= JME_TD_IPCSUM; 1728 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1729 cflags |= JME_TD_TCPCSUM; 1730 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1731 cflags |= JME_TD_UDPCSUM; 1732 } 1733 /* Configure VLAN. */ 1734 if ((m->m_flags & M_VLANTAG) != 0) { 1735 cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK); 1736 cflags |= JME_TD_VLAN_TAG; 1737 } 1738 1739 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1740 desc->flags = htole32(cflags); 1741 desc->buflen = htole32(tso_segsz); 1742 desc->addr_hi = htole32(m->m_pkthdr.len); 1743 desc->addr_lo = 0; 1744 sc->jme_cdata.jme_tx_cnt++; 1745 JME_DESC_INC(prod, JME_TX_RING_CNT); 1746 for (i = 0; i < nsegs; i++) { 1747 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1748 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1749 desc->buflen = htole32(txsegs[i].ds_len); 1750 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1751 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1752 sc->jme_cdata.jme_tx_cnt++; 1753 JME_DESC_INC(prod, JME_TX_RING_CNT); 1754 } 1755 1756 /* Update producer index. */ 1757 sc->jme_cdata.jme_tx_prod = prod; 1758 /* 1759 * Finally request interrupt and give the first descriptor 1760 * owenership to hardware. 1761 */ 1762 desc = txd->tx_desc; 1763 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1764 1765 txd->tx_m = m; 1766 txd->tx_ndesc = nsegs + 1; 1767 1768 /* Sync descriptors. */ 1769 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 1770 BUS_DMASYNC_PREWRITE); 1771 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 1772 sc->jme_cdata.jme_tx_ring_map, 1773 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1774 1775 return (0); 1776 } 1777 1778 static void 1779 jme_tx_task(void *arg, int pending) 1780 { 1781 struct ifnet *ifp; 1782 1783 ifp = (struct ifnet *)arg; 1784 jme_start(ifp); 1785 } 1786 1787 static void 1788 jme_start(struct ifnet *ifp) 1789 { 1790 struct jme_softc *sc; 1791 struct mbuf *m_head; 1792 int enq; 1793 1794 sc = ifp->if_softc; 1795 1796 JME_LOCK(sc); 1797 1798 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT) 1799 jme_txeof(sc); 1800 1801 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1802 IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) { 1803 JME_UNLOCK(sc); 1804 return; 1805 } 1806 1807 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1808 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1809 if (m_head == NULL) 1810 break; 1811 /* 1812 * Pack the data into the transmit ring. If we 1813 * don't have room, set the OACTIVE flag and wait 1814 * for the NIC to drain the ring. 1815 */ 1816 if (jme_encap(sc, &m_head)) { 1817 if (m_head == NULL) 1818 break; 1819 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1820 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1821 break; 1822 } 1823 1824 enq++; 1825 /* 1826 * If there's a BPF listener, bounce a copy of this frame 1827 * to him. 1828 */ 1829 ETHER_BPF_MTAP(ifp, m_head); 1830 } 1831 1832 if (enq > 0) { 1833 /* 1834 * Reading TXCSR takes very long time under heavy load 1835 * so cache TXCSR value and writes the ORed value with 1836 * the kick command to the TXCSR. This saves one register 1837 * access cycle. 1838 */ 1839 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1840 TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1841 /* Set a timeout in case the chip goes out to lunch. */ 1842 sc->jme_watchdog_timer = JME_TX_TIMEOUT; 1843 } 1844 1845 JME_UNLOCK(sc); 1846 } 1847 1848 static void 1849 jme_watchdog(struct jme_softc *sc) 1850 { 1851 struct ifnet *ifp; 1852 1853 JME_LOCK_ASSERT(sc); 1854 1855 if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer) 1856 return; 1857 1858 ifp = sc->jme_ifp; 1859 if ((sc->jme_flags & JME_FLAG_LINK) == 0) { 1860 if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n"); 1861 ifp->if_oerrors++; 1862 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1863 jme_init_locked(sc); 1864 return; 1865 } 1866 jme_txeof(sc); 1867 if (sc->jme_cdata.jme_tx_cnt == 0) { 1868 if_printf(sc->jme_ifp, 1869 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1870 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1871 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); 1872 return; 1873 } 1874 1875 if_printf(sc->jme_ifp, "watchdog timeout\n"); 1876 ifp->if_oerrors++; 1877 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1878 jme_init_locked(sc); 1879 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1880 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); 1881 } 1882 1883 static int 1884 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1885 { 1886 struct jme_softc *sc; 1887 struct ifreq *ifr; 1888 struct mii_data *mii; 1889 uint32_t reg; 1890 int error, mask; 1891 1892 sc = ifp->if_softc; 1893 ifr = (struct ifreq *)data; 1894 error = 0; 1895 switch (cmd) { 1896 case SIOCSIFMTU: 1897 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1898 ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 && 1899 ifr->ifr_mtu > JME_MAX_MTU)) { 1900 error = EINVAL; 1901 break; 1902 } 1903 1904 if (ifp->if_mtu != ifr->ifr_mtu) { 1905 /* 1906 * No special configuration is required when interface 1907 * MTU is changed but availability of TSO/Tx checksum 1908 * offload should be chcked against new MTU size as 1909 * FIFO size is just 2K. 1910 */ 1911 JME_LOCK(sc); 1912 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 1913 ifp->if_capenable &= 1914 ~(IFCAP_TXCSUM | IFCAP_TSO4); 1915 ifp->if_hwassist &= 1916 ~(JME_CSUM_FEATURES | CSUM_TSO); 1917 VLAN_CAPABILITIES(ifp); 1918 } 1919 ifp->if_mtu = ifr->ifr_mtu; 1920 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1921 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1922 jme_init_locked(sc); 1923 } 1924 JME_UNLOCK(sc); 1925 } 1926 break; 1927 case SIOCSIFFLAGS: 1928 JME_LOCK(sc); 1929 if ((ifp->if_flags & IFF_UP) != 0) { 1930 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1931 if (((ifp->if_flags ^ sc->jme_if_flags) 1932 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1933 jme_set_filter(sc); 1934 } else { 1935 if ((sc->jme_flags & JME_FLAG_DETACH) == 0) 1936 jme_init_locked(sc); 1937 } 1938 } else { 1939 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1940 jme_stop(sc); 1941 } 1942 sc->jme_if_flags = ifp->if_flags; 1943 JME_UNLOCK(sc); 1944 break; 1945 case SIOCADDMULTI: 1946 case SIOCDELMULTI: 1947 JME_LOCK(sc); 1948 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1949 jme_set_filter(sc); 1950 JME_UNLOCK(sc); 1951 break; 1952 case SIOCSIFMEDIA: 1953 case SIOCGIFMEDIA: 1954 mii = device_get_softc(sc->jme_miibus); 1955 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1956 break; 1957 case SIOCSIFCAP: 1958 JME_LOCK(sc); 1959 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1960 if ((mask & IFCAP_TXCSUM) != 0 && 1961 ifp->if_mtu < JME_TX_FIFO_SIZE) { 1962 if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1963 ifp->if_capenable ^= IFCAP_TXCSUM; 1964 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1965 ifp->if_hwassist |= JME_CSUM_FEATURES; 1966 else 1967 ifp->if_hwassist &= ~JME_CSUM_FEATURES; 1968 } 1969 } 1970 if ((mask & IFCAP_RXCSUM) != 0 && 1971 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1972 ifp->if_capenable ^= IFCAP_RXCSUM; 1973 reg = CSR_READ_4(sc, JME_RXMAC); 1974 reg &= ~RXMAC_CSUM_ENB; 1975 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1976 reg |= RXMAC_CSUM_ENB; 1977 CSR_WRITE_4(sc, JME_RXMAC, reg); 1978 } 1979 if ((mask & IFCAP_TSO4) != 0 && 1980 ifp->if_mtu < JME_TX_FIFO_SIZE) { 1981 if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1982 ifp->if_capenable ^= IFCAP_TSO4; 1983 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1984 ifp->if_hwassist |= CSUM_TSO; 1985 else 1986 ifp->if_hwassist &= ~CSUM_TSO; 1987 } 1988 } 1989 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1990 (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0) 1991 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1992 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1993 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1994 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1995 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1996 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1997 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1998 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1999 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 2000 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2001 jme_set_vlan(sc); 2002 } 2003 JME_UNLOCK(sc); 2004 VLAN_CAPABILITIES(ifp); 2005 break; 2006 default: 2007 error = ether_ioctl(ifp, cmd, data); 2008 break; 2009 } 2010 2011 return (error); 2012 } 2013 2014 static void 2015 jme_mac_config(struct jme_softc *sc) 2016 { 2017 struct mii_data *mii; 2018 uint32_t ghc, gpreg, rxmac, txmac, txpause; 2019 uint32_t txclk; 2020 2021 JME_LOCK_ASSERT(sc); 2022 2023 mii = device_get_softc(sc->jme_miibus); 2024 2025 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2026 DELAY(10); 2027 CSR_WRITE_4(sc, JME_GHC, 0); 2028 ghc = 0; 2029 txclk = 0; 2030 rxmac = CSR_READ_4(sc, JME_RXMAC); 2031 rxmac &= ~RXMAC_FC_ENB; 2032 txmac = CSR_READ_4(sc, JME_TXMAC); 2033 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 2034 txpause = CSR_READ_4(sc, JME_TXPFC); 2035 txpause &= ~TXPFC_PAUSE_ENB; 2036 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2037 ghc |= GHC_FULL_DUPLEX; 2038 rxmac &= ~RXMAC_COLL_DET_ENB; 2039 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 2040 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 2041 TXMAC_FRAME_BURST); 2042 #ifdef notyet 2043 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2044 txpause |= TXPFC_PAUSE_ENB; 2045 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2046 rxmac |= RXMAC_FC_ENB; 2047 #endif 2048 /* Disable retry transmit timer/retry limit. */ 2049 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 2050 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 2051 } else { 2052 rxmac |= RXMAC_COLL_DET_ENB; 2053 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 2054 /* Enable retry transmit timer/retry limit. */ 2055 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 2056 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 2057 } 2058 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 2059 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2060 case IFM_10_T: 2061 ghc |= GHC_SPEED_10; 2062 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2063 break; 2064 case IFM_100_TX: 2065 ghc |= GHC_SPEED_100; 2066 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2067 break; 2068 case IFM_1000_T: 2069 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2070 break; 2071 ghc |= GHC_SPEED_1000; 2072 txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000; 2073 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 2074 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 2075 break; 2076 default: 2077 break; 2078 } 2079 if (sc->jme_rev == DEVICEID_JMC250 && 2080 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 2081 /* 2082 * Workaround occasional packet loss issue of JMC250 A2 2083 * when it runs on half-duplex media. 2084 */ 2085 gpreg = CSR_READ_4(sc, JME_GPREG1); 2086 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 2087 gpreg &= ~GPREG1_HDPX_FIX; 2088 else 2089 gpreg |= GPREG1_HDPX_FIX; 2090 CSR_WRITE_4(sc, JME_GPREG1, gpreg); 2091 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 2092 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2093 /* Extend interface FIFO depth. */ 2094 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2095 0x1B, 0x0000); 2096 } else { 2097 /* Select default interface FIFO depth. */ 2098 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2099 0x1B, 0x0004); 2100 } 2101 } 2102 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2103 ghc |= txclk; 2104 CSR_WRITE_4(sc, JME_GHC, ghc); 2105 CSR_WRITE_4(sc, JME_RXMAC, rxmac); 2106 CSR_WRITE_4(sc, JME_TXMAC, txmac); 2107 CSR_WRITE_4(sc, JME_TXPFC, txpause); 2108 } 2109 2110 static void 2111 jme_link_task(void *arg, int pending) 2112 { 2113 struct jme_softc *sc; 2114 struct mii_data *mii; 2115 struct ifnet *ifp; 2116 struct jme_txdesc *txd; 2117 bus_addr_t paddr; 2118 int i; 2119 2120 sc = (struct jme_softc *)arg; 2121 2122 JME_LOCK(sc); 2123 mii = device_get_softc(sc->jme_miibus); 2124 ifp = sc->jme_ifp; 2125 if (mii == NULL || ifp == NULL || 2126 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2127 JME_UNLOCK(sc); 2128 return; 2129 } 2130 2131 sc->jme_flags &= ~JME_FLAG_LINK; 2132 if ((mii->mii_media_status & IFM_AVALID) != 0) { 2133 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2134 case IFM_10_T: 2135 case IFM_100_TX: 2136 sc->jme_flags |= JME_FLAG_LINK; 2137 break; 2138 case IFM_1000_T: 2139 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2140 break; 2141 sc->jme_flags |= JME_FLAG_LINK; 2142 break; 2143 default: 2144 break; 2145 } 2146 } 2147 2148 /* 2149 * Disabling Rx/Tx MACs have a side-effect of resetting 2150 * JME_TXNDA/JME_RXNDA register to the first address of 2151 * Tx/Rx descriptor address. So driver should reset its 2152 * internal procucer/consumer pointer and reclaim any 2153 * allocated resources. Note, just saving the value of 2154 * JME_TXNDA and JME_RXNDA registers before stopping MAC 2155 * and restoring JME_TXNDA/JME_RXNDA register is not 2156 * sufficient to make sure correct MAC state because 2157 * stopping MAC operation can take a while and hardware 2158 * might have updated JME_TXNDA/JME_RXNDA registers 2159 * during the stop operation. 2160 */ 2161 /* Block execution of task. */ 2162 taskqueue_block(sc->jme_tq); 2163 /* Disable interrupts and stop driver. */ 2164 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2165 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2166 callout_stop(&sc->jme_tick_ch); 2167 sc->jme_watchdog_timer = 0; 2168 2169 /* Stop receiver/transmitter. */ 2170 jme_stop_rx(sc); 2171 jme_stop_tx(sc); 2172 2173 /* XXX Drain all queued tasks. */ 2174 JME_UNLOCK(sc); 2175 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 2176 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task); 2177 JME_LOCK(sc); 2178 2179 jme_rxintr(sc, JME_RX_RING_CNT); 2180 if (sc->jme_cdata.jme_rxhead != NULL) 2181 m_freem(sc->jme_cdata.jme_rxhead); 2182 JME_RXCHAIN_RESET(sc); 2183 jme_txeof(sc); 2184 if (sc->jme_cdata.jme_tx_cnt != 0) { 2185 /* Remove queued packets for transmit. */ 2186 for (i = 0; i < JME_TX_RING_CNT; i++) { 2187 txd = &sc->jme_cdata.jme_txdesc[i]; 2188 if (txd->tx_m != NULL) { 2189 bus_dmamap_sync( 2190 sc->jme_cdata.jme_tx_tag, 2191 txd->tx_dmamap, 2192 BUS_DMASYNC_POSTWRITE); 2193 bus_dmamap_unload( 2194 sc->jme_cdata.jme_tx_tag, 2195 txd->tx_dmamap); 2196 m_freem(txd->tx_m); 2197 txd->tx_m = NULL; 2198 txd->tx_ndesc = 0; 2199 ifp->if_oerrors++; 2200 } 2201 } 2202 } 2203 2204 /* 2205 * Reuse configured Rx descriptors and reset 2206 * procuder/consumer index. 2207 */ 2208 sc->jme_cdata.jme_rx_cons = 0; 2209 atomic_set_int(&sc->jme_morework, 0); 2210 jme_init_tx_ring(sc); 2211 /* Initialize shadow status block. */ 2212 jme_init_ssb(sc); 2213 2214 /* Program MAC with resolved speed/duplex/flow-control. */ 2215 if ((sc->jme_flags & JME_FLAG_LINK) != 0) { 2216 jme_mac_config(sc); 2217 jme_stats_clear(sc); 2218 2219 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2220 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2221 2222 /* Set Tx ring address to the hardware. */ 2223 paddr = JME_TX_RING_ADDR(sc, 0); 2224 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2225 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2226 2227 /* Set Rx ring address to the hardware. */ 2228 paddr = JME_RX_RING_ADDR(sc, 0); 2229 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2230 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2231 2232 /* Restart receiver/transmitter. */ 2233 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 2234 RXCSR_RXQ_START); 2235 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 2236 } 2237 2238 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2239 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2240 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2241 /* Unblock execution of task. */ 2242 taskqueue_unblock(sc->jme_tq); 2243 /* Reenable interrupts. */ 2244 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2245 2246 JME_UNLOCK(sc); 2247 } 2248 2249 static int 2250 jme_intr(void *arg) 2251 { 2252 struct jme_softc *sc; 2253 uint32_t status; 2254 2255 sc = (struct jme_softc *)arg; 2256 2257 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 2258 if (status == 0 || status == 0xFFFFFFFF) 2259 return (FILTER_STRAY); 2260 /* Disable interrupts. */ 2261 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2262 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2263 2264 return (FILTER_HANDLED); 2265 } 2266 2267 static void 2268 jme_int_task(void *arg, int pending) 2269 { 2270 struct jme_softc *sc; 2271 struct ifnet *ifp; 2272 uint32_t status; 2273 int more; 2274 2275 sc = (struct jme_softc *)arg; 2276 ifp = sc->jme_ifp; 2277 2278 status = CSR_READ_4(sc, JME_INTR_STATUS); 2279 more = atomic_readandclear_int(&sc->jme_morework); 2280 if (more != 0) { 2281 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO; 2282 more = 0; 2283 } 2284 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 2285 goto done; 2286 /* Reset PCC counter/timer and Ack interrupts. */ 2287 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 2288 if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 2289 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 2290 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 2291 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 2292 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 2293 more = 0; 2294 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2295 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) { 2296 more = jme_rxintr(sc, sc->jme_process_limit); 2297 if (more != 0) 2298 atomic_set_int(&sc->jme_morework, 1); 2299 } 2300 if ((status & INTR_RXQ_DESC_EMPTY) != 0) { 2301 /* 2302 * Notify hardware availability of new Rx 2303 * buffers. 2304 * Reading RXCSR takes very long time under 2305 * heavy load so cache RXCSR value and writes 2306 * the ORed value with the kick command to 2307 * the RXCSR. This saves one register access 2308 * cycle. 2309 */ 2310 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 2311 RXCSR_RX_ENB | RXCSR_RXQ_START); 2312 } 2313 /* 2314 * Reclaiming Tx buffers are deferred to make jme(4) run 2315 * without locks held. 2316 */ 2317 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2318 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); 2319 } 2320 2321 if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) { 2322 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2323 return; 2324 } 2325 done: 2326 /* Reenable interrupts. */ 2327 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2328 } 2329 2330 static void 2331 jme_txeof(struct jme_softc *sc) 2332 { 2333 struct ifnet *ifp; 2334 struct jme_txdesc *txd; 2335 uint32_t status; 2336 int cons, nsegs; 2337 2338 JME_LOCK_ASSERT(sc); 2339 2340 ifp = sc->jme_ifp; 2341 2342 cons = sc->jme_cdata.jme_tx_cons; 2343 if (cons == sc->jme_cdata.jme_tx_prod) 2344 return; 2345 2346 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2347 sc->jme_cdata.jme_tx_ring_map, 2348 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2349 2350 /* 2351 * Go through our Tx list and free mbufs for those 2352 * frames which have been transmitted. 2353 */ 2354 for (; cons != sc->jme_cdata.jme_tx_prod;) { 2355 txd = &sc->jme_cdata.jme_txdesc[cons]; 2356 status = le32toh(txd->tx_desc->flags); 2357 if ((status & JME_TD_OWN) == JME_TD_OWN) 2358 break; 2359 2360 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 2361 ifp->if_oerrors++; 2362 else { 2363 ifp->if_opackets++; 2364 if ((status & JME_TD_COLLISION) != 0) 2365 ifp->if_collisions += 2366 le32toh(txd->tx_desc->buflen) & 2367 JME_TD_BUF_LEN_MASK; 2368 } 2369 /* 2370 * Only the first descriptor of multi-descriptor 2371 * transmission is updated so driver have to skip entire 2372 * chained buffers for the transmiited frame. In other 2373 * words, JME_TD_OWN bit is valid only at the first 2374 * descriptor of a multi-descriptor transmission. 2375 */ 2376 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2377 sc->jme_rdata.jme_tx_ring[cons].flags = 0; 2378 JME_DESC_INC(cons, JME_TX_RING_CNT); 2379 } 2380 2381 /* Reclaim transferred mbufs. */ 2382 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 2383 BUS_DMASYNC_POSTWRITE); 2384 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 2385 2386 KASSERT(txd->tx_m != NULL, 2387 ("%s: freeing NULL mbuf!\n", __func__)); 2388 m_freem(txd->tx_m); 2389 txd->tx_m = NULL; 2390 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc; 2391 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0, 2392 ("%s: Active Tx desc counter was garbled\n", __func__)); 2393 txd->tx_ndesc = 0; 2394 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2395 } 2396 sc->jme_cdata.jme_tx_cons = cons; 2397 /* Unarm watchog timer when there is no pending descriptors in queue. */ 2398 if (sc->jme_cdata.jme_tx_cnt == 0) 2399 sc->jme_watchdog_timer = 0; 2400 2401 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2402 sc->jme_cdata.jme_tx_ring_map, 2403 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2404 } 2405 2406 static __inline void 2407 jme_discard_rxbuf(struct jme_softc *sc, int cons) 2408 { 2409 struct jme_desc *desc; 2410 2411 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2412 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 2413 desc->buflen = htole32(MCLBYTES); 2414 } 2415 2416 /* Receive a frame. */ 2417 static void 2418 jme_rxeof(struct jme_softc *sc) 2419 { 2420 struct ifnet *ifp; 2421 struct jme_desc *desc; 2422 struct jme_rxdesc *rxd; 2423 struct mbuf *mp, *m; 2424 uint32_t flags, status; 2425 int cons, count, nsegs; 2426 2427 ifp = sc->jme_ifp; 2428 2429 cons = sc->jme_cdata.jme_rx_cons; 2430 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2431 flags = le32toh(desc->flags); 2432 status = le32toh(desc->buflen); 2433 nsegs = JME_RX_NSEGS(status); 2434 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2435 if ((status & JME_RX_ERR_STAT) != 0) { 2436 ifp->if_ierrors++; 2437 jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons); 2438 #ifdef JME_SHOW_ERRORS 2439 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n", 2440 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2441 #endif 2442 sc->jme_cdata.jme_rx_cons += nsegs; 2443 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2444 return; 2445 } 2446 2447 for (count = 0; count < nsegs; count++, 2448 JME_DESC_INC(cons, JME_RX_RING_CNT)) { 2449 rxd = &sc->jme_cdata.jme_rxdesc[cons]; 2450 mp = rxd->rx_m; 2451 /* Add a new receive buffer to the ring. */ 2452 if (jme_newbuf(sc, rxd) != 0) { 2453 ifp->if_iqdrops++; 2454 /* Reuse buffer. */ 2455 for (; count < nsegs; count++) { 2456 jme_discard_rxbuf(sc, cons); 2457 JME_DESC_INC(cons, JME_RX_RING_CNT); 2458 } 2459 if (sc->jme_cdata.jme_rxhead != NULL) { 2460 m_freem(sc->jme_cdata.jme_rxhead); 2461 JME_RXCHAIN_RESET(sc); 2462 } 2463 break; 2464 } 2465 2466 /* 2467 * Assume we've received a full sized frame. 2468 * Actual size is fixed when we encounter the end of 2469 * multi-segmented frame. 2470 */ 2471 mp->m_len = MCLBYTES; 2472 2473 /* Chain received mbufs. */ 2474 if (sc->jme_cdata.jme_rxhead == NULL) { 2475 sc->jme_cdata.jme_rxhead = mp; 2476 sc->jme_cdata.jme_rxtail = mp; 2477 } else { 2478 /* 2479 * Receive processor can receive a maximum frame 2480 * size of 65535 bytes. 2481 */ 2482 mp->m_flags &= ~M_PKTHDR; 2483 sc->jme_cdata.jme_rxtail->m_next = mp; 2484 sc->jme_cdata.jme_rxtail = mp; 2485 } 2486 2487 if (count == nsegs - 1) { 2488 /* Last desc. for this frame. */ 2489 m = sc->jme_cdata.jme_rxhead; 2490 m->m_flags |= M_PKTHDR; 2491 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen; 2492 if (nsegs > 1) { 2493 /* Set first mbuf size. */ 2494 m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2495 /* Set last mbuf size. */ 2496 mp->m_len = sc->jme_cdata.jme_rxlen - 2497 ((MCLBYTES - JME_RX_PAD_BYTES) + 2498 (MCLBYTES * (nsegs - 2))); 2499 } else 2500 m->m_len = sc->jme_cdata.jme_rxlen; 2501 m->m_pkthdr.rcvif = ifp; 2502 2503 /* 2504 * Account for 10bytes auto padding which is used 2505 * to align IP header on 32bit boundary. Also note, 2506 * CRC bytes is automatically removed by the 2507 * hardware. 2508 */ 2509 m->m_data += JME_RX_PAD_BYTES; 2510 2511 /* Set checksum information. */ 2512 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2513 (flags & JME_RD_IPV4) != 0) { 2514 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2515 if ((flags & JME_RD_IPCSUM) != 0) 2516 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2517 if (((flags & JME_RD_MORE_FRAG) == 0) && 2518 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2519 (JME_RD_TCP | JME_RD_TCPCSUM) || 2520 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2521 (JME_RD_UDP | JME_RD_UDPCSUM))) { 2522 m->m_pkthdr.csum_flags |= 2523 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2524 m->m_pkthdr.csum_data = 0xffff; 2525 } 2526 } 2527 2528 /* Check for VLAN tagged packets. */ 2529 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2530 (flags & JME_RD_VLAN_TAG) != 0) { 2531 m->m_pkthdr.ether_vtag = 2532 flags & JME_RD_VLAN_MASK; 2533 m->m_flags |= M_VLANTAG; 2534 } 2535 2536 ifp->if_ipackets++; 2537 /* Pass it on. */ 2538 (*ifp->if_input)(ifp, m); 2539 2540 /* Reset mbuf chains. */ 2541 JME_RXCHAIN_RESET(sc); 2542 } 2543 } 2544 2545 sc->jme_cdata.jme_rx_cons += nsegs; 2546 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2547 } 2548 2549 static int 2550 jme_rxintr(struct jme_softc *sc, int count) 2551 { 2552 struct jme_desc *desc; 2553 int nsegs, prog, pktlen; 2554 2555 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2556 sc->jme_cdata.jme_rx_ring_map, 2557 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2558 2559 for (prog = 0; count > 0; prog++) { 2560 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons]; 2561 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2562 break; 2563 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2564 break; 2565 nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2566 /* 2567 * Check number of segments against received bytes. 2568 * Non-matching value would indicate that hardware 2569 * is still trying to update Rx descriptors. I'm not 2570 * sure whether this check is needed. 2571 */ 2572 pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2573 if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES)) 2574 break; 2575 prog++; 2576 /* Received a frame. */ 2577 jme_rxeof(sc); 2578 count -= nsegs; 2579 } 2580 2581 if (prog > 0) 2582 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2583 sc->jme_cdata.jme_rx_ring_map, 2584 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2585 2586 return (count > 0 ? 0 : EAGAIN); 2587 } 2588 2589 static void 2590 jme_tick(void *arg) 2591 { 2592 struct jme_softc *sc; 2593 struct mii_data *mii; 2594 2595 sc = (struct jme_softc *)arg; 2596 2597 JME_LOCK_ASSERT(sc); 2598 2599 mii = device_get_softc(sc->jme_miibus); 2600 mii_tick(mii); 2601 /* 2602 * Reclaim Tx buffers that have been completed. It's not 2603 * needed here but it would release allocated mbuf chains 2604 * faster and limit the maximum delay to a hz. 2605 */ 2606 jme_txeof(sc); 2607 jme_stats_update(sc); 2608 jme_watchdog(sc); 2609 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2610 } 2611 2612 static void 2613 jme_reset(struct jme_softc *sc) 2614 { 2615 2616 /* Stop receiver, transmitter. */ 2617 jme_stop_rx(sc); 2618 jme_stop_tx(sc); 2619 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2620 DELAY(10); 2621 CSR_WRITE_4(sc, JME_GHC, 0); 2622 } 2623 2624 static void 2625 jme_init(void *xsc) 2626 { 2627 struct jme_softc *sc; 2628 2629 sc = (struct jme_softc *)xsc; 2630 JME_LOCK(sc); 2631 jme_init_locked(sc); 2632 JME_UNLOCK(sc); 2633 } 2634 2635 static void 2636 jme_init_locked(struct jme_softc *sc) 2637 { 2638 struct ifnet *ifp; 2639 struct mii_data *mii; 2640 uint8_t eaddr[ETHER_ADDR_LEN]; 2641 bus_addr_t paddr; 2642 uint32_t reg; 2643 int error; 2644 2645 JME_LOCK_ASSERT(sc); 2646 2647 ifp = sc->jme_ifp; 2648 mii = device_get_softc(sc->jme_miibus); 2649 2650 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2651 return; 2652 /* 2653 * Cancel any pending I/O. 2654 */ 2655 jme_stop(sc); 2656 2657 /* 2658 * Reset the chip to a known state. 2659 */ 2660 jme_reset(sc); 2661 2662 /* Init descriptors. */ 2663 error = jme_init_rx_ring(sc); 2664 if (error != 0) { 2665 device_printf(sc->jme_dev, 2666 "%s: initialization failed: no memory for Rx buffers.\n", 2667 __func__); 2668 jme_stop(sc); 2669 return; 2670 } 2671 jme_init_tx_ring(sc); 2672 /* Initialize shadow status block. */ 2673 jme_init_ssb(sc); 2674 2675 /* Reprogram the station address. */ 2676 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2677 CSR_WRITE_4(sc, JME_PAR0, 2678 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 2679 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 2680 2681 /* 2682 * Configure Tx queue. 2683 * Tx priority queue weight value : 0 2684 * Tx FIFO threshold for processing next packet : 16QW 2685 * Maximum Tx DMA length : 512 2686 * Allow Tx DMA burst. 2687 */ 2688 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2689 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2690 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2691 sc->jme_txcsr |= sc->jme_tx_dma_size; 2692 sc->jme_txcsr |= TXCSR_DMA_BURST; 2693 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2694 2695 /* Set Tx descriptor counter. */ 2696 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT); 2697 2698 /* Set Tx ring address to the hardware. */ 2699 paddr = JME_TX_RING_ADDR(sc, 0); 2700 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2701 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2702 2703 /* Configure TxMAC parameters. */ 2704 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2705 reg |= TXMAC_THRESH_1_PKT; 2706 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2707 CSR_WRITE_4(sc, JME_TXMAC, reg); 2708 2709 /* 2710 * Configure Rx queue. 2711 * FIFO full threshold for transmitting Tx pause packet : 128T 2712 * FIFO threshold for processing next packet : 128QW 2713 * Rx queue 0 select 2714 * Max Rx DMA length : 128 2715 * Rx descriptor retry : 32 2716 * Rx descriptor retry time gap : 256ns 2717 * Don't receive runt/bad frame. 2718 */ 2719 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2720 /* 2721 * Since Rx FIFO size is 4K bytes, receiving frames larger 2722 * than 4K bytes will suffer from Rx FIFO overruns. So 2723 * decrease FIFO threshold to reduce the FIFO overruns for 2724 * frames larger than 4000 bytes. 2725 * For best performance of standard MTU sized frames use 2726 * maximum allowable FIFO threshold, 128QW. Note these do 2727 * not hold on chip full mask verion >=2. For these 2728 * controllers 64QW and 128QW are not valid value. 2729 */ 2730 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) 2731 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2732 else { 2733 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2734 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 2735 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2736 else 2737 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2738 } 2739 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 2740 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2741 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2742 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2743 2744 /* Set Rx descriptor counter. */ 2745 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT); 2746 2747 /* Set Rx ring address to the hardware. */ 2748 paddr = JME_RX_RING_ADDR(sc, 0); 2749 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2750 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2751 2752 /* Clear receive filter. */ 2753 CSR_WRITE_4(sc, JME_RXMAC, 0); 2754 /* Set up the receive filter. */ 2755 jme_set_filter(sc); 2756 jme_set_vlan(sc); 2757 2758 /* 2759 * Disable all WOL bits as WOL can interfere normal Rx 2760 * operation. Also clear WOL detection status bits. 2761 */ 2762 reg = CSR_READ_4(sc, JME_PMCS); 2763 reg &= ~PMCS_WOL_ENB_MASK; 2764 CSR_WRITE_4(sc, JME_PMCS, reg); 2765 2766 reg = CSR_READ_4(sc, JME_RXMAC); 2767 /* 2768 * Pad 10bytes right before received frame. This will greatly 2769 * help Rx performance on strict-alignment architectures as 2770 * it does not need to copy the frame to align the payload. 2771 */ 2772 reg |= RXMAC_PAD_10BYTES; 2773 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2774 reg |= RXMAC_CSUM_ENB; 2775 CSR_WRITE_4(sc, JME_RXMAC, reg); 2776 2777 /* Configure general purpose reg0 */ 2778 reg = CSR_READ_4(sc, JME_GPREG0); 2779 reg &= ~GPREG0_PCC_UNIT_MASK; 2780 /* Set PCC timer resolution to micro-seconds unit. */ 2781 reg |= GPREG0_PCC_UNIT_US; 2782 /* 2783 * Disable all shadow register posting as we have to read 2784 * JME_INTR_STATUS register in jme_int_task. Also it seems 2785 * that it's hard to synchronize interrupt status between 2786 * hardware and software with shadow posting due to 2787 * requirements of bus_dmamap_sync(9). 2788 */ 2789 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2790 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2791 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2792 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2793 /* Disable posting of DW0. */ 2794 reg &= ~GPREG0_POST_DW0_ENB; 2795 /* Clear PME message. */ 2796 reg &= ~GPREG0_PME_ENB; 2797 /* Set PHY address. */ 2798 reg &= ~GPREG0_PHY_ADDR_MASK; 2799 reg |= sc->jme_phyaddr; 2800 CSR_WRITE_4(sc, JME_GPREG0, reg); 2801 2802 /* Configure Tx queue 0 packet completion coalescing. */ 2803 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 2804 PCCTX_COAL_TO_MASK; 2805 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 2806 PCCTX_COAL_PKT_MASK; 2807 reg |= PCCTX_COAL_TXQ0; 2808 CSR_WRITE_4(sc, JME_PCCTX, reg); 2809 2810 /* Configure Rx queue 0 packet completion coalescing. */ 2811 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 2812 PCCRX_COAL_TO_MASK; 2813 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 2814 PCCRX_COAL_PKT_MASK; 2815 CSR_WRITE_4(sc, JME_PCCRX0, reg); 2816 2817 /* Configure shadow status block but don't enable posting. */ 2818 paddr = sc->jme_rdata.jme_ssb_block_paddr; 2819 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2820 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2821 2822 /* Disable Timer 1 and Timer 2. */ 2823 CSR_WRITE_4(sc, JME_TIMER1, 0); 2824 CSR_WRITE_4(sc, JME_TIMER2, 0); 2825 2826 /* Configure retry transmit period, retry limit value. */ 2827 CSR_WRITE_4(sc, JME_TXTRHD, 2828 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2829 TXTRHD_RT_PERIOD_MASK) | 2830 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2831 TXTRHD_RT_LIMIT_SHIFT)); 2832 2833 /* Disable RSS. */ 2834 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 2835 2836 /* Initialize the interrupt mask. */ 2837 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2838 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2839 2840 /* 2841 * Enabling Tx/Rx DMA engines and Rx queue processing is 2842 * done after detection of valid link in jme_link_task. 2843 */ 2844 2845 sc->jme_flags &= ~JME_FLAG_LINK; 2846 /* Set the current media. */ 2847 mii_mediachg(mii); 2848 2849 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2850 2851 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2852 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2853 } 2854 2855 static void 2856 jme_stop(struct jme_softc *sc) 2857 { 2858 struct ifnet *ifp; 2859 struct jme_txdesc *txd; 2860 struct jme_rxdesc *rxd; 2861 int i; 2862 2863 JME_LOCK_ASSERT(sc); 2864 /* 2865 * Mark the interface down and cancel the watchdog timer. 2866 */ 2867 ifp = sc->jme_ifp; 2868 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2869 sc->jme_flags &= ~JME_FLAG_LINK; 2870 callout_stop(&sc->jme_tick_ch); 2871 sc->jme_watchdog_timer = 0; 2872 2873 /* 2874 * Disable interrupts. 2875 */ 2876 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2877 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2878 2879 /* Disable updating shadow status block. */ 2880 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 2881 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 2882 2883 /* Stop receiver, transmitter. */ 2884 jme_stop_rx(sc); 2885 jme_stop_tx(sc); 2886 2887 /* Reclaim Rx/Tx buffers that have been completed. */ 2888 jme_rxintr(sc, JME_RX_RING_CNT); 2889 if (sc->jme_cdata.jme_rxhead != NULL) 2890 m_freem(sc->jme_cdata.jme_rxhead); 2891 JME_RXCHAIN_RESET(sc); 2892 jme_txeof(sc); 2893 /* 2894 * Free RX and TX mbufs still in the queues. 2895 */ 2896 for (i = 0; i < JME_RX_RING_CNT; i++) { 2897 rxd = &sc->jme_cdata.jme_rxdesc[i]; 2898 if (rxd->rx_m != NULL) { 2899 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, 2900 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2901 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, 2902 rxd->rx_dmamap); 2903 m_freem(rxd->rx_m); 2904 rxd->rx_m = NULL; 2905 } 2906 } 2907 for (i = 0; i < JME_TX_RING_CNT; i++) { 2908 txd = &sc->jme_cdata.jme_txdesc[i]; 2909 if (txd->tx_m != NULL) { 2910 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, 2911 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2912 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, 2913 txd->tx_dmamap); 2914 m_freem(txd->tx_m); 2915 txd->tx_m = NULL; 2916 txd->tx_ndesc = 0; 2917 } 2918 } 2919 jme_stats_update(sc); 2920 jme_stats_save(sc); 2921 } 2922 2923 static void 2924 jme_stop_tx(struct jme_softc *sc) 2925 { 2926 uint32_t reg; 2927 int i; 2928 2929 reg = CSR_READ_4(sc, JME_TXCSR); 2930 if ((reg & TXCSR_TX_ENB) == 0) 2931 return; 2932 reg &= ~TXCSR_TX_ENB; 2933 CSR_WRITE_4(sc, JME_TXCSR, reg); 2934 for (i = JME_TIMEOUT; i > 0; i--) { 2935 DELAY(1); 2936 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 2937 break; 2938 } 2939 if (i == 0) 2940 device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 2941 } 2942 2943 static void 2944 jme_stop_rx(struct jme_softc *sc) 2945 { 2946 uint32_t reg; 2947 int i; 2948 2949 reg = CSR_READ_4(sc, JME_RXCSR); 2950 if ((reg & RXCSR_RX_ENB) == 0) 2951 return; 2952 reg &= ~RXCSR_RX_ENB; 2953 CSR_WRITE_4(sc, JME_RXCSR, reg); 2954 for (i = JME_TIMEOUT; i > 0; i--) { 2955 DELAY(1); 2956 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 2957 break; 2958 } 2959 if (i == 0) 2960 device_printf(sc->jme_dev, "stopping recevier timeout!\n"); 2961 } 2962 2963 static void 2964 jme_init_tx_ring(struct jme_softc *sc) 2965 { 2966 struct jme_ring_data *rd; 2967 struct jme_txdesc *txd; 2968 int i; 2969 2970 sc->jme_cdata.jme_tx_prod = 0; 2971 sc->jme_cdata.jme_tx_cons = 0; 2972 sc->jme_cdata.jme_tx_cnt = 0; 2973 2974 rd = &sc->jme_rdata; 2975 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE); 2976 for (i = 0; i < JME_TX_RING_CNT; i++) { 2977 txd = &sc->jme_cdata.jme_txdesc[i]; 2978 txd->tx_m = NULL; 2979 txd->tx_desc = &rd->jme_tx_ring[i]; 2980 txd->tx_ndesc = 0; 2981 } 2982 2983 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2984 sc->jme_cdata.jme_tx_ring_map, 2985 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2986 } 2987 2988 static void 2989 jme_init_ssb(struct jme_softc *sc) 2990 { 2991 struct jme_ring_data *rd; 2992 2993 rd = &sc->jme_rdata; 2994 bzero(rd->jme_ssb_block, JME_SSB_SIZE); 2995 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map, 2996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2997 } 2998 2999 static int 3000 jme_init_rx_ring(struct jme_softc *sc) 3001 { 3002 struct jme_ring_data *rd; 3003 struct jme_rxdesc *rxd; 3004 int i; 3005 3006 sc->jme_cdata.jme_rx_cons = 0; 3007 JME_RXCHAIN_RESET(sc); 3008 atomic_set_int(&sc->jme_morework, 0); 3009 3010 rd = &sc->jme_rdata; 3011 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE); 3012 for (i = 0; i < JME_RX_RING_CNT; i++) { 3013 rxd = &sc->jme_cdata.jme_rxdesc[i]; 3014 rxd->rx_m = NULL; 3015 rxd->rx_desc = &rd->jme_rx_ring[i]; 3016 if (jme_newbuf(sc, rxd) != 0) 3017 return (ENOBUFS); 3018 } 3019 3020 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 3021 sc->jme_cdata.jme_rx_ring_map, 3022 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3023 3024 return (0); 3025 } 3026 3027 static int 3028 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd) 3029 { 3030 struct jme_desc *desc; 3031 struct mbuf *m; 3032 bus_dma_segment_t segs[1]; 3033 bus_dmamap_t map; 3034 int nsegs; 3035 3036 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3037 if (m == NULL) 3038 return (ENOBUFS); 3039 /* 3040 * JMC250 has 64bit boundary alignment limitation so jme(4) 3041 * takes advantage of 10 bytes padding feature of hardware 3042 * in order not to copy entire frame to align IP header on 3043 * 32bit boundary. 3044 */ 3045 m->m_len = m->m_pkthdr.len = MCLBYTES; 3046 3047 if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag, 3048 sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3049 m_freem(m); 3050 return (ENOBUFS); 3051 } 3052 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3053 3054 if (rxd->rx_m != NULL) { 3055 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3056 BUS_DMASYNC_POSTREAD); 3057 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap); 3058 } 3059 map = rxd->rx_dmamap; 3060 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap; 3061 sc->jme_cdata.jme_rx_sparemap = map; 3062 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3063 BUS_DMASYNC_PREREAD); 3064 rxd->rx_m = m; 3065 3066 desc = rxd->rx_desc; 3067 desc->buflen = htole32(segs[0].ds_len); 3068 desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr)); 3069 desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr)); 3070 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 3071 3072 return (0); 3073 } 3074 3075 static void 3076 jme_set_vlan(struct jme_softc *sc) 3077 { 3078 struct ifnet *ifp; 3079 uint32_t reg; 3080 3081 JME_LOCK_ASSERT(sc); 3082 3083 ifp = sc->jme_ifp; 3084 reg = CSR_READ_4(sc, JME_RXMAC); 3085 reg &= ~RXMAC_VLAN_ENB; 3086 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3087 reg |= RXMAC_VLAN_ENB; 3088 CSR_WRITE_4(sc, JME_RXMAC, reg); 3089 } 3090 3091 static void 3092 jme_set_filter(struct jme_softc *sc) 3093 { 3094 struct ifnet *ifp; 3095 struct ifmultiaddr *ifma; 3096 uint32_t crc; 3097 uint32_t mchash[2]; 3098 uint32_t rxcfg; 3099 3100 JME_LOCK_ASSERT(sc); 3101 3102 ifp = sc->jme_ifp; 3103 3104 rxcfg = CSR_READ_4(sc, JME_RXMAC); 3105 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 3106 RXMAC_ALLMULTI); 3107 /* Always accept frames destined to our station address. */ 3108 rxcfg |= RXMAC_UNICAST; 3109 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3110 rxcfg |= RXMAC_BROADCAST; 3111 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3112 if ((ifp->if_flags & IFF_PROMISC) != 0) 3113 rxcfg |= RXMAC_PROMISC; 3114 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3115 rxcfg |= RXMAC_ALLMULTI; 3116 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 3117 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 3118 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3119 return; 3120 } 3121 3122 /* 3123 * Set up the multicast address filter by passing all multicast 3124 * addresses through a CRC generator, and then using the low-order 3125 * 6 bits as an index into the 64 bit multicast hash table. The 3126 * high order bits select the register, while the rest of the bits 3127 * select the bit within the register. 3128 */ 3129 rxcfg |= RXMAC_MULTICAST; 3130 bzero(mchash, sizeof(mchash)); 3131 3132 if_maddr_rlock(ifp); 3133 TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) { 3134 if (ifma->ifma_addr->sa_family != AF_LINK) 3135 continue; 3136 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3137 ifma->ifma_addr), ETHER_ADDR_LEN); 3138 3139 /* Just want the 6 least significant bits. */ 3140 crc &= 0x3f; 3141 3142 /* Set the corresponding bit in the hash table. */ 3143 mchash[crc >> 5] |= 1 << (crc & 0x1f); 3144 } 3145 if_maddr_runlock(ifp); 3146 3147 CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 3148 CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 3149 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3150 } 3151 3152 static void 3153 jme_stats_clear(struct jme_softc *sc) 3154 { 3155 3156 JME_LOCK_ASSERT(sc); 3157 3158 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3159 return; 3160 3161 /* Disable and clear counters. */ 3162 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3163 /* Activate hw counters. */ 3164 CSR_WRITE_4(sc, JME_STATCSR, 0); 3165 CSR_READ_4(sc, JME_STATCSR); 3166 bzero(&sc->jme_stats, sizeof(struct jme_hw_stats)); 3167 } 3168 3169 static void 3170 jme_stats_save(struct jme_softc *sc) 3171 { 3172 3173 JME_LOCK_ASSERT(sc); 3174 3175 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3176 return; 3177 /* Save current counters. */ 3178 bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats)); 3179 /* Disable and clear counters. */ 3180 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3181 } 3182 3183 static void 3184 jme_stats_update(struct jme_softc *sc) 3185 { 3186 struct jme_hw_stats *stat, *ostat; 3187 uint32_t reg; 3188 3189 JME_LOCK_ASSERT(sc); 3190 3191 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3192 return; 3193 stat = &sc->jme_stats; 3194 ostat = &sc->jme_ostats; 3195 stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD); 3196 stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD); 3197 reg = CSR_READ_4(sc, JME_STAT_CRCMII); 3198 stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >> 3199 STAT_RX_CRC_ERR_SHIFT; 3200 stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >> 3201 STAT_RX_MII_ERR_SHIFT; 3202 reg = CSR_READ_4(sc, JME_STAT_RXERR); 3203 stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >> 3204 STAT_RXERR_OFLOW_SHIFT; 3205 stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >> 3206 STAT_RXERR_MPTY_SHIFT; 3207 reg = CSR_READ_4(sc, JME_STAT_FAIL); 3208 stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT; 3209 stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT; 3210 3211 /* Account for previous counters. */ 3212 stat->rx_good_frames += ostat->rx_good_frames; 3213 stat->rx_crc_errs += ostat->rx_crc_errs; 3214 stat->rx_mii_errs += ostat->rx_mii_errs; 3215 stat->rx_fifo_oflows += ostat->rx_fifo_oflows; 3216 stat->rx_desc_empty += ostat->rx_desc_empty; 3217 stat->rx_bad_frames += ostat->rx_bad_frames; 3218 stat->tx_good_frames += ostat->tx_good_frames; 3219 stat->tx_bad_frames += ostat->tx_bad_frames; 3220 } 3221 3222 static int 3223 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3224 { 3225 int error, value; 3226 3227 if (arg1 == NULL) 3228 return (EINVAL); 3229 value = *(int *)arg1; 3230 error = sysctl_handle_int(oidp, &value, 0, req); 3231 if (error || req->newptr == NULL) 3232 return (error); 3233 if (value < low || value > high) 3234 return (EINVAL); 3235 *(int *)arg1 = value; 3236 3237 return (0); 3238 } 3239 3240 static int 3241 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS) 3242 { 3243 return (sysctl_int_range(oidp, arg1, arg2, req, 3244 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX)); 3245 } 3246 3247 static int 3248 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3249 { 3250 return (sysctl_int_range(oidp, arg1, arg2, req, 3251 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX)); 3252 } 3253 3254 static int 3255 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS) 3256 { 3257 return (sysctl_int_range(oidp, arg1, arg2, req, 3258 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX)); 3259 } 3260 3261 static int 3262 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3263 { 3264 return (sysctl_int_range(oidp, arg1, arg2, req, 3265 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX)); 3266 } 3267 3268 static int 3269 sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS) 3270 { 3271 return (sysctl_int_range(oidp, arg1, arg2, req, 3272 JME_PROC_MIN, JME_PROC_MAX)); 3273 } 3274