1 /*- 2 * Copyright (C) 2014 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of Intel Corporation nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/errno.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/module.h> 38 #include <sys/priority.h> 39 #include <sys/proc.h> 40 #include <sys/syslog.h> 41 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <machine/resource.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/smbus/smbconf.h> 49 50 #include "smbus_if.h" 51 52 #define ISMT_DESC_ENTRIES 32 53 54 /* Hardware Descriptor Constants - Control Field */ 55 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ 56 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ 57 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ 58 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ 59 #define ISMT_DESC_I2C 0x20 /* I2C Enable */ 60 #define ISMT_DESC_INT 0x40 /* Interrupt */ 61 #define ISMT_DESC_SOE 0x80 /* Stop On Error */ 62 63 /* Hardware Descriptor Constants - Status Field */ 64 #define ISMT_DESC_SCS 0x01 /* Success */ 65 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ 66 #define ISMT_DESC_NAK 0x08 /* NAK Received */ 67 #define ISMT_DESC_CRC 0x10 /* CRC Error */ 68 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ 69 #define ISMT_DESC_COL 0x40 /* Collisions */ 70 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ 71 72 /* Macros */ 73 #define ISMT_DESC_ADDR_RW(addr, is_read) ((addr) | (is_read)) 74 75 /* iSMT General Register address offsets (SMBBAR + <addr>) */ 76 #define ISMT_GR_GCTRL 0x000 /* General Control */ 77 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ 78 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ 79 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ 80 #define ISMT_GR_ERRSTS 0x018 /* Error Status */ 81 #define ISMT_GR_ERRINFO 0x01c /* Error Information */ 82 83 /* iSMT Master Registers */ 84 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ 85 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ 86 #define ISMT_MSTR_MSTS 0x10c /* Master Status */ 87 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ 88 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ 89 90 /* iSMT Miscellaneous Registers */ 91 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ 92 93 /* General Control Register (GCTRL) bit definitions */ 94 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ 95 #define ISMT_GCTRL_KILL 0x08 /* Kill */ 96 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ 97 98 /* Master Control Register (MCTRL) bit definitions */ 99 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ 100 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ 101 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ 102 103 /* Master Status Register (MSTS) bit definitions */ 104 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ 105 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ 106 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ 107 #define ISMT_MSTS_IP 0x01 /* In Progress */ 108 109 /* Master Descriptor Size (MDS) bit definitions */ 110 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ 111 112 /* SMBus PHY Global Timing Register (SPGT) bit definitions */ 113 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ 114 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ 115 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ 116 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ 117 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ 118 119 /* MSI Control Register (MSICTL) bit definitions */ 120 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ 121 122 #define ISMT_MAX_BLOCK_SIZE 32 /* per SMBus spec */ 123 124 //#define ISMT_DEBUG device_printf 125 #ifndef ISMT_DEBUG 126 #define ISMT_DEBUG(...) 127 #endif 128 129 /* iSMT Hardware Descriptor */ 130 struct ismt_desc { 131 uint8_t tgtaddr_rw; /* target address & r/w bit */ 132 uint8_t wr_len_cmd; /* write length in bytes or a command */ 133 uint8_t rd_len; /* read length */ 134 uint8_t control; /* control bits */ 135 uint8_t status; /* status bits */ 136 uint8_t retry; /* collision retry and retry count */ 137 uint8_t rxbytes; /* received bytes */ 138 uint8_t txbytes; /* transmitted bytes */ 139 uint32_t dptr_low; /* lower 32 bit of the data pointer */ 140 uint32_t dptr_high; /* upper 32 bit of the data pointer */ 141 } __packed; 142 143 #define DESC_SIZE (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)) 144 145 #define DMA_BUFFER_SIZE 64 146 147 struct ismt_softc { 148 device_t pcidev; 149 device_t smbdev; 150 151 struct thread *bus_reserved; 152 153 int intr_rid; 154 struct resource *intr_res; 155 void *intr_handle; 156 157 bus_space_tag_t mmio_tag; 158 bus_space_handle_t mmio_handle; 159 int mmio_rid; 160 struct resource *mmio_res; 161 162 uint8_t head; 163 164 struct ismt_desc *desc; 165 bus_dma_tag_t desc_dma_tag; 166 bus_dmamap_t desc_dma_map; 167 uint64_t desc_bus_addr; 168 169 uint8_t *dma_buffer; 170 bus_dma_tag_t dma_buffer_dma_tag; 171 bus_dmamap_t dma_buffer_dma_map; 172 uint64_t dma_buffer_bus_addr; 173 174 uint8_t using_msi; 175 }; 176 177 static void 178 ismt_intr(void *arg) 179 { 180 struct ismt_softc *sc = arg; 181 uint32_t val; 182 183 val = bus_read_4(sc->mmio_res, ISMT_MSTR_MSTS); 184 ISMT_DEBUG(sc->pcidev, "%s MSTS=0x%x\n", __func__, val); 185 186 val |= (ISMT_MSTS_MIS | ISMT_MSTS_MEIS); 187 bus_write_4(sc->mmio_res, ISMT_MSTR_MSTS, val); 188 189 wakeup(sc); 190 } 191 192 static int 193 ismt_callback(device_t dev, int index, void *data) 194 { 195 struct ismt_softc *sc; 196 int acquired, err; 197 198 sc = device_get_softc(dev); 199 200 switch (index) { 201 case SMB_REQUEST_BUS: 202 acquired = atomic_cmpset_ptr( 203 (uintptr_t *)&sc->bus_reserved, 204 (uintptr_t)NULL, (uintptr_t)curthread); 205 ISMT_DEBUG(dev, "SMB_REQUEST_BUS acquired=%d\n", acquired); 206 if (acquired) 207 err = 0; 208 else 209 err = EWOULDBLOCK; 210 break; 211 case SMB_RELEASE_BUS: 212 KASSERT(sc->bus_reserved == curthread, 213 ("SMB_RELEASE_BUS called by wrong thread\n")); 214 ISMT_DEBUG(dev, "SMB_RELEASE_BUS\n"); 215 atomic_store_rel_ptr((uintptr_t *)&sc->bus_reserved, 216 (uintptr_t)NULL); 217 err = 0; 218 break; 219 default: 220 err = SMB_EABORT; 221 break; 222 } 223 224 return (err); 225 } 226 227 static struct ismt_desc * 228 ismt_alloc_desc(struct ismt_softc *sc) 229 { 230 struct ismt_desc *desc; 231 232 KASSERT(sc->bus_reserved == curthread, 233 ("curthread %p did not request bus (%p has reserved)\n", 234 curthread, sc->bus_reserved)); 235 236 desc = &sc->desc[sc->head++]; 237 if (sc->head == ISMT_DESC_ENTRIES) 238 sc->head = 0; 239 240 memset(desc, 0, sizeof(*desc)); 241 242 return (desc); 243 } 244 245 static int 246 ismt_submit(struct ismt_softc *sc, struct ismt_desc *desc, uint8_t slave, 247 uint8_t is_read) 248 { 249 uint32_t err, fmhp, val; 250 251 desc->control |= ISMT_DESC_FAIR; 252 if (sc->using_msi) 253 desc->control |= ISMT_DESC_INT; 254 255 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(slave, is_read); 256 desc->dptr_low = (sc->dma_buffer_bus_addr & 0xFFFFFFFFLL); 257 desc->dptr_high = (sc->dma_buffer_bus_addr >> 32); 258 259 wmb(); 260 261 fmhp = sc->head << 16; 262 val = bus_read_4(sc->mmio_res, ISMT_MSTR_MCTRL); 263 val &= ~ISMT_MCTRL_FMHP; 264 val |= fmhp; 265 bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, val); 266 267 /* set the start bit */ 268 val = bus_read_4(sc->mmio_res, ISMT_MSTR_MCTRL); 269 val |= ISMT_MCTRL_SS; 270 bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, val); 271 272 err = tsleep(sc, PWAIT, "ismt_wait", 5 * hz); 273 274 if (err != 0) { 275 ISMT_DEBUG(sc->pcidev, "%s timeout\n", __func__); 276 return (SMB_ETIMEOUT); 277 } 278 279 ISMT_DEBUG(sc->pcidev, "%s status=0x%x\n", __func__, desc->status); 280 281 if (desc->status & ISMT_DESC_SCS) 282 return (SMB_ENOERR); 283 284 if (desc->status & ISMT_DESC_NAK) 285 return (SMB_ENOACK); 286 287 if (desc->status & ISMT_DESC_CRC) 288 return (SMB_EBUSERR); 289 290 if (desc->status & ISMT_DESC_COL) 291 return (SMB_ECOLLI); 292 293 if (desc->status & ISMT_DESC_LPR) 294 return (SMB_EINVAL); 295 296 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) 297 return (SMB_ETIMEOUT); 298 299 return (SMB_EBUSERR); 300 } 301 302 303 static int 304 ismt_quick(device_t dev, u_char slave, int how) 305 { 306 struct ismt_desc *desc; 307 struct ismt_softc *sc; 308 int is_read; 309 310 ISMT_DEBUG(dev, "%s\n", __func__); 311 312 if (how != SMB_QREAD && how != SMB_QWRITE) { 313 return (SMB_ENOTSUPP); 314 } 315 316 sc = device_get_softc(dev); 317 desc = ismt_alloc_desc(sc); 318 is_read = (how == SMB_QREAD ? 1 : 0); 319 return (ismt_submit(sc, desc, slave, is_read)); 320 } 321 322 static int 323 ismt_sendb(device_t dev, u_char slave, char byte) 324 { 325 struct ismt_desc *desc; 326 struct ismt_softc *sc; 327 328 ISMT_DEBUG(dev, "%s\n", __func__); 329 330 sc = device_get_softc(dev); 331 desc = ismt_alloc_desc(sc); 332 desc->control = ISMT_DESC_CWRL; 333 desc->wr_len_cmd = byte; 334 335 return (ismt_submit(sc, desc, slave, 0)); 336 } 337 338 static int 339 ismt_recvb(device_t dev, u_char slave, char *byte) 340 { 341 struct ismt_desc *desc; 342 struct ismt_softc *sc; 343 int err; 344 345 ISMT_DEBUG(dev, "%s\n", __func__); 346 347 sc = device_get_softc(dev); 348 desc = ismt_alloc_desc(sc); 349 desc->rd_len = 1; 350 351 err = ismt_submit(sc, desc, slave, 1); 352 353 if (err != SMB_ENOERR) 354 return (err); 355 356 *byte = sc->dma_buffer[0]; 357 358 return (err); 359 } 360 361 static int 362 ismt_writeb(device_t dev, u_char slave, char cmd, char byte) 363 { 364 struct ismt_desc *desc; 365 struct ismt_softc *sc; 366 367 ISMT_DEBUG(dev, "%s\n", __func__); 368 369 sc = device_get_softc(dev); 370 desc = ismt_alloc_desc(sc); 371 desc->wr_len_cmd = 2; 372 sc->dma_buffer[0] = cmd; 373 sc->dma_buffer[1] = byte; 374 375 return (ismt_submit(sc, desc, slave, 0)); 376 } 377 378 static int 379 ismt_writew(device_t dev, u_char slave, char cmd, short word) 380 { 381 struct ismt_desc *desc; 382 struct ismt_softc *sc; 383 384 ISMT_DEBUG(dev, "%s\n", __func__); 385 386 sc = device_get_softc(dev); 387 desc = ismt_alloc_desc(sc); 388 desc->wr_len_cmd = 3; 389 sc->dma_buffer[0] = cmd; 390 sc->dma_buffer[1] = word & 0xFF; 391 sc->dma_buffer[2] = word >> 8; 392 393 return (ismt_submit(sc, desc, slave, 0)); 394 } 395 396 static int 397 ismt_readb(device_t dev, u_char slave, char cmd, char *byte) 398 { 399 struct ismt_desc *desc; 400 struct ismt_softc *sc; 401 int err; 402 403 ISMT_DEBUG(dev, "%s\n", __func__); 404 405 sc = device_get_softc(dev); 406 desc = ismt_alloc_desc(sc); 407 desc->control = ISMT_DESC_CWRL; 408 desc->wr_len_cmd = cmd; 409 desc->rd_len = 1; 410 411 err = ismt_submit(sc, desc, slave, 1); 412 413 if (err != SMB_ENOERR) 414 return (err); 415 416 *byte = sc->dma_buffer[0]; 417 418 return (err); 419 } 420 421 static int 422 ismt_readw(device_t dev, u_char slave, char cmd, short *word) 423 { 424 struct ismt_desc *desc; 425 struct ismt_softc *sc; 426 int err; 427 428 ISMT_DEBUG(dev, "%s\n", __func__); 429 430 sc = device_get_softc(dev); 431 desc = ismt_alloc_desc(sc); 432 desc->control = ISMT_DESC_CWRL; 433 desc->wr_len_cmd = cmd; 434 desc->rd_len = 2; 435 436 err = ismt_submit(sc, desc, slave, 1); 437 438 if (err != SMB_ENOERR) 439 return (err); 440 441 *word = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8); 442 443 return (err); 444 } 445 446 static int 447 ismt_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata) 448 { 449 struct ismt_desc *desc; 450 struct ismt_softc *sc; 451 int err; 452 453 ISMT_DEBUG(dev, "%s\n", __func__); 454 455 sc = device_get_softc(dev); 456 desc = ismt_alloc_desc(sc); 457 desc->wr_len_cmd = 3; 458 desc->rd_len = 2; 459 sc->dma_buffer[0] = cmd; 460 sc->dma_buffer[1] = sdata & 0xff; 461 sc->dma_buffer[2] = sdata >> 8; 462 463 err = ismt_submit(sc, desc, slave, 0); 464 465 if (err != SMB_ENOERR) 466 return (err); 467 468 *rdata = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8); 469 470 return (err); 471 } 472 473 static int 474 ismt_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf) 475 { 476 struct ismt_desc *desc; 477 struct ismt_softc *sc; 478 479 ISMT_DEBUG(dev, "%s\n", __func__); 480 481 if (count == 0 || count > ISMT_MAX_BLOCK_SIZE) 482 return (SMB_EINVAL); 483 484 sc = device_get_softc(dev); 485 desc = ismt_alloc_desc(sc); 486 desc->control = ISMT_DESC_I2C; 487 desc->wr_len_cmd = count + 1; 488 sc->dma_buffer[0] = cmd; 489 memcpy(&sc->dma_buffer[1], buf, count); 490 491 return (ismt_submit(sc, desc, slave, 0)); 492 } 493 494 static int 495 ismt_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf) 496 { 497 struct ismt_desc *desc; 498 struct ismt_softc *sc; 499 int err; 500 501 ISMT_DEBUG(dev, "%s\n", __func__); 502 503 if (*count == 0 || *count > ISMT_MAX_BLOCK_SIZE) 504 return (SMB_EINVAL); 505 506 sc = device_get_softc(dev); 507 desc = ismt_alloc_desc(sc); 508 desc->control = ISMT_DESC_I2C | ISMT_DESC_CWRL; 509 desc->wr_len_cmd = cmd; 510 desc->rd_len = *count; 511 512 err = ismt_submit(sc, desc, slave, 0); 513 514 if (err != SMB_ENOERR) 515 return (err); 516 517 memcpy(buf, sc->dma_buffer, desc->rxbytes); 518 *count = desc->rxbytes; 519 520 return (err); 521 } 522 523 static int 524 ismt_detach(device_t dev) 525 { 526 struct ismt_softc *sc; 527 int error; 528 529 ISMT_DEBUG(dev, "%s\n", __func__); 530 sc = device_get_softc(dev); 531 532 error = bus_generic_detach(dev); 533 if (error) 534 return (error); 535 536 device_delete_child(dev, sc->smbdev); 537 538 if (sc->intr_handle != NULL) { 539 bus_teardown_intr(dev, sc->intr_res, sc->intr_handle); 540 sc->intr_handle = NULL; 541 } 542 if (sc->intr_res != NULL) { 543 bus_release_resource(dev, 544 SYS_RES_IRQ, sc->intr_rid, sc->intr_res); 545 sc->intr_res = NULL; 546 } 547 if (sc->using_msi == 1) 548 pci_release_msi(dev); 549 550 if (sc->mmio_res != NULL) { 551 bus_release_resource(dev, 552 SYS_RES_MEMORY, sc->mmio_rid, sc->mmio_res); 553 sc->mmio_res = NULL; 554 } 555 556 bus_dmamap_unload(sc->desc_dma_tag, sc->desc_dma_map); 557 bus_dmamap_unload(sc->dma_buffer_dma_tag, sc->dma_buffer_dma_map); 558 559 bus_dmamem_free(sc->desc_dma_tag, sc->desc, 560 sc->desc_dma_map); 561 bus_dmamem_free(sc->dma_buffer_dma_tag, sc->dma_buffer, 562 sc->dma_buffer_dma_map); 563 564 bus_dma_tag_destroy(sc->desc_dma_tag); 565 bus_dma_tag_destroy(sc->dma_buffer_dma_tag); 566 567 pci_disable_busmaster(dev); 568 569 return 0; 570 } 571 572 static void 573 ismt_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 574 { 575 uint64_t *bus_addr = (uint64_t *)arg; 576 577 KASSERT(error == 0, ("%s: error=%d\n", __func__, error)); 578 KASSERT(nseg == 1, ("%s: nseg=%d\n", __func__, nseg)); 579 580 *bus_addr = seg[0].ds_addr; 581 } 582 583 static int 584 ismt_attach(device_t dev) 585 { 586 struct ismt_softc *sc = device_get_softc(dev); 587 int err, num_vectors, val; 588 589 sc->pcidev = dev; 590 pci_enable_busmaster(dev); 591 592 if ((sc->smbdev = device_add_child(dev, "smbus", -1)) == NULL) { 593 device_printf(dev, "no smbus child found\n"); 594 err = ENXIO; 595 goto fail; 596 } 597 598 sc->mmio_rid = PCIR_BAR(0); 599 sc->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 600 &sc->mmio_rid, RF_ACTIVE); 601 if (sc->mmio_res == NULL) { 602 device_printf(dev, "cannot allocate mmio region\n"); 603 err = ENOMEM; 604 goto fail; 605 } 606 607 sc->mmio_tag = rman_get_bustag(sc->mmio_res); 608 sc->mmio_handle = rman_get_bushandle(sc->mmio_res); 609 610 /* Attach "smbus" child */ 611 if ((err = bus_generic_attach(dev)) != 0) { 612 device_printf(dev, "failed to attach child: %d\n", err); 613 err = ENXIO; 614 goto fail; 615 } 616 617 bus_dma_tag_create(bus_get_dma_tag(dev), 4, PAGE_SIZE, 618 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 619 DESC_SIZE, 1, DESC_SIZE, 620 0, NULL, NULL, &sc->desc_dma_tag); 621 622 bus_dma_tag_create(bus_get_dma_tag(dev), 4, PAGE_SIZE, 623 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 624 DMA_BUFFER_SIZE, 1, DMA_BUFFER_SIZE, 625 0, NULL, NULL, &sc->dma_buffer_dma_tag); 626 627 bus_dmamap_create(sc->desc_dma_tag, 0, 628 &sc->desc_dma_map); 629 bus_dmamap_create(sc->dma_buffer_dma_tag, 0, 630 &sc->dma_buffer_dma_map); 631 632 bus_dmamem_alloc(sc->desc_dma_tag, 633 (void **)&sc->desc, BUS_DMA_WAITOK, 634 &sc->desc_dma_map); 635 bus_dmamem_alloc(sc->dma_buffer_dma_tag, 636 (void **)&sc->dma_buffer, BUS_DMA_WAITOK, 637 &sc->dma_buffer_dma_map); 638 639 bus_dmamap_load(sc->desc_dma_tag, 640 sc->desc_dma_map, sc->desc, DESC_SIZE, 641 ismt_single_map, &sc->desc_bus_addr, 0); 642 bus_dmamap_load(sc->dma_buffer_dma_tag, 643 sc->dma_buffer_dma_map, sc->dma_buffer, DMA_BUFFER_SIZE, 644 ismt_single_map, &sc->dma_buffer_bus_addr, 0); 645 646 bus_write_4(sc->mmio_res, ISMT_MSTR_MDBA, 647 (sc->desc_bus_addr & 0xFFFFFFFFLL)); 648 bus_write_4(sc->mmio_res, ISMT_MSTR_MDBA + 4, 649 (sc->desc_bus_addr >> 32)); 650 651 /* initialize the Master Control Register (MCTRL) */ 652 bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, ISMT_MCTRL_MEIE); 653 654 /* initialize the Master Status Register (MSTS) */ 655 bus_write_4(sc->mmio_res, ISMT_MSTR_MSTS, 0); 656 657 /* initialize the Master Descriptor Size (MDS) */ 658 val = bus_read_4(sc->mmio_res, ISMT_MSTR_MDS); 659 val &= ~ISMT_MDS_MASK; 660 val |= (ISMT_DESC_ENTRIES - 1); 661 bus_write_4(sc->mmio_res, ISMT_MSTR_MDS, val); 662 663 sc->using_msi = 1; 664 665 if (pci_msi_count(dev) == 0) { 666 sc->using_msi = 0; 667 goto intx; 668 } 669 670 num_vectors = 1; 671 if (pci_alloc_msi(dev, &num_vectors) != 0) { 672 sc->using_msi = 0; 673 goto intx; 674 } 675 676 sc->intr_rid = 1; 677 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 678 &sc->intr_rid, RF_ACTIVE); 679 680 if (sc->intr_res == NULL) { 681 sc->using_msi = 0; 682 pci_release_msi(dev); 683 } 684 685 intx: 686 if (sc->using_msi == 0) { 687 sc->intr_rid = 0; 688 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 689 &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); 690 if (sc->intr_res == NULL) { 691 device_printf(dev, "cannot allocate irq\n"); 692 err = ENXIO; 693 goto fail; 694 } 695 } 696 697 ISMT_DEBUG(dev, "using_msi = %d\n", sc->using_msi); 698 699 err = bus_setup_intr(dev, sc->intr_res, 700 INTR_TYPE_MISC | INTR_MPSAFE, NULL, ismt_intr, sc, 701 &sc->intr_handle); 702 if (err != 0) { 703 device_printf(dev, "cannot setup interrupt\n"); 704 err = ENXIO; 705 goto fail; 706 } 707 708 return (0); 709 710 fail: 711 ismt_detach(dev); 712 return (err); 713 } 714 715 #define ID_INTEL_S1200_SMT0 0x0c598086 716 #define ID_INTEL_S1200_SMT1 0x0c5a8086 717 #define ID_INTEL_C2000_SMT 0x1f158086 718 #define ID_INTEL_C3000_SMT 0x19ac8086 719 720 static int 721 ismt_probe(device_t dev) 722 { 723 const char *desc; 724 725 switch (pci_get_devid(dev)) { 726 case ID_INTEL_S1200_SMT0: 727 desc = "Atom Processor S1200 SMBus 2.0 Controller 0"; 728 break; 729 case ID_INTEL_S1200_SMT1: 730 desc = "Atom Processor S1200 SMBus 2.0 Controller 1"; 731 break; 732 case ID_INTEL_C2000_SMT: 733 desc = "Atom Processor C2000 SMBus 2.0"; 734 break; 735 case ID_INTEL_C3000_SMT: 736 desc = "Atom Processor C3000 SMBus 2.0"; 737 break; 738 default: 739 return (ENXIO); 740 } 741 742 device_set_desc(dev, desc); 743 return (BUS_PROBE_DEFAULT); 744 } 745 746 /* Device methods */ 747 static device_method_t ismt_pci_methods[] = { 748 DEVMETHOD(device_probe, ismt_probe), 749 DEVMETHOD(device_attach, ismt_attach), 750 DEVMETHOD(device_detach, ismt_detach), 751 752 DEVMETHOD(smbus_callback, ismt_callback), 753 DEVMETHOD(smbus_quick, ismt_quick), 754 DEVMETHOD(smbus_sendb, ismt_sendb), 755 DEVMETHOD(smbus_recvb, ismt_recvb), 756 DEVMETHOD(smbus_writeb, ismt_writeb), 757 DEVMETHOD(smbus_writew, ismt_writew), 758 DEVMETHOD(smbus_readb, ismt_readb), 759 DEVMETHOD(smbus_readw, ismt_readw), 760 DEVMETHOD(smbus_pcall, ismt_pcall), 761 DEVMETHOD(smbus_bwrite, ismt_bwrite), 762 DEVMETHOD(smbus_bread, ismt_bread), 763 764 DEVMETHOD_END 765 }; 766 767 static driver_t ismt_pci_driver = { 768 "ismt", 769 ismt_pci_methods, 770 sizeof(struct ismt_softc) 771 }; 772 773 DRIVER_MODULE(ismt, pci, ismt_pci_driver, 0, 0); 774 DRIVER_MODULE(smbus, ismt, smbus_driver, 0, 0); 775 776 MODULE_DEPEND(ismt, pci, 1, 1, 1); 777 MODULE_DEPEND(ismt, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); 778 MODULE_VERSION(ismt, 1); 779