1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2023 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef IRDMA_USER_H 36 #define IRDMA_USER_H 37 38 #define irdma_handle void * 39 #define irdma_adapter_handle irdma_handle 40 #define irdma_qp_handle irdma_handle 41 #define irdma_cq_handle irdma_handle 42 #define irdma_pd_id irdma_handle 43 #define irdma_stag_handle irdma_handle 44 #define irdma_stag_index u32 45 #define irdma_stag u32 46 #define irdma_stag_key u8 47 #define irdma_tagged_offset u64 48 #define irdma_access_privileges u32 49 #define irdma_physical_fragment u64 50 #define irdma_address_list u64 * 51 #define irdma_sgl struct irdma_sge * 52 53 #define IRDMA_MAX_MR_SIZE 0x200000000000ULL 54 55 #define IRDMA_ACCESS_FLAGS_LOCALREAD 0x01 56 #define IRDMA_ACCESS_FLAGS_LOCALWRITE 0x02 57 #define IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY 0x04 58 #define IRDMA_ACCESS_FLAGS_REMOTEREAD 0x05 59 #define IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY 0x08 60 #define IRDMA_ACCESS_FLAGS_REMOTEWRITE 0x0a 61 #define IRDMA_ACCESS_FLAGS_BIND_WINDOW 0x10 62 #define IRDMA_ACCESS_FLAGS_ZERO_BASED 0x20 63 #define IRDMA_ACCESS_FLAGS_ALL 0x3f 64 65 #define IRDMA_OP_TYPE_RDMA_WRITE 0x00 66 #define IRDMA_OP_TYPE_RDMA_READ 0x01 67 #define IRDMA_OP_TYPE_SEND 0x03 68 #define IRDMA_OP_TYPE_SEND_INV 0x04 69 #define IRDMA_OP_TYPE_SEND_SOL 0x05 70 #define IRDMA_OP_TYPE_SEND_SOL_INV 0x06 71 #define IRDMA_OP_TYPE_RDMA_WRITE_SOL 0x0d 72 #define IRDMA_OP_TYPE_BIND_MW 0x08 73 #define IRDMA_OP_TYPE_FAST_REG_NSMR 0x09 74 #define IRDMA_OP_TYPE_INV_STAG 0x0a 75 #define IRDMA_OP_TYPE_RDMA_READ_INV_STAG 0x0b 76 #define IRDMA_OP_TYPE_NOP 0x0c 77 #define IRDMA_OP_TYPE_REC 0x3e 78 #define IRDMA_OP_TYPE_REC_IMM 0x3f 79 80 #define IRDMA_FLUSH_MAJOR_ERR 1 81 #define IRDMA_SRQFLUSH_RSVD_MAJOR_ERR 0xfffe 82 83 /* Async Events codes */ 84 #define IRDMA_AE_AMP_UNALLOCATED_STAG 0x0102 85 #define IRDMA_AE_AMP_INVALID_STAG 0x0103 86 #define IRDMA_AE_AMP_BAD_QP 0x0104 87 #define IRDMA_AE_AMP_BAD_PD 0x0105 88 #define IRDMA_AE_AMP_BAD_STAG_KEY 0x0106 89 #define IRDMA_AE_AMP_BAD_STAG_INDEX 0x0107 90 #define IRDMA_AE_AMP_BOUNDS_VIOLATION 0x0108 91 #define IRDMA_AE_AMP_RIGHTS_VIOLATION 0x0109 92 #define IRDMA_AE_AMP_TO_WRAP 0x010a 93 #define IRDMA_AE_AMP_FASTREG_VALID_STAG 0x010c 94 #define IRDMA_AE_AMP_FASTREG_MW_STAG 0x010d 95 #define IRDMA_AE_AMP_FASTREG_INVALID_RIGHTS 0x010e 96 #define IRDMA_AE_AMP_FASTREG_INVALID_LENGTH 0x0110 97 #define IRDMA_AE_AMP_INVALIDATE_SHARED 0x0111 98 #define IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS 0x0112 99 #define IRDMA_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS 0x0113 100 #define IRDMA_AE_AMP_MWBIND_VALID_STAG 0x0114 101 #define IRDMA_AE_AMP_MWBIND_OF_MR_STAG 0x0115 102 #define IRDMA_AE_AMP_MWBIND_TO_ZERO_BASED_STAG 0x0116 103 #define IRDMA_AE_AMP_MWBIND_TO_MW_STAG 0x0117 104 #define IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS 0x0118 105 #define IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119 106 #define IRDMA_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a 107 #define IRDMA_AE_AMP_MWBIND_BIND_DISABLED 0x011b 108 #define IRDMA_AE_PRIV_OPERATION_DENIED 0x011c 109 #define IRDMA_AE_AMP_INVALIDATE_TYPE1_MW 0x011d 110 #define IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW 0x011e 111 #define IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG 0x011f 112 #define IRDMA_AE_AMP_MWBIND_WRONG_TYPE 0x0120 113 #define IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH 0x0121 114 #define IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0132 115 #define IRDMA_AE_UDA_XMIT_BAD_PD 0x0133 116 #define IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT 0x0134 117 #define IRDMA_AE_UDA_L4LEN_INVALID 0x0135 118 #define IRDMA_AE_BAD_CLOSE 0x0201 119 #define IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202 120 #define IRDMA_AE_CQ_OPERATION_ERROR 0x0203 121 #define IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205 122 #define IRDMA_AE_STAG_ZERO_INVALID 0x0206 123 #define IRDMA_AE_IB_RREQ_AND_Q1_FULL 0x0207 124 #define IRDMA_AE_IB_INVALID_REQUEST 0x0208 125 #define IRDMA_AE_WQE_UNEXPECTED_OPCODE 0x020a 126 #define IRDMA_AE_WQE_INVALID_PARAMETER 0x020b 127 #define IRDMA_AE_WQE_INVALID_FRAG_DATA 0x020c 128 #define IRDMA_AE_IB_REMOTE_ACCESS_ERROR 0x020d 129 #define IRDMA_AE_IB_REMOTE_OP_ERROR 0x020e 130 #define IRDMA_AE_WQE_LSMM_TOO_LONG 0x0220 131 #define IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301 132 #define IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303 133 #define IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304 134 #define IRDMA_AE_DDP_UBE_INVALID_MO 0x0305 135 #define IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE 0x0306 136 #define IRDMA_AE_DDP_UBE_INVALID_QN 0x0307 137 #define IRDMA_AE_DDP_NO_L_BIT 0x0308 138 #define IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION 0x0311 139 #define IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE 0x0312 140 #define IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST 0x0313 141 #define IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP 0x0314 142 #define IRDMA_AE_ROCE_RSP_LENGTH_ERROR 0x0316 143 #define IRDMA_AE_ROCE_EMPTY_MCG 0x0380 144 #define IRDMA_AE_ROCE_BAD_MC_IP_ADDR 0x0381 145 #define IRDMA_AE_ROCE_BAD_MC_QPID 0x0382 146 #define IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH 0x0383 147 #define IRDMA_AE_INVALID_ARP_ENTRY 0x0401 148 #define IRDMA_AE_INVALID_TCP_OPTION_RCVD 0x0402 149 #define IRDMA_AE_STALE_ARP_ENTRY 0x0403 150 #define IRDMA_AE_INVALID_AH_ENTRY 0x0406 151 #define IRDMA_AE_LLP_CLOSE_COMPLETE 0x0501 152 #define IRDMA_AE_LLP_CONNECTION_RESET 0x0502 153 #define IRDMA_AE_LLP_FIN_RECEIVED 0x0503 154 #define IRDMA_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH 0x0504 155 #define IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505 156 #define IRDMA_AE_LLP_SEGMENT_TOO_SMALL 0x0507 157 #define IRDMA_AE_LLP_SYN_RECEIVED 0x0508 158 #define IRDMA_AE_LLP_TERMINATE_RECEIVED 0x0509 159 #define IRDMA_AE_LLP_TOO_MANY_RETRIES 0x050a 160 #define IRDMA_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES 0x050b 161 #define IRDMA_AE_LLP_DOUBT_REACHABILITY 0x050c 162 #define IRDMA_AE_LLP_CONNECTION_ESTABLISHED 0x050e 163 #define IRDMA_AE_RESOURCE_EXHAUSTION 0x0520 164 #define IRDMA_AE_RESET_SENT 0x0601 165 #define IRDMA_AE_TERMINATE_SENT 0x0602 166 #define IRDMA_AE_RESET_NOT_SENT 0x0603 167 #define IRDMA_AE_LCE_QP_CATASTROPHIC 0x0700 168 #define IRDMA_AE_LCE_FUNCTION_CATASTROPHIC 0x0701 169 #define IRDMA_AE_LCE_CQ_CATASTROPHIC 0x0702 170 #define IRDMA_AE_QP_SUSPEND_COMPLETE 0x0900 171 172 enum irdma_device_caps_const { 173 IRDMA_WQE_SIZE = 4, 174 IRDMA_CQP_WQE_SIZE = 8, 175 IRDMA_CQE_SIZE = 4, 176 IRDMA_EXTENDED_CQE_SIZE = 8, 177 IRDMA_AEQE_SIZE = 2, 178 IRDMA_CEQE_SIZE = 1, 179 IRDMA_CQP_CTX_SIZE = 8, 180 IRDMA_SHADOW_AREA_SIZE = 8, 181 IRDMA_GATHER_STATS_BUF_SIZE = 1024, 182 IRDMA_MIN_IW_QP_ID = 0, 183 IRDMA_QUERY_FPM_BUF_SIZE = 176, 184 IRDMA_COMMIT_FPM_BUF_SIZE = 176, 185 IRDMA_MAX_IW_QP_ID = 262143, 186 IRDMA_MIN_CEQID = 0, 187 IRDMA_MAX_CEQID = 1023, 188 IRDMA_CEQ_MAX_COUNT = IRDMA_MAX_CEQID + 1, 189 IRDMA_MIN_CQID = 0, 190 IRDMA_MAX_CQID = 524287, 191 IRDMA_MIN_AEQ_ENTRIES = 1, 192 IRDMA_MAX_AEQ_ENTRIES = 524287, 193 IRDMA_MIN_CEQ_ENTRIES = 1, 194 IRDMA_MAX_CEQ_ENTRIES = 262143, 195 IRDMA_MIN_CQ_SIZE = 1, 196 IRDMA_MAX_CQ_SIZE = 1048575, 197 IRDMA_DB_ID_ZERO = 0, 198 /* 64K + 1 */ 199 IRDMA_MAX_OUTBOUND_MSG_SIZE = 65537, 200 /* 64K +1 */ 201 IRDMA_MAX_INBOUND_MSG_SIZE = 65537, 202 IRDMA_MAX_PUSH_PAGE_COUNT = 1024, 203 IRDMA_MAX_PE_ENA_VF_COUNT = 32, 204 IRDMA_MAX_VF_FPM_ID = 47, 205 IRDMA_MAX_SQ_PAYLOAD_SIZE = 2145386496, 206 IRDMA_MAX_INLINE_DATA_SIZE = 101, 207 IRDMA_MAX_WQ_ENTRIES = 32768, 208 IRDMA_Q2_BUF_SIZE = 256, 209 IRDMA_QP_CTX_SIZE = 256, 210 IRDMA_MAX_PDS = 262144, 211 }; 212 213 enum irdma_addressing_type { 214 IRDMA_ADDR_TYPE_ZERO_BASED = 0, 215 IRDMA_ADDR_TYPE_VA_BASED = 1, 216 }; 217 218 enum irdma_flush_opcode { 219 FLUSH_INVALID = 0, 220 FLUSH_GENERAL_ERR, 221 FLUSH_PROT_ERR, 222 FLUSH_REM_ACCESS_ERR, 223 FLUSH_LOC_QP_OP_ERR, 224 FLUSH_REM_OP_ERR, 225 FLUSH_LOC_LEN_ERR, 226 FLUSH_FATAL_ERR, 227 FLUSH_RETRY_EXC_ERR, 228 FLUSH_MW_BIND_ERR, 229 FLUSH_REM_INV_REQ_ERR, 230 }; 231 232 enum irdma_qp_event_type { 233 IRDMA_QP_EVENT_CATASTROPHIC, 234 IRDMA_QP_EVENT_ACCESS_ERR, 235 IRDMA_QP_EVENT_REQ_ERR, 236 }; 237 238 enum irdma_cmpl_status { 239 IRDMA_COMPL_STATUS_SUCCESS = 0, 240 IRDMA_COMPL_STATUS_FLUSHED, 241 IRDMA_COMPL_STATUS_INVALID_WQE, 242 IRDMA_COMPL_STATUS_QP_CATASTROPHIC, 243 IRDMA_COMPL_STATUS_REMOTE_TERMINATION, 244 IRDMA_COMPL_STATUS_INVALID_STAG, 245 IRDMA_COMPL_STATUS_BASE_BOUND_VIOLATION, 246 IRDMA_COMPL_STATUS_ACCESS_VIOLATION, 247 IRDMA_COMPL_STATUS_INVALID_PD_ID, 248 IRDMA_COMPL_STATUS_WRAP_ERROR, 249 IRDMA_COMPL_STATUS_STAG_INVALID_PDID, 250 IRDMA_COMPL_STATUS_RDMA_READ_ZERO_ORD, 251 IRDMA_COMPL_STATUS_QP_NOT_PRIVLEDGED, 252 IRDMA_COMPL_STATUS_STAG_NOT_INVALID, 253 IRDMA_COMPL_STATUS_INVALID_PHYS_BUF_SIZE, 254 IRDMA_COMPL_STATUS_INVALID_PHYS_BUF_ENTRY, 255 IRDMA_COMPL_STATUS_INVALID_FBO, 256 IRDMA_COMPL_STATUS_INVALID_LEN, 257 IRDMA_COMPL_STATUS_INVALID_ACCESS, 258 IRDMA_COMPL_STATUS_PHYS_BUF_LIST_TOO_LONG, 259 IRDMA_COMPL_STATUS_INVALID_VIRT_ADDRESS, 260 IRDMA_COMPL_STATUS_INVALID_REGION, 261 IRDMA_COMPL_STATUS_INVALID_WINDOW, 262 IRDMA_COMPL_STATUS_INVALID_TOTAL_LEN, 263 IRDMA_COMPL_STATUS_UNKNOWN, 264 }; 265 266 enum irdma_cmpl_notify { 267 IRDMA_CQ_COMPL_EVENT = 0, 268 IRDMA_CQ_COMPL_SOLICITED = 1, 269 }; 270 271 enum irdma_qp_caps { 272 IRDMA_WRITE_WITH_IMM = 1, 273 IRDMA_SEND_WITH_IMM = 2, 274 IRDMA_ROCE = 4, 275 IRDMA_PUSH_MODE = 8, 276 }; 277 278 struct irdma_qp_uk; 279 struct irdma_cq_uk; 280 struct irdma_qp_uk_init_info; 281 struct irdma_cq_uk_init_info; 282 283 struct irdma_sge { 284 irdma_tagged_offset tag_off; 285 u32 len; 286 irdma_stag stag; 287 }; 288 289 struct irdma_ring { 290 volatile u32 head; 291 volatile u32 tail; /* effective tail */ 292 u32 size; 293 }; 294 295 struct irdma_cqe { 296 __le64 buf[IRDMA_CQE_SIZE]; 297 }; 298 299 struct irdma_extended_cqe { 300 __le64 buf[IRDMA_EXTENDED_CQE_SIZE]; 301 }; 302 303 struct irdma_post_send { 304 irdma_sgl sg_list; 305 u32 num_sges; 306 u32 qkey; 307 u32 dest_qp; 308 u32 ah_id; 309 }; 310 311 struct irdma_post_rq_info { 312 u64 wr_id; 313 irdma_sgl sg_list; 314 u32 num_sges; 315 }; 316 317 struct irdma_rdma_write { 318 irdma_sgl lo_sg_list; 319 u32 num_lo_sges; 320 struct irdma_sge rem_addr; 321 }; 322 323 struct irdma_rdma_read { 324 irdma_sgl lo_sg_list; 325 u32 num_lo_sges; 326 struct irdma_sge rem_addr; 327 }; 328 329 struct irdma_bind_window { 330 irdma_stag mr_stag; 331 u64 bind_len; 332 void *va; 333 enum irdma_addressing_type addressing_type; 334 bool ena_reads:1; 335 bool ena_writes:1; 336 irdma_stag mw_stag; 337 bool mem_window_type_1:1; 338 }; 339 340 struct irdma_inv_local_stag { 341 irdma_stag target_stag; 342 }; 343 344 struct irdma_post_sq_info { 345 u64 wr_id; 346 u8 op_type; 347 u8 l4len; 348 bool signaled:1; 349 bool read_fence:1; 350 bool local_fence:1; 351 bool inline_data:1; 352 bool imm_data_valid:1; 353 bool push_wqe:1; 354 bool report_rtt:1; 355 bool udp_hdr:1; 356 bool defer_flag:1; 357 u32 imm_data; 358 u32 stag_to_inv; 359 union { 360 struct irdma_post_send send; 361 struct irdma_rdma_write rdma_write; 362 struct irdma_rdma_read rdma_read; 363 struct irdma_bind_window bind_window; 364 struct irdma_inv_local_stag inv_local_stag; 365 } op; 366 }; 367 368 struct irdma_cq_poll_info { 369 u64 wr_id; 370 irdma_qp_handle qp_handle; 371 u32 bytes_xfered; 372 u32 qp_id; 373 u32 ud_src_qpn; 374 u32 imm_data; 375 irdma_stag inv_stag; /* or L_R_Key */ 376 enum irdma_cmpl_status comp_status; 377 u16 major_err; 378 u16 minor_err; 379 u16 ud_vlan; 380 u8 ud_smac[6]; 381 u8 op_type; 382 u8 q_type; 383 bool stag_invalid_set:1; /* or L_R_Key set */ 384 bool push_dropped:1; 385 bool error:1; 386 bool solicited_event:1; 387 bool ipv4:1; 388 bool ud_vlan_valid:1; 389 bool ud_smac_valid:1; 390 bool imm_valid:1; 391 bool signaled:1; 392 union { 393 u32 tcp_sqn; 394 u32 roce_psn; 395 u32 rtt; 396 u32 raw; 397 } stat; 398 }; 399 400 struct qp_err_code { 401 enum irdma_flush_opcode flush_code; 402 enum irdma_qp_event_type event_type; 403 }; 404 405 int irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp, 406 struct irdma_post_sq_info *info, bool post_sq); 407 int irdma_uk_inline_send(struct irdma_qp_uk *qp, 408 struct irdma_post_sq_info *info, bool post_sq); 409 int irdma_uk_post_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, 410 bool post_sq); 411 int irdma_uk_post_receive(struct irdma_qp_uk *qp, 412 struct irdma_post_rq_info *info); 413 void irdma_uk_qp_post_wr(struct irdma_qp_uk *qp); 414 int irdma_uk_rdma_read(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 415 bool inv_stag, bool post_sq); 416 int irdma_uk_rdma_write(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 417 bool post_sq); 418 int irdma_uk_send(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 419 bool post_sq); 420 int irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp, 421 struct irdma_post_sq_info *info, 422 bool post_sq); 423 424 struct irdma_wqe_uk_ops { 425 void (*iw_copy_inline_data)(u8 *dest, struct irdma_sge *sge_list, u32 num_sges, u8 polarity); 426 u16 (*iw_inline_data_size_to_quanta)(u32 data_size); 427 void (*iw_set_fragment)(__le64 *wqe, u32 offset, struct irdma_sge *sge, 428 u8 valid); 429 void (*iw_set_mw_bind_wqe)(__le64 *wqe, 430 struct irdma_bind_window *op_info); 431 }; 432 433 int irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq, 434 struct irdma_cq_poll_info *info); 435 void irdma_uk_cq_request_notification(struct irdma_cq_uk *cq, 436 enum irdma_cmpl_notify cq_notify); 437 void irdma_uk_cq_resize(struct irdma_cq_uk *cq, void *cq_base, int size); 438 void irdma_uk_cq_set_resized_cnt(struct irdma_cq_uk *qp, u16 cnt); 439 int irdma_uk_cq_init(struct irdma_cq_uk *cq, 440 struct irdma_cq_uk_init_info *info); 441 int irdma_uk_qp_init(struct irdma_qp_uk *qp, 442 struct irdma_qp_uk_init_info *info); 443 void irdma_uk_calc_shift_wq(struct irdma_qp_uk_init_info *ukinfo, u8 *sq_shift, 444 u8 *rq_shift); 445 int irdma_uk_calc_depth_shift_sq(struct irdma_qp_uk_init_info *ukinfo, 446 u32 *sq_depth, u8 *sq_shift); 447 int irdma_uk_calc_depth_shift_rq(struct irdma_qp_uk_init_info *ukinfo, 448 u32 *rq_depth, u8 *rq_shift); 449 struct irdma_sq_uk_wr_trk_info { 450 u64 wrid; 451 u32 wr_len; 452 u16 quanta; 453 u8 signaled; 454 u8 reserved[1]; 455 }; 456 457 struct irdma_qp_quanta { 458 __le64 elem[IRDMA_WQE_SIZE]; 459 }; 460 461 struct irdma_qp_uk { 462 struct irdma_qp_quanta *sq_base; 463 struct irdma_qp_quanta *rq_base; 464 struct irdma_uk_attrs *uk_attrs; 465 u32 IOMEM *wqe_alloc_db; 466 struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; 467 struct irdma_sig_wr_trk_info *sq_sigwrtrk_array; 468 u64 *rq_wrid_array; 469 __le64 *shadow_area; 470 __le32 *push_db; 471 __le64 *push_wqe; 472 struct irdma_ring sq_ring; 473 struct irdma_ring sq_sig_ring; 474 struct irdma_ring rq_ring; 475 struct irdma_ring initial_ring; 476 u32 qp_id; 477 u32 qp_caps; 478 u32 sq_size; 479 u32 rq_size; 480 u32 max_sq_frag_cnt; 481 u32 max_rq_frag_cnt; 482 u32 max_inline_data; 483 u32 last_rx_cmpl_idx; 484 u32 last_tx_cmpl_idx; 485 struct irdma_wqe_uk_ops wqe_ops; 486 u16 conn_wqes; 487 u8 qp_type; 488 u8 swqe_polarity; 489 u8 swqe_polarity_deferred; 490 u8 rwqe_polarity; 491 u8 rq_wqe_size; 492 u8 rq_wqe_size_multiplier; 493 bool deferred_flag:1; 494 bool push_mode:1; /* whether the last post wqe was pushed */ 495 bool push_dropped:1; 496 bool first_sq_wq:1; 497 bool sq_flush_complete:1; /* Indicates flush was seen and SQ was empty after the flush */ 498 bool rq_flush_complete:1; /* Indicates flush was seen and RQ was empty after the flush */ 499 bool destroy_pending:1; /* Indicates the QP is being destroyed */ 500 void *back_qp; 501 spinlock_t *lock; 502 u8 dbg_rq_flushed; 503 u16 ord_cnt; 504 u8 sq_flush_seen; 505 u8 rq_flush_seen; 506 u8 rd_fence_rate; 507 }; 508 509 struct irdma_cq_uk { 510 struct irdma_cqe *cq_base; 511 u32 IOMEM *cqe_alloc_db; 512 u32 IOMEM *cq_ack_db; 513 __le64 *shadow_area; 514 u32 cq_id; 515 u32 cq_size; 516 struct irdma_ring cq_ring; 517 u8 polarity; 518 bool avoid_mem_cflct:1; 519 }; 520 521 struct irdma_qp_uk_init_info { 522 struct irdma_qp_quanta *sq; 523 struct irdma_qp_quanta *rq; 524 struct irdma_uk_attrs *uk_attrs; 525 u32 IOMEM *wqe_alloc_db; 526 __le64 *shadow_area; 527 struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; 528 struct irdma_sig_wr_trk_info *sq_sigwrtrk_array; 529 u64 *rq_wrid_array; 530 u32 qp_id; 531 u32 qp_caps; 532 u32 sq_size; 533 u32 rq_size; 534 u32 max_sq_frag_cnt; 535 u32 max_rq_frag_cnt; 536 u32 max_inline_data; 537 u32 sq_depth; 538 u32 rq_depth; 539 u8 first_sq_wq; 540 u8 type; 541 u8 sq_shift; 542 u8 rq_shift; 543 u8 rd_fence_rate; 544 int abi_ver; 545 bool legacy_mode; 546 }; 547 548 struct irdma_cq_uk_init_info { 549 u32 IOMEM *cqe_alloc_db; 550 u32 IOMEM *cq_ack_db; 551 struct irdma_cqe *cq_base; 552 __le64 *shadow_area; 553 u32 cq_size; 554 u32 cq_id; 555 bool avoid_mem_cflct; 556 }; 557 558 __le64 *irdma_qp_get_next_send_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx, 559 u16 *quanta, u32 total_size, 560 struct irdma_post_sq_info *info); 561 __le64 *irdma_qp_get_next_recv_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx); 562 int irdma_uk_clean_cq(void *q, struct irdma_cq_uk *cq); 563 int irdma_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, bool post_sq); 564 int irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta); 565 int irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size); 566 void irdma_get_wqe_shift(struct irdma_uk_attrs *uk_attrs, u32 sge, 567 u32 inline_data, u8 *shift); 568 int irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs, u32 sq_size, u8 shift, u32 *sqdepth); 569 int irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs, u32 rq_size, u8 shift, u32 *rqdepth); 570 void irdma_qp_push_wqe(struct irdma_qp_uk *qp, __le64 *wqe, u16 quanta, 571 u32 wqe_idx, bool post_sq); 572 void irdma_clr_wqes(struct irdma_qp_uk *qp, u32 qp_wqe_idx); 573 574 static inline struct qp_err_code irdma_ae_to_qp_err_code(u16 ae_id) 575 { 576 struct qp_err_code qp_err = { 0 }; 577 578 switch (ae_id) { 579 case IRDMA_AE_AMP_BOUNDS_VIOLATION: 580 case IRDMA_AE_AMP_INVALID_STAG: 581 case IRDMA_AE_AMP_RIGHTS_VIOLATION: 582 case IRDMA_AE_AMP_UNALLOCATED_STAG: 583 case IRDMA_AE_AMP_BAD_PD: 584 case IRDMA_AE_AMP_BAD_QP: 585 case IRDMA_AE_AMP_BAD_STAG_KEY: 586 case IRDMA_AE_AMP_BAD_STAG_INDEX: 587 case IRDMA_AE_AMP_TO_WRAP: 588 case IRDMA_AE_PRIV_OPERATION_DENIED: 589 qp_err.flush_code = FLUSH_PROT_ERR; 590 qp_err.event_type = IRDMA_QP_EVENT_ACCESS_ERR; 591 break; 592 case IRDMA_AE_UDA_XMIT_BAD_PD: 593 case IRDMA_AE_WQE_UNEXPECTED_OPCODE: 594 qp_err.flush_code = FLUSH_LOC_QP_OP_ERR; 595 qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; 596 break; 597 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: 598 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 599 case IRDMA_AE_UDA_L4LEN_INVALID: 600 case IRDMA_AE_DDP_UBE_INVALID_MO: 601 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: 602 qp_err.flush_code = FLUSH_LOC_LEN_ERR; 603 qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; 604 break; 605 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: 606 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: 607 qp_err.flush_code = FLUSH_REM_ACCESS_ERR; 608 qp_err.event_type = IRDMA_QP_EVENT_ACCESS_ERR; 609 break; 610 case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS: 611 case IRDMA_AE_AMP_MWBIND_BIND_DISABLED: 612 case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS: 613 case IRDMA_AE_AMP_MWBIND_VALID_STAG: 614 qp_err.flush_code = FLUSH_MW_BIND_ERR; 615 qp_err.event_type = IRDMA_QP_EVENT_ACCESS_ERR; 616 break; 617 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 618 qp_err.flush_code = FLUSH_RETRY_EXC_ERR; 619 qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; 620 break; 621 case IRDMA_AE_IB_INVALID_REQUEST: 622 qp_err.flush_code = FLUSH_REM_INV_REQ_ERR; 623 qp_err.event_type = IRDMA_QP_EVENT_REQ_ERR; 624 break; 625 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 626 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 627 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: 628 case IRDMA_AE_IB_REMOTE_OP_ERROR: 629 qp_err.flush_code = FLUSH_REM_OP_ERR; 630 qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; 631 break; 632 case IRDMA_AE_LCE_QP_CATASTROPHIC: 633 qp_err.flush_code = FLUSH_FATAL_ERR; 634 qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; 635 break; 636 default: 637 qp_err.flush_code = FLUSH_GENERAL_ERR; 638 qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; 639 break; 640 } 641 642 return qp_err; 643 } 644 #endif /* IRDMA_USER_H */ 645