1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2016 - 2021 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #ifndef IRDMA_UDA_D_H 37 #define IRDMA_UDA_D_H 38 /* L4 packet type */ 39 #define IRDMA_E_UDA_SQ_L4T_UNKNOWN 0 40 #define IRDMA_E_UDA_SQ_L4T_TCP 1 41 #define IRDMA_E_UDA_SQ_L4T_SCTP 2 42 #define IRDMA_E_UDA_SQ_L4T_UDP 3 43 /* Inner IP header type */ 44 #define IRDMA_E_UDA_SQ_IIPT_UNKNOWN 0 45 #define IRDMA_E_UDA_SQ_IIPT_IPV6 1 46 #define IRDMA_E_UDA_SQ_IIPT_IPV4_NO_CSUM 2 47 #define IRDMA_E_UDA_SQ_IIPT_IPV4_CSUM 3 48 #define IRDMA_UDA_QPSQ_PUSHWQE_S 56 49 #define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56) 50 #define IRDMA_UDA_QPSQ_INLINEDATAFLAG_S 57 51 #define IRDMA_UDA_QPSQ_INLINEDATAFLAG BIT_ULL(57) 52 #define IRDMA_UDA_QPSQ_INLINEDATALEN_S 48 53 #define IRDMA_UDA_QPSQ_INLINEDATALEN GENMASK_ULL(55, 48) 54 #define IRDMA_UDA_QPSQ_ADDFRAGCNT_S 38 55 #define IRDMA_UDA_QPSQ_ADDFRAGCNT GENMASK_ULL(41, 38) 56 #define IRDMA_UDA_QPSQ_IPFRAGFLAGS_S 42 57 #define IRDMA_UDA_QPSQ_IPFRAGFLAGS GENMASK_ULL(43, 42) 58 #define IRDMA_UDA_QPSQ_NOCHECKSUM_S 45 59 #define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45) 60 #define IRDMA_UDA_QPSQ_AHIDXVALID_S 46 61 #define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46) 62 #define IRDMA_UDA_QPSQ_LOCAL_FENCE_S 61 63 #define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61) 64 #define IRDMA_UDA_QPSQ_AHIDX_S 0 65 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0) 66 #define IRDMA_UDA_QPSQ_PROTOCOL_S 16 67 #define IRDMA_UDA_QPSQ_PROTOCOL GENMASK_ULL(23, 16) 68 #define IRDMA_UDA_QPSQ_EXTHDRLEN_S 32 69 #define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32) 70 #define IRDMA_UDA_QPSQ_MULTICAST_S 63 71 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63) 72 #define IRDMA_UDA_QPSQ_MACLEN_S 56 73 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56) 74 #define IRDMA_UDA_QPSQ_MACLEN_LINE 2 75 #define IRDMA_UDA_QPSQ_IPLEN_S 48 76 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48) 77 #define IRDMA_UDA_QPSQ_IPLEN_LINE 2 78 #define IRDMA_UDA_QPSQ_L4T_S 30 79 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30) 80 #define IRDMA_UDA_QPSQ_L4T_LINE 2 81 #define IRDMA_UDA_QPSQ_IIPT_S 28 82 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28) 83 #define IRDMA_UDA_QPSQ_IIPT_LINE 2 84 #define IRDMA_UDA_QPSQ_DO_LPB_LINE 3 85 #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM_S 45 86 #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM BIT_ULL(45) 87 #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM_LINE 3 88 #define IRDMA_UDA_QPSQ_IMMDATA_S 0 89 #define IRDMA_UDA_QPSQ_IMMDATA GENMASK_ULL(63, 0) 90 /* Byte Offset 0 */ 91 #define IRDMA_UDAQPC_IPV4_S 3 92 #define IRDMA_UDAQPC_IPV4 BIT_ULL(3) 93 #define IRDMA_UDAQPC_INSERTVLANTAG_S 5 94 #define IRDMA_UDAQPC_INSERTVLANTAG BIT_ULL(5) 95 #define IRDMA_UDAQPC_ISQP1_S 6 96 #define IRDMA_UDAQPC_ISQP1 BIT_ULL(6) 97 #define IRDMA_UDAQPC_RQWQESIZE_S IRDMAQPC_RQWQESIZE_S 98 #define IRDMA_UDAQPC_RQWQESIZE IRDMAQPC_RQWQESIZE 99 #define IRDMA_UDAQPC_ECNENABLE_S 14 100 #define IRDMA_UDAQPC_ECNENABLE BIT_ULL(14) 101 #define IRDMA_UDAQPC_PDINDEXHI_S 20 102 #define IRDMA_UDAQPC_PDINDEXHI GENMASK_ULL(21, 20) 103 #define IRDMA_UDAQPC_DCTCPENABLE_S 25 104 #define IRDMA_UDAQPC_DCTCPENABLE BIT_ULL(25) 105 #define IRDMA_UDAQPC_RCVTPHEN_S IRDMAQPC_RCVTPHEN_S 106 #define IRDMA_UDAQPC_RCVTPHEN IRDMAQPC_RCVTPHEN 107 #define IRDMA_UDAQPC_XMITTPHEN_S IRDMAQPC_XMITTPHEN_S 108 #define IRDMA_UDAQPC_XMITTPHEN IRDMAQPC_XMITTPHEN 109 #define IRDMA_UDAQPC_RQTPHEN_S IRDMAQPC_RQTPHEN_S 110 #define IRDMA_UDAQPC_RQTPHEN IRDMAQPC_RQTPHEN 111 #define IRDMA_UDAQPC_SQTPHEN_S IRDMAQPC_SQTPHEN_S 112 #define IRDMA_UDAQPC_SQTPHEN IRDMAQPC_SQTPHEN 113 #define IRDMA_UDAQPC_PPIDX_S IRDMAQPC_PPIDX_S 114 #define IRDMA_UDAQPC_PPIDX IRDMAQPC_PPIDX 115 #define IRDMA_UDAQPC_PMENA_S IRDMAQPC_PMENA_S 116 #define IRDMA_UDAQPC_PMENA IRDMAQPC_PMENA 117 #define IRDMA_UDAQPC_INSERTTAG2_S 11 118 #define IRDMA_UDAQPC_INSERTTAG2 BIT_ULL(11) 119 #define IRDMA_UDAQPC_INSERTTAG3_S 14 120 #define IRDMA_UDAQPC_INSERTTAG3 BIT_ULL(14) 121 #define IRDMA_UDAQPC_RQSIZE_S IRDMAQPC_RQSIZE_S 122 #define IRDMA_UDAQPC_RQSIZE IRDMAQPC_RQSIZE 123 #define IRDMA_UDAQPC_SQSIZE_S IRDMAQPC_SQSIZE_S 124 #define IRDMA_UDAQPC_SQSIZE IRDMAQPC_SQSIZE 125 #define IRDMA_UDAQPC_TXCQNUM_S IRDMAQPC_TXCQNUM_S 126 #define IRDMA_UDAQPC_TXCQNUM IRDMAQPC_TXCQNUM 127 #define IRDMA_UDAQPC_RXCQNUM_S IRDMAQPC_RXCQNUM_S 128 #define IRDMA_UDAQPC_RXCQNUM IRDMAQPC_RXCQNUM 129 #define IRDMA_UDAQPC_QPCOMPCTX_S IRDMAQPC_QPCOMPCTX_S 130 #define IRDMA_UDAQPC_QPCOMPCTX IRDMAQPC_QPCOMPCTX 131 #define IRDMA_UDAQPC_SQTPHVAL_S IRDMAQPC_SQTPHVAL_S 132 #define IRDMA_UDAQPC_SQTPHVAL IRDMAQPC_SQTPHVAL 133 #define IRDMA_UDAQPC_RQTPHVAL_S IRDMAQPC_RQTPHVAL_S 134 #define IRDMA_UDAQPC_RQTPHVAL IRDMAQPC_RQTPHVAL 135 #define IRDMA_UDAQPC_QSHANDLE_S IRDMAQPC_QSHANDLE_S 136 #define IRDMA_UDAQPC_QSHANDLE IRDMAQPC_QSHANDLE 137 #define IRDMA_UDAQPC_RQHDRRINGBUFSIZE_S 48 138 #define IRDMA_UDAQPC_RQHDRRINGBUFSIZE GENMASK_ULL(49, 48) 139 #define IRDMA_UDAQPC_SQHDRRINGBUFSIZE_S 32 140 #define IRDMA_UDAQPC_SQHDRRINGBUFSIZE GENMASK_ULL(33, 32) 141 #define IRDMA_UDAQPC_PRIVILEGEENABLE_S 25 142 #define IRDMA_UDAQPC_PRIVILEGEENABLE BIT_ULL(25) 143 #define IRDMA_UDAQPC_USE_STATISTICS_INSTANCE_S 26 144 #define IRDMA_UDAQPC_USE_STATISTICS_INSTANCE BIT_ULL(26) 145 #define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX_S 0 146 #define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX GENMASK_ULL(6, 0) 147 #define IRDMA_UDAQPC_PRIVHDRGENENABLE_S 0 148 #define IRDMA_UDAQPC_PRIVHDRGENENABLE BIT_ULL(0) 149 #define IRDMA_UDAQPC_RQHDRSPLITENABLE_S 3 150 #define IRDMA_UDAQPC_RQHDRSPLITENABLE BIT_ULL(3) 151 #define IRDMA_UDAQPC_RQHDRRINGBUFENABLE_S 2 152 #define IRDMA_UDAQPC_RQHDRRINGBUFENABLE BIT_ULL(2) 153 #define IRDMA_UDAQPC_SQHDRRINGBUFENABLE_S 1 154 #define IRDMA_UDAQPC_SQHDRRINGBUFENABLE BIT_ULL(1) 155 #define IRDMA_UDAQPC_IPID_S 32 156 #define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32) 157 #define IRDMA_UDAQPC_SNDMSS_S 16 158 #define IRDMA_UDAQPC_SNDMSS GENMASK_ULL(29, 16) 159 #define IRDMA_UDAQPC_VLANTAG_S 0 160 #define IRDMA_UDAQPC_VLANTAG GENMASK_ULL(15, 0) 161 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI_S 20 162 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI GENMASK_ULL(21, 20) 163 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO_S 48 164 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO GENMASK_ULL(63, 48) 165 #define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX_S 24 166 #define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX GENMASK_ULL(29, 24) 167 #define IRDMA_UDA_CQPSQ_MAV_ARPINDEX_S 48 168 #define IRDMA_UDA_CQPSQ_MAV_ARPINDEX GENMASK_ULL(63, 48) 169 #define IRDMA_UDA_CQPSQ_MAV_TC_S 32 170 #define IRDMA_UDA_CQPSQ_MAV_TC GENMASK_ULL(39, 32) 171 #define IRDMA_UDA_CQPSQ_MAV_HOPLIMIT_S 32 172 #define IRDMA_UDA_CQPSQ_MAV_HOPLIMIT GENMASK_ULL(39, 32) 173 #define IRDMA_UDA_CQPSQ_MAV_FLOWLABEL_S 0 174 #define IRDMA_UDA_CQPSQ_MAV_FLOWLABEL GENMASK_ULL(19, 0) 175 #define IRDMA_UDA_CQPSQ_MAV_ADDR0_S 32 176 #define IRDMA_UDA_CQPSQ_MAV_ADDR0 GENMASK_ULL(63, 32) 177 #define IRDMA_UDA_CQPSQ_MAV_ADDR1_S 0 178 #define IRDMA_UDA_CQPSQ_MAV_ADDR1 GENMASK_ULL(31, 0) 179 #define IRDMA_UDA_CQPSQ_MAV_ADDR2_S 32 180 #define IRDMA_UDA_CQPSQ_MAV_ADDR2 GENMASK_ULL(63, 32) 181 #define IRDMA_UDA_CQPSQ_MAV_ADDR3_S 0 182 #define IRDMA_UDA_CQPSQ_MAV_ADDR3 GENMASK_ULL(31, 0) 183 #define IRDMA_UDA_CQPSQ_MAV_WQEVALID_S 63 184 #define IRDMA_UDA_CQPSQ_MAV_WQEVALID BIT_ULL(63) 185 #define IRDMA_UDA_CQPSQ_MAV_OPCODE_S 32 186 #define IRDMA_UDA_CQPSQ_MAV_OPCODE GENMASK_ULL(37, 32) 187 #define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK_S 62 188 #define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK BIT_ULL(62) 189 #define IRDMA_UDA_CQPSQ_MAV_IPV4VALID_S 59 190 #define IRDMA_UDA_CQPSQ_MAV_IPV4VALID BIT_ULL(59) 191 192 #define IRDMA_UDA_CQPSQ_MAV_AVIDX_S 0 193 #define IRDMA_UDA_CQPSQ_MAV_AVIDX GENMASK_ULL(16, 0) 194 #define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG_S 60 195 #define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG BIT_ULL(60) 196 #define IRDMA_UDA_MGCTX_VFFLAG_S 29 197 #define IRDMA_UDA_MGCTX_VFFLAG BIT_ULL(29) 198 #define IRDMA_UDA_MGCTX_DESTPORT_S 32 199 #define IRDMA_UDA_MGCTX_DESTPORT GENMASK_ULL(47, 32) 200 #define IRDMA_UDA_MGCTX_VFID_S 22 201 #define IRDMA_UDA_MGCTX_VFID GENMASK_ULL(28, 22) 202 #define IRDMA_UDA_MGCTX_VALIDENT_S 31 203 #define IRDMA_UDA_MGCTX_VALIDENT BIT_ULL(31) 204 #define IRDMA_UDA_MGCTX_PFID_S 18 205 #define IRDMA_UDA_MGCTX_PFID GENMASK_ULL(21, 18) 206 #define IRDMA_UDA_MGCTX_FLAGIGNOREDPORT_S 30 207 #define IRDMA_UDA_MGCTX_FLAGIGNOREDPORT BIT_ULL(30) 208 #define IRDMA_UDA_MGCTX_QPID_S 0 209 #define IRDMA_UDA_MGCTX_QPID GENMASK_ULL(17, 0) 210 #define IRDMA_UDA_CQPSQ_MG_WQEVALID_S 63 211 #define IRDMA_UDA_CQPSQ_MG_WQEVALID BIT_ULL(63) 212 #define IRDMA_UDA_CQPSQ_MG_OPCODE_S 32 213 #define IRDMA_UDA_CQPSQ_MG_OPCODE GENMASK_ULL(37, 32) 214 #define IRDMA_UDA_CQPSQ_MG_MGIDX_S 0 215 #define IRDMA_UDA_CQPSQ_MG_MGIDX GENMASK_ULL(12, 0) 216 #define IRDMA_UDA_CQPSQ_MG_IPV4VALID_S 60 217 #define IRDMA_UDA_CQPSQ_MG_IPV4VALID BIT_ULL(60) 218 #define IRDMA_UDA_CQPSQ_MG_VLANVALID_S 59 219 #define IRDMA_UDA_CQPSQ_MG_VLANVALID BIT_ULL(59) 220 #define IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID_S 0 221 #define IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID GENMASK_ULL(5, 0) 222 #define IRDMA_UDA_CQPSQ_MG_VLANID_S 32 223 #define IRDMA_UDA_CQPSQ_MG_VLANID GENMASK_ULL(43, 32) 224 #define IRDMA_UDA_CQPSQ_QS_HANDLE_S 0 225 #define IRDMA_UDA_CQPSQ_QS_HANDLE GENMASK_ULL(9, 0) 226 #define IRDMA_UDA_CQPSQ_QHASH_QPN_S 32 227 #define IRDMA_UDA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32) 228 #define IRDMA_UDA_CQPSQ_QHASH__S 0 229 #define IRDMA_UDA_CQPSQ_QHASH_ BIT_ULL(0) 230 #define IRDMA_UDA_CQPSQ_QHASH_SRC_PORT_S 16 231 #define IRDMA_UDA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16) 232 #define IRDMA_UDA_CQPSQ_QHASH_DEST_PORT_S 0 233 #define IRDMA_UDA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0) 234 #define IRDMA_UDA_CQPSQ_QHASH_ADDR0_S 32 235 #define IRDMA_UDA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32) 236 #define IRDMA_UDA_CQPSQ_QHASH_ADDR1_S 0 237 #define IRDMA_UDA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0) 238 #define IRDMA_UDA_CQPSQ_QHASH_ADDR2_S 32 239 #define IRDMA_UDA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32) 240 #define IRDMA_UDA_CQPSQ_QHASH_ADDR3_S 0 241 #define IRDMA_UDA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0) 242 #define IRDMA_UDA_CQPSQ_QHASH_WQEVALID_S 63 243 #define IRDMA_UDA_CQPSQ_QHASH_WQEVALID BIT_ULL(63) 244 #define IRDMA_UDA_CQPSQ_QHASH_OPCODE_S 32 245 #define IRDMA_UDA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32) 246 #define IRDMA_UDA_CQPSQ_QHASH_MANAGE_S 61 247 #define IRDMA_UDA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61) 248 #define IRDMA_UDA_CQPSQ_QHASH_IPV4VALID_S 60 249 #define IRDMA_UDA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60) 250 #define IRDMA_UDA_CQPSQ_QHASH_LANFWD_S 59 251 #define IRDMA_UDA_CQPSQ_QHASH_LANFWD BIT_ULL(59) 252 #define IRDMA_UDA_CQPSQ_QHASH_ENTRYTYPE_S 42 253 #define IRDMA_UDA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42) 254 #endif /* IRDMA_UDA_D_H */ 255