1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-NetBSD 3 * 4 * Copyright (c) 1995, David Greenman 5 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 37 */ 38 39 #ifdef HAVE_KERNEL_OPTION_HEADERS 40 #include "opt_device_polling.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/kernel.h> 48 #include <sys/mbuf.h> 49 #include <sys/lock.h> 50 #include <sys/malloc.h> 51 #include <sys/module.h> 52 #include <sys/mutex.h> 53 #include <sys/rman.h> 54 #include <sys/socket.h> 55 #include <sys/sockio.h> 56 #include <sys/sysctl.h> 57 58 #include <net/bpf.h> 59 #include <net/ethernet.h> 60 #include <net/if.h> 61 #include <net/if_var.h> 62 #include <net/if_arp.h> 63 #include <net/if_dl.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 #include <net/if_vlan_var.h> 67 68 #include <netinet/in.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 74 #include <machine/bus.h> 75 #include <machine/in_cksum.h> 76 #include <machine/resource.h> 77 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 80 81 #include <dev/mii/mii.h> 82 #include <dev/mii/miivar.h> 83 84 #include <dev/fxp/if_fxpreg.h> 85 #include <dev/fxp/if_fxpvar.h> 86 #include <dev/fxp/rcvbundl.h> 87 88 MODULE_DEPEND(fxp, pci, 1, 1, 1); 89 MODULE_DEPEND(fxp, ether, 1, 1, 1); 90 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 91 #include "miibus_if.h" 92 93 /* 94 * NOTE! On !x86 we typically have an alignment constraint. The 95 * card DMAs the packet immediately following the RFA. However, 96 * the first thing in the packet is a 14-byte Ethernet header. 97 * This means that the packet is misaligned. To compensate, 98 * we actually offset the RFA 2 bytes into the cluster. This 99 * alignes the packet after the Ethernet header at a 32-bit 100 * boundary. HOWEVER! This means that the RFA is misaligned! 101 */ 102 #define RFA_ALIGNMENT_FUDGE 2 103 104 /* 105 * Set initial transmit threshold at 64 (512 bytes). This is 106 * increased by 64 (512 bytes) at a time, to maximum of 192 107 * (1536 bytes), if an underrun occurs. 108 */ 109 static int tx_threshold = 64; 110 111 /* 112 * The configuration byte map has several undefined fields which 113 * must be one or must be zero. Set up a template for these bits. 114 * The actual configuration is performed in fxp_init_body. 115 * 116 * See struct fxp_cb_config for the bit definitions. 117 */ 118 static const u_char fxp_cb_config_template[] = { 119 0x0, 0x0, /* cb_status */ 120 0x0, 0x0, /* cb_command */ 121 0x0, 0x0, 0x0, 0x0, /* link_addr */ 122 0x0, /* 0 */ 123 0x0, /* 1 */ 124 0x0, /* 2 */ 125 0x0, /* 3 */ 126 0x0, /* 4 */ 127 0x0, /* 5 */ 128 0x32, /* 6 */ 129 0x0, /* 7 */ 130 0x0, /* 8 */ 131 0x0, /* 9 */ 132 0x6, /* 10 */ 133 0x0, /* 11 */ 134 0x0, /* 12 */ 135 0x0, /* 13 */ 136 0xf2, /* 14 */ 137 0x48, /* 15 */ 138 0x0, /* 16 */ 139 0x40, /* 17 */ 140 0xf0, /* 18 */ 141 0x0, /* 19 */ 142 0x3f, /* 20 */ 143 0x5, /* 21 */ 144 0x0, /* 22 */ 145 0x0, /* 23 */ 146 0x0, /* 24 */ 147 0x0, /* 25 */ 148 0x0, /* 26 */ 149 0x0, /* 27 */ 150 0x0, /* 28 */ 151 0x0, /* 29 */ 152 0x0, /* 30 */ 153 0x0 /* 31 */ 154 }; 155 156 /* 157 * Claim various Intel PCI device identifiers for this driver. The 158 * sub-vendor and sub-device field are extensively used to identify 159 * particular variants, but we don't currently differentiate between 160 * them. 161 */ 162 static const struct fxp_ident fxp_ident_table[] = { 163 { 0x8086, 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" }, 164 { 0x8086, 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" }, 165 { 0x8086, 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 166 { 0x8086, 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 167 { 0x8086, 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 168 { 0x8086, 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 169 { 0x8086, 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 170 { 0x8086, 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 171 { 0x8086, 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 172 { 0x8086, 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 173 { 0x8086, 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 174 { 0x8086, 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 175 { 0x8086, 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 176 { 0x8086, 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 177 { 0x8086, 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 178 { 0x8086, 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 179 { 0x8086, 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 180 { 0x8086, 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 181 { 0x8086, 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" }, 182 { 0x8086, 0x1064, -1, 6, "Intel 82562EZ (ICH6)" }, 183 { 0x8086, 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 184 { 0x8086, 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 185 { 0x8086, 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 186 { 0x8086, 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" }, 187 { 0x8086, 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" }, 188 { 0x8086, 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" }, 189 { 0x8086, 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 190 { 0x8086, 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" }, 191 { 0x8086, 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" }, 192 { 0x8086, 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" }, 193 { 0x8086, 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" }, 194 { 0x8086, 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" }, 195 { 0x8086, 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" }, 196 { 0x8086, 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" }, 197 { 0x8086, 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" }, 198 { 0x8086, 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" }, 199 { 0x8086, 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" }, 200 { 0x8086, 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" }, 201 { 0x8086, 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" }, 202 { 0x8086, 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" }, 203 { 0x8086, 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" }, 204 { 0x8086, 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" }, 205 { 0x8086, 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" }, 206 { 0x8086, 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 207 { 0x8086, 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 208 { 0, 0, -1, 0, NULL }, 209 }; 210 211 #ifdef FXP_IP_CSUM_WAR 212 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 213 #else 214 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 215 #endif 216 217 static int fxp_probe(device_t dev); 218 static int fxp_attach(device_t dev); 219 static int fxp_detach(device_t dev); 220 static int fxp_shutdown(device_t dev); 221 static int fxp_suspend(device_t dev); 222 static int fxp_resume(device_t dev); 223 224 static const struct fxp_ident *fxp_find_ident(device_t dev); 225 static void fxp_intr(void *xsc); 226 static void fxp_rxcsum(struct fxp_softc *sc, if_t ifp, 227 struct mbuf *m, uint16_t status, int pos); 228 static int fxp_intr_body(struct fxp_softc *sc, if_t ifp, 229 uint8_t statack, int count); 230 static void fxp_init(void *xsc); 231 static void fxp_init_body(struct fxp_softc *sc, int); 232 static void fxp_tick(void *xsc); 233 static void fxp_start(if_t ifp); 234 static void fxp_start_body(if_t ifp); 235 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 236 static void fxp_txeof(struct fxp_softc *sc); 237 static void fxp_stop(struct fxp_softc *sc); 238 static void fxp_release(struct fxp_softc *sc); 239 static int fxp_ioctl(if_t ifp, u_long command, 240 caddr_t data); 241 static void fxp_watchdog(struct fxp_softc *sc); 242 static void fxp_add_rfabuf(struct fxp_softc *sc, 243 struct fxp_rx *rxp); 244 static void fxp_discard_rfabuf(struct fxp_softc *sc, 245 struct fxp_rx *rxp); 246 static int fxp_new_rfabuf(struct fxp_softc *sc, 247 struct fxp_rx *rxp); 248 static int fxp_mc_addrs(struct fxp_softc *sc); 249 static void fxp_mc_setup(struct fxp_softc *sc); 250 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 251 int autosize); 252 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 253 uint16_t data); 254 static void fxp_autosize_eeprom(struct fxp_softc *sc); 255 static void fxp_load_eeprom(struct fxp_softc *sc); 256 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 257 int offset, int words); 258 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 259 int offset, int words); 260 static int fxp_ifmedia_upd(if_t ifp); 261 static void fxp_ifmedia_sts(if_t ifp, 262 struct ifmediareq *ifmr); 263 static int fxp_serial_ifmedia_upd(if_t ifp); 264 static void fxp_serial_ifmedia_sts(if_t ifp, 265 struct ifmediareq *ifmr); 266 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 267 static int fxp_miibus_writereg(device_t dev, int phy, int reg, 268 int value); 269 static void fxp_miibus_statchg(device_t dev); 270 static void fxp_load_ucode(struct fxp_softc *sc); 271 static void fxp_update_stats(struct fxp_softc *sc); 272 static void fxp_sysctl_node(struct fxp_softc *sc); 273 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 274 int low, int high); 275 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 276 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 277 static void fxp_scb_wait(struct fxp_softc *sc); 278 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 279 static void fxp_dma_wait(struct fxp_softc *sc, 280 volatile uint16_t *status, bus_dma_tag_t dmat, 281 bus_dmamap_t map); 282 283 static device_method_t fxp_methods[] = { 284 /* Device interface */ 285 DEVMETHOD(device_probe, fxp_probe), 286 DEVMETHOD(device_attach, fxp_attach), 287 DEVMETHOD(device_detach, fxp_detach), 288 DEVMETHOD(device_shutdown, fxp_shutdown), 289 DEVMETHOD(device_suspend, fxp_suspend), 290 DEVMETHOD(device_resume, fxp_resume), 291 292 /* MII interface */ 293 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 294 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 295 DEVMETHOD(miibus_statchg, fxp_miibus_statchg), 296 297 DEVMETHOD_END 298 }; 299 300 static driver_t fxp_driver = { 301 "fxp", 302 fxp_methods, 303 sizeof(struct fxp_softc), 304 }; 305 306 static devclass_t fxp_devclass; 307 308 DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, fxp_devclass, NULL, NULL, 309 SI_ORDER_ANY); 310 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL); 311 312 static struct resource_spec fxp_res_spec_mem[] = { 313 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 314 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 315 { -1, 0 } 316 }; 317 318 static struct resource_spec fxp_res_spec_io[] = { 319 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 320 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 321 { -1, 0 } 322 }; 323 324 /* 325 * Wait for the previous command to be accepted (but not necessarily 326 * completed). 327 */ 328 static void 329 fxp_scb_wait(struct fxp_softc *sc) 330 { 331 union { 332 uint16_t w; 333 uint8_t b[2]; 334 } flowctl; 335 int i = 10000; 336 337 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 338 DELAY(2); 339 if (i == 0) { 340 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH); 341 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS); 342 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 343 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 344 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 345 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 346 } 347 } 348 349 static void 350 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 351 { 352 353 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 354 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 355 fxp_scb_wait(sc); 356 } 357 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 358 } 359 360 static void 361 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 362 bus_dma_tag_t dmat, bus_dmamap_t map) 363 { 364 int i; 365 366 for (i = 10000; i > 0; i--) { 367 DELAY(2); 368 bus_dmamap_sync(dmat, map, 369 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 370 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0) 371 break; 372 } 373 if (i == 0) 374 device_printf(sc->dev, "DMA timeout\n"); 375 } 376 377 static const struct fxp_ident * 378 fxp_find_ident(device_t dev) 379 { 380 uint16_t vendor; 381 uint16_t device; 382 uint8_t revid; 383 const struct fxp_ident *ident; 384 385 vendor = pci_get_vendor(dev); 386 device = pci_get_device(dev); 387 revid = pci_get_revid(dev); 388 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 389 if (ident->vendor == vendor && ident->device == device && 390 (ident->revid == revid || ident->revid == -1)) { 391 return (ident); 392 } 393 } 394 return (NULL); 395 } 396 397 /* 398 * Return identification string if this device is ours. 399 */ 400 static int 401 fxp_probe(device_t dev) 402 { 403 const struct fxp_ident *ident; 404 405 ident = fxp_find_ident(dev); 406 if (ident != NULL) { 407 device_set_desc(dev, ident->name); 408 return (BUS_PROBE_DEFAULT); 409 } 410 return (ENXIO); 411 } 412 413 static void 414 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 415 { 416 uint32_t *addr; 417 418 if (error) 419 return; 420 421 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 422 addr = arg; 423 *addr = segs->ds_addr; 424 } 425 426 static int 427 fxp_attach(device_t dev) 428 { 429 struct fxp_softc *sc; 430 struct fxp_cb_tx *tcbp; 431 struct fxp_tx *txp; 432 struct fxp_rx *rxp; 433 if_t ifp; 434 uint32_t val; 435 uint16_t data; 436 u_char eaddr[ETHER_ADDR_LEN]; 437 int error, flags, i, pmc, prefer_iomap; 438 439 error = 0; 440 sc = device_get_softc(dev); 441 sc->dev = dev; 442 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 443 MTX_DEF); 444 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 445 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 446 fxp_serial_ifmedia_sts); 447 448 ifp = sc->ifp = if_gethandle(IFT_ETHER); 449 if (ifp == (void *)NULL) { 450 device_printf(dev, "can not if_alloc()\n"); 451 error = ENOSPC; 452 goto fail; 453 } 454 455 /* 456 * Enable bus mastering. 457 */ 458 pci_enable_busmaster(dev); 459 460 /* 461 * Figure out which we should try first - memory mapping or i/o mapping? 462 * We default to memory mapping. Then we accept an override from the 463 * command line. Then we check to see which one is enabled. 464 */ 465 prefer_iomap = 0; 466 resource_int_value(device_get_name(dev), device_get_unit(dev), 467 "prefer_iomap", &prefer_iomap); 468 if (prefer_iomap) 469 sc->fxp_spec = fxp_res_spec_io; 470 else 471 sc->fxp_spec = fxp_res_spec_mem; 472 473 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 474 if (error) { 475 if (sc->fxp_spec == fxp_res_spec_mem) 476 sc->fxp_spec = fxp_res_spec_io; 477 else 478 sc->fxp_spec = fxp_res_spec_mem; 479 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 480 } 481 if (error) { 482 device_printf(dev, "could not allocate resources\n"); 483 error = ENXIO; 484 goto fail; 485 } 486 487 if (bootverbose) { 488 device_printf(dev, "using %s space register mapping\n", 489 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 490 } 491 492 /* 493 * Put CU/RU idle state and prepare full reset. 494 */ 495 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 496 DELAY(10); 497 /* Full reset and disable interrupts. */ 498 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 499 DELAY(10); 500 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 501 502 /* 503 * Find out how large of an SEEPROM we have. 504 */ 505 fxp_autosize_eeprom(sc); 506 fxp_load_eeprom(sc); 507 508 /* 509 * Find out the chip revision; lump all 82557 revs together. 510 */ 511 sc->ident = fxp_find_ident(dev); 512 if (sc->ident->ich > 0) { 513 /* Assume ICH controllers are 82559. */ 514 sc->revision = FXP_REV_82559_A0; 515 } else { 516 data = sc->eeprom[FXP_EEPROM_MAP_CNTR]; 517 if ((data >> 8) == 1) 518 sc->revision = FXP_REV_82557; 519 else 520 sc->revision = pci_get_revid(dev); 521 } 522 523 /* 524 * Check availability of WOL. 82559ER does not support WOL. 525 */ 526 if (sc->revision >= FXP_REV_82558_A4 && 527 sc->revision != FXP_REV_82559S_A) { 528 data = sc->eeprom[FXP_EEPROM_MAP_ID]; 529 if ((data & 0x20) != 0 && 530 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) 531 sc->flags |= FXP_FLAG_WOLCAP; 532 } 533 534 if (sc->revision == FXP_REV_82550_C) { 535 /* 536 * 82550C with server extension requires microcode to 537 * receive fragmented UDP datagrams. However if the 538 * microcode is used for client-only featured 82550C 539 * it locks up controller. 540 */ 541 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT]; 542 if ((data & 0x0400) == 0) 543 sc->flags |= FXP_FLAG_NO_UCODE; 544 } 545 546 /* Receiver lock-up workaround detection. */ 547 if (sc->revision < FXP_REV_82558_A4) { 548 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT]; 549 if ((data & 0x03) != 0x03) { 550 sc->flags |= FXP_FLAG_RXBUG; 551 device_printf(dev, "Enabling Rx lock-up workaround\n"); 552 } 553 } 554 555 /* 556 * Determine whether we must use the 503 serial interface. 557 */ 558 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY]; 559 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 560 && (data & FXP_PHY_SERIAL_ONLY)) 561 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 562 563 fxp_sysctl_node(sc); 564 /* 565 * Enable workarounds for certain chip revision deficiencies. 566 * 567 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 568 * some systems based a normal 82559 design, have a defect where 569 * the chip can cause a PCI protocol violation if it receives 570 * a CU_RESUME command when it is entering the IDLE state. The 571 * workaround is to disable Dynamic Standby Mode, so the chip never 572 * deasserts CLKRUN#, and always remains in an active state. 573 * 574 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 575 */ 576 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) || 577 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) { 578 data = sc->eeprom[FXP_EEPROM_MAP_ID]; 579 if (data & 0x02) { /* STB enable */ 580 uint16_t cksum; 581 int i; 582 583 device_printf(dev, 584 "Disabling dynamic standby mode in EEPROM\n"); 585 data &= ~0x02; 586 sc->eeprom[FXP_EEPROM_MAP_ID] = data; 587 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1); 588 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 589 cksum = 0; 590 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) 591 cksum += sc->eeprom[i]; 592 i = (1 << sc->eeprom_size) - 1; 593 cksum = 0xBABA - cksum; 594 fxp_write_eeprom(sc, &cksum, i, 1); 595 device_printf(dev, 596 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 597 i, sc->eeprom[i], cksum); 598 sc->eeprom[i] = cksum; 599 /* 600 * If the user elects to continue, try the software 601 * workaround, as it is better than nothing. 602 */ 603 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 604 } 605 } 606 607 /* 608 * If we are not a 82557 chip, we can enable extended features. 609 */ 610 if (sc->revision != FXP_REV_82557) { 611 /* 612 * If MWI is enabled in the PCI configuration, and there 613 * is a valid cacheline size (8 or 16 dwords), then tell 614 * the board to turn on MWI. 615 */ 616 val = pci_read_config(dev, PCIR_COMMAND, 2); 617 if (val & PCIM_CMD_MWRICEN && 618 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 619 sc->flags |= FXP_FLAG_MWI_ENABLE; 620 621 /* turn on the extended TxCB feature */ 622 sc->flags |= FXP_FLAG_EXT_TXCB; 623 624 /* enable reception of long frames for VLAN */ 625 sc->flags |= FXP_FLAG_LONG_PKT_EN; 626 } else { 627 /* a hack to get long VLAN frames on a 82557 */ 628 sc->flags |= FXP_FLAG_SAVE_BAD; 629 } 630 631 /* For 82559 or later chips, Rx checksum offload is supported. */ 632 if (sc->revision >= FXP_REV_82559_A0) { 633 /* 82559ER does not support Rx checksum offloading. */ 634 if (sc->ident->device != 0x1209) 635 sc->flags |= FXP_FLAG_82559_RXCSUM; 636 } 637 /* 638 * Enable use of extended RFDs and TCBs for 82550 639 * and later chips. Note: we need extended TXCB support 640 * too, but that's already enabled by the code above. 641 * Be careful to do this only on the right devices. 642 */ 643 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 644 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 645 || sc->revision == FXP_REV_82551_10) { 646 sc->rfa_size = sizeof (struct fxp_rfa); 647 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 648 sc->flags |= FXP_FLAG_EXT_RFA; 649 /* Use extended RFA instead of 82559 checksum mode. */ 650 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 651 } else { 652 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 653 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 654 } 655 656 /* 657 * Allocate DMA tags and DMA safe memory. 658 */ 659 sc->maxtxseg = FXP_NTXSEG; 660 sc->maxsegsize = MCLBYTES; 661 if (sc->flags & FXP_FLAG_EXT_RFA) { 662 sc->maxtxseg--; 663 sc->maxsegsize = FXP_TSO_SEGSIZE; 664 } 665 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 666 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 667 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 668 sc->maxtxseg, sc->maxsegsize, 0, 669 busdma_lock_mutex, &Giant, &sc->fxp_txmtag); 670 if (error) { 671 device_printf(dev, "could not create TX DMA tag\n"); 672 goto fail; 673 } 674 675 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 676 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 677 MCLBYTES, 1, MCLBYTES, 0, 678 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag); 679 if (error) { 680 device_printf(dev, "could not create RX DMA tag\n"); 681 goto fail; 682 } 683 684 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 685 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 686 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 687 busdma_lock_mutex, &Giant, &sc->fxp_stag); 688 if (error) { 689 device_printf(dev, "could not create stats DMA tag\n"); 690 goto fail; 691 } 692 693 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 694 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap); 695 if (error) { 696 device_printf(dev, "could not allocate stats DMA memory\n"); 697 goto fail; 698 } 699 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 700 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 701 BUS_DMA_NOWAIT); 702 if (error) { 703 device_printf(dev, "could not load the stats DMA buffer\n"); 704 goto fail; 705 } 706 707 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 708 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 709 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, 710 busdma_lock_mutex, &Giant, &sc->cbl_tag); 711 if (error) { 712 device_printf(dev, "could not create TxCB DMA tag\n"); 713 goto fail; 714 } 715 716 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 717 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map); 718 if (error) { 719 device_printf(dev, "could not allocate TxCB DMA memory\n"); 720 goto fail; 721 } 722 723 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 724 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 725 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT); 726 if (error) { 727 device_printf(dev, "could not load TxCB DMA buffer\n"); 728 goto fail; 729 } 730 731 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 732 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 733 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 734 busdma_lock_mutex, &Giant, &sc->mcs_tag); 735 if (error) { 736 device_printf(dev, 737 "could not create multicast setup DMA tag\n"); 738 goto fail; 739 } 740 741 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 742 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map); 743 if (error) { 744 device_printf(dev, 745 "could not allocate multicast setup DMA memory\n"); 746 goto fail; 747 } 748 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 749 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 750 BUS_DMA_NOWAIT); 751 if (error) { 752 device_printf(dev, 753 "can't load the multicast setup DMA buffer\n"); 754 goto fail; 755 } 756 757 /* 758 * Pre-allocate the TX DMA maps and setup the pointers to 759 * the TX command blocks. 760 */ 761 txp = sc->fxp_desc.tx_list; 762 tcbp = sc->fxp_desc.cbl_list; 763 for (i = 0; i < FXP_NTXCB; i++) { 764 txp[i].tx_cb = tcbp + i; 765 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map); 766 if (error) { 767 device_printf(dev, "can't create DMA map for TX\n"); 768 goto fail; 769 } 770 } 771 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map); 772 if (error) { 773 device_printf(dev, "can't create spare DMA map\n"); 774 goto fail; 775 } 776 777 /* 778 * Pre-allocate our receive buffers. 779 */ 780 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 781 for (i = 0; i < FXP_NRFABUFS; i++) { 782 rxp = &sc->fxp_desc.rx_list[i]; 783 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map); 784 if (error) { 785 device_printf(dev, "can't create DMA map for RX\n"); 786 goto fail; 787 } 788 if (fxp_new_rfabuf(sc, rxp) != 0) { 789 error = ENOMEM; 790 goto fail; 791 } 792 fxp_add_rfabuf(sc, rxp); 793 } 794 795 /* 796 * Read MAC address. 797 */ 798 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff; 799 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8; 800 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff; 801 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8; 802 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff; 803 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8; 804 if (bootverbose) { 805 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 806 pci_get_vendor(dev), pci_get_device(dev), 807 pci_get_subvendor(dev), pci_get_subdevice(dev), 808 pci_get_revid(dev)); 809 device_printf(dev, "Dynamic Standby mode is %s\n", 810 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" : 811 "disabled"); 812 } 813 814 /* 815 * If this is only a 10Mbps device, then there is no MII, and 816 * the PHY will use a serial interface instead. 817 * 818 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 819 * doesn't have a programming interface of any sort. The 820 * media is sensed automatically based on how the link partner 821 * is configured. This is, in essence, manual configuration. 822 */ 823 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 824 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 825 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 826 } else { 827 /* 828 * i82557 wedge when isolating all of their PHYs. 829 */ 830 flags = MIIF_NOISOLATE; 831 if (sc->revision >= FXP_REV_82558_A4) 832 flags |= MIIF_DOPAUSE; 833 error = mii_attach(dev, &sc->miibus, ifp, 834 (ifm_change_cb_t)fxp_ifmedia_upd, 835 (ifm_stat_cb_t)fxp_ifmedia_sts, BMSR_DEFCAPMASK, 836 MII_PHY_ANY, MII_OFFSET_ANY, flags); 837 if (error != 0) { 838 device_printf(dev, "attaching PHYs failed\n"); 839 goto fail; 840 } 841 } 842 843 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 844 if_setdev(ifp, dev); 845 if_setinitfn(ifp, fxp_init); 846 if_setsoftc(ifp, sc); 847 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 848 if_setioctlfn(ifp, fxp_ioctl); 849 if_setstartfn(ifp, fxp_start); 850 851 if_setcapabilities(ifp, 0); 852 if_setcapenable(ifp, 0); 853 854 /* Enable checksum offload/TSO for 82550 or better chips */ 855 if (sc->flags & FXP_FLAG_EXT_RFA) { 856 if_sethwassist(ifp, FXP_CSUM_FEATURES | CSUM_TSO); 857 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 858 if_setcapenablebit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 859 } 860 861 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 862 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 863 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0); 864 } 865 866 if (sc->flags & FXP_FLAG_WOLCAP) { 867 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 868 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0); 869 } 870 871 #ifdef DEVICE_POLLING 872 /* Inform the world we support polling. */ 873 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 874 #endif 875 876 /* 877 * Attach the interface. 878 */ 879 ether_ifattach(ifp, eaddr); 880 881 /* 882 * Tell the upper layer(s) we support long frames. 883 * Must appear after the call to ether_ifattach() because 884 * ether_ifattach() sets ifi_hdrlen to the default value. 885 */ 886 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 887 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 888 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0); 889 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { 890 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | 891 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 892 if_setcapenablebit(ifp, IFCAP_VLAN_HWTAGGING | 893 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 894 } 895 896 /* 897 * Let the system queue as many packets as we have available 898 * TX descriptors. 899 */ 900 if_setsendqlen(ifp, FXP_NTXCB - 1); 901 if_setsendqready(ifp); 902 903 /* 904 * Hook our interrupt after all initialization is complete. 905 */ 906 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 907 NULL, fxp_intr, sc, &sc->ih); 908 if (error) { 909 device_printf(dev, "could not setup irq\n"); 910 ether_ifdetach(sc->ifp); 911 goto fail; 912 } 913 914 /* 915 * Configure hardware to reject magic frames otherwise 916 * system will hang on recipt of magic frames. 917 */ 918 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 919 FXP_LOCK(sc); 920 /* Clear wakeup events. */ 921 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); 922 fxp_init_body(sc, 0); 923 fxp_stop(sc); 924 FXP_UNLOCK(sc); 925 } 926 927 fail: 928 if (error) 929 fxp_release(sc); 930 return (error); 931 } 932 933 /* 934 * Release all resources. The softc lock should not be held and the 935 * interrupt should already be torn down. 936 */ 937 static void 938 fxp_release(struct fxp_softc *sc) 939 { 940 struct fxp_rx *rxp; 941 struct fxp_tx *txp; 942 int i; 943 944 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 945 KASSERT(sc->ih == NULL, 946 ("fxp_release() called with intr handle still active")); 947 if (sc->miibus) 948 device_delete_child(sc->dev, sc->miibus); 949 bus_generic_detach(sc->dev); 950 ifmedia_removeall(&sc->sc_media); 951 if (sc->fxp_desc.cbl_list) { 952 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 953 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 954 sc->cbl_map); 955 } 956 if (sc->fxp_stats) { 957 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 958 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 959 } 960 if (sc->mcsp) { 961 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 962 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 963 } 964 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 965 if (sc->fxp_rxmtag) { 966 for (i = 0; i < FXP_NRFABUFS; i++) { 967 rxp = &sc->fxp_desc.rx_list[i]; 968 if (rxp->rx_mbuf != NULL) { 969 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 970 BUS_DMASYNC_POSTREAD); 971 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 972 m_freem(rxp->rx_mbuf); 973 } 974 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map); 975 } 976 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map); 977 bus_dma_tag_destroy(sc->fxp_rxmtag); 978 } 979 if (sc->fxp_txmtag) { 980 for (i = 0; i < FXP_NTXCB; i++) { 981 txp = &sc->fxp_desc.tx_list[i]; 982 if (txp->tx_mbuf != NULL) { 983 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 984 BUS_DMASYNC_POSTWRITE); 985 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 986 m_freem(txp->tx_mbuf); 987 } 988 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map); 989 } 990 bus_dma_tag_destroy(sc->fxp_txmtag); 991 } 992 if (sc->fxp_stag) 993 bus_dma_tag_destroy(sc->fxp_stag); 994 if (sc->cbl_tag) 995 bus_dma_tag_destroy(sc->cbl_tag); 996 if (sc->mcs_tag) 997 bus_dma_tag_destroy(sc->mcs_tag); 998 if (sc->ifp) 999 if_free(sc->ifp); 1000 1001 mtx_destroy(&sc->sc_mtx); 1002 } 1003 1004 /* 1005 * Detach interface. 1006 */ 1007 static int 1008 fxp_detach(device_t dev) 1009 { 1010 struct fxp_softc *sc = device_get_softc(dev); 1011 1012 #ifdef DEVICE_POLLING 1013 if (if_getcapenable(sc->ifp) & IFCAP_POLLING) 1014 ether_poll_deregister(sc->ifp); 1015 #endif 1016 1017 FXP_LOCK(sc); 1018 /* 1019 * Stop DMA and drop transmit queue, but disable interrupts first. 1020 */ 1021 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1022 fxp_stop(sc); 1023 FXP_UNLOCK(sc); 1024 callout_drain(&sc->stat_ch); 1025 1026 /* 1027 * Close down routes etc. 1028 */ 1029 ether_ifdetach(sc->ifp); 1030 1031 /* 1032 * Unhook interrupt before dropping lock. This is to prevent 1033 * races with fxp_intr(). 1034 */ 1035 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 1036 sc->ih = NULL; 1037 1038 /* Release our allocated resources. */ 1039 fxp_release(sc); 1040 return (0); 1041 } 1042 1043 /* 1044 * Device shutdown routine. Called at system shutdown after sync. The 1045 * main purpose of this routine is to shut off receiver DMA so that 1046 * kernel memory doesn't get clobbered during warmboot. 1047 */ 1048 static int 1049 fxp_shutdown(device_t dev) 1050 { 1051 1052 /* 1053 * Make sure that DMA is disabled prior to reboot. Not doing 1054 * do could allow DMA to corrupt kernel memory during the 1055 * reboot before the driver initializes. 1056 */ 1057 return (fxp_suspend(dev)); 1058 } 1059 1060 /* 1061 * Device suspend routine. Stop the interface and save some PCI 1062 * settings in case the BIOS doesn't restore them properly on 1063 * resume. 1064 */ 1065 static int 1066 fxp_suspend(device_t dev) 1067 { 1068 struct fxp_softc *sc = device_get_softc(dev); 1069 if_t ifp; 1070 int pmc; 1071 uint16_t pmstat; 1072 1073 FXP_LOCK(sc); 1074 1075 ifp = sc->ifp; 1076 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1077 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1078 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1079 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) { 1080 /* Request PME. */ 1081 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1082 sc->flags |= FXP_FLAG_WOL; 1083 /* Reconfigure hardware to accept magic frames. */ 1084 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1085 fxp_init_body(sc, 0); 1086 } 1087 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1088 } 1089 fxp_stop(sc); 1090 1091 sc->suspended = 1; 1092 1093 FXP_UNLOCK(sc); 1094 return (0); 1095 } 1096 1097 /* 1098 * Device resume routine. re-enable busmastering, and restart the interface if 1099 * appropriate. 1100 */ 1101 static int 1102 fxp_resume(device_t dev) 1103 { 1104 struct fxp_softc *sc = device_get_softc(dev); 1105 if_t ifp = sc->ifp; 1106 int pmc; 1107 uint16_t pmstat; 1108 1109 FXP_LOCK(sc); 1110 1111 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1112 sc->flags &= ~FXP_FLAG_WOL; 1113 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1114 /* Disable PME and clear PME status. */ 1115 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1116 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1117 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) 1118 CSR_WRITE_1(sc, FXP_CSR_PMDR, 1119 CSR_READ_1(sc, FXP_CSR_PMDR)); 1120 } 1121 1122 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1123 DELAY(10); 1124 1125 /* reinitialize interface if necessary */ 1126 if (if_getflags(ifp) & IFF_UP) 1127 fxp_init_body(sc, 1); 1128 1129 sc->suspended = 0; 1130 1131 FXP_UNLOCK(sc); 1132 return (0); 1133 } 1134 1135 static void 1136 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1137 { 1138 uint16_t reg; 1139 int x; 1140 1141 /* 1142 * Shift in data. 1143 */ 1144 for (x = 1 << (length - 1); x; x >>= 1) { 1145 if (data & x) 1146 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1147 else 1148 reg = FXP_EEPROM_EECS; 1149 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1150 DELAY(1); 1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1152 DELAY(1); 1153 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1154 DELAY(1); 1155 } 1156 } 1157 1158 /* 1159 * Read from the serial EEPROM. Basically, you manually shift in 1160 * the read opcode (one bit at a time) and then shift in the address, 1161 * and then you shift out the data (all of this one bit at a time). 1162 * The word size is 16 bits, so you have to provide the address for 1163 * every 16 bits of data. 1164 */ 1165 static uint16_t 1166 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1167 { 1168 uint16_t reg, data; 1169 int x; 1170 1171 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1172 /* 1173 * Shift in read opcode. 1174 */ 1175 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1176 /* 1177 * Shift in address. 1178 */ 1179 data = 0; 1180 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1181 if (offset & x) 1182 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1183 else 1184 reg = FXP_EEPROM_EECS; 1185 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1186 DELAY(1); 1187 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1188 DELAY(1); 1189 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1190 DELAY(1); 1191 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1192 data++; 1193 if (autosize && reg == 0) { 1194 sc->eeprom_size = data; 1195 break; 1196 } 1197 } 1198 /* 1199 * Shift out data. 1200 */ 1201 data = 0; 1202 reg = FXP_EEPROM_EECS; 1203 for (x = 1 << 15; x; x >>= 1) { 1204 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1205 DELAY(1); 1206 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1207 data |= x; 1208 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1209 DELAY(1); 1210 } 1211 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1212 DELAY(1); 1213 1214 return (data); 1215 } 1216 1217 static void 1218 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1219 { 1220 int i; 1221 1222 /* 1223 * Erase/write enable. 1224 */ 1225 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1226 fxp_eeprom_shiftin(sc, 0x4, 3); 1227 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1228 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1229 DELAY(1); 1230 /* 1231 * Shift in write opcode, address, data. 1232 */ 1233 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1234 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1235 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1236 fxp_eeprom_shiftin(sc, data, 16); 1237 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1238 DELAY(1); 1239 /* 1240 * Wait for EEPROM to finish up. 1241 */ 1242 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1243 DELAY(1); 1244 for (i = 0; i < 1000; i++) { 1245 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1246 break; 1247 DELAY(50); 1248 } 1249 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1250 DELAY(1); 1251 /* 1252 * Erase/write disable. 1253 */ 1254 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1255 fxp_eeprom_shiftin(sc, 0x4, 3); 1256 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1257 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1258 DELAY(1); 1259 } 1260 1261 /* 1262 * From NetBSD: 1263 * 1264 * Figure out EEPROM size. 1265 * 1266 * 559's can have either 64-word or 256-word EEPROMs, the 558 1267 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1268 * talks about the existence of 16 to 256 word EEPROMs. 1269 * 1270 * The only known sizes are 64 and 256, where the 256 version is used 1271 * by CardBus cards to store CIS information. 1272 * 1273 * The address is shifted in msb-to-lsb, and after the last 1274 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1275 * after which follows the actual data. We try to detect this zero, by 1276 * probing the data-out bit in the EEPROM control register just after 1277 * having shifted in a bit. If the bit is zero, we assume we've 1278 * shifted enough address bits. The data-out should be tri-state, 1279 * before this, which should translate to a logical one. 1280 */ 1281 static void 1282 fxp_autosize_eeprom(struct fxp_softc *sc) 1283 { 1284 1285 /* guess maximum size of 256 words */ 1286 sc->eeprom_size = 8; 1287 1288 /* autosize */ 1289 (void) fxp_eeprom_getword(sc, 0, 1); 1290 } 1291 1292 static void 1293 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1294 { 1295 int i; 1296 1297 for (i = 0; i < words; i++) 1298 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1299 } 1300 1301 static void 1302 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1303 { 1304 int i; 1305 1306 for (i = 0; i < words; i++) 1307 fxp_eeprom_putword(sc, offset + i, data[i]); 1308 } 1309 1310 static void 1311 fxp_load_eeprom(struct fxp_softc *sc) 1312 { 1313 int i; 1314 uint16_t cksum; 1315 1316 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size); 1317 cksum = 0; 1318 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) 1319 cksum += sc->eeprom[i]; 1320 cksum = 0xBABA - cksum; 1321 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1]) 1322 device_printf(sc->dev, 1323 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n", 1324 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]); 1325 } 1326 1327 /* 1328 * Grab the softc lock and call the real fxp_start_body() routine 1329 */ 1330 static void 1331 fxp_start(if_t ifp) 1332 { 1333 struct fxp_softc *sc = if_getsoftc(ifp); 1334 1335 FXP_LOCK(sc); 1336 fxp_start_body(ifp); 1337 FXP_UNLOCK(sc); 1338 } 1339 1340 /* 1341 * Start packet transmission on the interface. 1342 * This routine must be called with the softc lock held, and is an 1343 * internal entry point only. 1344 */ 1345 static void 1346 fxp_start_body(if_t ifp) 1347 { 1348 struct fxp_softc *sc = if_getsoftc(ifp); 1349 struct mbuf *mb_head; 1350 int txqueued; 1351 1352 FXP_LOCK_ASSERT(sc, MA_OWNED); 1353 1354 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1355 IFF_DRV_RUNNING) 1356 return; 1357 1358 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1359 fxp_txeof(sc); 1360 /* 1361 * We're finished if there is nothing more to add to the list or if 1362 * we're all filled up with buffers to transmit. 1363 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1364 * a NOP command when needed. 1365 */ 1366 txqueued = 0; 1367 while (!if_sendq_empty(ifp) && sc->tx_queued < FXP_NTXCB - 1) { 1368 1369 /* 1370 * Grab a packet to transmit. 1371 */ 1372 mb_head = if_dequeue(ifp); 1373 if (mb_head == NULL) 1374 break; 1375 1376 if (fxp_encap(sc, &mb_head)) { 1377 if (mb_head == NULL) 1378 break; 1379 if_sendq_prepend(ifp, mb_head); 1380 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1381 } 1382 txqueued++; 1383 /* 1384 * Pass packet to bpf if there is a listener. 1385 */ 1386 if_bpfmtap(ifp, mb_head); 1387 } 1388 1389 /* 1390 * We're finished. If we added to the list, issue a RESUME to get DMA 1391 * going again if suspended. 1392 */ 1393 if (txqueued > 0) { 1394 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1395 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1396 fxp_scb_wait(sc); 1397 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1398 /* 1399 * Set a 5 second timer just in case we don't hear 1400 * from the card again. 1401 */ 1402 sc->watchdog_timer = 5; 1403 } 1404 } 1405 1406 static int 1407 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1408 { 1409 if_t ifp; 1410 struct mbuf *m; 1411 struct fxp_tx *txp; 1412 struct fxp_cb_tx *cbp; 1413 struct tcphdr *tcp; 1414 bus_dma_segment_t segs[FXP_NTXSEG]; 1415 int error, i, nseg, tcp_payload; 1416 1417 FXP_LOCK_ASSERT(sc, MA_OWNED); 1418 ifp = sc->ifp; 1419 1420 tcp_payload = 0; 1421 tcp = NULL; 1422 /* 1423 * Get pointer to next available tx desc. 1424 */ 1425 txp = sc->fxp_desc.tx_last->tx_next; 1426 1427 /* 1428 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1429 * Ethernet Controller Family Open Source Software 1430 * Developer Manual says: 1431 * Using software parsing is only allowed with legal 1432 * TCP/IP or UDP/IP packets. 1433 * ... 1434 * For all other datagrams, hardware parsing must 1435 * be used. 1436 * Software parsing appears to truncate ICMP and 1437 * fragmented UDP packets that contain one to three 1438 * bytes in the second (and final) mbuf of the packet. 1439 */ 1440 if (sc->flags & FXP_FLAG_EXT_RFA) 1441 txp->tx_cb->ipcb_ip_activation_high = 1442 FXP_IPCB_HARDWAREPARSING_ENABLE; 1443 1444 m = *m_head; 1445 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1446 /* 1447 * 82550/82551 requires ethernet/IP/TCP headers must be 1448 * contained in the first active transmit buffer. 1449 */ 1450 struct ether_header *eh; 1451 struct ip *ip; 1452 uint32_t ip_off, poff; 1453 1454 if (M_WRITABLE(*m_head) == 0) { 1455 /* Get a writable copy. */ 1456 m = m_dup(*m_head, M_NOWAIT); 1457 m_freem(*m_head); 1458 if (m == NULL) { 1459 *m_head = NULL; 1460 return (ENOBUFS); 1461 } 1462 *m_head = m; 1463 } 1464 ip_off = sizeof(struct ether_header); 1465 m = m_pullup(*m_head, ip_off); 1466 if (m == NULL) { 1467 *m_head = NULL; 1468 return (ENOBUFS); 1469 } 1470 eh = mtod(m, struct ether_header *); 1471 /* Check the existence of VLAN tag. */ 1472 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1473 ip_off = sizeof(struct ether_vlan_header); 1474 m = m_pullup(m, ip_off); 1475 if (m == NULL) { 1476 *m_head = NULL; 1477 return (ENOBUFS); 1478 } 1479 } 1480 m = m_pullup(m, ip_off + sizeof(struct ip)); 1481 if (m == NULL) { 1482 *m_head = NULL; 1483 return (ENOBUFS); 1484 } 1485 ip = (struct ip *)(mtod(m, char *) + ip_off); 1486 poff = ip_off + (ip->ip_hl << 2); 1487 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1488 if (m == NULL) { 1489 *m_head = NULL; 1490 return (ENOBUFS); 1491 } 1492 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1493 m = m_pullup(m, poff + (tcp->th_off << 2)); 1494 if (m == NULL) { 1495 *m_head = NULL; 1496 return (ENOBUFS); 1497 } 1498 1499 /* 1500 * Since 82550/82551 doesn't modify IP length and pseudo 1501 * checksum in the first frame driver should compute it. 1502 */ 1503 ip = (struct ip *)(mtod(m, char *) + ip_off); 1504 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1505 ip->ip_sum = 0; 1506 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) + 1507 (tcp->th_off << 2)); 1508 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1509 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1510 m->m_pkthdr.tso_segsz)); 1511 /* Compute total TCP payload. */ 1512 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1513 tcp_payload -= tcp->th_off << 2; 1514 *m_head = m; 1515 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1516 /* 1517 * Deal with TCP/IP checksum offload. Note that 1518 * in order for TCP checksum offload to work, 1519 * the pseudo header checksum must have already 1520 * been computed and stored in the checksum field 1521 * in the TCP header. The stack should have 1522 * already done this for us. 1523 */ 1524 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1525 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1526 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1527 1528 #ifdef FXP_IP_CSUM_WAR 1529 /* 1530 * XXX The 82550 chip appears to have trouble 1531 * dealing with IP header checksums in very small 1532 * datagrams, namely fragments from 1 to 3 bytes 1533 * in size. For example, say you want to transmit 1534 * a UDP packet of 1473 bytes. The packet will be 1535 * fragmented over two IP datagrams, the latter 1536 * containing only one byte of data. The 82550 will 1537 * botch the header checksum on the 1-byte fragment. 1538 * As long as the datagram contains 4 or more bytes 1539 * of data, you're ok. 1540 * 1541 * The following code attempts to work around this 1542 * problem: if the datagram is less than 38 bytes 1543 * in size (14 bytes ether header, 20 bytes IP header, 1544 * plus 4 bytes of data), we punt and compute the IP 1545 * header checksum by hand. This workaround doesn't 1546 * work very well, however, since it can be fooled 1547 * by things like VLAN tags and IP options that make 1548 * the header sizes/offsets vary. 1549 */ 1550 1551 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1552 if (m->m_pkthdr.len < 38) { 1553 struct ip *ip; 1554 m->m_data += ETHER_HDR_LEN; 1555 ip = mtod(m, struct ip *); 1556 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1557 m->m_data -= ETHER_HDR_LEN; 1558 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1559 } else { 1560 txp->tx_cb->ipcb_ip_activation_high = 1561 FXP_IPCB_HARDWAREPARSING_ENABLE; 1562 txp->tx_cb->ipcb_ip_schedule |= 1563 FXP_IPCB_IP_CHECKSUM_ENABLE; 1564 } 1565 } 1566 #endif 1567 } 1568 1569 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head, 1570 segs, &nseg, 0); 1571 if (error == EFBIG) { 1572 m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg); 1573 if (m == NULL) { 1574 m_freem(*m_head); 1575 *m_head = NULL; 1576 return (ENOMEM); 1577 } 1578 *m_head = m; 1579 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, 1580 *m_head, segs, &nseg, 0); 1581 if (error != 0) { 1582 m_freem(*m_head); 1583 *m_head = NULL; 1584 return (ENOMEM); 1585 } 1586 } else if (error != 0) 1587 return (error); 1588 if (nseg == 0) { 1589 m_freem(*m_head); 1590 *m_head = NULL; 1591 return (EIO); 1592 } 1593 1594 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1595 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1596 1597 cbp = txp->tx_cb; 1598 for (i = 0; i < nseg; i++) { 1599 /* 1600 * If this is an 82550/82551, then we're using extended 1601 * TxCBs _and_ we're using checksum offload. This means 1602 * that the TxCB is really an IPCB. One major difference 1603 * between the two is that with plain extended TxCBs, 1604 * the bottom half of the TxCB contains two entries from 1605 * the TBD array, whereas IPCBs contain just one entry: 1606 * one entry (8 bytes) has been sacrificed for the TCP/IP 1607 * checksum offload control bits. So to make things work 1608 * right, we have to start filling in the TBD array 1609 * starting from a different place depending on whether 1610 * the chip is an 82550/82551 or not. 1611 */ 1612 if (sc->flags & FXP_FLAG_EXT_RFA) { 1613 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1614 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1615 } else { 1616 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1617 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1618 } 1619 } 1620 if (sc->flags & FXP_FLAG_EXT_RFA) { 1621 /* Configure dynamic TBD for 82550/82551. */ 1622 cbp->tbd_number = 0xFF; 1623 cbp->tbd[nseg].tb_size |= htole32(0x8000); 1624 } else 1625 cbp->tbd_number = nseg; 1626 /* Configure TSO. */ 1627 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1628 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1629 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16); 1630 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1631 FXP_IPCB_IP_CHECKSUM_ENABLE | 1632 FXP_IPCB_TCP_PACKET | 1633 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1634 } 1635 /* Configure VLAN hardware tag insertion. */ 1636 if ((m->m_flags & M_VLANTAG) != 0) { 1637 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); 1638 txp->tx_cb->ipcb_ip_activation_high |= 1639 FXP_IPCB_INSERTVLAN_ENABLE; 1640 } 1641 1642 txp->tx_mbuf = m; 1643 txp->tx_cb->cb_status = 0; 1644 txp->tx_cb->byte_count = 0; 1645 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1646 txp->tx_cb->cb_command = 1647 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1648 FXP_CB_COMMAND_S); 1649 else 1650 txp->tx_cb->cb_command = 1651 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1652 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1653 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1654 txp->tx_cb->tx_threshold = tx_threshold; 1655 1656 /* 1657 * Advance the end of list forward. 1658 */ 1659 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1660 sc->fxp_desc.tx_last = txp; 1661 1662 /* 1663 * Advance the beginning of the list forward if there are 1664 * no other packets queued (when nothing is queued, tx_first 1665 * sits on the last TxCB that was sent out). 1666 */ 1667 if (sc->tx_queued == 0) 1668 sc->fxp_desc.tx_first = txp; 1669 1670 sc->tx_queued++; 1671 1672 return (0); 1673 } 1674 1675 #ifdef DEVICE_POLLING 1676 static poll_handler_t fxp_poll; 1677 1678 static int 1679 fxp_poll(if_t ifp, enum poll_cmd cmd, int count) 1680 { 1681 struct fxp_softc *sc = if_getsoftc(ifp); 1682 uint8_t statack; 1683 int rx_npkts = 0; 1684 1685 FXP_LOCK(sc); 1686 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 1687 FXP_UNLOCK(sc); 1688 return (rx_npkts); 1689 } 1690 1691 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1692 FXP_SCB_STATACK_FR; 1693 if (cmd == POLL_AND_CHECK_STATUS) { 1694 uint8_t tmp; 1695 1696 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1697 if (tmp == 0xff || tmp == 0) { 1698 FXP_UNLOCK(sc); 1699 return (rx_npkts); /* nothing to do */ 1700 } 1701 tmp &= ~statack; 1702 /* ack what we can */ 1703 if (tmp != 0) 1704 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1705 statack |= tmp; 1706 } 1707 rx_npkts = fxp_intr_body(sc, ifp, statack, count); 1708 FXP_UNLOCK(sc); 1709 return (rx_npkts); 1710 } 1711 #endif /* DEVICE_POLLING */ 1712 1713 /* 1714 * Process interface interrupts. 1715 */ 1716 static void 1717 fxp_intr(void *xsc) 1718 { 1719 struct fxp_softc *sc = xsc; 1720 if_t ifp = sc->ifp; 1721 uint8_t statack; 1722 1723 FXP_LOCK(sc); 1724 if (sc->suspended) { 1725 FXP_UNLOCK(sc); 1726 return; 1727 } 1728 1729 #ifdef DEVICE_POLLING 1730 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1731 FXP_UNLOCK(sc); 1732 return; 1733 } 1734 #endif 1735 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1736 /* 1737 * It should not be possible to have all bits set; the 1738 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1739 * all bits are set, this may indicate that the card has 1740 * been physically ejected, so ignore it. 1741 */ 1742 if (statack == 0xff) { 1743 FXP_UNLOCK(sc); 1744 return; 1745 } 1746 1747 /* 1748 * First ACK all the interrupts in this pass. 1749 */ 1750 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1751 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1752 fxp_intr_body(sc, ifp, statack, -1); 1753 } 1754 FXP_UNLOCK(sc); 1755 } 1756 1757 static void 1758 fxp_txeof(struct fxp_softc *sc) 1759 { 1760 if_t ifp; 1761 struct fxp_tx *txp; 1762 1763 ifp = sc->ifp; 1764 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1765 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1766 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1767 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1768 txp = txp->tx_next) { 1769 if (txp->tx_mbuf != NULL) { 1770 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 1771 BUS_DMASYNC_POSTWRITE); 1772 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 1773 m_freem(txp->tx_mbuf); 1774 txp->tx_mbuf = NULL; 1775 /* clear this to reset csum offload bits */ 1776 txp->tx_cb->tbd[0].tb_addr = 0; 1777 } 1778 sc->tx_queued--; 1779 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1780 } 1781 sc->fxp_desc.tx_first = txp; 1782 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1783 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1784 if (sc->tx_queued == 0) 1785 sc->watchdog_timer = 0; 1786 } 1787 1788 static void 1789 fxp_rxcsum(struct fxp_softc *sc, if_t ifp, struct mbuf *m, 1790 uint16_t status, int pos) 1791 { 1792 struct ether_header *eh; 1793 struct ip *ip; 1794 struct udphdr *uh; 1795 int32_t hlen, len, pktlen, temp32; 1796 uint16_t csum, *opts; 1797 1798 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1799 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1800 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1801 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1802 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1803 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1804 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1805 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1806 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1807 CSUM_PSEUDO_HDR; 1808 m->m_pkthdr.csum_data = 0xffff; 1809 } 1810 } 1811 return; 1812 } 1813 1814 pktlen = m->m_pkthdr.len; 1815 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1816 return; 1817 eh = mtod(m, struct ether_header *); 1818 if (eh->ether_type != htons(ETHERTYPE_IP)) 1819 return; 1820 ip = (struct ip *)(eh + 1); 1821 if (ip->ip_v != IPVERSION) 1822 return; 1823 1824 hlen = ip->ip_hl << 2; 1825 pktlen -= sizeof(struct ether_header); 1826 if (hlen < sizeof(struct ip)) 1827 return; 1828 if (ntohs(ip->ip_len) < hlen) 1829 return; 1830 if (ntohs(ip->ip_len) != pktlen) 1831 return; 1832 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1833 return; /* can't handle fragmented packet */ 1834 1835 switch (ip->ip_p) { 1836 case IPPROTO_TCP: 1837 if (pktlen < (hlen + sizeof(struct tcphdr))) 1838 return; 1839 break; 1840 case IPPROTO_UDP: 1841 if (pktlen < (hlen + sizeof(struct udphdr))) 1842 return; 1843 uh = (struct udphdr *)((caddr_t)ip + hlen); 1844 if (uh->uh_sum == 0) 1845 return; /* no checksum */ 1846 break; 1847 default: 1848 return; 1849 } 1850 /* Extract computed checksum. */ 1851 csum = be16dec(mtod(m, char *) + pos); 1852 /* checksum fixup for IP options */ 1853 len = hlen - sizeof(struct ip); 1854 if (len > 0) { 1855 opts = (uint16_t *)(ip + 1); 1856 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1857 temp32 = csum - *opts; 1858 temp32 = (temp32 >> 16) + (temp32 & 65535); 1859 csum = temp32 & 65535; 1860 } 1861 } 1862 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1863 m->m_pkthdr.csum_data = csum; 1864 } 1865 1866 static int 1867 fxp_intr_body(struct fxp_softc *sc, if_t ifp, uint8_t statack, 1868 int count) 1869 { 1870 struct mbuf *m; 1871 struct fxp_rx *rxp; 1872 struct fxp_rfa *rfa; 1873 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1874 int rx_npkts; 1875 uint16_t status; 1876 1877 rx_npkts = 0; 1878 FXP_LOCK_ASSERT(sc, MA_OWNED); 1879 1880 if (rnr) 1881 sc->rnr++; 1882 #ifdef DEVICE_POLLING 1883 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1884 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1885 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1886 rnr = 1; 1887 } 1888 #endif 1889 1890 /* 1891 * Free any finished transmit mbuf chains. 1892 * 1893 * Handle the CNA event likt a CXTNO event. It used to 1894 * be that this event (control unit not ready) was not 1895 * encountered, but it is now with the SMPng modifications. 1896 * The exact sequence of events that occur when the interface 1897 * is brought up are different now, and if this event 1898 * goes unhandled, the configuration/rxfilter setup sequence 1899 * can stall for several seconds. The result is that no 1900 * packets go out onto the wire for about 5 to 10 seconds 1901 * after the interface is ifconfig'ed for the first time. 1902 */ 1903 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1904 fxp_txeof(sc); 1905 1906 /* 1907 * Try to start more packets transmitting. 1908 */ 1909 if (!if_sendq_empty(ifp)) 1910 fxp_start_body(ifp); 1911 1912 /* 1913 * Just return if nothing happened on the receive side. 1914 */ 1915 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1916 return (rx_npkts); 1917 1918 /* 1919 * Process receiver interrupts. If a no-resource (RNR) 1920 * condition exists, get whatever packets we can and 1921 * re-start the receiver. 1922 * 1923 * When using polling, we do not process the list to completion, 1924 * so when we get an RNR interrupt we must defer the restart 1925 * until we hit the last buffer with the C bit set. 1926 * If we run out of cycles and rfa_headm has the C bit set, 1927 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1928 * that the info will be used in the subsequent polling cycle. 1929 */ 1930 for (;;) { 1931 rxp = sc->fxp_desc.rx_head; 1932 m = rxp->rx_mbuf; 1933 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1934 RFA_ALIGNMENT_FUDGE); 1935 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 1936 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1937 1938 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1939 if (count >= 0 && count-- == 0) { 1940 if (rnr) { 1941 /* Defer RNR processing until the next time. */ 1942 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1943 rnr = 0; 1944 } 1945 break; 1946 } 1947 #endif /* DEVICE_POLLING */ 1948 1949 status = le16toh(rfa->rfa_status); 1950 if ((status & FXP_RFA_STATUS_C) == 0) 1951 break; 1952 1953 if ((status & FXP_RFA_STATUS_RNR) != 0) 1954 rnr++; 1955 /* 1956 * Advance head forward. 1957 */ 1958 sc->fxp_desc.rx_head = rxp->rx_next; 1959 1960 /* 1961 * Add a new buffer to the receive chain. 1962 * If this fails, the old buffer is recycled 1963 * instead. 1964 */ 1965 if (fxp_new_rfabuf(sc, rxp) == 0) { 1966 int total_len; 1967 1968 /* 1969 * Fetch packet length (the top 2 bits of 1970 * actual_size are flags set by the controller 1971 * upon completion), and drop the packet in case 1972 * of bogus length or CRC errors. 1973 */ 1974 total_len = le16toh(rfa->actual_size) & 0x3fff; 1975 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1976 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 1977 /* Adjust for appended checksum bytes. */ 1978 total_len -= 2; 1979 } 1980 if (total_len < (int)sizeof(struct ether_header) || 1981 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE - 1982 sc->rfa_size) || 1983 status & (FXP_RFA_STATUS_CRC | 1984 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) { 1985 m_freem(m); 1986 fxp_add_rfabuf(sc, rxp); 1987 continue; 1988 } 1989 1990 m->m_pkthdr.len = m->m_len = total_len; 1991 if_setrcvif(m, ifp); 1992 1993 /* Do IP checksum checking. */ 1994 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1995 fxp_rxcsum(sc, ifp, m, status, total_len); 1996 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 1997 (status & FXP_RFA_STATUS_VLAN) != 0) { 1998 m->m_pkthdr.ether_vtag = 1999 ntohs(rfa->rfax_vlan_id); 2000 m->m_flags |= M_VLANTAG; 2001 } 2002 /* 2003 * Drop locks before calling if_input() since it 2004 * may re-enter fxp_start() in the netisr case. 2005 * This would result in a lock reversal. Better 2006 * performance might be obtained by chaining all 2007 * packets received, dropping the lock, and then 2008 * calling if_input() on each one. 2009 */ 2010 FXP_UNLOCK(sc); 2011 if_input(ifp, m); 2012 FXP_LOCK(sc); 2013 rx_npkts++; 2014 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2015 return (rx_npkts); 2016 } else { 2017 /* Reuse RFA and loaded DMA map. */ 2018 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2019 fxp_discard_rfabuf(sc, rxp); 2020 } 2021 fxp_add_rfabuf(sc, rxp); 2022 } 2023 if (rnr) { 2024 fxp_scb_wait(sc); 2025 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 2026 sc->fxp_desc.rx_head->rx_addr); 2027 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2028 } 2029 return (rx_npkts); 2030 } 2031 2032 static void 2033 fxp_update_stats(struct fxp_softc *sc) 2034 { 2035 if_t ifp = sc->ifp; 2036 struct fxp_stats *sp = sc->fxp_stats; 2037 struct fxp_hwstats *hsp; 2038 uint32_t *status; 2039 2040 FXP_LOCK_ASSERT(sc, MA_OWNED); 2041 2042 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2043 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2044 /* Update statistical counters. */ 2045 if (sc->revision >= FXP_REV_82559_A0) 2046 status = &sp->completion_status; 2047 else if (sc->revision >= FXP_REV_82558_A4) 2048 status = (uint32_t *)&sp->tx_tco; 2049 else 2050 status = &sp->tx_pause; 2051 if (*status == htole32(FXP_STATS_DR_COMPLETE)) { 2052 hsp = &sc->fxp_hwstats; 2053 hsp->tx_good += le32toh(sp->tx_good); 2054 hsp->tx_maxcols += le32toh(sp->tx_maxcols); 2055 hsp->tx_latecols += le32toh(sp->tx_latecols); 2056 hsp->tx_underruns += le32toh(sp->tx_underruns); 2057 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs); 2058 hsp->tx_deffered += le32toh(sp->tx_deffered); 2059 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions); 2060 hsp->tx_multiple_collisions += 2061 le32toh(sp->tx_multiple_collisions); 2062 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions); 2063 hsp->rx_good += le32toh(sp->rx_good); 2064 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors); 2065 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors); 2066 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors); 2067 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors); 2068 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors); 2069 hsp->rx_shortframes += le32toh(sp->rx_shortframes); 2070 hsp->tx_pause += le32toh(sp->tx_pause); 2071 hsp->rx_pause += le32toh(sp->rx_pause); 2072 hsp->rx_controls += le32toh(sp->rx_controls); 2073 hsp->tx_tco += le16toh(sp->tx_tco); 2074 hsp->rx_tco += le16toh(sp->rx_tco); 2075 2076 if_inc_counter(ifp, IFCOUNTER_OPACKETS, le32toh(sp->tx_good)); 2077 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2078 le32toh(sp->tx_total_collisions)); 2079 if (sp->rx_good) { 2080 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 2081 le32toh(sp->rx_good)); 2082 sc->rx_idle_secs = 0; 2083 } else if (sc->flags & FXP_FLAG_RXBUG) { 2084 /* 2085 * Receiver's been idle for another second. 2086 */ 2087 sc->rx_idle_secs++; 2088 } 2089 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2090 le32toh(sp->rx_crc_errors) + 2091 le32toh(sp->rx_alignment_errors) + 2092 le32toh(sp->rx_rnr_errors) + 2093 le32toh(sp->rx_overrun_errors)); 2094 /* 2095 * If any transmit underruns occurred, bump up the transmit 2096 * threshold by another 512 bytes (64 * 8). 2097 */ 2098 if (sp->tx_underruns) { 2099 if_inc_counter(ifp, IFCOUNTER_OERRORS, 2100 le32toh(sp->tx_underruns)); 2101 if (tx_threshold < 192) 2102 tx_threshold += 64; 2103 } 2104 *status = 0; 2105 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2106 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2107 } 2108 } 2109 2110 /* 2111 * Update packet in/out/collision statistics. The i82557 doesn't 2112 * allow you to access these counters without doing a fairly 2113 * expensive DMA to get _all_ of the statistics it maintains, so 2114 * we do this operation here only once per second. The statistics 2115 * counters in the kernel are updated from the previous dump-stats 2116 * DMA and then a new dump-stats DMA is started. The on-chip 2117 * counters are zeroed when the DMA completes. If we can't start 2118 * the DMA immediately, we don't wait - we just prepare to read 2119 * them again next time. 2120 */ 2121 static void 2122 fxp_tick(void *xsc) 2123 { 2124 struct fxp_softc *sc = xsc; 2125 if_t ifp = sc->ifp; 2126 2127 FXP_LOCK_ASSERT(sc, MA_OWNED); 2128 2129 /* Update statistical counters. */ 2130 fxp_update_stats(sc); 2131 2132 /* 2133 * Release any xmit buffers that have completed DMA. This isn't 2134 * strictly necessary to do here, but it's advantagous for mbufs 2135 * with external storage to be released in a timely manner rather 2136 * than being defered for a potentially long time. This limits 2137 * the delay to a maximum of one second. 2138 */ 2139 fxp_txeof(sc); 2140 2141 /* 2142 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2143 * then assume the receiver has locked up and attempt to clear 2144 * the condition by reprogramming the multicast filter. This is 2145 * a work-around for a bug in the 82557 where the receiver locks 2146 * up if it gets certain types of garbage in the synchronization 2147 * bits prior to the packet header. This bug is supposed to only 2148 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2149 * mode as well (perhaps due to a 10/100 speed transition). 2150 */ 2151 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2152 sc->rx_idle_secs = 0; 2153 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2154 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2155 fxp_init_body(sc, 1); 2156 } 2157 return; 2158 } 2159 /* 2160 * If there is no pending command, start another stats 2161 * dump. Otherwise punt for now. 2162 */ 2163 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2164 /* 2165 * Start another stats dump. 2166 */ 2167 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2168 } 2169 if (sc->miibus != NULL) 2170 mii_tick(device_get_softc(sc->miibus)); 2171 2172 /* 2173 * Check that chip hasn't hung. 2174 */ 2175 fxp_watchdog(sc); 2176 2177 /* 2178 * Schedule another timeout one second from now. 2179 */ 2180 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2181 } 2182 2183 /* 2184 * Stop the interface. Cancels the statistics updater and resets 2185 * the interface. 2186 */ 2187 static void 2188 fxp_stop(struct fxp_softc *sc) 2189 { 2190 if_t ifp = sc->ifp; 2191 struct fxp_tx *txp; 2192 int i; 2193 2194 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2195 sc->watchdog_timer = 0; 2196 2197 /* 2198 * Cancel stats updater. 2199 */ 2200 callout_stop(&sc->stat_ch); 2201 2202 /* 2203 * Preserve PCI configuration, configure, IA/multicast 2204 * setup and put RU and CU into idle state. 2205 */ 2206 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2207 DELAY(50); 2208 /* Disable interrupts. */ 2209 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2210 2211 fxp_update_stats(sc); 2212 2213 /* 2214 * Release any xmit buffers. 2215 */ 2216 txp = sc->fxp_desc.tx_list; 2217 for (i = 0; i < FXP_NTXCB; i++) { 2218 if (txp[i].tx_mbuf != NULL) { 2219 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map, 2220 BUS_DMASYNC_POSTWRITE); 2221 bus_dmamap_unload(sc->fxp_txmtag, txp[i].tx_map); 2222 m_freem(txp[i].tx_mbuf); 2223 txp[i].tx_mbuf = NULL; 2224 /* clear this to reset csum offload bits */ 2225 txp[i].tx_cb->tbd[0].tb_addr = 0; 2226 } 2227 } 2228 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2229 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2230 sc->tx_queued = 0; 2231 } 2232 2233 /* 2234 * Watchdog/transmission transmit timeout handler. Called when a 2235 * transmission is started on the interface, but no interrupt is 2236 * received before the timeout. This usually indicates that the 2237 * card has wedged for some reason. 2238 */ 2239 static void 2240 fxp_watchdog(struct fxp_softc *sc) 2241 { 2242 if_t ifp = sc->ifp; 2243 2244 FXP_LOCK_ASSERT(sc, MA_OWNED); 2245 2246 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2247 return; 2248 2249 device_printf(sc->dev, "device timeout\n"); 2250 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2251 2252 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2253 fxp_init_body(sc, 1); 2254 } 2255 2256 /* 2257 * Acquire locks and then call the real initialization function. This 2258 * is necessary because ether_ioctl() calls if_init() and this would 2259 * result in mutex recursion if the mutex was held. 2260 */ 2261 static void 2262 fxp_init(void *xsc) 2263 { 2264 struct fxp_softc *sc = xsc; 2265 2266 FXP_LOCK(sc); 2267 fxp_init_body(sc, 1); 2268 FXP_UNLOCK(sc); 2269 } 2270 2271 /* 2272 * Perform device initialization. This routine must be called with the 2273 * softc lock held. 2274 */ 2275 static void 2276 fxp_init_body(struct fxp_softc *sc, int setmedia) 2277 { 2278 if_t ifp = sc->ifp; 2279 struct mii_data *mii; 2280 struct fxp_cb_config *cbp; 2281 struct fxp_cb_ias *cb_ias; 2282 struct fxp_cb_tx *tcbp; 2283 struct fxp_tx *txp; 2284 int i, prm; 2285 2286 FXP_LOCK_ASSERT(sc, MA_OWNED); 2287 2288 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2289 return; 2290 2291 /* 2292 * Cancel any pending I/O 2293 */ 2294 fxp_stop(sc); 2295 2296 /* 2297 * Issue software reset, which also unloads the microcode. 2298 */ 2299 sc->flags &= ~FXP_FLAG_UCODE; 2300 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2301 DELAY(50); 2302 2303 prm = (if_getflags(ifp) & IFF_PROMISC) ? 1 : 0; 2304 2305 /* 2306 * Initialize base of CBL and RFA memory. Loading with zero 2307 * sets it up for regular linear addressing. 2308 */ 2309 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2310 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2311 2312 fxp_scb_wait(sc); 2313 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2314 2315 /* 2316 * Initialize base of dump-stats buffer. 2317 */ 2318 fxp_scb_wait(sc); 2319 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 2320 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2321 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2322 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2323 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2324 2325 /* 2326 * Attempt to load microcode if requested. 2327 * For ICH based controllers do not load microcode. 2328 */ 2329 if (sc->ident->ich == 0) { 2330 if (if_getflags(ifp) & IFF_LINK0 && 2331 (sc->flags & FXP_FLAG_UCODE) == 0) 2332 fxp_load_ucode(sc); 2333 } 2334 2335 /* 2336 * Set IFF_ALLMULTI status. It's needed in configure action 2337 * command. 2338 */ 2339 fxp_mc_addrs(sc); 2340 2341 /* 2342 * We temporarily use memory that contains the TxCB list to 2343 * construct the config CB. The TxCB list memory is rebuilt 2344 * later. 2345 */ 2346 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2347 2348 /* 2349 * This bcopy is kind of disgusting, but there are a bunch of must be 2350 * zero and must be one bits in this structure and this is the easiest 2351 * way to initialize them all to proper values. 2352 */ 2353 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2354 2355 cbp->cb_status = 0; 2356 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2357 FXP_CB_COMMAND_EL); 2358 cbp->link_addr = 0xffffffff; /* (no) next command */ 2359 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2360 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2361 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2362 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2363 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2364 cbp->type_enable = 0; /* actually reserved */ 2365 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2366 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2367 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2368 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2369 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2370 cbp->late_scb = 0; /* (don't) defer SCB update */ 2371 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2372 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2373 cbp->ci_int = 1; /* interrupt on CU idle */ 2374 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2375 cbp->ext_stats_dis = 1; /* disable extended counters */ 2376 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2377 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2378 cbp->disc_short_rx = !prm; /* discard short packets */ 2379 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2380 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2381 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2382 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2383 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2384 cbp->csma_dis = 0; /* (don't) disable link */ 2385 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2386 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) ? 1 : 0; 2387 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2388 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2389 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2390 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2391 cbp->nsai = 1; /* (don't) disable source addr insert */ 2392 cbp->preamble_length = 2; /* (7 byte) preamble */ 2393 cbp->loopback = 0; /* (don't) loopback */ 2394 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2395 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2396 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2397 cbp->promiscuous = prm; /* promiscuous mode */ 2398 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2399 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2400 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2401 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2402 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2403 2404 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2405 cbp->padding = 1; /* (do) pad short tx packets */ 2406 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2407 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2408 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2409 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2410 cbp->force_fdx = 0; /* (don't) force full duplex */ 2411 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2412 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2413 cbp->mc_all = if_getflags(ifp) & IFF_ALLMULTI ? 1 : prm; 2414 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2415 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && 2416 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; 2417 2418 if (sc->revision == FXP_REV_82557) { 2419 /* 2420 * The 82557 has no hardware flow control, the values 2421 * below are the defaults for the chip. 2422 */ 2423 cbp->fc_delay_lsb = 0; 2424 cbp->fc_delay_msb = 0x40; 2425 cbp->pri_fc_thresh = 3; 2426 cbp->tx_fc_dis = 0; 2427 cbp->rx_fc_restop = 0; 2428 cbp->rx_fc_restart = 0; 2429 cbp->fc_filter = 0; 2430 cbp->pri_fc_loc = 1; 2431 } else { 2432 /* Set pause RX FIFO threshold to 1KB. */ 2433 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1); 2434 /* Set pause time. */ 2435 cbp->fc_delay_lsb = 0xff; 2436 cbp->fc_delay_msb = 0xff; 2437 cbp->pri_fc_thresh = 3; 2438 mii = device_get_softc(sc->miibus); 2439 if ((IFM_OPTIONS(mii->mii_media_active) & 2440 IFM_ETH_TXPAUSE) != 0) 2441 /* enable transmit FC */ 2442 cbp->tx_fc_dis = 0; 2443 else 2444 /* disable transmit FC */ 2445 cbp->tx_fc_dis = 1; 2446 if ((IFM_OPTIONS(mii->mii_media_active) & 2447 IFM_ETH_RXPAUSE) != 0) { 2448 /* enable FC restart/restop frames */ 2449 cbp->rx_fc_restart = 1; 2450 cbp->rx_fc_restop = 1; 2451 } else { 2452 /* disable FC restart/restop frames */ 2453 cbp->rx_fc_restart = 0; 2454 cbp->rx_fc_restop = 0; 2455 } 2456 cbp->fc_filter = !prm; /* drop FC frames to host */ 2457 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2458 } 2459 2460 /* Enable 82558 and 82559 extended statistics functionality. */ 2461 if (sc->revision >= FXP_REV_82558_A4) { 2462 if (sc->revision >= FXP_REV_82559_A0) { 2463 /* 2464 * Extend configuration table size to 32 2465 * to include TCO configuration. 2466 */ 2467 cbp->byte_count = 32; 2468 cbp->ext_stats_dis = 1; 2469 /* Enable TCO stats. */ 2470 cbp->tno_int_or_tco_en = 1; 2471 cbp->gamla_rx = 1; 2472 } else 2473 cbp->ext_stats_dis = 0; 2474 } 2475 2476 /* 2477 * Start the config command/DMA. 2478 */ 2479 fxp_scb_wait(sc); 2480 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2481 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2482 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2483 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2484 /* ...and wait for it to complete. */ 2485 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2486 2487 /* 2488 * Now initialize the station address. Temporarily use the TxCB 2489 * memory area like we did above for the config CB. 2490 */ 2491 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2492 cb_ias->cb_status = 0; 2493 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2494 cb_ias->link_addr = 0xffffffff; 2495 bcopy(if_getlladdr(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2496 2497 /* 2498 * Start the IAS (Individual Address Setup) command/DMA. 2499 */ 2500 fxp_scb_wait(sc); 2501 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2502 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2503 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2504 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2505 /* ...and wait for it to complete. */ 2506 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2507 2508 /* 2509 * Initialize the multicast address list. 2510 */ 2511 fxp_mc_setup(sc); 2512 2513 /* 2514 * Initialize transmit control block (TxCB) list. 2515 */ 2516 txp = sc->fxp_desc.tx_list; 2517 tcbp = sc->fxp_desc.cbl_list; 2518 bzero(tcbp, FXP_TXCB_SZ); 2519 for (i = 0; i < FXP_NTXCB; i++) { 2520 txp[i].tx_mbuf = NULL; 2521 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2522 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2523 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2524 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2525 if (sc->flags & FXP_FLAG_EXT_TXCB) 2526 tcbp[i].tbd_array_addr = 2527 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2528 else 2529 tcbp[i].tbd_array_addr = 2530 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2531 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2532 } 2533 /* 2534 * Set the suspend flag on the first TxCB and start the control 2535 * unit. It will execute the NOP and then suspend. 2536 */ 2537 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2538 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2539 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2540 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2541 sc->tx_queued = 1; 2542 2543 fxp_scb_wait(sc); 2544 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2545 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2546 2547 /* 2548 * Initialize receiver buffer area - RFA. 2549 */ 2550 fxp_scb_wait(sc); 2551 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2552 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2553 2554 if (sc->miibus != NULL && setmedia != 0) 2555 mii_mediachg(device_get_softc(sc->miibus)); 2556 2557 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2558 2559 /* 2560 * Enable interrupts. 2561 */ 2562 #ifdef DEVICE_POLLING 2563 /* 2564 * ... but only do that if we are not polling. And because (presumably) 2565 * the default is interrupts on, we need to disable them explicitly! 2566 */ 2567 if (if_getcapenable(ifp) & IFCAP_POLLING ) 2568 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2569 else 2570 #endif /* DEVICE_POLLING */ 2571 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2572 2573 /* 2574 * Start stats updater. 2575 */ 2576 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2577 } 2578 2579 static int 2580 fxp_serial_ifmedia_upd(if_t ifp) 2581 { 2582 2583 return (0); 2584 } 2585 2586 static void 2587 fxp_serial_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2588 { 2589 2590 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2591 } 2592 2593 /* 2594 * Change media according to request. 2595 */ 2596 static int 2597 fxp_ifmedia_upd(if_t ifp) 2598 { 2599 struct fxp_softc *sc = if_getsoftc(ifp); 2600 struct mii_data *mii; 2601 struct mii_softc *miisc; 2602 2603 mii = device_get_softc(sc->miibus); 2604 FXP_LOCK(sc); 2605 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2606 PHY_RESET(miisc); 2607 mii_mediachg(mii); 2608 FXP_UNLOCK(sc); 2609 return (0); 2610 } 2611 2612 /* 2613 * Notify the world which media we're using. 2614 */ 2615 static void 2616 fxp_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2617 { 2618 struct fxp_softc *sc = if_getsoftc(ifp); 2619 struct mii_data *mii; 2620 2621 mii = device_get_softc(sc->miibus); 2622 FXP_LOCK(sc); 2623 mii_pollstat(mii); 2624 ifmr->ifm_active = mii->mii_media_active; 2625 ifmr->ifm_status = mii->mii_media_status; 2626 FXP_UNLOCK(sc); 2627 } 2628 2629 /* 2630 * Add a buffer to the end of the RFA buffer list. 2631 * Return 0 if successful, 1 for failure. A failure results in 2632 * reusing the RFA buffer. 2633 * The RFA struct is stuck at the beginning of mbuf cluster and the 2634 * data pointer is fixed up to point just past it. 2635 */ 2636 static int 2637 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2638 { 2639 struct mbuf *m; 2640 struct fxp_rfa *rfa; 2641 bus_dmamap_t tmp_map; 2642 int error; 2643 2644 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2645 if (m == NULL) 2646 return (ENOBUFS); 2647 2648 /* 2649 * Move the data pointer up so that the incoming data packet 2650 * will be 32-bit aligned. 2651 */ 2652 m->m_data += RFA_ALIGNMENT_FUDGE; 2653 2654 /* 2655 * Get a pointer to the base of the mbuf cluster and move 2656 * data start past it. 2657 */ 2658 rfa = mtod(m, struct fxp_rfa *); 2659 m->m_data += sc->rfa_size; 2660 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2661 2662 rfa->rfa_status = 0; 2663 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2664 rfa->actual_size = 0; 2665 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2666 sc->rfa_size; 2667 2668 /* 2669 * Initialize the rest of the RFA. Note that since the RFA 2670 * is misaligned, we cannot store values directly. We're thus 2671 * using the le32enc() function which handles endianness and 2672 * is also alignment-safe. 2673 */ 2674 le32enc(&rfa->link_addr, 0xffffffff); 2675 le32enc(&rfa->rbd_addr, 0xffffffff); 2676 2677 /* Map the RFA into DMA memory. */ 2678 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa, 2679 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2680 &rxp->rx_addr, BUS_DMA_NOWAIT); 2681 if (error) { 2682 m_freem(m); 2683 return (error); 2684 } 2685 2686 if (rxp->rx_mbuf != NULL) 2687 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 2688 tmp_map = sc->spare_map; 2689 sc->spare_map = rxp->rx_map; 2690 rxp->rx_map = tmp_map; 2691 rxp->rx_mbuf = m; 2692 2693 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2694 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2695 return (0); 2696 } 2697 2698 static void 2699 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2700 { 2701 struct fxp_rfa *p_rfa; 2702 struct fxp_rx *p_rx; 2703 2704 /* 2705 * If there are other buffers already on the list, attach this 2706 * one to the end by fixing up the tail to point to this one. 2707 */ 2708 if (sc->fxp_desc.rx_head != NULL) { 2709 p_rx = sc->fxp_desc.rx_tail; 2710 p_rfa = (struct fxp_rfa *) 2711 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2712 p_rx->rx_next = rxp; 2713 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2714 p_rfa->rfa_control = 0; 2715 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map, 2716 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2717 } else { 2718 rxp->rx_next = NULL; 2719 sc->fxp_desc.rx_head = rxp; 2720 } 2721 sc->fxp_desc.rx_tail = rxp; 2722 } 2723 2724 static void 2725 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2726 { 2727 struct mbuf *m; 2728 struct fxp_rfa *rfa; 2729 2730 m = rxp->rx_mbuf; 2731 m->m_data = m->m_ext.ext_buf; 2732 /* 2733 * Move the data pointer up so that the incoming data packet 2734 * will be 32-bit aligned. 2735 */ 2736 m->m_data += RFA_ALIGNMENT_FUDGE; 2737 2738 /* 2739 * Get a pointer to the base of the mbuf cluster and move 2740 * data start past it. 2741 */ 2742 rfa = mtod(m, struct fxp_rfa *); 2743 m->m_data += sc->rfa_size; 2744 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2745 2746 rfa->rfa_status = 0; 2747 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2748 rfa->actual_size = 0; 2749 2750 /* 2751 * Initialize the rest of the RFA. Note that since the RFA 2752 * is misaligned, we cannot store values directly. We're thus 2753 * using the le32enc() function which handles endianness and 2754 * is also alignment-safe. 2755 */ 2756 le32enc(&rfa->link_addr, 0xffffffff); 2757 le32enc(&rfa->rbd_addr, 0xffffffff); 2758 2759 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2760 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2761 } 2762 2763 static int 2764 fxp_miibus_readreg(device_t dev, int phy, int reg) 2765 { 2766 struct fxp_softc *sc = device_get_softc(dev); 2767 int count = 10000; 2768 int value; 2769 2770 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2771 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2772 2773 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2774 && count--) 2775 DELAY(10); 2776 2777 if (count <= 0) 2778 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2779 2780 return (value & 0xffff); 2781 } 2782 2783 static int 2784 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2785 { 2786 struct fxp_softc *sc = device_get_softc(dev); 2787 int count = 10000; 2788 2789 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2790 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2791 (value & 0xffff)); 2792 2793 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2794 count--) 2795 DELAY(10); 2796 2797 if (count <= 0) 2798 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2799 return (0); 2800 } 2801 2802 static void 2803 fxp_miibus_statchg(device_t dev) 2804 { 2805 struct fxp_softc *sc; 2806 struct mii_data *mii; 2807 if_t ifp; 2808 2809 sc = device_get_softc(dev); 2810 mii = device_get_softc(sc->miibus); 2811 ifp = sc->ifp; 2812 if (mii == NULL || ifp == (void *)NULL || 2813 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || 2814 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) != 2815 (IFM_AVALID | IFM_ACTIVE)) 2816 return; 2817 2818 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T && 2819 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2820 sc->cu_resume_bug = 1; 2821 else 2822 sc->cu_resume_bug = 0; 2823 /* 2824 * Call fxp_init_body in order to adjust the flow control settings. 2825 * Note that the 82557 doesn't support hardware flow control. 2826 */ 2827 if (sc->revision == FXP_REV_82557) 2828 return; 2829 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2830 fxp_init_body(sc, 0); 2831 } 2832 2833 static int 2834 fxp_ioctl(if_t ifp, u_long command, caddr_t data) 2835 { 2836 struct fxp_softc *sc = if_getsoftc(ifp); 2837 struct ifreq *ifr = (struct ifreq *)data; 2838 struct mii_data *mii; 2839 int flag, mask, error = 0, reinit; 2840 2841 switch (command) { 2842 case SIOCSIFFLAGS: 2843 FXP_LOCK(sc); 2844 /* 2845 * If interface is marked up and not running, then start it. 2846 * If it is marked down and running, stop it. 2847 * XXX If it's up then re-initialize it. This is so flags 2848 * such as IFF_PROMISC are handled. 2849 */ 2850 if (if_getflags(ifp) & IFF_UP) { 2851 if (((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) && 2852 ((if_getflags(ifp) ^ sc->if_flags) & 2853 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) { 2854 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2855 fxp_init_body(sc, 0); 2856 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2857 fxp_init_body(sc, 1); 2858 } else { 2859 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2860 fxp_stop(sc); 2861 } 2862 sc->if_flags = if_getflags(ifp); 2863 FXP_UNLOCK(sc); 2864 break; 2865 2866 case SIOCADDMULTI: 2867 case SIOCDELMULTI: 2868 FXP_LOCK(sc); 2869 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2870 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2871 fxp_init_body(sc, 0); 2872 } 2873 FXP_UNLOCK(sc); 2874 break; 2875 2876 case SIOCSIFMEDIA: 2877 case SIOCGIFMEDIA: 2878 if (sc->miibus != NULL) { 2879 mii = device_get_softc(sc->miibus); 2880 error = ifmedia_ioctl(ifp, ifr, 2881 &mii->mii_media, command); 2882 } else { 2883 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2884 } 2885 break; 2886 2887 case SIOCSIFCAP: 2888 reinit = 0; 2889 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap; 2890 #ifdef DEVICE_POLLING 2891 if (mask & IFCAP_POLLING) { 2892 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2893 error = ether_poll_register(fxp_poll, ifp); 2894 if (error) 2895 return(error); 2896 FXP_LOCK(sc); 2897 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2898 FXP_SCB_INTR_DISABLE); 2899 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 2900 FXP_UNLOCK(sc); 2901 } else { 2902 error = ether_poll_deregister(ifp); 2903 /* Enable interrupts in any case */ 2904 FXP_LOCK(sc); 2905 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2906 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 2907 FXP_UNLOCK(sc); 2908 } 2909 } 2910 #endif 2911 FXP_LOCK(sc); 2912 if ((mask & IFCAP_TXCSUM) != 0 && 2913 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 2914 if_togglecapenable(ifp, IFCAP_TXCSUM); 2915 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2916 if_sethwassistbits(ifp, FXP_CSUM_FEATURES, 0); 2917 else 2918 if_sethwassistbits(ifp, 0, FXP_CSUM_FEATURES); 2919 } 2920 if ((mask & IFCAP_RXCSUM) != 0 && 2921 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 2922 if_togglecapenable(ifp, IFCAP_RXCSUM); 2923 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2924 reinit++; 2925 } 2926 if ((mask & IFCAP_TSO4) != 0 && 2927 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 2928 if_togglecapenable(ifp, IFCAP_TSO4); 2929 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 2930 if_sethwassistbits(ifp, CSUM_TSO, 0); 2931 else 2932 if_sethwassistbits(ifp, 0, CSUM_TSO); 2933 } 2934 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2935 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2936 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2937 if ((mask & IFCAP_VLAN_MTU) != 0 && 2938 (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) != 0) { 2939 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 2940 if (sc->revision != FXP_REV_82557) 2941 flag = FXP_FLAG_LONG_PKT_EN; 2942 else /* a hack to get long frames on the old chip */ 2943 flag = FXP_FLAG_SAVE_BAD; 2944 sc->flags ^= flag; 2945 if (if_getflags(ifp) & IFF_UP) 2946 reinit++; 2947 } 2948 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2949 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2950 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2951 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2952 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2953 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2954 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2955 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2956 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2957 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2958 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO | 2959 IFCAP_VLAN_HWCSUM); 2960 reinit++; 2961 } 2962 if (reinit > 0 && 2963 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2964 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2965 fxp_init_body(sc, 0); 2966 } 2967 FXP_UNLOCK(sc); 2968 if_vlancap(ifp); 2969 break; 2970 2971 default: 2972 error = ether_ioctl(ifp, command, data); 2973 } 2974 return (error); 2975 } 2976 2977 /* 2978 * Fill in the multicast address list and return number of entries. 2979 */ 2980 static int 2981 fxp_mc_addrs(struct fxp_softc *sc) 2982 { 2983 struct fxp_cb_mcs *mcsp = sc->mcsp; 2984 if_t ifp = sc->ifp; 2985 int nmcasts = 0; 2986 2987 if ((if_getflags(ifp) & IFF_ALLMULTI) == 0) { 2988 if_maddr_rlock(ifp); 2989 if_setupmultiaddr(ifp, mcsp->mc_addr, &nmcasts, MAXMCADDR); 2990 if (nmcasts >= MAXMCADDR) { 2991 if_setflagbits(ifp, IFF_ALLMULTI, 0); 2992 nmcasts = 0; 2993 } 2994 if_maddr_runlock(ifp); 2995 } 2996 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2997 return (nmcasts); 2998 } 2999 3000 /* 3001 * Program the multicast filter. 3002 * 3003 * We have an artificial restriction that the multicast setup command 3004 * must be the first command in the chain, so we take steps to ensure 3005 * this. By requiring this, it allows us to keep up the performance of 3006 * the pre-initialized command ring (esp. link pointers) by not actually 3007 * inserting the mcsetup command in the ring - i.e. its link pointer 3008 * points to the TxCB ring, but the mcsetup descriptor itself is not part 3009 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 3010 * lead into the regular TxCB ring when it completes. 3011 */ 3012 static void 3013 fxp_mc_setup(struct fxp_softc *sc) 3014 { 3015 struct fxp_cb_mcs *mcsp; 3016 int count; 3017 3018 FXP_LOCK_ASSERT(sc, MA_OWNED); 3019 3020 mcsp = sc->mcsp; 3021 mcsp->cb_status = 0; 3022 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 3023 mcsp->link_addr = 0xffffffff; 3024 fxp_mc_addrs(sc); 3025 3026 /* 3027 * Wait until command unit is idle. This should never be the 3028 * case when nothing is queued, but make sure anyway. 3029 */ 3030 count = 100; 3031 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) != 3032 FXP_SCB_CUS_IDLE && --count) 3033 DELAY(10); 3034 if (count == 0) { 3035 device_printf(sc->dev, "command queue timeout\n"); 3036 return; 3037 } 3038 3039 /* 3040 * Start the multicast setup command. 3041 */ 3042 fxp_scb_wait(sc); 3043 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 3044 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3045 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 3046 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3047 /* ...and wait for it to complete. */ 3048 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 3049 } 3050 3051 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 3052 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 3053 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 3054 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 3055 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 3056 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 3057 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 3058 3059 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 3060 3061 static const struct ucode { 3062 uint32_t revision; 3063 uint32_t *ucode; 3064 int length; 3065 u_short int_delay_offset; 3066 u_short bundle_max_offset; 3067 } ucode_table[] = { 3068 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 3069 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 3070 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 3071 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 3072 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 3073 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 3074 { FXP_REV_82550, UCODE(fxp_ucode_d102), 3075 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 3076 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 3077 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 3078 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 3079 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3080 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e), 3081 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3082 { 0, NULL, 0, 0, 0 } 3083 }; 3084 3085 static void 3086 fxp_load_ucode(struct fxp_softc *sc) 3087 { 3088 const struct ucode *uc; 3089 struct fxp_cb_ucode *cbp; 3090 int i; 3091 3092 if (sc->flags & FXP_FLAG_NO_UCODE) 3093 return; 3094 3095 for (uc = ucode_table; uc->ucode != NULL; uc++) 3096 if (sc->revision == uc->revision) 3097 break; 3098 if (uc->ucode == NULL) 3099 return; 3100 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 3101 cbp->cb_status = 0; 3102 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 3103 cbp->link_addr = 0xffffffff; /* (no) next command */ 3104 for (i = 0; i < uc->length; i++) 3105 cbp->ucode[i] = htole32(uc->ucode[i]); 3106 if (uc->int_delay_offset) 3107 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 3108 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 3109 if (uc->bundle_max_offset) 3110 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 3111 htole16(sc->tunable_bundle_max); 3112 /* 3113 * Download the ucode to the chip. 3114 */ 3115 fxp_scb_wait(sc); 3116 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 3117 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3118 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 3119 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3120 /* ...and wait for it to complete. */ 3121 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 3122 device_printf(sc->dev, 3123 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 3124 sc->tunable_int_delay, 3125 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 3126 sc->flags |= FXP_FLAG_UCODE; 3127 bzero(cbp, FXP_TXCB_SZ); 3128 } 3129 3130 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \ 3131 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 3132 3133 static void 3134 fxp_sysctl_node(struct fxp_softc *sc) 3135 { 3136 struct sysctl_ctx_list *ctx; 3137 struct sysctl_oid_list *child, *parent; 3138 struct sysctl_oid *tree; 3139 struct fxp_hwstats *hsp; 3140 3141 ctx = device_get_sysctl_ctx(sc->dev); 3142 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3143 3144 SYSCTL_ADD_PROC(ctx, child, 3145 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 3146 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 3147 "FXP driver receive interrupt microcode bundling delay"); 3148 SYSCTL_ADD_PROC(ctx, child, 3149 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 3150 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 3151 "FXP driver receive interrupt microcode bundle size limit"); 3152 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 3153 "FXP RNR events"); 3154 3155 /* 3156 * Pull in device tunables. 3157 */ 3158 sc->tunable_int_delay = TUNABLE_INT_DELAY; 3159 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 3160 (void) resource_int_value(device_get_name(sc->dev), 3161 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay); 3162 (void) resource_int_value(device_get_name(sc->dev), 3163 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max); 3164 sc->rnr = 0; 3165 3166 hsp = &sc->fxp_hwstats; 3167 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 3168 NULL, "FXP statistics"); 3169 parent = SYSCTL_CHILDREN(tree); 3170 3171 /* Rx MAC statistics. */ 3172 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 3173 NULL, "Rx MAC statistics"); 3174 child = SYSCTL_CHILDREN(tree); 3175 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3176 &hsp->rx_good, "Good frames"); 3177 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors", 3178 &hsp->rx_crc_errors, "CRC errors"); 3179 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors", 3180 &hsp->rx_alignment_errors, "Alignment errors"); 3181 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors", 3182 &hsp->rx_rnr_errors, "RNR errors"); 3183 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors", 3184 &hsp->rx_overrun_errors, "Overrun errors"); 3185 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors", 3186 &hsp->rx_cdt_errors, "Collision detect errors"); 3187 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes", 3188 &hsp->rx_shortframes, "Short frame errors"); 3189 if (sc->revision >= FXP_REV_82558_A4) { 3190 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3191 &hsp->rx_pause, "Pause frames"); 3192 FXP_SYSCTL_STAT_ADD(ctx, child, "controls", 3193 &hsp->rx_controls, "Unsupported control frames"); 3194 } 3195 if (sc->revision >= FXP_REV_82559_A0) 3196 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3197 &hsp->rx_tco, "TCO frames"); 3198 3199 /* Tx MAC statistics. */ 3200 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 3201 NULL, "Tx MAC statistics"); 3202 child = SYSCTL_CHILDREN(tree); 3203 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3204 &hsp->tx_good, "Good frames"); 3205 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols", 3206 &hsp->tx_maxcols, "Maximum collisions errors"); 3207 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols", 3208 &hsp->tx_latecols, "Late collisions errors"); 3209 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns", 3210 &hsp->tx_underruns, "Underrun errors"); 3211 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs", 3212 &hsp->tx_lostcrs, "Lost carrier sense"); 3213 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered", 3214 &hsp->tx_deffered, "Deferred"); 3215 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions", 3216 &hsp->tx_single_collisions, "Single collisions"); 3217 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions", 3218 &hsp->tx_multiple_collisions, "Multiple collisions"); 3219 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions", 3220 &hsp->tx_total_collisions, "Total collisions"); 3221 if (sc->revision >= FXP_REV_82558_A4) 3222 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3223 &hsp->tx_pause, "Pause frames"); 3224 if (sc->revision >= FXP_REV_82559_A0) 3225 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3226 &hsp->tx_tco, "TCO frames"); 3227 } 3228 3229 #undef FXP_SYSCTL_STAT_ADD 3230 3231 static int 3232 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3233 { 3234 int error, value; 3235 3236 value = *(int *)arg1; 3237 error = sysctl_handle_int(oidp, &value, 0, req); 3238 if (error || !req->newptr) 3239 return (error); 3240 if (value < low || value > high) 3241 return (EINVAL); 3242 *(int *)arg1 = value; 3243 return (0); 3244 } 3245 3246 /* 3247 * Interrupt delay is expressed in microseconds, a multiplier is used 3248 * to convert this to the appropriate clock ticks before using. 3249 */ 3250 static int 3251 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3252 { 3253 3254 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3255 } 3256 3257 static int 3258 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3259 { 3260 3261 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3262 } 3263