1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011-2012 Stefan Bethke. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/bus.h> 31 #include <sys/errno.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/socket.h> 35 #include <sys/sockio.h> 36 #include <sys/sysctl.h> 37 #include <sys/systm.h> 38 39 #include <net/if.h> 40 #include <net/if_arp.h> 41 #include <net/ethernet.h> 42 #include <net/if_dl.h> 43 #include <net/if_media.h> 44 #include <net/if_types.h> 45 46 #include <machine/bus.h> 47 #include <dev/iicbus/iic.h> 48 #include <dev/iicbus/iiconf.h> 49 #include <dev/iicbus/iicbus.h> 50 #include <dev/mii/mii.h> 51 #include <dev/mii/miivar.h> 52 #include <dev/mdio/mdio.h> 53 54 #include <dev/etherswitch/etherswitch.h> 55 56 #include <dev/etherswitch/arswitch/arswitchreg.h> 57 #include <dev/etherswitch/arswitch/arswitchvar.h> 58 #include <dev/etherswitch/arswitch/arswitch_reg.h> 59 60 #include "mdio_if.h" 61 #include "miibus_if.h" 62 #include "etherswitch_if.h" 63 64 static inline void 65 arswitch_split_setpage(device_t dev, uint32_t addr, uint16_t *phy, 66 uint16_t *reg) 67 { 68 struct arswitch_softc *sc = device_get_softc(dev); 69 uint16_t page; 70 71 page = (addr >> 9) & 0x1ff; 72 *phy = (addr >> 6) & 0x7; 73 *reg = (addr >> 1) & 0x1f; 74 75 if (sc->page != page) { 76 MDIO_WRITEREG(device_get_parent(dev), 0x18, 0, page); 77 DELAY(2000); 78 sc->page = page; 79 } 80 } 81 82 /* 83 * Read half a register. Some of the registers define control bits, and 84 * the sequence of half-word accesses matters. The register addresses 85 * are word-even (mod 4). 86 */ 87 static inline int 88 arswitch_readreg16(device_t dev, int addr) 89 { 90 uint16_t phy, reg; 91 92 arswitch_split_setpage(dev, addr, &phy, ®); 93 return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg)); 94 } 95 96 /* 97 * Write half a register. See above! 98 */ 99 static inline int 100 arswitch_writereg16(device_t dev, int addr, int data) 101 { 102 uint16_t phy, reg; 103 104 arswitch_split_setpage(dev, addr, &phy, ®); 105 return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data)); 106 } 107 108 void 109 arswitch_writedbg(device_t dev, int phy, uint16_t dbg_addr, 110 uint16_t dbg_data) 111 { 112 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 113 MII_ATH_DBG_ADDR, dbg_addr); 114 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 115 MII_ATH_DBG_DATA, dbg_data); 116 } 117 118 void 119 arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr, 120 uint16_t dbg_data) 121 { 122 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 123 MII_ATH_MMD_ADDR, dbg_addr); 124 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 125 MII_ATH_MMD_DATA, dbg_data); 126 } 127 128 static uint32_t 129 arswitch_reg_read32(device_t dev, int phy, int reg) 130 { 131 uint16_t lo, hi; 132 lo = MDIO_READREG(device_get_parent(dev), phy, reg); 133 hi = MDIO_READREG(device_get_parent(dev), phy, reg + 1); 134 135 return (hi << 16) | lo; 136 } 137 138 static int 139 arswitch_reg_write32(device_t dev, int phy, int reg, uint32_t value) 140 { 141 struct arswitch_softc *sc; 142 int r; 143 uint16_t lo, hi; 144 145 sc = device_get_softc(dev); 146 lo = value & 0xffff; 147 hi = (uint16_t) (value >> 16); 148 149 if (sc->mii_lo_first) { 150 r = MDIO_WRITEREG(device_get_parent(dev), 151 phy, reg, lo); 152 r |= MDIO_WRITEREG(device_get_parent(dev), 153 phy, reg + 1, hi); 154 } else { 155 r = MDIO_WRITEREG(device_get_parent(dev), 156 phy, reg + 1, hi); 157 r |= MDIO_WRITEREG(device_get_parent(dev), 158 phy, reg, lo); 159 } 160 161 return r; 162 } 163 164 int 165 arswitch_readreg(device_t dev, int addr) 166 { 167 uint16_t phy, reg; 168 169 arswitch_split_setpage(dev, addr, &phy, ®); 170 return arswitch_reg_read32(dev, 0x10 | phy, reg); 171 } 172 173 int 174 arswitch_writereg(device_t dev, int addr, int value) 175 { 176 uint16_t phy, reg; 177 178 arswitch_split_setpage(dev, addr, &phy, ®); 179 return (arswitch_reg_write32(dev, 0x10 | phy, reg, value)); 180 } 181 182 /* 183 * Read/write 16 bit values in the switch register space. 184 * 185 * Some of the registers are control registers (eg the MDIO 186 * data versus control space) and so need to be treated 187 * differently. 188 */ 189 int 190 arswitch_readreg_lsb(device_t dev, int addr) 191 { 192 193 return (arswitch_readreg16(dev, addr)); 194 } 195 196 int 197 arswitch_readreg_msb(device_t dev, int addr) 198 { 199 200 return (arswitch_readreg16(dev, addr + 2) << 16); 201 } 202 203 int 204 arswitch_writereg_lsb(device_t dev, int addr, int data) 205 { 206 207 return (arswitch_writereg16(dev, addr, data & 0xffff)); 208 } 209 210 int 211 arswitch_writereg_msb(device_t dev, int addr, int data) 212 { 213 214 return (arswitch_writereg16(dev, addr + 2, (data >> 16) & 0xffff)); 215 } 216 217 int 218 arswitch_modifyreg(device_t dev, int addr, int mask, int set) 219 { 220 int value; 221 uint16_t phy, reg; 222 223 ARSWITCH_LOCK_ASSERT((struct arswitch_softc *)device_get_softc(dev), 224 MA_OWNED); 225 226 arswitch_split_setpage(dev, addr, &phy, ®); 227 228 value = arswitch_reg_read32(dev, 0x10 | phy, reg); 229 value &= ~mask; 230 value |= set; 231 return (arswitch_reg_write32(dev, 0x10 | phy, reg, value)); 232 } 233 234 int 235 arswitch_waitreg(device_t dev, int addr, int mask, int val, int timeout) 236 { 237 struct arswitch_softc *sc = device_get_softc(dev); 238 int err, v; 239 uint16_t phy, reg; 240 241 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); 242 243 arswitch_split_setpage(dev, addr, &phy, ®); 244 245 err = -1; 246 while (1) { 247 v = arswitch_reg_read32(dev, 0x10 | phy, reg); 248 v &= mask; 249 if (v == val) { 250 err = 0; 251 break; 252 } 253 if (!timeout) 254 break; 255 DELAY(1); 256 timeout--; 257 } 258 if (err != 0) { 259 DPRINTF(sc, ARSWITCH_DBG_ANY, 260 "%s: waitreg failed; addr=0x%08x, mask=0x%08x, val=0x%08x\n", 261 __func__, addr, mask, val); 262 } 263 return (err); 264 } 265