1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Matthew Macy <mmacy@mattmacy.io> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "if_em.h" 30 31 #ifdef RSS 32 #include <net/rss_config.h> 33 #include <netinet/in_rss.h> 34 #endif 35 36 #ifdef VERBOSE_DEBUG 37 #define DPRINTF device_printf 38 #else 39 #define DPRINTF(...) 40 #endif 41 42 /********************************************************************* 43 * Local Function prototypes 44 *********************************************************************/ 45 static int igb_isc_txd_encap(void *, if_pkt_info_t); 46 static void igb_isc_txd_flush(void *, uint16_t, qidx_t); 47 static int igb_isc_txd_credits_update(void *, uint16_t, bool); 48 49 static void igb_isc_rxd_refill(void *, if_rxd_update_t); 50 51 static void igb_isc_rxd_flush(void *, uint16_t, uint8_t, qidx_t); 52 static int igb_isc_rxd_available(void *, uint16_t, qidx_t, qidx_t); 53 54 static int igb_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri); 55 56 static int igb_tx_ctx_setup(struct tx_ring *, if_pkt_info_t, uint32_t *, 57 uint32_t *); 58 static int igb_tso_setup(struct tx_ring *, if_pkt_info_t, uint32_t *, 59 uint32_t *); 60 61 static void igb_rx_checksum(uint32_t, if_rxd_info_t, uint32_t); 62 static int igb_determine_rsstype(uint16_t); 63 64 extern void igb_if_enable_intr(if_ctx_t); 65 extern int em_intr(void *); 66 67 struct if_txrx igb_txrx = { 68 .ift_txd_encap = igb_isc_txd_encap, 69 .ift_txd_flush = igb_isc_txd_flush, 70 .ift_txd_credits_update = igb_isc_txd_credits_update, 71 .ift_rxd_available = igb_isc_rxd_available, 72 .ift_rxd_pkt_get = igb_isc_rxd_pkt_get, 73 .ift_rxd_refill = igb_isc_rxd_refill, 74 .ift_rxd_flush = igb_isc_rxd_flush, 75 .ift_legacy_intr = em_intr 76 }; 77 78 /********************************************************************** 79 * 80 * Setup work for hardware segmentation offload (TSO) on 81 * adapters using advanced tx descriptors 82 * 83 **********************************************************************/ 84 static int 85 igb_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len, 86 uint32_t *olinfo_status) 87 { 88 struct e1000_adv_tx_context_desc *TXD; 89 struct e1000_softc *sc = txr->sc; 90 uint32_t type_tucmd_mlhl = 0, vlan_macip_lens = 0; 91 uint32_t mss_l4len_idx = 0; 92 uint32_t paylen; 93 94 switch(pi->ipi_etype) { 95 case ETHERTYPE_IPV6: 96 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6; 97 break; 98 case ETHERTYPE_IP: 99 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 100 /* Tell transmit desc to also do IPv4 checksum. */ 101 *olinfo_status |= E1000_TXD_POPTS_IXSM << 8; 102 break; 103 default: 104 panic("%s: CSUM_TSO but no supported IP version (0x%04x)", 105 __func__, ntohs(pi->ipi_etype)); 106 break; 107 } 108 109 TXD = (struct e1000_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 110 111 /* This is used in the transmit desc in encap */ 112 paylen = pi->ipi_len - pi->ipi_ehdrlen - pi->ipi_ip_hlen - pi->ipi_tcp_hlen; 113 114 /* VLAN MACLEN IPLEN */ 115 if (pi->ipi_mflags & M_VLANTAG) { 116 vlan_macip_lens |= (pi->ipi_vtag << E1000_ADVTXD_VLAN_SHIFT); 117 } 118 119 vlan_macip_lens |= pi->ipi_ehdrlen << E1000_ADVTXD_MACLEN_SHIFT; 120 vlan_macip_lens |= pi->ipi_ip_hlen; 121 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 122 123 /* ADV DTYPE TUCMD */ 124 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 125 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 126 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 127 128 /* MSS L4LEN IDX */ 129 mss_l4len_idx |= (pi->ipi_tso_segsz << E1000_ADVTXD_MSS_SHIFT); 130 mss_l4len_idx |= (pi->ipi_tcp_hlen << E1000_ADVTXD_L4LEN_SHIFT); 131 /* 82575 needs the queue index added */ 132 if (sc->hw.mac.type == e1000_82575) 133 mss_l4len_idx |= txr->me << 4; 134 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 135 136 TXD->u.seqnum_seed = htole32(0); 137 *cmd_type_len |= E1000_ADVTXD_DCMD_TSE; 138 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 139 *olinfo_status |= paylen << E1000_ADVTXD_PAYLEN_SHIFT; 140 141 return (1); 142 } 143 144 /********************************************************************* 145 * 146 * Advanced Context Descriptor setup for VLAN, CSUM or TSO 147 * 148 **********************************************************************/ 149 static int 150 igb_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len, 151 uint32_t *olinfo_status) 152 { 153 struct e1000_adv_tx_context_desc *TXD; 154 struct e1000_softc *sc = txr->sc; 155 uint32_t vlan_macip_lens, type_tucmd_mlhl; 156 uint32_t mss_l4len_idx; 157 mss_l4len_idx = vlan_macip_lens = type_tucmd_mlhl = 0; 158 159 /* First check if TSO is to be used */ 160 if (pi->ipi_csum_flags & CSUM_TSO) 161 return (igb_tso_setup(txr, pi, cmd_type_len, olinfo_status)); 162 163 /* Indicate the whole packet as payload when not doing TSO */ 164 *olinfo_status |= pi->ipi_len << E1000_ADVTXD_PAYLEN_SHIFT; 165 166 /* Now ready a context descriptor */ 167 TXD = (struct e1000_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 168 169 /* 170 ** In advanced descriptors the vlan tag must 171 ** be placed into the context descriptor. Hence 172 ** we need to make one even if not doing offloads. 173 */ 174 if (pi->ipi_mflags & M_VLANTAG) { 175 vlan_macip_lens |= (pi->ipi_vtag << E1000_ADVTXD_VLAN_SHIFT); 176 } else if ((pi->ipi_csum_flags & IGB_CSUM_OFFLOAD) == 0) { 177 return (0); 178 } 179 180 /* Set the ether header length */ 181 vlan_macip_lens |= pi->ipi_ehdrlen << E1000_ADVTXD_MACLEN_SHIFT; 182 183 switch(pi->ipi_etype) { 184 case ETHERTYPE_IP: 185 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 186 break; 187 case ETHERTYPE_IPV6: 188 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6; 189 break; 190 default: 191 break; 192 } 193 194 vlan_macip_lens |= pi->ipi_ip_hlen; 195 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 196 197 switch (pi->ipi_ipproto) { 198 case IPPROTO_TCP: 199 if (pi->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP)) { 200 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 201 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 202 } 203 break; 204 case IPPROTO_UDP: 205 if (pi->ipi_csum_flags & (CSUM_IP_UDP | CSUM_IP6_UDP)) { 206 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP; 207 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 208 } 209 break; 210 case IPPROTO_SCTP: 211 if (pi->ipi_csum_flags & (CSUM_IP_SCTP | CSUM_IP6_SCTP)) { 212 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP; 213 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 214 } 215 break; 216 default: 217 break; 218 } 219 220 /* 82575 needs the queue index added */ 221 if (sc->hw.mac.type == e1000_82575) 222 mss_l4len_idx = txr->me << 4; 223 224 /* Now copy bits into descriptor */ 225 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 226 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 227 TXD->u.seqnum_seed = htole32(0); 228 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 229 230 return (1); 231 } 232 233 static int 234 igb_isc_txd_encap(void *arg, if_pkt_info_t pi) 235 { 236 struct e1000_softc *sc = arg; 237 if_softc_ctx_t scctx = sc->shared; 238 struct em_tx_queue *que = &sc->tx_queues[pi->ipi_qsidx]; 239 struct tx_ring *txr = &que->txr; 240 int nsegs = pi->ipi_nsegs; 241 bus_dma_segment_t *segs = pi->ipi_segs; 242 union e1000_adv_tx_desc *txd = NULL; 243 int i, j, pidx_last; 244 uint32_t olinfo_status, cmd_type_len, txd_flags; 245 qidx_t ntxd; 246 247 pidx_last = olinfo_status = 0; 248 /* Basic descriptor defines */ 249 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | 250 E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT); 251 252 if (pi->ipi_mflags & M_VLANTAG) 253 cmd_type_len |= E1000_ADVTXD_DCMD_VLE; 254 255 i = pi->ipi_pidx; 256 ntxd = scctx->isc_ntxd[0]; 257 txd_flags = pi->ipi_flags & IPI_TX_INTR ? E1000_ADVTXD_DCMD_RS : 0; 258 /* Consume the first descriptor */ 259 i += igb_tx_ctx_setup(txr, pi, &cmd_type_len, &olinfo_status); 260 if (i == scctx->isc_ntxd[0]) 261 i = 0; 262 263 /* 82575 needs the queue index added */ 264 if (sc->hw.mac.type == e1000_82575) 265 olinfo_status |= txr->me << 4; 266 267 for (j = 0; j < nsegs; j++) { 268 bus_size_t seglen; 269 bus_addr_t segaddr; 270 271 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i]; 272 seglen = segs[j].ds_len; 273 segaddr = htole64(segs[j].ds_addr); 274 275 txd->read.buffer_addr = segaddr; 276 txd->read.cmd_type_len = htole32(E1000_TXD_CMD_IFCS | 277 cmd_type_len | seglen); 278 txd->read.olinfo_status = htole32(olinfo_status); 279 pidx_last = i; 280 if (++i == scctx->isc_ntxd[0]) { 281 i = 0; 282 } 283 } 284 if (txd_flags) { 285 txr->tx_rsq[txr->tx_rs_pidx] = pidx_last; 286 txr->tx_rs_pidx = (txr->tx_rs_pidx+1) & (ntxd-1); 287 MPASS(txr->tx_rs_pidx != txr->tx_rs_cidx); 288 } 289 290 txd->read.cmd_type_len |= htole32(E1000_TXD_CMD_EOP | txd_flags); 291 pi->ipi_new_pidx = i; 292 293 /* Sent data accounting for AIM */ 294 txr->tx_bytes += pi->ipi_len; 295 ++txr->tx_packets; 296 297 return (0); 298 } 299 300 static void 301 igb_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx) 302 { 303 struct e1000_softc *sc = arg; 304 struct em_tx_queue *que = &sc->tx_queues[txqid]; 305 struct tx_ring *txr = &que->txr; 306 307 E1000_WRITE_REG(&sc->hw, E1000_TDT(txr->me), pidx); 308 } 309 310 static int 311 igb_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear) 312 { 313 struct e1000_softc *sc = arg; 314 if_softc_ctx_t scctx = sc->shared; 315 struct em_tx_queue *que = &sc->tx_queues[txqid]; 316 struct tx_ring *txr = &que->txr; 317 318 qidx_t processed = 0; 319 int updated; 320 qidx_t cur, prev, ntxd, rs_cidx; 321 int32_t delta; 322 uint8_t status; 323 324 rs_cidx = txr->tx_rs_cidx; 325 if (rs_cidx == txr->tx_rs_pidx) 326 return (0); 327 cur = txr->tx_rsq[rs_cidx]; 328 status = ((union e1000_adv_tx_desc *)&txr->tx_base[cur])->wb.status; 329 updated = !!(status & E1000_TXD_STAT_DD); 330 331 if (!updated) 332 return (0); 333 334 /* If clear is false just let caller know that there 335 * are descriptors to reclaim */ 336 if (!clear) 337 return (1); 338 339 prev = txr->tx_cidx_processed; 340 ntxd = scctx->isc_ntxd[0]; 341 do { 342 MPASS(prev != cur); 343 delta = (int32_t)cur - (int32_t)prev; 344 if (delta < 0) 345 delta += ntxd; 346 MPASS(delta > 0); 347 348 processed += delta; 349 prev = cur; 350 rs_cidx = (rs_cidx + 1) & (ntxd-1); 351 if (rs_cidx == txr->tx_rs_pidx) 352 break; 353 cur = txr->tx_rsq[rs_cidx]; 354 status = ((union e1000_adv_tx_desc *)&txr->tx_base[cur])->wb.status; 355 } while ((status & E1000_TXD_STAT_DD)); 356 357 txr->tx_rs_cidx = rs_cidx; 358 txr->tx_cidx_processed = prev; 359 return (processed); 360 } 361 362 static void 363 igb_isc_rxd_refill(void *arg, if_rxd_update_t iru) 364 { 365 struct e1000_softc *sc = arg; 366 if_softc_ctx_t scctx = sc->shared; 367 uint16_t rxqid = iru->iru_qsidx; 368 struct em_rx_queue *que = &sc->rx_queues[rxqid]; 369 union e1000_adv_rx_desc *rxd; 370 struct rx_ring *rxr = &que->rxr; 371 uint64_t *paddrs; 372 uint32_t next_pidx, pidx; 373 uint16_t count; 374 int i; 375 376 paddrs = iru->iru_paddrs; 377 pidx = iru->iru_pidx; 378 count = iru->iru_count; 379 380 for (i = 0, next_pidx = pidx; i < count; i++) { 381 rxd = (union e1000_adv_rx_desc *)&rxr->rx_base[next_pidx]; 382 383 rxd->read.pkt_addr = htole64(paddrs[i]); 384 if (++next_pidx == scctx->isc_nrxd[0]) 385 next_pidx = 0; 386 } 387 } 388 389 static void 390 igb_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, qidx_t pidx) 391 { 392 struct e1000_softc *sc = arg; 393 struct em_rx_queue *que = &sc->rx_queues[rxqid]; 394 struct rx_ring *rxr = &que->rxr; 395 396 E1000_WRITE_REG(&sc->hw, E1000_RDT(rxr->me), pidx); 397 } 398 399 static int 400 igb_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget) 401 { 402 struct e1000_softc *sc = arg; 403 if_softc_ctx_t scctx = sc->shared; 404 struct em_rx_queue *que = &sc->rx_queues[rxqid]; 405 struct rx_ring *rxr = &que->rxr; 406 union e1000_adv_rx_desc *rxd; 407 uint32_t staterr = 0; 408 int cnt, i; 409 410 for (cnt = 0, i = idx; cnt < scctx->isc_nrxd[0] && cnt <= budget;) { 411 rxd = (union e1000_adv_rx_desc *)&rxr->rx_base[i]; 412 staterr = le32toh(rxd->wb.upper.status_error); 413 414 if ((staterr & E1000_RXD_STAT_DD) == 0) 415 break; 416 if (++i == scctx->isc_nrxd[0]) 417 i = 0; 418 if (staterr & E1000_RXD_STAT_EOP) 419 cnt++; 420 } 421 return (cnt); 422 } 423 424 /**************************************************************** 425 * Routine sends data which has been dma'ed into host memory 426 * to upper layer. Initialize ri structure. 427 * 428 * Returns 0 upon success, errno on failure 429 ***************************************************************/ 430 431 static int 432 igb_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri) 433 { 434 struct e1000_softc *sc = arg; 435 if_softc_ctx_t scctx = sc->shared; 436 struct em_rx_queue *que = &sc->rx_queues[ri->iri_qsidx]; 437 struct rx_ring *rxr = &que->rxr; 438 union e1000_adv_rx_desc *rxd; 439 440 uint16_t pkt_info, len; 441 uint32_t ptype, staterr; 442 int i, cidx; 443 bool eop; 444 445 staterr = i = 0; 446 cidx = ri->iri_cidx; 447 448 do { 449 rxd = (union e1000_adv_rx_desc *)&rxr->rx_base[cidx]; 450 staterr = le32toh(rxd->wb.upper.status_error); 451 pkt_info = le16toh(rxd->wb.lower.lo_dword.hs_rss.pkt_info); 452 453 MPASS ((staterr & E1000_RXD_STAT_DD) != 0); 454 455 len = le16toh(rxd->wb.upper.length); 456 ptype = le32toh(rxd->wb.lower.lo_dword.data) & IGB_PKTTYPE_MASK; 457 458 ri->iri_len += len; 459 rxr->rx_bytes += ri->iri_len; 460 461 rxd->wb.upper.status_error = 0; 462 eop = ((staterr & E1000_RXD_STAT_EOP) == E1000_RXD_STAT_EOP); 463 464 /* Make sure bad packets are discarded */ 465 if (eop && ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) != 0)) { 466 sc->dropped_pkts++; 467 ++rxr->rx_discarded; 468 return (EBADMSG); 469 } 470 ri->iri_frags[i].irf_flid = 0; 471 ri->iri_frags[i].irf_idx = cidx; 472 ri->iri_frags[i].irf_len = len; 473 474 if (++cidx == scctx->isc_nrxd[0]) 475 cidx = 0; 476 #ifdef notyet 477 if (rxr->hdr_split == true) { 478 ri->iri_frags[i].irf_flid = 1; 479 ri->iri_frags[i].irf_idx = cidx; 480 if (++cidx == scctx->isc_nrxd[0]) 481 cidx = 0; 482 } 483 #endif 484 i++; 485 } while (!eop); 486 487 rxr->rx_packets++; 488 489 if ((scctx->isc_capenable & IFCAP_RXCSUM) != 0) 490 igb_rx_checksum(staterr, ri, ptype); 491 492 if (staterr & E1000_RXD_STAT_VP) { 493 if (((sc->hw.mac.type == e1000_i350) || 494 (sc->hw.mac.type == e1000_i354)) && 495 (staterr & E1000_RXDEXT_STATERR_LB)) 496 ri->iri_vtag = be16toh(rxd->wb.upper.vlan); 497 else 498 ri->iri_vtag = le16toh(rxd->wb.upper.vlan); 499 ri->iri_flags |= M_VLANTAG; 500 } 501 502 ri->iri_flowid = 503 le32toh(rxd->wb.lower.hi_dword.rss); 504 ri->iri_rsstype = igb_determine_rsstype(pkt_info); 505 ri->iri_nfrags = i; 506 507 return (0); 508 } 509 510 /********************************************************************* 511 * 512 * Verify that the hardware indicated that the checksum is valid. 513 * Inform the stack about the status of checksum so that stack 514 * doesn't spend time verifying the checksum. 515 * 516 *********************************************************************/ 517 static void 518 igb_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype) 519 { 520 uint16_t status = (uint16_t)staterr; 521 uint8_t errors = (uint8_t)(staterr >> 24); 522 523 if (__predict_false(status & E1000_RXD_STAT_IXSM)) 524 return; 525 526 /* If there is a layer 3 or 4 error we are done */ 527 if (__predict_false(errors & (E1000_RXD_ERR_IPE | E1000_RXD_ERR_TCPE))) 528 return; 529 530 /* IP Checksum Good */ 531 if (status & E1000_RXD_STAT_IPCS) 532 ri->iri_csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID); 533 534 /* Valid L4E checksum */ 535 if (__predict_true(status & 536 (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) { 537 /* SCTP header present */ 538 if (__predict_false((ptype & E1000_RXDADV_PKTTYPE_ETQF) == 0 && 539 (ptype & E1000_RXDADV_PKTTYPE_SCTP) != 0)) { 540 ri->iri_csum_flags |= CSUM_SCTP_VALID; 541 } else { 542 ri->iri_csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 543 ri->iri_csum_data = htons(0xffff); 544 } 545 } 546 } 547 548 /******************************************************************** 549 * 550 * Parse the packet type to determine the appropriate hash 551 * 552 ******************************************************************/ 553 static int 554 igb_determine_rsstype(uint16_t pkt_info) 555 { 556 switch (pkt_info & E1000_RXDADV_RSSTYPE_MASK) { 557 case E1000_RXDADV_RSSTYPE_IPV4_TCP: 558 return M_HASHTYPE_RSS_TCP_IPV4; 559 case E1000_RXDADV_RSSTYPE_IPV4: 560 return M_HASHTYPE_RSS_IPV4; 561 case E1000_RXDADV_RSSTYPE_IPV6_TCP: 562 return M_HASHTYPE_RSS_TCP_IPV6; 563 case E1000_RXDADV_RSSTYPE_IPV6_EX: 564 return M_HASHTYPE_RSS_IPV6_EX; 565 case E1000_RXDADV_RSSTYPE_IPV6: 566 return M_HASHTYPE_RSS_IPV6; 567 case E1000_RXDADV_RSSTYPE_IPV6_TCP_EX: 568 return M_HASHTYPE_RSS_TCP_IPV6_EX; 569 default: 570 return M_HASHTYPE_OPAQUE; 571 } 572 } 573