1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 static const char em_driver_version[] = "7.7.8-fbsd"; 41 static const char igb_driver_version[] = "2.5.28-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static const pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 57 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 58 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 61 62 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 63 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 65 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 66 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 68 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 69 70 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 71 72 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 73 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 74 75 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 76 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 78 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 79 80 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 81 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 84 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 85 86 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 88 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 95 96 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 97 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 98 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 99 100 /* Intel(R) - em-class devices */ 101 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 108 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 109 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 113 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 114 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 116 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 117 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 121 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 139 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 140 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 148 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 150 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 152 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 197 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 198 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"), 199 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"), 200 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"), 201 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"), 202 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"), 203 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"), 204 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"), 205 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"), 206 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"), 207 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"), 208 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"), 209 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"), 210 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"), 211 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"), 212 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"), 213 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"), 214 /* required last entry */ 215 PVID_END 216 }; 217 218 static const pci_vendor_info_t igb_vendor_info_array[] = 219 { 220 /* Intel(R) - igb-class devices */ 221 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 222 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 224 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 225 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 226 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 227 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 230 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 231 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 232 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 233 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 234 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 235 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 238 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 239 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 240 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 241 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 242 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 244 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 245 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 246 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 247 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 248 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 249 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 250 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 251 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 252 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 253 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 254 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 255 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 256 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 257 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 258 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 259 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 260 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 261 /* required last entry */ 262 PVID_END 263 }; 264 265 /********************************************************************* 266 * Function prototypes 267 *********************************************************************/ 268 static void *em_register(device_t); 269 static void *igb_register(device_t); 270 static int em_if_attach_pre(if_ctx_t); 271 static int em_if_attach_post(if_ctx_t); 272 static int em_if_detach(if_ctx_t); 273 static int em_if_shutdown(if_ctx_t); 274 static int em_if_suspend(if_ctx_t); 275 static int em_if_resume(if_ctx_t); 276 277 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 278 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 279 static void em_if_queues_free(if_ctx_t); 280 281 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 282 static void em_if_init(if_ctx_t); 283 static void em_if_stop(if_ctx_t); 284 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 285 static int em_if_media_change(if_ctx_t); 286 static int em_if_mtu_set(if_ctx_t, uint32_t); 287 static void em_if_timer(if_ctx_t, uint16_t); 288 static void em_if_vlan_register(if_ctx_t, u16); 289 static void em_if_vlan_unregister(if_ctx_t, u16); 290 static void em_if_watchdog_reset(if_ctx_t); 291 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 292 293 static void em_identify_hardware(if_ctx_t); 294 static int em_allocate_pci_resources(if_ctx_t); 295 static void em_free_pci_resources(if_ctx_t); 296 static void em_reset(if_ctx_t); 297 static int em_setup_interface(if_ctx_t); 298 static int em_setup_msix(if_ctx_t); 299 300 static void em_initialize_transmit_unit(if_ctx_t); 301 static void em_initialize_receive_unit(if_ctx_t); 302 303 static void em_if_intr_enable(if_ctx_t); 304 static void em_if_intr_disable(if_ctx_t); 305 static void igb_if_intr_enable(if_ctx_t); 306 static void igb_if_intr_disable(if_ctx_t); 307 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 308 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 309 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 310 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 311 static void em_if_multi_set(if_ctx_t); 312 static void em_if_update_admin_status(if_ctx_t); 313 static void em_if_debug(if_ctx_t); 314 static void em_update_stats_counters(struct e1000_softc *); 315 static void em_add_hw_stats(struct e1000_softc *); 316 static int em_if_set_promisc(if_ctx_t, int); 317 static bool em_if_vlan_filter_capable(if_ctx_t); 318 static bool em_if_vlan_filter_used(if_ctx_t); 319 static void em_if_vlan_filter_enable(struct e1000_softc *); 320 static void em_if_vlan_filter_disable(struct e1000_softc *); 321 static void em_if_vlan_filter_write(struct e1000_softc *); 322 static void em_setup_vlan_hw_support(if_ctx_t ctx); 323 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 324 static void em_print_nvm_info(struct e1000_softc *); 325 static void em_fw_version_locked(if_ctx_t); 326 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 327 static void em_print_fw_version(struct e1000_softc *); 328 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 329 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 330 static int em_get_rs(SYSCTL_HANDLER_ARGS); 331 static void em_print_debug_info(struct e1000_softc *); 332 static int em_is_valid_ether_addr(u8 *); 333 static void em_newitr(struct e1000_softc *, struct em_rx_queue *, 334 struct tx_ring *, struct rx_ring *); 335 static bool em_automask_tso(if_ctx_t); 336 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 337 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 338 const char *, struct em_int_delay_info *, int, int); 339 /* Management and WOL Support */ 340 static void em_init_manageability(struct e1000_softc *); 341 static void em_release_manageability(struct e1000_softc *); 342 static void em_get_hw_control(struct e1000_softc *); 343 static void em_release_hw_control(struct e1000_softc *); 344 static void em_get_wakeup(if_ctx_t); 345 static void em_enable_wakeup(if_ctx_t); 346 static int em_enable_phy_wakeup(struct e1000_softc *); 347 static void em_disable_aspm(struct e1000_softc *); 348 349 int em_intr(void *); 350 351 /* MSI-X handlers */ 352 static int em_if_msix_intr_assign(if_ctx_t, int); 353 static int em_msix_link(void *); 354 static void em_handle_link(void *); 355 356 static void em_enable_vectors_82574(if_ctx_t); 357 358 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 359 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 360 static int igb_sysctl_dmac(SYSCTL_HANDLER_ARGS); 361 static void em_if_led_func(if_ctx_t, int); 362 363 static int em_get_regs(SYSCTL_HANDLER_ARGS); 364 365 static void lem_smartspeed(struct e1000_softc *); 366 static void igb_configure_queues(struct e1000_softc *); 367 static void em_flush_desc_rings(struct e1000_softc *); 368 369 370 /********************************************************************* 371 * FreeBSD Device Interface Entry Points 372 *********************************************************************/ 373 static device_method_t em_methods[] = { 374 /* Device interface */ 375 DEVMETHOD(device_register, em_register), 376 DEVMETHOD(device_probe, iflib_device_probe), 377 DEVMETHOD(device_attach, iflib_device_attach), 378 DEVMETHOD(device_detach, iflib_device_detach), 379 DEVMETHOD(device_shutdown, iflib_device_shutdown), 380 DEVMETHOD(device_suspend, iflib_device_suspend), 381 DEVMETHOD(device_resume, iflib_device_resume), 382 DEVMETHOD_END 383 }; 384 385 static device_method_t igb_methods[] = { 386 /* Device interface */ 387 DEVMETHOD(device_register, igb_register), 388 DEVMETHOD(device_probe, iflib_device_probe), 389 DEVMETHOD(device_attach, iflib_device_attach), 390 DEVMETHOD(device_detach, iflib_device_detach), 391 DEVMETHOD(device_shutdown, iflib_device_shutdown), 392 DEVMETHOD(device_suspend, iflib_device_suspend), 393 DEVMETHOD(device_resume, iflib_device_resume), 394 DEVMETHOD_END 395 }; 396 397 398 static driver_t em_driver = { 399 "em", em_methods, sizeof(struct e1000_softc), 400 }; 401 402 DRIVER_MODULE(em, pci, em_driver, 0, 0); 403 404 MODULE_DEPEND(em, pci, 1, 1, 1); 405 MODULE_DEPEND(em, ether, 1, 1, 1); 406 MODULE_DEPEND(em, iflib, 1, 1, 1); 407 408 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 409 410 static driver_t igb_driver = { 411 "igb", igb_methods, sizeof(struct e1000_softc), 412 }; 413 414 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 415 416 MODULE_DEPEND(igb, pci, 1, 1, 1); 417 MODULE_DEPEND(igb, ether, 1, 1, 1); 418 MODULE_DEPEND(igb, iflib, 1, 1, 1); 419 420 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 421 422 static device_method_t em_if_methods[] = { 423 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 424 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 425 DEVMETHOD(ifdi_detach, em_if_detach), 426 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 427 DEVMETHOD(ifdi_suspend, em_if_suspend), 428 DEVMETHOD(ifdi_resume, em_if_resume), 429 DEVMETHOD(ifdi_init, em_if_init), 430 DEVMETHOD(ifdi_stop, em_if_stop), 431 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 432 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 433 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 434 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 435 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 436 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 437 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 438 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 439 DEVMETHOD(ifdi_media_status, em_if_media_status), 440 DEVMETHOD(ifdi_media_change, em_if_media_change), 441 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 442 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 443 DEVMETHOD(ifdi_timer, em_if_timer), 444 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 445 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 446 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 447 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 448 DEVMETHOD(ifdi_led_func, em_if_led_func), 449 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 450 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 451 DEVMETHOD(ifdi_debug, em_if_debug), 452 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 453 DEVMETHOD_END 454 }; 455 456 static driver_t em_if_driver = { 457 "em_if", em_if_methods, sizeof(struct e1000_softc) 458 }; 459 460 static device_method_t igb_if_methods[] = { 461 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 462 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 463 DEVMETHOD(ifdi_detach, em_if_detach), 464 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 465 DEVMETHOD(ifdi_suspend, em_if_suspend), 466 DEVMETHOD(ifdi_resume, em_if_resume), 467 DEVMETHOD(ifdi_init, em_if_init), 468 DEVMETHOD(ifdi_stop, em_if_stop), 469 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 470 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 471 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 472 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 473 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 474 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 475 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 476 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 477 DEVMETHOD(ifdi_media_status, em_if_media_status), 478 DEVMETHOD(ifdi_media_change, em_if_media_change), 479 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 480 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 481 DEVMETHOD(ifdi_timer, em_if_timer), 482 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 483 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 484 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 485 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 486 DEVMETHOD(ifdi_led_func, em_if_led_func), 487 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 488 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 489 DEVMETHOD(ifdi_debug, em_if_debug), 490 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 491 DEVMETHOD_END 492 }; 493 494 static driver_t igb_if_driver = { 495 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 496 }; 497 498 /********************************************************************* 499 * Tunable default values. 500 *********************************************************************/ 501 502 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 503 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 504 505 /* Allow common code without TSO */ 506 #ifndef CSUM_TSO 507 #define CSUM_TSO 0 508 #endif 509 510 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 511 "EM driver parameters"); 512 513 static int em_disable_crc_stripping = 0; 514 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 515 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 516 517 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 518 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 519 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 520 0, "Default transmit interrupt delay in usecs"); 521 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 522 0, "Default receive interrupt delay in usecs"); 523 524 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 525 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 526 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 527 &em_tx_abs_int_delay_dflt, 0, 528 "Default transmit interrupt delay limit in usecs"); 529 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 530 &em_rx_abs_int_delay_dflt, 0, 531 "Default receive interrupt delay limit in usecs"); 532 533 static int em_smart_pwr_down = false; 534 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 535 0, "Set to true to leave smart power down enabled on newer adapters"); 536 537 static bool em_unsupported_tso = false; 538 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 539 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 540 541 /* Controls whether promiscuous also shows bad packets */ 542 static int em_debug_sbp = false; 543 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 544 "Show bad packets in promiscuous mode"); 545 546 /* Energy efficient ethernet - default to OFF */ 547 static int eee_setting = 1; 548 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 549 "Enable Energy Efficient Ethernet"); 550 551 /* 552 * AIM: Adaptive Interrupt Moderation 553 * which means that the interrupt rate is varied over time based on the 554 * traffic for that interrupt vector 555 */ 556 static int em_enable_aim = 1; 557 SYSCTL_INT(_hw_em, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &em_enable_aim, 558 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)"); 559 560 /* 561 ** Tuneable Interrupt rate 562 */ 563 static int em_max_interrupt_rate = EM_INTS_DEFAULT; 564 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 565 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 566 567 /* Global used in WOL setup with multiport cards */ 568 static int global_quad_port_a = 0; 569 570 extern struct if_txrx igb_txrx; 571 extern struct if_txrx em_txrx; 572 extern struct if_txrx lem_txrx; 573 574 static struct if_shared_ctx em_sctx_init = { 575 .isc_magic = IFLIB_MAGIC, 576 .isc_q_align = PAGE_SIZE, 577 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 578 .isc_tx_maxsegsize = PAGE_SIZE, 579 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 580 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 581 .isc_rx_maxsize = MJUM9BYTES, 582 .isc_rx_nsegments = 1, 583 .isc_rx_maxsegsize = MJUM9BYTES, 584 .isc_nfl = 1, 585 .isc_nrxqs = 1, 586 .isc_ntxqs = 1, 587 .isc_admin_intrcnt = 1, 588 .isc_vendor_info = em_vendor_info_array, 589 .isc_driver_version = em_driver_version, 590 .isc_driver = &em_if_driver, 591 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 592 593 .isc_nrxd_min = {EM_MIN_RXD}, 594 .isc_ntxd_min = {EM_MIN_TXD}, 595 .isc_nrxd_max = {EM_MAX_RXD}, 596 .isc_ntxd_max = {EM_MAX_TXD}, 597 .isc_nrxd_default = {EM_DEFAULT_RXD}, 598 .isc_ntxd_default = {EM_DEFAULT_TXD}, 599 }; 600 601 static struct if_shared_ctx igb_sctx_init = { 602 .isc_magic = IFLIB_MAGIC, 603 .isc_q_align = PAGE_SIZE, 604 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 605 .isc_tx_maxsegsize = PAGE_SIZE, 606 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 607 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 608 .isc_rx_maxsize = MJUM9BYTES, 609 .isc_rx_nsegments = 1, 610 .isc_rx_maxsegsize = MJUM9BYTES, 611 .isc_nfl = 1, 612 .isc_nrxqs = 1, 613 .isc_ntxqs = 1, 614 .isc_admin_intrcnt = 1, 615 .isc_vendor_info = igb_vendor_info_array, 616 .isc_driver_version = igb_driver_version, 617 .isc_driver = &igb_if_driver, 618 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 619 620 .isc_nrxd_min = {EM_MIN_RXD}, 621 .isc_ntxd_min = {EM_MIN_TXD}, 622 .isc_nrxd_max = {IGB_MAX_RXD}, 623 .isc_ntxd_max = {IGB_MAX_TXD}, 624 .isc_nrxd_default = {EM_DEFAULT_RXD}, 625 .isc_ntxd_default = {EM_DEFAULT_TXD}, 626 }; 627 628 /***************************************************************** 629 * 630 * Dump Registers 631 * 632 ****************************************************************/ 633 #define IGB_REGS_LEN 739 634 635 static int em_get_regs(SYSCTL_HANDLER_ARGS) 636 { 637 struct e1000_softc *sc = (struct e1000_softc *)arg1; 638 struct e1000_hw *hw = &sc->hw; 639 struct sbuf *sb; 640 u32 *regs_buff; 641 int rc; 642 643 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 644 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 645 646 rc = sysctl_wire_old_buffer(req, 0); 647 MPASS(rc == 0); 648 if (rc != 0) { 649 free(regs_buff, M_DEVBUF); 650 return (rc); 651 } 652 653 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 654 MPASS(sb != NULL); 655 if (sb == NULL) { 656 free(regs_buff, M_DEVBUF); 657 return (ENOMEM); 658 } 659 660 /* General Registers */ 661 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 662 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 663 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 664 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 665 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 666 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 667 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 668 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 669 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 670 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 671 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 672 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 673 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 674 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 675 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 676 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 677 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 678 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 679 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 680 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 681 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 682 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 683 684 sbuf_printf(sb, "General Registers\n"); 685 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 686 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 687 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 688 689 sbuf_printf(sb, "Interrupt Registers\n"); 690 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 691 692 sbuf_printf(sb, "RX Registers\n"); 693 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 694 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 695 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 696 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 697 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 698 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 699 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 700 701 sbuf_printf(sb, "TX Registers\n"); 702 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 703 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 704 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 705 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 706 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 707 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 708 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 709 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 710 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 711 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 712 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 713 714 free(regs_buff, M_DEVBUF); 715 716 #ifdef DUMP_DESCS 717 { 718 if_softc_ctx_t scctx = sc->shared; 719 struct rx_ring *rxr = &rx_que->rxr; 720 struct tx_ring *txr = &tx_que->txr; 721 int ntxd = scctx->isc_ntxd[0]; 722 int nrxd = scctx->isc_nrxd[0]; 723 int j; 724 725 for (j = 0; j < nrxd; j++) { 726 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 727 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 728 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 729 } 730 731 for (j = 0; j < min(ntxd, 256); j++) { 732 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 733 734 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 735 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 736 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 737 738 } 739 } 740 #endif 741 742 rc = sbuf_finish(sb); 743 sbuf_delete(sb); 744 return(rc); 745 } 746 747 static void * 748 em_register(device_t dev) 749 { 750 return (&em_sctx_init); 751 } 752 753 static void * 754 igb_register(device_t dev) 755 { 756 return (&igb_sctx_init); 757 } 758 759 static int 760 em_set_num_queues(if_ctx_t ctx) 761 { 762 struct e1000_softc *sc = iflib_get_softc(ctx); 763 int maxqueues; 764 765 /* Sanity check based on HW */ 766 switch (sc->hw.mac.type) { 767 case e1000_82576: 768 case e1000_82580: 769 case e1000_i350: 770 case e1000_i354: 771 maxqueues = 8; 772 break; 773 case e1000_i210: 774 case e1000_82575: 775 maxqueues = 4; 776 break; 777 case e1000_i211: 778 case e1000_82574: 779 maxqueues = 2; 780 break; 781 default: 782 maxqueues = 1; 783 break; 784 } 785 786 return (maxqueues); 787 } 788 789 #define LEM_CAPS \ 790 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 791 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 792 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 793 794 #define EM_CAPS \ 795 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 796 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 797 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 798 IFCAP_TSO6 799 800 #define IGB_CAPS \ 801 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 802 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 803 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 804 IFCAP_TSO6 805 806 /********************************************************************* 807 * Device initialization routine 808 * 809 * The attach entry point is called when the driver is being loaded. 810 * This routine identifies the type of hardware, allocates all resources 811 * and initializes the hardware. 812 * 813 * return 0 on success, positive on failure 814 *********************************************************************/ 815 static int 816 em_if_attach_pre(if_ctx_t ctx) 817 { 818 struct e1000_softc *sc; 819 if_softc_ctx_t scctx; 820 device_t dev; 821 struct e1000_hw *hw; 822 struct sysctl_oid_list *child; 823 struct sysctl_ctx_list *ctx_list; 824 int error = 0; 825 826 INIT_DEBUGOUT("em_if_attach_pre: begin"); 827 dev = iflib_get_dev(ctx); 828 sc = iflib_get_softc(ctx); 829 830 sc->ctx = sc->osdep.ctx = ctx; 831 sc->dev = sc->osdep.dev = dev; 832 scctx = sc->shared = iflib_get_softc_ctx(ctx); 833 sc->media = iflib_get_media(ctx); 834 hw = &sc->hw; 835 836 /* Determine hardware and mac info */ 837 em_identify_hardware(ctx); 838 839 /* SYSCTL stuff */ 840 ctx_list = device_get_sysctl_ctx(dev); 841 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 842 843 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 844 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 845 em_sysctl_nvm_info, "I", "NVM Information"); 846 847 sc->enable_aim = em_enable_aim; 848 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", 849 CTLFLAG_RW, &sc->enable_aim, 0, 850 "Interrupt Moderation (1=normal, 2=lowlatency)"); 851 852 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 853 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 854 em_sysctl_print_fw_version, "A", 855 "Prints FW/NVM Versions"); 856 857 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 858 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 859 em_sysctl_debug_info, "I", "Debug Information"); 860 861 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 862 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 863 em_set_flowcntl, "I", "Flow Control"); 864 865 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 866 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 867 em_get_regs, "A", "Dump Registers"); 868 869 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 870 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 871 em_get_rs, "I", "Dump RS indexes"); 872 873 if (hw->mac.type >= e1000_i350) { 874 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 875 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 876 igb_sysctl_dmac, "I", "DMA Coalesce"); 877 } 878 879 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 880 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 881 if (bootverbose) 882 device_printf(dev, "attach_pre capping queues at %d\n", 883 scctx->isc_ntxqsets_max); 884 885 if (hw->mac.type >= igb_mac_min) { 886 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 887 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 888 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 889 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 890 scctx->isc_txrx = &igb_txrx; 891 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 892 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 893 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 894 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 895 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 896 CSUM_IP6_TCP | CSUM_IP6_UDP; 897 if (hw->mac.type != e1000_82575) 898 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 899 /* 900 ** Some new devices, as with ixgbe, now may 901 ** use a different BAR, so we need to keep 902 ** track of which is used. 903 */ 904 scctx->isc_msix_bar = pci_msix_table_bar(dev); 905 } else if (hw->mac.type >= em_mac_min) { 906 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 907 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 908 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 909 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 910 scctx->isc_txrx = &em_txrx; 911 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 912 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 913 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 914 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 915 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 916 CSUM_IP6_TCP | CSUM_IP6_UDP; 917 918 /* Disable TSO on all em(4) until ring stalls can be debugged */ 919 scctx->isc_capenable &= ~IFCAP_TSO; 920 921 /* 922 * Disable TSO on SPT due to errata that downclocks DMA performance 923 * i218-i219 Specification Update 1.5.4.5 924 */ 925 if (hw->mac.type == e1000_pch_spt) 926 scctx->isc_capenable &= ~IFCAP_TSO; 927 928 /* 929 * We support MSI-X with 82574 only, but indicate to iflib(4) 930 * that it shall give MSI at least a try with other devices. 931 */ 932 if (hw->mac.type == e1000_82574) { 933 scctx->isc_msix_bar = pci_msix_table_bar(dev); 934 } else { 935 scctx->isc_msix_bar = -1; 936 scctx->isc_disable_msix = 1; 937 } 938 } else { 939 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 940 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 941 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 942 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 943 scctx->isc_txrx = &lem_txrx; 944 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 945 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 946 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 947 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 948 if (em_unsupported_tso) 949 scctx->isc_capabilities |= IFCAP_TSO6; 950 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 951 CSUM_IP6_TCP | CSUM_IP6_UDP; 952 953 /* Disable TSO on all lem(4) until ring stalls can be debugged */ 954 scctx->isc_capenable &= ~IFCAP_TSO; 955 956 /* 82541ER doesn't do HW tagging */ 957 if (hw->device_id == E1000_DEV_ID_82541ER || 958 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 959 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 960 scctx->isc_capenable = scctx->isc_capabilities; 961 } 962 /* This is the first e1000 chip and it does not do offloads */ 963 if (hw->mac.type == e1000_82542) { 964 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 965 IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWTAGGING | 966 IFCAP_VLAN_HWFILTER | IFCAP_TSO | IFCAP_VLAN_HWTSO); 967 scctx->isc_capenable = scctx->isc_capabilities; 968 } 969 /* These can't do TSO for various reasons */ 970 if (hw->mac.type < e1000_82544 || hw->mac.type == e1000_82547 || 971 hw->mac.type == e1000_82547_rev_2) { 972 scctx->isc_capabilities &= ~(IFCAP_TSO | IFCAP_VLAN_HWTSO); 973 scctx->isc_capenable = scctx->isc_capabilities; 974 } 975 /* XXXKB: No IPv6 before this? */ 976 if (hw->mac.type < e1000_82545){ 977 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 978 scctx->isc_capenable = scctx->isc_capabilities; 979 } 980 /* "PCI/PCI-X SDM 4.0" page 33 (b) - FDX requirement on these chips */ 981 if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2) 982 scctx->isc_capenable &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 983 IFCAP_HWCSUM_IPV6); 984 985 /* INTx only */ 986 scctx->isc_msix_bar = 0; 987 } 988 989 /* Setup PCI resources */ 990 if (em_allocate_pci_resources(ctx)) { 991 device_printf(dev, "Allocation of PCI resources failed\n"); 992 error = ENXIO; 993 goto err_pci; 994 } 995 996 /* 997 ** For ICH8 and family we need to 998 ** map the flash memory, and this 999 ** must happen after the MAC is 1000 ** identified 1001 */ 1002 if ((hw->mac.type == e1000_ich8lan) || 1003 (hw->mac.type == e1000_ich9lan) || 1004 (hw->mac.type == e1000_ich10lan) || 1005 (hw->mac.type == e1000_pchlan) || 1006 (hw->mac.type == e1000_pch2lan) || 1007 (hw->mac.type == e1000_pch_lpt)) { 1008 int rid = EM_BAR_TYPE_FLASH; 1009 sc->flash = bus_alloc_resource_any(dev, 1010 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1011 if (sc->flash == NULL) { 1012 device_printf(dev, "Mapping of Flash failed\n"); 1013 error = ENXIO; 1014 goto err_pci; 1015 } 1016 /* This is used in the shared code */ 1017 hw->flash_address = (u8 *)sc->flash; 1018 sc->osdep.flash_bus_space_tag = 1019 rman_get_bustag(sc->flash); 1020 sc->osdep.flash_bus_space_handle = 1021 rman_get_bushandle(sc->flash); 1022 } 1023 /* 1024 ** In the new SPT device flash is not a 1025 ** separate BAR, rather it is also in BAR0, 1026 ** so use the same tag and an offset handle for the 1027 ** FLASH read/write macros in the shared code. 1028 */ 1029 else if (hw->mac.type >= e1000_pch_spt) { 1030 sc->osdep.flash_bus_space_tag = 1031 sc->osdep.mem_bus_space_tag; 1032 sc->osdep.flash_bus_space_handle = 1033 sc->osdep.mem_bus_space_handle 1034 + E1000_FLASH_BASE_ADDR; 1035 } 1036 1037 /* Do Shared Code initialization */ 1038 error = e1000_setup_init_funcs(hw, true); 1039 if (error) { 1040 device_printf(dev, "Setup of Shared code failed, error %d\n", 1041 error); 1042 error = ENXIO; 1043 goto err_pci; 1044 } 1045 1046 em_setup_msix(ctx); 1047 e1000_get_bus_info(hw); 1048 1049 /* Set up some sysctls for the tunable interrupt delays */ 1050 if (hw->mac.type < igb_mac_min) { 1051 em_add_int_delay_sysctl(sc, "rx_int_delay", 1052 "receive interrupt delay in usecs", &sc->rx_int_delay, 1053 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1054 em_add_int_delay_sysctl(sc, "tx_int_delay", 1055 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1056 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1057 } 1058 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) { 1059 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1060 "receive interrupt delay limit in usecs", &sc->rx_abs_int_delay, 1061 E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt); 1062 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1063 "transmit interrupt delay limit in usecs", &sc->tx_abs_int_delay, 1064 E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt); 1065 em_add_int_delay_sysctl(sc, "itr", 1066 "interrupt delay limit in usecs/4", &sc->tx_itr, 1067 E1000_REGISTER(hw, E1000_ITR), 1068 EM_INTS_TO_ITR(em_max_interrupt_rate)); 1069 } 1070 1071 hw->mac.autoneg = DO_AUTO_NEG; 1072 hw->phy.autoneg_wait_to_complete = false; 1073 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1074 1075 if (hw->mac.type < em_mac_min) { 1076 e1000_init_script_state_82541(hw, true); 1077 e1000_set_tbi_compatibility_82543(hw, true); 1078 } 1079 /* Copper options */ 1080 if (hw->phy.media_type == e1000_media_type_copper) { 1081 hw->phy.mdix = AUTO_ALL_MODES; 1082 hw->phy.disable_polarity_correction = false; 1083 hw->phy.ms_type = EM_MASTER_SLAVE; 1084 } 1085 1086 /* 1087 * Set the frame limits assuming 1088 * standard ethernet sized frames. 1089 */ 1090 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1091 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1092 1093 /* 1094 * This controls when hardware reports transmit completion 1095 * status. 1096 */ 1097 hw->mac.report_tx_early = 1; 1098 1099 /* Allocate multicast array memory. */ 1100 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1101 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1102 if (sc->mta == NULL) { 1103 device_printf(dev, "Can not allocate multicast setup array\n"); 1104 error = ENOMEM; 1105 goto err_late; 1106 } 1107 1108 /* Clear the IFCAP_TSO auto mask */ 1109 sc->tso_automasked = 0; 1110 1111 /* Check SOL/IDER usage */ 1112 if (e1000_check_reset_block(hw)) 1113 device_printf(dev, "PHY reset is blocked" 1114 " due to SOL/IDER session.\n"); 1115 1116 /* Sysctl for setting Energy Efficient Ethernet */ 1117 if (hw->mac.type < igb_mac_min) 1118 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1119 else 1120 hw->dev_spec._82575.eee_disable = eee_setting; 1121 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1122 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1123 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1124 1125 /* 1126 ** Start from a known state, this is 1127 ** important in reading the nvm and 1128 ** mac from that. 1129 */ 1130 e1000_reset_hw(hw); 1131 1132 /* Make sure we have a good EEPROM before we read from it */ 1133 if (e1000_validate_nvm_checksum(hw) < 0) { 1134 /* 1135 ** Some PCI-E parts fail the first check due to 1136 ** the link being in sleep state, call it again, 1137 ** if it fails a second time its a real issue. 1138 */ 1139 if (e1000_validate_nvm_checksum(hw) < 0) { 1140 device_printf(dev, 1141 "The EEPROM Checksum Is Not Valid\n"); 1142 error = EIO; 1143 goto err_late; 1144 } 1145 } 1146 1147 /* Copy the permanent MAC address out of the EEPROM */ 1148 if (e1000_read_mac_addr(hw) < 0) { 1149 device_printf(dev, "EEPROM read error while reading MAC" 1150 " address\n"); 1151 error = EIO; 1152 goto err_late; 1153 } 1154 1155 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1156 if (sc->vf_ifp) { 1157 ether_gen_addr(iflib_get_ifp(ctx), 1158 (struct ether_addr *)hw->mac.addr); 1159 } else { 1160 device_printf(dev, "Invalid MAC address\n"); 1161 error = EIO; 1162 goto err_late; 1163 } 1164 } 1165 1166 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1167 em_fw_version_locked(ctx); 1168 1169 em_print_fw_version(sc); 1170 1171 /* 1172 * Get Wake-on-Lan and Management info for later use 1173 */ 1174 em_get_wakeup(ctx); 1175 1176 /* Enable only WOL MAGIC by default */ 1177 scctx->isc_capenable &= ~IFCAP_WOL; 1178 if (sc->wol != 0) 1179 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1180 1181 iflib_set_mac(ctx, hw->mac.addr); 1182 1183 return (0); 1184 1185 err_late: 1186 em_release_hw_control(sc); 1187 err_pci: 1188 em_free_pci_resources(ctx); 1189 free(sc->mta, M_DEVBUF); 1190 1191 return (error); 1192 } 1193 1194 static int 1195 em_if_attach_post(if_ctx_t ctx) 1196 { 1197 struct e1000_softc *sc = iflib_get_softc(ctx); 1198 struct e1000_hw *hw = &sc->hw; 1199 int error = 0; 1200 1201 /* Setup OS specific network interface */ 1202 error = em_setup_interface(ctx); 1203 if (error != 0) { 1204 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1205 goto err_late; 1206 } 1207 1208 em_reset(ctx); 1209 1210 /* Initialize statistics */ 1211 em_update_stats_counters(sc); 1212 hw->mac.get_link_status = 1; 1213 em_if_update_admin_status(ctx); 1214 em_add_hw_stats(sc); 1215 1216 /* Non-AMT based hardware can now take control from firmware */ 1217 if (sc->has_manage && !sc->has_amt) 1218 em_get_hw_control(sc); 1219 1220 INIT_DEBUGOUT("em_if_attach_post: end"); 1221 1222 return (0); 1223 1224 err_late: 1225 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1226 return (error); 1227 } 1228 1229 /********************************************************************* 1230 * Device removal routine 1231 * 1232 * The detach entry point is called when the driver is being removed. 1233 * This routine stops the adapter and deallocates all the resources 1234 * that were allocated for driver operation. 1235 * 1236 * return 0 on success, positive on failure 1237 *********************************************************************/ 1238 static int 1239 em_if_detach(if_ctx_t ctx) 1240 { 1241 struct e1000_softc *sc = iflib_get_softc(ctx); 1242 1243 INIT_DEBUGOUT("em_if_detach: begin"); 1244 1245 e1000_phy_hw_reset(&sc->hw); 1246 1247 em_release_manageability(sc); 1248 em_release_hw_control(sc); 1249 em_free_pci_resources(ctx); 1250 free(sc->mta, M_DEVBUF); 1251 sc->mta = NULL; 1252 1253 return (0); 1254 } 1255 1256 /********************************************************************* 1257 * 1258 * Shutdown entry point 1259 * 1260 **********************************************************************/ 1261 1262 static int 1263 em_if_shutdown(if_ctx_t ctx) 1264 { 1265 return em_if_suspend(ctx); 1266 } 1267 1268 /* 1269 * Suspend/resume device methods. 1270 */ 1271 static int 1272 em_if_suspend(if_ctx_t ctx) 1273 { 1274 struct e1000_softc *sc = iflib_get_softc(ctx); 1275 1276 em_release_manageability(sc); 1277 em_release_hw_control(sc); 1278 em_enable_wakeup(ctx); 1279 return (0); 1280 } 1281 1282 static int 1283 em_if_resume(if_ctx_t ctx) 1284 { 1285 struct e1000_softc *sc = iflib_get_softc(ctx); 1286 1287 if (sc->hw.mac.type == e1000_pch2lan) 1288 e1000_resume_workarounds_pchlan(&sc->hw); 1289 em_if_init(ctx); 1290 em_init_manageability(sc); 1291 1292 return(0); 1293 } 1294 1295 static int 1296 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1297 { 1298 int max_frame_size; 1299 struct e1000_softc *sc = iflib_get_softc(ctx); 1300 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1301 1302 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1303 1304 switch (sc->hw.mac.type) { 1305 case e1000_82571: 1306 case e1000_82572: 1307 case e1000_ich9lan: 1308 case e1000_ich10lan: 1309 case e1000_pch2lan: 1310 case e1000_pch_lpt: 1311 case e1000_pch_spt: 1312 case e1000_pch_cnp: 1313 case e1000_pch_tgp: 1314 case e1000_pch_adp: 1315 case e1000_pch_mtp: 1316 case e1000_pch_ptp: 1317 case e1000_82574: 1318 case e1000_82583: 1319 case e1000_80003es2lan: 1320 /* 9K Jumbo Frame size */ 1321 max_frame_size = 9234; 1322 break; 1323 case e1000_pchlan: 1324 max_frame_size = 4096; 1325 break; 1326 case e1000_82542: 1327 case e1000_ich8lan: 1328 /* Adapters that do not support jumbo frames */ 1329 max_frame_size = ETHER_MAX_LEN; 1330 break; 1331 default: 1332 if (sc->hw.mac.type >= igb_mac_min) 1333 max_frame_size = 9234; 1334 else /* lem */ 1335 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1336 } 1337 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1338 return (EINVAL); 1339 } 1340 1341 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1342 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1343 return (0); 1344 } 1345 1346 /********************************************************************* 1347 * Init entry point 1348 * 1349 * This routine is used in two ways. It is used by the stack as 1350 * init entry point in network interface structure. It is also used 1351 * by the driver as a hw/sw initialization routine to get to a 1352 * consistent state. 1353 * 1354 **********************************************************************/ 1355 static void 1356 em_if_init(if_ctx_t ctx) 1357 { 1358 struct e1000_softc *sc = iflib_get_softc(ctx); 1359 if_softc_ctx_t scctx = sc->shared; 1360 if_t ifp = iflib_get_ifp(ctx); 1361 struct em_tx_queue *tx_que; 1362 int i; 1363 1364 INIT_DEBUGOUT("em_if_init: begin"); 1365 1366 /* Get the latest mac address, User can use a LAA */ 1367 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1368 ETHER_ADDR_LEN); 1369 1370 /* Put the address into the Receive Address Array */ 1371 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1372 1373 /* 1374 * With the 82571 adapter, RAR[0] may be overwritten 1375 * when the other port is reset, we make a duplicate 1376 * in RAR[14] for that eventuality, this assures 1377 * the interface continues to function. 1378 */ 1379 if (sc->hw.mac.type == e1000_82571) { 1380 e1000_set_laa_state_82571(&sc->hw, true); 1381 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1382 E1000_RAR_ENTRIES - 1); 1383 } 1384 1385 /* Initialize the hardware */ 1386 em_reset(ctx); 1387 em_if_update_admin_status(ctx); 1388 1389 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1390 struct tx_ring *txr = &tx_que->txr; 1391 1392 txr->tx_rs_cidx = txr->tx_rs_pidx; 1393 1394 /* Initialize the last processed descriptor to be the end of 1395 * the ring, rather than the start, so that we avoid an 1396 * off-by-one error when calculating how many descriptors are 1397 * done in the credits_update function. 1398 */ 1399 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1400 } 1401 1402 /* Setup VLAN support, basic and offload if available */ 1403 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1404 1405 /* Clear bad data from Rx FIFOs */ 1406 if (sc->hw.mac.type >= igb_mac_min) 1407 e1000_rx_fifo_flush_base(&sc->hw); 1408 1409 /* Configure for OS presence */ 1410 em_init_manageability(sc); 1411 1412 /* Prepare transmit descriptors and buffers */ 1413 em_initialize_transmit_unit(ctx); 1414 1415 /* Setup Multicast table */ 1416 em_if_multi_set(ctx); 1417 1418 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1419 em_initialize_receive_unit(ctx); 1420 1421 /* Set up VLAN support and filter */ 1422 em_setup_vlan_hw_support(ctx); 1423 1424 /* Don't lose promiscuous settings */ 1425 em_if_set_promisc(ctx, if_getflags(ifp)); 1426 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1427 1428 /* MSI-X configuration for 82574 */ 1429 if (sc->hw.mac.type == e1000_82574) { 1430 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1431 1432 tmp |= E1000_CTRL_EXT_PBA_CLR; 1433 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1434 /* Set the IVAR - interrupt vector routing. */ 1435 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1436 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1437 igb_configure_queues(sc); 1438 1439 /* this clears any pending interrupts */ 1440 E1000_READ_REG(&sc->hw, E1000_ICR); 1441 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1442 1443 /* AMT based hardware can now take control from firmware */ 1444 if (sc->has_manage && sc->has_amt) 1445 em_get_hw_control(sc); 1446 1447 /* Set Energy Efficient Ethernet */ 1448 if (sc->hw.mac.type >= igb_mac_min && 1449 sc->hw.phy.media_type == e1000_media_type_copper) { 1450 if (sc->hw.mac.type == e1000_i354) 1451 e1000_set_eee_i354(&sc->hw, true, true); 1452 else 1453 e1000_set_eee_i350(&sc->hw, true, true); 1454 } 1455 } 1456 1457 enum itr_latency_target { 1458 itr_latency_disabled = 0, 1459 itr_latency_lowest = 1, 1460 itr_latency_low = 2, 1461 itr_latency_bulk = 3 1462 }; 1463 /********************************************************************* 1464 * 1465 * Helper to calculate next (E)ITR value for AIM 1466 * 1467 *********************************************************************/ 1468 static void 1469 em_newitr(struct e1000_softc *sc, struct em_rx_queue *que, 1470 struct tx_ring *txr, struct rx_ring *rxr) 1471 { 1472 struct e1000_hw *hw = &sc->hw; 1473 u32 newitr; 1474 u32 bytes; 1475 u32 bytes_packets; 1476 u32 packets; 1477 u8 nextlatency; 1478 1479 /* Idle, do nothing */ 1480 if ((txr->tx_bytes == 0) && (rxr->rx_bytes == 0)) 1481 return; 1482 1483 newitr = 0; 1484 1485 if (sc->enable_aim) { 1486 nextlatency = rxr->rx_nextlatency; 1487 1488 /* Use half default (4K) ITR if sub-gig */ 1489 if (sc->link_speed != 1000) { 1490 newitr = EM_INTS_4K; 1491 goto em_set_next_itr; 1492 } 1493 /* Want at least enough packet buffer for two frames to AIM */ 1494 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { 1495 newitr = em_max_interrupt_rate; 1496 sc->enable_aim = 0; 1497 goto em_set_next_itr; 1498 } 1499 1500 /* Get the largest values from the associated tx and rx ring */ 1501 if (txr->tx_bytes && txr->tx_packets) { 1502 bytes = txr->tx_bytes; 1503 bytes_packets = txr->tx_bytes/txr->tx_packets; 1504 packets = txr->tx_packets; 1505 } 1506 if (rxr->rx_bytes && rxr->rx_packets) { 1507 bytes = max(bytes, rxr->rx_bytes); 1508 bytes_packets = max(bytes_packets, rxr->rx_bytes/rxr->rx_packets); 1509 packets = max(packets, rxr->rx_packets); 1510 } 1511 1512 /* Latency state machine */ 1513 switch (nextlatency) { 1514 case itr_latency_disabled: /* Bootstrapping */ 1515 nextlatency = itr_latency_low; 1516 break; 1517 case itr_latency_lowest: /* 70k ints/s */ 1518 /* TSO and jumbo frames */ 1519 if (bytes_packets > 8000) 1520 nextlatency = itr_latency_bulk; 1521 else if ((packets < 5) && (bytes > 512)) 1522 nextlatency = itr_latency_low; 1523 break; 1524 case itr_latency_low: /* 20k ints/s */ 1525 if (bytes > 10000) { 1526 /* Handle TSO */ 1527 if (bytes_packets > 8000) 1528 nextlatency = itr_latency_bulk; 1529 else if ((packets < 10) || (bytes_packets > 1200)) 1530 nextlatency = itr_latency_bulk; 1531 else if (packets > 35) 1532 nextlatency = itr_latency_lowest; 1533 } else if (bytes_packets > 2000) { 1534 nextlatency = itr_latency_bulk; 1535 } else if (packets < 3 && bytes < 512) { 1536 nextlatency = itr_latency_lowest; 1537 } 1538 break; 1539 case itr_latency_bulk: /* 4k ints/s */ 1540 if (bytes > 25000) { 1541 if (packets > 35) 1542 nextlatency = itr_latency_low; 1543 } else if (bytes < 1500) 1544 nextlatency = itr_latency_low; 1545 break; 1546 default: 1547 nextlatency = itr_latency_low; 1548 device_printf(sc->dev, "Unexpected newitr transition %d\n", 1549 nextlatency); 1550 break; 1551 } 1552 1553 /* Trim itr_latency_lowest for default AIM setting */ 1554 if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest) 1555 nextlatency = itr_latency_low; 1556 1557 /* Request new latency */ 1558 rxr->rx_nextlatency = nextlatency; 1559 } else { 1560 /* We may have toggled to AIM disabled */ 1561 nextlatency = itr_latency_disabled; 1562 rxr->rx_nextlatency = nextlatency; 1563 } 1564 1565 /* ITR state machine */ 1566 switch(nextlatency) { 1567 case itr_latency_lowest: 1568 newitr = EM_INTS_70K; 1569 break; 1570 case itr_latency_low: 1571 newitr = EM_INTS_20K; 1572 break; 1573 case itr_latency_bulk: 1574 newitr = EM_INTS_4K; 1575 break; 1576 case itr_latency_disabled: 1577 default: 1578 newitr = em_max_interrupt_rate; 1579 break; 1580 } 1581 1582 em_set_next_itr: 1583 if (hw->mac.type >= igb_mac_min) { 1584 newitr = IGB_INTS_TO_EITR(newitr); 1585 1586 if (hw->mac.type == e1000_82575) 1587 newitr |= newitr << 16; 1588 else 1589 newitr |= E1000_EITR_CNT_IGNR; 1590 1591 if (newitr != que->itr_setting) { 1592 que->itr_setting = newitr; 1593 E1000_WRITE_REG(hw, E1000_EITR(que->msix), que->itr_setting); 1594 } 1595 } else { 1596 newitr = EM_INTS_TO_ITR(newitr); 1597 1598 if (newitr != que->itr_setting) { 1599 que->itr_setting = newitr; 1600 if (hw->mac.type == e1000_82574 && que->msix) { 1601 E1000_WRITE_REG(hw, 1602 E1000_EITR_82574(que->msix), que->itr_setting); 1603 } else { 1604 E1000_WRITE_REG(hw, E1000_ITR, que->itr_setting); 1605 } 1606 } 1607 } 1608 } 1609 1610 /********************************************************************* 1611 * 1612 * Fast Legacy/MSI Combined Interrupt Service routine 1613 * 1614 *********************************************************************/ 1615 int 1616 em_intr(void *arg) 1617 { 1618 struct e1000_softc *sc = arg; 1619 struct e1000_hw *hw = &sc->hw; 1620 struct em_rx_queue *que = &sc->rx_queues[0]; 1621 struct tx_ring *txr = &sc->tx_queues[0].txr; 1622 struct rx_ring *rxr = &que->rxr; 1623 if_ctx_t ctx = sc->ctx; 1624 u32 reg_icr; 1625 1626 reg_icr = E1000_READ_REG(hw, E1000_ICR); 1627 1628 /* Hot eject? */ 1629 if (reg_icr == 0xffffffff) 1630 return FILTER_STRAY; 1631 1632 /* Definitely not our interrupt. */ 1633 if (reg_icr == 0x0) 1634 return FILTER_STRAY; 1635 1636 /* 1637 * Starting with the 82571 chip, bit 31 should be used to 1638 * determine whether the interrupt belongs to us. 1639 */ 1640 if (hw->mac.type >= e1000_82571 && 1641 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1642 return FILTER_STRAY; 1643 1644 /* 1645 * Only MSI-X interrupts have one-shot behavior by taking advantage 1646 * of the EIAC register. Thus, explicitly disable interrupts. This 1647 * also works around the MSI message reordering errata on certain 1648 * systems. 1649 */ 1650 IFDI_INTR_DISABLE(ctx); 1651 1652 /* Link status change */ 1653 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1654 em_handle_link(ctx); 1655 1656 if (reg_icr & E1000_ICR_RXO) 1657 sc->rx_overruns++; 1658 1659 if (hw->mac.type >= e1000_82540) 1660 em_newitr(sc, que, txr, rxr); 1661 1662 /* Reset state */ 1663 txr->tx_bytes = 0; 1664 txr->tx_packets = 0; 1665 rxr->rx_bytes = 0; 1666 rxr->rx_packets = 0; 1667 1668 return (FILTER_SCHEDULE_THREAD); 1669 } 1670 1671 static int 1672 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1673 { 1674 struct e1000_softc *sc = iflib_get_softc(ctx); 1675 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1676 1677 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1678 return (0); 1679 } 1680 1681 static int 1682 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1683 { 1684 struct e1000_softc *sc = iflib_get_softc(ctx); 1685 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1686 1687 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1688 return (0); 1689 } 1690 1691 static int 1692 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1693 { 1694 struct e1000_softc *sc = iflib_get_softc(ctx); 1695 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1696 1697 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1698 return (0); 1699 } 1700 1701 static int 1702 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1703 { 1704 struct e1000_softc *sc = iflib_get_softc(ctx); 1705 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1706 1707 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1708 return (0); 1709 } 1710 1711 /********************************************************************* 1712 * 1713 * MSI-X RX Interrupt Service routine 1714 * 1715 **********************************************************************/ 1716 static int 1717 em_msix_que(void *arg) 1718 { 1719 struct em_rx_queue *que = arg; 1720 struct e1000_softc *sc = que->sc; 1721 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; 1722 struct rx_ring *rxr = &que->rxr; 1723 1724 ++que->irqs; 1725 1726 em_newitr(sc, que, txr, rxr); 1727 1728 /* Reset state */ 1729 txr->tx_bytes = 0; 1730 txr->tx_packets = 0; 1731 rxr->rx_bytes = 0; 1732 rxr->rx_packets = 0; 1733 1734 return (FILTER_SCHEDULE_THREAD); 1735 } 1736 1737 /********************************************************************* 1738 * 1739 * MSI-X Link Fast Interrupt Service routine 1740 * 1741 **********************************************************************/ 1742 static int 1743 em_msix_link(void *arg) 1744 { 1745 struct e1000_softc *sc = arg; 1746 u32 reg_icr; 1747 1748 ++sc->link_irq; 1749 MPASS(sc->hw.back != NULL); 1750 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1751 1752 if (reg_icr & E1000_ICR_RXO) 1753 sc->rx_overruns++; 1754 1755 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1756 em_handle_link(sc->ctx); 1757 1758 /* Re-arm unconditionally */ 1759 if (sc->hw.mac.type >= igb_mac_min) { 1760 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1761 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1762 } else if (sc->hw.mac.type == e1000_82574) { 1763 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1764 E1000_IMS_OTHER); 1765 /* 1766 * Because we must read the ICR for this interrupt it may 1767 * clear other causes using autoclear, for this reason we 1768 * simply create a soft interrupt for all these vectors. 1769 */ 1770 if (reg_icr) 1771 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1772 } else 1773 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1774 1775 return (FILTER_HANDLED); 1776 } 1777 1778 static void 1779 em_handle_link(void *context) 1780 { 1781 if_ctx_t ctx = context; 1782 struct e1000_softc *sc = iflib_get_softc(ctx); 1783 1784 sc->hw.mac.get_link_status = 1; 1785 iflib_admin_intr_deferred(ctx); 1786 } 1787 1788 /********************************************************************* 1789 * 1790 * Media Ioctl callback 1791 * 1792 * This routine is called whenever the user queries the status of 1793 * the interface using ifconfig. 1794 * 1795 **********************************************************************/ 1796 static void 1797 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1798 { 1799 struct e1000_softc *sc = iflib_get_softc(ctx); 1800 u_char fiber_type = IFM_1000_SX; 1801 1802 INIT_DEBUGOUT("em_if_media_status: begin"); 1803 1804 iflib_admin_intr_deferred(ctx); 1805 1806 ifmr->ifm_status = IFM_AVALID; 1807 ifmr->ifm_active = IFM_ETHER; 1808 1809 if (!sc->link_active) { 1810 return; 1811 } 1812 1813 ifmr->ifm_status |= IFM_ACTIVE; 1814 1815 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1816 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1817 if (sc->hw.mac.type == e1000_82545) 1818 fiber_type = IFM_1000_LX; 1819 ifmr->ifm_active |= fiber_type | IFM_FDX; 1820 } else { 1821 switch (sc->link_speed) { 1822 case 10: 1823 ifmr->ifm_active |= IFM_10_T; 1824 break; 1825 case 100: 1826 ifmr->ifm_active |= IFM_100_TX; 1827 break; 1828 case 1000: 1829 ifmr->ifm_active |= IFM_1000_T; 1830 break; 1831 } 1832 if (sc->link_duplex == FULL_DUPLEX) 1833 ifmr->ifm_active |= IFM_FDX; 1834 else 1835 ifmr->ifm_active |= IFM_HDX; 1836 } 1837 } 1838 1839 /********************************************************************* 1840 * 1841 * Media Ioctl callback 1842 * 1843 * This routine is called when the user changes speed/duplex using 1844 * media/mediopt option with ifconfig. 1845 * 1846 **********************************************************************/ 1847 static int 1848 em_if_media_change(if_ctx_t ctx) 1849 { 1850 struct e1000_softc *sc = iflib_get_softc(ctx); 1851 struct ifmedia *ifm = iflib_get_media(ctx); 1852 1853 INIT_DEBUGOUT("em_if_media_change: begin"); 1854 1855 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1856 return (EINVAL); 1857 1858 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1859 case IFM_AUTO: 1860 sc->hw.mac.autoneg = DO_AUTO_NEG; 1861 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1862 break; 1863 case IFM_1000_LX: 1864 case IFM_1000_SX: 1865 case IFM_1000_T: 1866 sc->hw.mac.autoneg = DO_AUTO_NEG; 1867 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1868 break; 1869 case IFM_100_TX: 1870 sc->hw.mac.autoneg = false; 1871 sc->hw.phy.autoneg_advertised = 0; 1872 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1873 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1874 else 1875 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1876 break; 1877 case IFM_10_T: 1878 sc->hw.mac.autoneg = false; 1879 sc->hw.phy.autoneg_advertised = 0; 1880 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1881 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1882 else 1883 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1884 break; 1885 default: 1886 device_printf(sc->dev, "Unsupported media type\n"); 1887 } 1888 1889 em_if_init(ctx); 1890 1891 return (0); 1892 } 1893 1894 static int 1895 em_if_set_promisc(if_ctx_t ctx, int flags) 1896 { 1897 struct e1000_softc *sc = iflib_get_softc(ctx); 1898 if_t ifp = iflib_get_ifp(ctx); 1899 u32 reg_rctl; 1900 int mcnt = 0; 1901 1902 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1903 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1904 if (flags & IFF_ALLMULTI) 1905 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1906 else 1907 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1908 1909 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1910 reg_rctl &= (~E1000_RCTL_MPE); 1911 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1912 1913 if (flags & IFF_PROMISC) { 1914 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1915 em_if_vlan_filter_disable(sc); 1916 /* Turn this on if you want to see bad packets */ 1917 if (em_debug_sbp) 1918 reg_rctl |= E1000_RCTL_SBP; 1919 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1920 } else { 1921 if (flags & IFF_ALLMULTI) { 1922 reg_rctl |= E1000_RCTL_MPE; 1923 reg_rctl &= ~E1000_RCTL_UPE; 1924 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1925 } 1926 if (em_if_vlan_filter_used(ctx)) 1927 em_if_vlan_filter_enable(sc); 1928 } 1929 return (0); 1930 } 1931 1932 static u_int 1933 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1934 { 1935 u8 *mta = arg; 1936 1937 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1938 return (0); 1939 1940 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1941 1942 return (1); 1943 } 1944 1945 /********************************************************************* 1946 * Multicast Update 1947 * 1948 * This routine is called whenever multicast address list is updated. 1949 * 1950 **********************************************************************/ 1951 static void 1952 em_if_multi_set(if_ctx_t ctx) 1953 { 1954 struct e1000_softc *sc = iflib_get_softc(ctx); 1955 if_t ifp = iflib_get_ifp(ctx); 1956 u8 *mta; /* Multicast array memory */ 1957 u32 reg_rctl = 0; 1958 int mcnt = 0; 1959 1960 IOCTL_DEBUGOUT("em_set_multi: begin"); 1961 1962 mta = sc->mta; 1963 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1964 1965 if (sc->hw.mac.type == e1000_82542 && 1966 sc->hw.revision_id == E1000_REVISION_2) { 1967 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1968 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1969 e1000_pci_clear_mwi(&sc->hw); 1970 reg_rctl |= E1000_RCTL_RST; 1971 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1972 msec_delay(5); 1973 } 1974 1975 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1976 1977 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1978 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1979 1980 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1981 1982 if (if_getflags(ifp) & IFF_PROMISC) 1983 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1984 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1985 if_getflags(ifp) & IFF_ALLMULTI) { 1986 reg_rctl |= E1000_RCTL_MPE; 1987 reg_rctl &= ~E1000_RCTL_UPE; 1988 } else 1989 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1990 1991 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1992 1993 if (sc->hw.mac.type == e1000_82542 && 1994 sc->hw.revision_id == E1000_REVISION_2) { 1995 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1996 reg_rctl &= ~E1000_RCTL_RST; 1997 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1998 msec_delay(5); 1999 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2000 e1000_pci_set_mwi(&sc->hw); 2001 } 2002 } 2003 2004 /********************************************************************* 2005 * Timer routine 2006 * 2007 * This routine schedules em_if_update_admin_status() to check for 2008 * link status and to gather statistics as well as to perform some 2009 * controller-specific hardware patting. 2010 * 2011 **********************************************************************/ 2012 static void 2013 em_if_timer(if_ctx_t ctx, uint16_t qid) 2014 { 2015 2016 if (qid != 0) 2017 return; 2018 2019 iflib_admin_intr_deferred(ctx); 2020 } 2021 2022 static void 2023 em_if_update_admin_status(if_ctx_t ctx) 2024 { 2025 struct e1000_softc *sc = iflib_get_softc(ctx); 2026 struct e1000_hw *hw = &sc->hw; 2027 device_t dev = iflib_get_dev(ctx); 2028 u32 link_check, thstat, ctrl; 2029 bool automasked = false; 2030 2031 link_check = thstat = ctrl = 0; 2032 /* Get the cached link value or read phy for real */ 2033 switch (hw->phy.media_type) { 2034 case e1000_media_type_copper: 2035 if (hw->mac.get_link_status) { 2036 if (hw->mac.type == e1000_pch_spt) 2037 msec_delay(50); 2038 /* Do the work to read phy */ 2039 e1000_check_for_link(hw); 2040 link_check = !hw->mac.get_link_status; 2041 if (link_check) /* ESB2 fix */ 2042 e1000_cfg_on_link_up(hw); 2043 } else { 2044 link_check = true; 2045 } 2046 break; 2047 case e1000_media_type_fiber: 2048 e1000_check_for_link(hw); 2049 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 2050 E1000_STATUS_LU); 2051 break; 2052 case e1000_media_type_internal_serdes: 2053 e1000_check_for_link(hw); 2054 link_check = hw->mac.serdes_has_link; 2055 break; 2056 /* VF device is type_unknown */ 2057 case e1000_media_type_unknown: 2058 e1000_check_for_link(hw); 2059 link_check = !hw->mac.get_link_status; 2060 /* FALLTHROUGH */ 2061 default: 2062 break; 2063 } 2064 2065 /* Check for thermal downshift or shutdown */ 2066 if (hw->mac.type == e1000_i350) { 2067 thstat = E1000_READ_REG(hw, E1000_THSTAT); 2068 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 2069 } 2070 2071 /* Now check for a transition */ 2072 if (link_check && (sc->link_active == 0)) { 2073 e1000_get_speed_and_duplex(hw, &sc->link_speed, 2074 &sc->link_duplex); 2075 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2076 if ((sc->link_speed != SPEED_1000) && 2077 ((hw->mac.type == e1000_82571) || 2078 (hw->mac.type == e1000_82572))) { 2079 int tarc0; 2080 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2081 tarc0 &= ~TARC_SPEED_MODE_BIT; 2082 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2083 } 2084 if (bootverbose) 2085 device_printf(dev, "Link is up %d Mbps %s\n", 2086 sc->link_speed, 2087 ((sc->link_duplex == FULL_DUPLEX) ? 2088 "Full Duplex" : "Half Duplex")); 2089 sc->link_active = 1; 2090 sc->smartspeed = 0; 2091 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 2092 E1000_CTRL_EXT_LINK_MODE_GMII && 2093 (thstat & E1000_THSTAT_LINK_THROTTLE)) 2094 device_printf(dev, "Link: thermal downshift\n"); 2095 /* Delay Link Up for Phy update */ 2096 if (((hw->mac.type == e1000_i210) || 2097 (hw->mac.type == e1000_i211)) && 2098 (hw->phy.id == I210_I_PHY_ID)) 2099 msec_delay(I210_LINK_DELAY); 2100 /* Reset if the media type changed. */ 2101 if (hw->dev_spec._82575.media_changed && 2102 hw->mac.type >= igb_mac_min) { 2103 hw->dev_spec._82575.media_changed = false; 2104 sc->flags |= IGB_MEDIA_RESET; 2105 em_reset(ctx); 2106 } 2107 /* Only do TSO on gigabit Ethernet for older chips due to errata */ 2108 if (hw->mac.type < igb_mac_min) 2109 automasked = em_automask_tso(ctx); 2110 2111 /* Automasking resets the interface, so don't mark it up yet */ 2112 if (!automasked) 2113 iflib_link_state_change(ctx, LINK_STATE_UP, 2114 IF_Mbps(sc->link_speed)); 2115 } else if (!link_check && (sc->link_active == 1)) { 2116 sc->link_speed = 0; 2117 sc->link_duplex = 0; 2118 sc->link_active = 0; 2119 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 2120 } 2121 em_update_stats_counters(sc); 2122 2123 /* Reset LAA into RAR[0] on 82571 */ 2124 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 2125 e1000_rar_set(hw, hw->mac.addr, 0); 2126 2127 if (hw->mac.type < em_mac_min) 2128 lem_smartspeed(sc); 2129 } 2130 2131 static void 2132 em_if_watchdog_reset(if_ctx_t ctx) 2133 { 2134 struct e1000_softc *sc = iflib_get_softc(ctx); 2135 2136 /* 2137 * Just count the event; iflib(4) will already trigger a 2138 * sufficient reset of the controller. 2139 */ 2140 sc->watchdog_events++; 2141 } 2142 2143 /********************************************************************* 2144 * 2145 * This routine disables all traffic on the adapter by issuing a 2146 * global reset on the MAC. 2147 * 2148 **********************************************************************/ 2149 static void 2150 em_if_stop(if_ctx_t ctx) 2151 { 2152 struct e1000_softc *sc = iflib_get_softc(ctx); 2153 2154 INIT_DEBUGOUT("em_if_stop: begin"); 2155 2156 /* I219 needs special flushing to avoid hangs */ 2157 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2158 em_flush_desc_rings(sc); 2159 2160 e1000_reset_hw(&sc->hw); 2161 if (sc->hw.mac.type >= e1000_82544) 2162 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 2163 2164 e1000_led_off(&sc->hw); 2165 e1000_cleanup_led(&sc->hw); 2166 } 2167 2168 /********************************************************************* 2169 * 2170 * Determine hardware revision. 2171 * 2172 **********************************************************************/ 2173 static void 2174 em_identify_hardware(if_ctx_t ctx) 2175 { 2176 device_t dev = iflib_get_dev(ctx); 2177 struct e1000_softc *sc = iflib_get_softc(ctx); 2178 2179 /* Make sure our PCI config space has the necessary stuff set */ 2180 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2181 2182 /* Save off the information about this board */ 2183 sc->hw.vendor_id = pci_get_vendor(dev); 2184 sc->hw.device_id = pci_get_device(dev); 2185 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2186 sc->hw.subsystem_vendor_id = 2187 pci_read_config(dev, PCIR_SUBVEND_0, 2); 2188 sc->hw.subsystem_device_id = 2189 pci_read_config(dev, PCIR_SUBDEV_0, 2); 2190 2191 /* Do Shared Code Init and Setup */ 2192 if (e1000_set_mac_type(&sc->hw)) { 2193 device_printf(dev, "Setup init failure\n"); 2194 return; 2195 } 2196 2197 /* Are we a VF device? */ 2198 if ((sc->hw.mac.type == e1000_vfadapt) || 2199 (sc->hw.mac.type == e1000_vfadapt_i350)) 2200 sc->vf_ifp = 1; 2201 else 2202 sc->vf_ifp = 0; 2203 } 2204 2205 static int 2206 em_allocate_pci_resources(if_ctx_t ctx) 2207 { 2208 struct e1000_softc *sc = iflib_get_softc(ctx); 2209 device_t dev = iflib_get_dev(ctx); 2210 int rid, val; 2211 2212 rid = PCIR_BAR(0); 2213 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2214 &rid, RF_ACTIVE); 2215 if (sc->memory == NULL) { 2216 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2217 return (ENXIO); 2218 } 2219 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2220 sc->osdep.mem_bus_space_handle = 2221 rman_get_bushandle(sc->memory); 2222 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2223 2224 /* Only older adapters use IO mapping */ 2225 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2226 /* Figure our where our IO BAR is ? */ 2227 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2228 val = pci_read_config(dev, rid, 4); 2229 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2230 break; 2231 } 2232 rid += 4; 2233 /* check for 64bit BAR */ 2234 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2235 rid += 4; 2236 } 2237 if (rid >= PCIR_CIS) { 2238 device_printf(dev, "Unable to locate IO BAR\n"); 2239 return (ENXIO); 2240 } 2241 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2242 &rid, RF_ACTIVE); 2243 if (sc->ioport == NULL) { 2244 device_printf(dev, "Unable to allocate bus resource: " 2245 "ioport\n"); 2246 return (ENXIO); 2247 } 2248 sc->hw.io_base = 0; 2249 sc->osdep.io_bus_space_tag = 2250 rman_get_bustag(sc->ioport); 2251 sc->osdep.io_bus_space_handle = 2252 rman_get_bushandle(sc->ioport); 2253 } 2254 2255 sc->hw.back = &sc->osdep; 2256 2257 return (0); 2258 } 2259 2260 /********************************************************************* 2261 * 2262 * Set up the MSI-X Interrupt handlers 2263 * 2264 **********************************************************************/ 2265 static int 2266 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2267 { 2268 struct e1000_softc *sc = iflib_get_softc(ctx); 2269 struct em_rx_queue *rx_que = sc->rx_queues; 2270 struct em_tx_queue *tx_que = sc->tx_queues; 2271 int error, rid, i, vector = 0, rx_vectors; 2272 char buf[16]; 2273 2274 /* First set up ring resources */ 2275 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2276 rid = vector + 1; 2277 snprintf(buf, sizeof(buf), "rxq%d", i); 2278 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2279 if (error) { 2280 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2281 sc->rx_num_queues = i + 1; 2282 goto fail; 2283 } 2284 2285 rx_que->msix = vector; 2286 2287 /* 2288 * Set the bit to enable interrupt 2289 * in E1000_IMS -- bits 20 and 21 2290 * are for RX0 and RX1, note this has 2291 * NOTHING to do with the MSI-X vector 2292 */ 2293 if (sc->hw.mac.type == e1000_82574) { 2294 rx_que->eims = 1 << (20 + i); 2295 sc->ims |= rx_que->eims; 2296 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2297 } else if (sc->hw.mac.type == e1000_82575) 2298 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2299 else 2300 rx_que->eims = 1 << vector; 2301 } 2302 rx_vectors = vector; 2303 2304 vector = 0; 2305 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2306 snprintf(buf, sizeof(buf), "txq%d", i); 2307 tx_que = &sc->tx_queues[i]; 2308 iflib_softirq_alloc_generic(ctx, 2309 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2310 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2311 2312 tx_que->msix = (vector % sc->rx_num_queues); 2313 2314 /* 2315 * Set the bit to enable interrupt 2316 * in E1000_IMS -- bits 22 and 23 2317 * are for TX0 and TX1, note this has 2318 * NOTHING to do with the MSI-X vector 2319 */ 2320 if (sc->hw.mac.type == e1000_82574) { 2321 tx_que->eims = 1 << (22 + i); 2322 sc->ims |= tx_que->eims; 2323 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2324 } else if (sc->hw.mac.type == e1000_82575) { 2325 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2326 } else { 2327 tx_que->eims = 1 << i; 2328 } 2329 } 2330 2331 /* Link interrupt */ 2332 rid = rx_vectors + 1; 2333 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2334 2335 if (error) { 2336 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2337 goto fail; 2338 } 2339 sc->linkvec = rx_vectors; 2340 if (sc->hw.mac.type < igb_mac_min) { 2341 sc->ivars |= (8 | rx_vectors) << 16; 2342 sc->ivars |= 0x80000000; 2343 /* Enable the "Other" interrupt type for link status change */ 2344 sc->ims |= E1000_IMS_OTHER; 2345 } 2346 2347 return (0); 2348 fail: 2349 iflib_irq_free(ctx, &sc->irq); 2350 rx_que = sc->rx_queues; 2351 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2352 iflib_irq_free(ctx, &rx_que->que_irq); 2353 return (error); 2354 } 2355 2356 static void 2357 igb_configure_queues(struct e1000_softc *sc) 2358 { 2359 struct e1000_hw *hw = &sc->hw; 2360 struct em_rx_queue *rx_que; 2361 struct em_tx_queue *tx_que; 2362 u32 tmp, ivar = 0, newitr = 0; 2363 2364 /* First turn on RSS capability */ 2365 if (hw->mac.type != e1000_82575) 2366 E1000_WRITE_REG(hw, E1000_GPIE, 2367 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2368 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2369 2370 /* Turn on MSI-X */ 2371 switch (hw->mac.type) { 2372 case e1000_82580: 2373 case e1000_i350: 2374 case e1000_i354: 2375 case e1000_i210: 2376 case e1000_i211: 2377 case e1000_vfadapt: 2378 case e1000_vfadapt_i350: 2379 /* RX entries */ 2380 for (int i = 0; i < sc->rx_num_queues; i++) { 2381 u32 index = i >> 1; 2382 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2383 rx_que = &sc->rx_queues[i]; 2384 if (i & 1) { 2385 ivar &= 0xFF00FFFF; 2386 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2387 } else { 2388 ivar &= 0xFFFFFF00; 2389 ivar |= rx_que->msix | E1000_IVAR_VALID; 2390 } 2391 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2392 } 2393 /* TX entries */ 2394 for (int i = 0; i < sc->tx_num_queues; i++) { 2395 u32 index = i >> 1; 2396 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2397 tx_que = &sc->tx_queues[i]; 2398 if (i & 1) { 2399 ivar &= 0x00FFFFFF; 2400 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2401 } else { 2402 ivar &= 0xFFFF00FF; 2403 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2404 } 2405 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2406 sc->que_mask |= tx_que->eims; 2407 } 2408 2409 /* And for the link interrupt */ 2410 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2411 sc->link_mask = 1 << sc->linkvec; 2412 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2413 break; 2414 case e1000_82576: 2415 /* RX entries */ 2416 for (int i = 0; i < sc->rx_num_queues; i++) { 2417 u32 index = i & 0x7; /* Each IVAR has two entries */ 2418 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2419 rx_que = &sc->rx_queues[i]; 2420 if (i < 8) { 2421 ivar &= 0xFFFFFF00; 2422 ivar |= rx_que->msix | E1000_IVAR_VALID; 2423 } else { 2424 ivar &= 0xFF00FFFF; 2425 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2426 } 2427 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2428 sc->que_mask |= rx_que->eims; 2429 } 2430 /* TX entries */ 2431 for (int i = 0; i < sc->tx_num_queues; i++) { 2432 u32 index = i & 0x7; /* Each IVAR has two entries */ 2433 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2434 tx_que = &sc->tx_queues[i]; 2435 if (i < 8) { 2436 ivar &= 0xFFFF00FF; 2437 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2438 } else { 2439 ivar &= 0x00FFFFFF; 2440 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2441 } 2442 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2443 sc->que_mask |= tx_que->eims; 2444 } 2445 2446 /* And for the link interrupt */ 2447 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2448 sc->link_mask = 1 << sc->linkvec; 2449 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2450 break; 2451 2452 case e1000_82575: 2453 /* enable MSI-X support*/ 2454 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2455 tmp |= E1000_CTRL_EXT_PBA_CLR; 2456 /* Auto-Mask interrupts upon ICR read. */ 2457 tmp |= E1000_CTRL_EXT_EIAME; 2458 tmp |= E1000_CTRL_EXT_IRCA; 2459 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2460 2461 /* Queues */ 2462 for (int i = 0; i < sc->rx_num_queues; i++) { 2463 rx_que = &sc->rx_queues[i]; 2464 tmp = E1000_EICR_RX_QUEUE0 << i; 2465 tmp |= E1000_EICR_TX_QUEUE0 << i; 2466 rx_que->eims = tmp; 2467 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2468 i, rx_que->eims); 2469 sc->que_mask |= rx_que->eims; 2470 } 2471 2472 /* Link */ 2473 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2474 E1000_EIMS_OTHER); 2475 sc->link_mask |= E1000_EIMS_OTHER; 2476 default: 2477 break; 2478 } 2479 2480 /* Set the igb starting interrupt rate */ 2481 if (em_max_interrupt_rate > 0) { 2482 newitr = IGB_INTS_TO_EITR(em_max_interrupt_rate); 2483 2484 if (hw->mac.type == e1000_82575) 2485 newitr |= newitr << 16; 2486 else 2487 newitr |= E1000_EITR_CNT_IGNR; 2488 2489 for (int i = 0; i < sc->rx_num_queues; i++) { 2490 rx_que = &sc->rx_queues[i]; 2491 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2492 } 2493 } 2494 2495 return; 2496 } 2497 2498 static void 2499 em_free_pci_resources(if_ctx_t ctx) 2500 { 2501 struct e1000_softc *sc = iflib_get_softc(ctx); 2502 struct em_rx_queue *que = sc->rx_queues; 2503 device_t dev = iflib_get_dev(ctx); 2504 2505 /* Release all MSI-X queue resources */ 2506 if (sc->intr_type == IFLIB_INTR_MSIX) 2507 iflib_irq_free(ctx, &sc->irq); 2508 2509 if (que != NULL) { 2510 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2511 iflib_irq_free(ctx, &que->que_irq); 2512 } 2513 } 2514 2515 if (sc->memory != NULL) { 2516 bus_release_resource(dev, SYS_RES_MEMORY, 2517 rman_get_rid(sc->memory), sc->memory); 2518 sc->memory = NULL; 2519 } 2520 2521 if (sc->flash != NULL) { 2522 bus_release_resource(dev, SYS_RES_MEMORY, 2523 rman_get_rid(sc->flash), sc->flash); 2524 sc->flash = NULL; 2525 } 2526 2527 if (sc->ioport != NULL) { 2528 bus_release_resource(dev, SYS_RES_IOPORT, 2529 rman_get_rid(sc->ioport), sc->ioport); 2530 sc->ioport = NULL; 2531 } 2532 } 2533 2534 /* Set up MSI or MSI-X */ 2535 static int 2536 em_setup_msix(if_ctx_t ctx) 2537 { 2538 struct e1000_softc *sc = iflib_get_softc(ctx); 2539 2540 if (sc->hw.mac.type == e1000_82574) { 2541 em_enable_vectors_82574(ctx); 2542 } 2543 return (0); 2544 } 2545 2546 /********************************************************************* 2547 * 2548 * Workaround for SmartSpeed on 82541 and 82547 controllers 2549 * 2550 **********************************************************************/ 2551 static void 2552 lem_smartspeed(struct e1000_softc *sc) 2553 { 2554 u16 phy_tmp; 2555 2556 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2557 sc->hw.mac.autoneg == 0 || 2558 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2559 return; 2560 2561 if (sc->smartspeed == 0) { 2562 /* If Master/Slave config fault is asserted twice, 2563 * we assume back-to-back */ 2564 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2565 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2566 return; 2567 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2568 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2569 e1000_read_phy_reg(&sc->hw, 2570 PHY_1000T_CTRL, &phy_tmp); 2571 if(phy_tmp & CR_1000T_MS_ENABLE) { 2572 phy_tmp &= ~CR_1000T_MS_ENABLE; 2573 e1000_write_phy_reg(&sc->hw, 2574 PHY_1000T_CTRL, phy_tmp); 2575 sc->smartspeed++; 2576 if(sc->hw.mac.autoneg && 2577 !e1000_copper_link_autoneg(&sc->hw) && 2578 !e1000_read_phy_reg(&sc->hw, 2579 PHY_CONTROL, &phy_tmp)) { 2580 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2581 MII_CR_RESTART_AUTO_NEG); 2582 e1000_write_phy_reg(&sc->hw, 2583 PHY_CONTROL, phy_tmp); 2584 } 2585 } 2586 } 2587 return; 2588 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2589 /* If still no link, perhaps using 2/3 pair cable */ 2590 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2591 phy_tmp |= CR_1000T_MS_ENABLE; 2592 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2593 if(sc->hw.mac.autoneg && 2594 !e1000_copper_link_autoneg(&sc->hw) && 2595 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2596 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2597 MII_CR_RESTART_AUTO_NEG); 2598 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2599 } 2600 } 2601 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2602 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2603 sc->smartspeed = 0; 2604 } 2605 2606 /********************************************************************* 2607 * 2608 * Initialize the DMA Coalescing feature 2609 * 2610 **********************************************************************/ 2611 static void 2612 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2613 { 2614 device_t dev = sc->dev; 2615 struct e1000_hw *hw = &sc->hw; 2616 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2617 u16 hwm; 2618 u16 max_frame_size; 2619 2620 if (hw->mac.type == e1000_i211) 2621 return; 2622 2623 max_frame_size = sc->shared->isc_max_frame_size; 2624 if (hw->mac.type > e1000_82580) { 2625 2626 if (sc->dmac == 0) { /* Disabling it */ 2627 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2628 return; 2629 } else 2630 device_printf(dev, "DMA Coalescing enabled\n"); 2631 2632 /* Set starting threshold */ 2633 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2634 2635 hwm = 64 * pba - max_frame_size / 16; 2636 if (hwm < 64 * (pba - 6)) 2637 hwm = 64 * (pba - 6); 2638 reg = E1000_READ_REG(hw, E1000_FCRTC); 2639 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2640 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2641 & E1000_FCRTC_RTH_COAL_MASK); 2642 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2643 2644 2645 dmac = pba - max_frame_size / 512; 2646 if (dmac < pba - 10) 2647 dmac = pba - 10; 2648 reg = E1000_READ_REG(hw, E1000_DMACR); 2649 reg &= ~E1000_DMACR_DMACTHR_MASK; 2650 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2651 & E1000_DMACR_DMACTHR_MASK); 2652 2653 /* transition to L0x or L1 if available..*/ 2654 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2655 2656 /* Check if status is 2.5Gb backplane connection 2657 * before configuration of watchdog timer, which is 2658 * in msec values in 12.8usec intervals 2659 * watchdog timer= msec values in 32usec intervals 2660 * for non 2.5Gb connection 2661 */ 2662 if (hw->mac.type == e1000_i354) { 2663 int status = E1000_READ_REG(hw, E1000_STATUS); 2664 if ((status & E1000_STATUS_2P5_SKU) && 2665 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2666 reg |= ((sc->dmac * 5) >> 6); 2667 else 2668 reg |= (sc->dmac >> 5); 2669 } else { 2670 reg |= (sc->dmac >> 5); 2671 } 2672 2673 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2674 2675 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2676 2677 /* Set the interval before transition */ 2678 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2679 if (hw->mac.type == e1000_i350) 2680 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2681 /* 2682 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2683 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2684 */ 2685 if (hw->mac.type == e1000_i354) { 2686 int status = E1000_READ_REG(hw, E1000_STATUS); 2687 if ((status & E1000_STATUS_2P5_SKU) && 2688 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2689 reg |= 0xA; 2690 else 2691 reg |= 0x4; 2692 } else { 2693 reg |= 0x4; 2694 } 2695 2696 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2697 2698 /* free space in tx packet buffer to wake from DMA coal */ 2699 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2700 (2 * max_frame_size)) >> 6); 2701 2702 /* make low power state decision controlled by DMA coal */ 2703 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2704 reg &= ~E1000_PCIEMISC_LX_DECISION; 2705 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2706 2707 } else if (hw->mac.type == e1000_82580) { 2708 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2709 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2710 reg & ~E1000_PCIEMISC_LX_DECISION); 2711 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2712 } 2713 } 2714 /********************************************************************* 2715 * The 3 following flush routines are used as a workaround in the 2716 * I219 client parts and only for them. 2717 * 2718 * em_flush_tx_ring - remove all descriptors from the tx_ring 2719 * 2720 * We want to clear all pending descriptors from the TX ring. 2721 * zeroing happens when the HW reads the regs. We assign the ring itself as 2722 * the data of the next descriptor. We don't care about the data we are about 2723 * to reset the HW. 2724 **********************************************************************/ 2725 static void 2726 em_flush_tx_ring(struct e1000_softc *sc) 2727 { 2728 struct e1000_hw *hw = &sc->hw; 2729 struct tx_ring *txr = &sc->tx_queues->txr; 2730 struct e1000_tx_desc *txd; 2731 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2732 u16 size = 512; 2733 2734 tctl = E1000_READ_REG(hw, E1000_TCTL); 2735 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2736 2737 txd = &txr->tx_base[txr->tx_cidx_processed]; 2738 2739 /* Just use the ring as a dummy buffer addr */ 2740 txd->buffer_addr = txr->tx_paddr; 2741 txd->lower.data = htole32(txd_lower | size); 2742 txd->upper.data = 0; 2743 2744 /* flush descriptors to memory before notifying the HW */ 2745 wmb(); 2746 2747 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2748 mb(); 2749 usec_delay(250); 2750 } 2751 2752 /********************************************************************* 2753 * em_flush_rx_ring - remove all descriptors from the rx_ring 2754 * 2755 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2756 **********************************************************************/ 2757 static void 2758 em_flush_rx_ring(struct e1000_softc *sc) 2759 { 2760 struct e1000_hw *hw = &sc->hw; 2761 u32 rctl, rxdctl; 2762 2763 rctl = E1000_READ_REG(hw, E1000_RCTL); 2764 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2765 E1000_WRITE_FLUSH(hw); 2766 usec_delay(150); 2767 2768 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2769 /* zero the lower 14 bits (prefetch and host thresholds) */ 2770 rxdctl &= 0xffffc000; 2771 /* 2772 * update thresholds: prefetch threshold to 31, host threshold to 1 2773 * and make sure the granularity is "descriptors" and not "cache lines" 2774 */ 2775 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2776 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2777 2778 /* momentarily enable the RX ring for the changes to take effect */ 2779 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2780 E1000_WRITE_FLUSH(hw); 2781 usec_delay(150); 2782 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2783 } 2784 2785 /********************************************************************* 2786 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2787 * 2788 * In I219, the descriptor rings must be emptied before resetting the HW 2789 * or before changing the device state to D3 during runtime (runtime PM). 2790 * 2791 * Failure to do this will cause the HW to enter a unit hang state which can 2792 * only be released by PCI reset on the device 2793 * 2794 **********************************************************************/ 2795 static void 2796 em_flush_desc_rings(struct e1000_softc *sc) 2797 { 2798 struct e1000_hw *hw = &sc->hw; 2799 device_t dev = sc->dev; 2800 u16 hang_state; 2801 u32 fext_nvm11, tdlen; 2802 2803 /* First, disable MULR fix in FEXTNVM11 */ 2804 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2805 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 2806 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 2807 2808 /* do nothing if we're not in faulty state, or if the queue is empty */ 2809 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 2810 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2811 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 2812 return; 2813 em_flush_tx_ring(sc); 2814 2815 /* recheck, maybe the fault is caused by the rx ring */ 2816 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2817 if (hang_state & FLUSH_DESC_REQUIRED) 2818 em_flush_rx_ring(sc); 2819 } 2820 2821 2822 /********************************************************************* 2823 * 2824 * Initialize the hardware to a configuration as specified by the 2825 * sc structure. 2826 * 2827 **********************************************************************/ 2828 static void 2829 em_reset(if_ctx_t ctx) 2830 { 2831 device_t dev = iflib_get_dev(ctx); 2832 struct e1000_softc *sc = iflib_get_softc(ctx); 2833 if_t ifp = iflib_get_ifp(ctx); 2834 struct e1000_hw *hw = &sc->hw; 2835 u32 rx_buffer_size; 2836 u32 pba; 2837 2838 INIT_DEBUGOUT("em_reset: begin"); 2839 /* Let the firmware know the OS is in control */ 2840 em_get_hw_control(sc); 2841 2842 /* Set up smart power down as default off on newer adapters. */ 2843 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2844 hw->mac.type == e1000_82572)) { 2845 u16 phy_tmp = 0; 2846 2847 /* Speed up time to link by disabling smart power down. */ 2848 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2849 phy_tmp &= ~IGP02E1000_PM_SPD; 2850 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2851 } 2852 2853 /* 2854 * Packet Buffer Allocation (PBA) 2855 * Writing PBA sets the receive portion of the buffer 2856 * the remainder is used for the transmit buffer. 2857 */ 2858 switch (hw->mac.type) { 2859 /* 82547: Total Packet Buffer is 40K */ 2860 case e1000_82547: 2861 case e1000_82547_rev_2: 2862 if (hw->mac.max_frame_size > 8192) 2863 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2864 else 2865 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2866 break; 2867 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2868 case e1000_82571: 2869 case e1000_82572: 2870 case e1000_80003es2lan: 2871 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2872 break; 2873 /* 82573: Total Packet Buffer is 32K */ 2874 case e1000_82573: 2875 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2876 break; 2877 case e1000_82574: 2878 case e1000_82583: 2879 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2880 break; 2881 case e1000_ich8lan: 2882 pba = E1000_PBA_8K; 2883 break; 2884 case e1000_ich9lan: 2885 case e1000_ich10lan: 2886 /* Boost Receive side for jumbo frames */ 2887 if (hw->mac.max_frame_size > 4096) 2888 pba = E1000_PBA_14K; 2889 else 2890 pba = E1000_PBA_10K; 2891 break; 2892 case e1000_pchlan: 2893 case e1000_pch2lan: 2894 case e1000_pch_lpt: 2895 case e1000_pch_spt: 2896 case e1000_pch_cnp: 2897 case e1000_pch_tgp: 2898 case e1000_pch_adp: 2899 case e1000_pch_mtp: 2900 case e1000_pch_ptp: 2901 pba = E1000_PBA_26K; 2902 break; 2903 case e1000_82575: 2904 pba = E1000_PBA_32K; 2905 break; 2906 case e1000_82576: 2907 case e1000_vfadapt: 2908 pba = E1000_READ_REG(hw, E1000_RXPBS); 2909 pba &= E1000_RXPBS_SIZE_MASK_82576; 2910 break; 2911 case e1000_82580: 2912 case e1000_i350: 2913 case e1000_i354: 2914 case e1000_vfadapt_i350: 2915 pba = E1000_READ_REG(hw, E1000_RXPBS); 2916 pba = e1000_rxpbs_adjust_82580(pba); 2917 break; 2918 case e1000_i210: 2919 case e1000_i211: 2920 pba = E1000_PBA_34K; 2921 break; 2922 default: 2923 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2924 if (hw->mac.max_frame_size > 8192) 2925 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2926 else 2927 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2928 } 2929 2930 /* Special needs in case of Jumbo frames */ 2931 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 2932 u32 tx_space, min_tx, min_rx; 2933 pba = E1000_READ_REG(hw, E1000_PBA); 2934 tx_space = pba >> 16; 2935 pba &= 0xffff; 2936 min_tx = (hw->mac.max_frame_size + 2937 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2938 min_tx = roundup2(min_tx, 1024); 2939 min_tx >>= 10; 2940 min_rx = hw->mac.max_frame_size; 2941 min_rx = roundup2(min_rx, 1024); 2942 min_rx >>= 10; 2943 if (tx_space < min_tx && 2944 ((min_tx - tx_space) < pba)) { 2945 pba = pba - (min_tx - tx_space); 2946 /* 2947 * if short on rx space, rx wins 2948 * and must trump tx adjustment 2949 */ 2950 if (pba < min_rx) 2951 pba = min_rx; 2952 } 2953 E1000_WRITE_REG(hw, E1000_PBA, pba); 2954 } 2955 2956 if (hw->mac.type < igb_mac_min) 2957 E1000_WRITE_REG(hw, E1000_PBA, pba); 2958 2959 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2960 2961 /* 2962 * These parameters control the automatic generation (Tx) and 2963 * response (Rx) to Ethernet PAUSE frames. 2964 * - High water mark should allow for at least two frames to be 2965 * received after sending an XOFF. 2966 * - Low water mark works best when it is very near the high water mark. 2967 * This allows the receiver to restart by sending XON when it has 2968 * drained a bit. Here we use an arbitrary value of 1500 which will 2969 * restart after one full frame is pulled from the buffer. There 2970 * could be several smaller frames in the buffer and if so they will 2971 * not trigger the XON until their total number reduces the buffer 2972 * by 1500. 2973 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2974 */ 2975 rx_buffer_size = (pba & 0xffff) << 10; 2976 hw->fc.high_water = rx_buffer_size - 2977 roundup2(hw->mac.max_frame_size, 1024); 2978 hw->fc.low_water = hw->fc.high_water - 1500; 2979 2980 if (sc->fc) /* locally set flow control value? */ 2981 hw->fc.requested_mode = sc->fc; 2982 else 2983 hw->fc.requested_mode = e1000_fc_full; 2984 2985 if (hw->mac.type == e1000_80003es2lan) 2986 hw->fc.pause_time = 0xFFFF; 2987 else 2988 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2989 2990 hw->fc.send_xon = true; 2991 2992 /* Device specific overrides/settings */ 2993 switch (hw->mac.type) { 2994 case e1000_pchlan: 2995 /* Workaround: no TX flow ctrl for PCH */ 2996 hw->fc.requested_mode = e1000_fc_rx_pause; 2997 hw->fc.pause_time = 0xFFFF; /* override */ 2998 if (if_getmtu(ifp) > ETHERMTU) { 2999 hw->fc.high_water = 0x3500; 3000 hw->fc.low_water = 0x1500; 3001 } else { 3002 hw->fc.high_water = 0x5000; 3003 hw->fc.low_water = 0x3000; 3004 } 3005 hw->fc.refresh_time = 0x1000; 3006 break; 3007 case e1000_pch2lan: 3008 case e1000_pch_lpt: 3009 case e1000_pch_spt: 3010 case e1000_pch_cnp: 3011 case e1000_pch_tgp: 3012 case e1000_pch_adp: 3013 case e1000_pch_mtp: 3014 case e1000_pch_ptp: 3015 hw->fc.high_water = 0x5C20; 3016 hw->fc.low_water = 0x5048; 3017 hw->fc.pause_time = 0x0650; 3018 hw->fc.refresh_time = 0x0400; 3019 /* Jumbos need adjusted PBA */ 3020 if (if_getmtu(ifp) > ETHERMTU) 3021 E1000_WRITE_REG(hw, E1000_PBA, 12); 3022 else 3023 E1000_WRITE_REG(hw, E1000_PBA, 26); 3024 break; 3025 case e1000_82575: 3026 case e1000_82576: 3027 /* 8-byte granularity */ 3028 hw->fc.low_water = hw->fc.high_water - 8; 3029 break; 3030 case e1000_82580: 3031 case e1000_i350: 3032 case e1000_i354: 3033 case e1000_i210: 3034 case e1000_i211: 3035 case e1000_vfadapt: 3036 case e1000_vfadapt_i350: 3037 /* 16-byte granularity */ 3038 hw->fc.low_water = hw->fc.high_water - 16; 3039 break; 3040 case e1000_ich9lan: 3041 case e1000_ich10lan: 3042 if (if_getmtu(ifp) > ETHERMTU) { 3043 hw->fc.high_water = 0x2800; 3044 hw->fc.low_water = hw->fc.high_water - 8; 3045 break; 3046 } 3047 /* FALLTHROUGH */ 3048 default: 3049 if (hw->mac.type == e1000_80003es2lan) 3050 hw->fc.pause_time = 0xFFFF; 3051 break; 3052 } 3053 3054 /* I219 needs some special flushing to avoid hangs */ 3055 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 3056 em_flush_desc_rings(sc); 3057 3058 /* Issue a global reset */ 3059 e1000_reset_hw(hw); 3060 if (hw->mac.type >= igb_mac_min) { 3061 E1000_WRITE_REG(hw, E1000_WUC, 0); 3062 } else { 3063 E1000_WRITE_REG(hw, E1000_WUFC, 0); 3064 em_disable_aspm(sc); 3065 } 3066 if (sc->flags & IGB_MEDIA_RESET) { 3067 e1000_setup_init_funcs(hw, true); 3068 e1000_get_bus_info(hw); 3069 sc->flags &= ~IGB_MEDIA_RESET; 3070 } 3071 /* and a re-init */ 3072 if (e1000_init_hw(hw) < 0) { 3073 device_printf(dev, "Hardware Initialization Failed\n"); 3074 return; 3075 } 3076 if (hw->mac.type >= igb_mac_min) 3077 igb_init_dmac(sc, pba); 3078 3079 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */ 3080 sc->pba = pba; 3081 3082 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 3083 e1000_get_phy_info(hw); 3084 e1000_check_for_link(hw); 3085 } 3086 3087 /* 3088 * Initialise the RSS mapping for NICs that support multiple transmit/ 3089 * receive rings. 3090 */ 3091 3092 #define RSSKEYLEN 10 3093 static void 3094 em_initialize_rss_mapping(struct e1000_softc *sc) 3095 { 3096 uint8_t rss_key[4 * RSSKEYLEN]; 3097 uint32_t reta = 0; 3098 struct e1000_hw *hw = &sc->hw; 3099 int i; 3100 3101 /* 3102 * Configure RSS key 3103 */ 3104 arc4rand(rss_key, sizeof(rss_key), 0); 3105 for (i = 0; i < RSSKEYLEN; ++i) { 3106 uint32_t rssrk = 0; 3107 3108 rssrk = EM_RSSRK_VAL(rss_key, i); 3109 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 3110 } 3111 3112 /* 3113 * Configure RSS redirect table in following fashion: 3114 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3115 */ 3116 for (i = 0; i < sizeof(reta); ++i) { 3117 uint32_t q; 3118 3119 q = (i % sc->rx_num_queues) << 7; 3120 reta |= q << (8 * i); 3121 } 3122 3123 for (i = 0; i < 32; ++i) 3124 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 3125 3126 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 3127 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3128 E1000_MRQC_RSS_FIELD_IPV4 | 3129 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 3130 E1000_MRQC_RSS_FIELD_IPV6_EX | 3131 E1000_MRQC_RSS_FIELD_IPV6); 3132 } 3133 3134 static void 3135 igb_initialize_rss_mapping(struct e1000_softc *sc) 3136 { 3137 struct e1000_hw *hw = &sc->hw; 3138 int i; 3139 int queue_id; 3140 u32 reta; 3141 u32 rss_key[10], mrqc, shift = 0; 3142 3143 /* XXX? */ 3144 if (hw->mac.type == e1000_82575) 3145 shift = 6; 3146 3147 /* 3148 * The redirection table controls which destination 3149 * queue each bucket redirects traffic to. 3150 * Each DWORD represents four queues, with the LSB 3151 * being the first queue in the DWORD. 3152 * 3153 * This just allocates buckets to queues using round-robin 3154 * allocation. 3155 * 3156 * NOTE: It Just Happens to line up with the default 3157 * RSS allocation method. 3158 */ 3159 3160 /* Warning FM follows */ 3161 reta = 0; 3162 for (i = 0; i < 128; i++) { 3163 #ifdef RSS 3164 queue_id = rss_get_indirection_to_bucket(i); 3165 /* 3166 * If we have more queues than buckets, we'll 3167 * end up mapping buckets to a subset of the 3168 * queues. 3169 * 3170 * If we have more buckets than queues, we'll 3171 * end up instead assigning multiple buckets 3172 * to queues. 3173 * 3174 * Both are suboptimal, but we need to handle 3175 * the case so we don't go out of bounds 3176 * indexing arrays and such. 3177 */ 3178 queue_id = queue_id % sc->rx_num_queues; 3179 #else 3180 queue_id = (i % sc->rx_num_queues); 3181 #endif 3182 /* Adjust if required */ 3183 queue_id = queue_id << shift; 3184 3185 /* 3186 * The low 8 bits are for hash value (n+0); 3187 * The next 8 bits are for hash value (n+1), etc. 3188 */ 3189 reta = reta >> 8; 3190 reta = reta | ( ((uint32_t) queue_id) << 24); 3191 if ((i & 3) == 3) { 3192 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3193 reta = 0; 3194 } 3195 } 3196 3197 /* Now fill in hash table */ 3198 3199 /* 3200 * MRQC: Multiple Receive Queues Command 3201 * Set queuing to RSS control, number depends on the device. 3202 */ 3203 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3204 3205 #ifdef RSS 3206 /* XXX ew typecasting */ 3207 rss_getkey((uint8_t *) &rss_key); 3208 #else 3209 arc4rand(&rss_key, sizeof(rss_key), 0); 3210 #endif 3211 for (i = 0; i < 10; i++) 3212 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3213 3214 /* 3215 * Configure the RSS fields to hash upon. 3216 */ 3217 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3218 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3219 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3220 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3221 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3222 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3223 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3224 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3225 3226 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3227 } 3228 3229 /********************************************************************* 3230 * 3231 * Setup networking device structure and register interface media. 3232 * 3233 **********************************************************************/ 3234 static int 3235 em_setup_interface(if_ctx_t ctx) 3236 { 3237 if_t ifp = iflib_get_ifp(ctx); 3238 struct e1000_softc *sc = iflib_get_softc(ctx); 3239 if_softc_ctx_t scctx = sc->shared; 3240 3241 INIT_DEBUGOUT("em_setup_interface: begin"); 3242 3243 /* Single Queue */ 3244 if (sc->tx_num_queues == 1) { 3245 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3246 if_setsendqready(ifp); 3247 } 3248 3249 /* 3250 * Specify the media types supported by this adapter and register 3251 * callbacks to update media and link information 3252 */ 3253 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3254 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3255 u_char fiber_type = IFM_1000_SX; /* default type */ 3256 3257 if (sc->hw.mac.type == e1000_82545) 3258 fiber_type = IFM_1000_LX; 3259 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3260 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3261 } else { 3262 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3263 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3264 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3265 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3266 if (sc->hw.phy.type != e1000_phy_ife) { 3267 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3268 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 3269 } 3270 } 3271 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3272 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3273 return (0); 3274 } 3275 3276 static int 3277 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 3278 { 3279 struct e1000_softc *sc = iflib_get_softc(ctx); 3280 if_softc_ctx_t scctx = sc->shared; 3281 int error = E1000_SUCCESS; 3282 struct em_tx_queue *que; 3283 int i, j; 3284 3285 MPASS(sc->tx_num_queues > 0); 3286 MPASS(sc->tx_num_queues == ntxqsets); 3287 3288 /* First allocate the top level queue structs */ 3289 if (!(sc->tx_queues = 3290 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3291 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3292 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3293 return(ENOMEM); 3294 } 3295 3296 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3297 /* Set up some basics */ 3298 3299 struct tx_ring *txr = &que->txr; 3300 txr->sc = que->sc = sc; 3301 que->me = txr->me = i; 3302 3303 /* Allocate report status array */ 3304 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 3305 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 3306 error = ENOMEM; 3307 goto fail; 3308 } 3309 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3310 txr->tx_rsq[j] = QIDX_INVALID; 3311 /* get the virtual and physical address of the hardware queues */ 3312 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3313 txr->tx_paddr = paddrs[i*ntxqs]; 3314 } 3315 3316 if (bootverbose) 3317 device_printf(iflib_get_dev(ctx), 3318 "allocated for %d tx_queues\n", sc->tx_num_queues); 3319 return (0); 3320 fail: 3321 em_if_queues_free(ctx); 3322 return (error); 3323 } 3324 3325 static int 3326 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 3327 { 3328 struct e1000_softc *sc = iflib_get_softc(ctx); 3329 int error = E1000_SUCCESS; 3330 struct em_rx_queue *que; 3331 int i; 3332 3333 MPASS(sc->rx_num_queues > 0); 3334 MPASS(sc->rx_num_queues == nrxqsets); 3335 3336 /* First allocate the top level queue structs */ 3337 if (!(sc->rx_queues = 3338 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3339 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3340 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3341 error = ENOMEM; 3342 goto fail; 3343 } 3344 3345 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3346 /* Set up some basics */ 3347 struct rx_ring *rxr = &que->rxr; 3348 rxr->sc = que->sc = sc; 3349 rxr->que = que; 3350 que->me = rxr->me = i; 3351 3352 /* get the virtual and physical address of the hardware queues */ 3353 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3354 rxr->rx_paddr = paddrs[i*nrxqs]; 3355 } 3356 3357 if (bootverbose) 3358 device_printf(iflib_get_dev(ctx), 3359 "allocated for %d rx_queues\n", sc->rx_num_queues); 3360 3361 return (0); 3362 fail: 3363 em_if_queues_free(ctx); 3364 return (error); 3365 } 3366 3367 static void 3368 em_if_queues_free(if_ctx_t ctx) 3369 { 3370 struct e1000_softc *sc = iflib_get_softc(ctx); 3371 struct em_tx_queue *tx_que = sc->tx_queues; 3372 struct em_rx_queue *rx_que = sc->rx_queues; 3373 3374 if (tx_que != NULL) { 3375 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3376 struct tx_ring *txr = &tx_que->txr; 3377 if (txr->tx_rsq == NULL) 3378 break; 3379 3380 free(txr->tx_rsq, M_DEVBUF); 3381 txr->tx_rsq = NULL; 3382 } 3383 free(sc->tx_queues, M_DEVBUF); 3384 sc->tx_queues = NULL; 3385 } 3386 3387 if (rx_que != NULL) { 3388 free(sc->rx_queues, M_DEVBUF); 3389 sc->rx_queues = NULL; 3390 } 3391 } 3392 3393 /********************************************************************* 3394 * 3395 * Enable transmit unit. 3396 * 3397 **********************************************************************/ 3398 static void 3399 em_initialize_transmit_unit(if_ctx_t ctx) 3400 { 3401 struct e1000_softc *sc = iflib_get_softc(ctx); 3402 if_softc_ctx_t scctx = sc->shared; 3403 struct em_tx_queue *que; 3404 struct tx_ring *txr; 3405 struct e1000_hw *hw = &sc->hw; 3406 u32 tctl, txdctl = 0, tarc, tipg = 0; 3407 3408 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3409 3410 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3411 u64 bus_addr; 3412 caddr_t offp, endp; 3413 3414 que = &sc->tx_queues[i]; 3415 txr = &que->txr; 3416 bus_addr = txr->tx_paddr; 3417 3418 /* Clear checksum offload context. */ 3419 offp = (caddr_t)&txr->csum_flags; 3420 endp = (caddr_t)(txr + 1); 3421 bzero(offp, endp - offp); 3422 3423 /* Base and Len of TX Ring */ 3424 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3425 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3426 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3427 (u32)(bus_addr >> 32)); 3428 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3429 (u32)bus_addr); 3430 /* Init the HEAD/TAIL indices */ 3431 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3432 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3433 3434 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3435 E1000_READ_REG(hw, E1000_TDBAL(i)), 3436 E1000_READ_REG(hw, E1000_TDLEN(i))); 3437 3438 txdctl = 0; /* clear txdctl */ 3439 txdctl |= 0x1f; /* PTHRESH */ 3440 txdctl |= 1 << 8; /* HTHRESH */ 3441 txdctl |= 1 << 16;/* WTHRESH */ 3442 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3443 txdctl |= E1000_TXDCTL_GRAN; 3444 txdctl |= 1 << 25; /* LWTHRESH */ 3445 3446 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3447 } 3448 3449 /* Set the default values for the Tx Inter Packet Gap timer */ 3450 switch (hw->mac.type) { 3451 case e1000_80003es2lan: 3452 tipg = DEFAULT_82543_TIPG_IPGR1; 3453 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3454 E1000_TIPG_IPGR2_SHIFT; 3455 break; 3456 case e1000_82542: 3457 tipg = DEFAULT_82542_TIPG_IPGT; 3458 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3459 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3460 break; 3461 default: 3462 if (hw->phy.media_type == e1000_media_type_fiber || 3463 hw->phy.media_type == e1000_media_type_internal_serdes) 3464 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3465 else 3466 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3467 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3468 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3469 } 3470 3471 if (hw->mac.type < igb_mac_min) { 3472 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3473 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3474 3475 if (sc->tx_int_delay.value > 0) 3476 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3477 } 3478 3479 if (hw->mac.type >= e1000_82540) 3480 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value); 3481 3482 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3483 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3484 tarc |= TARC_SPEED_MODE_BIT; 3485 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3486 } else if (hw->mac.type == e1000_80003es2lan) { 3487 /* errata: program both queues to unweighted RR */ 3488 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3489 tarc |= 1; 3490 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3491 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3492 tarc |= 1; 3493 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3494 } else if (hw->mac.type == e1000_82574) { 3495 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3496 tarc |= TARC_ERRATA_BIT; 3497 if ( sc->tx_num_queues > 1) { 3498 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3499 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3500 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3501 } else 3502 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3503 } 3504 3505 /* Program the Transmit Control Register */ 3506 tctl = E1000_READ_REG(hw, E1000_TCTL); 3507 tctl &= ~E1000_TCTL_CT; 3508 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3509 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3510 3511 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min) 3512 tctl |= E1000_TCTL_MULR; 3513 3514 /* This write will effectively turn on the transmit unit. */ 3515 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3516 3517 /* SPT and KBL errata workarounds */ 3518 if (hw->mac.type == e1000_pch_spt) { 3519 u32 reg; 3520 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3521 reg |= E1000_RCTL_RDMTS_HEX; 3522 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3523 /* i218-i219 Specification Update 1.5.4.5 */ 3524 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3525 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3526 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3527 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3528 } 3529 } 3530 3531 /********************************************************************* 3532 * 3533 * Enable receive unit. 3534 * 3535 **********************************************************************/ 3536 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3537 3538 static void 3539 em_initialize_receive_unit(if_ctx_t ctx) 3540 { 3541 struct e1000_softc *sc = iflib_get_softc(ctx); 3542 if_softc_ctx_t scctx = sc->shared; 3543 if_t ifp = iflib_get_ifp(ctx); 3544 struct e1000_hw *hw = &sc->hw; 3545 struct em_rx_queue *que; 3546 int i; 3547 uint32_t rctl, rxcsum; 3548 3549 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3550 3551 /* 3552 * Make sure receives are disabled while setting 3553 * up the descriptor ring 3554 */ 3555 rctl = E1000_READ_REG(hw, E1000_RCTL); 3556 /* Do not disable if ever enabled on this hardware */ 3557 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3558 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3559 3560 /* Setup the Receive Control Register */ 3561 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3562 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3563 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3564 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3565 3566 /* Do not store bad packets */ 3567 rctl &= ~E1000_RCTL_SBP; 3568 3569 /* Enable Long Packet receive */ 3570 if (if_getmtu(ifp) > ETHERMTU) 3571 rctl |= E1000_RCTL_LPE; 3572 else 3573 rctl &= ~E1000_RCTL_LPE; 3574 3575 /* Strip the CRC */ 3576 if (!em_disable_crc_stripping) 3577 rctl |= E1000_RCTL_SECRC; 3578 3579 /* lem/em default interrupt moderation */ 3580 if (hw->mac.type < igb_mac_min) { 3581 if (hw->mac.type >= e1000_82540) { 3582 E1000_WRITE_REG(hw, E1000_RADV, sc->rx_abs_int_delay.value); 3583 3584 /* Set the default interrupt throttling rate */ 3585 E1000_WRITE_REG(hw, E1000_ITR, 3586 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3587 } 3588 3589 /* XXX TEMPORARY WORKAROUND: on some systems with 82573 3590 * long latencies are observed, like Lenovo X60. This 3591 * change eliminates the problem, but since having positive 3592 * values in RDTR is a known source of problems on other 3593 * platforms another solution is being sought. 3594 */ 3595 if (hw->mac.type == e1000_82573) 3596 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3597 else 3598 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3599 } 3600 3601 if (hw->mac.type >= em_mac_min) { 3602 uint32_t rfctl; 3603 /* Use extended rx descriptor formats */ 3604 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3605 rfctl |= E1000_RFCTL_EXTEN; 3606 3607 /* 3608 * When using MSI-X interrupts we need to throttle 3609 * using the EITR register (82574 only) 3610 */ 3611 if (hw->mac.type == e1000_82574) { 3612 for (int i = 0; i < 4; i++) 3613 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3614 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3615 /* Disable accelerated acknowledge */ 3616 rfctl |= E1000_RFCTL_ACK_DIS; 3617 } 3618 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3619 } 3620 3621 /* Set up L3 and L4 csum Rx descriptor offloads */ 3622 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3623 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3624 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3625 if (hw->mac.type > e1000_82575) 3626 rxcsum |= E1000_RXCSUM_CRCOFL; 3627 else if (hw->mac.type < em_mac_min && 3628 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3629 rxcsum |= E1000_RXCSUM_IPV6OFL; 3630 } else { 3631 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3632 if (hw->mac.type > e1000_82575) 3633 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3634 else if (hw->mac.type < em_mac_min) 3635 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3636 } 3637 3638 if (sc->rx_num_queues > 1) { 3639 /* RSS hash needed in the Rx descriptor */ 3640 rxcsum |= E1000_RXCSUM_PCSD; 3641 3642 if (hw->mac.type >= igb_mac_min) 3643 igb_initialize_rss_mapping(sc); 3644 else 3645 em_initialize_rss_mapping(sc); 3646 } 3647 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3648 3649 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3650 struct rx_ring *rxr = &que->rxr; 3651 /* Setup the Base and Length of the Rx Descriptor Ring */ 3652 u64 bus_addr = rxr->rx_paddr; 3653 #if 0 3654 u32 rdt = sc->rx_num_queues -1; /* default */ 3655 #endif 3656 3657 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3658 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3659 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3660 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3661 /* Setup the Head and Tail Descriptor Pointers */ 3662 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3663 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3664 } 3665 3666 /* 3667 * Set PTHRESH for improved jumbo performance 3668 * According to 10.2.5.11 of Intel 82574 Datasheet, 3669 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3670 * Only write to RXDCTL(1) if there is a need for different 3671 * settings. 3672 */ 3673 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3674 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3675 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3676 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3677 } else if (hw->mac.type == e1000_82574) { 3678 for (int i = 0; i < sc->rx_num_queues; i++) { 3679 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3680 rxdctl |= 0x20; /* PTHRESH */ 3681 rxdctl |= 4 << 8; /* HTHRESH */ 3682 rxdctl |= 4 << 16;/* WTHRESH */ 3683 rxdctl |= 1 << 24; /* Switch to granularity */ 3684 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3685 } 3686 } else if (hw->mac.type >= igb_mac_min) { 3687 u32 psize, srrctl = 0; 3688 3689 if (if_getmtu(ifp) > ETHERMTU) { 3690 psize = scctx->isc_max_frame_size; 3691 /* are we on a vlan? */ 3692 if (if_vlantrunkinuse(ifp)) 3693 psize += VLAN_TAG_SIZE; 3694 3695 if (sc->vf_ifp) 3696 e1000_rlpml_set_vf(hw, psize); 3697 else 3698 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3699 } 3700 3701 /* Set maximum packet buffer len */ 3702 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3703 E1000_SRRCTL_BSIZEPKT_SHIFT; 3704 3705 /* 3706 * If TX flow control is disabled and there's >1 queue defined, 3707 * enable DROP. 3708 * 3709 * This drops frames rather than hanging the RX MAC for all queues. 3710 */ 3711 if ((sc->rx_num_queues > 1) && 3712 (sc->fc == e1000_fc_none || 3713 sc->fc == e1000_fc_rx_pause)) { 3714 srrctl |= E1000_SRRCTL_DROP_EN; 3715 } 3716 /* Setup the Base and Length of the Rx Descriptor Rings */ 3717 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3718 struct rx_ring *rxr = &que->rxr; 3719 u64 bus_addr = rxr->rx_paddr; 3720 u32 rxdctl; 3721 3722 #ifdef notyet 3723 /* Configure for header split? -- ignore for now */ 3724 rxr->hdr_split = igb_header_split; 3725 #else 3726 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3727 #endif 3728 3729 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3730 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3731 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3732 (uint32_t)(bus_addr >> 32)); 3733 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3734 (uint32_t)bus_addr); 3735 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3736 /* Enable this Queue */ 3737 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3738 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3739 rxdctl &= 0xFFF00000; 3740 rxdctl |= IGB_RX_PTHRESH; 3741 rxdctl |= IGB_RX_HTHRESH << 8; 3742 rxdctl |= IGB_RX_WTHRESH << 16; 3743 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3744 } 3745 } else if (hw->mac.type >= e1000_pch2lan) { 3746 if (if_getmtu(ifp) > ETHERMTU) 3747 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3748 else 3749 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3750 } 3751 3752 /* Make sure VLAN Filters are off */ 3753 rctl &= ~E1000_RCTL_VFE; 3754 3755 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3756 if (hw->mac.type < igb_mac_min) { 3757 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3758 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3759 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3760 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3761 else if (sc->rx_mbuf_sz > 8192) 3762 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3763 else { 3764 rctl |= E1000_RCTL_SZ_2048; 3765 rctl &= ~E1000_RCTL_BSEX; 3766 } 3767 } else 3768 rctl |= E1000_RCTL_SZ_2048; 3769 3770 /* 3771 * rctl bits 11:10 are as follows 3772 * lem: reserved 3773 * em: DTYPE 3774 * igb: reserved 3775 * and should be 00 on all of the above 3776 */ 3777 rctl &= ~0x00000C00; 3778 3779 /* Write out the settings */ 3780 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3781 3782 return; 3783 } 3784 3785 static void 3786 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3787 { 3788 struct e1000_softc *sc = iflib_get_softc(ctx); 3789 u32 index, bit; 3790 3791 index = (vtag >> 5) & 0x7F; 3792 bit = vtag & 0x1F; 3793 sc->shadow_vfta[index] |= (1 << bit); 3794 ++sc->num_vlans; 3795 em_if_vlan_filter_write(sc); 3796 } 3797 3798 static void 3799 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3800 { 3801 struct e1000_softc *sc = iflib_get_softc(ctx); 3802 u32 index, bit; 3803 3804 index = (vtag >> 5) & 0x7F; 3805 bit = vtag & 0x1F; 3806 sc->shadow_vfta[index] &= ~(1 << bit); 3807 --sc->num_vlans; 3808 em_if_vlan_filter_write(sc); 3809 } 3810 3811 static bool 3812 em_if_vlan_filter_capable(if_ctx_t ctx) 3813 { 3814 if_t ifp = iflib_get_ifp(ctx); 3815 3816 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3817 !em_disable_crc_stripping) 3818 return (true); 3819 3820 return (false); 3821 } 3822 3823 static bool 3824 em_if_vlan_filter_used(if_ctx_t ctx) 3825 { 3826 struct e1000_softc *sc = iflib_get_softc(ctx); 3827 3828 if (!em_if_vlan_filter_capable(ctx)) 3829 return (false); 3830 3831 for (int i = 0; i < EM_VFTA_SIZE; i++) 3832 if (sc->shadow_vfta[i] != 0) 3833 return (true); 3834 3835 return (false); 3836 } 3837 3838 static void 3839 em_if_vlan_filter_enable(struct e1000_softc *sc) 3840 { 3841 struct e1000_hw *hw = &sc->hw; 3842 u32 reg; 3843 3844 reg = E1000_READ_REG(hw, E1000_RCTL); 3845 reg &= ~E1000_RCTL_CFIEN; 3846 reg |= E1000_RCTL_VFE; 3847 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3848 } 3849 3850 static void 3851 em_if_vlan_filter_disable(struct e1000_softc *sc) 3852 { 3853 struct e1000_hw *hw = &sc->hw; 3854 u32 reg; 3855 3856 reg = E1000_READ_REG(hw, E1000_RCTL); 3857 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3858 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3859 } 3860 3861 static void 3862 em_if_vlan_filter_write(struct e1000_softc *sc) 3863 { 3864 struct e1000_hw *hw = &sc->hw; 3865 3866 if (sc->vf_ifp) 3867 return; 3868 3869 /* Disable interrupts for lem-class devices during the filter change */ 3870 if (hw->mac.type < em_mac_min) 3871 em_if_intr_disable(sc->ctx); 3872 3873 for (int i = 0; i < EM_VFTA_SIZE; i++) 3874 if (sc->shadow_vfta[i] != 0) { 3875 /* XXXKB: incomplete VF support, we return early above */ 3876 if (sc->vf_ifp) 3877 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3878 else 3879 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3880 } 3881 3882 /* Re-enable interrupts for lem-class devices */ 3883 if (hw->mac.type < em_mac_min) 3884 em_if_intr_enable(sc->ctx); 3885 } 3886 3887 static void 3888 em_setup_vlan_hw_support(if_ctx_t ctx) 3889 { 3890 struct e1000_softc *sc = iflib_get_softc(ctx); 3891 struct e1000_hw *hw = &sc->hw; 3892 if_t ifp = iflib_get_ifp(ctx); 3893 u32 reg; 3894 3895 /* XXXKB: Return early if we are a VF until VF decap and filter management 3896 * is ready and tested. 3897 */ 3898 if (sc->vf_ifp) 3899 return; 3900 3901 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3902 !em_disable_crc_stripping) { 3903 reg = E1000_READ_REG(hw, E1000_CTRL); 3904 reg |= E1000_CTRL_VME; 3905 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3906 } else { 3907 reg = E1000_READ_REG(hw, E1000_CTRL); 3908 reg &= ~E1000_CTRL_VME; 3909 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3910 } 3911 3912 /* If we aren't doing HW filtering, we're done */ 3913 if (!em_if_vlan_filter_capable(ctx)) { 3914 em_if_vlan_filter_disable(sc); 3915 return; 3916 } 3917 3918 /* 3919 * A soft reset zero's out the VFTA, so 3920 * we need to repopulate it now. 3921 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 3922 * traffic through. This will write the entire table. 3923 */ 3924 em_if_vlan_register(ctx, 0); 3925 3926 /* Enable the Filter Table */ 3927 em_if_vlan_filter_enable(sc); 3928 } 3929 3930 static void 3931 em_if_intr_enable(if_ctx_t ctx) 3932 { 3933 struct e1000_softc *sc = iflib_get_softc(ctx); 3934 struct e1000_hw *hw = &sc->hw; 3935 u32 ims_mask = IMS_ENABLE_MASK; 3936 3937 if (sc->intr_type == IFLIB_INTR_MSIX) { 3938 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3939 ims_mask |= sc->ims; 3940 } 3941 3942 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3943 E1000_WRITE_FLUSH(hw); 3944 } 3945 3946 static void 3947 em_if_intr_disable(if_ctx_t ctx) 3948 { 3949 struct e1000_softc *sc = iflib_get_softc(ctx); 3950 struct e1000_hw *hw = &sc->hw; 3951 3952 if (sc->intr_type == IFLIB_INTR_MSIX) 3953 E1000_WRITE_REG(hw, EM_EIAC, 0); 3954 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3955 E1000_WRITE_FLUSH(hw); 3956 } 3957 3958 static void 3959 igb_if_intr_enable(if_ctx_t ctx) 3960 { 3961 struct e1000_softc *sc = iflib_get_softc(ctx); 3962 struct e1000_hw *hw = &sc->hw; 3963 u32 mask; 3964 3965 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3966 mask = (sc->que_mask | sc->link_mask); 3967 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3968 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3969 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3970 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3971 } else 3972 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3973 E1000_WRITE_FLUSH(hw); 3974 } 3975 3976 static void 3977 igb_if_intr_disable(if_ctx_t ctx) 3978 { 3979 struct e1000_softc *sc = iflib_get_softc(ctx); 3980 struct e1000_hw *hw = &sc->hw; 3981 3982 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3983 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3984 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3985 } 3986 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3987 E1000_WRITE_FLUSH(hw); 3988 } 3989 3990 /* 3991 * Bit of a misnomer, what this really means is 3992 * to enable OS management of the system... aka 3993 * to disable special hardware management features 3994 */ 3995 static void 3996 em_init_manageability(struct e1000_softc *sc) 3997 { 3998 /* A shared code workaround */ 3999 #define E1000_82542_MANC2H E1000_MANC2H 4000 if (sc->has_manage) { 4001 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 4002 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4003 4004 /* disable hardware interception of ARP */ 4005 manc &= ~(E1000_MANC_ARP_EN); 4006 4007 /* enable receiving management packets to the host */ 4008 manc |= E1000_MANC_EN_MNG2HOST; 4009 #define E1000_MNG2HOST_PORT_623 (1 << 5) 4010 #define E1000_MNG2HOST_PORT_664 (1 << 6) 4011 manc2h |= E1000_MNG2HOST_PORT_623; 4012 manc2h |= E1000_MNG2HOST_PORT_664; 4013 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 4014 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4015 } 4016 } 4017 4018 /* 4019 * Give control back to hardware management 4020 * controller if there is one. 4021 */ 4022 static void 4023 em_release_manageability(struct e1000_softc *sc) 4024 { 4025 if (sc->has_manage) { 4026 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4027 4028 /* re-enable hardware interception of ARP */ 4029 manc |= E1000_MANC_ARP_EN; 4030 manc &= ~E1000_MANC_EN_MNG2HOST; 4031 4032 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4033 } 4034 } 4035 4036 /* 4037 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 4038 * For ASF and Pass Through versions of f/w this means 4039 * that the driver is loaded. For AMT version type f/w 4040 * this means that the network i/f is open. 4041 */ 4042 static void 4043 em_get_hw_control(struct e1000_softc *sc) 4044 { 4045 u32 ctrl_ext, swsm; 4046 4047 if (sc->vf_ifp) 4048 return; 4049 4050 if (sc->hw.mac.type == e1000_82573) { 4051 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4052 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4053 swsm | E1000_SWSM_DRV_LOAD); 4054 return; 4055 } 4056 /* else */ 4057 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4058 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4059 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4060 } 4061 4062 /* 4063 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4064 * For ASF and Pass Through versions of f/w this means that 4065 * the driver is no longer loaded. For AMT versions of the 4066 * f/w this means that the network i/f is closed. 4067 */ 4068 static void 4069 em_release_hw_control(struct e1000_softc *sc) 4070 { 4071 u32 ctrl_ext, swsm; 4072 4073 if (!sc->has_manage) 4074 return; 4075 4076 if (sc->hw.mac.type == e1000_82573) { 4077 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4078 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4079 swsm & ~E1000_SWSM_DRV_LOAD); 4080 return; 4081 } 4082 /* else */ 4083 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4084 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4085 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4086 return; 4087 } 4088 4089 static int 4090 em_is_valid_ether_addr(u8 *addr) 4091 { 4092 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4093 4094 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4095 return (false); 4096 } 4097 4098 return (true); 4099 } 4100 4101 static bool 4102 em_automask_tso(if_ctx_t ctx) 4103 { 4104 struct e1000_softc *sc = iflib_get_softc(ctx); 4105 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 4106 if_t ifp = iflib_get_ifp(ctx); 4107 4108 if (!em_unsupported_tso && sc->link_speed && 4109 sc->link_speed != SPEED_1000 && scctx->isc_capenable & IFCAP_TSO) { 4110 device_printf(sc->dev, "Disabling TSO for 10/100 Ethernet.\n"); 4111 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 4112 scctx->isc_capenable &= ~IFCAP_TSO; 4113 if_setcapenablebit(ifp, 0, IFCAP_TSO); 4114 /* iflib_init_locked handles ifnet hwassistbits */ 4115 iflib_request_reset(ctx); 4116 return true; 4117 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 4118 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 4119 scctx->isc_capenable |= sc->tso_automasked; 4120 if_setcapenablebit(ifp, sc->tso_automasked, 0); 4121 sc->tso_automasked = 0; 4122 /* iflib_init_locked handles ifnet hwassistbits */ 4123 iflib_request_reset(ctx); 4124 return true; 4125 } 4126 4127 return false; 4128 } 4129 4130 /* 4131 ** Parse the interface capabilities with regard 4132 ** to both system management and wake-on-lan for 4133 ** later use. 4134 */ 4135 static void 4136 em_get_wakeup(if_ctx_t ctx) 4137 { 4138 struct e1000_softc *sc = iflib_get_softc(ctx); 4139 device_t dev = iflib_get_dev(ctx); 4140 u16 eeprom_data = 0, device_id, apme_mask; 4141 4142 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 4143 apme_mask = EM_EEPROM_APME; 4144 4145 switch (sc->hw.mac.type) { 4146 case e1000_82542: 4147 case e1000_82543: 4148 break; 4149 case e1000_82544: 4150 e1000_read_nvm(&sc->hw, 4151 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 4152 apme_mask = EM_82544_APME; 4153 break; 4154 case e1000_82546: 4155 case e1000_82546_rev_3: 4156 if (sc->hw.bus.func == 1) { 4157 e1000_read_nvm(&sc->hw, 4158 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4159 break; 4160 } else 4161 e1000_read_nvm(&sc->hw, 4162 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4163 break; 4164 case e1000_82573: 4165 case e1000_82583: 4166 sc->has_amt = true; 4167 /* FALLTHROUGH */ 4168 case e1000_82571: 4169 case e1000_82572: 4170 case e1000_80003es2lan: 4171 if (sc->hw.bus.func == 1) { 4172 e1000_read_nvm(&sc->hw, 4173 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4174 break; 4175 } else 4176 e1000_read_nvm(&sc->hw, 4177 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4178 break; 4179 case e1000_ich8lan: 4180 case e1000_ich9lan: 4181 case e1000_ich10lan: 4182 case e1000_pchlan: 4183 case e1000_pch2lan: 4184 case e1000_pch_lpt: 4185 case e1000_pch_spt: 4186 case e1000_82575: /* listing all igb devices */ 4187 case e1000_82576: 4188 case e1000_82580: 4189 case e1000_i350: 4190 case e1000_i354: 4191 case e1000_i210: 4192 case e1000_i211: 4193 case e1000_vfadapt: 4194 case e1000_vfadapt_i350: 4195 apme_mask = E1000_WUC_APME; 4196 sc->has_amt = true; 4197 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4198 break; 4199 default: 4200 e1000_read_nvm(&sc->hw, 4201 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4202 break; 4203 } 4204 if (eeprom_data & apme_mask) 4205 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4206 /* 4207 * We have the eeprom settings, now apply the special cases 4208 * where the eeprom may be wrong or the board won't support 4209 * wake on lan on a particular port 4210 */ 4211 device_id = pci_get_device(dev); 4212 switch (device_id) { 4213 case E1000_DEV_ID_82546GB_PCIE: 4214 sc->wol = 0; 4215 break; 4216 case E1000_DEV_ID_82546EB_FIBER: 4217 case E1000_DEV_ID_82546GB_FIBER: 4218 /* Wake events only supported on port A for dual fiber 4219 * regardless of eeprom setting */ 4220 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4221 E1000_STATUS_FUNC_1) 4222 sc->wol = 0; 4223 break; 4224 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4225 /* if quad port adapter, disable WoL on all but port A */ 4226 if (global_quad_port_a != 0) 4227 sc->wol = 0; 4228 /* Reset for multiple quad port adapters */ 4229 if (++global_quad_port_a == 4) 4230 global_quad_port_a = 0; 4231 break; 4232 case E1000_DEV_ID_82571EB_FIBER: 4233 /* Wake events only supported on port A for dual fiber 4234 * regardless of eeprom setting */ 4235 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4236 E1000_STATUS_FUNC_1) 4237 sc->wol = 0; 4238 break; 4239 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4240 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4241 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4242 /* if quad port adapter, disable WoL on all but port A */ 4243 if (global_quad_port_a != 0) 4244 sc->wol = 0; 4245 /* Reset for multiple quad port adapters */ 4246 if (++global_quad_port_a == 4) 4247 global_quad_port_a = 0; 4248 break; 4249 } 4250 return; 4251 } 4252 4253 4254 /* 4255 * Enable PCI Wake On Lan capability 4256 */ 4257 static void 4258 em_enable_wakeup(if_ctx_t ctx) 4259 { 4260 struct e1000_softc *sc = iflib_get_softc(ctx); 4261 device_t dev = iflib_get_dev(ctx); 4262 if_t ifp = iflib_get_ifp(ctx); 4263 int error = 0; 4264 u32 pmc, ctrl, ctrl_ext, rctl; 4265 u16 status; 4266 4267 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4268 return; 4269 4270 /* 4271 * Determine type of Wakeup: note that wol 4272 * is set with all bits on by default. 4273 */ 4274 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4275 sc->wol &= ~E1000_WUFC_MAG; 4276 4277 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4278 sc->wol &= ~E1000_WUFC_EX; 4279 4280 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4281 sc->wol &= ~E1000_WUFC_MC; 4282 else { 4283 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4284 rctl |= E1000_RCTL_MPE; 4285 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4286 } 4287 4288 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4289 goto pme; 4290 4291 /* Advertise the wakeup capability */ 4292 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4293 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4294 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4295 4296 /* Keep the laser running on Fiber adapters */ 4297 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4298 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4299 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4300 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4301 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4302 } 4303 4304 if ((sc->hw.mac.type == e1000_ich8lan) || 4305 (sc->hw.mac.type == e1000_pchlan) || 4306 (sc->hw.mac.type == e1000_ich9lan) || 4307 (sc->hw.mac.type == e1000_ich10lan)) 4308 e1000_suspend_workarounds_ich8lan(&sc->hw); 4309 4310 if ( sc->hw.mac.type >= e1000_pchlan) { 4311 error = em_enable_phy_wakeup(sc); 4312 if (error) 4313 goto pme; 4314 } else { 4315 /* Enable wakeup by the MAC */ 4316 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4317 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4318 } 4319 4320 if (sc->hw.phy.type == e1000_phy_igp_3) 4321 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4322 4323 pme: 4324 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4325 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4326 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4327 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4328 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4329 4330 return; 4331 } 4332 4333 /* 4334 * WOL in the newer chipset interfaces (pchlan) 4335 * require thing to be copied into the phy 4336 */ 4337 static int 4338 em_enable_phy_wakeup(struct e1000_softc *sc) 4339 { 4340 struct e1000_hw *hw = &sc->hw; 4341 u32 mreg, ret = 0; 4342 u16 preg; 4343 4344 /* copy MAC RARs to PHY RARs */ 4345 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4346 4347 /* copy MAC MTA to PHY MTA */ 4348 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4349 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4350 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4351 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4352 (u16)((mreg >> 16) & 0xFFFF)); 4353 } 4354 4355 /* configure PHY Rx Control register */ 4356 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4357 mreg = E1000_READ_REG(hw, E1000_RCTL); 4358 if (mreg & E1000_RCTL_UPE) 4359 preg |= BM_RCTL_UPE; 4360 if (mreg & E1000_RCTL_MPE) 4361 preg |= BM_RCTL_MPE; 4362 preg &= ~(BM_RCTL_MO_MASK); 4363 if (mreg & E1000_RCTL_MO_3) 4364 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4365 << BM_RCTL_MO_SHIFT); 4366 if (mreg & E1000_RCTL_BAM) 4367 preg |= BM_RCTL_BAM; 4368 if (mreg & E1000_RCTL_PMCF) 4369 preg |= BM_RCTL_PMCF; 4370 mreg = E1000_READ_REG(hw, E1000_CTRL); 4371 if (mreg & E1000_CTRL_RFCE) 4372 preg |= BM_RCTL_RFCE; 4373 e1000_write_phy_reg(hw, BM_RCTL, preg); 4374 4375 /* enable PHY wakeup in MAC register */ 4376 E1000_WRITE_REG(hw, E1000_WUC, 4377 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4378 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4379 4380 /* configure and enable PHY wakeup in PHY registers */ 4381 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4382 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4383 4384 /* activate PHY wakeup */ 4385 ret = hw->phy.ops.acquire(hw); 4386 if (ret) { 4387 printf("Could not acquire PHY\n"); 4388 return ret; 4389 } 4390 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4391 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4392 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4393 if (ret) { 4394 printf("Could not read PHY page 769\n"); 4395 goto out; 4396 } 4397 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4398 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4399 if (ret) 4400 printf("Could not set PHY Host Wakeup bit\n"); 4401 out: 4402 hw->phy.ops.release(hw); 4403 4404 return ret; 4405 } 4406 4407 static void 4408 em_if_led_func(if_ctx_t ctx, int onoff) 4409 { 4410 struct e1000_softc *sc = iflib_get_softc(ctx); 4411 4412 if (onoff) { 4413 e1000_setup_led(&sc->hw); 4414 e1000_led_on(&sc->hw); 4415 } else { 4416 e1000_led_off(&sc->hw); 4417 e1000_cleanup_led(&sc->hw); 4418 } 4419 } 4420 4421 /* 4422 * Disable the L0S and L1 LINK states 4423 */ 4424 static void 4425 em_disable_aspm(struct e1000_softc *sc) 4426 { 4427 int base, reg; 4428 u16 link_cap,link_ctrl; 4429 device_t dev = sc->dev; 4430 4431 switch (sc->hw.mac.type) { 4432 case e1000_82573: 4433 case e1000_82574: 4434 case e1000_82583: 4435 break; 4436 default: 4437 return; 4438 } 4439 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4440 return; 4441 reg = base + PCIER_LINK_CAP; 4442 link_cap = pci_read_config(dev, reg, 2); 4443 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4444 return; 4445 reg = base + PCIER_LINK_CTL; 4446 link_ctrl = pci_read_config(dev, reg, 2); 4447 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4448 pci_write_config(dev, reg, link_ctrl, 2); 4449 return; 4450 } 4451 4452 /********************************************************************** 4453 * 4454 * Update the board statistics counters. 4455 * 4456 **********************************************************************/ 4457 static void 4458 em_update_stats_counters(struct e1000_softc *sc) 4459 { 4460 u64 prev_xoffrxc = sc->stats.xoffrxc; 4461 4462 if(sc->hw.phy.media_type == e1000_media_type_copper || 4463 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4464 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4465 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4466 } 4467 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4468 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4469 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4470 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4471 4472 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4473 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4474 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4475 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4476 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4477 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4478 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4479 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4480 /* 4481 ** For watchdog management we need to know if we have been 4482 ** paused during the last interval, so capture that here. 4483 */ 4484 if (sc->stats.xoffrxc != prev_xoffrxc) 4485 sc->shared->isc_pause_frames = 1; 4486 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4487 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4488 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4489 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4490 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4491 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4492 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4493 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4494 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4495 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4496 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4497 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4498 4499 /* For the 64-bit byte counters the low dword must be read first. */ 4500 /* Both registers clear on the read of the high dword */ 4501 4502 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4503 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4504 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4505 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4506 4507 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4508 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4509 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4510 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4511 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4512 4513 sc->stats.mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC); 4514 sc->stats.mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC); 4515 sc->stats.mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC); 4516 4517 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4518 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4519 4520 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4521 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4522 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4523 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4524 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4525 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4526 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4527 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4528 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4529 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4530 4531 /* Interrupt Counts */ 4532 4533 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4534 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4535 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4536 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4537 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4538 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4539 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4540 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4541 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4542 4543 if (sc->hw.mac.type >= e1000_82543) { 4544 sc->stats.algnerrc += 4545 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4546 sc->stats.rxerrc += 4547 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4548 sc->stats.tncrs += 4549 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4550 sc->stats.cexterr += 4551 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4552 sc->stats.tsctc += 4553 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4554 sc->stats.tsctfc += 4555 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4556 } 4557 } 4558 4559 static uint64_t 4560 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4561 { 4562 struct e1000_softc *sc = iflib_get_softc(ctx); 4563 if_t ifp = iflib_get_ifp(ctx); 4564 4565 switch (cnt) { 4566 case IFCOUNTER_COLLISIONS: 4567 return (sc->stats.colc); 4568 case IFCOUNTER_IERRORS: 4569 return (sc->dropped_pkts + sc->stats.rxerrc + 4570 sc->stats.crcerrs + sc->stats.algnerrc + 4571 sc->stats.ruc + sc->stats.roc + 4572 sc->stats.mpc + sc->stats.cexterr); 4573 case IFCOUNTER_OERRORS: 4574 return (sc->stats.ecol + sc->stats.latecol + 4575 sc->watchdog_events); 4576 default: 4577 return (if_get_counter_default(ifp, cnt)); 4578 } 4579 } 4580 4581 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4582 * @ctx: iflib context 4583 * @event: event code to check 4584 * 4585 * Defaults to returning false for unknown events. 4586 * 4587 * @returns true if iflib needs to reinit the interface 4588 */ 4589 static bool 4590 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4591 { 4592 switch (event) { 4593 case IFLIB_RESTART_VLAN_CONFIG: 4594 default: 4595 return (false); 4596 } 4597 } 4598 4599 /* Export a single 32-bit register via a read-only sysctl. */ 4600 static int 4601 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4602 { 4603 struct e1000_softc *sc; 4604 u_int val; 4605 4606 sc = oidp->oid_arg1; 4607 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4608 return (sysctl_handle_int(oidp, &val, 0, req)); 4609 } 4610 4611 /* Per queue holdoff interrupt rate handler */ 4612 static int 4613 em_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 4614 { 4615 struct em_rx_queue *rque; 4616 struct em_tx_queue *tque; 4617 struct e1000_hw *hw; 4618 int error; 4619 u32 reg, usec, rate; 4620 4621 bool tx = oidp->oid_arg2; 4622 4623 if (tx) { 4624 tque = oidp->oid_arg1; 4625 hw = &tque->sc->hw; 4626 if (hw->mac.type >= igb_mac_min) 4627 reg = E1000_READ_REG(hw, E1000_EITR(tque->me)); 4628 else if (hw->mac.type == e1000_82574 && tque->msix) 4629 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me)); 4630 else 4631 reg = E1000_READ_REG(hw, E1000_ITR); 4632 } else { 4633 rque = oidp->oid_arg1; 4634 hw = &rque->sc->hw; 4635 if (hw->mac.type >= igb_mac_min) 4636 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix)); 4637 else if (hw->mac.type == e1000_82574 && rque->msix) 4638 reg = E1000_READ_REG(hw, E1000_EITR_82574(rque->msix)); 4639 else 4640 reg = E1000_READ_REG(hw, E1000_ITR); 4641 } 4642 4643 if (hw->mac.type < igb_mac_min) { 4644 if (reg > 0) 4645 rate = EM_INTS_TO_ITR(reg); 4646 else 4647 rate = 0; 4648 } else { 4649 usec = (reg & IGB_QVECTOR_MASK); 4650 if (usec > 0) 4651 rate = IGB_INTS_TO_EITR(usec); 4652 else 4653 rate = 0; 4654 } 4655 4656 error = sysctl_handle_int(oidp, &rate, 0, req); 4657 if (error || !req->newptr) 4658 return error; 4659 return 0; 4660 } 4661 4662 /* 4663 * Add sysctl variables, one per statistic, to the system. 4664 */ 4665 static void 4666 em_add_hw_stats(struct e1000_softc *sc) 4667 { 4668 device_t dev = iflib_get_dev(sc->ctx); 4669 struct em_tx_queue *tx_que = sc->tx_queues; 4670 struct em_rx_queue *rx_que = sc->rx_queues; 4671 4672 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4673 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4674 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4675 struct e1000_hw_stats *stats = &sc->stats; 4676 4677 struct sysctl_oid *stat_node, *queue_node, *int_node; 4678 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4679 4680 #define QUEUE_NAME_LEN 32 4681 char namebuf[QUEUE_NAME_LEN]; 4682 4683 /* Driver Statistics */ 4684 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4685 CTLFLAG_RD, &sc->dropped_pkts, 4686 "Driver dropped packets"); 4687 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4688 CTLFLAG_RD, &sc->link_irq, 4689 "Link MSI-X IRQ Handled"); 4690 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4691 CTLFLAG_RD, &sc->rx_overruns, 4692 "RX overruns"); 4693 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4694 CTLFLAG_RD, &sc->watchdog_events, 4695 "Watchdog timeouts"); 4696 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4697 CTLTYPE_UINT | CTLFLAG_RD, 4698 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4699 "Device Control Register"); 4700 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4701 CTLTYPE_UINT | CTLFLAG_RD, 4702 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4703 "Receiver Control Register"); 4704 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4705 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4706 "Flow Control High Watermark"); 4707 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4708 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4709 "Flow Control Low Watermark"); 4710 4711 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4712 struct tx_ring *txr = &tx_que->txr; 4713 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4714 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4715 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4716 queue_list = SYSCTL_CHILDREN(queue_node); 4717 4718 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4719 CTLTYPE_UINT | CTLFLAG_RD, tx_que, 4720 true, em_sysctl_interrupt_rate_handler, 4721 "IU", "Interrupt Rate"); 4722 4723 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4724 CTLTYPE_UINT | CTLFLAG_RD, sc, 4725 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4726 "Transmit Descriptor Head"); 4727 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4728 CTLTYPE_UINT | CTLFLAG_RD, sc, 4729 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4730 "Transmit Descriptor Tail"); 4731 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4732 CTLFLAG_RD, &txr->tx_irq, 4733 "Queue MSI-X Transmit Interrupts"); 4734 } 4735 4736 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4737 struct rx_ring *rxr = &rx_que->rxr; 4738 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4739 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4740 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4741 queue_list = SYSCTL_CHILDREN(queue_node); 4742 4743 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4744 CTLTYPE_UINT | CTLFLAG_RD, rx_que, 4745 false, em_sysctl_interrupt_rate_handler, 4746 "IU", "Interrupt Rate"); 4747 4748 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4749 CTLTYPE_UINT | CTLFLAG_RD, sc, 4750 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4751 "Receive Descriptor Head"); 4752 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4753 CTLTYPE_UINT | CTLFLAG_RD, sc, 4754 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4755 "Receive Descriptor Tail"); 4756 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4757 CTLFLAG_RD, &rxr->rx_irq, 4758 "Queue MSI-X Receive Interrupts"); 4759 } 4760 4761 /* MAC stats get their own sub node */ 4762 4763 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4764 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4765 stat_list = SYSCTL_CHILDREN(stat_node); 4766 4767 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4768 CTLFLAG_RD, &stats->ecol, 4769 "Excessive collisions"); 4770 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4771 CTLFLAG_RD, &stats->scc, 4772 "Single collisions"); 4773 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4774 CTLFLAG_RD, &stats->mcc, 4775 "Multiple collisions"); 4776 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4777 CTLFLAG_RD, &stats->latecol, 4778 "Late collisions"); 4779 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4780 CTLFLAG_RD, &stats->colc, 4781 "Collision Count"); 4782 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4783 CTLFLAG_RD, &sc->stats.symerrs, 4784 "Symbol Errors"); 4785 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4786 CTLFLAG_RD, &sc->stats.sec, 4787 "Sequence Errors"); 4788 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4789 CTLFLAG_RD, &sc->stats.dc, 4790 "Defer Count"); 4791 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4792 CTLFLAG_RD, &sc->stats.mpc, 4793 "Missed Packets"); 4794 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors", 4795 CTLFLAG_RD, &sc->stats.rlec, 4796 "Receive Length Errors"); 4797 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4798 CTLFLAG_RD, &sc->stats.rnbc, 4799 "Receive No Buffers"); 4800 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4801 CTLFLAG_RD, &sc->stats.ruc, 4802 "Receive Undersize"); 4803 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4804 CTLFLAG_RD, &sc->stats.rfc, 4805 "Fragmented Packets Received "); 4806 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4807 CTLFLAG_RD, &sc->stats.roc, 4808 "Oversized Packets Received"); 4809 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4810 CTLFLAG_RD, &sc->stats.rjc, 4811 "Recevied Jabber"); 4812 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4813 CTLFLAG_RD, &sc->stats.rxerrc, 4814 "Receive Errors"); 4815 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4816 CTLFLAG_RD, &sc->stats.crcerrs, 4817 "CRC errors"); 4818 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4819 CTLFLAG_RD, &sc->stats.algnerrc, 4820 "Alignment Errors"); 4821 /* On 82575 these are collision counts */ 4822 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4823 CTLFLAG_RD, &sc->stats.cexterr, 4824 "Collision/Carrier extension errors"); 4825 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4826 CTLFLAG_RD, &sc->stats.xonrxc, 4827 "XON Received"); 4828 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4829 CTLFLAG_RD, &sc->stats.xontxc, 4830 "XON Transmitted"); 4831 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4832 CTLFLAG_RD, &sc->stats.xoffrxc, 4833 "XOFF Received"); 4834 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4835 CTLFLAG_RD, &sc->stats.xofftxc, 4836 "XOFF Transmitted"); 4837 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd", 4838 CTLFLAG_RD, &sc->stats.fcruc, 4839 "Unsupported Flow Control Received"); 4840 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd", 4841 CTLFLAG_RD, &sc->stats.mgprc, 4842 "Management Packets Received"); 4843 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop", 4844 CTLFLAG_RD, &sc->stats.mgpdc, 4845 "Management Packets Dropped"); 4846 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd", 4847 CTLFLAG_RD, &sc->stats.mgptc, 4848 "Management Packets Transmitted"); 4849 4850 /* Packet Reception Stats */ 4851 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4852 CTLFLAG_RD, &sc->stats.tpr, 4853 "Total Packets Received "); 4854 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4855 CTLFLAG_RD, &sc->stats.gprc, 4856 "Good Packets Received"); 4857 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4858 CTLFLAG_RD, &sc->stats.bprc, 4859 "Broadcast Packets Received"); 4860 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4861 CTLFLAG_RD, &sc->stats.mprc, 4862 "Multicast Packets Received"); 4863 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4864 CTLFLAG_RD, &sc->stats.prc64, 4865 "64 byte frames received "); 4866 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4867 CTLFLAG_RD, &sc->stats.prc127, 4868 "65-127 byte frames received"); 4869 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4870 CTLFLAG_RD, &sc->stats.prc255, 4871 "128-255 byte frames received"); 4872 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4873 CTLFLAG_RD, &sc->stats.prc511, 4874 "256-511 byte frames received"); 4875 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4876 CTLFLAG_RD, &sc->stats.prc1023, 4877 "512-1023 byte frames received"); 4878 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4879 CTLFLAG_RD, &sc->stats.prc1522, 4880 "1023-1522 byte frames received"); 4881 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4882 CTLFLAG_RD, &sc->stats.gorc, 4883 "Good Octets Received"); 4884 4885 /* Packet Transmission Stats */ 4886 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4887 CTLFLAG_RD, &sc->stats.gotc, 4888 "Good Octets Transmitted"); 4889 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4890 CTLFLAG_RD, &sc->stats.tpt, 4891 "Total Packets Transmitted"); 4892 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4893 CTLFLAG_RD, &sc->stats.gptc, 4894 "Good Packets Transmitted"); 4895 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4896 CTLFLAG_RD, &sc->stats.bptc, 4897 "Broadcast Packets Transmitted"); 4898 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4899 CTLFLAG_RD, &sc->stats.mptc, 4900 "Multicast Packets Transmitted"); 4901 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4902 CTLFLAG_RD, &sc->stats.ptc64, 4903 "64 byte frames transmitted "); 4904 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4905 CTLFLAG_RD, &sc->stats.ptc127, 4906 "65-127 byte frames transmitted"); 4907 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4908 CTLFLAG_RD, &sc->stats.ptc255, 4909 "128-255 byte frames transmitted"); 4910 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4911 CTLFLAG_RD, &sc->stats.ptc511, 4912 "256-511 byte frames transmitted"); 4913 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4914 CTLFLAG_RD, &sc->stats.ptc1023, 4915 "512-1023 byte frames transmitted"); 4916 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4917 CTLFLAG_RD, &sc->stats.ptc1522, 4918 "1024-1522 byte frames transmitted"); 4919 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4920 CTLFLAG_RD, &sc->stats.tsctc, 4921 "TSO Contexts Transmitted"); 4922 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4923 CTLFLAG_RD, &sc->stats.tsctfc, 4924 "TSO Contexts Failed"); 4925 4926 4927 /* Interrupt Stats */ 4928 4929 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4930 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4931 int_list = SYSCTL_CHILDREN(int_node); 4932 4933 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4934 CTLFLAG_RD, &sc->stats.iac, 4935 "Interrupt Assertion Count"); 4936 4937 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4938 CTLFLAG_RD, &sc->stats.icrxptc, 4939 "Interrupt Cause Rx Pkt Timer Expire Count"); 4940 4941 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4942 CTLFLAG_RD, &sc->stats.icrxatc, 4943 "Interrupt Cause Rx Abs Timer Expire Count"); 4944 4945 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4946 CTLFLAG_RD, &sc->stats.ictxptc, 4947 "Interrupt Cause Tx Pkt Timer Expire Count"); 4948 4949 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4950 CTLFLAG_RD, &sc->stats.ictxatc, 4951 "Interrupt Cause Tx Abs Timer Expire Count"); 4952 4953 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4954 CTLFLAG_RD, &sc->stats.ictxqec, 4955 "Interrupt Cause Tx Queue Empty Count"); 4956 4957 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4958 CTLFLAG_RD, &sc->stats.ictxqmtc, 4959 "Interrupt Cause Tx Queue Min Thresh Count"); 4960 4961 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4962 CTLFLAG_RD, &sc->stats.icrxdmtc, 4963 "Interrupt Cause Rx Desc Min Thresh Count"); 4964 4965 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4966 CTLFLAG_RD, &sc->stats.icrxoc, 4967 "Interrupt Cause Receiver Overrun Count"); 4968 } 4969 4970 static void 4971 em_fw_version_locked(if_ctx_t ctx) 4972 { 4973 struct e1000_softc *sc = iflib_get_softc(ctx); 4974 struct e1000_hw *hw = &sc->hw; 4975 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4976 uint16_t eep = 0; 4977 4978 /* 4979 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4980 * NVM locking model, so we do it in em_if_attach_pre() and store the 4981 * info in the softc 4982 */ 4983 ASSERT_CTX_LOCK_HELD(hw); 4984 4985 *fw_ver = (struct e1000_fw_version){0}; 4986 4987 if (hw->mac.type >= igb_mac_min) { 4988 /* 4989 * Use the Shared Code for igb(4) 4990 */ 4991 e1000_get_fw_version(hw, fw_ver); 4992 } else { 4993 /* 4994 * Otherwise, EEPROM version should be present on (almost?) all 4995 * devices here 4996 */ 4997 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4998 INIT_DEBUGOUT("can't get EEPROM version"); 4999 return; 5000 } 5001 5002 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 5003 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 5004 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 5005 } 5006 } 5007 5008 static void 5009 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 5010 { 5011 const char *space = ""; 5012 5013 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 5014 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 5015 fw_ver->eep_minor, fw_ver->eep_build); 5016 space = " "; 5017 } 5018 5019 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 5020 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 5021 space, fw_ver->invm_major, fw_ver->invm_minor, 5022 fw_ver->invm_img_type); 5023 space = " "; 5024 } 5025 5026 if (fw_ver->or_valid) { 5027 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 5028 space, fw_ver->or_major, fw_ver->or_build, 5029 fw_ver->or_patch); 5030 space = " "; 5031 } 5032 5033 if (fw_ver->etrack_id) 5034 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 5035 } 5036 5037 static void 5038 em_print_fw_version(struct e1000_softc *sc ) 5039 { 5040 device_t dev = sc->dev; 5041 struct sbuf *buf; 5042 int error = 0; 5043 5044 buf = sbuf_new_auto(); 5045 if (!buf) { 5046 device_printf(dev, "Could not allocate sbuf for output.\n"); 5047 return; 5048 } 5049 5050 em_sbuf_fw_version(&sc->fw_ver, buf); 5051 5052 error = sbuf_finish(buf); 5053 if (error) 5054 device_printf(dev, "Error finishing sbuf: %d\n", error); 5055 else if (sbuf_len(buf)) 5056 device_printf(dev, "%s\n", sbuf_data(buf)); 5057 5058 sbuf_delete(buf); 5059 } 5060 5061 static int 5062 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 5063 { 5064 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5065 device_t dev = sc->dev; 5066 struct sbuf *buf; 5067 int error = 0; 5068 5069 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5070 if (!buf) { 5071 device_printf(dev, "Could not allocate sbuf for output.\n"); 5072 return (ENOMEM); 5073 } 5074 5075 em_sbuf_fw_version(&sc->fw_ver, buf); 5076 5077 error = sbuf_finish(buf); 5078 if (error) 5079 device_printf(dev, "Error finishing sbuf: %d\n", error); 5080 5081 sbuf_delete(buf); 5082 5083 return (0); 5084 } 5085 5086 /********************************************************************** 5087 * 5088 * This routine provides a way to dump out the adapter eeprom, 5089 * often a useful debug/service tool. This only dumps the first 5090 * 32 words, stuff that matters is in that extent. 5091 * 5092 **********************************************************************/ 5093 static int 5094 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 5095 { 5096 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5097 int error; 5098 int result; 5099 5100 result = -1; 5101 error = sysctl_handle_int(oidp, &result, 0, req); 5102 5103 if (error || !req->newptr) 5104 return (error); 5105 5106 /* 5107 * This value will cause a hex dump of the 5108 * first 32 16-bit words of the EEPROM to 5109 * the screen. 5110 */ 5111 if (result == 1) 5112 em_print_nvm_info(sc); 5113 5114 return (error); 5115 } 5116 5117 static void 5118 em_print_nvm_info(struct e1000_softc *sc) 5119 { 5120 struct e1000_hw *hw = &sc->hw; 5121 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 5122 u16 eeprom_data; 5123 int i, j, row = 0; 5124 5125 /* Its a bit crude, but it gets the job done */ 5126 printf("\nInterface EEPROM Dump:\n"); 5127 printf("Offset\n0x0000 "); 5128 5129 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 5130 sx_xlock(iflib_ctx_lock); 5131 ASSERT_CTX_LOCK_HELD(hw); 5132 for (i = 0, j = 0; i < 32; i++, j++) { 5133 if (j == 8) { /* Make the offset block */ 5134 j = 0; ++row; 5135 printf("\n0x00%x0 ",row); 5136 } 5137 e1000_read_nvm(hw, i, 1, &eeprom_data); 5138 printf("%04x ", eeprom_data); 5139 } 5140 sx_xunlock(iflib_ctx_lock); 5141 printf("\n"); 5142 } 5143 5144 static int 5145 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 5146 { 5147 struct em_int_delay_info *info; 5148 struct e1000_softc *sc; 5149 u32 regval; 5150 int error, usecs, ticks; 5151 5152 info = (struct em_int_delay_info *) arg1; 5153 usecs = info->value; 5154 error = sysctl_handle_int(oidp, &usecs, 0, req); 5155 if (error != 0 || req->newptr == NULL) 5156 return (error); 5157 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 5158 return (EINVAL); 5159 info->value = usecs; 5160 ticks = EM_USECS_TO_TICKS(usecs); 5161 if (info->offset == E1000_ITR) /* units are 256ns here */ 5162 ticks *= 4; 5163 5164 sc = info->sc; 5165 5166 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 5167 regval = (regval & ~0xffff) | (ticks & 0xffff); 5168 /* Handle a few special cases. */ 5169 switch (info->offset) { 5170 case E1000_RDTR: 5171 break; 5172 case E1000_TIDV: 5173 if (ticks == 0) { 5174 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 5175 /* Don't write 0 into the TIDV register. */ 5176 regval++; 5177 } else 5178 sc->txd_cmd |= E1000_TXD_CMD_IDE; 5179 break; 5180 } 5181 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 5182 return (0); 5183 } 5184 5185 static void 5186 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 5187 const char *description, struct em_int_delay_info *info, 5188 int offset, int value) 5189 { 5190 info->sc = sc; 5191 info->offset = offset; 5192 info->value = value; 5193 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5194 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 5195 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 5196 info, 0, em_sysctl_int_delay, "I", description); 5197 } 5198 5199 /* 5200 * Set flow control using sysctl: 5201 * Flow control values: 5202 * 0 - off 5203 * 1 - rx pause 5204 * 2 - tx pause 5205 * 3 - full 5206 */ 5207 static int 5208 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 5209 { 5210 int error; 5211 static int input = 3; /* default is full */ 5212 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5213 5214 error = sysctl_handle_int(oidp, &input, 0, req); 5215 5216 if ((error) || (req->newptr == NULL)) 5217 return (error); 5218 5219 if (input == sc->fc) /* no change? */ 5220 return (error); 5221 5222 switch (input) { 5223 case e1000_fc_rx_pause: 5224 case e1000_fc_tx_pause: 5225 case e1000_fc_full: 5226 case e1000_fc_none: 5227 sc->hw.fc.requested_mode = input; 5228 sc->fc = input; 5229 break; 5230 default: 5231 /* Do nothing */ 5232 return (error); 5233 } 5234 5235 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 5236 e1000_force_mac_fc(&sc->hw); 5237 return (error); 5238 } 5239 5240 /* 5241 * Manage DMA Coalesce: 5242 * Control values: 5243 * 0/1 - off/on 5244 * Legal timer values are: 5245 * 250,500,1000-10000 in thousands 5246 */ 5247 static int 5248 igb_sysctl_dmac(SYSCTL_HANDLER_ARGS) 5249 { 5250 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5251 int error; 5252 5253 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); 5254 5255 if ((error) || (req->newptr == NULL)) 5256 return (error); 5257 5258 switch (sc->dmac) { 5259 case 0: 5260 /* Disabling */ 5261 break; 5262 case 1: /* Just enable and use default */ 5263 sc->dmac = 1000; 5264 break; 5265 case 250: 5266 case 500: 5267 case 1000: 5268 case 2000: 5269 case 3000: 5270 case 4000: 5271 case 5000: 5272 case 6000: 5273 case 7000: 5274 case 8000: 5275 case 9000: 5276 case 10000: 5277 /* Legal values - allow */ 5278 break; 5279 default: 5280 /* Do nothing, illegal value */ 5281 sc->dmac = 0; 5282 return (EINVAL); 5283 } 5284 /* Reinit the interface */ 5285 em_if_init(sc->ctx); 5286 return (error); 5287 } 5288 5289 /* 5290 * Manage Energy Efficient Ethernet: 5291 * Control values: 5292 * 0/1 - enabled/disabled 5293 */ 5294 static int 5295 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 5296 { 5297 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5298 int error, value; 5299 5300 if (sc->hw.mac.type < igb_mac_min) 5301 value = sc->hw.dev_spec.ich8lan.eee_disable; 5302 else 5303 value = sc->hw.dev_spec._82575.eee_disable; 5304 error = sysctl_handle_int(oidp, &value, 0, req); 5305 if (error || req->newptr == NULL) 5306 return (error); 5307 if (sc->hw.mac.type < igb_mac_min) 5308 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 5309 else 5310 sc->hw.dev_spec._82575.eee_disable = (value != 0); 5311 em_if_init(sc->ctx); 5312 5313 return (0); 5314 } 5315 5316 static int 5317 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5318 { 5319 struct e1000_softc *sc; 5320 int error; 5321 int result; 5322 5323 result = -1; 5324 error = sysctl_handle_int(oidp, &result, 0, req); 5325 5326 if (error || !req->newptr) 5327 return (error); 5328 5329 if (result == 1) { 5330 sc = (struct e1000_softc *) arg1; 5331 em_print_debug_info(sc); 5332 } 5333 5334 return (error); 5335 } 5336 5337 static int 5338 em_get_rs(SYSCTL_HANDLER_ARGS) 5339 { 5340 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5341 int error; 5342 int result; 5343 5344 result = 0; 5345 error = sysctl_handle_int(oidp, &result, 0, req); 5346 5347 if (error || !req->newptr || result != 1) 5348 return (error); 5349 em_dump_rs(sc); 5350 5351 return (error); 5352 } 5353 5354 static void 5355 em_if_debug(if_ctx_t ctx) 5356 { 5357 em_dump_rs(iflib_get_softc(ctx)); 5358 } 5359 5360 /* 5361 * This routine is meant to be fluid, add whatever is 5362 * needed for debugging a problem. -jfv 5363 */ 5364 static void 5365 em_print_debug_info(struct e1000_softc *sc) 5366 { 5367 device_t dev = iflib_get_dev(sc->ctx); 5368 if_t ifp = iflib_get_ifp(sc->ctx); 5369 struct tx_ring *txr = &sc->tx_queues->txr; 5370 struct rx_ring *rxr = &sc->rx_queues->rxr; 5371 5372 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5373 printf("Interface is RUNNING "); 5374 else 5375 printf("Interface is NOT RUNNING\n"); 5376 5377 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5378 printf("and INACTIVE\n"); 5379 else 5380 printf("and ACTIVE\n"); 5381 5382 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5383 device_printf(dev, "TX Queue %d ------\n", i); 5384 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5385 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5386 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5387 5388 } 5389 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5390 device_printf(dev, "RX Queue %d ------\n", j); 5391 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5392 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5393 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5394 } 5395 } 5396 5397 /* 5398 * 82574 only: 5399 * Write a new value to the EEPROM increasing the number of MSI-X 5400 * vectors from 3 to 5, for proper multiqueue support. 5401 */ 5402 static void 5403 em_enable_vectors_82574(if_ctx_t ctx) 5404 { 5405 struct e1000_softc *sc = iflib_get_softc(ctx); 5406 struct e1000_hw *hw = &sc->hw; 5407 device_t dev = iflib_get_dev(ctx); 5408 u16 edata; 5409 5410 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5411 if (bootverbose) 5412 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5413 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5414 device_printf(dev, "Writing to eeprom: increasing " 5415 "reported MSI-X vectors from 3 to 5...\n"); 5416 edata &= ~(EM_NVM_MSIX_N_MASK); 5417 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5418 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5419 e1000_update_nvm_checksum(hw); 5420 device_printf(dev, "Writing to eeprom: done\n"); 5421 } 5422 } 5423