1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) - lem-class legacy devices */ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 98 99 /* Intel(R) - em-class devices */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 197 /* required last entry */ 198 PVID_END 199 }; 200 201 static pci_vendor_info_t igb_vendor_info_array[] = 202 { 203 /* Intel(R) - igb-class devices */ 204 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 205 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 206 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 207 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 208 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 209 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 210 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 211 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 212 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 213 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 214 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 215 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 216 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 217 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 218 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 219 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 220 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 221 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 222 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 224 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 225 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 226 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 227 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 230 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 231 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 232 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 233 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 234 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 235 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 238 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 239 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 240 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 241 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 242 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 244 /* required last entry */ 245 PVID_END 246 }; 247 248 /********************************************************************* 249 * Function prototypes 250 *********************************************************************/ 251 static void *em_register(device_t); 252 static void *igb_register(device_t); 253 static int em_if_attach_pre(if_ctx_t); 254 static int em_if_attach_post(if_ctx_t); 255 static int em_if_detach(if_ctx_t); 256 static int em_if_shutdown(if_ctx_t); 257 static int em_if_suspend(if_ctx_t); 258 static int em_if_resume(if_ctx_t); 259 260 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 261 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 262 static void em_if_queues_free(if_ctx_t); 263 264 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 265 static void em_if_init(if_ctx_t); 266 static void em_if_stop(if_ctx_t); 267 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 268 static int em_if_media_change(if_ctx_t); 269 static int em_if_mtu_set(if_ctx_t, uint32_t); 270 static void em_if_timer(if_ctx_t, uint16_t); 271 static void em_if_vlan_register(if_ctx_t, u16); 272 static void em_if_vlan_unregister(if_ctx_t, u16); 273 static void em_if_watchdog_reset(if_ctx_t); 274 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 275 276 static void em_identify_hardware(if_ctx_t); 277 static int em_allocate_pci_resources(if_ctx_t); 278 static void em_free_pci_resources(if_ctx_t); 279 static void em_reset(if_ctx_t); 280 static int em_setup_interface(if_ctx_t); 281 static int em_setup_msix(if_ctx_t); 282 283 static void em_initialize_transmit_unit(if_ctx_t); 284 static void em_initialize_receive_unit(if_ctx_t); 285 286 static void em_if_intr_enable(if_ctx_t); 287 static void em_if_intr_disable(if_ctx_t); 288 static void igb_if_intr_enable(if_ctx_t); 289 static void igb_if_intr_disable(if_ctx_t); 290 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 291 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 292 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 293 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 294 static void em_if_multi_set(if_ctx_t); 295 static void em_if_update_admin_status(if_ctx_t); 296 static void em_if_debug(if_ctx_t); 297 static void em_update_stats_counters(struct e1000_softc *); 298 static void em_add_hw_stats(struct e1000_softc *); 299 static int em_if_set_promisc(if_ctx_t, int); 300 static bool em_if_vlan_filter_capable(if_ctx_t); 301 static bool em_if_vlan_filter_used(if_ctx_t); 302 static void em_if_vlan_filter_enable(struct e1000_softc *); 303 static void em_if_vlan_filter_disable(struct e1000_softc *); 304 static void em_if_vlan_filter_write(struct e1000_softc *); 305 static void em_setup_vlan_hw_support(if_ctx_t ctx); 306 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 307 static void em_print_nvm_info(struct e1000_softc *); 308 static void em_fw_version_locked(if_ctx_t); 309 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 310 static void em_print_fw_version(struct e1000_softc *); 311 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 312 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 313 static int em_get_rs(SYSCTL_HANDLER_ARGS); 314 static void em_print_debug_info(struct e1000_softc *); 315 static int em_is_valid_ether_addr(u8 *); 316 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 317 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 318 const char *, struct em_int_delay_info *, int, int); 319 /* Management and WOL Support */ 320 static void em_init_manageability(struct e1000_softc *); 321 static void em_release_manageability(struct e1000_softc *); 322 static void em_get_hw_control(struct e1000_softc *); 323 static void em_release_hw_control(struct e1000_softc *); 324 static void em_get_wakeup(if_ctx_t); 325 static void em_enable_wakeup(if_ctx_t); 326 static int em_enable_phy_wakeup(struct e1000_softc *); 327 static void em_disable_aspm(struct e1000_softc *); 328 329 int em_intr(void *); 330 331 /* MSI-X handlers */ 332 static int em_if_msix_intr_assign(if_ctx_t, int); 333 static int em_msix_link(void *); 334 static void em_handle_link(void *); 335 336 static void em_enable_vectors_82574(if_ctx_t); 337 338 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 339 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 340 static void em_if_led_func(if_ctx_t, int); 341 342 static int em_get_regs(SYSCTL_HANDLER_ARGS); 343 344 static void lem_smartspeed(struct e1000_softc *); 345 static void igb_configure_queues(struct e1000_softc *); 346 347 348 /********************************************************************* 349 * FreeBSD Device Interface Entry Points 350 *********************************************************************/ 351 static device_method_t em_methods[] = { 352 /* Device interface */ 353 DEVMETHOD(device_register, em_register), 354 DEVMETHOD(device_probe, iflib_device_probe), 355 DEVMETHOD(device_attach, iflib_device_attach), 356 DEVMETHOD(device_detach, iflib_device_detach), 357 DEVMETHOD(device_shutdown, iflib_device_shutdown), 358 DEVMETHOD(device_suspend, iflib_device_suspend), 359 DEVMETHOD(device_resume, iflib_device_resume), 360 DEVMETHOD_END 361 }; 362 363 static device_method_t igb_methods[] = { 364 /* Device interface */ 365 DEVMETHOD(device_register, igb_register), 366 DEVMETHOD(device_probe, iflib_device_probe), 367 DEVMETHOD(device_attach, iflib_device_attach), 368 DEVMETHOD(device_detach, iflib_device_detach), 369 DEVMETHOD(device_shutdown, iflib_device_shutdown), 370 DEVMETHOD(device_suspend, iflib_device_suspend), 371 DEVMETHOD(device_resume, iflib_device_resume), 372 DEVMETHOD_END 373 }; 374 375 376 static driver_t em_driver = { 377 "em", em_methods, sizeof(struct e1000_softc), 378 }; 379 380 DRIVER_MODULE(em, pci, em_driver, 0, 0); 381 382 MODULE_DEPEND(em, pci, 1, 1, 1); 383 MODULE_DEPEND(em, ether, 1, 1, 1); 384 MODULE_DEPEND(em, iflib, 1, 1, 1); 385 386 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 387 388 static driver_t igb_driver = { 389 "igb", igb_methods, sizeof(struct e1000_softc), 390 }; 391 392 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 393 394 MODULE_DEPEND(igb, pci, 1, 1, 1); 395 MODULE_DEPEND(igb, ether, 1, 1, 1); 396 MODULE_DEPEND(igb, iflib, 1, 1, 1); 397 398 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 399 400 static device_method_t em_if_methods[] = { 401 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 402 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 403 DEVMETHOD(ifdi_detach, em_if_detach), 404 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 405 DEVMETHOD(ifdi_suspend, em_if_suspend), 406 DEVMETHOD(ifdi_resume, em_if_resume), 407 DEVMETHOD(ifdi_init, em_if_init), 408 DEVMETHOD(ifdi_stop, em_if_stop), 409 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 410 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 411 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 412 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 413 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 414 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 415 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 416 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 417 DEVMETHOD(ifdi_media_status, em_if_media_status), 418 DEVMETHOD(ifdi_media_change, em_if_media_change), 419 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 420 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 421 DEVMETHOD(ifdi_timer, em_if_timer), 422 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 423 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 424 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 425 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 426 DEVMETHOD(ifdi_led_func, em_if_led_func), 427 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 428 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 429 DEVMETHOD(ifdi_debug, em_if_debug), 430 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 431 DEVMETHOD_END 432 }; 433 434 static driver_t em_if_driver = { 435 "em_if", em_if_methods, sizeof(struct e1000_softc) 436 }; 437 438 static device_method_t igb_if_methods[] = { 439 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 440 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 441 DEVMETHOD(ifdi_detach, em_if_detach), 442 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 443 DEVMETHOD(ifdi_suspend, em_if_suspend), 444 DEVMETHOD(ifdi_resume, em_if_resume), 445 DEVMETHOD(ifdi_init, em_if_init), 446 DEVMETHOD(ifdi_stop, em_if_stop), 447 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 448 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 449 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 450 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 451 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 452 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 453 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 454 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 455 DEVMETHOD(ifdi_media_status, em_if_media_status), 456 DEVMETHOD(ifdi_media_change, em_if_media_change), 457 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 458 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 459 DEVMETHOD(ifdi_timer, em_if_timer), 460 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 461 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 462 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 463 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 464 DEVMETHOD(ifdi_led_func, em_if_led_func), 465 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 466 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 467 DEVMETHOD(ifdi_debug, em_if_debug), 468 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 469 DEVMETHOD_END 470 }; 471 472 static driver_t igb_if_driver = { 473 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 474 }; 475 476 /********************************************************************* 477 * Tunable default values. 478 *********************************************************************/ 479 480 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 481 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 482 483 #define MAX_INTS_PER_SEC 8000 484 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 485 486 /* Allow common code without TSO */ 487 #ifndef CSUM_TSO 488 #define CSUM_TSO 0 489 #endif 490 491 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 492 "EM driver parameters"); 493 494 static int em_disable_crc_stripping = 0; 495 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 496 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 497 498 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 499 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 500 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 501 0, "Default transmit interrupt delay in usecs"); 502 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 503 0, "Default receive interrupt delay in usecs"); 504 505 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 506 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 507 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 508 &em_tx_abs_int_delay_dflt, 0, 509 "Default transmit interrupt delay limit in usecs"); 510 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 511 &em_rx_abs_int_delay_dflt, 0, 512 "Default receive interrupt delay limit in usecs"); 513 514 static int em_smart_pwr_down = false; 515 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 516 0, "Set to true to leave smart power down enabled on newer adapters"); 517 518 /* Controls whether promiscuous also shows bad packets */ 519 static int em_debug_sbp = false; 520 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 521 "Show bad packets in promiscuous mode"); 522 523 /* How many packets rxeof tries to clean at a time */ 524 static int em_rx_process_limit = 100; 525 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 526 &em_rx_process_limit, 0, 527 "Maximum number of received packets to process " 528 "at a time, -1 means unlimited"); 529 530 /* Energy efficient ethernet - default to OFF */ 531 static int eee_setting = 1; 532 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 533 "Enable Energy Efficient Ethernet"); 534 535 /* 536 ** Tuneable Interrupt rate 537 */ 538 static int em_max_interrupt_rate = 8000; 539 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 540 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 541 542 543 544 /* Global used in WOL setup with multiport cards */ 545 static int global_quad_port_a = 0; 546 547 extern struct if_txrx igb_txrx; 548 extern struct if_txrx em_txrx; 549 extern struct if_txrx lem_txrx; 550 551 static struct if_shared_ctx em_sctx_init = { 552 .isc_magic = IFLIB_MAGIC, 553 .isc_q_align = PAGE_SIZE, 554 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 555 .isc_tx_maxsegsize = PAGE_SIZE, 556 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 557 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 558 .isc_rx_maxsize = MJUM9BYTES, 559 .isc_rx_nsegments = 1, 560 .isc_rx_maxsegsize = MJUM9BYTES, 561 .isc_nfl = 1, 562 .isc_nrxqs = 1, 563 .isc_ntxqs = 1, 564 .isc_admin_intrcnt = 1, 565 .isc_vendor_info = em_vendor_info_array, 566 .isc_driver_version = em_driver_version, 567 .isc_driver = &em_if_driver, 568 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 569 570 .isc_nrxd_min = {EM_MIN_RXD}, 571 .isc_ntxd_min = {EM_MIN_TXD}, 572 .isc_nrxd_max = {EM_MAX_RXD}, 573 .isc_ntxd_max = {EM_MAX_TXD}, 574 .isc_nrxd_default = {EM_DEFAULT_RXD}, 575 .isc_ntxd_default = {EM_DEFAULT_TXD}, 576 }; 577 578 static struct if_shared_ctx igb_sctx_init = { 579 .isc_magic = IFLIB_MAGIC, 580 .isc_q_align = PAGE_SIZE, 581 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 582 .isc_tx_maxsegsize = PAGE_SIZE, 583 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 584 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 585 .isc_rx_maxsize = MJUM9BYTES, 586 .isc_rx_nsegments = 1, 587 .isc_rx_maxsegsize = MJUM9BYTES, 588 .isc_nfl = 1, 589 .isc_nrxqs = 1, 590 .isc_ntxqs = 1, 591 .isc_admin_intrcnt = 1, 592 .isc_vendor_info = igb_vendor_info_array, 593 .isc_driver_version = em_driver_version, 594 .isc_driver = &igb_if_driver, 595 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 596 597 .isc_nrxd_min = {EM_MIN_RXD}, 598 .isc_ntxd_min = {EM_MIN_TXD}, 599 .isc_nrxd_max = {IGB_MAX_RXD}, 600 .isc_ntxd_max = {IGB_MAX_TXD}, 601 .isc_nrxd_default = {EM_DEFAULT_RXD}, 602 .isc_ntxd_default = {EM_DEFAULT_TXD}, 603 }; 604 605 /***************************************************************** 606 * 607 * Dump Registers 608 * 609 ****************************************************************/ 610 #define IGB_REGS_LEN 739 611 612 static int em_get_regs(SYSCTL_HANDLER_ARGS) 613 { 614 struct e1000_softc *sc = (struct e1000_softc *)arg1; 615 struct e1000_hw *hw = &sc->hw; 616 struct sbuf *sb; 617 u32 *regs_buff; 618 int rc; 619 620 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 621 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 622 623 rc = sysctl_wire_old_buffer(req, 0); 624 MPASS(rc == 0); 625 if (rc != 0) { 626 free(regs_buff, M_DEVBUF); 627 return (rc); 628 } 629 630 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 631 MPASS(sb != NULL); 632 if (sb == NULL) { 633 free(regs_buff, M_DEVBUF); 634 return (ENOMEM); 635 } 636 637 /* General Registers */ 638 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 639 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 640 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 641 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 642 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 643 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 644 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 645 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 646 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 647 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 648 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 649 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 650 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 651 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 652 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 653 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 654 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 655 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 656 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 657 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 658 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 659 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 660 661 sbuf_printf(sb, "General Registers\n"); 662 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 663 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 664 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 665 666 sbuf_printf(sb, "Interrupt Registers\n"); 667 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 668 669 sbuf_printf(sb, "RX Registers\n"); 670 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 671 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 672 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 673 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 674 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 675 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 676 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 677 678 sbuf_printf(sb, "TX Registers\n"); 679 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 680 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 681 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 682 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 683 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 684 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 685 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 686 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 687 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 688 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 689 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 690 691 free(regs_buff, M_DEVBUF); 692 693 #ifdef DUMP_DESCS 694 { 695 if_softc_ctx_t scctx = sc->shared; 696 struct rx_ring *rxr = &rx_que->rxr; 697 struct tx_ring *txr = &tx_que->txr; 698 int ntxd = scctx->isc_ntxd[0]; 699 int nrxd = scctx->isc_nrxd[0]; 700 int j; 701 702 for (j = 0; j < nrxd; j++) { 703 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 704 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 705 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 706 } 707 708 for (j = 0; j < min(ntxd, 256); j++) { 709 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 710 711 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 712 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 713 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 714 715 } 716 } 717 #endif 718 719 rc = sbuf_finish(sb); 720 sbuf_delete(sb); 721 return(rc); 722 } 723 724 static void * 725 em_register(device_t dev) 726 { 727 return (&em_sctx_init); 728 } 729 730 static void * 731 igb_register(device_t dev) 732 { 733 return (&igb_sctx_init); 734 } 735 736 static int 737 em_set_num_queues(if_ctx_t ctx) 738 { 739 struct e1000_softc *sc = iflib_get_softc(ctx); 740 int maxqueues; 741 742 /* Sanity check based on HW */ 743 switch (sc->hw.mac.type) { 744 case e1000_82576: 745 case e1000_82580: 746 case e1000_i350: 747 case e1000_i354: 748 maxqueues = 8; 749 break; 750 case e1000_i210: 751 case e1000_82575: 752 maxqueues = 4; 753 break; 754 case e1000_i211: 755 case e1000_82574: 756 maxqueues = 2; 757 break; 758 default: 759 maxqueues = 1; 760 break; 761 } 762 763 return (maxqueues); 764 } 765 766 #define LEM_CAPS \ 767 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 768 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 769 770 #define EM_CAPS \ 771 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 772 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 773 IFCAP_LRO | IFCAP_VLAN_HWTSO 774 775 #define IGB_CAPS \ 776 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 777 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 778 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 779 IFCAP_TSO6 780 781 /********************************************************************* 782 * Device initialization routine 783 * 784 * The attach entry point is called when the driver is being loaded. 785 * This routine identifies the type of hardware, allocates all resources 786 * and initializes the hardware. 787 * 788 * return 0 on success, positive on failure 789 *********************************************************************/ 790 static int 791 em_if_attach_pre(if_ctx_t ctx) 792 { 793 struct e1000_softc *sc; 794 if_softc_ctx_t scctx; 795 device_t dev; 796 struct e1000_hw *hw; 797 struct sysctl_oid_list *child; 798 struct sysctl_ctx_list *ctx_list; 799 int error = 0; 800 801 INIT_DEBUGOUT("em_if_attach_pre: begin"); 802 dev = iflib_get_dev(ctx); 803 sc = iflib_get_softc(ctx); 804 805 sc->ctx = sc->osdep.ctx = ctx; 806 sc->dev = sc->osdep.dev = dev; 807 scctx = sc->shared = iflib_get_softc_ctx(ctx); 808 sc->media = iflib_get_media(ctx); 809 hw = &sc->hw; 810 811 sc->tx_process_limit = scctx->isc_ntxd[0]; 812 813 /* Determine hardware and mac info */ 814 em_identify_hardware(ctx); 815 816 /* SYSCTL stuff */ 817 ctx_list = device_get_sysctl_ctx(dev); 818 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 819 820 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 821 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 822 em_sysctl_nvm_info, "I", "NVM Information"); 823 824 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 825 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 826 em_sysctl_print_fw_version, "A", 827 "Prints FW/NVM Versions"); 828 829 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 830 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 831 em_sysctl_debug_info, "I", "Debug Information"); 832 833 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 834 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 835 em_set_flowcntl, "I", "Flow Control"); 836 837 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 838 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 839 em_get_regs, "A", "Dump Registers"); 840 841 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 842 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 843 em_get_rs, "I", "Dump RS indexes"); 844 845 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 846 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 847 if (bootverbose) 848 device_printf(dev, "attach_pre capping queues at %d\n", 849 scctx->isc_ntxqsets_max); 850 851 if (hw->mac.type >= igb_mac_min) { 852 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 853 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 854 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 855 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 856 scctx->isc_txrx = &igb_txrx; 857 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 858 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 859 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 860 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 861 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 862 CSUM_IP6_TCP | CSUM_IP6_UDP; 863 if (hw->mac.type != e1000_82575) 864 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 865 /* 866 ** Some new devices, as with ixgbe, now may 867 ** use a different BAR, so we need to keep 868 ** track of which is used. 869 */ 870 scctx->isc_msix_bar = pci_msix_table_bar(dev); 871 } else if (hw->mac.type >= em_mac_min) { 872 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 873 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 874 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 875 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 876 scctx->isc_txrx = &em_txrx; 877 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 878 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 879 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 880 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 881 /* 882 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 883 * by default as we don't have workarounds for all associated 884 * silicon errata. E. g., with several MACs such as 82573E, 885 * TSO only works at Gigabit speed and otherwise can cause the 886 * hardware to hang (which also would be next to impossible to 887 * work around given that already queued TSO-using descriptors 888 * would need to be flushed and vlan(4) reconfigured at runtime 889 * in case of a link speed change). Moreover, MACs like 82579 890 * still can hang at Gigabit even with all publicly documented 891 * TSO workarounds implemented. Generally, the penality of 892 * these workarounds is rather high and may involve copying 893 * mbuf data around so advantages of TSO lapse. Still, TSO may 894 * work for a few MACs of this class - at least when sticking 895 * with Gigabit - in which case users may enable TSO manually. 896 */ 897 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 898 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 899 /* 900 * We support MSI-X with 82574 only, but indicate to iflib(4) 901 * that it shall give MSI at least a try with other devices. 902 */ 903 if (hw->mac.type == e1000_82574) { 904 scctx->isc_msix_bar = pci_msix_table_bar(dev);; 905 } else { 906 scctx->isc_msix_bar = -1; 907 scctx->isc_disable_msix = 1; 908 } 909 } else { 910 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 911 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 912 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 913 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 914 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 915 scctx->isc_txrx = &lem_txrx; 916 scctx->isc_capabilities = LEM_CAPS; 917 if (hw->mac.type < e1000_82543) 918 scctx->isc_capabilities &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 919 /* 82541ER doesn't do HW tagging */ 920 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM) 921 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 922 /* INTx only */ 923 scctx->isc_msix_bar = 0; 924 scctx->isc_capenable = scctx->isc_capabilities; 925 } 926 927 /* Setup PCI resources */ 928 if (em_allocate_pci_resources(ctx)) { 929 device_printf(dev, "Allocation of PCI resources failed\n"); 930 error = ENXIO; 931 goto err_pci; 932 } 933 934 /* 935 ** For ICH8 and family we need to 936 ** map the flash memory, and this 937 ** must happen after the MAC is 938 ** identified 939 */ 940 if ((hw->mac.type == e1000_ich8lan) || 941 (hw->mac.type == e1000_ich9lan) || 942 (hw->mac.type == e1000_ich10lan) || 943 (hw->mac.type == e1000_pchlan) || 944 (hw->mac.type == e1000_pch2lan) || 945 (hw->mac.type == e1000_pch_lpt)) { 946 int rid = EM_BAR_TYPE_FLASH; 947 sc->flash = bus_alloc_resource_any(dev, 948 SYS_RES_MEMORY, &rid, RF_ACTIVE); 949 if (sc->flash == NULL) { 950 device_printf(dev, "Mapping of Flash failed\n"); 951 error = ENXIO; 952 goto err_pci; 953 } 954 /* This is used in the shared code */ 955 hw->flash_address = (u8 *)sc->flash; 956 sc->osdep.flash_bus_space_tag = 957 rman_get_bustag(sc->flash); 958 sc->osdep.flash_bus_space_handle = 959 rman_get_bushandle(sc->flash); 960 } 961 /* 962 ** In the new SPT device flash is not a 963 ** separate BAR, rather it is also in BAR0, 964 ** so use the same tag and an offset handle for the 965 ** FLASH read/write macros in the shared code. 966 */ 967 else if (hw->mac.type >= e1000_pch_spt) { 968 sc->osdep.flash_bus_space_tag = 969 sc->osdep.mem_bus_space_tag; 970 sc->osdep.flash_bus_space_handle = 971 sc->osdep.mem_bus_space_handle 972 + E1000_FLASH_BASE_ADDR; 973 } 974 975 /* Do Shared Code initialization */ 976 error = e1000_setup_init_funcs(hw, true); 977 if (error) { 978 device_printf(dev, "Setup of Shared code failed, error %d\n", 979 error); 980 error = ENXIO; 981 goto err_pci; 982 } 983 984 em_setup_msix(ctx); 985 e1000_get_bus_info(hw); 986 987 /* Set up some sysctls for the tunable interrupt delays */ 988 em_add_int_delay_sysctl(sc, "rx_int_delay", 989 "receive interrupt delay in usecs", &sc->rx_int_delay, 990 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 991 em_add_int_delay_sysctl(sc, "tx_int_delay", 992 "transmit interrupt delay in usecs", &sc->tx_int_delay, 993 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 994 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 995 "receive interrupt delay limit in usecs", 996 &sc->rx_abs_int_delay, 997 E1000_REGISTER(hw, E1000_RADV), 998 em_rx_abs_int_delay_dflt); 999 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1000 "transmit interrupt delay limit in usecs", 1001 &sc->tx_abs_int_delay, 1002 E1000_REGISTER(hw, E1000_TADV), 1003 em_tx_abs_int_delay_dflt); 1004 em_add_int_delay_sysctl(sc, "itr", 1005 "interrupt delay limit in usecs/4", 1006 &sc->tx_itr, 1007 E1000_REGISTER(hw, E1000_ITR), 1008 DEFAULT_ITR); 1009 1010 hw->mac.autoneg = DO_AUTO_NEG; 1011 hw->phy.autoneg_wait_to_complete = false; 1012 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1013 1014 if (hw->mac.type < em_mac_min) { 1015 e1000_init_script_state_82541(hw, true); 1016 e1000_set_tbi_compatibility_82543(hw, true); 1017 } 1018 /* Copper options */ 1019 if (hw->phy.media_type == e1000_media_type_copper) { 1020 hw->phy.mdix = AUTO_ALL_MODES; 1021 hw->phy.disable_polarity_correction = false; 1022 hw->phy.ms_type = EM_MASTER_SLAVE; 1023 } 1024 1025 /* 1026 * Set the frame limits assuming 1027 * standard ethernet sized frames. 1028 */ 1029 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1030 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1031 1032 /* 1033 * This controls when hardware reports transmit completion 1034 * status. 1035 */ 1036 hw->mac.report_tx_early = 1; 1037 1038 /* Allocate multicast array memory. */ 1039 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1040 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1041 if (sc->mta == NULL) { 1042 device_printf(dev, "Can not allocate multicast setup array\n"); 1043 error = ENOMEM; 1044 goto err_late; 1045 } 1046 1047 /* Check SOL/IDER usage */ 1048 if (e1000_check_reset_block(hw)) 1049 device_printf(dev, "PHY reset is blocked" 1050 " due to SOL/IDER session.\n"); 1051 1052 /* Sysctl for setting Energy Efficient Ethernet */ 1053 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1054 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1055 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1056 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1057 1058 /* 1059 ** Start from a known state, this is 1060 ** important in reading the nvm and 1061 ** mac from that. 1062 */ 1063 e1000_reset_hw(hw); 1064 1065 /* Make sure we have a good EEPROM before we read from it */ 1066 if (e1000_validate_nvm_checksum(hw) < 0) { 1067 /* 1068 ** Some PCI-E parts fail the first check due to 1069 ** the link being in sleep state, call it again, 1070 ** if it fails a second time its a real issue. 1071 */ 1072 if (e1000_validate_nvm_checksum(hw) < 0) { 1073 device_printf(dev, 1074 "The EEPROM Checksum Is Not Valid\n"); 1075 error = EIO; 1076 goto err_late; 1077 } 1078 } 1079 1080 /* Copy the permanent MAC address out of the EEPROM */ 1081 if (e1000_read_mac_addr(hw) < 0) { 1082 device_printf(dev, "EEPROM read error while reading MAC" 1083 " address\n"); 1084 error = EIO; 1085 goto err_late; 1086 } 1087 1088 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1089 if (sc->vf_ifp) { 1090 ether_gen_addr(iflib_get_ifp(ctx), 1091 (struct ether_addr *)hw->mac.addr); 1092 } else { 1093 device_printf(dev, "Invalid MAC address\n"); 1094 error = EIO; 1095 goto err_late; 1096 } 1097 } 1098 1099 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1100 em_fw_version_locked(ctx); 1101 1102 em_print_fw_version(sc); 1103 1104 /* Disable ULP support */ 1105 e1000_disable_ulp_lpt_lp(hw, true); 1106 1107 /* 1108 * Get Wake-on-Lan and Management info for later use 1109 */ 1110 em_get_wakeup(ctx); 1111 1112 /* Enable only WOL MAGIC by default */ 1113 scctx->isc_capenable &= ~IFCAP_WOL; 1114 if (sc->wol != 0) 1115 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1116 1117 iflib_set_mac(ctx, hw->mac.addr); 1118 1119 return (0); 1120 1121 err_late: 1122 em_release_hw_control(sc); 1123 err_pci: 1124 em_free_pci_resources(ctx); 1125 free(sc->mta, M_DEVBUF); 1126 1127 return (error); 1128 } 1129 1130 static int 1131 em_if_attach_post(if_ctx_t ctx) 1132 { 1133 struct e1000_softc *sc = iflib_get_softc(ctx); 1134 struct e1000_hw *hw = &sc->hw; 1135 int error = 0; 1136 1137 /* Setup OS specific network interface */ 1138 error = em_setup_interface(ctx); 1139 if (error != 0) { 1140 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1141 goto err_late; 1142 } 1143 1144 em_reset(ctx); 1145 1146 /* Initialize statistics */ 1147 em_update_stats_counters(sc); 1148 hw->mac.get_link_status = 1; 1149 em_if_update_admin_status(ctx); 1150 em_add_hw_stats(sc); 1151 1152 /* Non-AMT based hardware can now take control from firmware */ 1153 if (sc->has_manage && !sc->has_amt) 1154 em_get_hw_control(sc); 1155 1156 INIT_DEBUGOUT("em_if_attach_post: end"); 1157 1158 return (0); 1159 1160 err_late: 1161 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1162 return (error); 1163 } 1164 1165 /********************************************************************* 1166 * Device removal routine 1167 * 1168 * The detach entry point is called when the driver is being removed. 1169 * This routine stops the adapter and deallocates all the resources 1170 * that were allocated for driver operation. 1171 * 1172 * return 0 on success, positive on failure 1173 *********************************************************************/ 1174 static int 1175 em_if_detach(if_ctx_t ctx) 1176 { 1177 struct e1000_softc *sc = iflib_get_softc(ctx); 1178 1179 INIT_DEBUGOUT("em_if_detach: begin"); 1180 1181 e1000_phy_hw_reset(&sc->hw); 1182 1183 em_release_manageability(sc); 1184 em_release_hw_control(sc); 1185 em_free_pci_resources(ctx); 1186 free(sc->mta, M_DEVBUF); 1187 sc->mta = NULL; 1188 1189 return (0); 1190 } 1191 1192 /********************************************************************* 1193 * 1194 * Shutdown entry point 1195 * 1196 **********************************************************************/ 1197 1198 static int 1199 em_if_shutdown(if_ctx_t ctx) 1200 { 1201 return em_if_suspend(ctx); 1202 } 1203 1204 /* 1205 * Suspend/resume device methods. 1206 */ 1207 static int 1208 em_if_suspend(if_ctx_t ctx) 1209 { 1210 struct e1000_softc *sc = iflib_get_softc(ctx); 1211 1212 em_release_manageability(sc); 1213 em_release_hw_control(sc); 1214 em_enable_wakeup(ctx); 1215 return (0); 1216 } 1217 1218 static int 1219 em_if_resume(if_ctx_t ctx) 1220 { 1221 struct e1000_softc *sc = iflib_get_softc(ctx); 1222 1223 if (sc->hw.mac.type == e1000_pch2lan) 1224 e1000_resume_workarounds_pchlan(&sc->hw); 1225 em_if_init(ctx); 1226 em_init_manageability(sc); 1227 1228 return(0); 1229 } 1230 1231 static int 1232 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1233 { 1234 int max_frame_size; 1235 struct e1000_softc *sc = iflib_get_softc(ctx); 1236 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1237 1238 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1239 1240 switch (sc->hw.mac.type) { 1241 case e1000_82571: 1242 case e1000_82572: 1243 case e1000_ich9lan: 1244 case e1000_ich10lan: 1245 case e1000_pch2lan: 1246 case e1000_pch_lpt: 1247 case e1000_pch_spt: 1248 case e1000_pch_cnp: 1249 case e1000_pch_tgp: 1250 case e1000_pch_adp: 1251 case e1000_pch_mtp: 1252 case e1000_82574: 1253 case e1000_82583: 1254 case e1000_80003es2lan: 1255 /* 9K Jumbo Frame size */ 1256 max_frame_size = 9234; 1257 break; 1258 case e1000_pchlan: 1259 max_frame_size = 4096; 1260 break; 1261 case e1000_82542: 1262 case e1000_ich8lan: 1263 /* Adapters that do not support jumbo frames */ 1264 max_frame_size = ETHER_MAX_LEN; 1265 break; 1266 default: 1267 if (sc->hw.mac.type >= igb_mac_min) 1268 max_frame_size = 9234; 1269 else /* lem */ 1270 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1271 } 1272 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1273 return (EINVAL); 1274 } 1275 1276 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1277 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1278 return (0); 1279 } 1280 1281 /********************************************************************* 1282 * Init entry point 1283 * 1284 * This routine is used in two ways. It is used by the stack as 1285 * init entry point in network interface structure. It is also used 1286 * by the driver as a hw/sw initialization routine to get to a 1287 * consistent state. 1288 * 1289 **********************************************************************/ 1290 static void 1291 em_if_init(if_ctx_t ctx) 1292 { 1293 struct e1000_softc *sc = iflib_get_softc(ctx); 1294 if_softc_ctx_t scctx = sc->shared; 1295 struct ifnet *ifp = iflib_get_ifp(ctx); 1296 struct em_tx_queue *tx_que; 1297 int i; 1298 1299 INIT_DEBUGOUT("em_if_init: begin"); 1300 1301 /* Get the latest mac address, User can use a LAA */ 1302 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1303 ETHER_ADDR_LEN); 1304 1305 /* Put the address into the Receive Address Array */ 1306 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1307 1308 /* 1309 * With the 82571 adapter, RAR[0] may be overwritten 1310 * when the other port is reset, we make a duplicate 1311 * in RAR[14] for that eventuality, this assures 1312 * the interface continues to function. 1313 */ 1314 if (sc->hw.mac.type == e1000_82571) { 1315 e1000_set_laa_state_82571(&sc->hw, true); 1316 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1317 E1000_RAR_ENTRIES - 1); 1318 } 1319 1320 1321 /* Initialize the hardware */ 1322 em_reset(ctx); 1323 em_if_update_admin_status(ctx); 1324 1325 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1326 struct tx_ring *txr = &tx_que->txr; 1327 1328 txr->tx_rs_cidx = txr->tx_rs_pidx; 1329 1330 /* Initialize the last processed descriptor to be the end of 1331 * the ring, rather than the start, so that we avoid an 1332 * off-by-one error when calculating how many descriptors are 1333 * done in the credits_update function. 1334 */ 1335 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1336 } 1337 1338 /* Setup VLAN support, basic and offload if available */ 1339 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1340 1341 /* Clear bad data from Rx FIFOs */ 1342 if (sc->hw.mac.type >= igb_mac_min) 1343 e1000_rx_fifo_flush_base(&sc->hw); 1344 1345 /* Configure for OS presence */ 1346 em_init_manageability(sc); 1347 1348 /* Prepare transmit descriptors and buffers */ 1349 em_initialize_transmit_unit(ctx); 1350 1351 /* Setup Multicast table */ 1352 em_if_multi_set(ctx); 1353 1354 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1355 em_initialize_receive_unit(ctx); 1356 1357 /* Set up VLAN support and filter */ 1358 em_setup_vlan_hw_support(ctx); 1359 1360 /* Don't lose promiscuous settings */ 1361 em_if_set_promisc(ctx, if_getflags(ifp)); 1362 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1363 1364 /* MSI-X configuration for 82574 */ 1365 if (sc->hw.mac.type == e1000_82574) { 1366 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1367 1368 tmp |= E1000_CTRL_EXT_PBA_CLR; 1369 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1370 /* Set the IVAR - interrupt vector routing. */ 1371 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1372 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1373 igb_configure_queues(sc); 1374 1375 /* this clears any pending interrupts */ 1376 E1000_READ_REG(&sc->hw, E1000_ICR); 1377 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1378 1379 /* AMT based hardware can now take control from firmware */ 1380 if (sc->has_manage && sc->has_amt) 1381 em_get_hw_control(sc); 1382 1383 /* Set Energy Efficient Ethernet */ 1384 if (sc->hw.mac.type >= igb_mac_min && 1385 sc->hw.phy.media_type == e1000_media_type_copper) { 1386 if (sc->hw.mac.type == e1000_i354) 1387 e1000_set_eee_i354(&sc->hw, true, true); 1388 else 1389 e1000_set_eee_i350(&sc->hw, true, true); 1390 } 1391 } 1392 1393 /********************************************************************* 1394 * 1395 * Fast Legacy/MSI Combined Interrupt Service routine 1396 * 1397 *********************************************************************/ 1398 int 1399 em_intr(void *arg) 1400 { 1401 struct e1000_softc *sc = arg; 1402 if_ctx_t ctx = sc->ctx; 1403 u32 reg_icr; 1404 1405 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1406 1407 /* Hot eject? */ 1408 if (reg_icr == 0xffffffff) 1409 return FILTER_STRAY; 1410 1411 /* Definitely not our interrupt. */ 1412 if (reg_icr == 0x0) 1413 return FILTER_STRAY; 1414 1415 /* 1416 * Starting with the 82571 chip, bit 31 should be used to 1417 * determine whether the interrupt belongs to us. 1418 */ 1419 if (sc->hw.mac.type >= e1000_82571 && 1420 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1421 return FILTER_STRAY; 1422 1423 /* 1424 * Only MSI-X interrupts have one-shot behavior by taking advantage 1425 * of the EIAC register. Thus, explicitly disable interrupts. This 1426 * also works around the MSI message reordering errata on certain 1427 * systems. 1428 */ 1429 IFDI_INTR_DISABLE(ctx); 1430 1431 /* Link status change */ 1432 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1433 em_handle_link(ctx); 1434 1435 if (reg_icr & E1000_ICR_RXO) 1436 sc->rx_overruns++; 1437 1438 return (FILTER_SCHEDULE_THREAD); 1439 } 1440 1441 static int 1442 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1443 { 1444 struct e1000_softc *sc = iflib_get_softc(ctx); 1445 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1446 1447 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1448 return (0); 1449 } 1450 1451 static int 1452 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1453 { 1454 struct e1000_softc *sc = iflib_get_softc(ctx); 1455 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1456 1457 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1458 return (0); 1459 } 1460 1461 static int 1462 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1463 { 1464 struct e1000_softc *sc = iflib_get_softc(ctx); 1465 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1466 1467 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1468 return (0); 1469 } 1470 1471 static int 1472 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1473 { 1474 struct e1000_softc *sc = iflib_get_softc(ctx); 1475 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1476 1477 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1478 return (0); 1479 } 1480 1481 /********************************************************************* 1482 * 1483 * MSI-X RX Interrupt Service routine 1484 * 1485 **********************************************************************/ 1486 static int 1487 em_msix_que(void *arg) 1488 { 1489 struct em_rx_queue *que = arg; 1490 1491 ++que->irqs; 1492 1493 return (FILTER_SCHEDULE_THREAD); 1494 } 1495 1496 /********************************************************************* 1497 * 1498 * MSI-X Link Fast Interrupt Service routine 1499 * 1500 **********************************************************************/ 1501 static int 1502 em_msix_link(void *arg) 1503 { 1504 struct e1000_softc *sc = arg; 1505 u32 reg_icr; 1506 1507 ++sc->link_irq; 1508 MPASS(sc->hw.back != NULL); 1509 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1510 1511 if (reg_icr & E1000_ICR_RXO) 1512 sc->rx_overruns++; 1513 1514 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1515 em_handle_link(sc->ctx); 1516 1517 /* Re-arm unconditionally */ 1518 if (sc->hw.mac.type >= igb_mac_min) { 1519 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1520 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1521 } else if (sc->hw.mac.type == e1000_82574) { 1522 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1523 E1000_IMS_OTHER); 1524 /* 1525 * Because we must read the ICR for this interrupt it may 1526 * clear other causes using autoclear, for this reason we 1527 * simply create a soft interrupt for all these vectors. 1528 */ 1529 if (reg_icr) 1530 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1531 } else 1532 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1533 1534 return (FILTER_HANDLED); 1535 } 1536 1537 static void 1538 em_handle_link(void *context) 1539 { 1540 if_ctx_t ctx = context; 1541 struct e1000_softc *sc = iflib_get_softc(ctx); 1542 1543 sc->hw.mac.get_link_status = 1; 1544 iflib_admin_intr_deferred(ctx); 1545 } 1546 1547 /********************************************************************* 1548 * 1549 * Media Ioctl callback 1550 * 1551 * This routine is called whenever the user queries the status of 1552 * the interface using ifconfig. 1553 * 1554 **********************************************************************/ 1555 static void 1556 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1557 { 1558 struct e1000_softc *sc = iflib_get_softc(ctx); 1559 u_char fiber_type = IFM_1000_SX; 1560 1561 INIT_DEBUGOUT("em_if_media_status: begin"); 1562 1563 iflib_admin_intr_deferred(ctx); 1564 1565 ifmr->ifm_status = IFM_AVALID; 1566 ifmr->ifm_active = IFM_ETHER; 1567 1568 if (!sc->link_active) { 1569 return; 1570 } 1571 1572 ifmr->ifm_status |= IFM_ACTIVE; 1573 1574 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1575 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1576 if (sc->hw.mac.type == e1000_82545) 1577 fiber_type = IFM_1000_LX; 1578 ifmr->ifm_active |= fiber_type | IFM_FDX; 1579 } else { 1580 switch (sc->link_speed) { 1581 case 10: 1582 ifmr->ifm_active |= IFM_10_T; 1583 break; 1584 case 100: 1585 ifmr->ifm_active |= IFM_100_TX; 1586 break; 1587 case 1000: 1588 ifmr->ifm_active |= IFM_1000_T; 1589 break; 1590 } 1591 if (sc->link_duplex == FULL_DUPLEX) 1592 ifmr->ifm_active |= IFM_FDX; 1593 else 1594 ifmr->ifm_active |= IFM_HDX; 1595 } 1596 } 1597 1598 /********************************************************************* 1599 * 1600 * Media Ioctl callback 1601 * 1602 * This routine is called when the user changes speed/duplex using 1603 * media/mediopt option with ifconfig. 1604 * 1605 **********************************************************************/ 1606 static int 1607 em_if_media_change(if_ctx_t ctx) 1608 { 1609 struct e1000_softc *sc = iflib_get_softc(ctx); 1610 struct ifmedia *ifm = iflib_get_media(ctx); 1611 1612 INIT_DEBUGOUT("em_if_media_change: begin"); 1613 1614 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1615 return (EINVAL); 1616 1617 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1618 case IFM_AUTO: 1619 sc->hw.mac.autoneg = DO_AUTO_NEG; 1620 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1621 break; 1622 case IFM_1000_LX: 1623 case IFM_1000_SX: 1624 case IFM_1000_T: 1625 sc->hw.mac.autoneg = DO_AUTO_NEG; 1626 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1627 break; 1628 case IFM_100_TX: 1629 sc->hw.mac.autoneg = DO_AUTO_NEG; 1630 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 1631 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 1632 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1633 } else { 1634 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 1635 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1636 } 1637 break; 1638 case IFM_10_T: 1639 sc->hw.mac.autoneg = DO_AUTO_NEG; 1640 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 1641 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 1642 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1643 } else { 1644 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 1645 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1646 } 1647 break; 1648 default: 1649 device_printf(sc->dev, "Unsupported media type\n"); 1650 } 1651 1652 em_if_init(ctx); 1653 1654 return (0); 1655 } 1656 1657 static int 1658 em_if_set_promisc(if_ctx_t ctx, int flags) 1659 { 1660 struct e1000_softc *sc = iflib_get_softc(ctx); 1661 struct ifnet *ifp = iflib_get_ifp(ctx); 1662 u32 reg_rctl; 1663 int mcnt = 0; 1664 1665 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1666 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1667 if (flags & IFF_ALLMULTI) 1668 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1669 else 1670 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1671 1672 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1673 reg_rctl &= (~E1000_RCTL_MPE); 1674 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1675 1676 if (flags & IFF_PROMISC) { 1677 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1678 em_if_vlan_filter_disable(sc); 1679 /* Turn this on if you want to see bad packets */ 1680 if (em_debug_sbp) 1681 reg_rctl |= E1000_RCTL_SBP; 1682 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1683 } else { 1684 if (flags & IFF_ALLMULTI) { 1685 reg_rctl |= E1000_RCTL_MPE; 1686 reg_rctl &= ~E1000_RCTL_UPE; 1687 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1688 } 1689 if (em_if_vlan_filter_used(ctx)) 1690 em_if_vlan_filter_enable(sc); 1691 } 1692 return (0); 1693 } 1694 1695 static u_int 1696 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1697 { 1698 u8 *mta = arg; 1699 1700 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1701 return (0); 1702 1703 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1704 1705 return (1); 1706 } 1707 1708 /********************************************************************* 1709 * Multicast Update 1710 * 1711 * This routine is called whenever multicast address list is updated. 1712 * 1713 **********************************************************************/ 1714 static void 1715 em_if_multi_set(if_ctx_t ctx) 1716 { 1717 struct e1000_softc *sc = iflib_get_softc(ctx); 1718 struct ifnet *ifp = iflib_get_ifp(ctx); 1719 u8 *mta; /* Multicast array memory */ 1720 u32 reg_rctl = 0; 1721 int mcnt = 0; 1722 1723 IOCTL_DEBUGOUT("em_set_multi: begin"); 1724 1725 mta = sc->mta; 1726 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1727 1728 if (sc->hw.mac.type == e1000_82542 && 1729 sc->hw.revision_id == E1000_REVISION_2) { 1730 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1731 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1732 e1000_pci_clear_mwi(&sc->hw); 1733 reg_rctl |= E1000_RCTL_RST; 1734 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1735 msec_delay(5); 1736 } 1737 1738 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1739 1740 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1741 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1742 1743 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1744 1745 if (if_getflags(ifp) & IFF_PROMISC) 1746 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1747 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1748 if_getflags(ifp) & IFF_ALLMULTI) { 1749 reg_rctl |= E1000_RCTL_MPE; 1750 reg_rctl &= ~E1000_RCTL_UPE; 1751 } else 1752 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1753 1754 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1755 1756 if (sc->hw.mac.type == e1000_82542 && 1757 sc->hw.revision_id == E1000_REVISION_2) { 1758 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1759 reg_rctl &= ~E1000_RCTL_RST; 1760 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1761 msec_delay(5); 1762 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1763 e1000_pci_set_mwi(&sc->hw); 1764 } 1765 } 1766 1767 /********************************************************************* 1768 * Timer routine 1769 * 1770 * This routine schedules em_if_update_admin_status() to check for 1771 * link status and to gather statistics as well as to perform some 1772 * controller-specific hardware patting. 1773 * 1774 **********************************************************************/ 1775 static void 1776 em_if_timer(if_ctx_t ctx, uint16_t qid) 1777 { 1778 1779 if (qid != 0) 1780 return; 1781 1782 iflib_admin_intr_deferred(ctx); 1783 } 1784 1785 static void 1786 em_if_update_admin_status(if_ctx_t ctx) 1787 { 1788 struct e1000_softc *sc = iflib_get_softc(ctx); 1789 struct e1000_hw *hw = &sc->hw; 1790 device_t dev = iflib_get_dev(ctx); 1791 u32 link_check, thstat, ctrl; 1792 1793 link_check = thstat = ctrl = 0; 1794 /* Get the cached link value or read phy for real */ 1795 switch (hw->phy.media_type) { 1796 case e1000_media_type_copper: 1797 if (hw->mac.get_link_status) { 1798 if (hw->mac.type == e1000_pch_spt) 1799 msec_delay(50); 1800 /* Do the work to read phy */ 1801 e1000_check_for_link(hw); 1802 link_check = !hw->mac.get_link_status; 1803 if (link_check) /* ESB2 fix */ 1804 e1000_cfg_on_link_up(hw); 1805 } else { 1806 link_check = true; 1807 } 1808 break; 1809 case e1000_media_type_fiber: 1810 e1000_check_for_link(hw); 1811 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1812 E1000_STATUS_LU); 1813 break; 1814 case e1000_media_type_internal_serdes: 1815 e1000_check_for_link(hw); 1816 link_check = hw->mac.serdes_has_link; 1817 break; 1818 /* VF device is type_unknown */ 1819 case e1000_media_type_unknown: 1820 e1000_check_for_link(hw); 1821 link_check = !hw->mac.get_link_status; 1822 /* FALLTHROUGH */ 1823 default: 1824 break; 1825 } 1826 1827 /* Check for thermal downshift or shutdown */ 1828 if (hw->mac.type == e1000_i350) { 1829 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1830 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1831 } 1832 1833 /* Now check for a transition */ 1834 if (link_check && (sc->link_active == 0)) { 1835 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1836 &sc->link_duplex); 1837 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1838 if ((sc->link_speed != SPEED_1000) && 1839 ((hw->mac.type == e1000_82571) || 1840 (hw->mac.type == e1000_82572))) { 1841 int tarc0; 1842 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1843 tarc0 &= ~TARC_SPEED_MODE_BIT; 1844 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1845 } 1846 if (bootverbose) 1847 device_printf(dev, "Link is up %d Mbps %s\n", 1848 sc->link_speed, 1849 ((sc->link_duplex == FULL_DUPLEX) ? 1850 "Full Duplex" : "Half Duplex")); 1851 sc->link_active = 1; 1852 sc->smartspeed = 0; 1853 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1854 E1000_CTRL_EXT_LINK_MODE_GMII && 1855 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1856 device_printf(dev, "Link: thermal downshift\n"); 1857 /* Delay Link Up for Phy update */ 1858 if (((hw->mac.type == e1000_i210) || 1859 (hw->mac.type == e1000_i211)) && 1860 (hw->phy.id == I210_I_PHY_ID)) 1861 msec_delay(I210_LINK_DELAY); 1862 /* Reset if the media type changed. */ 1863 if (hw->dev_spec._82575.media_changed && 1864 hw->mac.type >= igb_mac_min) { 1865 hw->dev_spec._82575.media_changed = false; 1866 sc->flags |= IGB_MEDIA_RESET; 1867 em_reset(ctx); 1868 } 1869 iflib_link_state_change(ctx, LINK_STATE_UP, 1870 IF_Mbps(sc->link_speed)); 1871 } else if (!link_check && (sc->link_active == 1)) { 1872 sc->link_speed = 0; 1873 sc->link_duplex = 0; 1874 sc->link_active = 0; 1875 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1876 } 1877 em_update_stats_counters(sc); 1878 1879 /* Reset LAA into RAR[0] on 82571 */ 1880 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1881 e1000_rar_set(hw, hw->mac.addr, 0); 1882 1883 if (hw->mac.type < em_mac_min) 1884 lem_smartspeed(sc); 1885 } 1886 1887 static void 1888 em_if_watchdog_reset(if_ctx_t ctx) 1889 { 1890 struct e1000_softc *sc = iflib_get_softc(ctx); 1891 1892 /* 1893 * Just count the event; iflib(4) will already trigger a 1894 * sufficient reset of the controller. 1895 */ 1896 sc->watchdog_events++; 1897 } 1898 1899 /********************************************************************* 1900 * 1901 * This routine disables all traffic on the adapter by issuing a 1902 * global reset on the MAC. 1903 * 1904 **********************************************************************/ 1905 static void 1906 em_if_stop(if_ctx_t ctx) 1907 { 1908 struct e1000_softc *sc = iflib_get_softc(ctx); 1909 1910 INIT_DEBUGOUT("em_if_stop: begin"); 1911 1912 e1000_reset_hw(&sc->hw); 1913 if (sc->hw.mac.type >= e1000_82544) 1914 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1915 1916 e1000_led_off(&sc->hw); 1917 e1000_cleanup_led(&sc->hw); 1918 } 1919 1920 /********************************************************************* 1921 * 1922 * Determine hardware revision. 1923 * 1924 **********************************************************************/ 1925 static void 1926 em_identify_hardware(if_ctx_t ctx) 1927 { 1928 device_t dev = iflib_get_dev(ctx); 1929 struct e1000_softc *sc = iflib_get_softc(ctx); 1930 1931 /* Make sure our PCI config space has the necessary stuff set */ 1932 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1933 1934 /* Save off the information about this board */ 1935 sc->hw.vendor_id = pci_get_vendor(dev); 1936 sc->hw.device_id = pci_get_device(dev); 1937 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1938 sc->hw.subsystem_vendor_id = 1939 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1940 sc->hw.subsystem_device_id = 1941 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1942 1943 /* Do Shared Code Init and Setup */ 1944 if (e1000_set_mac_type(&sc->hw)) { 1945 device_printf(dev, "Setup init failure\n"); 1946 return; 1947 } 1948 1949 /* Are we a VF device? */ 1950 if ((sc->hw.mac.type == e1000_vfadapt) || 1951 (sc->hw.mac.type == e1000_vfadapt_i350)) 1952 sc->vf_ifp = 1; 1953 else 1954 sc->vf_ifp = 0; 1955 } 1956 1957 static int 1958 em_allocate_pci_resources(if_ctx_t ctx) 1959 { 1960 struct e1000_softc *sc = iflib_get_softc(ctx); 1961 device_t dev = iflib_get_dev(ctx); 1962 int rid, val; 1963 1964 rid = PCIR_BAR(0); 1965 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1966 &rid, RF_ACTIVE); 1967 if (sc->memory == NULL) { 1968 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1969 return (ENXIO); 1970 } 1971 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 1972 sc->osdep.mem_bus_space_handle = 1973 rman_get_bushandle(sc->memory); 1974 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 1975 1976 /* Only older adapters use IO mapping */ 1977 if (sc->hw.mac.type < em_mac_min && 1978 sc->hw.mac.type > e1000_82543) { 1979 /* Figure our where our IO BAR is ? */ 1980 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1981 val = pci_read_config(dev, rid, 4); 1982 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1983 break; 1984 } 1985 rid += 4; 1986 /* check for 64bit BAR */ 1987 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1988 rid += 4; 1989 } 1990 if (rid >= PCIR_CIS) { 1991 device_printf(dev, "Unable to locate IO BAR\n"); 1992 return (ENXIO); 1993 } 1994 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1995 &rid, RF_ACTIVE); 1996 if (sc->ioport == NULL) { 1997 device_printf(dev, "Unable to allocate bus resource: " 1998 "ioport\n"); 1999 return (ENXIO); 2000 } 2001 sc->hw.io_base = 0; 2002 sc->osdep.io_bus_space_tag = 2003 rman_get_bustag(sc->ioport); 2004 sc->osdep.io_bus_space_handle = 2005 rman_get_bushandle(sc->ioport); 2006 } 2007 2008 sc->hw.back = &sc->osdep; 2009 2010 return (0); 2011 } 2012 2013 /********************************************************************* 2014 * 2015 * Set up the MSI-X Interrupt handlers 2016 * 2017 **********************************************************************/ 2018 static int 2019 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2020 { 2021 struct e1000_softc *sc = iflib_get_softc(ctx); 2022 struct em_rx_queue *rx_que = sc->rx_queues; 2023 struct em_tx_queue *tx_que = sc->tx_queues; 2024 int error, rid, i, vector = 0, rx_vectors; 2025 char buf[16]; 2026 2027 /* First set up ring resources */ 2028 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2029 rid = vector + 1; 2030 snprintf(buf, sizeof(buf), "rxq%d", i); 2031 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2032 if (error) { 2033 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2034 sc->rx_num_queues = i + 1; 2035 goto fail; 2036 } 2037 2038 rx_que->msix = vector; 2039 2040 /* 2041 * Set the bit to enable interrupt 2042 * in E1000_IMS -- bits 20 and 21 2043 * are for RX0 and RX1, note this has 2044 * NOTHING to do with the MSI-X vector 2045 */ 2046 if (sc->hw.mac.type == e1000_82574) { 2047 rx_que->eims = 1 << (20 + i); 2048 sc->ims |= rx_que->eims; 2049 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2050 } else if (sc->hw.mac.type == e1000_82575) 2051 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2052 else 2053 rx_que->eims = 1 << vector; 2054 } 2055 rx_vectors = vector; 2056 2057 vector = 0; 2058 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2059 snprintf(buf, sizeof(buf), "txq%d", i); 2060 tx_que = &sc->tx_queues[i]; 2061 iflib_softirq_alloc_generic(ctx, 2062 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2063 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2064 2065 tx_que->msix = (vector % sc->rx_num_queues); 2066 2067 /* 2068 * Set the bit to enable interrupt 2069 * in E1000_IMS -- bits 22 and 23 2070 * are for TX0 and TX1, note this has 2071 * NOTHING to do with the MSI-X vector 2072 */ 2073 if (sc->hw.mac.type == e1000_82574) { 2074 tx_que->eims = 1 << (22 + i); 2075 sc->ims |= tx_que->eims; 2076 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2077 } else if (sc->hw.mac.type == e1000_82575) { 2078 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2079 } else { 2080 tx_que->eims = 1 << i; 2081 } 2082 } 2083 2084 /* Link interrupt */ 2085 rid = rx_vectors + 1; 2086 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2087 2088 if (error) { 2089 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2090 goto fail; 2091 } 2092 sc->linkvec = rx_vectors; 2093 if (sc->hw.mac.type < igb_mac_min) { 2094 sc->ivars |= (8 | rx_vectors) << 16; 2095 sc->ivars |= 0x80000000; 2096 /* Enable the "Other" interrupt type for link status change */ 2097 sc->ims |= E1000_IMS_OTHER; 2098 } 2099 2100 return (0); 2101 fail: 2102 iflib_irq_free(ctx, &sc->irq); 2103 rx_que = sc->rx_queues; 2104 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2105 iflib_irq_free(ctx, &rx_que->que_irq); 2106 return (error); 2107 } 2108 2109 static void 2110 igb_configure_queues(struct e1000_softc *sc) 2111 { 2112 struct e1000_hw *hw = &sc->hw; 2113 struct em_rx_queue *rx_que; 2114 struct em_tx_queue *tx_que; 2115 u32 tmp, ivar = 0, newitr = 0; 2116 2117 /* First turn on RSS capability */ 2118 if (hw->mac.type != e1000_82575) 2119 E1000_WRITE_REG(hw, E1000_GPIE, 2120 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2121 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2122 2123 /* Turn on MSI-X */ 2124 switch (hw->mac.type) { 2125 case e1000_82580: 2126 case e1000_i350: 2127 case e1000_i354: 2128 case e1000_i210: 2129 case e1000_i211: 2130 case e1000_vfadapt: 2131 case e1000_vfadapt_i350: 2132 /* RX entries */ 2133 for (int i = 0; i < sc->rx_num_queues; i++) { 2134 u32 index = i >> 1; 2135 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2136 rx_que = &sc->rx_queues[i]; 2137 if (i & 1) { 2138 ivar &= 0xFF00FFFF; 2139 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2140 } else { 2141 ivar &= 0xFFFFFF00; 2142 ivar |= rx_que->msix | E1000_IVAR_VALID; 2143 } 2144 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2145 } 2146 /* TX entries */ 2147 for (int i = 0; i < sc->tx_num_queues; i++) { 2148 u32 index = i >> 1; 2149 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2150 tx_que = &sc->tx_queues[i]; 2151 if (i & 1) { 2152 ivar &= 0x00FFFFFF; 2153 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2154 } else { 2155 ivar &= 0xFFFF00FF; 2156 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2157 } 2158 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2159 sc->que_mask |= tx_que->eims; 2160 } 2161 2162 /* And for the link interrupt */ 2163 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2164 sc->link_mask = 1 << sc->linkvec; 2165 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2166 break; 2167 case e1000_82576: 2168 /* RX entries */ 2169 for (int i = 0; i < sc->rx_num_queues; i++) { 2170 u32 index = i & 0x7; /* Each IVAR has two entries */ 2171 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2172 rx_que = &sc->rx_queues[i]; 2173 if (i < 8) { 2174 ivar &= 0xFFFFFF00; 2175 ivar |= rx_que->msix | E1000_IVAR_VALID; 2176 } else { 2177 ivar &= 0xFF00FFFF; 2178 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2179 } 2180 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2181 sc->que_mask |= rx_que->eims; 2182 } 2183 /* TX entries */ 2184 for (int i = 0; i < sc->tx_num_queues; i++) { 2185 u32 index = i & 0x7; /* Each IVAR has two entries */ 2186 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2187 tx_que = &sc->tx_queues[i]; 2188 if (i < 8) { 2189 ivar &= 0xFFFF00FF; 2190 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2191 } else { 2192 ivar &= 0x00FFFFFF; 2193 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2194 } 2195 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2196 sc->que_mask |= tx_que->eims; 2197 } 2198 2199 /* And for the link interrupt */ 2200 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2201 sc->link_mask = 1 << sc->linkvec; 2202 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2203 break; 2204 2205 case e1000_82575: 2206 /* enable MSI-X support*/ 2207 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2208 tmp |= E1000_CTRL_EXT_PBA_CLR; 2209 /* Auto-Mask interrupts upon ICR read. */ 2210 tmp |= E1000_CTRL_EXT_EIAME; 2211 tmp |= E1000_CTRL_EXT_IRCA; 2212 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2213 2214 /* Queues */ 2215 for (int i = 0; i < sc->rx_num_queues; i++) { 2216 rx_que = &sc->rx_queues[i]; 2217 tmp = E1000_EICR_RX_QUEUE0 << i; 2218 tmp |= E1000_EICR_TX_QUEUE0 << i; 2219 rx_que->eims = tmp; 2220 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2221 i, rx_que->eims); 2222 sc->que_mask |= rx_que->eims; 2223 } 2224 2225 /* Link */ 2226 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2227 E1000_EIMS_OTHER); 2228 sc->link_mask |= E1000_EIMS_OTHER; 2229 default: 2230 break; 2231 } 2232 2233 /* Set the starting interrupt rate */ 2234 if (em_max_interrupt_rate > 0) 2235 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2236 2237 if (hw->mac.type == e1000_82575) 2238 newitr |= newitr << 16; 2239 else 2240 newitr |= E1000_EITR_CNT_IGNR; 2241 2242 for (int i = 0; i < sc->rx_num_queues; i++) { 2243 rx_que = &sc->rx_queues[i]; 2244 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2245 } 2246 2247 return; 2248 } 2249 2250 static void 2251 em_free_pci_resources(if_ctx_t ctx) 2252 { 2253 struct e1000_softc *sc = iflib_get_softc(ctx); 2254 struct em_rx_queue *que = sc->rx_queues; 2255 device_t dev = iflib_get_dev(ctx); 2256 2257 /* Release all MSI-X queue resources */ 2258 if (sc->intr_type == IFLIB_INTR_MSIX) 2259 iflib_irq_free(ctx, &sc->irq); 2260 2261 if (que != NULL) { 2262 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2263 iflib_irq_free(ctx, &que->que_irq); 2264 } 2265 } 2266 2267 if (sc->memory != NULL) { 2268 bus_release_resource(dev, SYS_RES_MEMORY, 2269 rman_get_rid(sc->memory), sc->memory); 2270 sc->memory = NULL; 2271 } 2272 2273 if (sc->flash != NULL) { 2274 bus_release_resource(dev, SYS_RES_MEMORY, 2275 rman_get_rid(sc->flash), sc->flash); 2276 sc->flash = NULL; 2277 } 2278 2279 if (sc->ioport != NULL) { 2280 bus_release_resource(dev, SYS_RES_IOPORT, 2281 rman_get_rid(sc->ioport), sc->ioport); 2282 sc->ioport = NULL; 2283 } 2284 } 2285 2286 /* Set up MSI or MSI-X */ 2287 static int 2288 em_setup_msix(if_ctx_t ctx) 2289 { 2290 struct e1000_softc *sc = iflib_get_softc(ctx); 2291 2292 if (sc->hw.mac.type == e1000_82574) { 2293 em_enable_vectors_82574(ctx); 2294 } 2295 return (0); 2296 } 2297 2298 /********************************************************************* 2299 * 2300 * Workaround for SmartSpeed on 82541 and 82547 controllers 2301 * 2302 **********************************************************************/ 2303 static void 2304 lem_smartspeed(struct e1000_softc *sc) 2305 { 2306 u16 phy_tmp; 2307 2308 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2309 sc->hw.mac.autoneg == 0 || 2310 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2311 return; 2312 2313 if (sc->smartspeed == 0) { 2314 /* If Master/Slave config fault is asserted twice, 2315 * we assume back-to-back */ 2316 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2317 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2318 return; 2319 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2320 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2321 e1000_read_phy_reg(&sc->hw, 2322 PHY_1000T_CTRL, &phy_tmp); 2323 if(phy_tmp & CR_1000T_MS_ENABLE) { 2324 phy_tmp &= ~CR_1000T_MS_ENABLE; 2325 e1000_write_phy_reg(&sc->hw, 2326 PHY_1000T_CTRL, phy_tmp); 2327 sc->smartspeed++; 2328 if(sc->hw.mac.autoneg && 2329 !e1000_copper_link_autoneg(&sc->hw) && 2330 !e1000_read_phy_reg(&sc->hw, 2331 PHY_CONTROL, &phy_tmp)) { 2332 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2333 MII_CR_RESTART_AUTO_NEG); 2334 e1000_write_phy_reg(&sc->hw, 2335 PHY_CONTROL, phy_tmp); 2336 } 2337 } 2338 } 2339 return; 2340 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2341 /* If still no link, perhaps using 2/3 pair cable */ 2342 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2343 phy_tmp |= CR_1000T_MS_ENABLE; 2344 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2345 if(sc->hw.mac.autoneg && 2346 !e1000_copper_link_autoneg(&sc->hw) && 2347 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2348 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2349 MII_CR_RESTART_AUTO_NEG); 2350 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2351 } 2352 } 2353 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2354 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2355 sc->smartspeed = 0; 2356 } 2357 2358 /********************************************************************* 2359 * 2360 * Initialize the DMA Coalescing feature 2361 * 2362 **********************************************************************/ 2363 static void 2364 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2365 { 2366 device_t dev = sc->dev; 2367 struct e1000_hw *hw = &sc->hw; 2368 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2369 u16 hwm; 2370 u16 max_frame_size; 2371 2372 if (hw->mac.type == e1000_i211) 2373 return; 2374 2375 max_frame_size = sc->shared->isc_max_frame_size; 2376 if (hw->mac.type > e1000_82580) { 2377 2378 if (sc->dmac == 0) { /* Disabling it */ 2379 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2380 return; 2381 } else 2382 device_printf(dev, "DMA Coalescing enabled\n"); 2383 2384 /* Set starting threshold */ 2385 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2386 2387 hwm = 64 * pba - max_frame_size / 16; 2388 if (hwm < 64 * (pba - 6)) 2389 hwm = 64 * (pba - 6); 2390 reg = E1000_READ_REG(hw, E1000_FCRTC); 2391 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2392 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2393 & E1000_FCRTC_RTH_COAL_MASK); 2394 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2395 2396 2397 dmac = pba - max_frame_size / 512; 2398 if (dmac < pba - 10) 2399 dmac = pba - 10; 2400 reg = E1000_READ_REG(hw, E1000_DMACR); 2401 reg &= ~E1000_DMACR_DMACTHR_MASK; 2402 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2403 & E1000_DMACR_DMACTHR_MASK); 2404 2405 /* transition to L0x or L1 if available..*/ 2406 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2407 2408 /* Check if status is 2.5Gb backplane connection 2409 * before configuration of watchdog timer, which is 2410 * in msec values in 12.8usec intervals 2411 * watchdog timer= msec values in 32usec intervals 2412 * for non 2.5Gb connection 2413 */ 2414 if (hw->mac.type == e1000_i354) { 2415 int status = E1000_READ_REG(hw, E1000_STATUS); 2416 if ((status & E1000_STATUS_2P5_SKU) && 2417 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2418 reg |= ((sc->dmac * 5) >> 6); 2419 else 2420 reg |= (sc->dmac >> 5); 2421 } else { 2422 reg |= (sc->dmac >> 5); 2423 } 2424 2425 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2426 2427 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2428 2429 /* Set the interval before transition */ 2430 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2431 if (hw->mac.type == e1000_i350) 2432 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2433 /* 2434 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2435 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2436 */ 2437 if (hw->mac.type == e1000_i354) { 2438 int status = E1000_READ_REG(hw, E1000_STATUS); 2439 if ((status & E1000_STATUS_2P5_SKU) && 2440 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2441 reg |= 0xA; 2442 else 2443 reg |= 0x4; 2444 } else { 2445 reg |= 0x4; 2446 } 2447 2448 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2449 2450 /* free space in tx packet buffer to wake from DMA coal */ 2451 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2452 (2 * max_frame_size)) >> 6); 2453 2454 /* make low power state decision controlled by DMA coal */ 2455 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2456 reg &= ~E1000_PCIEMISC_LX_DECISION; 2457 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2458 2459 } else if (hw->mac.type == e1000_82580) { 2460 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2461 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2462 reg & ~E1000_PCIEMISC_LX_DECISION); 2463 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2464 } 2465 } 2466 2467 /********************************************************************* 2468 * 2469 * Initialize the hardware to a configuration as specified by the 2470 * sc structure. 2471 * 2472 **********************************************************************/ 2473 static void 2474 em_reset(if_ctx_t ctx) 2475 { 2476 device_t dev = iflib_get_dev(ctx); 2477 struct e1000_softc *sc = iflib_get_softc(ctx); 2478 struct ifnet *ifp = iflib_get_ifp(ctx); 2479 struct e1000_hw *hw = &sc->hw; 2480 u32 rx_buffer_size; 2481 u32 pba; 2482 2483 INIT_DEBUGOUT("em_reset: begin"); 2484 /* Let the firmware know the OS is in control */ 2485 em_get_hw_control(sc); 2486 2487 /* Set up smart power down as default off on newer adapters. */ 2488 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2489 hw->mac.type == e1000_82572)) { 2490 u16 phy_tmp = 0; 2491 2492 /* Speed up time to link by disabling smart power down. */ 2493 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2494 phy_tmp &= ~IGP02E1000_PM_SPD; 2495 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2496 } 2497 2498 /* 2499 * Packet Buffer Allocation (PBA) 2500 * Writing PBA sets the receive portion of the buffer 2501 * the remainder is used for the transmit buffer. 2502 */ 2503 switch (hw->mac.type) { 2504 /* 82547: Total Packet Buffer is 40K */ 2505 case e1000_82547: 2506 case e1000_82547_rev_2: 2507 if (hw->mac.max_frame_size > 8192) 2508 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2509 else 2510 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2511 break; 2512 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2513 case e1000_82571: 2514 case e1000_82572: 2515 case e1000_80003es2lan: 2516 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2517 break; 2518 /* 82573: Total Packet Buffer is 32K */ 2519 case e1000_82573: 2520 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2521 break; 2522 case e1000_82574: 2523 case e1000_82583: 2524 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2525 break; 2526 case e1000_ich8lan: 2527 pba = E1000_PBA_8K; 2528 break; 2529 case e1000_ich9lan: 2530 case e1000_ich10lan: 2531 /* Boost Receive side for jumbo frames */ 2532 if (hw->mac.max_frame_size > 4096) 2533 pba = E1000_PBA_14K; 2534 else 2535 pba = E1000_PBA_10K; 2536 break; 2537 case e1000_pchlan: 2538 case e1000_pch2lan: 2539 case e1000_pch_lpt: 2540 case e1000_pch_spt: 2541 case e1000_pch_cnp: 2542 case e1000_pch_tgp: 2543 case e1000_pch_adp: 2544 case e1000_pch_mtp: 2545 pba = E1000_PBA_26K; 2546 break; 2547 case e1000_82575: 2548 pba = E1000_PBA_32K; 2549 break; 2550 case e1000_82576: 2551 case e1000_vfadapt: 2552 pba = E1000_READ_REG(hw, E1000_RXPBS); 2553 pba &= E1000_RXPBS_SIZE_MASK_82576; 2554 break; 2555 case e1000_82580: 2556 case e1000_i350: 2557 case e1000_i354: 2558 case e1000_vfadapt_i350: 2559 pba = E1000_READ_REG(hw, E1000_RXPBS); 2560 pba = e1000_rxpbs_adjust_82580(pba); 2561 break; 2562 case e1000_i210: 2563 case e1000_i211: 2564 pba = E1000_PBA_34K; 2565 break; 2566 default: 2567 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2568 if (hw->mac.max_frame_size > 8192) 2569 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2570 else 2571 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2572 } 2573 2574 /* Special needs in case of Jumbo frames */ 2575 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2576 u32 tx_space, min_tx, min_rx; 2577 pba = E1000_READ_REG(hw, E1000_PBA); 2578 tx_space = pba >> 16; 2579 pba &= 0xffff; 2580 min_tx = (hw->mac.max_frame_size + 2581 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2582 min_tx = roundup2(min_tx, 1024); 2583 min_tx >>= 10; 2584 min_rx = hw->mac.max_frame_size; 2585 min_rx = roundup2(min_rx, 1024); 2586 min_rx >>= 10; 2587 if (tx_space < min_tx && 2588 ((min_tx - tx_space) < pba)) { 2589 pba = pba - (min_tx - tx_space); 2590 /* 2591 * if short on rx space, rx wins 2592 * and must trump tx adjustment 2593 */ 2594 if (pba < min_rx) 2595 pba = min_rx; 2596 } 2597 E1000_WRITE_REG(hw, E1000_PBA, pba); 2598 } 2599 2600 if (hw->mac.type < igb_mac_min) 2601 E1000_WRITE_REG(hw, E1000_PBA, pba); 2602 2603 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2604 2605 /* 2606 * These parameters control the automatic generation (Tx) and 2607 * response (Rx) to Ethernet PAUSE frames. 2608 * - High water mark should allow for at least two frames to be 2609 * received after sending an XOFF. 2610 * - Low water mark works best when it is very near the high water mark. 2611 * This allows the receiver to restart by sending XON when it has 2612 * drained a bit. Here we use an arbitrary value of 1500 which will 2613 * restart after one full frame is pulled from the buffer. There 2614 * could be several smaller frames in the buffer and if so they will 2615 * not trigger the XON until their total number reduces the buffer 2616 * by 1500. 2617 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2618 */ 2619 rx_buffer_size = (pba & 0xffff) << 10; 2620 hw->fc.high_water = rx_buffer_size - 2621 roundup2(hw->mac.max_frame_size, 1024); 2622 hw->fc.low_water = hw->fc.high_water - 1500; 2623 2624 if (sc->fc) /* locally set flow control value? */ 2625 hw->fc.requested_mode = sc->fc; 2626 else 2627 hw->fc.requested_mode = e1000_fc_full; 2628 2629 if (hw->mac.type == e1000_80003es2lan) 2630 hw->fc.pause_time = 0xFFFF; 2631 else 2632 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2633 2634 hw->fc.send_xon = true; 2635 2636 /* Device specific overrides/settings */ 2637 switch (hw->mac.type) { 2638 case e1000_pchlan: 2639 /* Workaround: no TX flow ctrl for PCH */ 2640 hw->fc.requested_mode = e1000_fc_rx_pause; 2641 hw->fc.pause_time = 0xFFFF; /* override */ 2642 if (if_getmtu(ifp) > ETHERMTU) { 2643 hw->fc.high_water = 0x3500; 2644 hw->fc.low_water = 0x1500; 2645 } else { 2646 hw->fc.high_water = 0x5000; 2647 hw->fc.low_water = 0x3000; 2648 } 2649 hw->fc.refresh_time = 0x1000; 2650 break; 2651 case e1000_pch2lan: 2652 case e1000_pch_lpt: 2653 case e1000_pch_spt: 2654 case e1000_pch_cnp: 2655 case e1000_pch_tgp: 2656 case e1000_pch_adp: 2657 case e1000_pch_mtp: 2658 hw->fc.high_water = 0x5C20; 2659 hw->fc.low_water = 0x5048; 2660 hw->fc.pause_time = 0x0650; 2661 hw->fc.refresh_time = 0x0400; 2662 /* Jumbos need adjusted PBA */ 2663 if (if_getmtu(ifp) > ETHERMTU) 2664 E1000_WRITE_REG(hw, E1000_PBA, 12); 2665 else 2666 E1000_WRITE_REG(hw, E1000_PBA, 26); 2667 break; 2668 case e1000_82575: 2669 case e1000_82576: 2670 /* 8-byte granularity */ 2671 hw->fc.low_water = hw->fc.high_water - 8; 2672 break; 2673 case e1000_82580: 2674 case e1000_i350: 2675 case e1000_i354: 2676 case e1000_i210: 2677 case e1000_i211: 2678 case e1000_vfadapt: 2679 case e1000_vfadapt_i350: 2680 /* 16-byte granularity */ 2681 hw->fc.low_water = hw->fc.high_water - 16; 2682 break; 2683 case e1000_ich9lan: 2684 case e1000_ich10lan: 2685 if (if_getmtu(ifp) > ETHERMTU) { 2686 hw->fc.high_water = 0x2800; 2687 hw->fc.low_water = hw->fc.high_water - 8; 2688 break; 2689 } 2690 /* FALLTHROUGH */ 2691 default: 2692 if (hw->mac.type == e1000_80003es2lan) 2693 hw->fc.pause_time = 0xFFFF; 2694 break; 2695 } 2696 2697 /* Issue a global reset */ 2698 e1000_reset_hw(hw); 2699 if (hw->mac.type >= igb_mac_min) { 2700 E1000_WRITE_REG(hw, E1000_WUC, 0); 2701 } else { 2702 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2703 em_disable_aspm(sc); 2704 } 2705 if (sc->flags & IGB_MEDIA_RESET) { 2706 e1000_setup_init_funcs(hw, true); 2707 e1000_get_bus_info(hw); 2708 sc->flags &= ~IGB_MEDIA_RESET; 2709 } 2710 /* and a re-init */ 2711 if (e1000_init_hw(hw) < 0) { 2712 device_printf(dev, "Hardware Initialization Failed\n"); 2713 return; 2714 } 2715 if (hw->mac.type >= igb_mac_min) 2716 igb_init_dmac(sc, pba); 2717 2718 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2719 e1000_get_phy_info(hw); 2720 e1000_check_for_link(hw); 2721 } 2722 2723 /* 2724 * Initialise the RSS mapping for NICs that support multiple transmit/ 2725 * receive rings. 2726 */ 2727 2728 #define RSSKEYLEN 10 2729 static void 2730 em_initialize_rss_mapping(struct e1000_softc *sc) 2731 { 2732 uint8_t rss_key[4 * RSSKEYLEN]; 2733 uint32_t reta = 0; 2734 struct e1000_hw *hw = &sc->hw; 2735 int i; 2736 2737 /* 2738 * Configure RSS key 2739 */ 2740 arc4rand(rss_key, sizeof(rss_key), 0); 2741 for (i = 0; i < RSSKEYLEN; ++i) { 2742 uint32_t rssrk = 0; 2743 2744 rssrk = EM_RSSRK_VAL(rss_key, i); 2745 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2746 } 2747 2748 /* 2749 * Configure RSS redirect table in following fashion: 2750 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2751 */ 2752 for (i = 0; i < sizeof(reta); ++i) { 2753 uint32_t q; 2754 2755 q = (i % sc->rx_num_queues) << 7; 2756 reta |= q << (8 * i); 2757 } 2758 2759 for (i = 0; i < 32; ++i) 2760 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2761 2762 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2763 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2764 E1000_MRQC_RSS_FIELD_IPV4 | 2765 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2766 E1000_MRQC_RSS_FIELD_IPV6_EX | 2767 E1000_MRQC_RSS_FIELD_IPV6); 2768 } 2769 2770 static void 2771 igb_initialize_rss_mapping(struct e1000_softc *sc) 2772 { 2773 struct e1000_hw *hw = &sc->hw; 2774 int i; 2775 int queue_id; 2776 u32 reta; 2777 u32 rss_key[10], mrqc, shift = 0; 2778 2779 /* XXX? */ 2780 if (hw->mac.type == e1000_82575) 2781 shift = 6; 2782 2783 /* 2784 * The redirection table controls which destination 2785 * queue each bucket redirects traffic to. 2786 * Each DWORD represents four queues, with the LSB 2787 * being the first queue in the DWORD. 2788 * 2789 * This just allocates buckets to queues using round-robin 2790 * allocation. 2791 * 2792 * NOTE: It Just Happens to line up with the default 2793 * RSS allocation method. 2794 */ 2795 2796 /* Warning FM follows */ 2797 reta = 0; 2798 for (i = 0; i < 128; i++) { 2799 #ifdef RSS 2800 queue_id = rss_get_indirection_to_bucket(i); 2801 /* 2802 * If we have more queues than buckets, we'll 2803 * end up mapping buckets to a subset of the 2804 * queues. 2805 * 2806 * If we have more buckets than queues, we'll 2807 * end up instead assigning multiple buckets 2808 * to queues. 2809 * 2810 * Both are suboptimal, but we need to handle 2811 * the case so we don't go out of bounds 2812 * indexing arrays and such. 2813 */ 2814 queue_id = queue_id % sc->rx_num_queues; 2815 #else 2816 queue_id = (i % sc->rx_num_queues); 2817 #endif 2818 /* Adjust if required */ 2819 queue_id = queue_id << shift; 2820 2821 /* 2822 * The low 8 bits are for hash value (n+0); 2823 * The next 8 bits are for hash value (n+1), etc. 2824 */ 2825 reta = reta >> 8; 2826 reta = reta | ( ((uint32_t) queue_id) << 24); 2827 if ((i & 3) == 3) { 2828 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2829 reta = 0; 2830 } 2831 } 2832 2833 /* Now fill in hash table */ 2834 2835 /* 2836 * MRQC: Multiple Receive Queues Command 2837 * Set queuing to RSS control, number depends on the device. 2838 */ 2839 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 2840 2841 #ifdef RSS 2842 /* XXX ew typecasting */ 2843 rss_getkey((uint8_t *) &rss_key); 2844 #else 2845 arc4rand(&rss_key, sizeof(rss_key), 0); 2846 #endif 2847 for (i = 0; i < 10; i++) 2848 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2849 2850 /* 2851 * Configure the RSS fields to hash upon. 2852 */ 2853 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2854 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2855 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2856 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2857 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2858 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2859 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2860 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2861 2862 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2863 } 2864 2865 /********************************************************************* 2866 * 2867 * Setup networking device structure and register interface media. 2868 * 2869 **********************************************************************/ 2870 static int 2871 em_setup_interface(if_ctx_t ctx) 2872 { 2873 struct ifnet *ifp = iflib_get_ifp(ctx); 2874 struct e1000_softc *sc = iflib_get_softc(ctx); 2875 if_softc_ctx_t scctx = sc->shared; 2876 2877 INIT_DEBUGOUT("em_setup_interface: begin"); 2878 2879 /* Single Queue */ 2880 if (sc->tx_num_queues == 1) { 2881 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2882 if_setsendqready(ifp); 2883 } 2884 2885 /* 2886 * Specify the media types supported by this adapter and register 2887 * callbacks to update media and link information 2888 */ 2889 if (sc->hw.phy.media_type == e1000_media_type_fiber || 2890 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 2891 u_char fiber_type = IFM_1000_SX; /* default type */ 2892 2893 if (sc->hw.mac.type == e1000_82545) 2894 fiber_type = IFM_1000_LX; 2895 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2896 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 2897 } else { 2898 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2899 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2900 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2901 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2902 if (sc->hw.phy.type != e1000_phy_ife) { 2903 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2904 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2905 } 2906 } 2907 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2908 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 2909 return (0); 2910 } 2911 2912 static int 2913 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2914 { 2915 struct e1000_softc *sc = iflib_get_softc(ctx); 2916 if_softc_ctx_t scctx = sc->shared; 2917 int error = E1000_SUCCESS; 2918 struct em_tx_queue *que; 2919 int i, j; 2920 2921 MPASS(sc->tx_num_queues > 0); 2922 MPASS(sc->tx_num_queues == ntxqsets); 2923 2924 /* First allocate the top level queue structs */ 2925 if (!(sc->tx_queues = 2926 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2927 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2928 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2929 return(ENOMEM); 2930 } 2931 2932 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 2933 /* Set up some basics */ 2934 2935 struct tx_ring *txr = &que->txr; 2936 txr->sc = que->sc = sc; 2937 que->me = txr->me = i; 2938 2939 /* Allocate report status array */ 2940 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2941 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2942 error = ENOMEM; 2943 goto fail; 2944 } 2945 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2946 txr->tx_rsq[j] = QIDX_INVALID; 2947 /* get the virtual and physical address of the hardware queues */ 2948 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2949 txr->tx_paddr = paddrs[i*ntxqs]; 2950 } 2951 2952 if (bootverbose) 2953 device_printf(iflib_get_dev(ctx), 2954 "allocated for %d tx_queues\n", sc->tx_num_queues); 2955 return (0); 2956 fail: 2957 em_if_queues_free(ctx); 2958 return (error); 2959 } 2960 2961 static int 2962 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2963 { 2964 struct e1000_softc *sc = iflib_get_softc(ctx); 2965 int error = E1000_SUCCESS; 2966 struct em_rx_queue *que; 2967 int i; 2968 2969 MPASS(sc->rx_num_queues > 0); 2970 MPASS(sc->rx_num_queues == nrxqsets); 2971 2972 /* First allocate the top level queue structs */ 2973 if (!(sc->rx_queues = 2974 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2975 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2976 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2977 error = ENOMEM; 2978 goto fail; 2979 } 2980 2981 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 2982 /* Set up some basics */ 2983 struct rx_ring *rxr = &que->rxr; 2984 rxr->sc = que->sc = sc; 2985 rxr->que = que; 2986 que->me = rxr->me = i; 2987 2988 /* get the virtual and physical address of the hardware queues */ 2989 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2990 rxr->rx_paddr = paddrs[i*nrxqs]; 2991 } 2992 2993 if (bootverbose) 2994 device_printf(iflib_get_dev(ctx), 2995 "allocated for %d rx_queues\n", sc->rx_num_queues); 2996 2997 return (0); 2998 fail: 2999 em_if_queues_free(ctx); 3000 return (error); 3001 } 3002 3003 static void 3004 em_if_queues_free(if_ctx_t ctx) 3005 { 3006 struct e1000_softc *sc = iflib_get_softc(ctx); 3007 struct em_tx_queue *tx_que = sc->tx_queues; 3008 struct em_rx_queue *rx_que = sc->rx_queues; 3009 3010 if (tx_que != NULL) { 3011 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3012 struct tx_ring *txr = &tx_que->txr; 3013 if (txr->tx_rsq == NULL) 3014 break; 3015 3016 free(txr->tx_rsq, M_DEVBUF); 3017 txr->tx_rsq = NULL; 3018 } 3019 free(sc->tx_queues, M_DEVBUF); 3020 sc->tx_queues = NULL; 3021 } 3022 3023 if (rx_que != NULL) { 3024 free(sc->rx_queues, M_DEVBUF); 3025 sc->rx_queues = NULL; 3026 } 3027 } 3028 3029 /********************************************************************* 3030 * 3031 * Enable transmit unit. 3032 * 3033 **********************************************************************/ 3034 static void 3035 em_initialize_transmit_unit(if_ctx_t ctx) 3036 { 3037 struct e1000_softc *sc = iflib_get_softc(ctx); 3038 if_softc_ctx_t scctx = sc->shared; 3039 struct em_tx_queue *que; 3040 struct tx_ring *txr; 3041 struct e1000_hw *hw = &sc->hw; 3042 u32 tctl, txdctl = 0, tarc, tipg = 0; 3043 3044 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3045 3046 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3047 u64 bus_addr; 3048 caddr_t offp, endp; 3049 3050 que = &sc->tx_queues[i]; 3051 txr = &que->txr; 3052 bus_addr = txr->tx_paddr; 3053 3054 /* Clear checksum offload context. */ 3055 offp = (caddr_t)&txr->csum_flags; 3056 endp = (caddr_t)(txr + 1); 3057 bzero(offp, endp - offp); 3058 3059 /* Base and Len of TX Ring */ 3060 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3061 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3062 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3063 (u32)(bus_addr >> 32)); 3064 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3065 (u32)bus_addr); 3066 /* Init the HEAD/TAIL indices */ 3067 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3068 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3069 3070 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3071 E1000_READ_REG(hw, E1000_TDBAL(i)), 3072 E1000_READ_REG(hw, E1000_TDLEN(i))); 3073 3074 txdctl = 0; /* clear txdctl */ 3075 txdctl |= 0x1f; /* PTHRESH */ 3076 txdctl |= 1 << 8; /* HTHRESH */ 3077 txdctl |= 1 << 16;/* WTHRESH */ 3078 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3079 txdctl |= E1000_TXDCTL_GRAN; 3080 txdctl |= 1 << 25; /* LWTHRESH */ 3081 3082 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3083 } 3084 3085 /* Set the default values for the Tx Inter Packet Gap timer */ 3086 switch (hw->mac.type) { 3087 case e1000_80003es2lan: 3088 tipg = DEFAULT_82543_TIPG_IPGR1; 3089 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3090 E1000_TIPG_IPGR2_SHIFT; 3091 break; 3092 case e1000_82542: 3093 tipg = DEFAULT_82542_TIPG_IPGT; 3094 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3095 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3096 break; 3097 default: 3098 if (hw->phy.media_type == e1000_media_type_fiber || 3099 hw->phy.media_type == e1000_media_type_internal_serdes) 3100 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3101 else 3102 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3103 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3104 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3105 } 3106 3107 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3108 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3109 3110 if(hw->mac.type >= e1000_82540) 3111 E1000_WRITE_REG(hw, E1000_TADV, 3112 sc->tx_abs_int_delay.value); 3113 3114 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3115 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3116 tarc |= TARC_SPEED_MODE_BIT; 3117 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3118 } else if (hw->mac.type == e1000_80003es2lan) { 3119 /* errata: program both queues to unweighted RR */ 3120 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3121 tarc |= 1; 3122 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3123 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3124 tarc |= 1; 3125 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3126 } else if (hw->mac.type == e1000_82574) { 3127 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3128 tarc |= TARC_ERRATA_BIT; 3129 if ( sc->tx_num_queues > 1) { 3130 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3131 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3132 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3133 } else 3134 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3135 } 3136 3137 if (sc->tx_int_delay.value > 0) 3138 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3139 3140 /* Program the Transmit Control Register */ 3141 tctl = E1000_READ_REG(hw, E1000_TCTL); 3142 tctl &= ~E1000_TCTL_CT; 3143 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3144 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3145 3146 if (hw->mac.type >= e1000_82571) 3147 tctl |= E1000_TCTL_MULR; 3148 3149 /* This write will effectively turn on the transmit unit. */ 3150 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3151 3152 /* SPT and KBL errata workarounds */ 3153 if (hw->mac.type == e1000_pch_spt) { 3154 u32 reg; 3155 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3156 reg |= E1000_RCTL_RDMTS_HEX; 3157 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3158 /* i218-i219 Specification Update 1.5.4.5 */ 3159 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3160 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3161 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3162 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3163 } 3164 } 3165 3166 /********************************************************************* 3167 * 3168 * Enable receive unit. 3169 * 3170 **********************************************************************/ 3171 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3172 3173 static void 3174 em_initialize_receive_unit(if_ctx_t ctx) 3175 { 3176 struct e1000_softc *sc = iflib_get_softc(ctx); 3177 if_softc_ctx_t scctx = sc->shared; 3178 struct ifnet *ifp = iflib_get_ifp(ctx); 3179 struct e1000_hw *hw = &sc->hw; 3180 struct em_rx_queue *que; 3181 int i; 3182 uint32_t rctl, rxcsum; 3183 3184 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3185 3186 /* 3187 * Make sure receives are disabled while setting 3188 * up the descriptor ring 3189 */ 3190 rctl = E1000_READ_REG(hw, E1000_RCTL); 3191 /* Do not disable if ever enabled on this hardware */ 3192 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3193 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3194 3195 /* Setup the Receive Control Register */ 3196 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3197 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3198 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3199 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3200 3201 /* Do not store bad packets */ 3202 rctl &= ~E1000_RCTL_SBP; 3203 3204 /* Enable Long Packet receive */ 3205 if (if_getmtu(ifp) > ETHERMTU) 3206 rctl |= E1000_RCTL_LPE; 3207 else 3208 rctl &= ~E1000_RCTL_LPE; 3209 3210 /* Strip the CRC */ 3211 if (!em_disable_crc_stripping) 3212 rctl |= E1000_RCTL_SECRC; 3213 3214 if (hw->mac.type >= e1000_82540) { 3215 E1000_WRITE_REG(hw, E1000_RADV, 3216 sc->rx_abs_int_delay.value); 3217 3218 /* 3219 * Set the interrupt throttling rate. Value is calculated 3220 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3221 */ 3222 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3223 } 3224 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3225 3226 if (hw->mac.type >= em_mac_min) { 3227 uint32_t rfctl; 3228 /* Use extended rx descriptor formats */ 3229 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3230 rfctl |= E1000_RFCTL_EXTEN; 3231 3232 /* 3233 * When using MSI-X interrupts we need to throttle 3234 * using the EITR register (82574 only) 3235 */ 3236 if (hw->mac.type == e1000_82574) { 3237 for (int i = 0; i < 4; i++) 3238 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3239 DEFAULT_ITR); 3240 /* Disable accelerated acknowledge */ 3241 rfctl |= E1000_RFCTL_ACK_DIS; 3242 } 3243 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3244 } 3245 3246 /* Set up L3 and L4 csum Rx descriptor offloads */ 3247 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3248 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3249 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3250 if (hw->mac.type > e1000_82575) 3251 rxcsum |= E1000_RXCSUM_CRCOFL; 3252 else if (hw->mac.type < em_mac_min && 3253 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3254 rxcsum |= E1000_RXCSUM_IPV6OFL; 3255 } else { 3256 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3257 if (hw->mac.type > e1000_82575) 3258 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3259 else if (hw->mac.type < em_mac_min) 3260 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3261 } 3262 3263 if (sc->rx_num_queues > 1) { 3264 /* RSS hash needed in the Rx descriptor */ 3265 rxcsum |= E1000_RXCSUM_PCSD; 3266 3267 if (hw->mac.type >= igb_mac_min) 3268 igb_initialize_rss_mapping(sc); 3269 else 3270 em_initialize_rss_mapping(sc); 3271 } 3272 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3273 3274 /* 3275 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3276 * long latencies are observed, like Lenovo X60. This 3277 * change eliminates the problem, but since having positive 3278 * values in RDTR is a known source of problems on other 3279 * platforms another solution is being sought. 3280 */ 3281 if (hw->mac.type == e1000_82573) 3282 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3283 3284 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3285 struct rx_ring *rxr = &que->rxr; 3286 /* Setup the Base and Length of the Rx Descriptor Ring */ 3287 u64 bus_addr = rxr->rx_paddr; 3288 #if 0 3289 u32 rdt = sc->rx_num_queues -1; /* default */ 3290 #endif 3291 3292 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3293 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3294 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3295 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3296 /* Setup the Head and Tail Descriptor Pointers */ 3297 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3298 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3299 } 3300 3301 /* 3302 * Set PTHRESH for improved jumbo performance 3303 * According to 10.2.5.11 of Intel 82574 Datasheet, 3304 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3305 * Only write to RXDCTL(1) if there is a need for different 3306 * settings. 3307 */ 3308 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3309 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3310 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3311 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3312 } else if (hw->mac.type == e1000_82574) { 3313 for (int i = 0; i < sc->rx_num_queues; i++) { 3314 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3315 rxdctl |= 0x20; /* PTHRESH */ 3316 rxdctl |= 4 << 8; /* HTHRESH */ 3317 rxdctl |= 4 << 16;/* WTHRESH */ 3318 rxdctl |= 1 << 24; /* Switch to granularity */ 3319 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3320 } 3321 } else if (hw->mac.type >= igb_mac_min) { 3322 u32 psize, srrctl = 0; 3323 3324 if (if_getmtu(ifp) > ETHERMTU) { 3325 psize = scctx->isc_max_frame_size; 3326 /* are we on a vlan? */ 3327 if (ifp->if_vlantrunk != NULL) 3328 psize += VLAN_TAG_SIZE; 3329 3330 if (sc->vf_ifp) 3331 e1000_rlpml_set_vf(hw, psize); 3332 else 3333 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3334 } 3335 3336 /* Set maximum packet buffer len */ 3337 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3338 E1000_SRRCTL_BSIZEPKT_SHIFT; 3339 3340 /* 3341 * If TX flow control is disabled and there's >1 queue defined, 3342 * enable DROP. 3343 * 3344 * This drops frames rather than hanging the RX MAC for all queues. 3345 */ 3346 if ((sc->rx_num_queues > 1) && 3347 (sc->fc == e1000_fc_none || 3348 sc->fc == e1000_fc_rx_pause)) { 3349 srrctl |= E1000_SRRCTL_DROP_EN; 3350 } 3351 /* Setup the Base and Length of the Rx Descriptor Rings */ 3352 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3353 struct rx_ring *rxr = &que->rxr; 3354 u64 bus_addr = rxr->rx_paddr; 3355 u32 rxdctl; 3356 3357 #ifdef notyet 3358 /* Configure for header split? -- ignore for now */ 3359 rxr->hdr_split = igb_header_split; 3360 #else 3361 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3362 #endif 3363 3364 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3365 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3366 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3367 (uint32_t)(bus_addr >> 32)); 3368 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3369 (uint32_t)bus_addr); 3370 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3371 /* Enable this Queue */ 3372 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3373 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3374 rxdctl &= 0xFFF00000; 3375 rxdctl |= IGB_RX_PTHRESH; 3376 rxdctl |= IGB_RX_HTHRESH << 8; 3377 rxdctl |= IGB_RX_WTHRESH << 16; 3378 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3379 } 3380 } else if (hw->mac.type >= e1000_pch2lan) { 3381 if (if_getmtu(ifp) > ETHERMTU) 3382 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3383 else 3384 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3385 } 3386 3387 /* Make sure VLAN Filters are off */ 3388 rctl &= ~E1000_RCTL_VFE; 3389 3390 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3391 if (hw->mac.type < igb_mac_min) { 3392 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3393 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3394 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3395 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3396 else if (sc->rx_mbuf_sz > 8192) 3397 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3398 else { 3399 rctl |= E1000_RCTL_SZ_2048; 3400 rctl &= ~E1000_RCTL_BSEX; 3401 } 3402 } else 3403 rctl |= E1000_RCTL_SZ_2048; 3404 3405 /* 3406 * rctl bits 11:10 are as follows 3407 * lem: reserved 3408 * em: DTYPE 3409 * igb: reserved 3410 * and should be 00 on all of the above 3411 */ 3412 rctl &= ~0x00000C00; 3413 3414 /* Write out the settings */ 3415 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3416 3417 return; 3418 } 3419 3420 static void 3421 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3422 { 3423 struct e1000_softc *sc = iflib_get_softc(ctx); 3424 u32 index, bit; 3425 3426 index = (vtag >> 5) & 0x7F; 3427 bit = vtag & 0x1F; 3428 sc->shadow_vfta[index] |= (1 << bit); 3429 ++sc->num_vlans; 3430 em_if_vlan_filter_write(sc); 3431 } 3432 3433 static void 3434 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3435 { 3436 struct e1000_softc *sc = iflib_get_softc(ctx); 3437 u32 index, bit; 3438 3439 index = (vtag >> 5) & 0x7F; 3440 bit = vtag & 0x1F; 3441 sc->shadow_vfta[index] &= ~(1 << bit); 3442 --sc->num_vlans; 3443 em_if_vlan_filter_write(sc); 3444 } 3445 3446 static bool 3447 em_if_vlan_filter_capable(if_ctx_t ctx) 3448 { 3449 if_t ifp = iflib_get_ifp(ctx); 3450 3451 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3452 !em_disable_crc_stripping) 3453 return (true); 3454 3455 return (false); 3456 } 3457 3458 static bool 3459 em_if_vlan_filter_used(if_ctx_t ctx) 3460 { 3461 struct e1000_softc *sc = iflib_get_softc(ctx); 3462 3463 if (!em_if_vlan_filter_capable(ctx)) 3464 return (false); 3465 3466 for (int i = 0; i < EM_VFTA_SIZE; i++) 3467 if (sc->shadow_vfta[i] != 0) 3468 return (true); 3469 3470 return (false); 3471 } 3472 3473 static void 3474 em_if_vlan_filter_enable(struct e1000_softc *sc) 3475 { 3476 struct e1000_hw *hw = &sc->hw; 3477 u32 reg; 3478 3479 reg = E1000_READ_REG(hw, E1000_RCTL); 3480 reg &= ~E1000_RCTL_CFIEN; 3481 reg |= E1000_RCTL_VFE; 3482 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3483 } 3484 3485 static void 3486 em_if_vlan_filter_disable(struct e1000_softc *sc) 3487 { 3488 struct e1000_hw *hw = &sc->hw; 3489 u32 reg; 3490 3491 reg = E1000_READ_REG(hw, E1000_RCTL); 3492 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3493 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3494 } 3495 3496 static void 3497 em_if_vlan_filter_write(struct e1000_softc *sc) 3498 { 3499 struct e1000_hw *hw = &sc->hw; 3500 3501 if (sc->vf_ifp) 3502 return; 3503 3504 /* Disable interrupts for lem-class devices during the filter change */ 3505 if (hw->mac.type < em_mac_min) 3506 em_if_intr_disable(sc->ctx); 3507 3508 for (int i = 0; i < EM_VFTA_SIZE; i++) 3509 if (sc->shadow_vfta[i] != 0) { 3510 /* XXXKB: incomplete VF support, we return early above */ 3511 if (sc->vf_ifp) 3512 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3513 else 3514 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3515 } 3516 3517 /* Re-enable interrupts for lem-class devices */ 3518 if (hw->mac.type < em_mac_min) 3519 em_if_intr_enable(sc->ctx); 3520 } 3521 3522 static void 3523 em_setup_vlan_hw_support(if_ctx_t ctx) 3524 { 3525 struct e1000_softc *sc = iflib_get_softc(ctx); 3526 struct e1000_hw *hw = &sc->hw; 3527 struct ifnet *ifp = iflib_get_ifp(ctx); 3528 u32 reg; 3529 3530 /* XXXKB: Return early if we are a VF until VF decap and filter management 3531 * is ready and tested. 3532 */ 3533 if (sc->vf_ifp) 3534 return; 3535 3536 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3537 !em_disable_crc_stripping) { 3538 reg = E1000_READ_REG(hw, E1000_CTRL); 3539 reg |= E1000_CTRL_VME; 3540 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3541 } else { 3542 reg = E1000_READ_REG(hw, E1000_CTRL); 3543 reg &= ~E1000_CTRL_VME; 3544 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3545 } 3546 3547 /* If we aren't doing HW filtering, we're done */ 3548 if (!em_if_vlan_filter_capable(ctx)) { 3549 em_if_vlan_filter_disable(sc); 3550 return; 3551 } 3552 3553 /* 3554 * A soft reset zero's out the VFTA, so 3555 * we need to repopulate it now. 3556 */ 3557 em_if_vlan_filter_write(sc); 3558 3559 /* Enable the Filter Table */ 3560 em_if_vlan_filter_enable(sc); 3561 } 3562 3563 static void 3564 em_if_intr_enable(if_ctx_t ctx) 3565 { 3566 struct e1000_softc *sc = iflib_get_softc(ctx); 3567 struct e1000_hw *hw = &sc->hw; 3568 u32 ims_mask = IMS_ENABLE_MASK; 3569 3570 if (sc->intr_type == IFLIB_INTR_MSIX) { 3571 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3572 ims_mask |= sc->ims; 3573 } 3574 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3575 E1000_WRITE_FLUSH(hw); 3576 } 3577 3578 static void 3579 em_if_intr_disable(if_ctx_t ctx) 3580 { 3581 struct e1000_softc *sc = iflib_get_softc(ctx); 3582 struct e1000_hw *hw = &sc->hw; 3583 3584 if (sc->intr_type == IFLIB_INTR_MSIX) 3585 E1000_WRITE_REG(hw, EM_EIAC, 0); 3586 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3587 E1000_WRITE_FLUSH(hw); 3588 } 3589 3590 static void 3591 igb_if_intr_enable(if_ctx_t ctx) 3592 { 3593 struct e1000_softc *sc = iflib_get_softc(ctx); 3594 struct e1000_hw *hw = &sc->hw; 3595 u32 mask; 3596 3597 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3598 mask = (sc->que_mask | sc->link_mask); 3599 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3600 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3601 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3602 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3603 } else 3604 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3605 E1000_WRITE_FLUSH(hw); 3606 } 3607 3608 static void 3609 igb_if_intr_disable(if_ctx_t ctx) 3610 { 3611 struct e1000_softc *sc = iflib_get_softc(ctx); 3612 struct e1000_hw *hw = &sc->hw; 3613 3614 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3615 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3616 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3617 } 3618 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3619 E1000_WRITE_FLUSH(hw); 3620 } 3621 3622 /* 3623 * Bit of a misnomer, what this really means is 3624 * to enable OS management of the system... aka 3625 * to disable special hardware management features 3626 */ 3627 static void 3628 em_init_manageability(struct e1000_softc *sc) 3629 { 3630 /* A shared code workaround */ 3631 #define E1000_82542_MANC2H E1000_MANC2H 3632 if (sc->has_manage) { 3633 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3634 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3635 3636 /* disable hardware interception of ARP */ 3637 manc &= ~(E1000_MANC_ARP_EN); 3638 3639 /* enable receiving management packets to the host */ 3640 manc |= E1000_MANC_EN_MNG2HOST; 3641 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3642 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3643 manc2h |= E1000_MNG2HOST_PORT_623; 3644 manc2h |= E1000_MNG2HOST_PORT_664; 3645 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3646 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3647 } 3648 } 3649 3650 /* 3651 * Give control back to hardware management 3652 * controller if there is one. 3653 */ 3654 static void 3655 em_release_manageability(struct e1000_softc *sc) 3656 { 3657 if (sc->has_manage) { 3658 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3659 3660 /* re-enable hardware interception of ARP */ 3661 manc |= E1000_MANC_ARP_EN; 3662 manc &= ~E1000_MANC_EN_MNG2HOST; 3663 3664 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3665 } 3666 } 3667 3668 /* 3669 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3670 * For ASF and Pass Through versions of f/w this means 3671 * that the driver is loaded. For AMT version type f/w 3672 * this means that the network i/f is open. 3673 */ 3674 static void 3675 em_get_hw_control(struct e1000_softc *sc) 3676 { 3677 u32 ctrl_ext, swsm; 3678 3679 if (sc->vf_ifp) 3680 return; 3681 3682 if (sc->hw.mac.type == e1000_82573) { 3683 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3684 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3685 swsm | E1000_SWSM_DRV_LOAD); 3686 return; 3687 } 3688 /* else */ 3689 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3690 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3691 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3692 } 3693 3694 /* 3695 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3696 * For ASF and Pass Through versions of f/w this means that 3697 * the driver is no longer loaded. For AMT versions of the 3698 * f/w this means that the network i/f is closed. 3699 */ 3700 static void 3701 em_release_hw_control(struct e1000_softc *sc) 3702 { 3703 u32 ctrl_ext, swsm; 3704 3705 if (!sc->has_manage) 3706 return; 3707 3708 if (sc->hw.mac.type == e1000_82573) { 3709 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3710 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3711 swsm & ~E1000_SWSM_DRV_LOAD); 3712 return; 3713 } 3714 /* else */ 3715 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3716 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3717 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3718 return; 3719 } 3720 3721 static int 3722 em_is_valid_ether_addr(u8 *addr) 3723 { 3724 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3725 3726 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3727 return (false); 3728 } 3729 3730 return (true); 3731 } 3732 3733 /* 3734 ** Parse the interface capabilities with regard 3735 ** to both system management and wake-on-lan for 3736 ** later use. 3737 */ 3738 static void 3739 em_get_wakeup(if_ctx_t ctx) 3740 { 3741 struct e1000_softc *sc = iflib_get_softc(ctx); 3742 device_t dev = iflib_get_dev(ctx); 3743 u16 eeprom_data = 0, device_id, apme_mask; 3744 3745 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3746 apme_mask = EM_EEPROM_APME; 3747 3748 switch (sc->hw.mac.type) { 3749 case e1000_82542: 3750 case e1000_82543: 3751 break; 3752 case e1000_82544: 3753 e1000_read_nvm(&sc->hw, 3754 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3755 apme_mask = EM_82544_APME; 3756 break; 3757 case e1000_82546: 3758 case e1000_82546_rev_3: 3759 if (sc->hw.bus.func == 1) { 3760 e1000_read_nvm(&sc->hw, 3761 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3762 break; 3763 } else 3764 e1000_read_nvm(&sc->hw, 3765 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3766 break; 3767 case e1000_82573: 3768 case e1000_82583: 3769 sc->has_amt = true; 3770 /* FALLTHROUGH */ 3771 case e1000_82571: 3772 case e1000_82572: 3773 case e1000_80003es2lan: 3774 if (sc->hw.bus.func == 1) { 3775 e1000_read_nvm(&sc->hw, 3776 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3777 break; 3778 } else 3779 e1000_read_nvm(&sc->hw, 3780 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3781 break; 3782 case e1000_ich8lan: 3783 case e1000_ich9lan: 3784 case e1000_ich10lan: 3785 case e1000_pchlan: 3786 case e1000_pch2lan: 3787 case e1000_pch_lpt: 3788 case e1000_pch_spt: 3789 case e1000_82575: /* listing all igb devices */ 3790 case e1000_82576: 3791 case e1000_82580: 3792 case e1000_i350: 3793 case e1000_i354: 3794 case e1000_i210: 3795 case e1000_i211: 3796 case e1000_vfadapt: 3797 case e1000_vfadapt_i350: 3798 apme_mask = E1000_WUC_APME; 3799 sc->has_amt = true; 3800 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 3801 break; 3802 default: 3803 e1000_read_nvm(&sc->hw, 3804 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3805 break; 3806 } 3807 if (eeprom_data & apme_mask) 3808 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3809 /* 3810 * We have the eeprom settings, now apply the special cases 3811 * where the eeprom may be wrong or the board won't support 3812 * wake on lan on a particular port 3813 */ 3814 device_id = pci_get_device(dev); 3815 switch (device_id) { 3816 case E1000_DEV_ID_82546GB_PCIE: 3817 sc->wol = 0; 3818 break; 3819 case E1000_DEV_ID_82546EB_FIBER: 3820 case E1000_DEV_ID_82546GB_FIBER: 3821 /* Wake events only supported on port A for dual fiber 3822 * regardless of eeprom setting */ 3823 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3824 E1000_STATUS_FUNC_1) 3825 sc->wol = 0; 3826 break; 3827 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3828 /* if quad port adapter, disable WoL on all but port A */ 3829 if (global_quad_port_a != 0) 3830 sc->wol = 0; 3831 /* Reset for multiple quad port adapters */ 3832 if (++global_quad_port_a == 4) 3833 global_quad_port_a = 0; 3834 break; 3835 case E1000_DEV_ID_82571EB_FIBER: 3836 /* Wake events only supported on port A for dual fiber 3837 * regardless of eeprom setting */ 3838 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3839 E1000_STATUS_FUNC_1) 3840 sc->wol = 0; 3841 break; 3842 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3843 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3844 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3845 /* if quad port adapter, disable WoL on all but port A */ 3846 if (global_quad_port_a != 0) 3847 sc->wol = 0; 3848 /* Reset for multiple quad port adapters */ 3849 if (++global_quad_port_a == 4) 3850 global_quad_port_a = 0; 3851 break; 3852 } 3853 return; 3854 } 3855 3856 3857 /* 3858 * Enable PCI Wake On Lan capability 3859 */ 3860 static void 3861 em_enable_wakeup(if_ctx_t ctx) 3862 { 3863 struct e1000_softc *sc = iflib_get_softc(ctx); 3864 device_t dev = iflib_get_dev(ctx); 3865 if_t ifp = iflib_get_ifp(ctx); 3866 int error = 0; 3867 u32 pmc, ctrl, ctrl_ext, rctl; 3868 u16 status; 3869 3870 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3871 return; 3872 3873 /* 3874 * Determine type of Wakeup: note that wol 3875 * is set with all bits on by default. 3876 */ 3877 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3878 sc->wol &= ~E1000_WUFC_MAG; 3879 3880 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3881 sc->wol &= ~E1000_WUFC_EX; 3882 3883 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3884 sc->wol &= ~E1000_WUFC_MC; 3885 else { 3886 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 3887 rctl |= E1000_RCTL_MPE; 3888 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 3889 } 3890 3891 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3892 goto pme; 3893 3894 /* Advertise the wakeup capability */ 3895 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 3896 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3897 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 3898 3899 /* Keep the laser running on Fiber adapters */ 3900 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3901 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3902 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3903 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3904 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 3905 } 3906 3907 if ((sc->hw.mac.type == e1000_ich8lan) || 3908 (sc->hw.mac.type == e1000_pchlan) || 3909 (sc->hw.mac.type == e1000_ich9lan) || 3910 (sc->hw.mac.type == e1000_ich10lan)) 3911 e1000_suspend_workarounds_ich8lan(&sc->hw); 3912 3913 if ( sc->hw.mac.type >= e1000_pchlan) { 3914 error = em_enable_phy_wakeup(sc); 3915 if (error) 3916 goto pme; 3917 } else { 3918 /* Enable wakeup by the MAC */ 3919 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 3920 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 3921 } 3922 3923 if (sc->hw.phy.type == e1000_phy_igp_3) 3924 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 3925 3926 pme: 3927 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3928 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3929 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3930 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3931 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3932 3933 return; 3934 } 3935 3936 /* 3937 * WOL in the newer chipset interfaces (pchlan) 3938 * require thing to be copied into the phy 3939 */ 3940 static int 3941 em_enable_phy_wakeup(struct e1000_softc *sc) 3942 { 3943 struct e1000_hw *hw = &sc->hw; 3944 u32 mreg, ret = 0; 3945 u16 preg; 3946 3947 /* copy MAC RARs to PHY RARs */ 3948 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3949 3950 /* copy MAC MTA to PHY MTA */ 3951 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 3952 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3953 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3954 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3955 (u16)((mreg >> 16) & 0xFFFF)); 3956 } 3957 3958 /* configure PHY Rx Control register */ 3959 e1000_read_phy_reg(hw, BM_RCTL, &preg); 3960 mreg = E1000_READ_REG(hw, E1000_RCTL); 3961 if (mreg & E1000_RCTL_UPE) 3962 preg |= BM_RCTL_UPE; 3963 if (mreg & E1000_RCTL_MPE) 3964 preg |= BM_RCTL_MPE; 3965 preg &= ~(BM_RCTL_MO_MASK); 3966 if (mreg & E1000_RCTL_MO_3) 3967 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3968 << BM_RCTL_MO_SHIFT); 3969 if (mreg & E1000_RCTL_BAM) 3970 preg |= BM_RCTL_BAM; 3971 if (mreg & E1000_RCTL_PMCF) 3972 preg |= BM_RCTL_PMCF; 3973 mreg = E1000_READ_REG(hw, E1000_CTRL); 3974 if (mreg & E1000_CTRL_RFCE) 3975 preg |= BM_RCTL_RFCE; 3976 e1000_write_phy_reg(hw, BM_RCTL, preg); 3977 3978 /* enable PHY wakeup in MAC register */ 3979 E1000_WRITE_REG(hw, E1000_WUC, 3980 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3981 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 3982 3983 /* configure and enable PHY wakeup in PHY registers */ 3984 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 3985 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 3986 3987 /* activate PHY wakeup */ 3988 ret = hw->phy.ops.acquire(hw); 3989 if (ret) { 3990 printf("Could not acquire PHY\n"); 3991 return ret; 3992 } 3993 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3994 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3995 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3996 if (ret) { 3997 printf("Could not read PHY page 769\n"); 3998 goto out; 3999 } 4000 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4001 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4002 if (ret) 4003 printf("Could not set PHY Host Wakeup bit\n"); 4004 out: 4005 hw->phy.ops.release(hw); 4006 4007 return ret; 4008 } 4009 4010 static void 4011 em_if_led_func(if_ctx_t ctx, int onoff) 4012 { 4013 struct e1000_softc *sc = iflib_get_softc(ctx); 4014 4015 if (onoff) { 4016 e1000_setup_led(&sc->hw); 4017 e1000_led_on(&sc->hw); 4018 } else { 4019 e1000_led_off(&sc->hw); 4020 e1000_cleanup_led(&sc->hw); 4021 } 4022 } 4023 4024 /* 4025 * Disable the L0S and L1 LINK states 4026 */ 4027 static void 4028 em_disable_aspm(struct e1000_softc *sc) 4029 { 4030 int base, reg; 4031 u16 link_cap,link_ctrl; 4032 device_t dev = sc->dev; 4033 4034 switch (sc->hw.mac.type) { 4035 case e1000_82573: 4036 case e1000_82574: 4037 case e1000_82583: 4038 break; 4039 default: 4040 return; 4041 } 4042 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4043 return; 4044 reg = base + PCIER_LINK_CAP; 4045 link_cap = pci_read_config(dev, reg, 2); 4046 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4047 return; 4048 reg = base + PCIER_LINK_CTL; 4049 link_ctrl = pci_read_config(dev, reg, 2); 4050 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4051 pci_write_config(dev, reg, link_ctrl, 2); 4052 return; 4053 } 4054 4055 /********************************************************************** 4056 * 4057 * Update the board statistics counters. 4058 * 4059 **********************************************************************/ 4060 static void 4061 em_update_stats_counters(struct e1000_softc *sc) 4062 { 4063 u64 prev_xoffrxc = sc->stats.xoffrxc; 4064 4065 if(sc->hw.phy.media_type == e1000_media_type_copper || 4066 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4067 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4068 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4069 } 4070 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4071 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4072 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4073 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4074 4075 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4076 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4077 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4078 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4079 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4080 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4081 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4082 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4083 /* 4084 ** For watchdog management we need to know if we have been 4085 ** paused during the last interval, so capture that here. 4086 */ 4087 if (sc->stats.xoffrxc != prev_xoffrxc) 4088 sc->shared->isc_pause_frames = 1; 4089 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4090 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4091 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4092 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4093 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4094 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4095 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4096 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4097 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4098 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4099 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4100 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4101 4102 /* For the 64-bit byte counters the low dword must be read first. */ 4103 /* Both registers clear on the read of the high dword */ 4104 4105 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4106 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4107 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4108 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4109 4110 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4111 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4112 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4113 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4114 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4115 4116 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4117 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4118 4119 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4120 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4121 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4122 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4123 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4124 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4125 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4126 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4127 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4128 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4129 4130 /* Interrupt Counts */ 4131 4132 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4133 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4134 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4135 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4136 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4137 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4138 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4139 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4140 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4141 4142 if (sc->hw.mac.type >= e1000_82543) { 4143 sc->stats.algnerrc += 4144 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4145 sc->stats.rxerrc += 4146 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4147 sc->stats.tncrs += 4148 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4149 sc->stats.cexterr += 4150 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4151 sc->stats.tsctc += 4152 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4153 sc->stats.tsctfc += 4154 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4155 } 4156 } 4157 4158 static uint64_t 4159 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4160 { 4161 struct e1000_softc *sc = iflib_get_softc(ctx); 4162 struct ifnet *ifp = iflib_get_ifp(ctx); 4163 4164 switch (cnt) { 4165 case IFCOUNTER_COLLISIONS: 4166 return (sc->stats.colc); 4167 case IFCOUNTER_IERRORS: 4168 return (sc->dropped_pkts + sc->stats.rxerrc + 4169 sc->stats.crcerrs + sc->stats.algnerrc + 4170 sc->stats.ruc + sc->stats.roc + 4171 sc->stats.mpc + sc->stats.cexterr); 4172 case IFCOUNTER_OERRORS: 4173 return (sc->stats.ecol + sc->stats.latecol + 4174 sc->watchdog_events); 4175 default: 4176 return (if_get_counter_default(ifp, cnt)); 4177 } 4178 } 4179 4180 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4181 * @ctx: iflib context 4182 * @event: event code to check 4183 * 4184 * Defaults to returning true for unknown events. 4185 * 4186 * @returns true if iflib needs to reinit the interface 4187 */ 4188 static bool 4189 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4190 { 4191 switch (event) { 4192 case IFLIB_RESTART_VLAN_CONFIG: 4193 return (false); 4194 default: 4195 return (true); 4196 } 4197 } 4198 4199 /* Export a single 32-bit register via a read-only sysctl. */ 4200 static int 4201 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4202 { 4203 struct e1000_softc *sc; 4204 u_int val; 4205 4206 sc = oidp->oid_arg1; 4207 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4208 return (sysctl_handle_int(oidp, &val, 0, req)); 4209 } 4210 4211 /* 4212 * Add sysctl variables, one per statistic, to the system. 4213 */ 4214 static void 4215 em_add_hw_stats(struct e1000_softc *sc) 4216 { 4217 device_t dev = iflib_get_dev(sc->ctx); 4218 struct em_tx_queue *tx_que = sc->tx_queues; 4219 struct em_rx_queue *rx_que = sc->rx_queues; 4220 4221 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4222 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4223 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4224 struct e1000_hw_stats *stats = &sc->stats; 4225 4226 struct sysctl_oid *stat_node, *queue_node, *int_node; 4227 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4228 4229 #define QUEUE_NAME_LEN 32 4230 char namebuf[QUEUE_NAME_LEN]; 4231 4232 /* Driver Statistics */ 4233 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4234 CTLFLAG_RD, &sc->dropped_pkts, 4235 "Driver dropped packets"); 4236 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4237 CTLFLAG_RD, &sc->link_irq, 4238 "Link MSI-X IRQ Handled"); 4239 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4240 CTLFLAG_RD, &sc->rx_overruns, 4241 "RX overruns"); 4242 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4243 CTLFLAG_RD, &sc->watchdog_events, 4244 "Watchdog timeouts"); 4245 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4246 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4247 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4248 "Device Control Register"); 4249 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4250 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4251 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4252 "Receiver Control Register"); 4253 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4254 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4255 "Flow Control High Watermark"); 4256 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4257 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4258 "Flow Control Low Watermark"); 4259 4260 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4261 struct tx_ring *txr = &tx_que->txr; 4262 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4263 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4264 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4265 queue_list = SYSCTL_CHILDREN(queue_node); 4266 4267 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4268 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4269 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4270 "Transmit Descriptor Head"); 4271 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4272 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4273 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4274 "Transmit Descriptor Tail"); 4275 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4276 CTLFLAG_RD, &txr->tx_irq, 4277 "Queue MSI-X Transmit Interrupts"); 4278 } 4279 4280 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4281 struct rx_ring *rxr = &rx_que->rxr; 4282 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4283 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4284 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4285 queue_list = SYSCTL_CHILDREN(queue_node); 4286 4287 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4288 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4289 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4290 "Receive Descriptor Head"); 4291 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4292 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4293 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4294 "Receive Descriptor Tail"); 4295 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4296 CTLFLAG_RD, &rxr->rx_irq, 4297 "Queue MSI-X Receive Interrupts"); 4298 } 4299 4300 /* MAC stats get their own sub node */ 4301 4302 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4303 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4304 stat_list = SYSCTL_CHILDREN(stat_node); 4305 4306 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4307 CTLFLAG_RD, &stats->ecol, 4308 "Excessive collisions"); 4309 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4310 CTLFLAG_RD, &stats->scc, 4311 "Single collisions"); 4312 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4313 CTLFLAG_RD, &stats->mcc, 4314 "Multiple collisions"); 4315 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4316 CTLFLAG_RD, &stats->latecol, 4317 "Late collisions"); 4318 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4319 CTLFLAG_RD, &stats->colc, 4320 "Collision Count"); 4321 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4322 CTLFLAG_RD, &sc->stats.symerrs, 4323 "Symbol Errors"); 4324 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4325 CTLFLAG_RD, &sc->stats.sec, 4326 "Sequence Errors"); 4327 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4328 CTLFLAG_RD, &sc->stats.dc, 4329 "Defer Count"); 4330 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4331 CTLFLAG_RD, &sc->stats.mpc, 4332 "Missed Packets"); 4333 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4334 CTLFLAG_RD, &sc->stats.rnbc, 4335 "Receive No Buffers"); 4336 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4337 CTLFLAG_RD, &sc->stats.ruc, 4338 "Receive Undersize"); 4339 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4340 CTLFLAG_RD, &sc->stats.rfc, 4341 "Fragmented Packets Received "); 4342 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4343 CTLFLAG_RD, &sc->stats.roc, 4344 "Oversized Packets Received"); 4345 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4346 CTLFLAG_RD, &sc->stats.rjc, 4347 "Recevied Jabber"); 4348 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4349 CTLFLAG_RD, &sc->stats.rxerrc, 4350 "Receive Errors"); 4351 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4352 CTLFLAG_RD, &sc->stats.crcerrs, 4353 "CRC errors"); 4354 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4355 CTLFLAG_RD, &sc->stats.algnerrc, 4356 "Alignment Errors"); 4357 /* On 82575 these are collision counts */ 4358 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4359 CTLFLAG_RD, &sc->stats.cexterr, 4360 "Collision/Carrier extension errors"); 4361 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4362 CTLFLAG_RD, &sc->stats.xonrxc, 4363 "XON Received"); 4364 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4365 CTLFLAG_RD, &sc->stats.xontxc, 4366 "XON Transmitted"); 4367 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4368 CTLFLAG_RD, &sc->stats.xoffrxc, 4369 "XOFF Received"); 4370 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4371 CTLFLAG_RD, &sc->stats.xofftxc, 4372 "XOFF Transmitted"); 4373 4374 /* Packet Reception Stats */ 4375 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4376 CTLFLAG_RD, &sc->stats.tpr, 4377 "Total Packets Received "); 4378 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4379 CTLFLAG_RD, &sc->stats.gprc, 4380 "Good Packets Received"); 4381 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4382 CTLFLAG_RD, &sc->stats.bprc, 4383 "Broadcast Packets Received"); 4384 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4385 CTLFLAG_RD, &sc->stats.mprc, 4386 "Multicast Packets Received"); 4387 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4388 CTLFLAG_RD, &sc->stats.prc64, 4389 "64 byte frames received "); 4390 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4391 CTLFLAG_RD, &sc->stats.prc127, 4392 "65-127 byte frames received"); 4393 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4394 CTLFLAG_RD, &sc->stats.prc255, 4395 "128-255 byte frames received"); 4396 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4397 CTLFLAG_RD, &sc->stats.prc511, 4398 "256-511 byte frames received"); 4399 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4400 CTLFLAG_RD, &sc->stats.prc1023, 4401 "512-1023 byte frames received"); 4402 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4403 CTLFLAG_RD, &sc->stats.prc1522, 4404 "1023-1522 byte frames received"); 4405 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4406 CTLFLAG_RD, &sc->stats.gorc, 4407 "Good Octets Received"); 4408 4409 /* Packet Transmission Stats */ 4410 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4411 CTLFLAG_RD, &sc->stats.gotc, 4412 "Good Octets Transmitted"); 4413 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4414 CTLFLAG_RD, &sc->stats.tpt, 4415 "Total Packets Transmitted"); 4416 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4417 CTLFLAG_RD, &sc->stats.gptc, 4418 "Good Packets Transmitted"); 4419 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4420 CTLFLAG_RD, &sc->stats.bptc, 4421 "Broadcast Packets Transmitted"); 4422 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4423 CTLFLAG_RD, &sc->stats.mptc, 4424 "Multicast Packets Transmitted"); 4425 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4426 CTLFLAG_RD, &sc->stats.ptc64, 4427 "64 byte frames transmitted "); 4428 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4429 CTLFLAG_RD, &sc->stats.ptc127, 4430 "65-127 byte frames transmitted"); 4431 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4432 CTLFLAG_RD, &sc->stats.ptc255, 4433 "128-255 byte frames transmitted"); 4434 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4435 CTLFLAG_RD, &sc->stats.ptc511, 4436 "256-511 byte frames transmitted"); 4437 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4438 CTLFLAG_RD, &sc->stats.ptc1023, 4439 "512-1023 byte frames transmitted"); 4440 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4441 CTLFLAG_RD, &sc->stats.ptc1522, 4442 "1024-1522 byte frames transmitted"); 4443 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4444 CTLFLAG_RD, &sc->stats.tsctc, 4445 "TSO Contexts Transmitted"); 4446 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4447 CTLFLAG_RD, &sc->stats.tsctfc, 4448 "TSO Contexts Failed"); 4449 4450 4451 /* Interrupt Stats */ 4452 4453 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4454 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4455 int_list = SYSCTL_CHILDREN(int_node); 4456 4457 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4458 CTLFLAG_RD, &sc->stats.iac, 4459 "Interrupt Assertion Count"); 4460 4461 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4462 CTLFLAG_RD, &sc->stats.icrxptc, 4463 "Interrupt Cause Rx Pkt Timer Expire Count"); 4464 4465 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4466 CTLFLAG_RD, &sc->stats.icrxatc, 4467 "Interrupt Cause Rx Abs Timer Expire Count"); 4468 4469 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4470 CTLFLAG_RD, &sc->stats.ictxptc, 4471 "Interrupt Cause Tx Pkt Timer Expire Count"); 4472 4473 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4474 CTLFLAG_RD, &sc->stats.ictxatc, 4475 "Interrupt Cause Tx Abs Timer Expire Count"); 4476 4477 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4478 CTLFLAG_RD, &sc->stats.ictxqec, 4479 "Interrupt Cause Tx Queue Empty Count"); 4480 4481 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4482 CTLFLAG_RD, &sc->stats.ictxqmtc, 4483 "Interrupt Cause Tx Queue Min Thresh Count"); 4484 4485 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4486 CTLFLAG_RD, &sc->stats.icrxdmtc, 4487 "Interrupt Cause Rx Desc Min Thresh Count"); 4488 4489 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4490 CTLFLAG_RD, &sc->stats.icrxoc, 4491 "Interrupt Cause Receiver Overrun Count"); 4492 } 4493 4494 static void 4495 em_fw_version_locked(if_ctx_t ctx) 4496 { 4497 struct e1000_softc *sc = iflib_get_softc(ctx); 4498 struct e1000_hw *hw = &sc->hw; 4499 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4500 uint16_t eep = 0; 4501 4502 /* 4503 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4504 * NVM locking model, so we do it in em_if_attach_pre() and store the 4505 * info in the softc 4506 */ 4507 ASSERT_CTX_LOCK_HELD(hw); 4508 4509 *fw_ver = (struct e1000_fw_version){0}; 4510 4511 if (hw->mac.type >= igb_mac_min) { 4512 /* 4513 * Use the Shared Code for igb(4) 4514 */ 4515 e1000_get_fw_version(hw, fw_ver); 4516 } else { 4517 /* 4518 * Otherwise, EEPROM version should be present on (almost?) all 4519 * devices here 4520 */ 4521 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4522 INIT_DEBUGOUT("can't get EEPROM version"); 4523 return; 4524 } 4525 4526 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4527 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4528 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4529 } 4530 } 4531 4532 static void 4533 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4534 { 4535 const char *space = ""; 4536 4537 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4538 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4539 fw_ver->eep_minor, fw_ver->eep_build); 4540 space = " "; 4541 } 4542 4543 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4544 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4545 space, fw_ver->invm_major, fw_ver->invm_minor, 4546 fw_ver->invm_img_type); 4547 space = " "; 4548 } 4549 4550 if (fw_ver->or_valid) { 4551 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4552 space, fw_ver->or_major, fw_ver->or_build, 4553 fw_ver->or_patch); 4554 space = " "; 4555 } 4556 4557 if (fw_ver->etrack_id) 4558 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4559 } 4560 4561 static void 4562 em_print_fw_version(struct e1000_softc *sc ) 4563 { 4564 device_t dev = sc->dev; 4565 struct sbuf *buf; 4566 int error = 0; 4567 4568 buf = sbuf_new_auto(); 4569 if (!buf) { 4570 device_printf(dev, "Could not allocate sbuf for output.\n"); 4571 return; 4572 } 4573 4574 em_sbuf_fw_version(&sc->fw_ver, buf); 4575 4576 error = sbuf_finish(buf); 4577 if (error) 4578 device_printf(dev, "Error finishing sbuf: %d\n", error); 4579 else if (sbuf_len(buf)) 4580 device_printf(dev, "%s\n", sbuf_data(buf)); 4581 4582 sbuf_delete(buf); 4583 } 4584 4585 static int 4586 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4587 { 4588 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4589 device_t dev = sc->dev; 4590 struct sbuf *buf; 4591 int error = 0; 4592 4593 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4594 if (!buf) { 4595 device_printf(dev, "Could not allocate sbuf for output.\n"); 4596 return (ENOMEM); 4597 } 4598 4599 em_sbuf_fw_version(&sc->fw_ver, buf); 4600 4601 error = sbuf_finish(buf); 4602 if (error) 4603 device_printf(dev, "Error finishing sbuf: %d\n", error); 4604 4605 sbuf_delete(buf); 4606 4607 return (0); 4608 } 4609 4610 /********************************************************************** 4611 * 4612 * This routine provides a way to dump out the adapter eeprom, 4613 * often a useful debug/service tool. This only dumps the first 4614 * 32 words, stuff that matters is in that extent. 4615 * 4616 **********************************************************************/ 4617 static int 4618 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4619 { 4620 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4621 int error; 4622 int result; 4623 4624 result = -1; 4625 error = sysctl_handle_int(oidp, &result, 0, req); 4626 4627 if (error || !req->newptr) 4628 return (error); 4629 4630 /* 4631 * This value will cause a hex dump of the 4632 * first 32 16-bit words of the EEPROM to 4633 * the screen. 4634 */ 4635 if (result == 1) 4636 em_print_nvm_info(sc); 4637 4638 return (error); 4639 } 4640 4641 static void 4642 em_print_nvm_info(struct e1000_softc *sc) 4643 { 4644 struct e1000_hw *hw = &sc->hw; 4645 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4646 u16 eeprom_data; 4647 int i, j, row = 0; 4648 4649 /* Its a bit crude, but it gets the job done */ 4650 printf("\nInterface EEPROM Dump:\n"); 4651 printf("Offset\n0x0000 "); 4652 4653 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4654 sx_xlock(iflib_ctx_lock); 4655 ASSERT_CTX_LOCK_HELD(hw); 4656 for (i = 0, j = 0; i < 32; i++, j++) { 4657 if (j == 8) { /* Make the offset block */ 4658 j = 0; ++row; 4659 printf("\n0x00%x0 ",row); 4660 } 4661 e1000_read_nvm(hw, i, 1, &eeprom_data); 4662 printf("%04x ", eeprom_data); 4663 } 4664 sx_xunlock(iflib_ctx_lock); 4665 printf("\n"); 4666 } 4667 4668 static int 4669 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4670 { 4671 struct em_int_delay_info *info; 4672 struct e1000_softc *sc; 4673 u32 regval; 4674 int error, usecs, ticks; 4675 4676 info = (struct em_int_delay_info *) arg1; 4677 usecs = info->value; 4678 error = sysctl_handle_int(oidp, &usecs, 0, req); 4679 if (error != 0 || req->newptr == NULL) 4680 return (error); 4681 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4682 return (EINVAL); 4683 info->value = usecs; 4684 ticks = EM_USECS_TO_TICKS(usecs); 4685 if (info->offset == E1000_ITR) /* units are 256ns here */ 4686 ticks *= 4; 4687 4688 sc = info->sc; 4689 4690 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4691 regval = (regval & ~0xffff) | (ticks & 0xffff); 4692 /* Handle a few special cases. */ 4693 switch (info->offset) { 4694 case E1000_RDTR: 4695 break; 4696 case E1000_TIDV: 4697 if (ticks == 0) { 4698 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4699 /* Don't write 0 into the TIDV register. */ 4700 regval++; 4701 } else 4702 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4703 break; 4704 } 4705 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4706 return (0); 4707 } 4708 4709 static void 4710 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4711 const char *description, struct em_int_delay_info *info, 4712 int offset, int value) 4713 { 4714 info->sc = sc; 4715 info->offset = offset; 4716 info->value = value; 4717 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4718 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4719 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4720 info, 0, em_sysctl_int_delay, "I", description); 4721 } 4722 4723 /* 4724 * Set flow control using sysctl: 4725 * Flow control values: 4726 * 0 - off 4727 * 1 - rx pause 4728 * 2 - tx pause 4729 * 3 - full 4730 */ 4731 static int 4732 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4733 { 4734 int error; 4735 static int input = 3; /* default is full */ 4736 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4737 4738 error = sysctl_handle_int(oidp, &input, 0, req); 4739 4740 if ((error) || (req->newptr == NULL)) 4741 return (error); 4742 4743 if (input == sc->fc) /* no change? */ 4744 return (error); 4745 4746 switch (input) { 4747 case e1000_fc_rx_pause: 4748 case e1000_fc_tx_pause: 4749 case e1000_fc_full: 4750 case e1000_fc_none: 4751 sc->hw.fc.requested_mode = input; 4752 sc->fc = input; 4753 break; 4754 default: 4755 /* Do nothing */ 4756 return (error); 4757 } 4758 4759 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4760 e1000_force_mac_fc(&sc->hw); 4761 return (error); 4762 } 4763 4764 /* 4765 * Manage Energy Efficient Ethernet: 4766 * Control values: 4767 * 0/1 - enabled/disabled 4768 */ 4769 static int 4770 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4771 { 4772 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4773 int error, value; 4774 4775 value = sc->hw.dev_spec.ich8lan.eee_disable; 4776 error = sysctl_handle_int(oidp, &value, 0, req); 4777 if (error || req->newptr == NULL) 4778 return (error); 4779 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4780 em_if_init(sc->ctx); 4781 4782 return (0); 4783 } 4784 4785 static int 4786 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4787 { 4788 struct e1000_softc *sc; 4789 int error; 4790 int result; 4791 4792 result = -1; 4793 error = sysctl_handle_int(oidp, &result, 0, req); 4794 4795 if (error || !req->newptr) 4796 return (error); 4797 4798 if (result == 1) { 4799 sc = (struct e1000_softc *) arg1; 4800 em_print_debug_info(sc); 4801 } 4802 4803 return (error); 4804 } 4805 4806 static int 4807 em_get_rs(SYSCTL_HANDLER_ARGS) 4808 { 4809 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4810 int error; 4811 int result; 4812 4813 result = 0; 4814 error = sysctl_handle_int(oidp, &result, 0, req); 4815 4816 if (error || !req->newptr || result != 1) 4817 return (error); 4818 em_dump_rs(sc); 4819 4820 return (error); 4821 } 4822 4823 static void 4824 em_if_debug(if_ctx_t ctx) 4825 { 4826 em_dump_rs(iflib_get_softc(ctx)); 4827 } 4828 4829 /* 4830 * This routine is meant to be fluid, add whatever is 4831 * needed for debugging a problem. -jfv 4832 */ 4833 static void 4834 em_print_debug_info(struct e1000_softc *sc) 4835 { 4836 device_t dev = iflib_get_dev(sc->ctx); 4837 struct ifnet *ifp = iflib_get_ifp(sc->ctx); 4838 struct tx_ring *txr = &sc->tx_queues->txr; 4839 struct rx_ring *rxr = &sc->rx_queues->rxr; 4840 4841 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4842 printf("Interface is RUNNING "); 4843 else 4844 printf("Interface is NOT RUNNING\n"); 4845 4846 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4847 printf("and INACTIVE\n"); 4848 else 4849 printf("and ACTIVE\n"); 4850 4851 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 4852 device_printf(dev, "TX Queue %d ------\n", i); 4853 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4854 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 4855 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 4856 4857 } 4858 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 4859 device_printf(dev, "RX Queue %d ------\n", j); 4860 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4861 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 4862 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 4863 } 4864 } 4865 4866 /* 4867 * 82574 only: 4868 * Write a new value to the EEPROM increasing the number of MSI-X 4869 * vectors from 3 to 5, for proper multiqueue support. 4870 */ 4871 static void 4872 em_enable_vectors_82574(if_ctx_t ctx) 4873 { 4874 struct e1000_softc *sc = iflib_get_softc(ctx); 4875 struct e1000_hw *hw = &sc->hw; 4876 device_t dev = iflib_get_dev(ctx); 4877 u16 edata; 4878 4879 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4880 if (bootverbose) 4881 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4882 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4883 device_printf(dev, "Writing to eeprom: increasing " 4884 "reported MSI-X vectors from 3 to 5...\n"); 4885 edata &= ~(EM_NVM_MSIX_N_MASK); 4886 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4887 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4888 e1000_update_nvm_checksum(hw); 4889 device_printf(dev, "Writing to eeprom: done\n"); 4890 } 4891 } 4892