1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #ifndef _E1000_HW_H_ 37 #define _E1000_HW_H_ 38 39 #include "e1000_osdep.h" 40 #include "e1000_regs.h" 41 #include "e1000_defines.h" 42 43 struct e1000_hw; 44 45 #define E1000_DEV_ID_82542 0x1000 46 #define E1000_DEV_ID_82543GC_FIBER 0x1001 47 #define E1000_DEV_ID_82543GC_COPPER 0x1004 48 #define E1000_DEV_ID_82544EI_COPPER 0x1008 49 #define E1000_DEV_ID_82544EI_FIBER 0x1009 50 #define E1000_DEV_ID_82544GC_COPPER 0x100C 51 #define E1000_DEV_ID_82544GC_LOM 0x100D 52 #define E1000_DEV_ID_82540EM 0x100E 53 #define E1000_DEV_ID_82540EM_LOM 0x1015 54 #define E1000_DEV_ID_82540EP_LOM 0x1016 55 #define E1000_DEV_ID_82540EP 0x1017 56 #define E1000_DEV_ID_82540EP_LP 0x101E 57 #define E1000_DEV_ID_82545EM_COPPER 0x100F 58 #define E1000_DEV_ID_82545EM_FIBER 0x1011 59 #define E1000_DEV_ID_82545GM_COPPER 0x1026 60 #define E1000_DEV_ID_82545GM_FIBER 0x1027 61 #define E1000_DEV_ID_82545GM_SERDES 0x1028 62 #define E1000_DEV_ID_82546EB_COPPER 0x1010 63 #define E1000_DEV_ID_82546EB_FIBER 0x1012 64 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 65 #define E1000_DEV_ID_82546GB_COPPER 0x1079 66 #define E1000_DEV_ID_82546GB_FIBER 0x107A 67 #define E1000_DEV_ID_82546GB_SERDES 0x107B 68 #define E1000_DEV_ID_82546GB_PCIE 0x108A 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 70 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 71 #define E1000_DEV_ID_82541EI 0x1013 72 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 73 #define E1000_DEV_ID_82541ER_LOM 0x1014 74 #define E1000_DEV_ID_82541ER 0x1078 75 #define E1000_DEV_ID_82541GI 0x1076 76 #define E1000_DEV_ID_82541GI_LF 0x107C 77 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 78 #define E1000_DEV_ID_82547EI 0x1019 79 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 80 #define E1000_DEV_ID_82547GI 0x1075 81 #define E1000_DEV_ID_82571EB_COPPER 0x105E 82 #define E1000_DEV_ID_82571EB_FIBER 0x105F 83 #define E1000_DEV_ID_82571EB_SERDES 0x1060 84 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 85 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 86 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 87 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 88 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 89 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 90 #define E1000_DEV_ID_82572EI_COPPER 0x107D 91 #define E1000_DEV_ID_82572EI_FIBER 0x107E 92 #define E1000_DEV_ID_82572EI_SERDES 0x107F 93 #define E1000_DEV_ID_82572EI 0x10B9 94 #define E1000_DEV_ID_82573E 0x108B 95 #define E1000_DEV_ID_82573E_IAMT 0x108C 96 #define E1000_DEV_ID_82573L 0x109A 97 #define E1000_DEV_ID_82574L 0x10D3 98 #define E1000_DEV_ID_82574LA 0x10F6 99 #define E1000_DEV_ID_82583V 0x150C 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 104 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 105 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 106 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 107 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 108 #define E1000_DEV_ID_ICH8_IFE 0x104C 109 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 110 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 111 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 112 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 113 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 114 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 115 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 116 #define E1000_DEV_ID_ICH9_BM 0x10E5 117 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 118 #define E1000_DEV_ID_ICH9_IFE 0x10C0 119 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 120 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 121 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 122 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 123 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 124 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 125 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 126 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 127 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 128 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 129 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 130 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 131 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 132 #define E1000_DEV_ID_PCH2_LV_V 0x1503 133 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 134 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 135 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 136 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 137 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 138 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 139 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 140 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 141 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 142 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 143 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 144 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 145 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 146 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 147 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 148 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 149 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 150 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 151 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 152 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 153 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 154 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 155 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 156 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 157 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 158 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 159 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 160 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 161 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 162 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 163 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 164 #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 165 #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 166 #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 167 #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 168 #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 169 #define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5 170 #define E1000_DEV_ID_PCH_ADL_I219_LM16 0x1A1E 171 #define E1000_DEV_ID_PCH_ADL_I219_V16 0x1A1F 172 #define E1000_DEV_ID_PCH_ADL_I219_LM17 0x1A1C 173 #define E1000_DEV_ID_PCH_ADL_I219_V17 0x1A1D 174 #define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A 175 #define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B 176 #define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C 177 #define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D 178 #define E1000_DEV_ID_PCH_LNL_I219_LM20 0x550E 179 #define E1000_DEV_ID_PCH_LNL_I219_V20 0x550F 180 #define E1000_DEV_ID_PCH_LNL_I219_LM21 0x5510 181 #define E1000_DEV_ID_PCH_LNL_I219_V21 0x5511 182 #define E1000_DEV_ID_PCH_RPL_I219_LM22 0x0DC7 183 #define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8 184 #define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5 185 #define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6 186 #define E1000_DEV_ID_PCH_ARL_I219_LM24 0x57A0 187 #define E1000_DEV_ID_PCH_ARL_I219_V24 0x57A1 188 #define E1000_DEV_ID_PCH_PTP_I219_LM25 0x57B3 189 #define E1000_DEV_ID_PCH_PTP_I219_V25 0x57B4 190 #define E1000_DEV_ID_PCH_PTP_I219_LM26 0x57B5 191 #define E1000_DEV_ID_PCH_PTP_I219_V26 0x57B6 192 #define E1000_DEV_ID_PCH_PTP_I219_LM27 0x57B7 193 #define E1000_DEV_ID_PCH_PTP_I219_V27 0x57B8 194 #define E1000_DEV_ID_82576 0x10C9 195 #define E1000_DEV_ID_82576_FIBER 0x10E6 196 #define E1000_DEV_ID_82576_SERDES 0x10E7 197 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 198 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 199 #define E1000_DEV_ID_82576_NS 0x150A 200 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 201 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 202 #define E1000_DEV_ID_82576_VF 0x10CA 203 #define E1000_DEV_ID_82576_VF_HV 0x152D 204 #define E1000_DEV_ID_I350_VF 0x1520 205 #define E1000_DEV_ID_I350_VF_HV 0x152F 206 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 207 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 208 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 209 #define E1000_DEV_ID_82580_COPPER 0x150E 210 #define E1000_DEV_ID_82580_FIBER 0x150F 211 #define E1000_DEV_ID_82580_SERDES 0x1510 212 #define E1000_DEV_ID_82580_SGMII 0x1511 213 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 214 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 215 #define E1000_DEV_ID_I350_COPPER 0x1521 216 #define E1000_DEV_ID_I350_FIBER 0x1522 217 #define E1000_DEV_ID_I350_SERDES 0x1523 218 #define E1000_DEV_ID_I350_SGMII 0x1524 219 #define E1000_DEV_ID_I350_DA4 0x1546 220 #define E1000_DEV_ID_I210_COPPER 0x1533 221 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 222 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 223 #define E1000_DEV_ID_I210_FIBER 0x1536 224 #define E1000_DEV_ID_I210_SERDES 0x1537 225 #define E1000_DEV_ID_I210_SGMII 0x1538 226 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 227 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 228 #define E1000_DEV_ID_I210_SGMII_FLASHLESS 0x15F6 229 #define E1000_DEV_ID_I211_COPPER 0x1539 230 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 231 #define E1000_DEV_ID_I354_SGMII 0x1F41 232 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 233 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 234 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 235 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 236 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 237 238 #define E1000_REVISION_0 0 239 #define E1000_REVISION_1 1 240 #define E1000_REVISION_2 2 241 #define E1000_REVISION_3 3 242 #define E1000_REVISION_4 4 243 244 #define E1000_FUNC_0 0 245 #define E1000_FUNC_1 1 246 #define E1000_FUNC_2 2 247 #define E1000_FUNC_3 3 248 249 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 250 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 251 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 252 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 253 254 enum e1000_mac_type { 255 e1000_undefined = 0, 256 e1000_82542, 257 e1000_82543, 258 e1000_82544, 259 e1000_82540, 260 e1000_82545, 261 e1000_82545_rev_3, 262 e1000_82546, 263 e1000_82546_rev_3, 264 e1000_82541, 265 e1000_82541_rev_2, 266 e1000_82547, 267 e1000_82547_rev_2, 268 e1000_82571, 269 e1000_82572, 270 e1000_82573, 271 e1000_82574, 272 e1000_82583, 273 e1000_80003es2lan, 274 e1000_ich8lan, 275 e1000_ich9lan, 276 e1000_ich10lan, 277 e1000_pchlan, 278 e1000_pch2lan, 279 e1000_pch_lpt, 280 e1000_pch_spt, 281 e1000_pch_cnp, 282 e1000_pch_tgp, 283 e1000_pch_adp, 284 e1000_pch_mtp, 285 e1000_pch_ptp, 286 e1000_82575, 287 e1000_82576, 288 e1000_82580, 289 e1000_i350, 290 e1000_i354, 291 e1000_i210, 292 e1000_i211, 293 e1000_vfadapt, 294 e1000_vfadapt_i350, 295 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 296 }; 297 298 enum e1000_media_type { 299 e1000_media_type_unknown = 0, 300 e1000_media_type_copper = 1, 301 e1000_media_type_fiber = 2, 302 e1000_media_type_internal_serdes = 3, 303 e1000_num_media_types 304 }; 305 306 enum e1000_nvm_type { 307 e1000_nvm_unknown = 0, 308 e1000_nvm_none, 309 e1000_nvm_eeprom_spi, 310 e1000_nvm_eeprom_microwire, 311 e1000_nvm_flash_hw, 312 e1000_nvm_invm, 313 e1000_nvm_flash_sw 314 }; 315 316 enum e1000_nvm_override { 317 e1000_nvm_override_none = 0, 318 e1000_nvm_override_spi_small, 319 e1000_nvm_override_spi_large, 320 e1000_nvm_override_microwire_small, 321 e1000_nvm_override_microwire_large 322 }; 323 324 enum e1000_phy_type { 325 e1000_phy_unknown = 0, 326 e1000_phy_none, 327 e1000_phy_m88, 328 e1000_phy_igp, 329 e1000_phy_igp_2, 330 e1000_phy_gg82563, 331 e1000_phy_igp_3, 332 e1000_phy_ife, 333 e1000_phy_bm, 334 e1000_phy_82578, 335 e1000_phy_82577, 336 e1000_phy_82579, 337 e1000_phy_i217, 338 e1000_phy_82580, 339 e1000_phy_vf, 340 e1000_phy_i210, 341 }; 342 343 enum e1000_bus_type { 344 e1000_bus_type_unknown = 0, 345 e1000_bus_type_pci, 346 e1000_bus_type_pcix, 347 e1000_bus_type_pci_express, 348 e1000_bus_type_reserved 349 }; 350 351 enum e1000_bus_speed { 352 e1000_bus_speed_unknown = 0, 353 e1000_bus_speed_33, 354 e1000_bus_speed_66, 355 e1000_bus_speed_100, 356 e1000_bus_speed_120, 357 e1000_bus_speed_133, 358 e1000_bus_speed_2500, 359 e1000_bus_speed_5000, 360 e1000_bus_speed_reserved 361 }; 362 363 enum e1000_bus_width { 364 e1000_bus_width_unknown = 0, 365 e1000_bus_width_pcie_x1, 366 e1000_bus_width_pcie_x2, 367 e1000_bus_width_pcie_x4 = 4, 368 e1000_bus_width_pcie_x8 = 8, 369 e1000_bus_width_32, 370 e1000_bus_width_64, 371 e1000_bus_width_reserved 372 }; 373 374 enum e1000_1000t_rx_status { 375 e1000_1000t_rx_status_not_ok = 0, 376 e1000_1000t_rx_status_ok, 377 e1000_1000t_rx_status_undefined = 0xFF 378 }; 379 380 enum e1000_rev_polarity { 381 e1000_rev_polarity_normal = 0, 382 e1000_rev_polarity_reversed, 383 e1000_rev_polarity_undefined = 0xFF 384 }; 385 386 enum e1000_fc_mode { 387 e1000_fc_none = 0, 388 e1000_fc_rx_pause, 389 e1000_fc_tx_pause, 390 e1000_fc_full, 391 e1000_fc_default = 0xFF 392 }; 393 394 enum e1000_ffe_config { 395 e1000_ffe_config_enabled = 0, 396 e1000_ffe_config_active, 397 e1000_ffe_config_blocked 398 }; 399 400 enum e1000_dsp_config { 401 e1000_dsp_config_disabled = 0, 402 e1000_dsp_config_enabled, 403 e1000_dsp_config_activated, 404 e1000_dsp_config_undefined = 0xFF 405 }; 406 407 enum e1000_ms_type { 408 e1000_ms_hw_default = 0, 409 e1000_ms_force_master, 410 e1000_ms_force_slave, 411 e1000_ms_auto 412 }; 413 414 enum e1000_smart_speed { 415 e1000_smart_speed_default = 0, 416 e1000_smart_speed_on, 417 e1000_smart_speed_off 418 }; 419 420 enum e1000_serdes_link_state { 421 e1000_serdes_link_down = 0, 422 e1000_serdes_link_autoneg_progress, 423 e1000_serdes_link_autoneg_complete, 424 e1000_serdes_link_forced_up 425 }; 426 427 #define __le16 u16 428 #define __le32 u32 429 #define __le64 u64 430 /* Receive Descriptor */ 431 struct e1000_rx_desc { 432 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 433 __le16 length; /* Length of data DMAed into data buffer */ 434 __le16 csum; /* Packet checksum */ 435 u8 status; /* Descriptor status */ 436 u8 errors; /* Descriptor Errors */ 437 __le16 special; 438 }; 439 440 /* Receive Descriptor - Extended */ 441 union e1000_rx_desc_extended { 442 struct { 443 __le64 buffer_addr; 444 __le64 reserved; 445 } read; 446 struct { 447 struct { 448 __le32 mrq; /* Multiple Rx Queues */ 449 union { 450 __le32 rss; /* RSS Hash */ 451 struct { 452 __le16 ip_id; /* IP id */ 453 __le16 csum; /* Packet Checksum */ 454 } csum_ip; 455 } hi_dword; 456 } lower; 457 struct { 458 __le32 status_error; /* ext status/error */ 459 __le16 length; 460 __le16 vlan; /* VLAN tag */ 461 } upper; 462 } wb; /* writeback */ 463 }; 464 465 #define MAX_PS_BUFFERS 4 466 467 /* Number of packet split data buffers (not including the header buffer) */ 468 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 469 470 /* Receive Descriptor - Packet Split */ 471 union e1000_rx_desc_packet_split { 472 struct { 473 /* one buffer for protocol header(s), three data buffers */ 474 __le64 buffer_addr[MAX_PS_BUFFERS]; 475 } read; 476 struct { 477 struct { 478 __le32 mrq; /* Multiple Rx Queues */ 479 union { 480 __le32 rss; /* RSS Hash */ 481 struct { 482 __le16 ip_id; /* IP id */ 483 __le16 csum; /* Packet Checksum */ 484 } csum_ip; 485 } hi_dword; 486 } lower; 487 struct { 488 __le32 status_error; /* ext status/error */ 489 __le16 length0; /* length of buffer 0 */ 490 __le16 vlan; /* VLAN tag */ 491 } middle; 492 struct { 493 __le16 header_status; 494 /* length of buffers 1-3 */ 495 __le16 length[PS_PAGE_BUFFERS]; 496 } upper; 497 __le64 reserved; 498 } wb; /* writeback */ 499 }; 500 501 /* Transmit Descriptor */ 502 struct e1000_tx_desc { 503 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 504 union { 505 __le32 data; 506 struct { 507 __le16 length; /* Data buffer length */ 508 u8 cso; /* Checksum offset */ 509 u8 cmd; /* Descriptor control */ 510 } flags; 511 } lower; 512 union { 513 __le32 data; 514 struct { 515 u8 status; /* Descriptor status */ 516 u8 css; /* Checksum start */ 517 __le16 special; 518 } fields; 519 } upper; 520 }; 521 522 /* Offload Context Descriptor */ 523 struct e1000_context_desc { 524 union { 525 __le32 ip_config; 526 struct { 527 u8 ipcss; /* IP checksum start */ 528 u8 ipcso; /* IP checksum offset */ 529 __le16 ipcse; /* IP checksum end */ 530 } ip_fields; 531 } lower_setup; 532 union { 533 __le32 tcp_config; 534 struct { 535 u8 tucss; /* TCP checksum start */ 536 u8 tucso; /* TCP checksum offset */ 537 __le16 tucse; /* TCP checksum end */ 538 } tcp_fields; 539 } upper_setup; 540 __le32 cmd_and_length; 541 union { 542 __le32 data; 543 struct { 544 u8 status; /* Descriptor status */ 545 u8 hdr_len; /* Header length */ 546 __le16 mss; /* Maximum segment size */ 547 } fields; 548 } tcp_seg_setup; 549 }; 550 551 /* Offload data descriptor */ 552 struct e1000_data_desc { 553 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 554 union { 555 __le32 data; 556 struct { 557 __le16 length; /* Data buffer length */ 558 u8 typ_len_ext; 559 u8 cmd; 560 } flags; 561 } lower; 562 union { 563 __le32 data; 564 struct { 565 u8 status; /* Descriptor status */ 566 u8 popts; /* Packet Options */ 567 __le16 special; 568 } fields; 569 } upper; 570 }; 571 572 /* Statistics counters collected by the MAC */ 573 struct e1000_hw_stats { 574 u64 crcerrs; 575 u64 algnerrc; 576 u64 symerrs; 577 u64 rxerrc; 578 u64 mpc; 579 u64 scc; 580 u64 ecol; 581 u64 mcc; 582 u64 latecol; 583 u64 colc; 584 u64 dc; 585 u64 tncrs; 586 u64 sec; 587 u64 cexterr; 588 u64 rlec; 589 u64 xonrxc; 590 u64 xontxc; 591 u64 xoffrxc; 592 u64 xofftxc; 593 u64 fcruc; 594 u64 prc64; 595 u64 prc127; 596 u64 prc255; 597 u64 prc511; 598 u64 prc1023; 599 u64 prc1522; 600 u64 gprc; 601 u64 bprc; 602 u64 mprc; 603 u64 gptc; 604 u64 gorc; 605 u64 gotc; 606 u64 rnbc; 607 u64 ruc; 608 u64 rfc; 609 u64 roc; 610 u64 rjc; 611 u64 mgprc; 612 u64 mgpdc; 613 u64 mgptc; 614 u64 tor; 615 u64 tot; 616 u64 tpr; 617 u64 tpt; 618 u64 ptc64; 619 u64 ptc127; 620 u64 ptc255; 621 u64 ptc511; 622 u64 ptc1023; 623 u64 ptc1522; 624 u64 mptc; 625 u64 bptc; 626 u64 tsctc; 627 u64 tsctfc; 628 u64 iac; 629 u64 icrxptc; 630 u64 icrxatc; 631 u64 ictxptc; 632 u64 ictxatc; 633 u64 ictxqec; 634 u64 ictxqmtc; 635 u64 icrxdmtc; 636 u64 icrxoc; 637 u64 cbtmpc; 638 u64 htdpmc; 639 u64 cbrdpc; 640 u64 cbrmpc; 641 u64 rpthc; 642 u64 hgptc; 643 u64 htcbdpc; 644 u64 hgorc; 645 u64 hgotc; 646 u64 lenerrs; 647 u64 scvpc; 648 u64 hrmpc; 649 u64 doosync; 650 u64 o2bgptc; 651 u64 o2bspc; 652 u64 b2ospc; 653 u64 b2ogprc; 654 }; 655 656 struct e1000_vf_stats { 657 u64 base_gprc; 658 u64 base_gptc; 659 u64 base_gorc; 660 u64 base_gotc; 661 u64 base_mprc; 662 u64 base_gotlbc; 663 u64 base_gptlbc; 664 u64 base_gorlbc; 665 u64 base_gprlbc; 666 667 u32 last_gprc; 668 u32 last_gptc; 669 u32 last_gorc; 670 u32 last_gotc; 671 u32 last_mprc; 672 u32 last_gotlbc; 673 u32 last_gptlbc; 674 u32 last_gorlbc; 675 u32 last_gprlbc; 676 677 u64 gprc; 678 u64 gptc; 679 u64 gorc; 680 u64 gotc; 681 u64 mprc; 682 u64 gotlbc; 683 u64 gptlbc; 684 u64 gorlbc; 685 u64 gprlbc; 686 }; 687 688 struct e1000_phy_stats { 689 u32 idle_errors; 690 u32 receive_errors; 691 }; 692 693 struct e1000_host_mng_dhcp_cookie { 694 u32 signature; 695 u8 status; 696 u8 reserved0; 697 u16 vlan_id; 698 u32 reserved1; 699 u16 reserved2; 700 u8 reserved3; 701 u8 checksum; 702 }; 703 704 /* Host Interface "Rev 1" */ 705 struct e1000_host_command_header { 706 u8 command_id; 707 u8 command_length; 708 u8 command_options; 709 u8 checksum; 710 }; 711 712 #define E1000_HI_MAX_DATA_LENGTH 252 713 struct e1000_host_command_info { 714 struct e1000_host_command_header command_header; 715 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 716 }; 717 718 /* Host Interface "Rev 2" */ 719 struct e1000_host_mng_command_header { 720 u8 command_id; 721 u8 checksum; 722 u16 reserved1; 723 u16 reserved2; 724 u16 command_length; 725 }; 726 727 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 728 struct e1000_host_mng_command_info { 729 struct e1000_host_mng_command_header command_header; 730 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 731 }; 732 733 #include "e1000_mac.h" 734 #include "e1000_phy.h" 735 #include "e1000_nvm.h" 736 #include "e1000_manage.h" 737 #include "e1000_mbx.h" 738 739 /* Function pointers for the MAC. */ 740 struct e1000_mac_operations { 741 s32 (*init_params)(struct e1000_hw *); 742 s32 (*id_led_init)(struct e1000_hw *); 743 s32 (*blink_led)(struct e1000_hw *); 744 bool (*check_mng_mode)(struct e1000_hw *); 745 s32 (*check_for_link)(struct e1000_hw *); 746 s32 (*cleanup_led)(struct e1000_hw *); 747 void (*clear_hw_cntrs)(struct e1000_hw *); 748 void (*clear_vfta)(struct e1000_hw *); 749 s32 (*get_bus_info)(struct e1000_hw *); 750 void (*set_lan_id)(struct e1000_hw *); 751 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 752 s32 (*led_on)(struct e1000_hw *); 753 s32 (*led_off)(struct e1000_hw *); 754 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 755 s32 (*reset_hw)(struct e1000_hw *); 756 s32 (*init_hw)(struct e1000_hw *); 757 void (*shutdown_serdes)(struct e1000_hw *); 758 void (*power_up_serdes)(struct e1000_hw *); 759 s32 (*setup_link)(struct e1000_hw *); 760 s32 (*setup_physical_interface)(struct e1000_hw *); 761 s32 (*setup_led)(struct e1000_hw *); 762 void (*write_vfta)(struct e1000_hw *, u32, u32); 763 void (*config_collision_dist)(struct e1000_hw *); 764 int (*rar_set)(struct e1000_hw *, u8*, u32); 765 s32 (*read_mac_addr)(struct e1000_hw *); 766 s32 (*validate_mdi_setting)(struct e1000_hw *); 767 s32 (*set_obff_timer)(struct e1000_hw *, u32); 768 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 769 void (*release_swfw_sync)(struct e1000_hw *, u16); 770 }; 771 772 /* When to use various PHY register access functions: 773 * 774 * Func Caller 775 * Function Does Does When to use 776 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 777 * X_reg L,P,A n/a for simple PHY reg accesses 778 * X_reg_locked P,A L for multiple accesses of different regs 779 * on different pages 780 * X_reg_page A L,P for multiple accesses of different regs 781 * on the same page 782 * 783 * Where X=[read|write], L=locking, P=sets page, A=register access 784 * 785 */ 786 struct e1000_phy_operations { 787 s32 (*init_params)(struct e1000_hw *); 788 s32 (*acquire)(struct e1000_hw *); 789 s32 (*cfg_on_link_up)(struct e1000_hw *); 790 s32 (*check_polarity)(struct e1000_hw *); 791 s32 (*check_reset_block)(struct e1000_hw *); 792 s32 (*commit)(struct e1000_hw *); 793 s32 (*force_speed_duplex)(struct e1000_hw *); 794 s32 (*get_cfg_done)(struct e1000_hw *hw); 795 s32 (*get_cable_length)(struct e1000_hw *); 796 s32 (*get_info)(struct e1000_hw *); 797 s32 (*set_page)(struct e1000_hw *, u16); 798 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 799 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 800 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 801 void (*release)(struct e1000_hw *); 802 s32 (*reset)(struct e1000_hw *); 803 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 804 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 805 s32 (*write_reg)(struct e1000_hw *, u32, u16); 806 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 807 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 808 void (*power_up)(struct e1000_hw *); 809 void (*power_down)(struct e1000_hw *); 810 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 811 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 812 }; 813 814 /* Function pointers for the NVM. */ 815 struct e1000_nvm_operations { 816 s32 (*init_params)(struct e1000_hw *); 817 s32 (*acquire)(struct e1000_hw *); 818 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 819 void (*release)(struct e1000_hw *); 820 void (*reload)(struct e1000_hw *); 821 s32 (*update)(struct e1000_hw *); 822 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 823 s32 (*validate)(struct e1000_hw *); 824 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 825 }; 826 827 struct e1000_mac_info { 828 struct e1000_mac_operations ops; 829 u8 addr[ETHER_ADDR_LEN]; 830 u8 perm_addr[ETHER_ADDR_LEN]; 831 832 enum e1000_mac_type type; 833 834 u32 collision_delta; 835 u32 ledctl_default; 836 u32 ledctl_mode1; 837 u32 ledctl_mode2; 838 u32 mc_filter_type; 839 u32 tx_packet_delta; 840 u32 txcw; 841 842 u16 current_ifs_val; 843 u16 ifs_max_val; 844 u16 ifs_min_val; 845 u16 ifs_ratio; 846 u16 ifs_step_size; 847 u16 mta_reg_count; 848 u16 uta_reg_count; 849 850 /* Maximum size of the MTA register table in all supported adapters */ 851 #define MAX_MTA_REG 128 852 u32 mta_shadow[MAX_MTA_REG]; 853 u16 rar_entry_count; 854 855 u8 forced_speed_duplex; 856 857 bool adaptive_ifs; 858 bool has_fwsm; 859 bool arc_subsystem_valid; 860 bool asf_firmware_present; 861 bool autoneg; 862 bool autoneg_failed; 863 bool get_link_status; 864 bool in_ifs_mode; 865 bool report_tx_early; 866 enum e1000_serdes_link_state serdes_link_state; 867 bool serdes_has_link; 868 bool tx_pkt_filtering; 869 u32 max_frame_size; 870 }; 871 872 struct e1000_phy_info { 873 struct e1000_phy_operations ops; 874 enum e1000_phy_type type; 875 876 enum e1000_1000t_rx_status local_rx; 877 enum e1000_1000t_rx_status remote_rx; 878 enum e1000_ms_type ms_type; 879 enum e1000_ms_type original_ms_type; 880 enum e1000_rev_polarity cable_polarity; 881 enum e1000_smart_speed smart_speed; 882 883 u32 addr; 884 u32 id; 885 u32 reset_delay_us; /* in usec */ 886 u32 revision; 887 888 enum e1000_media_type media_type; 889 890 u16 autoneg_advertised; 891 u16 autoneg_mask; 892 u16 cable_length; 893 u16 max_cable_length; 894 u16 min_cable_length; 895 896 u8 mdix; 897 898 bool disable_polarity_correction; 899 bool is_mdix; 900 bool polarity_correction; 901 bool speed_downgraded; 902 bool autoneg_wait_to_complete; 903 }; 904 905 struct e1000_nvm_info { 906 struct e1000_nvm_operations ops; 907 enum e1000_nvm_type type; 908 enum e1000_nvm_override override; 909 910 u32 flash_bank_size; 911 u32 flash_base_addr; 912 913 u16 word_size; 914 u16 delay_usec; 915 u16 address_bits; 916 u16 opcode_bits; 917 u16 page_size; 918 }; 919 920 struct e1000_bus_info { 921 enum e1000_bus_type type; 922 enum e1000_bus_speed speed; 923 enum e1000_bus_width width; 924 925 u16 func; 926 u16 pci_cmd_word; 927 }; 928 929 struct e1000_fc_info { 930 u32 high_water; /* Flow control high-water mark */ 931 u32 low_water; /* Flow control low-water mark */ 932 u16 pause_time; /* Flow control pause timer */ 933 u16 refresh_time; /* Flow control refresh timer */ 934 bool send_xon; /* Flow control send XON */ 935 bool strict_ieee; /* Strict IEEE mode */ 936 enum e1000_fc_mode current_mode; /* FC mode in effect */ 937 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 938 }; 939 940 struct e1000_mbx_operations { 941 s32 (*init_params)(struct e1000_hw *hw); 942 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 943 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 944 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 945 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 946 s32 (*check_for_msg)(struct e1000_hw *, u16); 947 s32 (*check_for_ack)(struct e1000_hw *, u16); 948 s32 (*check_for_rst)(struct e1000_hw *, u16); 949 }; 950 951 struct e1000_mbx_stats { 952 u32 msgs_tx; 953 u32 msgs_rx; 954 955 u32 acks; 956 u32 reqs; 957 u32 rsts; 958 }; 959 960 struct e1000_mbx_info { 961 struct e1000_mbx_operations ops; 962 struct e1000_mbx_stats stats; 963 u32 timeout; 964 u32 usec_delay; 965 u16 size; 966 }; 967 968 struct e1000_dev_spec_82541 { 969 enum e1000_dsp_config dsp_config; 970 enum e1000_ffe_config ffe_config; 971 u16 spd_default; 972 bool phy_init_script; 973 }; 974 975 struct e1000_dev_spec_82542 { 976 bool dma_fairness; 977 }; 978 979 struct e1000_dev_spec_82543 { 980 u32 tbi_compatibility; 981 bool dma_fairness; 982 bool init_phy_disabled; 983 }; 984 985 struct e1000_dev_spec_82571 { 986 bool laa_is_present; 987 u32 smb_counter; 988 }; 989 990 struct e1000_dev_spec_80003es2lan { 991 bool mdic_wa_enable; 992 }; 993 994 struct e1000_shadow_ram { 995 u16 value; 996 bool modified; 997 }; 998 999 #define E1000_SHADOW_RAM_WORDS 2048 1000 1001 /* I218 PHY Ultra Low Power (ULP) states */ 1002 enum e1000_ulp_state { 1003 e1000_ulp_state_unknown, 1004 e1000_ulp_state_off, 1005 e1000_ulp_state_on, 1006 }; 1007 1008 struct e1000_dev_spec_ich8lan { 1009 bool kmrn_lock_loss_workaround_enabled; 1010 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 1011 bool nvm_k1_enabled; 1012 bool disable_k1_off; 1013 bool eee_disable; 1014 u16 eee_lp_ability; 1015 enum e1000_ulp_state ulp_state; 1016 bool ulp_capability_disabled; 1017 bool during_suspend_flow; 1018 bool smbus_disable; 1019 }; 1020 1021 struct e1000_dev_spec_82575 { 1022 bool sgmii_active; 1023 bool global_device_reset; 1024 bool eee_disable; 1025 bool module_plugged; 1026 bool clear_semaphore_once; 1027 u32 mtu; 1028 struct sfp_e1000_flags eth_flags; 1029 u8 media_port; 1030 bool media_changed; 1031 }; 1032 1033 struct e1000_dev_spec_vf { 1034 u32 vf_number; 1035 u32 v2p_mailbox; 1036 }; 1037 1038 struct e1000_hw { 1039 void *back; 1040 1041 u8 *hw_addr; 1042 u8 *flash_address; 1043 unsigned long io_base; 1044 1045 struct e1000_mac_info mac; 1046 struct e1000_fc_info fc; 1047 struct e1000_phy_info phy; 1048 struct e1000_nvm_info nvm; 1049 struct e1000_bus_info bus; 1050 struct e1000_mbx_info mbx; 1051 struct e1000_host_mng_dhcp_cookie mng_cookie; 1052 1053 union { 1054 struct e1000_dev_spec_82541 _82541; 1055 struct e1000_dev_spec_82542 _82542; 1056 struct e1000_dev_spec_82543 _82543; 1057 struct e1000_dev_spec_82571 _82571; 1058 struct e1000_dev_spec_80003es2lan _80003es2lan; 1059 struct e1000_dev_spec_ich8lan ich8lan; 1060 struct e1000_dev_spec_82575 _82575; 1061 struct e1000_dev_spec_vf vf; 1062 } dev_spec; 1063 1064 u16 device_id; 1065 u16 subsystem_vendor_id; 1066 u16 subsystem_device_id; 1067 u16 vendor_id; 1068 1069 u8 revision_id; 1070 }; 1071 1072 #include "e1000_82541.h" 1073 #include "e1000_82543.h" 1074 #include "e1000_82571.h" 1075 #include "e1000_80003es2lan.h" 1076 #include "e1000_ich8lan.h" 1077 #include "e1000_82575.h" 1078 #include "e1000_i210.h" 1079 #include "e1000_base.h" 1080 1081 /* These functions must be implemented by drivers */ 1082 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1083 void e1000_pci_set_mwi(struct e1000_hw *hw); 1084 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1085 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1086 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1087 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1088 1089 #endif 1090