1 /*- 2 * Copyright (c) 2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #ifdef DEV_NETMAP 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/lock.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/selinfo.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <machine/bus.h> 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/if_media.h> 48 #include <net/if_var.h> 49 #include <net/if_clone.h> 50 #include <net/if_types.h> 51 #include <net/netmap.h> 52 #include <dev/netmap/netmap_kern.h> 53 54 #include "common/common.h" 55 #include "common/t4_regs.h" 56 #include "common/t4_regs_values.h" 57 58 extern int fl_pad; /* XXXNM */ 59 60 /* 61 * 0 = normal netmap rx 62 * 1 = black hole 63 * 2 = supermassive black hole (buffer packing enabled) 64 */ 65 int black_hole = 0; 66 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RDTUN, &black_hole, 0, 67 "Sink incoming packets."); 68 69 int rx_ndesc = 256; 70 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN, 71 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated."); 72 73 int rx_nframes = 64; 74 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_nframes, CTLFLAG_RWTUN, 75 &rx_nframes, 0, "max # of frames received before waking up netmap rx."); 76 77 int holdoff_tmr_idx = 2; 78 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN, 79 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues."); 80 81 /* 82 * Congestion drops. 83 * -1: no congestion feedback (not recommended). 84 * 0: backpressure the channel instead of dropping packets right away. 85 * 1: no backpressure, drop packets for the congested queue immediately. 86 */ 87 static int nm_cong_drop = 1; 88 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_cong_drop, CTLFLAG_RDTUN, 89 &nm_cong_drop, 0, 90 "Congestion control for netmap rx queues (0 = backpressure, 1 = drop"); 91 92 int starve_fl = 0; 93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, starve_fl, CTLFLAG_RWTUN, 94 &starve_fl, 0, "Don't ring fl db for netmap rx queues."); 95 96 /* 97 * Try to process tx credits in bulk. This may cause a delay in the return of 98 * tx credits and is suitable for bursty or non-stop tx only. 99 */ 100 int lazy_tx_credit_flush = 1; 101 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lazy_tx_credit_flush, CTLFLAG_RWTUN, 102 &lazy_tx_credit_flush, 0, "lazy credit flush for netmap tx queues."); 103 104 /* 105 * Split the netmap rx queues into two groups that populate separate halves of 106 * the RSS indirection table. This allows filters with hashmask to steer to a 107 * particular group of queues. 108 */ 109 static int nm_split_rss = 0; 110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_split_rss, CTLFLAG_RWTUN, 111 &nm_split_rss, 0, "Split the netmap rx queues into two groups."); 112 113 static int 114 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong) 115 { 116 int rc, cntxt_id, i; 117 __be32 v; 118 struct adapter *sc = vi->pi->adapter; 119 struct sge_params *sp = &sc->params.sge; 120 struct netmap_adapter *na = NA(vi->ifp); 121 struct fw_iq_cmd c; 122 123 MPASS(na != NULL); 124 MPASS(nm_rxq->iq_desc != NULL); 125 MPASS(nm_rxq->fl_desc != NULL); 126 127 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE); 128 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len); 129 130 bzero(&c, sizeof(c)); 131 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 132 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 133 V_FW_IQ_CMD_VFN(0)); 134 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 135 FW_LEN16(c)); 136 MPASS(!forwarding_intr_to_fwq(sc)); 137 KASSERT(nm_rxq->intr_idx < sc->intr_count, 138 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx)); 139 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx); 140 c.type_to_iqandstindex = htobe32(v | 141 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 142 V_FW_IQ_CMD_VIID(vi->viid) | 143 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 144 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) | 145 F_FW_IQ_CMD_IQGTSMODE | 146 V_FW_IQ_CMD_IQINTCNTTHRESH(0) | 147 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 148 c.iqsize = htobe16(vi->qsize_rxq); 149 c.iqaddr = htobe64(nm_rxq->iq_ba); 150 if (cong >= 0) { 151 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN | 152 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF | 153 F_FW_IQ_CMD_FL0CONGEN); 154 } 155 c.iqns_to_fl0congen |= 156 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 157 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 158 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 159 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0)); 160 c.fl0dcaen_to_fl0cidxfthresh = 161 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 162 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 163 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 164 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 165 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE); 166 c.fl0addr = htobe64(nm_rxq->fl_ba); 167 168 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 169 if (rc != 0) { 170 device_printf(sc->dev, 171 "failed to create netmap ingress queue: %d\n", rc); 172 return (rc); 173 } 174 175 nm_rxq->iq_cidx = 0; 176 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE); 177 nm_rxq->iq_gen = F_RSPD_GEN; 178 nm_rxq->iq_cntxt_id = be16toh(c.iqid); 179 nm_rxq->iq_abs_id = be16toh(c.physiqid); 180 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start; 181 if (cntxt_id >= sc->sge.niq) { 182 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)", 183 __func__, cntxt_id, sc->sge.niq - 1); 184 } 185 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq; 186 187 nm_rxq->fl_cntxt_id = be16toh(c.fl0id); 188 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 189 MPASS(nm_rxq->fl_sidx == na->num_rx_desc); 190 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start; 191 if (cntxt_id >= sc->sge.neq) { 192 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)", 193 __func__, cntxt_id, sc->sge.neq - 1); 194 } 195 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq; 196 197 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) | 198 sc->chip_params->sge_fl_db; 199 200 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) { 201 uint32_t param, val; 202 203 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 204 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 205 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 206 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 207 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 208 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 209 if (cong == 0) 210 val = 1 << 19; 211 else { 212 val = 2 << 19; 213 for (i = 0; i < 4; i++) { 214 if (cong & (1 << i)) 215 val |= 1 << (i << 2); 216 } 217 } 218 219 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 220 if (rc != 0) { 221 /* report error but carry on */ 222 device_printf(sc->dev, 223 "failed to set congestion manager context for " 224 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc); 225 } 226 } 227 228 t4_write_reg(sc, sc->sge_gts_reg, 229 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 230 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 231 232 return (rc); 233 } 234 235 static int 236 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 237 { 238 struct adapter *sc = vi->pi->adapter; 239 int rc; 240 241 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 242 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff); 243 if (rc != 0) 244 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n", 245 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc); 246 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 247 return (rc); 248 } 249 250 static int 251 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 252 { 253 int rc, cntxt_id; 254 size_t len; 255 struct adapter *sc = vi->pi->adapter; 256 struct netmap_adapter *na = NA(vi->ifp); 257 struct fw_eq_eth_cmd c; 258 259 MPASS(na != NULL); 260 MPASS(nm_txq->desc != NULL); 261 262 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 263 bzero(nm_txq->desc, len); 264 265 bzero(&c, sizeof(c)); 266 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 267 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 268 V_FW_EQ_ETH_CMD_VFN(0)); 269 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 270 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 271 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 272 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 273 c.fetchszm_to_iqid = 274 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 275 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 276 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id)); 277 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 278 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 279 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE)); 280 c.eqaddr = htobe64(nm_txq->ba); 281 282 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 283 if (rc != 0) { 284 device_printf(vi->dev, 285 "failed to create netmap egress queue: %d\n", rc); 286 return (rc); 287 } 288 289 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 290 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start; 291 if (cntxt_id >= sc->sge.neq) 292 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__, 293 cntxt_id, sc->sge.neq - 1); 294 sc->sge.eqmap[cntxt_id] = (void *)nm_txq; 295 296 nm_txq->pidx = nm_txq->cidx = 0; 297 MPASS(nm_txq->sidx == na->num_tx_desc); 298 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0; 299 300 nm_txq->doorbells = sc->doorbells; 301 if (isset(&nm_txq->doorbells, DOORBELL_UDB) || 302 isset(&nm_txq->doorbells, DOORBELL_UDBWC) || 303 isset(&nm_txq->doorbells, DOORBELL_WCWR)) { 304 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 305 uint32_t mask = (1 << s_qpp) - 1; 306 volatile uint8_t *udb; 307 308 udb = sc->udbs_base + UDBS_DB_OFFSET; 309 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT; 310 nm_txq->udb_qid = nm_txq->cntxt_id & mask; 311 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 312 clrbit(&nm_txq->doorbells, DOORBELL_WCWR); 313 else { 314 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT; 315 nm_txq->udb_qid = 0; 316 } 317 nm_txq->udb = (volatile void *)udb; 318 } 319 320 return (rc); 321 } 322 323 static int 324 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 325 { 326 struct adapter *sc = vi->pi->adapter; 327 int rc; 328 329 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id); 330 if (rc != 0) 331 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__, 332 nm_txq->cntxt_id, rc); 333 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 334 return (rc); 335 } 336 337 static int 338 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 339 struct netmap_adapter *na) 340 { 341 struct netmap_slot *slot; 342 struct netmap_kring *kring; 343 struct sge_nm_rxq *nm_rxq; 344 struct sge_nm_txq *nm_txq; 345 int rc, i, j, hwidx, defq, nrssq; 346 struct hw_buf_info *hwb; 347 348 ASSERT_SYNCHRONIZED_OP(sc); 349 350 if ((vi->flags & VI_INIT_DONE) == 0 || 351 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 352 return (EAGAIN); 353 354 hwb = &sc->sge.hw_buf_info[0]; 355 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 356 if (hwb->size == NETMAP_BUF_SIZE(na)) 357 break; 358 } 359 if (i >= SGE_FLBUF_SIZES) { 360 if_printf(ifp, "no hwidx for netmap buffer size %d.\n", 361 NETMAP_BUF_SIZE(na)); 362 return (ENXIO); 363 } 364 hwidx = i; 365 366 /* Must set caps before calling netmap_reset */ 367 nm_set_native_flags(na); 368 369 for_each_nm_rxq(vi, i, nm_rxq) { 370 kring = na->rx_rings[nm_rxq->nid]; 371 if (!nm_kring_pending_on(kring) || 372 nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID) 373 continue; 374 375 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop)); 376 nm_rxq->fl_hwidx = hwidx; 377 slot = netmap_reset(na, NR_RX, i, 0); 378 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 379 380 /* We deal with 8 bufs at a time */ 381 MPASS((na->num_rx_desc & 7) == 0); 382 MPASS(na->num_rx_desc == nm_rxq->fl_sidx); 383 for (j = 0; j < nm_rxq->fl_sidx; j++) { 384 uint64_t ba; 385 386 PNMB(na, &slot[j], &ba); 387 MPASS(ba != 0); 388 nm_rxq->fl_desc[j] = htobe64(ba | hwidx); 389 } 390 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8; 391 MPASS((j & 7) == 0); 392 j /= 8; /* driver pidx to hardware pidx */ 393 wmb(); 394 t4_write_reg(sc, sc->sge_kdoorbell_reg, 395 nm_rxq->fl_db_val | V_PIDX(j)); 396 397 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON); 398 } 399 400 for_each_nm_txq(vi, i, nm_txq) { 401 kring = na->tx_rings[nm_txq->nid]; 402 if (!nm_kring_pending_on(kring) || 403 nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID) 404 continue; 405 406 alloc_nm_txq_hwq(vi, nm_txq); 407 slot = netmap_reset(na, NR_TX, i, 0); 408 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 409 } 410 411 if (vi->nm_rss == NULL) { 412 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE, 413 M_ZERO | M_WAITOK); 414 } 415 416 MPASS(vi->nnmrxq > 0); 417 if (nm_split_rss == 0 || vi->nnmrxq == 1) { 418 for (i = 0; i < vi->rss_size;) { 419 for_each_nm_rxq(vi, j, nm_rxq) { 420 vi->nm_rss[i++] = nm_rxq->iq_abs_id; 421 if (i == vi->rss_size) 422 break; 423 } 424 } 425 defq = vi->nm_rss[0]; 426 } else { 427 /* We have multiple queues and we want to split the table. */ 428 MPASS(nm_split_rss != 0); 429 MPASS(vi->nnmrxq > 1); 430 431 nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq]; 432 nrssq = vi->nnmrxq; 433 if (vi->nnmrxq & 1) { 434 /* 435 * Odd number of queues. The first rxq is designated the 436 * default queue, the rest are split evenly. 437 */ 438 defq = nm_rxq->iq_abs_id; 439 nm_rxq++; 440 nrssq--; 441 } else { 442 /* 443 * Even number of queues split into two halves. The 444 * first rxq in one of the halves is designated the 445 * default queue. 446 */ 447 #if 1 448 /* First rxq in the first half. */ 449 defq = nm_rxq->iq_abs_id; 450 #else 451 /* First rxq in the second half. */ 452 defq = nm_rxq[vi->nnmrxq / 2].iq_abs_id; 453 #endif 454 } 455 456 i = 0; 457 while (i < vi->rss_size / 2) { 458 for (j = 0; j < nrssq / 2; j++) { 459 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 460 if (i == vi->rss_size / 2) 461 break; 462 } 463 } 464 while (i < vi->rss_size) { 465 for (j = nrssq / 2; j < nrssq; j++) { 466 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 467 if (i == vi->rss_size) 468 break; 469 } 470 } 471 } 472 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 473 vi->nm_rss, vi->rss_size); 474 if (rc != 0) 475 if_printf(ifp, "netmap rss_config failed: %d\n", rc); 476 477 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0); 478 if (rc != 0) 479 if_printf(ifp, "netmap rss hash/defaultq config failed: %d\n", rc); 480 481 return (rc); 482 } 483 484 static int 485 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 486 struct netmap_adapter *na) 487 { 488 struct netmap_kring *kring; 489 int rc, i; 490 struct sge_nm_txq *nm_txq; 491 struct sge_nm_rxq *nm_rxq; 492 493 ASSERT_SYNCHRONIZED_OP(sc); 494 495 if (!nm_netmap_on(na)) 496 return (0); 497 498 if ((vi->flags & VI_INIT_DONE) == 0) 499 return (0); 500 501 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 502 vi->rss, vi->rss_size); 503 if (rc != 0) 504 if_printf(ifp, "failed to restore RSS config: %d\n", rc); 505 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 0, 0); 506 if (rc != 0) 507 if_printf(ifp, "failed to restore RSS hash/defaultq: %d\n", rc); 508 nm_clear_native_flags(na); 509 510 for_each_nm_txq(vi, i, nm_txq) { 511 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 512 513 kring = na->tx_rings[nm_txq->nid]; 514 if (!nm_kring_pending_off(kring) || 515 nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID) 516 continue; 517 518 /* Wait for hw pidx to catch up ... */ 519 while (be16toh(nm_txq->pidx) != spg->pidx) 520 pause("nmpidx", 1); 521 522 /* ... and then for the cidx. */ 523 while (spg->pidx != spg->cidx) 524 pause("nmcidx", 1); 525 526 free_nm_txq_hwq(vi, nm_txq); 527 } 528 for_each_nm_rxq(vi, i, nm_rxq) { 529 kring = na->rx_rings[nm_rxq->nid]; 530 if (!nm_kring_pending_off(kring) || 531 nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID) 532 continue; 533 534 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF)) 535 pause("nmst", 1); 536 537 free_nm_rxq_hwq(vi, nm_rxq); 538 } 539 540 return (rc); 541 } 542 543 static int 544 cxgbe_netmap_reg(struct netmap_adapter *na, int on) 545 { 546 struct ifnet *ifp = na->ifp; 547 struct vi_info *vi = ifp->if_softc; 548 struct adapter *sc = vi->pi->adapter; 549 int rc; 550 551 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg"); 552 if (rc != 0) 553 return (rc); 554 if (on) 555 rc = cxgbe_netmap_on(sc, vi, ifp, na); 556 else 557 rc = cxgbe_netmap_off(sc, vi, ifp, na); 558 end_synchronized_op(sc, 0); 559 560 return (rc); 561 } 562 563 /* How many packets can a single type1 WR carry in n descriptors */ 564 static inline int 565 ndesc_to_npkt(const int n) 566 { 567 568 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC); 569 570 return (n * 2 - 1); 571 } 572 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC)) 573 574 /* Space (in descriptors) needed for a type1 WR that carries n packets */ 575 static inline int 576 npkt_to_ndesc(const int n) 577 { 578 579 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 580 581 return ((n + 2) / 2); 582 } 583 584 /* Space (in 16B units) needed for a type1 WR that carries n packets */ 585 static inline int 586 npkt_to_len16(const int n) 587 { 588 589 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 590 591 return (n * 2 + 1); 592 } 593 594 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx) 595 596 static void 597 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq) 598 { 599 int n; 600 u_int db = nm_txq->doorbells; 601 602 MPASS(nm_txq->pidx != nm_txq->dbidx); 603 604 n = NMIDXDIFF(nm_txq, dbidx); 605 if (n > 1) 606 clrbit(&db, DOORBELL_WCWR); 607 wmb(); 608 609 switch (ffs(db) - 1) { 610 case DOORBELL_UDB: 611 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 612 break; 613 614 case DOORBELL_WCWR: { 615 volatile uint64_t *dst, *src; 616 617 /* 618 * Queues whose 128B doorbell segment fits in the page do not 619 * use relative qid (udb_qid is always 0). Only queues with 620 * doorbell segments can do WCWR. 621 */ 622 KASSERT(nm_txq->udb_qid == 0 && n == 1, 623 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p", 624 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq)); 625 626 dst = (volatile void *)((uintptr_t)nm_txq->udb + 627 UDBS_WR_OFFSET - UDBS_DB_OFFSET); 628 src = (void *)&nm_txq->desc[nm_txq->dbidx]; 629 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1]) 630 *dst++ = *src++; 631 wmb(); 632 break; 633 } 634 635 case DOORBELL_UDBWC: 636 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 637 wmb(); 638 break; 639 640 case DOORBELL_KDB: 641 t4_write_reg(sc, sc->sge_kdoorbell_reg, 642 V_QID(nm_txq->cntxt_id) | V_PIDX(n)); 643 break; 644 } 645 nm_txq->dbidx = nm_txq->pidx; 646 } 647 648 /* 649 * Write work requests to send 'npkt' frames and ring the doorbell to send them 650 * on their way. No need to check for wraparound. 651 */ 652 static void 653 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq, 654 struct netmap_kring *kring, int npkt, int npkt_remaining, int txcsum) 655 { 656 struct netmap_ring *ring = kring->ring; 657 struct netmap_slot *slot; 658 const u_int lim = kring->nkr_num_slots - 1; 659 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx]; 660 uint16_t len; 661 uint64_t ba; 662 struct cpl_tx_pkt_core *cpl; 663 struct ulptx_sgl *usgl; 664 int i, n; 665 666 while (npkt) { 667 n = min(npkt, MAX_NPKT_IN_TYPE1_WR); 668 len = 0; 669 670 wr = (void *)&nm_txq->desc[nm_txq->pidx]; 671 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 672 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n))); 673 wr->npkt = n; 674 wr->r3 = 0; 675 wr->type = 1; 676 cpl = (void *)(wr + 1); 677 678 for (i = 0; i < n; i++) { 679 slot = &ring->slot[kring->nr_hwcur]; 680 PNMB(kring->na, slot, &ba); 681 MPASS(ba != 0); 682 683 cpl->ctrl0 = nm_txq->cpl_ctrl0; 684 cpl->pack = 0; 685 cpl->len = htobe16(slot->len); 686 /* 687 * netmap(4) says "netmap does not use features such as 688 * checksum offloading, TCP segmentation offloading, 689 * encryption, VLAN encapsulation/decapsulation, etc." 690 * 691 * So the ncxl interfaces have tx hardware checksumming 692 * disabled by default. But you can override netmap by 693 * enabling IFCAP_TXCSUM on the interface manully. 694 */ 695 cpl->ctrl1 = txcsum ? 0 : 696 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 697 698 usgl = (void *)(cpl + 1); 699 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 700 V_ULPTX_NSGE(1)); 701 usgl->len0 = htobe32(slot->len); 702 usgl->addr0 = htobe64(ba); 703 704 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 705 cpl = (void *)(usgl + 1); 706 MPASS(slot->len + len <= UINT16_MAX); 707 len += slot->len; 708 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim); 709 } 710 wr->plen = htobe16(len); 711 712 npkt -= n; 713 nm_txq->pidx += npkt_to_ndesc(n); 714 MPASS(nm_txq->pidx <= nm_txq->sidx); 715 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) { 716 /* 717 * This routine doesn't know how to write WRs that wrap 718 * around. Make sure it wasn't asked to. 719 */ 720 MPASS(npkt == 0); 721 nm_txq->pidx = 0; 722 } 723 724 if (npkt == 0 && npkt_remaining == 0) { 725 /* All done. */ 726 if (lazy_tx_credit_flush == 0) { 727 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 728 F_FW_WR_EQUIQ); 729 nm_txq->equeqidx = nm_txq->pidx; 730 nm_txq->equiqidx = nm_txq->pidx; 731 } 732 ring_nm_txq_db(sc, nm_txq); 733 return; 734 } 735 736 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) { 737 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 738 F_FW_WR_EQUIQ); 739 nm_txq->equeqidx = nm_txq->pidx; 740 nm_txq->equiqidx = nm_txq->pidx; 741 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) { 742 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 743 nm_txq->equeqidx = nm_txq->pidx; 744 } 745 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC) 746 ring_nm_txq_db(sc, nm_txq); 747 } 748 749 /* Will get called again. */ 750 MPASS(npkt_remaining); 751 } 752 753 /* How many contiguous free descriptors starting at pidx */ 754 static inline int 755 contiguous_ndesc_available(struct sge_nm_txq *nm_txq) 756 { 757 758 if (nm_txq->cidx > nm_txq->pidx) 759 return (nm_txq->cidx - nm_txq->pidx - 1); 760 else if (nm_txq->cidx > 0) 761 return (nm_txq->sidx - nm_txq->pidx); 762 else 763 return (nm_txq->sidx - nm_txq->pidx - 1); 764 } 765 766 static int 767 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq) 768 { 769 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 770 uint16_t hw_cidx = spg->cidx; /* snapshot */ 771 struct fw_eth_tx_pkts_wr *wr; 772 int n = 0; 773 774 hw_cidx = be16toh(hw_cidx); 775 776 while (nm_txq->cidx != hw_cidx) { 777 wr = (void *)&nm_txq->desc[nm_txq->cidx]; 778 779 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR))); 780 MPASS(wr->type == 1); 781 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR); 782 783 n += wr->npkt; 784 nm_txq->cidx += npkt_to_ndesc(wr->npkt); 785 786 /* 787 * We never sent a WR that wrapped around so the credits coming 788 * back, WR by WR, should never cause the cidx to wrap around 789 * either. 790 */ 791 MPASS(nm_txq->cidx <= nm_txq->sidx); 792 if (__predict_false(nm_txq->cidx == nm_txq->sidx)) 793 nm_txq->cidx = 0; 794 } 795 796 return (n); 797 } 798 799 static int 800 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags) 801 { 802 struct netmap_adapter *na = kring->na; 803 struct ifnet *ifp = na->ifp; 804 struct vi_info *vi = ifp->if_softc; 805 struct adapter *sc = vi->pi->adapter; 806 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id]; 807 const u_int head = kring->rhead; 808 u_int reclaimed = 0; 809 int n, d, npkt_remaining, ndesc_remaining, txcsum; 810 811 /* 812 * Tx was at kring->nr_hwcur last time around and now we need to advance 813 * to kring->rhead. Note that the driver's pidx moves independent of 814 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation 815 * between descriptors and frames isn't 1:1). 816 */ 817 818 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 819 kring->nkr_num_slots - kring->nr_hwcur + head; 820 txcsum = ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6); 821 while (npkt_remaining) { 822 reclaimed += reclaim_nm_tx_desc(nm_txq); 823 ndesc_remaining = contiguous_ndesc_available(nm_txq); 824 /* Can't run out of descriptors with packets still remaining */ 825 MPASS(ndesc_remaining > 0); 826 827 /* # of desc needed to tx all remaining packets */ 828 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC; 829 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR) 830 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR); 831 832 if (d <= ndesc_remaining) 833 n = npkt_remaining; 834 else { 835 /* Can't send all, calculate how many can be sent */ 836 n = (ndesc_remaining / SGE_MAX_WR_NDESC) * 837 MAX_NPKT_IN_TYPE1_WR; 838 if (ndesc_remaining % SGE_MAX_WR_NDESC) 839 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC); 840 } 841 842 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */ 843 npkt_remaining -= n; 844 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining, txcsum); 845 } 846 MPASS(npkt_remaining == 0); 847 MPASS(kring->nr_hwcur == head); 848 MPASS(nm_txq->dbidx == nm_txq->pidx); 849 850 /* 851 * Second part: reclaim buffers for completed transmissions. 852 */ 853 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) { 854 reclaimed += reclaim_nm_tx_desc(nm_txq); 855 kring->nr_hwtail += reclaimed; 856 if (kring->nr_hwtail >= kring->nkr_num_slots) 857 kring->nr_hwtail -= kring->nkr_num_slots; 858 } 859 860 return (0); 861 } 862 863 static int 864 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags) 865 { 866 struct netmap_adapter *na = kring->na; 867 struct netmap_ring *ring = kring->ring; 868 struct ifnet *ifp = na->ifp; 869 struct vi_info *vi = ifp->if_softc; 870 struct adapter *sc = vi->pi->adapter; 871 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id]; 872 u_int const head = kring->rhead; 873 u_int n; 874 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 875 876 if (black_hole) 877 return (0); /* No updates ever. */ 878 879 if (netmap_no_pendintr || force_update) { 880 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx); 881 kring->nr_kflags &= ~NKR_PENDINTR; 882 } 883 884 if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) { 885 wmb(); 886 t4_write_reg(sc, sc->sge_kdoorbell_reg, 887 nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved)); 888 nm_rxq->fl_db_saved = 0; 889 } 890 891 /* Userspace done with buffers from kring->nr_hwcur to head */ 892 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 893 kring->nkr_num_slots - kring->nr_hwcur + head; 894 n &= ~7U; 895 if (n > 0) { 896 u_int fl_pidx = nm_rxq->fl_pidx; 897 struct netmap_slot *slot = &ring->slot[fl_pidx]; 898 uint64_t ba; 899 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx; 900 901 /* 902 * We always deal with 8 buffers at a time. We must have 903 * stopped at an 8B boundary (fl_pidx) last time around and we 904 * must have a multiple of 8B buffers to give to the freelist. 905 */ 906 MPASS((fl_pidx & 7) == 0); 907 MPASS((n & 7) == 0); 908 909 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots); 910 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx); 911 912 while (n > 0) { 913 for (i = 0; i < 8; i++, fl_pidx++, slot++) { 914 PNMB(na, slot, &ba); 915 MPASS(ba != 0); 916 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx); 917 slot->flags &= ~NS_BUF_CHANGED; 918 MPASS(fl_pidx <= nm_rxq->fl_sidx); 919 } 920 n -= 8; 921 if (fl_pidx == nm_rxq->fl_sidx) { 922 fl_pidx = 0; 923 slot = &ring->slot[0]; 924 } 925 if (++dbinc == 8 && n >= 32) { 926 wmb(); 927 if (starve_fl) 928 nm_rxq->fl_db_saved += dbinc; 929 else { 930 t4_write_reg(sc, sc->sge_kdoorbell_reg, 931 nm_rxq->fl_db_val | V_PIDX(dbinc)); 932 } 933 dbinc = 0; 934 } 935 } 936 MPASS(nm_rxq->fl_pidx == fl_pidx); 937 938 if (dbinc > 0) { 939 wmb(); 940 if (starve_fl) 941 nm_rxq->fl_db_saved += dbinc; 942 else { 943 t4_write_reg(sc, sc->sge_kdoorbell_reg, 944 nm_rxq->fl_db_val | V_PIDX(dbinc)); 945 } 946 } 947 } 948 949 return (0); 950 } 951 952 void 953 cxgbe_nm_attach(struct vi_info *vi) 954 { 955 struct port_info *pi; 956 struct adapter *sc; 957 struct netmap_adapter na; 958 959 MPASS(vi->nnmrxq > 0); 960 MPASS(vi->ifp != NULL); 961 962 pi = vi->pi; 963 sc = pi->adapter; 964 965 bzero(&na, sizeof(na)); 966 967 na.ifp = vi->ifp; 968 na.na_flags = NAF_BDG_MAYSLEEP; 969 970 /* Netmap doesn't know about the space reserved for the status page. */ 971 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE; 972 973 /* 974 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So 975 * num_rx_desc is based on the number of buffers that can be held in the 976 * freelist, and not the number of entries in the iq. (These two are 977 * not exactly the same due to the space taken up by the status page). 978 */ 979 na.num_rx_desc = rounddown(vi->qsize_rxq, 8); 980 na.nm_txsync = cxgbe_netmap_txsync; 981 na.nm_rxsync = cxgbe_netmap_rxsync; 982 na.nm_register = cxgbe_netmap_reg; 983 na.num_tx_rings = vi->nnmtxq; 984 na.num_rx_rings = vi->nnmrxq; 985 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */ 986 } 987 988 void 989 cxgbe_nm_detach(struct vi_info *vi) 990 { 991 992 MPASS(vi->nnmrxq > 0); 993 MPASS(vi->ifp != NULL); 994 995 netmap_detach(vi->ifp); 996 } 997 998 static inline const void * 999 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl) 1000 { 1001 1002 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL); 1003 1004 /* data[0] is RSS header */ 1005 return (&cpl->data[1]); 1006 } 1007 1008 static void 1009 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp, 1010 const struct cpl_sge_egr_update *egr) 1011 { 1012 uint32_t oq; 1013 struct sge_nm_txq *nm_txq; 1014 1015 oq = be32toh(egr->opcode_qid); 1016 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE); 1017 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start]; 1018 1019 netmap_tx_irq(ifp, nm_txq->nid); 1020 } 1021 1022 void 1023 service_nm_rxq(struct sge_nm_rxq *nm_rxq) 1024 { 1025 struct vi_info *vi = nm_rxq->vi; 1026 struct adapter *sc = vi->pi->adapter; 1027 struct ifnet *ifp = vi->ifp; 1028 struct netmap_adapter *na = NA(ifp); 1029 struct netmap_kring *kring = na->rx_rings[nm_rxq->nid]; 1030 struct netmap_ring *ring = kring->ring; 1031 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx]; 1032 const void *cpl; 1033 uint32_t lq; 1034 u_int work = 0; 1035 uint8_t opcode; 1036 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx); 1037 u_int fl_credits = fl_cidx & 7; 1038 u_int ndesc = 0; /* desc processed since last cidx update */ 1039 u_int nframes = 0; /* frames processed since last netmap wakeup */ 1040 1041 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) { 1042 1043 rmb(); 1044 1045 lq = be32toh(d->rsp.pldbuflen_qid); 1046 opcode = d->rss.opcode; 1047 cpl = &d->cpl[0]; 1048 1049 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) { 1050 case X_RSPD_TYPE_FLBUF: 1051 1052 /* fall through */ 1053 1054 case X_RSPD_TYPE_CPL: 1055 MPASS(opcode < NUM_CPL_CMDS); 1056 1057 switch (opcode) { 1058 case CPL_FW4_MSG: 1059 case CPL_FW6_MSG: 1060 cpl = unwrap_nm_fw6_msg(cpl); 1061 /* fall through */ 1062 case CPL_SGE_EGR_UPDATE: 1063 handle_nm_sge_egr_update(sc, ifp, cpl); 1064 break; 1065 case CPL_RX_PKT: 1066 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - 1067 sc->params.sge.fl_pktshift; 1068 ring->slot[fl_cidx].flags = 0; 1069 nframes++; 1070 if (!(lq & F_RSPD_NEWBUF)) { 1071 MPASS(black_hole == 2); 1072 break; 1073 } 1074 fl_credits++; 1075 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx)) 1076 fl_cidx = 0; 1077 break; 1078 default: 1079 panic("%s: unexpected opcode 0x%x on nm_rxq %p", 1080 __func__, opcode, nm_rxq); 1081 } 1082 break; 1083 1084 case X_RSPD_TYPE_INTR: 1085 /* Not equipped to handle forwarded interrupts. */ 1086 panic("%s: netmap queue received interrupt for iq %u\n", 1087 __func__, lq); 1088 1089 default: 1090 panic("%s: illegal response type %d on nm_rxq %p", 1091 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq); 1092 } 1093 1094 d++; 1095 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) { 1096 nm_rxq->iq_cidx = 0; 1097 d = &nm_rxq->iq_desc[0]; 1098 nm_rxq->iq_gen ^= F_RSPD_GEN; 1099 } 1100 1101 if (__predict_false(++nframes == rx_nframes) && !black_hole) { 1102 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1103 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1104 nframes = 0; 1105 } 1106 1107 if (__predict_false(++ndesc == rx_ndesc)) { 1108 if (black_hole && fl_credits >= 8) { 1109 fl_credits /= 8; 1110 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, 1111 nm_rxq->fl_sidx); 1112 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1113 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1114 fl_credits = fl_cidx & 7; 1115 } 1116 t4_write_reg(sc, sc->sge_gts_reg, 1117 V_CIDXINC(ndesc) | 1118 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 1119 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1120 ndesc = 0; 1121 } 1122 } 1123 1124 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1125 if (black_hole) { 1126 fl_credits /= 8; 1127 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx); 1128 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1129 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1130 } else if (nframes > 0) 1131 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1132 1133 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) | 1134 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) | 1135 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 1136 } 1137 #endif 1138