1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/counter.h> 39 #include <sys/rman.h> 40 #include <sys/types.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/rwlock.h> 44 #include <sys/sx.h> 45 #include <sys/vmem.h> 46 #include <vm/uma.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <machine/bus.h> 51 #include <sys/socket.h> 52 #include <sys/sysctl.h> 53 #include <sys/taskqueue.h> 54 #include <net/ethernet.h> 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_media.h> 58 #include <net/pfil.h> 59 #include <netinet/in.h> 60 #include <netinet/tcp_lro.h> 61 62 #include "offload.h" 63 #include "t4_ioctl.h" 64 #include "common/t4_msg.h" 65 #include "firmware/t4fw_interface.h" 66 67 #define KTR_CXGBE KTR_SPARE3 68 MALLOC_DECLARE(M_CXGBE); 69 #define CXGBE_UNIMPLEMENTED(s) \ 70 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 71 72 /* 73 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's 74 * LIST_HEAD when building iw_cxgbe. 75 */ 76 #define CXGBE_LIST_HEAD(name, type) \ 77 struct name { \ 78 struct type *lh_first; /* first element */ \ 79 } 80 81 #ifndef SYSCTL_ADD_UQUAD 82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 83 #define sysctl_handle_64 sysctl_handle_quad 84 #define CTLTYPE_U64 CTLTYPE_QUAD 85 #endif 86 87 SYSCTL_DECL(_hw_cxgbe); 88 89 struct adapter; 90 typedef struct adapter adapter_t; 91 92 enum { 93 /* 94 * All ingress queues use this entry size. Note that the firmware event 95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 96 * be at least 64. 97 */ 98 IQ_ESIZE = 64, 99 100 /* Default queue sizes for all kinds of ingress queues */ 101 FW_IQ_QSIZE = 256, 102 RX_IQ_QSIZE = 1024, 103 104 /* All egress queues use this entry size */ 105 EQ_ESIZE = 64, 106 107 /* Default queue sizes for all kinds of egress queues */ 108 CTRL_EQ_QSIZE = 1024, 109 TX_EQ_QSIZE = 1024, 110 111 #if MJUMPAGESIZE != MCLBYTES 112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 113 #else 114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 115 #endif 116 CL_METADATA_SIZE = CACHE_LINE_SIZE, 117 118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 119 TX_SGL_SEGS = 39, 120 TX_SGL_SEGS_TSO = 38, 121 TX_SGL_SEGS_VM = 38, 122 TX_SGL_SEGS_VM_TSO = 37, 123 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 124 TX_SGL_SEGS_VXLAN_TSO = 37, 125 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 126 }; 127 128 enum { 129 /* adapter intr_type */ 130 INTR_INTX = (1 << 0), 131 INTR_MSI = (1 << 1), 132 INTR_MSIX = (1 << 2) 133 }; 134 135 enum { 136 XGMAC_MTU = (1 << 0), 137 XGMAC_PROMISC = (1 << 1), 138 XGMAC_ALLMULTI = (1 << 2), 139 XGMAC_VLANEX = (1 << 3), 140 XGMAC_UCADDR = (1 << 4), 141 XGMAC_MCADDRS = (1 << 5), 142 143 XGMAC_ALL = 0xffff 144 }; 145 146 enum { 147 /* flags understood by begin_synchronized_op */ 148 HOLD_LOCK = (1 << 0), 149 SLEEP_OK = (1 << 1), 150 INTR_OK = (1 << 2), 151 152 /* flags understood by end_synchronized_op */ 153 LOCK_HELD = HOLD_LOCK, 154 }; 155 156 enum { 157 /* adapter flags */ 158 FULL_INIT_DONE = (1 << 0), 159 FW_OK = (1 << 1), 160 CHK_MBOX_ACCESS = (1 << 2), 161 MASTER_PF = (1 << 3), 162 ADAP_SYSCTL_CTX = (1 << 4), 163 ADAP_ERR = (1 << 5), 164 BUF_PACKING_OK = (1 << 6), 165 IS_VF = (1 << 7), 166 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 167 CXGBE_BUSY = (1 << 9), 168 HW_OFF_LIMITS = (1 << 10), /* off limits to all except reset_thread */ 169 170 /* port flags */ 171 HAS_TRACEQ = (1 << 3), 172 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 173 174 /* VI flags */ 175 DOOMED = (1 << 0), 176 VI_INIT_DONE = (1 << 1), 177 VI_SYSCTL_CTX = (1 << 2), 178 TX_USES_VM_WR = (1 << 3), 179 VI_SKIP_STATS = (1 << 4), 180 181 /* adapter debug_flags */ 182 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 183 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 184 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 185 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 186 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 187 }; 188 189 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 190 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 191 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 192 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 193 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 194 195 struct vi_info { 196 device_t dev; 197 struct port_info *pi; 198 struct adapter *adapter; 199 200 struct ifnet *ifp; 201 struct pfil_head *pfil; 202 203 unsigned long flags; 204 int if_flags; 205 206 uint16_t *rss, *nm_rss; 207 uint16_t viid; /* opaque VI identifier */ 208 uint16_t smt_idx; 209 uint16_t vin; 210 uint8_t vfvld; 211 int16_t xact_addr_filt;/* index of exact MAC address filter */ 212 uint16_t rss_size; /* size of VI's RSS table slice */ 213 uint16_t rss_base; /* start of VI's RSS table slice */ 214 int hashen; 215 216 int nintr; 217 int first_intr; 218 219 /* These need to be int as they are used in sysctl */ 220 int ntxq; /* # of tx queues */ 221 int first_txq; /* index of first tx queue */ 222 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 223 int nrxq; /* # of rx queues */ 224 int first_rxq; /* index of first rx queue */ 225 int nofldtxq; /* # of offload tx queues */ 226 int first_ofld_txq; /* index of first offload tx queue */ 227 int nofldrxq; /* # of offload rx queues */ 228 int first_ofld_rxq; /* index of first offload rx queue */ 229 int nnmtxq; 230 int first_nm_txq; 231 int nnmrxq; 232 int first_nm_rxq; 233 int tmr_idx; 234 int ofld_tmr_idx; 235 int pktc_idx; 236 int ofld_pktc_idx; 237 int qsize_rxq; 238 int qsize_txq; 239 240 struct timeval last_refreshed; 241 struct fw_vi_stats_vf stats; 242 struct mtx tick_mtx; 243 struct callout tick; 244 245 struct sysctl_ctx_list ctx; 246 struct sysctl_oid *rxq_oid; 247 struct sysctl_oid *txq_oid; 248 struct sysctl_oid *nm_rxq_oid; 249 struct sysctl_oid *nm_txq_oid; 250 struct sysctl_oid *ofld_rxq_oid; 251 struct sysctl_oid *ofld_txq_oid; 252 253 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 254 }; 255 256 struct tx_ch_rl_params { 257 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 258 uint32_t maxrate; 259 }; 260 261 /* CLRL state */ 262 enum clrl_state { 263 CS_UNINITIALIZED = 0, 264 CS_PARAMS_SET, /* sw parameters have been set. */ 265 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */ 266 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */ 267 CS_HW_CONFIGURED /* configured in the hardware. */ 268 }; 269 270 /* CLRL flags */ 271 enum { 272 CF_USER = (1 << 0), /* was configured by driver ioctl. */ 273 }; 274 275 struct tx_cl_rl_params { 276 enum clrl_state state; 277 int refcount; 278 uint8_t flags; 279 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 280 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 281 enum fw_sched_params_mode mode; /* aggr or per-flow */ 282 uint32_t maxrate; 283 uint16_t pktsize; 284 uint16_t burstsize; 285 }; 286 287 /* Tx scheduler parameters for a channel/port */ 288 struct tx_sched_params { 289 /* Channel Rate Limiter */ 290 struct tx_ch_rl_params ch_rl; 291 292 /* Class WRR */ 293 /* XXX */ 294 295 /* Class Rate Limiter (including the default pktsize and burstsize). */ 296 int pktsize; 297 int burstsize; 298 struct tx_cl_rl_params cl_rl[]; 299 }; 300 301 struct port_info { 302 device_t dev; 303 struct adapter *adapter; 304 305 struct vi_info *vi; 306 int nvi; 307 int up_vis; 308 int uld_vis; 309 bool vxlan_tcam_entry; 310 311 struct tx_sched_params *sched_params; 312 313 struct mtx pi_lock; 314 char lockname[16]; 315 unsigned long flags; 316 317 uint8_t lport; /* associated offload logical port */ 318 int8_t mdio_addr; 319 uint8_t port_type; 320 uint8_t mod_type; 321 uint8_t port_id; 322 uint8_t tx_chan; 323 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 324 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 325 uint8_t rx_c_chan; /* rx TP c-channel */ 326 327 struct link_config link_cfg; 328 struct ifmedia media; 329 330 struct port_stats stats; 331 u_int tnl_cong_drops; 332 u_int tx_parse_error; 333 int fcs_reg; 334 uint64_t fcs_base; 335 }; 336 337 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 338 339 struct cluster_metadata { 340 uma_zone_t zone; 341 caddr_t cl; 342 u_int refcount; 343 }; 344 345 struct fl_sdesc { 346 caddr_t cl; 347 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 348 int16_t moff; /* offset of metadata from cl */ 349 uint8_t zidx; 350 }; 351 352 struct tx_desc { 353 __be64 flit[8]; 354 }; 355 356 struct tx_sdesc { 357 struct mbuf *m; /* m_nextpkt linked chain of frames */ 358 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 359 }; 360 361 362 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 363 struct iq_desc { 364 struct rss_header rss; 365 uint8_t cpl[IQ_PAD]; 366 struct rsp_ctrl rsp; 367 }; 368 #undef IQ_PAD 369 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 370 371 enum { 372 /* iq flags */ 373 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 374 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 375 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 376 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 377 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 378 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 379 380 /* iq state */ 381 IQS_DISABLED = 0, 382 IQS_BUSY = 1, 383 IQS_IDLE = 2, 384 385 /* netmap related flags */ 386 NM_OFF = 0, 387 NM_ON = 1, 388 NM_BUSY = 2, 389 }; 390 391 enum { 392 CPL_COOKIE_RESERVED = 0, 393 CPL_COOKIE_FILTER, 394 CPL_COOKIE_DDP0, 395 CPL_COOKIE_DDP1, 396 CPL_COOKIE_TOM, 397 CPL_COOKIE_HASHFILTER, 398 CPL_COOKIE_ETHOFLD, 399 CPL_COOKIE_KERN_TLS, 400 401 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 402 }; 403 404 struct sge_iq; 405 struct rss_header; 406 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 407 struct mbuf *); 408 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 409 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 410 411 /* 412 * Ingress Queue: T4 is producer, driver is consumer. 413 */ 414 struct sge_iq { 415 uint32_t flags; 416 volatile int state; 417 struct adapter *adapter; 418 struct iq_desc *desc; /* KVA of descriptor ring */ 419 int8_t intr_pktc_idx; /* packet count threshold index */ 420 uint8_t gen; /* generation bit */ 421 uint8_t intr_params; /* interrupt holdoff parameters */ 422 int8_t cong; /* congestion settings */ 423 uint16_t qsize; /* size (# of entries) of the queue */ 424 uint16_t sidx; /* index of the entry with the status page */ 425 uint16_t cidx; /* consumer index */ 426 uint16_t cntxt_id; /* SGE context id for the iq */ 427 uint16_t abs_id; /* absolute SGE id for the iq */ 428 int16_t intr_idx; /* interrupt used by the queue */ 429 430 STAILQ_ENTRY(sge_iq) link; 431 432 bus_dma_tag_t desc_tag; 433 bus_dmamap_t desc_map; 434 bus_addr_t ba; /* bus address of descriptor ring */ 435 }; 436 437 enum { 438 /* eq type */ 439 EQ_CTRL = 1, 440 EQ_ETH = 2, 441 EQ_OFLD = 3, 442 443 /* eq flags */ 444 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 445 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 446 EQ_ENABLED = (1 << 3), /* open for business */ 447 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 448 }; 449 450 /* Listed in order of preference. Update t4_sysctls too if you change these */ 451 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 452 453 /* 454 * Egress Queue: driver is producer, T4 is consumer. 455 * 456 * Note: A free list is an egress queue (driver produces the buffers and T4 457 * consumes them) but it's special enough to have its own struct (see sge_fl). 458 */ 459 struct sge_eq { 460 unsigned int flags; /* MUST be first */ 461 unsigned int cntxt_id; /* SGE context id for the eq */ 462 unsigned int abs_id; /* absolute SGE id for the eq */ 463 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 464 uint8_t doorbells; 465 uint8_t tx_chan; /* tx channel used by the eq */ 466 struct mtx eq_lock; 467 468 struct tx_desc *desc; /* KVA of descriptor ring */ 469 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 470 u_int udb_qid; /* relative qid within the doorbell page */ 471 uint16_t sidx; /* index of the entry with the status page */ 472 uint16_t cidx; /* consumer idx (desc idx) */ 473 uint16_t pidx; /* producer idx (desc idx) */ 474 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 475 uint16_t dbidx; /* pidx of the most recent doorbell */ 476 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 477 volatile u_int equiq; /* EQUIQ outstanding */ 478 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 479 480 bus_dma_tag_t desc_tag; 481 bus_dmamap_t desc_map; 482 bus_addr_t ba; /* bus address of descriptor ring */ 483 char lockname[16]; 484 }; 485 486 struct rx_buf_info { 487 uma_zone_t zone; /* zone that this cluster comes from */ 488 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 489 * hwsize[hwidx1] = size1. No spare. */ 490 uint16_t size2; /* hwsize[hwidx2] = size2. 491 * spare in cluster = size1 - size2. */ 492 int8_t hwidx1; /* SGE bufsize idx for size1 */ 493 int8_t hwidx2; /* SGE bufsize idx for size2 */ 494 uint8_t type; /* EXT_xxx type of the cluster */ 495 }; 496 497 enum { 498 NUM_MEMWIN = 3, 499 500 MEMWIN0_APERTURE = 2048, 501 MEMWIN0_BASE = 0x1b800, 502 503 MEMWIN1_APERTURE = 32768, 504 MEMWIN1_BASE = 0x28000, 505 506 MEMWIN2_APERTURE_T4 = 65536, 507 MEMWIN2_BASE_T4 = 0x30000, 508 509 MEMWIN2_APERTURE_T5 = 128 * 1024, 510 MEMWIN2_BASE_T5 = 0x60000, 511 }; 512 513 struct memwin { 514 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 515 uint32_t mw_base; /* constant after setup_memwin */ 516 uint32_t mw_aperture; /* ditto */ 517 uint32_t mw_curpos; /* protected by mw_lock */ 518 }; 519 520 enum { 521 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 522 FL_DOOMED = (1 << 1), /* about to be destroyed */ 523 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 524 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 525 }; 526 527 #define FL_RUNNING_LOW(fl) \ 528 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 529 #define FL_NOT_RUNNING_LOW(fl) \ 530 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 531 532 struct sge_fl { 533 struct mtx fl_lock; 534 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 535 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 536 uint16_t zidx; /* refill zone idx */ 537 uint16_t safe_zidx; 538 uint16_t lowat; /* # of buffers <= this means fl needs help */ 539 int flags; 540 uint16_t buf_boundary; 541 542 /* The 16b idx all deal with hw descriptors */ 543 uint16_t dbidx; /* hw pidx after last doorbell */ 544 uint16_t sidx; /* index of status page */ 545 volatile uint16_t hw_cidx; 546 547 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 548 uint32_t cidx; /* consumer index */ 549 uint32_t pidx; /* producer index */ 550 551 uint32_t dbval; 552 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 553 volatile uint32_t *udb; 554 555 uint64_t cl_allocated; /* # of clusters allocated */ 556 uint64_t cl_recycled; /* # of clusters recycled */ 557 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 558 559 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 560 struct mbuf *m0; 561 struct mbuf **pnext; 562 u_int remaining; 563 564 uint16_t qsize; /* # of hw descriptors (status page included) */ 565 uint16_t cntxt_id; /* SGE context id for the freelist */ 566 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 567 bus_dma_tag_t desc_tag; 568 bus_dmamap_t desc_map; 569 char lockname[16]; 570 bus_addr_t ba; /* bus address of descriptor ring */ 571 }; 572 573 struct mp_ring; 574 575 struct txpkts { 576 uint8_t wr_type; /* type 0 or type 1 */ 577 uint8_t npkt; /* # of packets in this work request */ 578 uint8_t len16; /* # of 16B pieces used by this work request */ 579 uint8_t score; 580 uint8_t max_npkt; /* maximum number of packets allowed */ 581 uint16_t plen; /* total payload (sum of all packets) */ 582 583 /* straight from fw_eth_tx_pkts_vm_wr. */ 584 __u8 ethmacdst[6]; 585 __u8 ethmacsrc[6]; 586 __be16 ethtype; 587 __be16 vlantci; 588 589 struct mbuf *mb[15]; 590 }; 591 592 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 593 struct sge_txq { 594 struct sge_eq eq; /* MUST be first */ 595 596 struct ifnet *ifp; /* the interface this txq belongs to */ 597 struct mp_ring *r; /* tx software ring */ 598 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 599 struct sglist *gl; 600 __be32 cpl_ctrl0; /* for convenience */ 601 int tc_idx; /* traffic class */ 602 uint64_t last_tx; /* cycle count when eth_tx was last called */ 603 struct txpkts txp; 604 605 struct task tx_reclaim_task; 606 /* stats for common events first */ 607 608 uint64_t txcsum; /* # of times hardware assisted with checksum */ 609 uint64_t tso_wrs; /* # of TSO work requests */ 610 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 611 uint64_t imm_wrs; /* # of work requests with immediate data */ 612 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 613 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 614 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 615 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 616 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 617 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 618 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 619 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 620 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 621 uint64_t vxlan_txcsum; 622 623 uint64_t kern_tls_records; 624 uint64_t kern_tls_short; 625 uint64_t kern_tls_partial; 626 uint64_t kern_tls_full; 627 uint64_t kern_tls_octets; 628 uint64_t kern_tls_waste; 629 uint64_t kern_tls_options; 630 uint64_t kern_tls_header; 631 uint64_t kern_tls_fin; 632 uint64_t kern_tls_fin_short; 633 uint64_t kern_tls_cbc; 634 uint64_t kern_tls_gcm; 635 636 /* stats for not-that-common events */ 637 638 /* Optional scratch space for constructing work requests. */ 639 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 640 } __aligned(CACHE_LINE_SIZE); 641 642 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 643 struct sge_rxq { 644 struct sge_iq iq; /* MUST be first */ 645 struct sge_fl fl; /* MUST follow iq */ 646 647 struct ifnet *ifp; /* the interface this rxq belongs to */ 648 struct lro_ctrl lro; /* LRO state */ 649 650 /* stats for common events first */ 651 652 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 653 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 654 uint64_t vxlan_rxcsum; 655 656 /* stats for not-that-common events */ 657 658 } __aligned(CACHE_LINE_SIZE); 659 660 static inline struct sge_rxq * 661 iq_to_rxq(struct sge_iq *iq) 662 { 663 664 return (__containerof(iq, struct sge_rxq, iq)); 665 } 666 667 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 668 struct sge_ofld_rxq { 669 struct sge_iq iq; /* MUST be first */ 670 struct sge_fl fl; /* MUST follow iq */ 671 counter_u64_t rx_iscsi_ddp_setup_ok; 672 counter_u64_t rx_iscsi_ddp_setup_error; 673 uint64_t rx_iscsi_ddp_pdus; 674 uint64_t rx_iscsi_ddp_octets; 675 uint64_t rx_iscsi_fl_pdus; 676 uint64_t rx_iscsi_fl_octets; 677 uint64_t rx_iscsi_padding_errors; 678 uint64_t rx_iscsi_header_digest_errors; 679 uint64_t rx_iscsi_data_digest_errors; 680 u_long rx_toe_tls_records; 681 u_long rx_toe_tls_octets; 682 } __aligned(CACHE_LINE_SIZE); 683 684 static inline struct sge_ofld_rxq * 685 iq_to_ofld_rxq(struct sge_iq *iq) 686 { 687 688 return (__containerof(iq, struct sge_ofld_rxq, iq)); 689 } 690 691 struct wrqe { 692 STAILQ_ENTRY(wrqe) link; 693 struct sge_wrq *wrq; 694 int wr_len; 695 char wr[] __aligned(16); 696 }; 697 698 struct wrq_cookie { 699 TAILQ_ENTRY(wrq_cookie) link; 700 int ndesc; 701 int pidx; 702 }; 703 704 /* 705 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 706 * are of this type. 707 */ 708 struct sge_wrq { 709 struct sge_eq eq; /* MUST be first */ 710 711 struct adapter *adapter; 712 struct task wrq_tx_task; 713 714 /* Tx desc reserved but WR not "committed" yet. */ 715 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 716 717 /* List of WRs ready to go out as soon as descriptors are available. */ 718 STAILQ_HEAD(, wrqe) wr_list; 719 u_int nwr_pending; 720 u_int ndesc_needed; 721 722 /* stats for common events first */ 723 724 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 725 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 726 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 727 728 /* stats for not-that-common events */ 729 730 /* 731 * Scratch space for work requests that wrap around after reaching the 732 * status page, and some information about the last WR that used it. 733 */ 734 uint16_t ss_pidx; 735 uint16_t ss_len; 736 uint8_t ss[SGE_MAX_WR_LEN]; 737 738 } __aligned(CACHE_LINE_SIZE); 739 740 /* ofld_txq: SGE egress queue + miscellaneous items */ 741 struct sge_ofld_txq { 742 struct sge_wrq wrq; 743 counter_u64_t tx_iscsi_pdus; 744 counter_u64_t tx_iscsi_octets; 745 counter_u64_t tx_iscsi_iso_wrs; 746 counter_u64_t tx_toe_tls_records; 747 counter_u64_t tx_toe_tls_octets; 748 } __aligned(CACHE_LINE_SIZE); 749 750 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 751 struct sge_nm_rxq { 752 /* Items used by the driver rx ithread are in this cacheline. */ 753 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 754 u_int nid; /* netmap ring # for this queue */ 755 struct vi_info *vi; 756 757 struct iq_desc *iq_desc; 758 uint16_t iq_abs_id; 759 uint16_t iq_cntxt_id; 760 uint16_t iq_cidx; 761 uint16_t iq_sidx; 762 uint8_t iq_gen; 763 uint32_t fl_sidx; 764 765 /* Items used by netmap rxsync are in this cacheline. */ 766 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 767 uint16_t fl_cntxt_id; 768 uint32_t fl_pidx; 769 uint32_t fl_sidx2; /* copy of fl_sidx */ 770 uint32_t fl_db_val; 771 u_int fl_db_saved; 772 u_int fl_db_threshold; /* in descriptors */ 773 u_int fl_hwidx:4; 774 775 /* 776 * fl_cidx is used by both the ithread and rxsync, the rest are not used 777 * in the rx fast path. 778 */ 779 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 780 781 bus_dma_tag_t iq_desc_tag; 782 bus_dmamap_t iq_desc_map; 783 bus_addr_t iq_ba; 784 int intr_idx; 785 786 bus_dma_tag_t fl_desc_tag; 787 bus_dmamap_t fl_desc_map; 788 bus_addr_t fl_ba; 789 }; 790 791 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 792 struct sge_nm_txq { 793 struct tx_desc *desc; 794 uint16_t cidx; 795 uint16_t pidx; 796 uint16_t sidx; 797 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 798 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 799 uint16_t dbidx; /* pidx of the most recent doorbell */ 800 uint8_t doorbells; 801 volatile uint32_t *udb; 802 u_int udb_qid; 803 u_int cntxt_id; 804 __be32 cpl_ctrl0; /* for convenience */ 805 __be32 op_pkd; /* ditto */ 806 u_int nid; /* netmap ring # for this queue */ 807 808 /* infrequently used items after this */ 809 810 bus_dma_tag_t desc_tag; 811 bus_dmamap_t desc_map; 812 bus_addr_t ba; 813 int iqidx; 814 } __aligned(CACHE_LINE_SIZE); 815 816 struct sge { 817 int nrxq; /* total # of Ethernet rx queues */ 818 int ntxq; /* total # of Ethernet tx queues */ 819 int nofldrxq; /* total # of TOE rx queues */ 820 int nofldtxq; /* total # of TOE tx queues */ 821 int nnmrxq; /* total # of netmap rx queues */ 822 int nnmtxq; /* total # of netmap tx queues */ 823 int niq; /* total # of ingress queues */ 824 int neq; /* total # of egress queues */ 825 826 struct sge_iq fwq; /* Firmware event queue */ 827 struct sge_wrq *ctrlq; /* Control queues */ 828 struct sge_txq *txq; /* NIC tx queues */ 829 struct sge_rxq *rxq; /* NIC rx queues */ 830 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 831 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 832 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 833 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 834 835 uint16_t iq_start; /* first cntxt_id */ 836 uint16_t iq_base; /* first abs_id */ 837 int eq_start; /* first cntxt_id */ 838 int eq_base; /* first abs_id */ 839 int iqmap_sz; 840 int eqmap_sz; 841 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 842 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 843 844 int8_t safe_zidx; 845 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 846 }; 847 848 struct devnames { 849 const char *nexus_name; 850 const char *ifnet_name; 851 const char *vi_ifnet_name; 852 const char *pf03_drv_name; 853 const char *vf_nexus_name; 854 const char *vf_ifnet_name; 855 }; 856 857 struct clip_entry; 858 859 struct adapter { 860 SLIST_ENTRY(adapter) link; 861 device_t dev; 862 struct cdev *cdev; 863 const struct devnames *names; 864 865 /* PCIe register resources */ 866 int regs_rid; 867 struct resource *regs_res; 868 int msix_rid; 869 struct resource *msix_res; 870 bus_space_handle_t bh; 871 bus_space_tag_t bt; 872 bus_size_t mmio_len; 873 int udbs_rid; 874 struct resource *udbs_res; 875 volatile uint8_t *udbs_base; 876 877 unsigned int pf; 878 unsigned int mbox; 879 unsigned int vpd_busy; 880 unsigned int vpd_flag; 881 882 /* Interrupt information */ 883 int intr_type; 884 int intr_count; 885 struct irq { 886 struct resource *res; 887 int rid; 888 void *tag; 889 struct sge_rxq *rxq; 890 struct sge_nm_rxq *nm_rxq; 891 } __aligned(CACHE_LINE_SIZE) *irq; 892 int sge_gts_reg; 893 int sge_kdoorbell_reg; 894 895 bus_dma_tag_t dmat; /* Parent DMA tag */ 896 897 struct sge sge; 898 int lro_timeout; 899 int sc_do_rxcopy; 900 901 int vxlan_port; 902 u_int vxlan_refcount; 903 int rawf_base; 904 int nrawf; 905 906 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 907 struct task async_event_task; 908 struct port_info *port[MAX_NPORTS]; 909 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 910 911 CXGBE_LIST_HEAD(, clip_entry) *clip_table; 912 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */ 913 u_long clip_mask; 914 int clip_gen; 915 struct timeout_task clip_task; 916 917 void *tom_softc; /* (struct tom_data *) */ 918 struct tom_tunables tt; 919 struct t4_offload_policy *policy; 920 struct rwlock policy_lock; 921 922 void *iwarp_softc; /* (struct c4iw_dev *) */ 923 struct iw_tunables iwt; 924 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 925 void *ccr_softc; /* (struct ccr_softc *) */ 926 struct l2t_data *l2t; /* L2 table */ 927 struct smt_data *smt; /* Source MAC Table */ 928 struct tid_info tids; 929 vmem_t *key_map; 930 struct tls_tunables tlst; 931 932 uint8_t doorbells; 933 int offload_map; /* port_id's with IFCAP_TOE enabled */ 934 int bt_map; /* tx_chan's with BASE-T */ 935 int active_ulds; /* ULDs activated on this adapter */ 936 int flags; 937 int debug_flags; 938 939 char ifp_lockname[16]; 940 struct mtx ifp_lock; 941 struct ifnet *ifp; /* tracer ifp */ 942 struct ifmedia media; 943 int traceq; /* iq used by all tracers, -1 if none */ 944 int tracer_valid; /* bitmap of valid tracers */ 945 int tracer_enabled; /* bitmap of enabled tracers */ 946 947 char fw_version[16]; 948 char tp_version[16]; 949 char er_version[16]; 950 char bs_version[16]; 951 char cfg_file[32]; 952 u_int cfcsum; 953 struct adapter_params params; 954 const struct chip_params *chip_params; 955 struct t4_virt_res vres; 956 957 uint16_t nbmcaps; 958 uint16_t linkcaps; 959 uint16_t switchcaps; 960 uint16_t niccaps; 961 uint16_t toecaps; 962 uint16_t rdmacaps; 963 uint16_t cryptocaps; 964 uint16_t iscsicaps; 965 uint16_t fcoecaps; 966 967 struct sysctl_ctx_list ctx; 968 struct sysctl_oid *ctrlq_oid; 969 struct sysctl_oid *fwq_oid; 970 971 struct mtx sc_lock; 972 char lockname[16]; 973 974 /* Starving free lists */ 975 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 976 TAILQ_HEAD(, sge_fl) sfl; 977 struct callout sfl_callout; 978 979 /* 980 * Driver code that can run when the adapter is suspended must use this 981 * lock or a synchronized_op and check for HW_OFF_LIMITS before 982 * accessing hardware. 983 * 984 * XXX: could be changed to rwlock. wlock in suspend/resume and for 985 * indirect register access, rlock everywhere else. 986 */ 987 struct mtx reg_lock; 988 989 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 990 991 struct mtx tc_lock; 992 struct task tc_task; 993 994 struct task reset_task; 995 const void *reset_thread; 996 int num_resets; 997 int incarnation; 998 999 const char *last_op; 1000 const void *last_op_thr; 1001 int last_op_flags; 1002 1003 int swintr; 1004 int sensor_resets; 1005 1006 struct callout ktls_tick; 1007 }; 1008 1009 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 1010 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 1011 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 1012 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 1013 1014 #define ASSERT_SYNCHRONIZED_OP(sc) \ 1015 KASSERT(IS_BUSY(sc) && \ 1016 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 1017 ("%s: operation not synchronized.", __func__)) 1018 1019 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1020 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1021 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1022 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1023 1024 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1025 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1026 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1027 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1028 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1029 1030 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1031 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1032 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1033 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1034 1035 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1036 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1037 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1038 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1039 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1040 1041 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1042 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1043 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1044 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1045 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1046 1047 #define for_each_txq(vi, iter, q) \ 1048 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1049 iter < vi->ntxq; ++iter, ++q) 1050 #define for_each_rxq(vi, iter, q) \ 1051 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1052 iter < vi->nrxq; ++iter, ++q) 1053 #define for_each_ofld_txq(vi, iter, q) \ 1054 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1055 iter < vi->nofldtxq; ++iter, ++q) 1056 #define for_each_ofld_rxq(vi, iter, q) \ 1057 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1058 iter < vi->nofldrxq; ++iter, ++q) 1059 #define for_each_nm_txq(vi, iter, q) \ 1060 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1061 iter < vi->nnmtxq; ++iter, ++q) 1062 #define for_each_nm_rxq(vi, iter, q) \ 1063 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1064 iter < vi->nnmrxq; ++iter, ++q) 1065 #define for_each_vi(_pi, _iter, _vi) \ 1066 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1067 ++(_iter), ++(_vi)) 1068 1069 #define IDXINCR(idx, incr, wrap) do { \ 1070 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1071 } while (0) 1072 #define IDXDIFF(head, tail, wrap) \ 1073 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1074 1075 /* One for errors, one for firmware events */ 1076 #define T4_EXTRA_INTR 2 1077 1078 /* One for firmware events */ 1079 #define T4VF_EXTRA_INTR 1 1080 1081 static inline int 1082 forwarding_intr_to_fwq(struct adapter *sc) 1083 { 1084 1085 return (sc->intr_count == 1); 1086 } 1087 1088 /* Works reliably inside a sync_op or with reg_lock held. */ 1089 static inline bool 1090 hw_off_limits(struct adapter *sc) 1091 { 1092 return (__predict_false(sc->flags & HW_OFF_LIMITS)); 1093 } 1094 1095 static inline uint32_t 1096 t4_read_reg(struct adapter *sc, uint32_t reg) 1097 { 1098 if (hw_off_limits(sc)) 1099 MPASS(curthread == sc->reset_thread); 1100 return bus_space_read_4(sc->bt, sc->bh, reg); 1101 } 1102 1103 static inline void 1104 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1105 { 1106 if (hw_off_limits(sc)) 1107 MPASS(curthread == sc->reset_thread); 1108 bus_space_write_4(sc->bt, sc->bh, reg, val); 1109 } 1110 1111 static inline uint64_t 1112 t4_read_reg64(struct adapter *sc, uint32_t reg) 1113 { 1114 if (hw_off_limits(sc)) 1115 MPASS(curthread == sc->reset_thread); 1116 #ifdef __LP64__ 1117 return bus_space_read_8(sc->bt, sc->bh, reg); 1118 #else 1119 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1120 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1121 1122 #endif 1123 } 1124 1125 static inline void 1126 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1127 { 1128 if (hw_off_limits(sc)) 1129 MPASS(curthread == sc->reset_thread); 1130 #ifdef __LP64__ 1131 bus_space_write_8(sc->bt, sc->bh, reg, val); 1132 #else 1133 bus_space_write_4(sc->bt, sc->bh, reg, val); 1134 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1135 #endif 1136 } 1137 1138 static inline void 1139 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1140 { 1141 if (hw_off_limits(sc)) 1142 MPASS(curthread == sc->reset_thread); 1143 *val = pci_read_config(sc->dev, reg, 1); 1144 } 1145 1146 static inline void 1147 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1148 { 1149 if (hw_off_limits(sc)) 1150 MPASS(curthread == sc->reset_thread); 1151 pci_write_config(sc->dev, reg, val, 1); 1152 } 1153 1154 static inline void 1155 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1156 { 1157 1158 if (hw_off_limits(sc)) 1159 MPASS(curthread == sc->reset_thread); 1160 *val = pci_read_config(sc->dev, reg, 2); 1161 } 1162 1163 static inline void 1164 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1165 { 1166 if (hw_off_limits(sc)) 1167 MPASS(curthread == sc->reset_thread); 1168 pci_write_config(sc->dev, reg, val, 2); 1169 } 1170 1171 static inline void 1172 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1173 { 1174 if (hw_off_limits(sc)) 1175 MPASS(curthread == sc->reset_thread); 1176 *val = pci_read_config(sc->dev, reg, 4); 1177 } 1178 1179 static inline void 1180 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1181 { 1182 if (hw_off_limits(sc)) 1183 MPASS(curthread == sc->reset_thread); 1184 pci_write_config(sc->dev, reg, val, 4); 1185 } 1186 1187 static inline struct port_info * 1188 adap2pinfo(struct adapter *sc, int idx) 1189 { 1190 1191 return (sc->port[idx]); 1192 } 1193 1194 static inline void 1195 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1196 { 1197 1198 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1199 } 1200 1201 static inline int 1202 tx_resume_threshold(struct sge_eq *eq) 1203 { 1204 1205 /* not quite the same as qsize / 4, but this will do. */ 1206 return (eq->sidx / 4); 1207 } 1208 1209 static inline int 1210 t4_use_ldst(struct adapter *sc) 1211 { 1212 1213 #ifdef notyet 1214 return (sc->flags & FW_OK || !sc->use_bd); 1215 #else 1216 return (0); 1217 #endif 1218 } 1219 1220 static inline void 1221 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1222 const char *msg, const __be64 *const p, const bool err) 1223 { 1224 1225 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1226 return; 1227 if (p != NULL) { 1228 log(err ? LOG_ERR : LOG_DEBUG, 1229 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1230 "%016llx %016llx %016llx %016llx\n", 1231 device_get_nameunit(sc->dev), mbox, msg, 1232 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1233 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1234 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1235 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1236 } else { 1237 log(err ? LOG_ERR : LOG_DEBUG, 1238 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1239 "%016llx %016llx %016llx %016llx\n", 1240 device_get_nameunit(sc->dev), mbox, msg, 1241 (long long)t4_read_reg64(sc, reg), 1242 (long long)t4_read_reg64(sc, reg + 8), 1243 (long long)t4_read_reg64(sc, reg + 16), 1244 (long long)t4_read_reg64(sc, reg + 24), 1245 (long long)t4_read_reg64(sc, reg + 32), 1246 (long long)t4_read_reg64(sc, reg + 40), 1247 (long long)t4_read_reg64(sc, reg + 48), 1248 (long long)t4_read_reg64(sc, reg + 56)); 1249 } 1250 } 1251 1252 /* t4_main.c */ 1253 extern int t4_ntxq; 1254 extern int t4_nrxq; 1255 extern int t4_intr_types; 1256 extern int t4_tmr_idx; 1257 extern int t4_pktc_idx; 1258 extern unsigned int t4_qsize_rxq; 1259 extern unsigned int t4_qsize_txq; 1260 extern device_method_t cxgbe_methods[]; 1261 1262 int t4_os_find_pci_capability(struct adapter *, int); 1263 int t4_os_pci_save_state(struct adapter *); 1264 int t4_os_pci_restore_state(struct adapter *); 1265 void t4_os_portmod_changed(struct port_info *); 1266 void t4_os_link_changed(struct port_info *); 1267 void t4_iterate(void (*)(struct adapter *, void *), void *); 1268 void t4_init_devnames(struct adapter *); 1269 void t4_add_adapter(struct adapter *); 1270 int t4_detach_common(device_t); 1271 int t4_map_bars_0_and_4(struct adapter *); 1272 int t4_map_bar_2(struct adapter *); 1273 int t4_setup_intr_handlers(struct adapter *); 1274 void t4_sysctls(struct adapter *); 1275 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1276 void doom_vi(struct adapter *, struct vi_info *); 1277 void end_synchronized_op(struct adapter *, int); 1278 int update_mac_settings(struct ifnet *, int); 1279 int adapter_init(struct adapter *); 1280 int vi_init(struct vi_info *); 1281 void vi_sysctls(struct vi_info *); 1282 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1283 int alloc_atid(struct adapter *, void *); 1284 void *lookup_atid(struct adapter *, int); 1285 void free_atid(struct adapter *, int); 1286 void release_tid(struct adapter *, int, struct sge_wrq *); 1287 int cxgbe_media_change(struct ifnet *); 1288 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1289 bool t4_os_dump_cimla(struct adapter *, int, bool); 1290 void t4_os_dump_devlog(struct adapter *); 1291 1292 #ifdef KERN_TLS 1293 /* t4_kern_tls.c */ 1294 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1295 struct m_snd_tag **); 1296 void t6_ktls_modload(void); 1297 void t6_ktls_modunload(void); 1298 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *); 1299 int t6_ktls_parse_pkt(struct mbuf *, int *, int *); 1300 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int); 1301 #endif 1302 1303 /* t4_keyctx.c */ 1304 struct auth_hash; 1305 union authctx; 1306 #ifdef KERN_TLS 1307 struct ktls_session; 1308 struct tls_key_req; 1309 struct tls_keyctx; 1310 #endif 1311 1312 void t4_aes_getdeckey(void *, const void *, unsigned int); 1313 void t4_copy_partial_hash(int, union authctx *, void *); 1314 void t4_init_gmac_hash(const char *, int, char *); 1315 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int, 1316 char *); 1317 #ifdef KERN_TLS 1318 u_int t4_tls_key_info_size(const struct ktls_session *); 1319 int t4_tls_proto_ver(const struct ktls_session *); 1320 int t4_tls_cipher_mode(const struct ktls_session *); 1321 int t4_tls_auth_mode(const struct ktls_session *); 1322 int t4_tls_hmac_ctrl(const struct ktls_session *); 1323 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *); 1324 int t4_alloc_tls_keyid(struct adapter *); 1325 void t4_free_tls_keyid(struct adapter *, int); 1326 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int, 1327 struct tls_key_req *); 1328 #endif 1329 1330 #ifdef DEV_NETMAP 1331 /* t4_netmap.c */ 1332 struct sge_nm_rxq; 1333 void cxgbe_nm_attach(struct vi_info *); 1334 void cxgbe_nm_detach(struct vi_info *); 1335 void service_nm_rxq(struct sge_nm_rxq *); 1336 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1337 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1338 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1339 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1340 #endif 1341 1342 /* t4_sge.c */ 1343 void t4_sge_modload(void); 1344 void t4_sge_modunload(void); 1345 uint64_t t4_sge_extfree_refs(void); 1346 void t4_tweak_chip_settings(struct adapter *); 1347 int t4_verify_chip_settings(struct adapter *); 1348 void t4_init_rx_buf_info(struct adapter *); 1349 int t4_create_dma_tag(struct adapter *); 1350 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1351 struct sysctl_oid_list *); 1352 int t4_destroy_dma_tag(struct adapter *); 1353 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1354 bus_addr_t *, void **); 1355 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1356 void *); 1357 void free_fl_buffers(struct adapter *, struct sge_fl *); 1358 int t4_setup_adapter_queues(struct adapter *); 1359 int t4_teardown_adapter_queues(struct adapter *); 1360 int t4_setup_vi_queues(struct vi_info *); 1361 int t4_teardown_vi_queues(struct vi_info *); 1362 void t4_intr_all(void *); 1363 void t4_intr(void *); 1364 #ifdef DEV_NETMAP 1365 void t4_nm_intr(void *); 1366 void t4_vi_intr(void *); 1367 #endif 1368 void t4_intr_err(void *); 1369 void t4_intr_evt(void *); 1370 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1371 void t4_update_fl_bufsize(struct ifnet *); 1372 struct mbuf *alloc_wr_mbuf(int, int); 1373 int parse_pkt(struct mbuf **, bool); 1374 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1375 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1376 int tnl_cong(struct port_info *, int); 1377 void t4_register_an_handler(an_handler_t); 1378 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1379 void t4_register_cpl_handler(int, cpl_handler_t); 1380 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1381 #ifdef RATELIMIT 1382 int ethofld_transmit(struct ifnet *, struct mbuf *); 1383 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1384 #endif 1385 1386 /* t4_tracer.c */ 1387 struct t4_tracer; 1388 void t4_tracer_modload(void); 1389 void t4_tracer_modunload(void); 1390 void t4_tracer_port_detach(struct adapter *); 1391 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1392 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1393 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1394 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1395 1396 /* t4_sched.c */ 1397 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1398 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1399 int t4_init_tx_sched(struct adapter *); 1400 int t4_free_tx_sched(struct adapter *); 1401 void t4_update_tx_sched(struct adapter *); 1402 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1403 void t4_release_cl_rl(struct adapter *, int, int); 1404 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1405 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1406 #ifdef RATELIMIT 1407 void t4_init_etid_table(struct adapter *); 1408 void t4_free_etid_table(struct adapter *); 1409 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1410 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1411 struct m_snd_tag **); 1412 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1413 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *); 1414 #endif 1415 1416 /* t4_filter.c */ 1417 int get_filter_mode(struct adapter *, uint32_t *); 1418 int set_filter_mode(struct adapter *, uint32_t); 1419 int set_filter_mask(struct adapter *, uint32_t); 1420 int get_filter(struct adapter *, struct t4_filter *); 1421 int set_filter(struct adapter *, struct t4_filter *); 1422 int del_filter(struct adapter *, struct t4_filter *); 1423 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1424 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1425 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1426 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1427 void free_hftid_hash(struct tid_info *); 1428 1429 static inline struct wrqe * 1430 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1431 { 1432 int len = offsetof(struct wrqe, wr) + wr_len; 1433 struct wrqe *wr; 1434 1435 wr = malloc(len, M_CXGBE, M_NOWAIT); 1436 if (__predict_false(wr == NULL)) 1437 return (NULL); 1438 wr->wr_len = wr_len; 1439 wr->wrq = wrq; 1440 return (wr); 1441 } 1442 1443 static inline void * 1444 wrtod(struct wrqe *wr) 1445 { 1446 return (&wr->wr[0]); 1447 } 1448 1449 static inline void 1450 free_wrqe(struct wrqe *wr) 1451 { 1452 free(wr, M_CXGBE); 1453 } 1454 1455 static inline void 1456 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1457 { 1458 struct sge_wrq *wrq = wr->wrq; 1459 1460 TXQ_LOCK(wrq); 1461 t4_wrq_tx_locked(sc, wrq, wr); 1462 TXQ_UNLOCK(wrq); 1463 } 1464 1465 static inline int 1466 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1467 int len) 1468 { 1469 1470 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1471 } 1472 1473 static inline int 1474 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1475 const uint32_t *val, int len) 1476 { 1477 1478 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1479 } 1480 1481 /* Number of len16 -> number of descriptors */ 1482 static inline int 1483 tx_len16_to_desc(int len16) 1484 { 1485 1486 return (howmany(len16, EQ_ESIZE / 16)); 1487 } 1488 #endif 1489