xref: /freebsd/sys/dev/cxgb/common/cxgb_t3_cpl.h (revision 6137b5f7b8c183ee8806d79b3f1d8e5e3ddb3df3)
1 /**************************************************************************
2 SPDX-License-Identifier: BSD-2-Clause
3 
4 Copyright (c) 2007-2009 Chelsio Inc.
5 All rights reserved.
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10  1. Redistributions of source code must retain the above copyright notice,
11     this list of conditions and the following disclaimer.
12 
13  2. Neither the name of the Chelsio Corporation nor the names of its
14     contributors may be used to endorse or promote products derived from
15     this software without specific prior written permission.
16 
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 POSSIBILITY OF SUCH DAMAGE.
28 
29 ***************************************************************************/
30 #ifndef T3_CPL_H
31 #define T3_CPL_H
32 
33 enum CPL_opcode {
34 	CPL_PASS_OPEN_REQ     = 0x1,
35 	CPL_PASS_ACCEPT_RPL   = 0x2,
36 	CPL_ACT_OPEN_REQ      = 0x3,
37 	CPL_SET_TCB           = 0x4,
38 	CPL_SET_TCB_FIELD     = 0x5,
39 	CPL_GET_TCB           = 0x6,
40 	CPL_PCMD              = 0x7,
41 	CPL_CLOSE_CON_REQ     = 0x8,
42 	CPL_CLOSE_LISTSRV_REQ = 0x9,
43 	CPL_ABORT_REQ         = 0xA,
44 	CPL_ABORT_RPL         = 0xB,
45 	CPL_TX_DATA           = 0xC,
46 	CPL_RX_DATA_ACK       = 0xD,
47 	CPL_TX_PKT            = 0xE,
48 	CPL_RTE_DELETE_REQ    = 0xF,
49 	CPL_RTE_WRITE_REQ     = 0x10,
50 	CPL_RTE_READ_REQ      = 0x11,
51 	CPL_L2T_WRITE_REQ     = 0x12,
52 	CPL_L2T_READ_REQ      = 0x13,
53 	CPL_SMT_WRITE_REQ     = 0x14,
54 	CPL_SMT_READ_REQ      = 0x15,
55 	CPL_TX_PKT_LSO        = 0x16,
56 	CPL_PCMD_READ         = 0x17,
57 	CPL_BARRIER           = 0x18,
58 	CPL_TID_RELEASE       = 0x1A,
59 
60 	CPL_CLOSE_LISTSRV_RPL = 0x20,
61 	CPL_ERROR             = 0x21,
62 	CPL_GET_TCB_RPL       = 0x22,
63 	CPL_L2T_WRITE_RPL     = 0x23,
64 	CPL_PCMD_READ_RPL     = 0x24,
65 	CPL_PCMD_RPL          = 0x25,
66 	CPL_PEER_CLOSE        = 0x26,
67 	CPL_RTE_DELETE_RPL    = 0x27,
68 	CPL_RTE_WRITE_RPL     = 0x28,
69 	CPL_RX_DDP_COMPLETE   = 0x29,
70 	CPL_RX_PHYS_ADDR      = 0x2A,
71 	CPL_RX_PKT            = 0x2B,
72 	CPL_RX_URG_NOTIFY     = 0x2C,
73 	CPL_SET_TCB_RPL       = 0x2D,
74 	CPL_SMT_WRITE_RPL     = 0x2E,
75 	CPL_TX_DATA_ACK       = 0x2F,
76 
77 	CPL_ABORT_REQ_RSS     = 0x30,
78 	CPL_ABORT_RPL_RSS     = 0x31,
79 	CPL_CLOSE_CON_RPL     = 0x32,
80 	CPL_ISCSI_HDR         = 0x33,
81 	CPL_L2T_READ_RPL      = 0x34,
82 	CPL_RDMA_CQE          = 0x35,
83 	CPL_RDMA_CQE_READ_RSP = 0x36,
84 	CPL_RDMA_CQE_ERR      = 0x37,
85 	CPL_RTE_READ_RPL      = 0x38,
86 	CPL_RX_DATA           = 0x39,
87 
88 	CPL_ACT_OPEN_RPL      = 0x40,
89 	CPL_PASS_OPEN_RPL     = 0x41,
90 	CPL_RX_DATA_DDP       = 0x42,
91 	CPL_SMT_READ_RPL      = 0x43,
92 
93 	CPL_ACT_ESTABLISH     = 0x50,
94 	CPL_PASS_ESTABLISH    = 0x51,
95 
96 	CPL_PASS_ACCEPT_REQ   = 0x70,
97 
98 	CPL_ASYNC_NOTIF       = 0x80, /* fake opcode for async notifications */
99 
100 	CPL_TX_DMA_ACK        = 0xA0,
101 	CPL_RDMA_READ_REQ     = 0xA1,
102 	CPL_RDMA_TERMINATE    = 0xA2,
103 	CPL_TRACE_PKT         = 0xA3,
104 	CPL_RDMA_EC_STATUS    = 0xA5,
105 	CPL_SGE_EC_CR_RETURN  = 0xA6,
106 
107 	NUM_CPL_CMDS    /* must be last and previous entries must be sorted */
108 };
109 
110 enum CPL_error {
111 	CPL_ERR_NONE               = 0,
112 	CPL_ERR_TCAM_PARITY        = 1,
113 	CPL_ERR_TCAM_FULL          = 3,
114 	CPL_ERR_CONN_RESET         = 20,
115 	CPL_ERR_CONN_EXIST         = 22,
116 	CPL_ERR_ARP_MISS           = 23,
117 	CPL_ERR_BAD_SYN            = 24,
118 	CPL_ERR_CONN_TIMEDOUT      = 30,
119 	CPL_ERR_XMIT_TIMEDOUT      = 31,
120 	CPL_ERR_PERSIST_TIMEDOUT   = 32,
121 	CPL_ERR_FINWAIT2_TIMEDOUT  = 33,
122 	CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
123 	CPL_ERR_RTX_NEG_ADVICE     = 35,
124 	CPL_ERR_PERSIST_NEG_ADVICE = 36,
125 	CPL_ERR_ABORT_FAILED       = 42,
126 	CPL_ERR_GENERAL            = 99
127 };
128 
129 enum {
130 	CPL_CONN_POLICY_AUTO = 0,
131 	CPL_CONN_POLICY_ASK  = 1,
132 	CPL_CONN_POLICY_FILTER = 2,
133 	CPL_CONN_POLICY_DENY = 3
134 };
135 
136 enum {
137 	ULP_MODE_NONE          = 0,
138 	ULP_MODE_TCP_DDP       = 1,
139 	ULP_MODE_ISCSI         = 2,
140 	ULP_MODE_RDMA          = 4,
141 	ULP_MODE_TCPDDP        = 5
142 };
143 
144 enum {
145 	ULP_CRC_HEADER = 1 << 0,
146 	ULP_CRC_DATA   = 1 << 1
147 };
148 
149 enum {
150 	CPL_PASS_OPEN_ACCEPT,
151 	CPL_PASS_OPEN_REJECT,
152 	CPL_PASS_OPEN_ACCEPT_TNL
153 };
154 
155 enum {
156 	CPL_ABORT_SEND_RST = 0,
157 	CPL_ABORT_NO_RST,
158 	CPL_ABORT_POST_CLOSE_REQ = 2
159 };
160 
161 enum {                     /* TX_PKT_LSO ethernet types */
162 	CPL_ETH_II,
163 	CPL_ETH_II_VLAN,
164 	CPL_ETH_802_3,
165 	CPL_ETH_802_3_VLAN
166 };
167 
168 enum {                     /* TCP congestion control algorithms */
169 	CONG_ALG_RENO,
170 	CONG_ALG_TAHOE,
171 	CONG_ALG_NEWRENO,
172 	CONG_ALG_HIGHSPEED
173 };
174 
175 enum {                     /* RSS hash type */
176 	RSS_HASH_NONE = 0,
177 	RSS_HASH_2_TUPLE = 1,
178 	RSS_HASH_4_TUPLE = 2,
179 	RSS_HASH_TCPV6 = 3
180 };
181 
182 union opcode_tid {
183 	__be32 opcode_tid;
184 	__u8 opcode;
185 };
186 
187 #define S_OPCODE 24
188 #define V_OPCODE(x) ((x) << S_OPCODE)
189 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
190 #define G_TID(x)    ((x) & 0xFFFFFF)
191 
192 /* tid is assumed to be 24-bits */
193 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
194 
195 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
196 
197 /* extract the TID from a CPL command */
198 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
199 
200 struct tcp_options {
201 	__be16 mss;
202 	__u8 wsf;
203 #if defined(__LITTLE_ENDIAN_BITFIELD)
204 	__u8 :5;
205 	__u8 ecn:1;
206 	__u8 sack:1;
207 	__u8 tstamp:1;
208 #else
209 	__u8 tstamp:1;
210 	__u8 sack:1;
211 	__u8 ecn:1;
212 	__u8 :5;
213 #endif
214 };
215 
216 struct rss_header {
217 	__u8 opcode;
218 #if defined(__LITTLE_ENDIAN_BITFIELD)
219 	__u8 cpu_idx:6;
220 	__u8 hash_type:2;
221 #else
222 	__u8 hash_type:2;
223 	__u8 cpu_idx:6;
224 #endif
225 	__be16 cq_idx;
226 	__be32 rss_hash_val;
227 };
228 
229 #define S_HASHTYPE 22
230 #define M_HASHTYPE 0x3
231 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
232 
233 #define S_QNUM 0
234 #define M_QNUM 0xFFFF
235 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
236 
237 #ifndef CHELSIO_FW
238 struct work_request_hdr {
239 	union {
240 		struct {
241 			__be32 wr_hi;
242 			__be32 wr_lo;
243 		} ilp32;
244 		struct {
245 			__be64 wr_hilo;
246 		} lp64;
247 	} u;
248 };
249 
250 #define	wrh_hi		u.ilp32.wr_hi
251 #define	wrh_lo		u.ilp32.wr_lo
252 #define	wrh_hilo	u.lp64.wr_hilo
253 
254 /* wr_hi fields */
255 #define S_WR_SGE_CREDITS    0
256 #define M_WR_SGE_CREDITS    0xFF
257 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
258 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)
259 
260 #define S_WR_SGLSFLT    8
261 #define M_WR_SGLSFLT    0xFF
262 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
263 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)
264 
265 #define S_WR_BCNTLFLT    16
266 #define M_WR_BCNTLFLT    0xF
267 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
268 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
269 
270 /*
271  * Applicable to BYPASS WRs only: the uP will add a CPL_BARRIER before
272  * and after the BYPASS WR if the ATOMIC bit is set.
273  */
274 #define S_WR_ATOMIC	16
275 #define V_WR_ATOMIC(x)	((x) << S_WR_ATOMIC)
276 #define F_WR_ATOMIC	V_WR_ATOMIC(1U)
277 
278 /*
279  * Applicable to BYPASS WRs only: the uP will flush buffered non abort
280  * related WRs.
281  */
282 #define S_WR_FLUSH	17
283 #define V_WR_FLUSH(x)	((x) << S_WR_FLUSH)
284 #define F_WR_FLUSH	V_WR_FLUSH(1U)
285 
286 #define S_WR_CHN	18
287 #define V_WR_CHN(x)	((x) << S_WR_CHN)
288 #define F_WR_CHN	V_WR_CHN(1U)
289 
290 #define S_WR_CHN_VLD	19
291 #define V_WR_CHN_VLD(x)	((x) << S_WR_CHN_VLD)
292 #define F_WR_CHN_VLD	V_WR_CHN_VLD(1U)
293 
294 #define S_WR_DATATYPE    20
295 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
296 #define F_WR_DATATYPE    V_WR_DATATYPE(1U)
297 
298 #define S_WR_COMPL    21
299 #define V_WR_COMPL(x) ((x) << S_WR_COMPL)
300 #define F_WR_COMPL    V_WR_COMPL(1U)
301 
302 #define S_WR_EOP    22
303 #define V_WR_EOP(x) ((x) << S_WR_EOP)
304 #define F_WR_EOP    V_WR_EOP(1U)
305 
306 #define S_WR_SOP    23
307 #define V_WR_SOP(x) ((x) << S_WR_SOP)
308 #define F_WR_SOP    V_WR_SOP(1U)
309 
310 #define S_WR_OP    24
311 #define M_WR_OP    0xFF
312 #define V_WR_OP(x) ((x) << S_WR_OP)
313 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
314 
315 /* wr_lo fields */
316 #define S_WR_LEN    0
317 #define M_WR_LEN    0xFF
318 #define V_WR_LEN(x) ((x) << S_WR_LEN)
319 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)
320 
321 #define S_WR_TID    8
322 #define M_WR_TID    0xFFFFF
323 #define V_WR_TID(x) ((x) << S_WR_TID)
324 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)
325 
326 #define S_WR_CR_FLUSH    30
327 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
328 #define F_WR_CR_FLUSH    V_WR_CR_FLUSH(1U)
329 
330 #define S_WR_GEN    31
331 #define V_WR_GEN(x) ((x) << S_WR_GEN)
332 #define F_WR_GEN    V_WR_GEN(1U)
333 #define G_WR_GEN(x) ((x) >> S_WR_GEN)
334 
335 # define WR_HDR struct work_request_hdr wr
336 # define RSS_HDR
337 #else
338 # define WR_HDR
339 # define RSS_HDR struct rss_header rss_hdr;
340 #endif
341 
342 /* option 0 lower-half fields */
343 #define S_CPL_STATUS    0
344 #define M_CPL_STATUS    0xFF
345 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
346 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)
347 
348 #define S_INJECT_TIMER    6
349 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
350 #define F_INJECT_TIMER    V_INJECT_TIMER(1U)
351 
352 #define S_NO_OFFLOAD    7
353 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
354 #define F_NO_OFFLOAD    V_NO_OFFLOAD(1U)
355 
356 #define S_ULP_MODE    8
357 #define M_ULP_MODE    0xF
358 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
359 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
360 
361 #define S_RCV_BUFSIZ    12
362 #define M_RCV_BUFSIZ    0x3FFF
363 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
364 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
365 
366 #define S_TOS    26
367 #define M_TOS    0x3F
368 #define V_TOS(x) ((x) << S_TOS)
369 #define G_TOS(x) (((x) >> S_TOS) & M_TOS)
370 
371 /* option 0 upper-half fields */
372 #define S_DELACK    0
373 #define V_DELACK(x) ((x) << S_DELACK)
374 #define F_DELACK    V_DELACK(1U)
375 
376 #define S_NO_CONG    1
377 #define V_NO_CONG(x) ((x) << S_NO_CONG)
378 #define F_NO_CONG    V_NO_CONG(1U)
379 
380 #define S_SRC_MAC_SEL    2
381 #define M_SRC_MAC_SEL    0x3
382 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
383 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)
384 
385 #define S_L2T_IDX    4
386 #define M_L2T_IDX    0x7FF
387 #define V_L2T_IDX(x) ((x) << S_L2T_IDX)
388 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
389 
390 #define S_TX_CHANNEL    15
391 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
392 #define F_TX_CHANNEL    V_TX_CHANNEL(1U)
393 
394 #define S_TCAM_BYPASS    16
395 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
396 #define F_TCAM_BYPASS    V_TCAM_BYPASS(1U)
397 
398 #define S_NAGLE    17
399 #define V_NAGLE(x) ((x) << S_NAGLE)
400 #define F_NAGLE    V_NAGLE(1U)
401 
402 #define S_WND_SCALE    18
403 #define M_WND_SCALE    0xF
404 #define V_WND_SCALE(x) ((x) << S_WND_SCALE)
405 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
406 
407 #define S_KEEP_ALIVE    22
408 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
409 #define F_KEEP_ALIVE    V_KEEP_ALIVE(1U)
410 
411 #define S_MAX_RETRANS    23
412 #define M_MAX_RETRANS    0xF
413 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
414 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)
415 
416 #define S_MAX_RETRANS_OVERRIDE    27
417 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
418 #define F_MAX_RETRANS_OVERRIDE    V_MAX_RETRANS_OVERRIDE(1U)
419 
420 #define S_MSS_IDX    28
421 #define M_MSS_IDX    0xF
422 #define V_MSS_IDX(x) ((x) << S_MSS_IDX)
423 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
424 
425 /* option 1 fields */
426 #define S_RSS_ENABLE    0
427 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
428 #define F_RSS_ENABLE    V_RSS_ENABLE(1U)
429 
430 #define S_RSS_MASK_LEN    1
431 #define M_RSS_MASK_LEN    0x7
432 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
433 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
434 
435 #define S_CPU_IDX    4
436 #define M_CPU_IDX    0x3F
437 #define V_CPU_IDX(x) ((x) << S_CPU_IDX)
438 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
439 
440 #define S_OPT1_VLAN    6
441 #define M_OPT1_VLAN    0xFFF
442 #define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN)
443 #define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN)
444 
445 #define S_MAC_MATCH_VALID    18
446 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
447 #define F_MAC_MATCH_VALID    V_MAC_MATCH_VALID(1U)
448 
449 #define S_CONN_POLICY    19
450 #define M_CONN_POLICY    0x3
451 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
452 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
453 
454 #define S_SYN_DEFENSE    21
455 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
456 #define F_SYN_DEFENSE    V_SYN_DEFENSE(1U)
457 
458 #define S_VLAN_PRI    22
459 #define M_VLAN_PRI    0x3
460 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
461 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)
462 
463 #define S_VLAN_PRI_VALID    24
464 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
465 #define F_VLAN_PRI_VALID    V_VLAN_PRI_VALID(1U)
466 
467 #define S_PKT_TYPE    25
468 #define M_PKT_TYPE    0x3
469 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
470 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)
471 
472 #define S_MAC_MATCH    27
473 #define M_MAC_MATCH    0x1F
474 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
475 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)
476 
477 /* option 2 fields */
478 #define S_CPU_INDEX    0
479 #define M_CPU_INDEX    0x7F
480 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
481 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)
482 
483 #define S_CPU_INDEX_VALID    7
484 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
485 #define F_CPU_INDEX_VALID    V_CPU_INDEX_VALID(1U)
486 
487 #define S_RX_COALESCE    8
488 #define M_RX_COALESCE    0x3
489 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
490 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
491 
492 #define S_RX_COALESCE_VALID    10
493 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
494 #define F_RX_COALESCE_VALID    V_RX_COALESCE_VALID(1U)
495 
496 #define S_CONG_CONTROL_FLAVOR    11
497 #define M_CONG_CONTROL_FLAVOR    0x3
498 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
499 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)
500 
501 #define S_PACING_FLAVOR    13
502 #define M_PACING_FLAVOR    0x3
503 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
504 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)
505 
506 #define S_FLAVORS_VALID    15
507 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
508 #define F_FLAVORS_VALID    V_FLAVORS_VALID(1U)
509 
510 #define S_RX_FC_DISABLE    16
511 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
512 #define F_RX_FC_DISABLE    V_RX_FC_DISABLE(1U)
513 
514 #define S_RX_FC_VALID    17
515 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
516 #define F_RX_FC_VALID    V_RX_FC_VALID(1U)
517 
518 struct cpl_pass_open_req {
519 	WR_HDR;
520 	union opcode_tid ot;
521 	__be16 local_port;
522 	__be16 peer_port;
523 	__be32 local_ip;
524 	__be32 peer_ip;
525 	__be32 opt0h;
526 	__be32 opt0l;
527 	__be32 peer_netmask;
528 	__be32 opt1;
529 };
530 
531 struct cpl_pass_open_rpl {
532 	RSS_HDR
533 	union opcode_tid ot;
534 	__be16 local_port;
535 	__be16 peer_port;
536 	__be32 local_ip;
537 	__be32 peer_ip;
538 	__u8 resvd[7];
539 	__u8 status;
540 };
541 
542 struct cpl_pass_establish {
543 	RSS_HDR
544 	union opcode_tid ot;
545 	__be16 local_port;
546 	__be16 peer_port;
547 	__be32 local_ip;
548 	__be32 peer_ip;
549 	__be32 tos_tid;
550 	__be16 l2t_idx;
551 	__be16 tcp_opt;
552 	__be32 snd_isn;
553 	__be32 rcv_isn;
554 };
555 
556 /* cpl_pass_establish.tos_tid fields */
557 #define S_PASS_OPEN_TID    0
558 #define M_PASS_OPEN_TID    0xFFFFFF
559 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
560 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
561 
562 #define S_PASS_OPEN_TOS    24
563 #define M_PASS_OPEN_TOS    0xFF
564 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
565 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
566 
567 /* cpl_pass_establish.l2t_idx fields */
568 #define S_L2T_IDX16    5
569 #define M_L2T_IDX16    0x7FF
570 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16)
571 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16)
572 
573 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */
574 #define G_TCPOPT_WSCALE_OK(x)  (((x) >> 5) & 1)
575 #define G_TCPOPT_SACK(x)       (((x) >> 6) & 1)
576 #define G_TCPOPT_TSTAMP(x)     (((x) >> 7) & 1)
577 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
578 #define G_TCPOPT_MSS(x)        (((x) >> 12) & 0xf)
579 
580 struct cpl_pass_accept_req {
581 	RSS_HDR
582 	union opcode_tid ot;
583 	__be16 local_port;
584 	__be16 peer_port;
585 	__be32 local_ip;
586 	__be32 peer_ip;
587 	__be32 tos_tid;
588 	struct tcp_options tcp_options;
589 	__u8  dst_mac[6];
590 	__be16 vlan_tag;
591 	__u8  src_mac[6];
592 #if defined(__LITTLE_ENDIAN_BITFIELD)
593 	__u8  :3;
594 	__u8  addr_idx:3;
595 	__u8  port_idx:1;
596 	__u8  exact_match:1;
597 #else
598 	__u8  exact_match:1;
599 	__u8  port_idx:1;
600 	__u8  addr_idx:3;
601 	__u8  :3;
602 #endif
603 	__u8  rsvd;
604 	__be32 rcv_isn;
605 	__be32 rsvd2;
606 };
607 
608 struct cpl_pass_accept_rpl {
609 	WR_HDR;
610 	union opcode_tid ot;
611 	__be32 opt2;
612 	__be32 rsvd;
613 	__be32 peer_ip;
614 	__be32 opt0h;
615 	__be32 opt0l_status;
616 };
617 
618 struct cpl_act_open_req {
619 	WR_HDR;
620 	union opcode_tid ot;
621 	__be16 local_port;
622 	__be16 peer_port;
623 	__be32 local_ip;
624 	__be32 peer_ip;
625 	__be32 opt0h;
626 	__be32 opt0l;
627 	__be32 params;
628 	__be32 opt2;
629 };
630 
631 /* cpl_act_open_req.params fields */
632 #define S_AOPEN_VLAN_PRI    9
633 #define M_AOPEN_VLAN_PRI    0x3
634 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
635 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
636 
637 #define S_AOPEN_VLAN_PRI_VALID    11
638 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
639 #define F_AOPEN_VLAN_PRI_VALID    V_AOPEN_VLAN_PRI_VALID(1U)
640 
641 #define S_AOPEN_PKT_TYPE    12
642 #define M_AOPEN_PKT_TYPE    0x3
643 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
644 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
645 
646 #define S_AOPEN_MAC_MATCH    14
647 #define M_AOPEN_MAC_MATCH    0x1F
648 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
649 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
650 
651 #define S_AOPEN_MAC_MATCH_VALID    19
652 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
653 #define F_AOPEN_MAC_MATCH_VALID    V_AOPEN_MAC_MATCH_VALID(1U)
654 
655 #define S_AOPEN_IFF_VLAN    20
656 #define M_AOPEN_IFF_VLAN    0xFFF
657 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
658 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
659 
660 struct cpl_act_open_rpl {
661 	RSS_HDR
662 	union opcode_tid ot;
663 	__be16 local_port;
664 	__be16 peer_port;
665 	__be32 local_ip;
666 	__be32 peer_ip;
667 	__be32 atid;
668 	__u8  rsvd[3];
669 	__u8  status;
670 };
671 
672 struct cpl_act_establish {
673 	RSS_HDR
674 	union opcode_tid ot;
675 	__be16 local_port;
676 	__be16 peer_port;
677 	__be32 local_ip;
678 	__be32 peer_ip;
679 	__be32 tos_tid;
680 	__be16 l2t_idx;
681 	__be16 tcp_opt;
682 	__be32 snd_isn;
683 	__be32 rcv_isn;
684 };
685 
686 struct cpl_get_tcb {
687 	WR_HDR;
688 	union opcode_tid ot;
689 	__be16 cpuno;
690 	__be16 rsvd;
691 };
692 
693 struct cpl_get_tcb_rpl {
694 	RSS_HDR
695 	union opcode_tid ot;
696 	__u8 rsvd;
697 	__u8 status;
698 	__be16 len;
699 };
700 
701 struct cpl_set_tcb {
702 	WR_HDR;
703 	union opcode_tid ot;
704 	__u8  reply;
705 	__u8  cpu_idx;
706 	__be16 len;
707 };
708 
709 /* cpl_set_tcb.reply fields */
710 #define S_NO_REPLY    7
711 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
712 #define F_NO_REPLY    V_NO_REPLY(1U)
713 
714 struct cpl_set_tcb_field {
715 	WR_HDR;
716 	union opcode_tid ot;
717 	__u8  reply;
718 	__u8  cpu_idx;
719 	__be16 word;
720 	__be64 mask;
721 	__be64 val;
722 };
723 
724 struct cpl_set_tcb_rpl {
725 	RSS_HDR
726 	union opcode_tid ot;
727 	__u8 rsvd[3];
728 	__u8 status;
729 };
730 
731 struct cpl_pcmd {
732 	WR_HDR;
733 	union opcode_tid ot;
734 	__u8 rsvd[3];
735 #if defined(__LITTLE_ENDIAN_BITFIELD)
736 	__u8 src:1;
737 	__u8 bundle:1;
738 	__u8 channel:1;
739 	__u8 :5;
740 #else
741 	__u8 :5;
742 	__u8 channel:1;
743 	__u8 bundle:1;
744 	__u8 src:1;
745 #endif
746 	__be32 pcmd_parm[2];
747 };
748 
749 struct cpl_pcmd_reply {
750 	RSS_HDR
751 	union opcode_tid ot;
752 	__u8  status;
753 	__u8  rsvd;
754 	__be16 len;
755 };
756 
757 struct cpl_close_con_req {
758 	WR_HDR;
759 	union opcode_tid ot;
760 	__be32 rsvd;
761 };
762 
763 struct cpl_close_con_rpl {
764 	RSS_HDR
765 	union opcode_tid ot;
766 	__u8  rsvd[3];
767 	__u8  status;
768 	__be32 snd_nxt;
769 	__be32 rcv_nxt;
770 };
771 
772 struct cpl_close_listserv_req {
773 	WR_HDR;
774 	union opcode_tid ot;
775 	__u8  rsvd0;
776 	__u8  cpu_idx;
777 	__be16 rsvd1;
778 };
779 
780 struct cpl_close_listserv_rpl {
781 	RSS_HDR
782 	union opcode_tid ot;
783 	__u8 rsvd[3];
784 	__u8 status;
785 };
786 
787 struct cpl_abort_req_rss {
788 	RSS_HDR
789 	union opcode_tid ot;
790 	__be32 rsvd0;
791 	__u8  rsvd1;
792 	__u8  status;
793 	__u8  rsvd2[6];
794 };
795 
796 struct cpl_abort_req {
797 	WR_HDR;
798 	union opcode_tid ot;
799 	__be32 rsvd0;
800 	__u8  rsvd1;
801 	__u8  cmd;
802 	__u8  rsvd2[6];
803 };
804 
805 struct cpl_abort_rpl_rss {
806 	RSS_HDR
807 	union opcode_tid ot;
808 	__be32 rsvd0;
809 	__u8  rsvd1;
810 	__u8  status;
811 	__u8  rsvd2[6];
812 };
813 
814 struct cpl_abort_rpl {
815 	WR_HDR;
816 	union opcode_tid ot;
817 	__be32 rsvd0;
818 	__u8  rsvd1;
819 	__u8  cmd;
820 	__u8  rsvd2[6];
821 };
822 
823 struct cpl_peer_close {
824 	RSS_HDR
825 	union opcode_tid ot;
826 	__be32 rcv_nxt;
827 };
828 
829 struct tx_data_wr {
830 	WR_HDR;
831 	__be32 len;
832 	__be32 flags;
833 	__be32 sndseq;
834 	__be32 param;
835 };
836 
837 /* tx_data_wr.flags fields */
838 #define S_TX_ACK_PAGES		21
839 #define M_TX_ACK_PAGES		0x7
840 #define V_TX_ACK_PAGES(x) 	((x) << S_TX_ACK_PAGES)
841 #define G_TX_ACK_PAGES(x) 	(((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
842 
843 /* tx_data_wr.param fields */
844 #define S_TX_PORT    0
845 #define M_TX_PORT    0x7
846 #define V_TX_PORT(x) ((x) << S_TX_PORT)
847 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
848 
849 #define S_TX_MSS    4
850 #define M_TX_MSS    0xF
851 #define V_TX_MSS(x) ((x) << S_TX_MSS)
852 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
853 
854 #define S_TX_QOS    8
855 #define M_TX_QOS    0xFF
856 #define V_TX_QOS(x) ((x) << S_TX_QOS)
857 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
858 
859 #define S_TX_SNDBUF 16
860 #define M_TX_SNDBUF 0xFFFF
861 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
862 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
863 
864 struct cpl_tx_data {
865 	union opcode_tid ot;
866 	__be32 len;
867 	__be32 rsvd;
868 	__be16 urg;
869 	__be16 flags;
870 };
871 
872 /* cpl_tx_data.flags fields */
873 #define S_TX_ULP_SUBMODE    6
874 #define M_TX_ULP_SUBMODE    0xF
875 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
876 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
877 
878 #define S_TX_ULP_MODE    10
879 #define M_TX_ULP_MODE    0xF
880 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
881 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
882 
883 #define S_TX_SHOVE    14
884 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
885 #define F_TX_SHOVE    V_TX_SHOVE(1U)
886 
887 #define S_TX_MORE    15
888 #define V_TX_MORE(x) ((x) << S_TX_MORE)
889 #define F_TX_MORE    V_TX_MORE(1U)
890 
891 /* additional tx_data_wr.flags fields */
892 #define S_TX_CPU_IDX    0
893 #define M_TX_CPU_IDX    0x3F
894 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
895 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
896 
897 #define S_TX_URG    16
898 #define V_TX_URG(x) ((x) << S_TX_URG)
899 #define F_TX_URG    V_TX_URG(1U)
900 
901 #define S_TX_CLOSE    17
902 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
903 #define F_TX_CLOSE    V_TX_CLOSE(1U)
904 
905 #define S_TX_INIT    18
906 #define V_TX_INIT(x) ((x) << S_TX_INIT)
907 #define F_TX_INIT    V_TX_INIT(1U)
908 
909 #define S_TX_IMM_ACK    19
910 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
911 #define F_TX_IMM_ACK    V_TX_IMM_ACK(1U)
912 
913 #define S_TX_IMM_DMA    20
914 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
915 #define F_TX_IMM_DMA    V_TX_IMM_DMA(1U)
916 
917 struct cpl_tx_data_ack {
918 	RSS_HDR
919 	union opcode_tid ot;
920 	__be32 ack_seq;
921 };
922 
923 struct cpl_wr_ack {
924 	RSS_HDR
925 	union opcode_tid ot;
926 	__be16 credits;
927 	__be16 rsvd;
928 	__be32 snd_nxt;
929 	__be32 snd_una;
930 };
931 
932 struct cpl_sge_ec_cr_return {
933 	RSS_HDR
934 	union opcode_tid ot;
935 	__be16 sge_ec_id;
936 	__u8 cr;
937 	__u8 rsvd;
938 };
939 
940 struct cpl_rdma_ec_status {
941 	RSS_HDR
942 	union opcode_tid ot;
943 	__u8  rsvd[3];
944 	__u8  status;
945 };
946 
947 struct mngt_pktsched_wr {
948 	WR_HDR;
949 	__u8  mngt_opcode;
950 	__u8  rsvd[7];
951 	__u8  sched;
952 	__u8  idx;
953 	__u8  min;
954 	__u8  max;
955 	__u8  binding;
956 	__u8  rsvd1[3];
957 };
958 
959 struct cpl_iscsi_hdr {
960 	RSS_HDR
961 	union opcode_tid ot;
962 	__be16 pdu_len_ddp;
963 	__be16 len;
964 	__be32 seq;
965 	__be16 urg;
966 	__u8  rsvd;
967 	__u8  status;
968 };
969 
970 /* cpl_iscsi_hdr.pdu_len_ddp fields */
971 #define S_ISCSI_PDU_LEN    0
972 #define M_ISCSI_PDU_LEN    0x7FFF
973 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
974 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
975 
976 #define S_ISCSI_DDP    15
977 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
978 #define F_ISCSI_DDP    V_ISCSI_DDP(1U)
979 
980 struct cpl_rx_data {
981 	RSS_HDR
982 	union opcode_tid ot;
983 	__be16 rsvd;
984 	__be16 len;
985 	__be32 seq;
986 	__be16 urg;
987 #if defined(__LITTLE_ENDIAN_BITFIELD)
988 	__u8  dack_mode:2;
989 	__u8  psh:1;
990 	__u8  heartbeat:1;
991 	__u8  ddp_off:1;
992 	__u8  :3;
993 #else
994 	__u8  :3;
995 	__u8  ddp_off:1;
996 	__u8  heartbeat:1;
997 	__u8  psh:1;
998 	__u8  dack_mode:2;
999 #endif
1000 	__u8  status;
1001 };
1002 
1003 struct cpl_rx_data_ack {
1004 	WR_HDR;
1005 	union opcode_tid ot;
1006 	__be32 credit_dack;
1007 };
1008 
1009 /* cpl_rx_data_ack.ack_seq fields */
1010 #define S_RX_CREDITS    0
1011 #define M_RX_CREDITS    0x7FFFFFF
1012 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
1013 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
1014 
1015 #define S_RX_MODULATE    27
1016 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE)
1017 #define F_RX_MODULATE    V_RX_MODULATE(1U)
1018 
1019 #define S_RX_FORCE_ACK    28
1020 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
1021 #define F_RX_FORCE_ACK    V_RX_FORCE_ACK(1U)
1022 
1023 #define S_RX_DACK_MODE    29
1024 #define M_RX_DACK_MODE    0x3
1025 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
1026 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
1027 
1028 #define S_RX_DACK_CHANGE    31
1029 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
1030 #define F_RX_DACK_CHANGE    V_RX_DACK_CHANGE(1U)
1031 
1032 struct cpl_rx_urg_notify {
1033 	RSS_HDR
1034 	union opcode_tid ot;
1035 	__be32 seq;
1036 };
1037 
1038 struct cpl_rx_ddp_complete {
1039 	RSS_HDR
1040 	union opcode_tid ot;
1041 	__be32 ddp_report;
1042 };
1043 
1044 struct cpl_rx_data_ddp {
1045 	RSS_HDR
1046 	union opcode_tid ot;
1047 	__be16 urg;
1048 	__be16 len;
1049 	__be32 seq;
1050 	union {
1051 		__be32 nxt_seq;
1052 		__be32 ddp_report;
1053 	} u;
1054 	__be32 ulp_crc;
1055 	__be32 ddpvld_status;
1056 };
1057 
1058 /* cpl_rx_data_ddp.ddpvld_status fields */
1059 #define S_DDP_STATUS    0
1060 #define M_DDP_STATUS    0xFF
1061 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
1062 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS)
1063 
1064 #define S_DDP_VALID    15
1065 #define M_DDP_VALID    0x1FFFF
1066 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
1067 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
1068 
1069 #define S_DDP_PPOD_MISMATCH    15
1070 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1071 #define F_DDP_PPOD_MISMATCH    V_DDP_PPOD_MISMATCH(1U)
1072 
1073 #define S_DDP_PDU    16
1074 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1075 #define F_DDP_PDU    V_DDP_PDU(1U)
1076 
1077 #define S_DDP_LLIMIT_ERR    17
1078 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1079 #define F_DDP_LLIMIT_ERR    V_DDP_LLIMIT_ERR(1U)
1080 
1081 #define S_DDP_PPOD_PARITY_ERR    18
1082 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1083 #define F_DDP_PPOD_PARITY_ERR    V_DDP_PPOD_PARITY_ERR(1U)
1084 
1085 #define S_DDP_PADDING_ERR    19
1086 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1087 #define F_DDP_PADDING_ERR    V_DDP_PADDING_ERR(1U)
1088 
1089 #define S_DDP_HDRCRC_ERR    20
1090 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1091 #define F_DDP_HDRCRC_ERR    V_DDP_HDRCRC_ERR(1U)
1092 
1093 #define S_DDP_DATACRC_ERR    21
1094 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1095 #define F_DDP_DATACRC_ERR    V_DDP_DATACRC_ERR(1U)
1096 
1097 #define S_DDP_INVALID_TAG    22
1098 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1099 #define F_DDP_INVALID_TAG    V_DDP_INVALID_TAG(1U)
1100 
1101 #define S_DDP_ULIMIT_ERR    23
1102 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1103 #define F_DDP_ULIMIT_ERR    V_DDP_ULIMIT_ERR(1U)
1104 
1105 #define S_DDP_OFFSET_ERR    24
1106 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1107 #define F_DDP_OFFSET_ERR    V_DDP_OFFSET_ERR(1U)
1108 
1109 #define S_DDP_COLOR_ERR    25
1110 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1111 #define F_DDP_COLOR_ERR    V_DDP_COLOR_ERR(1U)
1112 
1113 #define S_DDP_TID_MISMATCH    26
1114 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1115 #define F_DDP_TID_MISMATCH    V_DDP_TID_MISMATCH(1U)
1116 
1117 #define S_DDP_INVALID_PPOD    27
1118 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1119 #define F_DDP_INVALID_PPOD    V_DDP_INVALID_PPOD(1U)
1120 
1121 #define S_DDP_ULP_MODE    28
1122 #define M_DDP_ULP_MODE    0xF
1123 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1124 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1125 
1126 /* cpl_rx_data_ddp.ddp_report fields */
1127 #define S_DDP_OFFSET    0
1128 #define M_DDP_OFFSET    0x3FFFFF
1129 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1130 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1131 
1132 #define S_DDP_DACK_MODE    22
1133 #define M_DDP_DACK_MODE    0x3
1134 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
1135 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE)
1136 
1137 #define S_DDP_URG    24
1138 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1139 #define F_DDP_URG    V_DDP_URG(1U)
1140 
1141 #define S_DDP_PSH    25
1142 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1143 #define F_DDP_PSH    V_DDP_PSH(1U)
1144 
1145 #define S_DDP_BUF_COMPLETE    26
1146 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1147 #define F_DDP_BUF_COMPLETE    V_DDP_BUF_COMPLETE(1U)
1148 
1149 #define S_DDP_BUF_TIMED_OUT    27
1150 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1151 #define F_DDP_BUF_TIMED_OUT    V_DDP_BUF_TIMED_OUT(1U)
1152 
1153 #define S_DDP_BUF_IDX    28
1154 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1155 #define F_DDP_BUF_IDX    V_DDP_BUF_IDX(1U)
1156 
1157 struct cpl_tx_pkt {
1158 	WR_HDR;
1159 	__be32 cntrl;
1160 	__be32 len;
1161 };
1162 
1163 struct cpl_tx_pkt_coalesce {
1164 	__be32 cntrl;
1165 	__be32 len;
1166 	__be64 addr;
1167 };
1168 
1169 struct tx_pkt_coalesce_wr {
1170 	WR_HDR;
1171 	struct cpl_tx_pkt_coalesce cpl[0];
1172 };
1173 
1174 struct cpl_tx_pkt_lso {
1175 	WR_HDR;
1176 	__be32 cntrl;
1177 	__be32 len;
1178 
1179 	__be32 rsvd;
1180 	__be32 lso_info;
1181 };
1182 
1183 struct cpl_tx_pkt_batch_entry {
1184 	__be32 cntrl;
1185 	__be32 len;
1186 	__be64 addr;
1187 };
1188 
1189 struct cpl_tx_pkt_batch {
1190 	WR_HDR;
1191 	struct cpl_tx_pkt_batch_entry pkt_entry[7];
1192 };
1193 
1194 
1195 /* cpl_tx_pkt*.cntrl fields */
1196 #define S_TXPKT_VLAN    0
1197 #define M_TXPKT_VLAN    0xFFFF
1198 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN)
1199 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1200 
1201 #define S_TXPKT_INTF    16
1202 #define M_TXPKT_INTF    0xF
1203 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1204 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1205 
1206 #define S_TXPKT_IPCSUM_DIS    20
1207 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS)
1208 #define F_TXPKT_IPCSUM_DIS    V_TXPKT_IPCSUM_DIS(1U)
1209 
1210 #define S_TXPKT_L4CSUM_DIS    21
1211 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS)
1212 #define F_TXPKT_L4CSUM_DIS    V_TXPKT_L4CSUM_DIS(1U)
1213 
1214 #define S_TXPKT_VLAN_VLD    22
1215 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD)
1216 #define F_TXPKT_VLAN_VLD    V_TXPKT_VLAN_VLD(1U)
1217 
1218 #define S_TXPKT_LOOPBACK    23
1219 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1220 #define F_TXPKT_LOOPBACK    V_TXPKT_LOOPBACK(1U)
1221 
1222 #define S_TXPKT_OPCODE    24
1223 #define M_TXPKT_OPCODE    0xFF
1224 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1225 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1226 
1227 /* cpl_tx_pkt_lso.lso_info fields */
1228 #define S_LSO_MSS    0
1229 #define M_LSO_MSS    0x3FFF
1230 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1231 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1232 
1233 #define S_LSO_ETH_TYPE    14
1234 #define M_LSO_ETH_TYPE    0x3
1235 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE)
1236 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE)
1237 
1238 #define S_LSO_TCPHDR_WORDS    16
1239 #define M_LSO_TCPHDR_WORDS    0xF
1240 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS)
1241 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS)
1242 
1243 #define S_LSO_IPHDR_WORDS    20
1244 #define M_LSO_IPHDR_WORDS    0xF
1245 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS)
1246 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS)
1247 
1248 #define S_LSO_IPV6    24
1249 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1250 #define F_LSO_IPV6    V_LSO_IPV6(1U)
1251 
1252 struct cpl_trace_pkt {
1253 #ifdef CHELSIO_FW
1254 	__u8 rss_opcode;
1255 #if defined(__LITTLE_ENDIAN_BITFIELD)
1256 	__u8 err:1;
1257 	__u8 :7;
1258 #else
1259 	__u8 :7;
1260 	__u8 err:1;
1261 #endif
1262 	__u8 rsvd0;
1263 #if defined(__LITTLE_ENDIAN_BITFIELD)
1264 	__u8 qid:4;
1265 	__u8 :4;
1266 #else
1267 	__u8 :4;
1268 	__u8 qid:4;
1269 #endif
1270 	__be32 tstamp;
1271 #endif /* CHELSIO_FW */
1272 
1273 	__u8  opcode;
1274 #if defined(__LITTLE_ENDIAN_BITFIELD)
1275 	__u8  iff:4;
1276 	__u8  :4;
1277 #else
1278 	__u8  :4;
1279 	__u8  iff:4;
1280 #endif
1281 	__u8  rsvd[4];
1282 	__be16 len;
1283 };
1284 
1285 struct cpl_rx_pkt {
1286 	RSS_HDR
1287 	__u8 opcode;
1288 #if defined(__LITTLE_ENDIAN_BITFIELD)
1289 	__u8 iff:4;
1290 	__u8 csum_valid:1;
1291 	__u8 ipmi_pkt:1;
1292 	__u8 vlan_valid:1;
1293 	__u8 fragment:1;
1294 #else
1295 	__u8 fragment:1;
1296 	__u8 vlan_valid:1;
1297 	__u8 ipmi_pkt:1;
1298 	__u8 csum_valid:1;
1299 	__u8 iff:4;
1300 #endif
1301 	__be16 csum;
1302 	__be16 vlan;
1303 	__be16 len;
1304 };
1305 
1306 struct cpl_l2t_write_req {
1307 	WR_HDR;
1308 	union opcode_tid ot;
1309 	__be32 params;
1310 	__u8  rsvd;
1311 	__u8  port_idx;
1312 	__u8  dst_mac[6];
1313 };
1314 
1315 /* cpl_l2t_write_req.params fields */
1316 #define S_L2T_W_IDX    0
1317 #define M_L2T_W_IDX    0x7FF
1318 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1319 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)
1320 
1321 #define S_L2T_W_VLAN    11
1322 #define M_L2T_W_VLAN    0xFFF
1323 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN)
1324 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN)
1325 
1326 #define S_L2T_W_IFF    23
1327 #define M_L2T_W_IFF    0xF
1328 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF)
1329 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF)
1330 
1331 #define S_L2T_W_PRIO    27
1332 #define M_L2T_W_PRIO    0x7
1333 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO)
1334 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO)
1335 
1336 struct cpl_l2t_write_rpl {
1337 	RSS_HDR
1338 	union opcode_tid ot;
1339 	__u8 status;
1340 	__u8 rsvd[3];
1341 };
1342 
1343 struct cpl_l2t_read_req {
1344 	WR_HDR;
1345 	union opcode_tid ot;
1346 	__be16 rsvd;
1347 	__be16 l2t_idx;
1348 };
1349 
1350 struct cpl_l2t_read_rpl {
1351 	RSS_HDR
1352 	union opcode_tid ot;
1353 	__be32 params;
1354 	__u8 rsvd[2];
1355 	__u8 dst_mac[6];
1356 };
1357 
1358 /* cpl_l2t_read_rpl.params fields */
1359 #define S_L2T_R_PRIO    0
1360 #define M_L2T_R_PRIO    0x7
1361 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO)
1362 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO)
1363 
1364 #define S_L2T_R_VLAN    8
1365 #define M_L2T_R_VLAN    0xFFF
1366 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN)
1367 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN)
1368 
1369 #define S_L2T_R_IFF    20
1370 #define M_L2T_R_IFF    0xF
1371 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF)
1372 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF)
1373 
1374 #define S_L2T_STATUS    24
1375 #define M_L2T_STATUS    0xFF
1376 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS)
1377 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS)
1378 
1379 struct cpl_smt_write_req {
1380 	WR_HDR;
1381 	union opcode_tid ot;
1382 	__u8 rsvd0;
1383 #if defined(__LITTLE_ENDIAN_BITFIELD)
1384 	__u8 mtu_idx:4;
1385 	__u8 iff:4;
1386 #else
1387 	__u8 iff:4;
1388 	__u8 mtu_idx:4;
1389 #endif
1390 	__be16 rsvd2;
1391 	__be16 rsvd3;
1392 	__u8  src_mac1[6];
1393 	__be16 rsvd4;
1394 	__u8  src_mac0[6];
1395 };
1396 
1397 struct cpl_smt_write_rpl {
1398 	RSS_HDR
1399 	union opcode_tid ot;
1400 	__u8 status;
1401 	__u8 rsvd[3];
1402 };
1403 
1404 struct cpl_smt_read_req {
1405 	WR_HDR;
1406 	union opcode_tid ot;
1407 	__u8 rsvd0;
1408 #if defined(__LITTLE_ENDIAN_BITFIELD)
1409 	__u8 :4;
1410 	__u8 iff:4;
1411 #else
1412 	__u8 iff:4;
1413 	__u8 :4;
1414 #endif
1415 	__be16 rsvd2;
1416 };
1417 
1418 struct cpl_smt_read_rpl {
1419 	RSS_HDR
1420 	union opcode_tid ot;
1421 	__u8 status;
1422 #if defined(__LITTLE_ENDIAN_BITFIELD)
1423 	__u8 mtu_idx:4;
1424 	__u8 :4;
1425 #else
1426 	__u8 :4;
1427 	__u8 mtu_idx:4;
1428 #endif
1429 	__be16 rsvd2;
1430 	__be16 rsvd3;
1431 	__u8  src_mac1[6];
1432 	__be16 rsvd4;
1433 	__u8  src_mac0[6];
1434 };
1435 
1436 struct cpl_rte_delete_req {
1437 	WR_HDR;
1438 	union opcode_tid ot;
1439 	__be32 params;
1440 };
1441 
1442 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */
1443 #define S_RTE_REQ_LUT_IX    8
1444 #define M_RTE_REQ_LUT_IX    0x7FF
1445 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1446 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1447 
1448 #define S_RTE_REQ_LUT_BASE    19
1449 #define M_RTE_REQ_LUT_BASE    0x7FF
1450 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1451 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1452 
1453 #define S_RTE_READ_REQ_SELECT    31
1454 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1455 #define F_RTE_READ_REQ_SELECT    V_RTE_READ_REQ_SELECT(1U)
1456 
1457 struct cpl_rte_delete_rpl {
1458 	RSS_HDR
1459 	union opcode_tid ot;
1460 	__u8 status;
1461 	__u8 rsvd[3];
1462 };
1463 
1464 struct cpl_rte_write_req {
1465 	WR_HDR;
1466 	union opcode_tid ot;
1467 #if defined(__LITTLE_ENDIAN_BITFIELD)
1468 	__u8 :6;
1469 	__u8 write_tcam:1;
1470 	__u8 write_l2t_lut:1;
1471 #else
1472 	__u8 write_l2t_lut:1;
1473 	__u8 write_tcam:1;
1474 	__u8 :6;
1475 #endif
1476 	__u8 rsvd[3];
1477 	__be32 lut_params;
1478 	__be16 rsvd2;
1479 	__be16 l2t_idx;
1480 	__be32 netmask;
1481 	__be32 faddr;
1482 };
1483 
1484 /* cpl_rte_write_req.lut_params fields */
1485 #define S_RTE_WRITE_REQ_LUT_IX    10
1486 #define M_RTE_WRITE_REQ_LUT_IX    0x7FF
1487 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX)
1488 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX)
1489 
1490 #define S_RTE_WRITE_REQ_LUT_BASE    21
1491 #define M_RTE_WRITE_REQ_LUT_BASE    0x7FF
1492 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE)
1493 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE)
1494 
1495 struct cpl_rte_write_rpl {
1496 	RSS_HDR
1497 	union opcode_tid ot;
1498 	__u8 status;
1499 	__u8 rsvd[3];
1500 };
1501 
1502 struct cpl_rte_read_req {
1503 	WR_HDR;
1504 	union opcode_tid ot;
1505 	__be32 params;
1506 };
1507 
1508 struct cpl_rte_read_rpl {
1509 	RSS_HDR
1510 	union opcode_tid ot;
1511 	__u8 status;
1512 	__u8 rsvd0;
1513 	__be16 l2t_idx;
1514 #if defined(__LITTLE_ENDIAN_BITFIELD)
1515 	__u8 :7;
1516 	__u8 select:1;
1517 #else
1518 	__u8 select:1;
1519 	__u8 :7;
1520 #endif
1521 	__u8 rsvd2[3];
1522 	__be32 addr;
1523 };
1524 
1525 struct cpl_tid_release {
1526 	WR_HDR;
1527 	union opcode_tid ot;
1528 	__be32 rsvd;
1529 };
1530 
1531 struct cpl_barrier {
1532 	WR_HDR;
1533 	__u8 opcode;
1534 	__u8 rsvd[7];
1535 };
1536 
1537 struct cpl_rdma_read_req {
1538 	__u8 opcode;
1539 	__u8 rsvd[15];
1540 };
1541 
1542 struct cpl_rdma_terminate {
1543 #ifdef CHELSIO_FW
1544 	__u8 opcode;
1545 	__u8 rsvd[2];
1546 #if defined(__LITTLE_ENDIAN_BITFIELD)
1547 	__u8 rspq:3;
1548 	__u8 :5;
1549 #else
1550 	__u8 :5;
1551 	__u8 rspq:3;
1552 #endif
1553 	__be32 tid_len;
1554 #endif
1555 	__be32 msn;
1556 	__be32 mo;
1557 	__u8  data[0];
1558 };
1559 
1560 /* cpl_rdma_terminate.tid_len fields */
1561 #define S_FLIT_CNT    0
1562 #define M_FLIT_CNT    0xFF
1563 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT)
1564 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT)
1565 
1566 #define S_TERM_TID    8
1567 #define M_TERM_TID    0xFFFFF
1568 #define V_TERM_TID(x) ((x) << S_TERM_TID)
1569 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1570 
1571 /* ULP_TX opcodes */
1572 enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 };
1573 
1574 #define S_ULPTX_CMD    28
1575 #define M_ULPTX_CMD    0xF
1576 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
1577 
1578 #define S_ULPTX_NFLITS    0
1579 #define M_ULPTX_NFLITS    0xFF
1580 #define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1581 
1582 struct ulp_mem_io {
1583 	WR_HDR;
1584 	__be32 cmd_lock_addr;
1585 	__be32 len;
1586 };
1587 
1588 /* ulp_mem_io.cmd_lock_addr fields */
1589 #define S_ULP_MEMIO_ADDR    0
1590 #define M_ULP_MEMIO_ADDR    0x7FFFFFF
1591 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1592 
1593 #define S_ULP_MEMIO_LOCK    27
1594 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1595 #define F_ULP_MEMIO_LOCK    V_ULP_MEMIO_LOCK(1U)
1596 
1597 /* ulp_mem_io.len fields */
1598 #define S_ULP_MEMIO_DATA_LEN    28
1599 #define M_ULP_MEMIO_DATA_LEN    0xF
1600 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1601 
1602 struct ulp_txpkt {
1603 	__be32 cmd_dest;
1604 	__be32 len;
1605 };
1606 
1607 /* ulp_txpkt.cmd_dest fields */
1608 #define S_ULP_TXPKT_DEST    24
1609 #define M_ULP_TXPKT_DEST    0xF
1610 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
1611 
1612 #endif  /* T3_CPL_H */
1613