1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2001 Eduardo Horvath. 5 * Copyright (c) 2001-2003 Thomas Moestl 6 * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 31 * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius 32 */ 33 34 #include <sys/cdefs.h> 35 /* 36 * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065 37 * Saturn Gigabit Ethernet controllers 38 */ 39 40 #if 0 41 #define CAS_DEBUG 42 #endif 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/bus.h> 47 #include <sys/callout.h> 48 #include <sys/endian.h> 49 #include <sys/mbuf.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/lock.h> 53 #include <sys/module.h> 54 #include <sys/mutex.h> 55 #include <sys/refcount.h> 56 #include <sys/resource.h> 57 #include <sys/rman.h> 58 #include <sys/socket.h> 59 #include <sys/sockio.h> 60 #include <sys/taskqueue.h> 61 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/if.h> 65 #include <net/if_var.h> 66 #include <net/if_arp.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_types.h> 70 #include <net/if_vlan_var.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/ip.h> 75 #include <netinet/tcp.h> 76 #include <netinet/udp.h> 77 78 #include <machine/bus.h> 79 #if defined(__powerpc__) 80 #include <dev/ofw/ofw_bus.h> 81 #include <dev/ofw/openfirm.h> 82 #include <machine/ofw_machdep.h> 83 #endif 84 #include <machine/resource.h> 85 86 #include <dev/mii/mii.h> 87 #include <dev/mii/miivar.h> 88 89 #include <dev/cas/if_casreg.h> 90 #include <dev/cas/if_casvar.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 95 #include "miibus_if.h" 96 97 #define RINGASSERT(n , min, max) \ 98 CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max)) 99 100 RINGASSERT(CAS_NRXCOMP, 128, 32768); 101 RINGASSERT(CAS_NRXDESC, 32, 8192); 102 RINGASSERT(CAS_NRXDESC2, 32, 8192); 103 RINGASSERT(CAS_NTXDESC, 32, 8192); 104 105 #undef RINGASSERT 106 107 #define CCDASSERT(m, a) \ 108 CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0) 109 110 CCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN); 111 CCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN); 112 CCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN); 113 114 #undef CCDASSERT 115 116 #define CAS_TRIES 10000 117 118 /* 119 * According to documentation, the hardware has support for basic TCP 120 * checksum offloading only, in practice this can be also used for UDP 121 * however (i.e. the problem of previous Sun NICs that a checksum of 0x0 122 * is not converted to 0xffff no longer exists). 123 */ 124 #define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 125 126 static inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx); 127 static int cas_attach(struct cas_softc *sc); 128 static int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, 129 uint32_t set); 130 static void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, 131 int nsegs, int error); 132 static void cas_detach(struct cas_softc *sc); 133 static int cas_disable_rx(struct cas_softc *sc); 134 static int cas_disable_tx(struct cas_softc *sc); 135 static void cas_eint(struct cas_softc *sc, u_int status); 136 static void cas_free(struct mbuf *m); 137 static void cas_init(void *xsc); 138 static void cas_init_locked(struct cas_softc *sc); 139 static void cas_init_regs(struct cas_softc *sc); 140 static int cas_intr(void *v); 141 static void cas_intr_task(void *arg, int pending __unused); 142 static int cas_ioctl(if_t ifp, u_long cmd, caddr_t data); 143 static int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head); 144 static int cas_mediachange(if_t ifp); 145 static void cas_mediastatus(if_t ifp, struct ifmediareq *ifmr); 146 static void cas_meminit(struct cas_softc *sc); 147 static void cas_mifinit(struct cas_softc *sc); 148 static int cas_mii_readreg(device_t dev, int phy, int reg); 149 static void cas_mii_statchg(device_t dev); 150 static int cas_mii_writereg(device_t dev, int phy, int reg, int val); 151 static void cas_reset(struct cas_softc *sc); 152 static int cas_reset_rx(struct cas_softc *sc); 153 static int cas_reset_tx(struct cas_softc *sc); 154 static void cas_resume(struct cas_softc *sc); 155 static u_int cas_descsize(u_int sz); 156 static void cas_rint(struct cas_softc *sc); 157 static void cas_rint_timeout(void *arg); 158 static inline void cas_rxcksum(struct mbuf *m, uint16_t cksum); 159 static inline void cas_rxcompinit(struct cas_rx_comp *rxcomp); 160 static u_int cas_rxcompsize(u_int sz); 161 static void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, 162 int nsegs, int error); 163 static void cas_setladrf(struct cas_softc *sc); 164 static void cas_start(if_t ifp); 165 static void cas_stop(if_t ifp); 166 static void cas_suspend(struct cas_softc *sc); 167 static void cas_tick(void *arg); 168 static void cas_tint(struct cas_softc *sc); 169 static void cas_tx_task(void *arg, int pending __unused); 170 static inline void cas_txkick(struct cas_softc *sc); 171 static void cas_watchdog(struct cas_softc *sc); 172 173 MODULE_DEPEND(cas, ether, 1, 1, 1); 174 MODULE_DEPEND(cas, miibus, 1, 1, 1); 175 176 #ifdef CAS_DEBUG 177 #include <sys/ktr.h> 178 #define KTR_CAS KTR_SPARE2 179 #endif 180 181 static int 182 cas_attach(struct cas_softc *sc) 183 { 184 struct cas_txsoft *txs; 185 if_t ifp; 186 int error, i; 187 uint32_t v; 188 189 /* Set up ifnet structure. */ 190 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 191 if_setsoftc(ifp, sc); 192 if_initname(ifp, device_get_name(sc->sc_dev), 193 device_get_unit(sc->sc_dev)); 194 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 195 if_setstartfn(ifp, cas_start); 196 if_setioctlfn(ifp, cas_ioctl); 197 if_setinitfn(ifp, cas_init); 198 if_setsendqlen(ifp, CAS_TXQUEUELEN); 199 if_setsendqready(ifp); 200 201 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 202 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 203 /* Create local taskq. */ 204 NET_TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc); 205 TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp); 206 sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK, 207 taskqueue_thread_enqueue, &sc->sc_tq); 208 if (sc->sc_tq == NULL) { 209 device_printf(sc->sc_dev, "could not create taskqueue\n"); 210 error = ENXIO; 211 goto fail_ifnet; 212 } 213 error = taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 214 device_get_nameunit(sc->sc_dev)); 215 if (error != 0) { 216 device_printf(sc->sc_dev, "could not start threads\n"); 217 goto fail_taskq; 218 } 219 220 /* Make sure the chip is stopped. */ 221 cas_reset(sc); 222 223 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 224 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 225 BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL, 226 &sc->sc_pdmatag); 227 if (error != 0) 228 goto fail_taskq; 229 230 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 231 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 232 CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag); 233 if (error != 0) 234 goto fail_ptag; 235 236 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 237 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 238 MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES, 239 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 240 if (error != 0) 241 goto fail_rtag; 242 243 error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0, 244 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 245 sizeof(struct cas_control_data), 1, 246 sizeof(struct cas_control_data), 0, 247 NULL, NULL, &sc->sc_cdmatag); 248 if (error != 0) 249 goto fail_ttag; 250 251 /* 252 * Allocate the control data structures, create and load the 253 * DMA map for it. 254 */ 255 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 256 (void **)&sc->sc_control_data, 257 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 258 &sc->sc_cddmamap)) != 0) { 259 device_printf(sc->sc_dev, 260 "unable to allocate control data, error = %d\n", error); 261 goto fail_ctag; 262 } 263 264 sc->sc_cddma = 0; 265 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 266 sc->sc_control_data, sizeof(struct cas_control_data), 267 cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 268 device_printf(sc->sc_dev, 269 "unable to load control data DMA map, error = %d\n", 270 error); 271 goto fail_cmem; 272 } 273 274 /* 275 * Initialize the transmit job descriptors. 276 */ 277 STAILQ_INIT(&sc->sc_txfreeq); 278 STAILQ_INIT(&sc->sc_txdirtyq); 279 280 /* 281 * Create the transmit buffer DMA maps. 282 */ 283 error = ENOMEM; 284 for (i = 0; i < CAS_TXQUEUELEN; i++) { 285 txs = &sc->sc_txsoft[i]; 286 txs->txs_mbuf = NULL; 287 txs->txs_ndescs = 0; 288 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 289 &txs->txs_dmamap)) != 0) { 290 device_printf(sc->sc_dev, 291 "unable to create TX DMA map %d, error = %d\n", 292 i, error); 293 goto fail_txd; 294 } 295 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 296 } 297 298 /* 299 * Allocate the receive buffers, create and load the DMA maps 300 * for them. 301 */ 302 for (i = 0; i < CAS_NRXDESC; i++) { 303 if ((error = bus_dmamem_alloc(sc->sc_rdmatag, 304 &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK, 305 &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) { 306 device_printf(sc->sc_dev, 307 "unable to allocate RX buffer %d, error = %d\n", 308 i, error); 309 goto fail_rxmem; 310 } 311 312 sc->sc_rxdptr = i; 313 sc->sc_rxdsoft[i].rxds_paddr = 0; 314 if ((error = bus_dmamap_load(sc->sc_rdmatag, 315 sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf, 316 CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 || 317 sc->sc_rxdsoft[i].rxds_paddr == 0) { 318 device_printf(sc->sc_dev, 319 "unable to load RX DMA map %d, error = %d\n", 320 i, error); 321 goto fail_rxmap; 322 } 323 } 324 325 if ((sc->sc_flags & CAS_SERDES) == 0) { 326 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII); 327 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, 328 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 329 cas_mifinit(sc); 330 /* 331 * Look for an external PHY. 332 */ 333 error = ENXIO; 334 v = CAS_READ_4(sc, CAS_MIF_CONF); 335 if ((v & CAS_MIF_CONF_MDI1) != 0) { 336 v |= CAS_MIF_CONF_PHY_SELECT; 337 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 338 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 339 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 340 /* Enable/unfreeze the GMII pins of Saturn. */ 341 if (sc->sc_variant == CAS_SATURN) { 342 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 343 CAS_READ_4(sc, CAS_SATURN_PCFG) & 344 ~CAS_SATURN_PCFG_FSI); 345 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 346 BUS_SPACE_BARRIER_READ | 347 BUS_SPACE_BARRIER_WRITE); 348 DELAY(10000); 349 } 350 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 351 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 352 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 353 } 354 /* 355 * Fall back on an internal PHY if no external PHY was found. 356 */ 357 if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) { 358 v &= ~CAS_MIF_CONF_PHY_SELECT; 359 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 360 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 361 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 362 /* Freeze the GMII pins of Saturn for saving power. */ 363 if (sc->sc_variant == CAS_SATURN) { 364 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 365 CAS_READ_4(sc, CAS_SATURN_PCFG) | 366 CAS_SATURN_PCFG_FSI); 367 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 368 BUS_SPACE_BARRIER_READ | 369 BUS_SPACE_BARRIER_WRITE); 370 DELAY(10000); 371 } 372 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 373 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 374 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 375 } 376 } else { 377 /* 378 * Use the external PCS SERDES. 379 */ 380 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES); 381 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE); 382 /* Enable/unfreeze the SERDES pins of Saturn. */ 383 if (sc->sc_variant == CAS_SATURN) { 384 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); 385 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 386 BUS_SPACE_BARRIER_WRITE); 387 } 388 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD); 389 CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4, 390 BUS_SPACE_BARRIER_WRITE); 391 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN); 392 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 393 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 394 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 395 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 396 CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE); 397 } 398 if (error != 0) { 399 device_printf(sc->sc_dev, "attaching PHYs failed\n"); 400 goto fail_rxmap; 401 } 402 sc->sc_mii = device_get_softc(sc->sc_miibus); 403 404 /* 405 * From this point forward, the attachment cannot fail. A failure 406 * before this point releases all resources that may have been 407 * allocated. 408 */ 409 410 /* Announce FIFO sizes. */ 411 v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE); 412 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 413 CAS_RX_FIFO_SIZE / 1024, v / 16); 414 415 /* Attach the interface. */ 416 ether_ifattach(ifp, sc->sc_enaddr); 417 418 /* 419 * Tell the upper layer(s) we support long frames/checksum offloads. 420 */ 421 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 422 if_setcapabilities(ifp, IFCAP_VLAN_MTU); 423 if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 424 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0); 425 if_sethwassist(ifp, CAS_CSUM_FEATURES); 426 } 427 if_setcapenable(ifp, if_getcapabilities(ifp)); 428 429 return (0); 430 431 /* 432 * Free any resources we've allocated during the failed attach 433 * attempt. Do this in reverse order and fall through. 434 */ 435 fail_rxmap: 436 for (i = 0; i < CAS_NRXDESC; i++) 437 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 438 bus_dmamap_unload(sc->sc_rdmatag, 439 sc->sc_rxdsoft[i].rxds_dmamap); 440 fail_rxmem: 441 for (i = 0; i < CAS_NRXDESC; i++) 442 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 443 bus_dmamem_free(sc->sc_rdmatag, 444 sc->sc_rxdsoft[i].rxds_buf, 445 sc->sc_rxdsoft[i].rxds_dmamap); 446 fail_txd: 447 for (i = 0; i < CAS_TXQUEUELEN; i++) 448 if (sc->sc_txsoft[i].txs_dmamap != NULL) 449 bus_dmamap_destroy(sc->sc_tdmatag, 450 sc->sc_txsoft[i].txs_dmamap); 451 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 452 fail_cmem: 453 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 454 sc->sc_cddmamap); 455 fail_ctag: 456 bus_dma_tag_destroy(sc->sc_cdmatag); 457 fail_ttag: 458 bus_dma_tag_destroy(sc->sc_tdmatag); 459 fail_rtag: 460 bus_dma_tag_destroy(sc->sc_rdmatag); 461 fail_ptag: 462 bus_dma_tag_destroy(sc->sc_pdmatag); 463 fail_taskq: 464 taskqueue_free(sc->sc_tq); 465 fail_ifnet: 466 if_free(ifp); 467 return (error); 468 } 469 470 static void 471 cas_detach(struct cas_softc *sc) 472 { 473 if_t ifp = sc->sc_ifp; 474 int i; 475 476 ether_ifdetach(ifp); 477 CAS_LOCK(sc); 478 cas_stop(ifp); 479 CAS_UNLOCK(sc); 480 callout_drain(&sc->sc_tick_ch); 481 callout_drain(&sc->sc_rx_ch); 482 taskqueue_drain(sc->sc_tq, &sc->sc_intr_task); 483 taskqueue_drain(sc->sc_tq, &sc->sc_tx_task); 484 if_free(ifp); 485 taskqueue_free(sc->sc_tq); 486 device_delete_child(sc->sc_dev, sc->sc_miibus); 487 488 for (i = 0; i < CAS_NRXDESC; i++) 489 if (sc->sc_rxdsoft[i].rxds_dmamap != NULL) 490 bus_dmamap_sync(sc->sc_rdmatag, 491 sc->sc_rxdsoft[i].rxds_dmamap, 492 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 493 for (i = 0; i < CAS_NRXDESC; i++) 494 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 495 bus_dmamap_unload(sc->sc_rdmatag, 496 sc->sc_rxdsoft[i].rxds_dmamap); 497 for (i = 0; i < CAS_NRXDESC; i++) 498 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 499 bus_dmamem_free(sc->sc_rdmatag, 500 sc->sc_rxdsoft[i].rxds_buf, 501 sc->sc_rxdsoft[i].rxds_dmamap); 502 for (i = 0; i < CAS_TXQUEUELEN; i++) 503 if (sc->sc_txsoft[i].txs_dmamap != NULL) 504 bus_dmamap_destroy(sc->sc_tdmatag, 505 sc->sc_txsoft[i].txs_dmamap); 506 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 507 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 508 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 509 sc->sc_cddmamap); 510 bus_dma_tag_destroy(sc->sc_cdmatag); 511 bus_dma_tag_destroy(sc->sc_tdmatag); 512 bus_dma_tag_destroy(sc->sc_rdmatag); 513 bus_dma_tag_destroy(sc->sc_pdmatag); 514 } 515 516 static void 517 cas_suspend(struct cas_softc *sc) 518 { 519 if_t ifp = sc->sc_ifp; 520 521 CAS_LOCK(sc); 522 cas_stop(ifp); 523 CAS_UNLOCK(sc); 524 } 525 526 static void 527 cas_resume(struct cas_softc *sc) 528 { 529 if_t ifp = sc->sc_ifp; 530 531 CAS_LOCK(sc); 532 /* 533 * On resume all registers have to be initialized again like 534 * after power-on. 535 */ 536 sc->sc_flags &= ~CAS_INITED; 537 if (if_getflags(ifp) & IFF_UP) 538 cas_init_locked(sc); 539 CAS_UNLOCK(sc); 540 } 541 542 static inline void 543 cas_rxcksum(struct mbuf *m, uint16_t cksum) 544 { 545 struct ether_header *eh; 546 struct ip *ip; 547 struct udphdr *uh; 548 uint16_t *opts; 549 int32_t hlen, len, pktlen; 550 uint32_t temp32; 551 552 pktlen = m->m_pkthdr.len; 553 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 554 return; 555 eh = mtod(m, struct ether_header *); 556 if (eh->ether_type != htons(ETHERTYPE_IP)) 557 return; 558 ip = (struct ip *)(eh + 1); 559 if (ip->ip_v != IPVERSION) 560 return; 561 562 hlen = ip->ip_hl << 2; 563 pktlen -= sizeof(struct ether_header); 564 if (hlen < sizeof(struct ip)) 565 return; 566 if (ntohs(ip->ip_len) < hlen) 567 return; 568 if (ntohs(ip->ip_len) != pktlen) 569 return; 570 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 571 return; /* Cannot handle fragmented packet. */ 572 573 switch (ip->ip_p) { 574 case IPPROTO_TCP: 575 if (pktlen < (hlen + sizeof(struct tcphdr))) 576 return; 577 break; 578 case IPPROTO_UDP: 579 if (pktlen < (hlen + sizeof(struct udphdr))) 580 return; 581 uh = (struct udphdr *)((uint8_t *)ip + hlen); 582 if (uh->uh_sum == 0) 583 return; /* no checksum */ 584 break; 585 default: 586 return; 587 } 588 589 cksum = ~cksum; 590 /* checksum fixup for IP options */ 591 len = hlen - sizeof(struct ip); 592 if (len > 0) { 593 opts = (uint16_t *)(ip + 1); 594 for (; len > 0; len -= sizeof(uint16_t), opts++) { 595 temp32 = cksum - *opts; 596 temp32 = (temp32 >> 16) + (temp32 & 65535); 597 cksum = temp32 & 65535; 598 } 599 } 600 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 601 m->m_pkthdr.csum_data = cksum; 602 } 603 604 static void 605 cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 606 { 607 struct cas_softc *sc = xsc; 608 609 if (error != 0) 610 return; 611 if (nsegs != 1) 612 panic("%s: bad control buffer segment count", __func__); 613 sc->sc_cddma = segs[0].ds_addr; 614 } 615 616 static void 617 cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 618 { 619 struct cas_softc *sc = xsc; 620 621 if (error != 0) 622 return; 623 if (nsegs != 1) 624 panic("%s: bad RX buffer segment count", __func__); 625 sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr; 626 } 627 628 static void 629 cas_tick(void *arg) 630 { 631 struct cas_softc *sc = arg; 632 if_t ifp = sc->sc_ifp; 633 uint32_t v; 634 635 CAS_LOCK_ASSERT(sc, MA_OWNED); 636 637 /* 638 * Unload collision and error counters. 639 */ 640 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 641 CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) + 642 CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT)); 643 v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) + 644 CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT); 645 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, v); 646 if_inc_counter(ifp, IFCOUNTER_OERRORS, v); 647 if_inc_counter(ifp, IFCOUNTER_IERRORS, 648 CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) + 649 CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) + 650 CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) + 651 CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL)); 652 653 /* 654 * Then clear the hardware counters. 655 */ 656 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 657 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 658 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 659 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 660 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 661 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 662 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 663 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 664 665 mii_tick(sc->sc_mii); 666 667 if (sc->sc_txfree != CAS_MAXTXFREE) 668 cas_tint(sc); 669 670 cas_watchdog(sc); 671 672 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 673 } 674 675 static int 676 cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set) 677 { 678 int i; 679 uint32_t reg; 680 681 for (i = CAS_TRIES; i--; DELAY(100)) { 682 reg = CAS_READ_4(sc, r); 683 if ((reg & clr) == 0 && (reg & set) == set) 684 return (1); 685 } 686 return (0); 687 } 688 689 static void 690 cas_reset(struct cas_softc *sc) 691 { 692 693 #ifdef CAS_DEBUG 694 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 695 #endif 696 /* Disable all interrupts in order to avoid spurious ones. */ 697 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 698 699 cas_reset_rx(sc); 700 cas_reset_tx(sc); 701 702 /* 703 * Do a full reset modulo the result of the last auto-negotiation 704 * when using the SERDES. 705 */ 706 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX | 707 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 708 CAS_BARRIER(sc, CAS_RESET, 4, 709 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 710 DELAY(3000); 711 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 712 device_printf(sc->sc_dev, "cannot reset device\n"); 713 } 714 715 static void 716 cas_stop(if_t ifp) 717 { 718 struct cas_softc *sc = if_getsoftc(ifp); 719 struct cas_txsoft *txs; 720 721 #ifdef CAS_DEBUG 722 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 723 #endif 724 725 callout_stop(&sc->sc_tick_ch); 726 callout_stop(&sc->sc_rx_ch); 727 728 /* Disable all interrupts in order to avoid spurious ones. */ 729 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 730 731 cas_reset_tx(sc); 732 cas_reset_rx(sc); 733 734 /* 735 * Release any queued transmit buffers. 736 */ 737 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 738 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 739 if (txs->txs_ndescs != 0) { 740 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 741 BUS_DMASYNC_POSTWRITE); 742 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 743 if (txs->txs_mbuf != NULL) { 744 m_freem(txs->txs_mbuf); 745 txs->txs_mbuf = NULL; 746 } 747 } 748 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 749 } 750 751 /* 752 * Mark the interface down and cancel the watchdog timer. 753 */ 754 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 755 sc->sc_flags &= ~CAS_LINK; 756 sc->sc_wdog_timer = 0; 757 } 758 759 static int 760 cas_reset_rx(struct cas_softc *sc) 761 { 762 763 /* 764 * Resetting while DMA is in progress can cause a bus hang, so we 765 * disable DMA first. 766 */ 767 (void)cas_disable_rx(sc); 768 CAS_WRITE_4(sc, CAS_RX_CONF, 0); 769 CAS_BARRIER(sc, CAS_RX_CONF, 4, 770 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 771 if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0)) 772 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 773 774 /* Finally, reset the ERX. */ 775 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | 776 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 777 CAS_BARRIER(sc, CAS_RESET, 4, 778 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 779 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX, 0)) { 780 device_printf(sc->sc_dev, "cannot reset receiver\n"); 781 return (1); 782 } 783 return (0); 784 } 785 786 static int 787 cas_reset_tx(struct cas_softc *sc) 788 { 789 790 /* 791 * Resetting while DMA is in progress can cause a bus hang, so we 792 * disable DMA first. 793 */ 794 (void)cas_disable_tx(sc); 795 CAS_WRITE_4(sc, CAS_TX_CONF, 0); 796 CAS_BARRIER(sc, CAS_TX_CONF, 4, 797 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 798 if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0)) 799 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 800 801 /* Finally, reset the ETX. */ 802 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX | 803 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 804 CAS_BARRIER(sc, CAS_RESET, 4, 805 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 806 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_TX, 0)) { 807 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 808 return (1); 809 } 810 return (0); 811 } 812 813 static int 814 cas_disable_rx(struct cas_softc *sc) 815 { 816 817 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 818 CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN); 819 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 820 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 821 if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 822 return (1); 823 if (bootverbose) 824 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 825 return (0); 826 } 827 828 static int 829 cas_disable_tx(struct cas_softc *sc) 830 { 831 832 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 833 CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN); 834 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 835 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 836 if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 837 return (1); 838 if (bootverbose) 839 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 840 return (0); 841 } 842 843 static inline void 844 cas_rxcompinit(struct cas_rx_comp *rxcomp) 845 { 846 847 rxcomp->crc_word1 = 0; 848 rxcomp->crc_word2 = 0; 849 rxcomp->crc_word3 = 850 htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO)); 851 rxcomp->crc_word4 = htole64(CAS_RC4_ZERO); 852 } 853 854 static void 855 cas_meminit(struct cas_softc *sc) 856 { 857 int i; 858 859 CAS_LOCK_ASSERT(sc, MA_OWNED); 860 861 /* 862 * Initialize the transmit descriptor ring. 863 */ 864 for (i = 0; i < CAS_NTXDESC; i++) { 865 sc->sc_txdescs[i].cd_flags = 0; 866 sc->sc_txdescs[i].cd_buf_ptr = 0; 867 } 868 sc->sc_txfree = CAS_MAXTXFREE; 869 sc->sc_txnext = 0; 870 sc->sc_txwin = 0; 871 872 /* 873 * Initialize the receive completion ring. 874 */ 875 for (i = 0; i < CAS_NRXCOMP; i++) 876 cas_rxcompinit(&sc->sc_rxcomps[i]); 877 sc->sc_rxcptr = 0; 878 879 /* 880 * Initialize the first receive descriptor ring. We leave 881 * the second one zeroed as we don't actually use it. 882 */ 883 for (i = 0; i < CAS_NRXDESC; i++) 884 CAS_INIT_RXDESC(sc, i, i); 885 sc->sc_rxdptr = 0; 886 887 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 888 } 889 890 static u_int 891 cas_descsize(u_int sz) 892 { 893 894 switch (sz) { 895 case 32: 896 return (CAS_DESC_32); 897 case 64: 898 return (CAS_DESC_64); 899 case 128: 900 return (CAS_DESC_128); 901 case 256: 902 return (CAS_DESC_256); 903 case 512: 904 return (CAS_DESC_512); 905 case 1024: 906 return (CAS_DESC_1K); 907 case 2048: 908 return (CAS_DESC_2K); 909 case 4096: 910 return (CAS_DESC_4K); 911 case 8192: 912 return (CAS_DESC_8K); 913 default: 914 printf("%s: invalid descriptor ring size %d\n", __func__, sz); 915 return (CAS_DESC_32); 916 } 917 } 918 919 static u_int 920 cas_rxcompsize(u_int sz) 921 { 922 923 switch (sz) { 924 case 128: 925 return (CAS_RX_CONF_COMP_128); 926 case 256: 927 return (CAS_RX_CONF_COMP_256); 928 case 512: 929 return (CAS_RX_CONF_COMP_512); 930 case 1024: 931 return (CAS_RX_CONF_COMP_1K); 932 case 2048: 933 return (CAS_RX_CONF_COMP_2K); 934 case 4096: 935 return (CAS_RX_CONF_COMP_4K); 936 case 8192: 937 return (CAS_RX_CONF_COMP_8K); 938 case 16384: 939 return (CAS_RX_CONF_COMP_16K); 940 case 32768: 941 return (CAS_RX_CONF_COMP_32K); 942 default: 943 printf("%s: invalid dcompletion ring size %d\n", __func__, sz); 944 return (CAS_RX_CONF_COMP_128); 945 } 946 } 947 948 static void 949 cas_init(void *xsc) 950 { 951 struct cas_softc *sc = xsc; 952 953 CAS_LOCK(sc); 954 cas_init_locked(sc); 955 CAS_UNLOCK(sc); 956 } 957 958 /* 959 * Initialization of interface; set up initialization block 960 * and transmit/receive descriptor rings. 961 */ 962 static void 963 cas_init_locked(struct cas_softc *sc) 964 { 965 if_t ifp = sc->sc_ifp; 966 uint32_t v; 967 968 CAS_LOCK_ASSERT(sc, MA_OWNED); 969 970 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 971 return; 972 973 #ifdef CAS_DEBUG 974 CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev), 975 __func__); 976 #endif 977 /* 978 * Initialization sequence. The numbered steps below correspond 979 * to the sequence outlined in section 6.3.5.1 in the Ethernet 980 * Channel Engine manual (part of the PCIO manual). 981 * See also the STP2002-STQ document from Sun Microsystems. 982 */ 983 984 /* step 1 & 2. Reset the Ethernet Channel. */ 985 cas_stop(ifp); 986 cas_reset(sc); 987 #ifdef CAS_DEBUG 988 CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev), 989 __func__); 990 #endif 991 992 if ((sc->sc_flags & CAS_SERDES) == 0) 993 /* Re-initialize the MIF. */ 994 cas_mifinit(sc); 995 996 /* step 3. Setup data structures in host memory. */ 997 cas_meminit(sc); 998 999 /* step 4. TX MAC registers & counters */ 1000 cas_init_regs(sc); 1001 1002 /* step 5. RX MAC registers & counters */ 1003 1004 /* step 6 & 7. Program Ring Base Addresses. */ 1005 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI, 1006 (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32)); 1007 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO, 1008 CAS_CDTXDADDR(sc, 0) & 0xffffffff); 1009 1010 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI, 1011 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32)); 1012 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO, 1013 CAS_CDRXCADDR(sc, 0) & 0xffffffff); 1014 1015 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI, 1016 (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32)); 1017 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO, 1018 CAS_CDRXDADDR(sc, 0) & 0xffffffff); 1019 1020 if ((sc->sc_flags & CAS_REG_PLUS) != 0) { 1021 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI, 1022 (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32)); 1023 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO, 1024 CAS_CDRXD2ADDR(sc, 0) & 0xffffffff); 1025 } 1026 1027 #ifdef CAS_DEBUG 1028 CTR5(KTR_CAS, 1029 "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx", 1030 CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0), 1031 CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma); 1032 #endif 1033 1034 /* step 8. Global Configuration & Interrupt Masks */ 1035 1036 /* Disable weighted round robin. */ 1037 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS); 1038 1039 /* 1040 * Enable infinite bursts for revisions without PCI issues if 1041 * applicable. Doing so greatly improves the TX performance. 1042 */ 1043 CAS_WRITE_4(sc, CAS_INF_BURST, 1044 (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN : 1045 0); 1046 1047 /* Set up interrupts. */ 1048 CAS_WRITE_4(sc, CAS_INTMASK, 1049 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 1050 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 1051 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 1052 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 1053 CAS_INTR_PCI_ERROR_INT 1054 #ifdef CAS_DEBUG 1055 | CAS_INTR_PCS_INT | CAS_INTR_MIF 1056 #endif 1057 )); 1058 /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */ 1059 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0); 1060 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW); 1061 CAS_WRITE_4(sc, CAS_MAC_TX_MASK, 1062 ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)); 1063 #ifdef CAS_DEBUG 1064 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1065 ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1066 CAS_MAC_CTRL_NON_PAUSE)); 1067 #else 1068 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1069 CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1070 CAS_MAC_CTRL_NON_PAUSE); 1071 #endif 1072 1073 /* Enable PCI error interrupts. */ 1074 CAS_WRITE_4(sc, CAS_ERROR_MASK, 1075 ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO | 1076 CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO)); 1077 1078 /* Enable PCI error interrupts in BIM configuration. */ 1079 CAS_WRITE_4(sc, CAS_BIM_CONF, 1080 CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN); 1081 1082 /* 1083 * step 9. ETX Configuration: encode receive descriptor ring size, 1084 * enable DMA and disable pre-interrupt writeback completion. 1085 */ 1086 v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT; 1087 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN | 1088 CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS); 1089 1090 /* step 10. ERX Configuration */ 1091 1092 /* 1093 * Encode receive completion and descriptor ring sizes, set the 1094 * swivel offset. 1095 */ 1096 v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT; 1097 v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT; 1098 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1099 v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT; 1100 CAS_WRITE_4(sc, CAS_RX_CONF, 1101 v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT)); 1102 1103 /* Set the PAUSE thresholds. We use the maximum OFF threshold. */ 1104 CAS_WRITE_4(sc, CAS_RX_PTHRS, 1105 (111 << CAS_RX_PTHRS_XOFF_SHFT) | (15 << CAS_RX_PTHRS_XON_SHFT)); 1106 1107 /* RX blanking */ 1108 CAS_WRITE_4(sc, CAS_RX_BLANK, 1109 (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT)); 1110 1111 /* Set RX_COMP_AFULL threshold to half of the RX completions. */ 1112 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS, 1113 (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT); 1114 1115 /* Initialize the RX page size register as appropriate for 8k. */ 1116 CAS_WRITE_4(sc, CAS_RX_PSZ, 1117 (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) | 1118 (4 << CAS_RX_PSZ_MB_CNT_SHFT) | 1119 (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) | 1120 (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT)); 1121 1122 /* Disable RX random early detection. */ 1123 CAS_WRITE_4(sc, CAS_RX_RED, 0); 1124 1125 /* Zero the RX reassembly DMA table. */ 1126 for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) { 1127 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v); 1128 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0); 1129 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0); 1130 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0); 1131 } 1132 1133 /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */ 1134 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0); 1135 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0); 1136 1137 /* Finally, enable RX DMA. */ 1138 CAS_WRITE_4(sc, CAS_RX_CONF, 1139 CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN); 1140 1141 /* step 11. Configure Media. */ 1142 1143 /* step 12. RX_MAC Configuration Register */ 1144 v = CAS_READ_4(sc, CAS_MAC_RX_CONF); 1145 v &= ~(CAS_MAC_RX_CONF_STRPPAD | CAS_MAC_RX_CONF_EN); 1146 v |= CAS_MAC_RX_CONF_STRPFCS; 1147 sc->sc_mac_rxcfg = v; 1148 /* 1149 * Clear the RX filter and reprogram it. This will also set the 1150 * current RX MAC configuration and enable it. 1151 */ 1152 cas_setladrf(sc); 1153 1154 /* step 13. TX_MAC Configuration Register */ 1155 v = CAS_READ_4(sc, CAS_MAC_TX_CONF); 1156 v |= CAS_MAC_TX_CONF_EN; 1157 (void)cas_disable_tx(sc); 1158 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v); 1159 1160 /* step 14. Issue Transmit Pending command. */ 1161 1162 /* step 15. Give the receiver a swift kick. */ 1163 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4); 1164 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0); 1165 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1166 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4); 1167 1168 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1169 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1170 1171 mii_mediachg(sc->sc_mii); 1172 1173 /* Start the one second timer. */ 1174 sc->sc_wdog_timer = 0; 1175 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1176 } 1177 1178 static int 1179 cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head) 1180 { 1181 bus_dma_segment_t txsegs[CAS_NTXSEGS]; 1182 struct cas_txsoft *txs; 1183 struct ip *ip; 1184 struct mbuf *m; 1185 uint64_t cflags; 1186 int error, nexttx, nsegs, offset, seg; 1187 1188 CAS_LOCK_ASSERT(sc, MA_OWNED); 1189 1190 /* Get a work queue entry. */ 1191 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1192 /* Ran out of descriptors. */ 1193 return (ENOBUFS); 1194 } 1195 1196 cflags = 0; 1197 if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) { 1198 if (M_WRITABLE(*m_head) == 0) { 1199 m = m_dup(*m_head, M_NOWAIT); 1200 m_freem(*m_head); 1201 *m_head = m; 1202 if (m == NULL) 1203 return (ENOBUFS); 1204 } 1205 offset = sizeof(struct ether_header); 1206 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1207 if (m == NULL) { 1208 *m_head = NULL; 1209 return (ENOBUFS); 1210 } 1211 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1212 offset += (ip->ip_hl << 2); 1213 cflags = (offset << CAS_TD_CKSUM_START_SHFT) | 1214 ((offset + m->m_pkthdr.csum_data) << 1215 CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN; 1216 *m_head = m; 1217 } 1218 1219 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1220 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1221 if (error == EFBIG) { 1222 m = m_collapse(*m_head, M_NOWAIT, CAS_NTXSEGS); 1223 if (m == NULL) { 1224 m_freem(*m_head); 1225 *m_head = NULL; 1226 return (ENOBUFS); 1227 } 1228 *m_head = m; 1229 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1230 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1231 BUS_DMA_NOWAIT); 1232 if (error != 0) { 1233 m_freem(*m_head); 1234 *m_head = NULL; 1235 return (error); 1236 } 1237 } else if (error != 0) 1238 return (error); 1239 /* If nsegs is wrong then the stack is corrupt. */ 1240 KASSERT(nsegs <= CAS_NTXSEGS, 1241 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1242 if (nsegs == 0) { 1243 m_freem(*m_head); 1244 *m_head = NULL; 1245 return (EIO); 1246 } 1247 1248 /* 1249 * Ensure we have enough descriptors free to describe 1250 * the packet. Note, we always reserve one descriptor 1251 * at the end of the ring as a termination point, in 1252 * order to prevent wrap-around. 1253 */ 1254 if (nsegs > sc->sc_txfree - 1) { 1255 txs->txs_ndescs = 0; 1256 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1257 return (ENOBUFS); 1258 } 1259 1260 txs->txs_ndescs = nsegs; 1261 txs->txs_firstdesc = sc->sc_txnext; 1262 nexttx = txs->txs_firstdesc; 1263 for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) { 1264 #ifdef CAS_DEBUG 1265 CTR6(KTR_CAS, 1266 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1267 __func__, seg, nexttx, txsegs[seg].ds_len, 1268 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr)); 1269 #endif 1270 sc->sc_txdescs[nexttx].cd_buf_ptr = 1271 htole64(txsegs[seg].ds_addr); 1272 KASSERT(txsegs[seg].ds_len < 1273 CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT, 1274 ("%s: segment size too large!", __func__)); 1275 sc->sc_txdescs[nexttx].cd_flags = 1276 htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT); 1277 txs->txs_lastdesc = nexttx; 1278 } 1279 1280 /* Set EOF on the last descriptor. */ 1281 #ifdef CAS_DEBUG 1282 CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d", 1283 __func__, seg, nexttx); 1284 #endif 1285 sc->sc_txdescs[txs->txs_lastdesc].cd_flags |= 1286 htole64(CAS_TD_END_OF_FRAME); 1287 1288 /* Lastly set SOF on the first descriptor. */ 1289 #ifdef CAS_DEBUG 1290 CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d", 1291 __func__, seg, nexttx); 1292 #endif 1293 if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) { 1294 sc->sc_txwin = 0; 1295 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1296 htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME); 1297 } else 1298 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1299 htole64(cflags | CAS_TD_START_OF_FRAME); 1300 1301 /* Sync the DMA map. */ 1302 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1303 BUS_DMASYNC_PREWRITE); 1304 1305 #ifdef CAS_DEBUG 1306 CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1307 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1308 txs->txs_ndescs); 1309 #endif 1310 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1311 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1312 txs->txs_mbuf = *m_head; 1313 1314 sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc); 1315 sc->sc_txfree -= txs->txs_ndescs; 1316 1317 return (0); 1318 } 1319 1320 static void 1321 cas_init_regs(struct cas_softc *sc) 1322 { 1323 int i; 1324 const u_char *laddr = if_getlladdr(sc->sc_ifp); 1325 1326 CAS_LOCK_ASSERT(sc, MA_OWNED); 1327 1328 /* These registers are not cleared on reset. */ 1329 if ((sc->sc_flags & CAS_INITED) == 0) { 1330 /* magic values */ 1331 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0); 1332 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8); 1333 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4); 1334 1335 /* min frame length */ 1336 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN); 1337 /* max frame length and max burst size */ 1338 CAS_WRITE_4(sc, CAS_MAC_MAX_BF, 1339 ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) << 1340 CAS_MAC_MAX_BF_FRM_SHFT) | 1341 (0x2000 << CAS_MAC_MAX_BF_BST_SHFT)); 1342 1343 /* more magic values */ 1344 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 1345 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4); 1346 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1347 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808); 1348 1349 /* random number seed */ 1350 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED, 1351 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1352 1353 /* secondary MAC addresses: 0:0:0:0:0:0 */ 1354 for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41; 1355 i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3) 1356 CAS_WRITE_4(sc, i, 0); 1357 1358 /* MAC control address: 01:80:c2:00:00:01 */ 1359 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001); 1360 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200); 1361 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180); 1362 1363 /* MAC filter address: 0:0:0:0:0:0 */ 1364 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0); 1365 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0); 1366 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0); 1367 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0); 1368 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0); 1369 1370 /* Zero the hash table. */ 1371 for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15; 1372 i += CAS_MAC_HASH1 - CAS_MAC_HASH0) 1373 CAS_WRITE_4(sc, i, 0); 1374 1375 sc->sc_flags |= CAS_INITED; 1376 } 1377 1378 /* Counters need to be zeroed. */ 1379 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 1380 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 1381 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 1382 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 1383 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0); 1384 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0); 1385 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0); 1386 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 1387 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 1388 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 1389 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 1390 1391 /* Set XOFF PAUSE time. */ 1392 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT); 1393 1394 /* Set the station address. */ 1395 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1396 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1397 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1398 1399 /* Enable MII outputs. */ 1400 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE); 1401 } 1402 1403 static void 1404 cas_tx_task(void *arg, int pending __unused) 1405 { 1406 if_t ifp; 1407 1408 ifp = (if_t)arg; 1409 cas_start(ifp); 1410 } 1411 1412 static inline void 1413 cas_txkick(struct cas_softc *sc) 1414 { 1415 1416 /* 1417 * Update the TX kick register. This register has to point to the 1418 * descriptor after the last valid one and for optimum performance 1419 * should be incremented in multiples of 4 (the DMA engine fetches/ 1420 * updates descriptors in batches of 4). 1421 */ 1422 #ifdef CAS_DEBUG 1423 CTR3(KTR_CAS, "%s: %s: kicking TX %d", 1424 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1425 #endif 1426 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1427 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext); 1428 } 1429 1430 static void 1431 cas_start(if_t ifp) 1432 { 1433 struct cas_softc *sc = if_getsoftc(ifp); 1434 struct mbuf *m; 1435 int kicked, ntx; 1436 1437 CAS_LOCK(sc); 1438 1439 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1440 IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) { 1441 CAS_UNLOCK(sc); 1442 return; 1443 } 1444 1445 if (sc->sc_txfree < CAS_MAXTXFREE / 4) 1446 cas_tint(sc); 1447 1448 #ifdef CAS_DEBUG 1449 CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d", 1450 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1451 sc->sc_txnext); 1452 #endif 1453 ntx = 0; 1454 kicked = 0; 1455 for (; !if_sendq_empty(ifp) && sc->sc_txfree > 1;) { 1456 m = if_dequeue(ifp); 1457 if (m == NULL) 1458 break; 1459 if (cas_load_txmbuf(sc, &m) != 0) { 1460 if (m == NULL) 1461 break; 1462 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1463 if_sendq_prepend(ifp, m); 1464 break; 1465 } 1466 if ((sc->sc_txnext % 4) == 0) { 1467 cas_txkick(sc); 1468 kicked = 1; 1469 } else 1470 kicked = 0; 1471 ntx++; 1472 BPF_MTAP(ifp, m); 1473 } 1474 1475 if (ntx > 0) { 1476 if (kicked == 0) 1477 cas_txkick(sc); 1478 #ifdef CAS_DEBUG 1479 CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d", 1480 device_get_name(sc->sc_dev), sc->sc_txnext); 1481 #endif 1482 1483 /* Set a watchdog timer in case the chip flakes out. */ 1484 sc->sc_wdog_timer = 5; 1485 #ifdef CAS_DEBUG 1486 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1487 device_get_name(sc->sc_dev), __func__, 1488 sc->sc_wdog_timer); 1489 #endif 1490 } 1491 1492 CAS_UNLOCK(sc); 1493 } 1494 1495 static void 1496 cas_tint(struct cas_softc *sc) 1497 { 1498 if_t ifp = sc->sc_ifp; 1499 struct cas_txsoft *txs; 1500 int progress; 1501 uint32_t txlast; 1502 #ifdef CAS_DEBUG 1503 int i; 1504 1505 CAS_LOCK_ASSERT(sc, MA_OWNED); 1506 1507 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1508 #endif 1509 1510 /* 1511 * Go through our TX list and free mbufs for those 1512 * frames that have been transmitted. 1513 */ 1514 progress = 0; 1515 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1516 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1517 #ifdef CAS_DEBUG 1518 if ((if_getflags(ifp) & IFF_DEBUG) != 0) { 1519 printf(" txsoft %p transmit chain:\n", txs); 1520 for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) { 1521 printf("descriptor %d: ", i); 1522 printf("cd_flags: 0x%016llx\t", 1523 (long long)le64toh( 1524 sc->sc_txdescs[i].cd_flags)); 1525 printf("cd_buf_ptr: 0x%016llx\n", 1526 (long long)le64toh( 1527 sc->sc_txdescs[i].cd_buf_ptr)); 1528 if (i == txs->txs_lastdesc) 1529 break; 1530 } 1531 } 1532 #endif 1533 1534 /* 1535 * In theory, we could harvest some descriptors before 1536 * the ring is empty, but that's a bit complicated. 1537 * 1538 * CAS_TX_COMPn points to the last descriptor 1539 * processed + 1. 1540 */ 1541 txlast = CAS_READ_4(sc, CAS_TX_COMP3); 1542 #ifdef CAS_DEBUG 1543 CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, " 1544 "txs->txs_lastdesc = %d, txlast = %d", 1545 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1546 #endif 1547 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1548 if ((txlast >= txs->txs_firstdesc) && 1549 (txlast <= txs->txs_lastdesc)) 1550 break; 1551 } else { 1552 /* Ick -- this command wraps. */ 1553 if ((txlast >= txs->txs_firstdesc) || 1554 (txlast <= txs->txs_lastdesc)) 1555 break; 1556 } 1557 1558 #ifdef CAS_DEBUG 1559 CTR1(KTR_CAS, "%s: releasing a descriptor", __func__); 1560 #endif 1561 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1562 1563 sc->sc_txfree += txs->txs_ndescs; 1564 1565 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1566 BUS_DMASYNC_POSTWRITE); 1567 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1568 if (txs->txs_mbuf != NULL) { 1569 m_freem(txs->txs_mbuf); 1570 txs->txs_mbuf = NULL; 1571 } 1572 1573 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1574 1575 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1576 progress = 1; 1577 } 1578 1579 #ifdef CAS_DEBUG 1580 CTR5(KTR_CAS, "%s: CAS_TX_SM1 %x CAS_TX_SM2 %x CAS_TX_DESC_BASE %llx " 1581 "CAS_TX_COMP3 %x", 1582 __func__, CAS_READ_4(sc, CAS_TX_SM1), CAS_READ_4(sc, CAS_TX_SM2), 1583 ((long long)CAS_READ_4(sc, CAS_TX_DESC3_BASE_HI) << 32) | 1584 CAS_READ_4(sc, CAS_TX_DESC3_BASE_LO), 1585 CAS_READ_4(sc, CAS_TX_COMP3)); 1586 #endif 1587 1588 if (progress) { 1589 /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */ 1590 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1591 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1592 sc->sc_wdog_timer = 0; 1593 } 1594 1595 #ifdef CAS_DEBUG 1596 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1597 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1598 #endif 1599 } 1600 1601 static void 1602 cas_rint_timeout(void *arg) 1603 { 1604 struct epoch_tracker et; 1605 struct cas_softc *sc = arg; 1606 1607 CAS_LOCK_ASSERT(sc, MA_OWNED); 1608 1609 NET_EPOCH_ENTER(et); 1610 cas_rint(sc); 1611 NET_EPOCH_EXIT(et); 1612 } 1613 1614 static void 1615 cas_rint(struct cas_softc *sc) 1616 { 1617 struct cas_rxdsoft *rxds, *rxds2; 1618 if_t ifp = sc->sc_ifp; 1619 struct mbuf *m, *m2; 1620 uint64_t word1, word2, word3 __unused, word4; 1621 uint32_t rxhead; 1622 u_int idx, idx2, len, off, skip; 1623 1624 CAS_LOCK_ASSERT(sc, MA_OWNED); 1625 1626 callout_stop(&sc->sc_rx_ch); 1627 1628 #ifdef CAS_DEBUG 1629 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1630 #endif 1631 1632 #define PRINTWORD(n, delimiter) \ 1633 printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter) 1634 1635 #define SKIPASSERT(n) \ 1636 KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \ 1637 ("%s: word ## n not 0", __func__)) 1638 1639 #define WORDTOH(n) \ 1640 word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n) 1641 1642 /* 1643 * Read the completion head register once. This limits 1644 * how long the following loop can execute. 1645 */ 1646 rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD); 1647 #ifdef CAS_DEBUG 1648 CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1649 __func__, sc->sc_rxcptr, sc->sc_rxdptr, rxhead); 1650 #endif 1651 skip = 0; 1652 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1653 for (; sc->sc_rxcptr != rxhead; 1654 sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) { 1655 if (skip != 0) { 1656 SKIPASSERT(1); 1657 SKIPASSERT(2); 1658 SKIPASSERT(3); 1659 1660 --skip; 1661 goto skip; 1662 } 1663 1664 WORDTOH(1); 1665 WORDTOH(2); 1666 WORDTOH(3); 1667 WORDTOH(4); 1668 1669 #ifdef CAS_DEBUG 1670 if ((if_getflags(ifp) & IFF_DEBUG) != 0) { 1671 printf(" completion %d: ", sc->sc_rxcptr); 1672 PRINTWORD(1, '\t'); 1673 PRINTWORD(2, '\t'); 1674 PRINTWORD(3, '\t'); 1675 PRINTWORD(4, '\n'); 1676 } 1677 #endif 1678 1679 if (__predict_false( 1680 (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW || 1681 (word4 & CAS_RC4_ZERO) != 0)) { 1682 /* 1683 * The descriptor is still marked as owned, although 1684 * it is supposed to have completed. This has been 1685 * observed on some machines. Just exiting here 1686 * might leave the packet sitting around until another 1687 * one arrives to trigger a new interrupt, which is 1688 * generally undesirable, so set up a timeout. 1689 */ 1690 callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS, 1691 cas_rint_timeout, sc); 1692 break; 1693 } 1694 1695 if (__predict_false( 1696 (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) { 1697 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1698 device_printf(sc->sc_dev, 1699 "receive error: CRC error\n"); 1700 continue; 1701 } 1702 1703 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1704 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1705 ("%s: data and header present", __func__)); 1706 KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 || 1707 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1708 ("%s: split and header present", __func__)); 1709 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1710 (word1 & CAS_RC1_RELEASE_HDR) == 0, 1711 ("%s: data present but header release", __func__)); 1712 KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 || 1713 (word1 & CAS_RC1_RELEASE_DATA) == 0, 1714 ("%s: header present but data release", __func__)); 1715 1716 if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) { 1717 idx = CAS_GET(word2, CAS_RC2_HDR_INDEX); 1718 off = CAS_GET(word2, CAS_RC2_HDR_OFF); 1719 #ifdef CAS_DEBUG 1720 CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d", 1721 __func__, idx, off, len); 1722 #endif 1723 rxds = &sc->sc_rxdsoft[idx]; 1724 MGETHDR(m, M_NOWAIT, MT_DATA); 1725 if (m != NULL) { 1726 refcount_acquire(&rxds->rxds_refcount); 1727 bus_dmamap_sync(sc->sc_rdmatag, 1728 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1729 m_extadd(m, (char *)rxds->rxds_buf + 1730 off * 256 + ETHER_ALIGN, len, cas_free, 1731 sc, (void *)(uintptr_t)idx, 1732 M_RDONLY, EXT_NET_DRV); 1733 if ((m->m_flags & M_EXT) == 0) { 1734 m_freem(m); 1735 m = NULL; 1736 } 1737 } 1738 if (m != NULL) { 1739 m->m_pkthdr.rcvif = ifp; 1740 m->m_pkthdr.len = m->m_len = len; 1741 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1742 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1743 cas_rxcksum(m, CAS_GET(word4, 1744 CAS_RC4_TCP_CSUM)); 1745 /* Pass it on. */ 1746 CAS_UNLOCK(sc); 1747 if_input(ifp, m); 1748 CAS_LOCK(sc); 1749 } else 1750 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1751 1752 if ((word1 & CAS_RC1_RELEASE_HDR) != 0 && 1753 refcount_release(&rxds->rxds_refcount) != 0) 1754 cas_add_rxdesc(sc, idx); 1755 } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) { 1756 idx = CAS_GET(word1, CAS_RC1_DATA_INDEX); 1757 off = CAS_GET(word1, CAS_RC1_DATA_OFF); 1758 #ifdef CAS_DEBUG 1759 CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d", 1760 __func__, idx, off, len); 1761 #endif 1762 rxds = &sc->sc_rxdsoft[idx]; 1763 MGETHDR(m, M_NOWAIT, MT_DATA); 1764 if (m != NULL) { 1765 refcount_acquire(&rxds->rxds_refcount); 1766 off += ETHER_ALIGN; 1767 m->m_len = min(CAS_PAGE_SIZE - off, len); 1768 bus_dmamap_sync(sc->sc_rdmatag, 1769 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1770 m_extadd(m, (char *)rxds->rxds_buf + off, 1771 m->m_len, cas_free, sc, 1772 (void *)(uintptr_t)idx, M_RDONLY, 1773 EXT_NET_DRV); 1774 if ((m->m_flags & M_EXT) == 0) { 1775 m_freem(m); 1776 m = NULL; 1777 } 1778 } 1779 idx2 = 0; 1780 m2 = NULL; 1781 rxds2 = NULL; 1782 if ((word1 & CAS_RC1_SPLIT_PKT) != 0) { 1783 KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0, 1784 ("%s: split but no release next", 1785 __func__)); 1786 1787 idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX); 1788 #ifdef CAS_DEBUG 1789 CTR2(KTR_CAS, "%s: split at idx %d", 1790 __func__, idx2); 1791 #endif 1792 rxds2 = &sc->sc_rxdsoft[idx2]; 1793 if (m != NULL) { 1794 MGET(m2, M_NOWAIT, MT_DATA); 1795 if (m2 != NULL) { 1796 refcount_acquire( 1797 &rxds2->rxds_refcount); 1798 m2->m_len = len - m->m_len; 1799 bus_dmamap_sync( 1800 sc->sc_rdmatag, 1801 rxds2->rxds_dmamap, 1802 BUS_DMASYNC_POSTREAD); 1803 m_extadd(m2, 1804 (char *)rxds2->rxds_buf, 1805 m2->m_len, cas_free, sc, 1806 (void *)(uintptr_t)idx2, 1807 M_RDONLY, EXT_NET_DRV); 1808 if ((m2->m_flags & M_EXT) == 1809 0) { 1810 m_freem(m2); 1811 m2 = NULL; 1812 } 1813 } 1814 } 1815 if (m2 != NULL) 1816 m->m_next = m2; 1817 else if (m != NULL) { 1818 m_freem(m); 1819 m = NULL; 1820 } 1821 } 1822 if (m != NULL) { 1823 m->m_pkthdr.rcvif = ifp; 1824 m->m_pkthdr.len = len; 1825 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1826 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1827 cas_rxcksum(m, CAS_GET(word4, 1828 CAS_RC4_TCP_CSUM)); 1829 /* Pass it on. */ 1830 CAS_UNLOCK(sc); 1831 if_input(ifp, m); 1832 CAS_LOCK(sc); 1833 } else 1834 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1835 1836 if ((word1 & CAS_RC1_RELEASE_DATA) != 0 && 1837 refcount_release(&rxds->rxds_refcount) != 0) 1838 cas_add_rxdesc(sc, idx); 1839 if ((word1 & CAS_RC1_SPLIT_PKT) != 0 && 1840 refcount_release(&rxds2->rxds_refcount) != 0) 1841 cas_add_rxdesc(sc, idx2); 1842 } 1843 1844 skip = CAS_GET(word1, CAS_RC1_SKIP); 1845 1846 skip: 1847 cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]); 1848 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1849 break; 1850 } 1851 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1852 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr); 1853 1854 #undef PRINTWORD 1855 #undef SKIPASSERT 1856 #undef WORDTOH 1857 1858 #ifdef CAS_DEBUG 1859 CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1860 __func__, sc->sc_rxcptr, sc->sc_rxdptr, 1861 CAS_READ_4(sc, CAS_RX_COMP_HEAD)); 1862 #endif 1863 } 1864 1865 static void 1866 cas_free(struct mbuf *m) 1867 { 1868 struct cas_rxdsoft *rxds; 1869 struct cas_softc *sc; 1870 u_int idx, locked; 1871 1872 sc = m->m_ext.ext_arg1; 1873 idx = (uintptr_t)m->m_ext.ext_arg2; 1874 rxds = &sc->sc_rxdsoft[idx]; 1875 if (refcount_release(&rxds->rxds_refcount) == 0) 1876 return; 1877 1878 /* 1879 * NB: this function can be called via m_freem(9) within 1880 * this driver! 1881 */ 1882 if ((locked = CAS_LOCK_OWNED(sc)) == 0) 1883 CAS_LOCK(sc); 1884 cas_add_rxdesc(sc, idx); 1885 if (locked == 0) 1886 CAS_UNLOCK(sc); 1887 } 1888 1889 static inline void 1890 cas_add_rxdesc(struct cas_softc *sc, u_int idx) 1891 { 1892 1893 CAS_LOCK_ASSERT(sc, MA_OWNED); 1894 1895 bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap, 1896 BUS_DMASYNC_PREREAD); 1897 CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx); 1898 sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr); 1899 1900 /* 1901 * Update the RX kick register. This register has to point to the 1902 * descriptor after the last valid one (before the current batch) 1903 * and for optimum performance should be incremented in multiples 1904 * of 4 (the DMA engine fetches/updates descriptors in batches of 4). 1905 */ 1906 if ((sc->sc_rxdptr % 4) == 0) { 1907 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1908 CAS_WRITE_4(sc, CAS_RX_KICK, 1909 (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK); 1910 } 1911 } 1912 1913 static void 1914 cas_eint(struct cas_softc *sc, u_int status) 1915 { 1916 if_t ifp = sc->sc_ifp; 1917 1918 CAS_LOCK_ASSERT(sc, MA_OWNED); 1919 1920 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1921 1922 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1923 if ((status & CAS_INTR_PCI_ERROR_INT) != 0) { 1924 status = CAS_READ_4(sc, CAS_ERROR_STATUS); 1925 printf(", PCI bus error 0x%x", status); 1926 if ((status & CAS_ERROR_OTHER) != 0) { 1927 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 1928 printf(", PCI status 0x%x", status); 1929 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 1930 } 1931 } 1932 printf("\n"); 1933 1934 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1935 cas_init_locked(sc); 1936 if (!if_sendq_empty(ifp)) 1937 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 1938 } 1939 1940 static int 1941 cas_intr(void *v) 1942 { 1943 struct cas_softc *sc = v; 1944 1945 if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) & 1946 CAS_INTR_SUMMARY) == 0)) 1947 return (FILTER_STRAY); 1948 1949 /* Disable interrupts. */ 1950 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 1951 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 1952 1953 return (FILTER_HANDLED); 1954 } 1955 1956 static void 1957 cas_intr_task(void *arg, int pending __unused) 1958 { 1959 struct cas_softc *sc = arg; 1960 if_t ifp = sc->sc_ifp; 1961 uint32_t status, status2; 1962 1963 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1964 1965 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1966 return; 1967 1968 status = CAS_READ_4(sc, CAS_STATUS); 1969 if (__predict_false((status & CAS_INTR_SUMMARY) == 0)) 1970 goto done; 1971 1972 CAS_LOCK(sc); 1973 #ifdef CAS_DEBUG 1974 CTR4(KTR_CAS, "%s: %s: cplt %x, status %x", 1975 device_get_name(sc->sc_dev), __func__, 1976 (status >> CAS_STATUS_TX_COMP3_SHFT), (u_int)status); 1977 1978 /* 1979 * PCS interrupts must be cleared, otherwise no traffic is passed! 1980 */ 1981 if ((status & CAS_INTR_PCS_INT) != 0) { 1982 status2 = 1983 CAS_READ_4(sc, CAS_PCS_INTR_STATUS) | 1984 CAS_READ_4(sc, CAS_PCS_INTR_STATUS); 1985 if ((status2 & CAS_PCS_INTR_LINK) != 0) 1986 device_printf(sc->sc_dev, 1987 "%s: PCS link status changed\n", __func__); 1988 } 1989 if ((status & CAS_MAC_CTRL_STATUS) != 0) { 1990 status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS); 1991 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 1992 device_printf(sc->sc_dev, 1993 "%s: PAUSE received (PAUSE time %d slots)\n", 1994 __func__, 1995 (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >> 1996 CAS_MAC_CTRL_STATUS_PT_SHFT); 1997 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 1998 device_printf(sc->sc_dev, 1999 "%s: transited to PAUSE state\n", __func__); 2000 if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0) 2001 device_printf(sc->sc_dev, 2002 "%s: transited to non-PAUSE state\n", __func__); 2003 } 2004 if ((status & CAS_INTR_MIF) != 0) 2005 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 2006 #endif 2007 2008 if (__predict_false((status & 2009 (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 2010 CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) { 2011 cas_eint(sc, status); 2012 CAS_UNLOCK(sc); 2013 return; 2014 } 2015 2016 if (__predict_false(status & CAS_INTR_TX_MAC_INT)) { 2017 status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS); 2018 if ((status2 & 2019 (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0) 2020 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2021 else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0) 2022 device_printf(sc->sc_dev, 2023 "MAC TX fault, status %x\n", status2); 2024 } 2025 2026 if (__predict_false(status & CAS_INTR_RX_MAC_INT)) { 2027 status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS); 2028 if ((status2 & CAS_MAC_RX_OVERFLOW) != 0) 2029 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2030 else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0) 2031 device_printf(sc->sc_dev, 2032 "MAC RX fault, status %x\n", status2); 2033 } 2034 2035 if ((status & 2036 (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2037 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) { 2038 cas_rint(sc); 2039 #ifdef CAS_DEBUG 2040 if (__predict_false((status & 2041 (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2042 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0)) 2043 device_printf(sc->sc_dev, 2044 "RX fault, status %x\n", status); 2045 #endif 2046 } 2047 2048 if ((status & 2049 (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0) 2050 cas_tint(sc); 2051 2052 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2053 CAS_UNLOCK(sc); 2054 return; 2055 } else if (!if_sendq_empty(ifp)) 2056 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2057 CAS_UNLOCK(sc); 2058 2059 status = CAS_READ_4(sc, CAS_STATUS_ALIAS); 2060 if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) { 2061 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 2062 return; 2063 } 2064 2065 done: 2066 /* Re-enable interrupts. */ 2067 CAS_WRITE_4(sc, CAS_INTMASK, 2068 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 2069 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 2070 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 2071 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 2072 CAS_INTR_PCI_ERROR_INT 2073 #ifdef CAS_DEBUG 2074 | CAS_INTR_PCS_INT | CAS_INTR_MIF 2075 #endif 2076 )); 2077 } 2078 2079 static void 2080 cas_watchdog(struct cas_softc *sc) 2081 { 2082 if_t ifp = sc->sc_ifp; 2083 2084 CAS_LOCK_ASSERT(sc, MA_OWNED); 2085 2086 #ifdef CAS_DEBUG 2087 CTR4(KTR_CAS, 2088 "%s: CAS_RX_CONF %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONF %x", 2089 __func__, CAS_READ_4(sc, CAS_RX_CONF), 2090 CAS_READ_4(sc, CAS_MAC_RX_STATUS), 2091 CAS_READ_4(sc, CAS_MAC_RX_CONF)); 2092 CTR4(KTR_CAS, 2093 "%s: CAS_TX_CONF %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONF %x", 2094 __func__, CAS_READ_4(sc, CAS_TX_CONF), 2095 CAS_READ_4(sc, CAS_MAC_TX_STATUS), 2096 CAS_READ_4(sc, CAS_MAC_TX_CONF)); 2097 #endif 2098 2099 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 2100 return; 2101 2102 if ((sc->sc_flags & CAS_LINK) != 0) 2103 device_printf(sc->sc_dev, "device timeout\n"); 2104 else if (bootverbose) 2105 device_printf(sc->sc_dev, "device timeout (no link)\n"); 2106 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2107 2108 /* Try to get more packets going. */ 2109 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2110 cas_init_locked(sc); 2111 if (!if_sendq_empty(ifp)) 2112 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2113 } 2114 2115 static void 2116 cas_mifinit(struct cas_softc *sc) 2117 { 2118 2119 /* Configure the MIF in frame mode. */ 2120 CAS_WRITE_4(sc, CAS_MIF_CONF, 2121 CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE); 2122 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 2123 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2124 } 2125 2126 /* 2127 * MII interface 2128 * 2129 * The MII interface supports at least three different operating modes: 2130 * 2131 * Bitbang mode is implemented using data, clock and output enable registers. 2132 * 2133 * Frame mode is implemented by loading a complete frame into the frame 2134 * register and polling the valid bit for completion. 2135 * 2136 * Polling mode uses the frame register but completion is indicated by 2137 * an interrupt. 2138 * 2139 */ 2140 static int 2141 cas_mii_readreg(device_t dev, int phy, int reg) 2142 { 2143 struct cas_softc *sc; 2144 int n; 2145 uint32_t v; 2146 2147 #ifdef CAS_DEBUG_PHY 2148 printf("%s: phy %d reg %d\n", __func__, phy, reg); 2149 #endif 2150 2151 sc = device_get_softc(dev); 2152 if ((sc->sc_flags & CAS_SERDES) != 0) { 2153 switch (reg) { 2154 case MII_BMCR: 2155 reg = CAS_PCS_CTRL; 2156 break; 2157 case MII_BMSR: 2158 reg = CAS_PCS_STATUS; 2159 break; 2160 case MII_PHYIDR1: 2161 case MII_PHYIDR2: 2162 return (0); 2163 case MII_ANAR: 2164 reg = CAS_PCS_ANAR; 2165 break; 2166 case MII_ANLPAR: 2167 reg = CAS_PCS_ANLPAR; 2168 break; 2169 case MII_EXTSR: 2170 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 2171 default: 2172 device_printf(sc->sc_dev, 2173 "%s: unhandled register %d\n", __func__, reg); 2174 return (0); 2175 } 2176 return (CAS_READ_4(sc, reg)); 2177 } 2178 2179 /* Construct the frame command. */ 2180 v = CAS_MIF_FRAME_READ | 2181 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2182 (reg << CAS_MIF_FRAME_REG_SHFT); 2183 2184 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2185 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2186 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2187 for (n = 0; n < 100; n++) { 2188 DELAY(1); 2189 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2190 if (v & CAS_MIF_FRAME_TA_LSB) 2191 return (v & CAS_MIF_FRAME_DATA); 2192 } 2193 2194 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2195 return (0); 2196 } 2197 2198 static int 2199 cas_mii_writereg(device_t dev, int phy, int reg, int val) 2200 { 2201 struct cas_softc *sc; 2202 int n; 2203 uint32_t v; 2204 2205 #ifdef CAS_DEBUG_PHY 2206 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 2207 #endif 2208 2209 sc = device_get_softc(dev); 2210 if ((sc->sc_flags & CAS_SERDES) != 0) { 2211 switch (reg) { 2212 case MII_BMSR: 2213 reg = CAS_PCS_STATUS; 2214 break; 2215 case MII_BMCR: 2216 reg = CAS_PCS_CTRL; 2217 if ((val & CAS_PCS_CTRL_RESET) == 0) 2218 break; 2219 CAS_WRITE_4(sc, CAS_PCS_CTRL, val); 2220 CAS_BARRIER(sc, CAS_PCS_CTRL, 4, 2221 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2222 if (!cas_bitwait(sc, CAS_PCS_CTRL, 2223 CAS_PCS_CTRL_RESET, 0)) 2224 device_printf(sc->sc_dev, 2225 "cannot reset PCS\n"); 2226 /* FALLTHROUGH */ 2227 case MII_ANAR: 2228 CAS_WRITE_4(sc, CAS_PCS_CONF, 0); 2229 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2230 BUS_SPACE_BARRIER_WRITE); 2231 CAS_WRITE_4(sc, CAS_PCS_ANAR, val); 2232 CAS_BARRIER(sc, CAS_PCS_ANAR, 4, 2233 BUS_SPACE_BARRIER_WRITE); 2234 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, 2235 CAS_PCS_SERDES_CTRL_ESD); 2236 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2237 BUS_SPACE_BARRIER_WRITE); 2238 CAS_WRITE_4(sc, CAS_PCS_CONF, 2239 CAS_PCS_CONF_EN); 2240 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2241 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2242 return (0); 2243 case MII_ANLPAR: 2244 reg = CAS_PCS_ANLPAR; 2245 break; 2246 default: 2247 device_printf(sc->sc_dev, 2248 "%s: unhandled register %d\n", __func__, reg); 2249 return (0); 2250 } 2251 CAS_WRITE_4(sc, reg, val); 2252 CAS_BARRIER(sc, reg, 4, 2253 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2254 return (0); 2255 } 2256 2257 /* Construct the frame command. */ 2258 v = CAS_MIF_FRAME_WRITE | 2259 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2260 (reg << CAS_MIF_FRAME_REG_SHFT) | 2261 (val & CAS_MIF_FRAME_DATA); 2262 2263 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2264 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2265 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2266 for (n = 0; n < 100; n++) { 2267 DELAY(1); 2268 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2269 if (v & CAS_MIF_FRAME_TA_LSB) 2270 return (1); 2271 } 2272 2273 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2274 return (0); 2275 } 2276 2277 static void 2278 cas_mii_statchg(device_t dev) 2279 { 2280 struct cas_softc *sc; 2281 if_t ifp; 2282 int gigabit; 2283 uint32_t rxcfg, txcfg, v; 2284 2285 sc = device_get_softc(dev); 2286 ifp = sc->sc_ifp; 2287 2288 CAS_LOCK_ASSERT(sc, MA_OWNED); 2289 2290 #ifdef CAS_DEBUG 2291 if ((if_getflags(ifp) & IFF_DEBUG) != 0) 2292 device_printf(sc->sc_dev, "%s: status changen", __func__); 2293 #endif 2294 2295 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2296 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2297 sc->sc_flags |= CAS_LINK; 2298 else 2299 sc->sc_flags &= ~CAS_LINK; 2300 2301 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2302 case IFM_1000_SX: 2303 case IFM_1000_LX: 2304 case IFM_1000_CX: 2305 case IFM_1000_T: 2306 gigabit = 1; 2307 break; 2308 default: 2309 gigabit = 0; 2310 } 2311 2312 /* 2313 * The configuration done here corresponds to the steps F) and 2314 * G) and as far as enabling of RX and TX MAC goes also step H) 2315 * of the initialization sequence outlined in section 11.2.1 of 2316 * the Cassini+ ASIC Specification. 2317 */ 2318 2319 rxcfg = sc->sc_mac_rxcfg; 2320 rxcfg &= ~CAS_MAC_RX_CONF_CARR; 2321 txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU | 2322 CAS_MAC_TX_CONF_NGUL; 2323 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2324 txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS; 2325 else if (gigabit != 0) { 2326 rxcfg |= CAS_MAC_RX_CONF_CARR; 2327 txcfg |= CAS_MAC_TX_CONF_CARR; 2328 } 2329 (void)cas_disable_tx(sc); 2330 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg); 2331 (void)cas_disable_rx(sc); 2332 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg); 2333 2334 v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) & 2335 ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP); 2336 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2337 IFM_ETH_RXPAUSE) != 0) 2338 v |= CAS_MAC_CTRL_CONF_RXP; 2339 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2340 IFM_ETH_TXPAUSE) != 0) 2341 v |= CAS_MAC_CTRL_CONF_TXP; 2342 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v); 2343 2344 /* 2345 * All supported chips have a bug causing incorrect checksum 2346 * to be calculated when letting them strip the FCS in half- 2347 * duplex mode. In theory we could disable FCS stripping and 2348 * manually adjust the checksum accordingly. It seems to make 2349 * more sense to optimze for the common case and just disable 2350 * hardware checksumming in half-duplex mode though. 2351 */ 2352 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) { 2353 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM); 2354 if_sethwassist(ifp, 0); 2355 } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 2356 if_setcapenable(ifp, if_getcapabilities(ifp)); 2357 if_sethwassist(ifp, CAS_CSUM_FEATURES); 2358 } 2359 2360 if (sc->sc_variant == CAS_SATURN) { 2361 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2362 /* silicon bug workaround */ 2363 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41); 2364 else 2365 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 2366 } 2367 2368 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2369 gigabit != 0) 2370 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2371 CAS_MAC_SLOT_TIME_CARR); 2372 else 2373 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2374 CAS_MAC_SLOT_TIME_NORM); 2375 2376 /* XIF Configuration */ 2377 v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED; 2378 if ((sc->sc_flags & CAS_SERDES) == 0) { 2379 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2380 v |= CAS_MAC_XIF_CONF_NOECHO; 2381 v |= CAS_MAC_XIF_CONF_BUF_OE; 2382 } 2383 if (gigabit != 0) 2384 v |= CAS_MAC_XIF_CONF_GMII; 2385 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2386 v |= CAS_MAC_XIF_CONF_FDXLED; 2387 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v); 2388 2389 sc->sc_mac_rxcfg = rxcfg; 2390 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 2391 (sc->sc_flags & CAS_LINK) != 0) { 2392 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 2393 txcfg | CAS_MAC_TX_CONF_EN); 2394 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 2395 rxcfg | CAS_MAC_RX_CONF_EN); 2396 } 2397 } 2398 2399 static int 2400 cas_mediachange(if_t ifp) 2401 { 2402 struct cas_softc *sc = if_getsoftc(ifp); 2403 int error; 2404 2405 /* XXX add support for serial media. */ 2406 2407 CAS_LOCK(sc); 2408 error = mii_mediachg(sc->sc_mii); 2409 CAS_UNLOCK(sc); 2410 return (error); 2411 } 2412 2413 static void 2414 cas_mediastatus(if_t ifp, struct ifmediareq *ifmr) 2415 { 2416 struct cas_softc *sc = if_getsoftc(ifp); 2417 2418 CAS_LOCK(sc); 2419 if ((if_getflags(ifp) & IFF_UP) == 0) { 2420 CAS_UNLOCK(sc); 2421 return; 2422 } 2423 2424 mii_pollstat(sc->sc_mii); 2425 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2426 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2427 CAS_UNLOCK(sc); 2428 } 2429 2430 static int 2431 cas_ioctl(if_t ifp, u_long cmd, caddr_t data) 2432 { 2433 struct cas_softc *sc = if_getsoftc(ifp); 2434 struct ifreq *ifr = (struct ifreq *)data; 2435 int error; 2436 2437 error = 0; 2438 switch (cmd) { 2439 case SIOCSIFFLAGS: 2440 CAS_LOCK(sc); 2441 if ((if_getflags(ifp) & IFF_UP) != 0) { 2442 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 2443 ((if_getflags(ifp) ^ sc->sc_ifflags) & 2444 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2445 cas_setladrf(sc); 2446 else 2447 cas_init_locked(sc); 2448 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2449 cas_stop(ifp); 2450 sc->sc_ifflags = if_getflags(ifp); 2451 CAS_UNLOCK(sc); 2452 break; 2453 case SIOCSIFCAP: 2454 CAS_LOCK(sc); 2455 if ((sc->sc_flags & CAS_NO_CSUM) != 0) { 2456 error = EINVAL; 2457 CAS_UNLOCK(sc); 2458 break; 2459 } 2460 if_setcapenable(ifp, ifr->ifr_reqcap); 2461 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2462 if_sethwassist(ifp, CAS_CSUM_FEATURES); 2463 else 2464 if_sethwassist(ifp, 0); 2465 CAS_UNLOCK(sc); 2466 break; 2467 case SIOCADDMULTI: 2468 case SIOCDELMULTI: 2469 CAS_LOCK(sc); 2470 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2471 cas_setladrf(sc); 2472 CAS_UNLOCK(sc); 2473 break; 2474 case SIOCSIFMTU: 2475 if ((ifr->ifr_mtu < ETHERMIN) || 2476 (ifr->ifr_mtu > ETHERMTU_JUMBO)) 2477 error = EINVAL; 2478 else 2479 if_setmtu(ifp, ifr->ifr_mtu); 2480 break; 2481 case SIOCGIFMEDIA: 2482 case SIOCSIFMEDIA: 2483 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2484 break; 2485 default: 2486 error = ether_ioctl(ifp, cmd, data); 2487 break; 2488 } 2489 2490 return (error); 2491 } 2492 2493 static u_int 2494 cas_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2495 { 2496 uint32_t crc, *hash = arg; 2497 2498 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN); 2499 /* We just want the 8 most significant bits. */ 2500 crc >>= 24; 2501 /* Set the corresponding bit in the filter. */ 2502 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2503 2504 return (1); 2505 } 2506 2507 static void 2508 cas_setladrf(struct cas_softc *sc) 2509 { 2510 if_t ifp = sc->sc_ifp; 2511 int i; 2512 uint32_t hash[16]; 2513 uint32_t v; 2514 2515 CAS_LOCK_ASSERT(sc, MA_OWNED); 2516 2517 /* 2518 * Turn off the RX MAC and the hash filter as required by the Sun 2519 * Cassini programming restrictions. 2520 */ 2521 v = sc->sc_mac_rxcfg & ~(CAS_MAC_RX_CONF_HFILTER | 2522 CAS_MAC_RX_CONF_EN); 2523 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2524 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2525 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2526 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER | 2527 CAS_MAC_RX_CONF_EN, 0)) 2528 device_printf(sc->sc_dev, 2529 "cannot disable RX MAC or hash filter\n"); 2530 2531 v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_PGRP); 2532 if ((if_getflags(ifp) & IFF_PROMISC) != 0) { 2533 v |= CAS_MAC_RX_CONF_PROMISC; 2534 goto chipit; 2535 } 2536 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) { 2537 v |= CAS_MAC_RX_CONF_PGRP; 2538 goto chipit; 2539 } 2540 2541 /* 2542 * Set up multicast address filter by passing all multicast 2543 * addresses through a crc generator, and then using the high 2544 * order 8 bits as an index into the 256 bit logical address 2545 * filter. The high order 4 bits selects the word, while the 2546 * other 4 bits select the bit within the word (where bit 0 2547 * is the MSB). 2548 */ 2549 2550 memset(hash, 0, sizeof(hash)); 2551 if_foreach_llmaddr(ifp, cas_hash_maddr, &hash); 2552 2553 v |= CAS_MAC_RX_CONF_HFILTER; 2554 2555 /* Now load the hash table into the chip (if we are using it). */ 2556 for (i = 0; i < 16; i++) 2557 CAS_WRITE_4(sc, 2558 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2559 hash[i]); 2560 2561 chipit: 2562 sc->sc_mac_rxcfg = v; 2563 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN); 2564 } 2565 2566 static int cas_pci_attach(device_t dev); 2567 static int cas_pci_detach(device_t dev); 2568 static int cas_pci_probe(device_t dev); 2569 static int cas_pci_resume(device_t dev); 2570 static int cas_pci_suspend(device_t dev); 2571 2572 static device_method_t cas_pci_methods[] = { 2573 /* Device interface */ 2574 DEVMETHOD(device_probe, cas_pci_probe), 2575 DEVMETHOD(device_attach, cas_pci_attach), 2576 DEVMETHOD(device_detach, cas_pci_detach), 2577 DEVMETHOD(device_suspend, cas_pci_suspend), 2578 DEVMETHOD(device_resume, cas_pci_resume), 2579 /* Use the suspend handler here, it is all that is required. */ 2580 DEVMETHOD(device_shutdown, cas_pci_suspend), 2581 2582 /* MII interface */ 2583 DEVMETHOD(miibus_readreg, cas_mii_readreg), 2584 DEVMETHOD(miibus_writereg, cas_mii_writereg), 2585 DEVMETHOD(miibus_statchg, cas_mii_statchg), 2586 2587 DEVMETHOD_END 2588 }; 2589 2590 static driver_t cas_pci_driver = { 2591 "cas", 2592 cas_pci_methods, 2593 sizeof(struct cas_softc) 2594 }; 2595 2596 static const struct cas_pci_dev { 2597 uint32_t cpd_devid; 2598 uint8_t cpd_revid; 2599 int cpd_variant; 2600 const char *cpd_desc; 2601 } cas_pci_devlist[] = { 2602 { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" }, 2603 { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" }, 2604 { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" }, 2605 { 0, 0, 0, NULL } 2606 }; 2607 2608 DRIVER_MODULE(cas, pci, cas_pci_driver, 0, 0); 2609 MODULE_PNP_INFO("W32:vendor/device", pci, cas, cas_pci_devlist, 2610 nitems(cas_pci_devlist) - 1); 2611 DRIVER_MODULE(miibus, cas, miibus_driver, 0, 0); 2612 MODULE_DEPEND(cas, pci, 1, 1, 1); 2613 2614 static int 2615 cas_pci_probe(device_t dev) 2616 { 2617 int i; 2618 2619 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2620 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2621 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2622 device_set_desc(dev, cas_pci_devlist[i].cpd_desc); 2623 return (BUS_PROBE_DEFAULT); 2624 } 2625 } 2626 2627 return (ENXIO); 2628 } 2629 2630 static struct resource_spec cas_pci_res_spec[] = { 2631 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */ 2632 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */ 2633 { -1, 0 } 2634 }; 2635 2636 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 2637 #define CAS_PHY_INTERFACE "phy-interface" 2638 #define CAS_PHY_TYPE "phy-type" 2639 #define CAS_PHY_TYPE_PCS "pcs" 2640 2641 static int 2642 cas_pci_attach(device_t dev) 2643 { 2644 char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)]; 2645 struct cas_softc *sc; 2646 int i; 2647 #if !defined(__powerpc__) 2648 u_char enaddr[4][ETHER_ADDR_LEN]; 2649 u_int j, k, lma, pcs[4], phy; 2650 #endif 2651 2652 sc = device_get_softc(dev); 2653 sc->sc_variant = CAS_UNKNOWN; 2654 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2655 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2656 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2657 sc->sc_variant = cas_pci_devlist[i].cpd_variant; 2658 break; 2659 } 2660 } 2661 if (sc->sc_variant == CAS_UNKNOWN) { 2662 device_printf(dev, "unknown adaptor\n"); 2663 return (ENXIO); 2664 } 2665 2666 /* PCI configuration */ 2667 pci_write_config(dev, PCIR_COMMAND, 2668 pci_read_config(dev, PCIR_COMMAND, 2) | PCIM_CMD_BUSMASTEREN | 2669 PCIM_CMD_MWRICEN | PCIM_CMD_PERRESPEN | PCIM_CMD_SERRESPEN, 2); 2670 2671 sc->sc_dev = dev; 2672 if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02) 2673 /* Hardware checksumming may hang TX. */ 2674 sc->sc_flags |= CAS_NO_CSUM; 2675 if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN) 2676 sc->sc_flags |= CAS_REG_PLUS; 2677 if (sc->sc_variant == CAS_CAS || 2678 (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11)) 2679 sc->sc_flags |= CAS_TABORT; 2680 if (bootverbose) 2681 device_printf(dev, "flags=0x%x\n", sc->sc_flags); 2682 2683 if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) { 2684 device_printf(dev, "failed to allocate resources\n"); 2685 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2686 return (ENXIO); 2687 } 2688 2689 CAS_LOCK_INIT(sc, device_get_nameunit(dev)); 2690 2691 #if defined(__powerpc__) 2692 OF_getetheraddr(dev, sc->sc_enaddr); 2693 if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf, 2694 sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev), 2695 CAS_PHY_TYPE, buf, sizeof(buf)) > 0) { 2696 buf[sizeof(buf) - 1] = '\0'; 2697 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2698 sc->sc_flags |= CAS_SERDES; 2699 } 2700 #else 2701 /* 2702 * Dig out VPD (vital product data) and read the MAC address as well 2703 * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI 2704 * FCode) and can't be accessed via the PCI capability pointer. 2705 * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described 2706 * in the free US Patent 7149820. 2707 */ 2708 2709 #define PCI_ROMHDR_SIZE 0x1c 2710 #define PCI_ROMHDR_SIG 0x00 2711 #define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */ 2712 #define PCI_ROMHDR_PTR_DATA 0x18 2713 #define PCI_ROM_SIZE 0x18 2714 #define PCI_ROM_SIG 0x00 2715 #define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */ 2716 /* reversed */ 2717 #define PCI_ROM_VENDOR 0x04 2718 #define PCI_ROM_DEVICE 0x06 2719 #define PCI_ROM_PTR_VPD 0x08 2720 #define PCI_VPDRES_BYTE0 0x00 2721 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 2722 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 2723 #define PCI_VPDRES_LARGE_LEN_LSB 0x01 2724 #define PCI_VPDRES_LARGE_LEN_MSB 0x02 2725 #define PCI_VPDRES_LARGE_SIZE 0x03 2726 #define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */ 2727 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 2728 #define PCI_VPD_KEY0 0x00 2729 #define PCI_VPD_KEY1 0x01 2730 #define PCI_VPD_LEN 0x02 2731 #define PCI_VPD_SIZE 0x03 2732 2733 #define CAS_ROM_READ_1(sc, offs) \ 2734 CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs)) 2735 #define CAS_ROM_READ_2(sc, offs) \ 2736 CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs)) 2737 #define CAS_ROM_READ_4(sc, offs) \ 2738 CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs)) 2739 2740 lma = phy = 0; 2741 memset(enaddr, 0, sizeof(enaddr)); 2742 memset(pcs, 0, sizeof(pcs)); 2743 2744 /* Enable PCI Expansion ROM access. */ 2745 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 2746 CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM); 2747 2748 /* Read PCI Expansion ROM header. */ 2749 if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC || 2750 (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < 2751 PCI_ROMHDR_SIZE) { 2752 device_printf(dev, "unexpected PCI Expansion ROM header\n"); 2753 goto fail_prom; 2754 } 2755 2756 /* Read PCI Expansion ROM data. */ 2757 if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC || 2758 CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) || 2759 CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) || 2760 (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < 2761 i + PCI_ROM_SIZE) { 2762 device_printf(dev, "unexpected PCI Expansion ROM data\n"); 2763 goto fail_prom; 2764 } 2765 2766 /* Read PCI VPD. */ 2767 next: 2768 if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc, 2769 j + PCI_VPDRES_BYTE0)) == 0) { 2770 device_printf(dev, "no large PCI VPD\n"); 2771 goto fail_prom; 2772 } 2773 2774 i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) | 2775 CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB); 2776 switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc, 2777 j + PCI_VPDRES_BYTE0))) { 2778 case PCI_VPDRES_TYPE_ID_STRING: 2779 /* Skip identifier string. */ 2780 j += PCI_VPDRES_LARGE_SIZE + i; 2781 goto next; 2782 case PCI_VPDRES_TYPE_VPD: 2783 for (j += PCI_VPDRES_LARGE_SIZE; i > 0; 2784 i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN), 2785 j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) { 2786 if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z') 2787 /* no Enhanced VPD */ 2788 continue; 2789 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I') 2790 /* no instance property */ 2791 continue; 2792 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') { 2793 /* byte array */ 2794 if (CAS_ROM_READ_1(sc, 2795 j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN) 2796 continue; 2797 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2798 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2799 buf, sizeof(buf)); 2800 buf[sizeof(buf) - 1] = '\0'; 2801 if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0) 2802 continue; 2803 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2804 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2805 5 + sizeof(CAS_LOCAL_MAC_ADDRESS), 2806 enaddr[lma], sizeof(enaddr[lma])); 2807 lma++; 2808 if (lma == 4 && phy == 4) 2809 break; 2810 } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 2811 'S') { 2812 /* string */ 2813 if (CAS_ROM_READ_1(sc, 2814 j + PCI_VPD_SIZE + 4) != 2815 sizeof(CAS_PHY_TYPE_PCS)) 2816 continue; 2817 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2818 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2819 buf, sizeof(buf)); 2820 buf[sizeof(buf) - 1] = '\0'; 2821 if (strcmp(buf, CAS_PHY_INTERFACE) == 0) 2822 k = sizeof(CAS_PHY_INTERFACE); 2823 else if (strcmp(buf, CAS_PHY_TYPE) == 0) 2824 k = sizeof(CAS_PHY_TYPE); 2825 else 2826 continue; 2827 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2828 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2829 5 + k, buf, sizeof(buf)); 2830 buf[sizeof(buf) - 1] = '\0'; 2831 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2832 pcs[phy] = 1; 2833 phy++; 2834 if (lma == 4 && phy == 4) 2835 break; 2836 } 2837 } 2838 break; 2839 default: 2840 device_printf(dev, "unexpected PCI VPD\n"); 2841 goto fail_prom; 2842 } 2843 2844 fail_prom: 2845 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0); 2846 2847 if (lma == 0) { 2848 device_printf(dev, "could not determine Ethernet address\n"); 2849 goto fail; 2850 } 2851 i = 0; 2852 if (lma > 1 && pci_get_slot(dev) < nitems(enaddr)) 2853 i = pci_get_slot(dev); 2854 memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN); 2855 2856 if (phy == 0) { 2857 device_printf(dev, "could not determine PHY type\n"); 2858 goto fail; 2859 } 2860 i = 0; 2861 if (phy > 1 && pci_get_slot(dev) < nitems(pcs)) 2862 i = pci_get_slot(dev); 2863 if (pcs[i] != 0) 2864 sc->sc_flags |= CAS_SERDES; 2865 #endif 2866 2867 if (cas_attach(sc) != 0) { 2868 device_printf(dev, "could not be attached\n"); 2869 goto fail; 2870 } 2871 2872 if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET | 2873 INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) { 2874 device_printf(dev, "failed to set up interrupt\n"); 2875 cas_detach(sc); 2876 goto fail; 2877 } 2878 return (0); 2879 2880 fail: 2881 CAS_LOCK_DESTROY(sc); 2882 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2883 return (ENXIO); 2884 } 2885 2886 static int 2887 cas_pci_detach(device_t dev) 2888 { 2889 struct cas_softc *sc; 2890 2891 sc = device_get_softc(dev); 2892 bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih); 2893 cas_detach(sc); 2894 CAS_LOCK_DESTROY(sc); 2895 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2896 return (0); 2897 } 2898 2899 static int 2900 cas_pci_suspend(device_t dev) 2901 { 2902 2903 cas_suspend(device_get_softc(dev)); 2904 return (0); 2905 } 2906 2907 static int 2908 cas_pci_resume(device_t dev) 2909 { 2910 2911 cas_resume(device_get_softc(dev)); 2912 return (0); 2913 } 2914