1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012-2014 Thomas Skibo <thomasskibo@yahoo.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * A network interface driver for Cadence GEM Gigabit Ethernet 31 * interface such as the one used in Xilinx Zynq-7000 SoC. 32 * 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 34 * (v1.4) November 16, 2012. Xilinx doc UG585. GEM is covered in Ch. 16 35 * and register definitions are in appendix B.18. 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/mbuf.h> 47 #include <sys/module.h> 48 #include <sys/rman.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/sysctl.h> 52 53 #include <machine/bus.h> 54 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_arp.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_mib.h> 61 #include <net/if_types.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #endif 69 70 #include <net/bpf.h> 71 #include <net/bpfdesc.h> 72 73 #include <dev/fdt/fdt_common.h> 74 #include <dev/ofw/ofw_bus.h> 75 #include <dev/ofw/ofw_bus_subr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 80 #include <dev/cadence/if_cgem_hw.h> 81 82 #include "miibus_if.h" 83 84 #define IF_CGEM_NAME "cgem" 85 86 #define CGEM_NUM_RX_DESCS 512 /* size of receive descriptor ring */ 87 #define CGEM_NUM_TX_DESCS 512 /* size of transmit descriptor ring */ 88 89 #define MAX_DESC_RING_SIZE (MAX(CGEM_NUM_RX_DESCS*sizeof(struct cgem_rx_desc),\ 90 CGEM_NUM_TX_DESCS*sizeof(struct cgem_tx_desc))) 91 92 93 /* Default for sysctl rxbufs. Must be < CGEM_NUM_RX_DESCS of course. */ 94 #define DEFAULT_NUM_RX_BUFS 256 /* number of receive bufs to queue. */ 95 96 #define TX_MAX_DMA_SEGS 8 /* maximum segs in a tx mbuf dma */ 97 98 #define CGEM_CKSUM_ASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP | \ 99 CSUM_TCP_IPV6 | CSUM_UDP_IPV6) 100 101 static struct ofw_compat_data compat_data[] = { 102 { "cadence,gem", 1 }, 103 { "cdns,macb", 1 }, 104 { "sifive,fu540-c000-gem", 1 }, 105 { NULL, 0 }, 106 }; 107 108 struct cgem_softc { 109 if_t ifp; 110 struct mtx sc_mtx; 111 device_t dev; 112 device_t miibus; 113 u_int mii_media_active; /* last active media */ 114 int if_old_flags; 115 struct resource *mem_res; 116 struct resource *irq_res; 117 void *intrhand; 118 struct callout tick_ch; 119 uint32_t net_ctl_shadow; 120 int ref_clk_num; 121 u_char eaddr[6]; 122 123 bus_dma_tag_t desc_dma_tag; 124 bus_dma_tag_t mbuf_dma_tag; 125 126 /* receive descriptor ring */ 127 struct cgem_rx_desc *rxring; 128 bus_addr_t rxring_physaddr; 129 struct mbuf *rxring_m[CGEM_NUM_RX_DESCS]; 130 bus_dmamap_t rxring_m_dmamap[CGEM_NUM_RX_DESCS]; 131 int rxring_hd_ptr; /* where to put rcv bufs */ 132 int rxring_tl_ptr; /* where to get receives */ 133 int rxring_queued; /* how many rcv bufs queued */ 134 bus_dmamap_t rxring_dma_map; 135 int rxbufs; /* tunable number rcv bufs */ 136 int rxhangwar; /* rx hang work-around */ 137 u_int rxoverruns; /* rx overruns */ 138 u_int rxnobufs; /* rx buf ring empty events */ 139 u_int rxdmamapfails; /* rx dmamap failures */ 140 uint32_t rx_frames_prev; 141 142 /* transmit descriptor ring */ 143 struct cgem_tx_desc *txring; 144 bus_addr_t txring_physaddr; 145 struct mbuf *txring_m[CGEM_NUM_TX_DESCS]; 146 bus_dmamap_t txring_m_dmamap[CGEM_NUM_TX_DESCS]; 147 int txring_hd_ptr; /* where to put next xmits */ 148 int txring_tl_ptr; /* next xmit mbuf to free */ 149 int txring_queued; /* num xmits segs queued */ 150 bus_dmamap_t txring_dma_map; 151 u_int txfull; /* tx ring full events */ 152 u_int txdefrags; /* tx calls to m_defrag() */ 153 u_int txdefragfails; /* tx m_defrag() failures */ 154 u_int txdmamapfails; /* tx dmamap failures */ 155 156 /* hardware provided statistics */ 157 struct cgem_hw_stats { 158 uint64_t tx_bytes; 159 uint32_t tx_frames; 160 uint32_t tx_frames_bcast; 161 uint32_t tx_frames_multi; 162 uint32_t tx_frames_pause; 163 uint32_t tx_frames_64b; 164 uint32_t tx_frames_65to127b; 165 uint32_t tx_frames_128to255b; 166 uint32_t tx_frames_256to511b; 167 uint32_t tx_frames_512to1023b; 168 uint32_t tx_frames_1024to1536b; 169 uint32_t tx_under_runs; 170 uint32_t tx_single_collisn; 171 uint32_t tx_multi_collisn; 172 uint32_t tx_excsv_collisn; 173 uint32_t tx_late_collisn; 174 uint32_t tx_deferred_frames; 175 uint32_t tx_carrier_sense_errs; 176 177 uint64_t rx_bytes; 178 uint32_t rx_frames; 179 uint32_t rx_frames_bcast; 180 uint32_t rx_frames_multi; 181 uint32_t rx_frames_pause; 182 uint32_t rx_frames_64b; 183 uint32_t rx_frames_65to127b; 184 uint32_t rx_frames_128to255b; 185 uint32_t rx_frames_256to511b; 186 uint32_t rx_frames_512to1023b; 187 uint32_t rx_frames_1024to1536b; 188 uint32_t rx_frames_undersize; 189 uint32_t rx_frames_oversize; 190 uint32_t rx_frames_jabber; 191 uint32_t rx_frames_fcs_errs; 192 uint32_t rx_frames_length_errs; 193 uint32_t rx_symbol_errs; 194 uint32_t rx_align_errs; 195 uint32_t rx_resource_errs; 196 uint32_t rx_overrun_errs; 197 uint32_t rx_ip_hdr_csum_errs; 198 uint32_t rx_tcp_csum_errs; 199 uint32_t rx_udp_csum_errs; 200 } stats; 201 }; 202 203 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) 204 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) 205 #define BARRIER(sc, off, len, flags) \ 206 (bus_barrier((sc)->mem_res, (off), (len), (flags)) 207 208 #define CGEM_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 209 #define CGEM_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 210 #define CGEM_LOCK_INIT(sc) mtx_init(&(sc)->sc_mtx, \ 211 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 212 #define CGEM_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) 213 #define CGEM_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 214 215 /* Allow platforms to optionally provide a way to set the reference clock. */ 216 int cgem_set_ref_clk(int unit, int frequency); 217 218 static devclass_t cgem_devclass; 219 220 static int cgem_probe(device_t dev); 221 static int cgem_attach(device_t dev); 222 static int cgem_detach(device_t dev); 223 static void cgem_tick(void *); 224 static void cgem_intr(void *); 225 226 static void cgem_mediachange(struct cgem_softc *, struct mii_data *); 227 228 static void 229 cgem_get_mac(struct cgem_softc *sc, u_char eaddr[]) 230 { 231 int i; 232 uint32_t rnd; 233 234 /* See if boot loader gave us a MAC address already. */ 235 for (i = 0; i < 4; i++) { 236 uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i)); 237 uint32_t high = RD4(sc, CGEM_SPEC_ADDR_HI(i)) & 0xffff; 238 if (low != 0 || high != 0) { 239 eaddr[0] = low & 0xff; 240 eaddr[1] = (low >> 8) & 0xff; 241 eaddr[2] = (low >> 16) & 0xff; 242 eaddr[3] = (low >> 24) & 0xff; 243 eaddr[4] = high & 0xff; 244 eaddr[5] = (high >> 8) & 0xff; 245 break; 246 } 247 } 248 249 /* No MAC from boot loader? Assign a random one. */ 250 if (i == 4) { 251 rnd = arc4random(); 252 253 eaddr[0] = 'b'; 254 eaddr[1] = 's'; 255 eaddr[2] = 'd'; 256 eaddr[3] = (rnd >> 16) & 0xff; 257 eaddr[4] = (rnd >> 8) & 0xff; 258 eaddr[5] = rnd & 0xff; 259 260 device_printf(sc->dev, "no mac address found, assigning " 261 "random: %02x:%02x:%02x:%02x:%02x:%02x\n", eaddr[0], 262 eaddr[1], eaddr[2], eaddr[3], eaddr[4], eaddr[5]); 263 } 264 265 /* Move address to first slot and zero out the rest. */ 266 WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) | 267 (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0]); 268 WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]); 269 270 for (i = 1; i < 4; i++) { 271 WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0); 272 WR4(sc, CGEM_SPEC_ADDR_HI(i), 0); 273 } 274 } 275 276 /* 277 * cgem_mac_hash(): map 48-bit address to a 6-bit hash. The 6-bit hash 278 * corresponds to a bit in a 64-bit hash register. Setting that bit in the hash 279 * register enables reception of all frames with a destination address that 280 * hashes to that 6-bit value. 281 * 282 * The hash function is described in sec. 16.2.3 in the Zynq-7000 Tech 283 * Reference Manual. Bits 0-5 in the hash are the exclusive-or of 284 * every sixth bit in the destination address. 285 */ 286 static int 287 cgem_mac_hash(u_char eaddr[]) 288 { 289 int hash; 290 int i, j; 291 292 hash = 0; 293 for (i = 0; i < 6; i++) 294 for (j = i; j < 48; j += 6) 295 if ((eaddr[j >> 3] & (1 << (j & 7))) != 0) 296 hash ^= (1 << i); 297 298 return hash; 299 } 300 301 static u_int 302 cgem_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 303 { 304 uint32_t *hashes = arg; 305 int index; 306 307 index = cgem_mac_hash(LLADDR(sdl)); 308 if (index > 31) 309 hashes[0] |= (1U << (index - 32)); 310 else 311 hashes[1] |= (1U << index); 312 313 return (1); 314 } 315 316 /* 317 * After any change in rx flags or multi-cast addresses, set up hash registers 318 * and net config register bits. 319 */ 320 static void 321 cgem_rx_filter(struct cgem_softc *sc) 322 { 323 if_t ifp = sc->ifp; 324 uint32_t hashes[2] = { 0, 0 }; 325 uint32_t net_cfg; 326 327 net_cfg = RD4(sc, CGEM_NET_CFG); 328 329 net_cfg &= ~(CGEM_NET_CFG_MULTI_HASH_EN | 330 CGEM_NET_CFG_NO_BCAST | CGEM_NET_CFG_COPY_ALL); 331 332 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 333 net_cfg |= CGEM_NET_CFG_COPY_ALL; 334 else { 335 if ((if_getflags(ifp) & IFF_BROADCAST) == 0) 336 net_cfg |= CGEM_NET_CFG_NO_BCAST; 337 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) { 338 hashes[0] = 0xffffffff; 339 hashes[1] = 0xffffffff; 340 } else 341 if_foreach_llmaddr(ifp, cgem_hash_maddr, hashes); 342 343 if (hashes[0] != 0 || hashes[1] != 0) 344 net_cfg |= CGEM_NET_CFG_MULTI_HASH_EN; 345 } 346 347 WR4(sc, CGEM_HASH_TOP, hashes[0]); 348 WR4(sc, CGEM_HASH_BOT, hashes[1]); 349 WR4(sc, CGEM_NET_CFG, net_cfg); 350 } 351 352 /* For bus_dmamap_load() callback. */ 353 static void 354 cgem_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 355 { 356 357 if (nsegs != 1 || error != 0) 358 return; 359 *(bus_addr_t *)arg = segs[0].ds_addr; 360 } 361 362 /* Create DMA'able descriptor rings. */ 363 static int 364 cgem_setup_descs(struct cgem_softc *sc) 365 { 366 int i, err; 367 368 sc->txring = NULL; 369 sc->rxring = NULL; 370 371 /* Allocate non-cached DMA space for RX and TX descriptors. */ 372 err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 373 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 374 MAX_DESC_RING_SIZE, 1, MAX_DESC_RING_SIZE, 0, 375 busdma_lock_mutex, &sc->sc_mtx, &sc->desc_dma_tag); 376 if (err) 377 return (err); 378 379 /* Set up a bus_dma_tag for mbufs. */ 380 err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 381 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 382 MCLBYTES, TX_MAX_DMA_SEGS, MCLBYTES, 0, 383 busdma_lock_mutex, &sc->sc_mtx, &sc->mbuf_dma_tag); 384 if (err) 385 return (err); 386 387 /* Allocate DMA memory in non-cacheable space. */ 388 err = bus_dmamem_alloc(sc->desc_dma_tag, (void **)&sc->rxring, 389 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rxring_dma_map); 390 if (err) 391 return (err); 392 393 /* Load descriptor DMA memory. */ 394 err = bus_dmamap_load(sc->desc_dma_tag, sc->rxring_dma_map, 395 (void *)sc->rxring, CGEM_NUM_RX_DESCS*sizeof(struct cgem_rx_desc), 396 cgem_getaddr, &sc->rxring_physaddr, BUS_DMA_NOWAIT); 397 if (err) 398 return (err); 399 400 /* Initialize RX descriptors. */ 401 for (i = 0; i < CGEM_NUM_RX_DESCS; i++) { 402 sc->rxring[i].addr = CGEM_RXDESC_OWN; 403 sc->rxring[i].ctl = 0; 404 sc->rxring_m[i] = NULL; 405 sc->rxring_m_dmamap[i] = NULL; 406 } 407 sc->rxring[CGEM_NUM_RX_DESCS - 1].addr |= CGEM_RXDESC_WRAP; 408 409 sc->rxring_hd_ptr = 0; 410 sc->rxring_tl_ptr = 0; 411 sc->rxring_queued = 0; 412 413 /* Allocate DMA memory for TX descriptors in non-cacheable space. */ 414 err = bus_dmamem_alloc(sc->desc_dma_tag, (void **)&sc->txring, 415 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->txring_dma_map); 416 if (err) 417 return (err); 418 419 /* Load TX descriptor DMA memory. */ 420 err = bus_dmamap_load(sc->desc_dma_tag, sc->txring_dma_map, 421 (void *)sc->txring, CGEM_NUM_TX_DESCS*sizeof(struct cgem_tx_desc), 422 cgem_getaddr, &sc->txring_physaddr, BUS_DMA_NOWAIT); 423 if (err) 424 return (err); 425 426 /* Initialize TX descriptor ring. */ 427 for (i = 0; i < CGEM_NUM_TX_DESCS; i++) { 428 sc->txring[i].addr = 0; 429 sc->txring[i].ctl = CGEM_TXDESC_USED; 430 sc->txring_m[i] = NULL; 431 sc->txring_m_dmamap[i] = NULL; 432 } 433 sc->txring[CGEM_NUM_TX_DESCS - 1].ctl |= CGEM_TXDESC_WRAP; 434 435 sc->txring_hd_ptr = 0; 436 sc->txring_tl_ptr = 0; 437 sc->txring_queued = 0; 438 439 return (0); 440 } 441 442 /* Fill receive descriptor ring with mbufs. */ 443 static void 444 cgem_fill_rqueue(struct cgem_softc *sc) 445 { 446 struct mbuf *m = NULL; 447 bus_dma_segment_t segs[TX_MAX_DMA_SEGS]; 448 int nsegs; 449 450 CGEM_ASSERT_LOCKED(sc); 451 452 while (sc->rxring_queued < sc->rxbufs) { 453 /* Get a cluster mbuf. */ 454 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 455 if (m == NULL) 456 break; 457 458 m->m_len = MCLBYTES; 459 m->m_pkthdr.len = MCLBYTES; 460 m->m_pkthdr.rcvif = sc->ifp; 461 462 /* Load map and plug in physical address. */ 463 if (bus_dmamap_create(sc->mbuf_dma_tag, 0, 464 &sc->rxring_m_dmamap[sc->rxring_hd_ptr])) { 465 sc->rxdmamapfails++; 466 m_free(m); 467 break; 468 } 469 if (bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag, 470 sc->rxring_m_dmamap[sc->rxring_hd_ptr], m, 471 segs, &nsegs, BUS_DMA_NOWAIT)) { 472 sc->rxdmamapfails++; 473 bus_dmamap_destroy(sc->mbuf_dma_tag, 474 sc->rxring_m_dmamap[sc->rxring_hd_ptr]); 475 sc->rxring_m_dmamap[sc->rxring_hd_ptr] = NULL; 476 m_free(m); 477 break; 478 } 479 sc->rxring_m[sc->rxring_hd_ptr] = m; 480 481 /* Sync cache with receive buffer. */ 482 bus_dmamap_sync(sc->mbuf_dma_tag, 483 sc->rxring_m_dmamap[sc->rxring_hd_ptr], 484 BUS_DMASYNC_PREREAD); 485 486 /* Write rx descriptor and increment head pointer. */ 487 sc->rxring[sc->rxring_hd_ptr].ctl = 0; 488 if (sc->rxring_hd_ptr == CGEM_NUM_RX_DESCS - 1) { 489 sc->rxring[sc->rxring_hd_ptr].addr = segs[0].ds_addr | 490 CGEM_RXDESC_WRAP; 491 sc->rxring_hd_ptr = 0; 492 } else 493 sc->rxring[sc->rxring_hd_ptr++].addr = segs[0].ds_addr; 494 495 sc->rxring_queued++; 496 } 497 } 498 499 /* Pull received packets off of receive descriptor ring. */ 500 static void 501 cgem_recv(struct cgem_softc *sc) 502 { 503 if_t ifp = sc->ifp; 504 struct mbuf *m, *m_hd, **m_tl; 505 uint32_t ctl; 506 507 CGEM_ASSERT_LOCKED(sc); 508 509 /* Pick up all packets in which the OWN bit is set. */ 510 m_hd = NULL; 511 m_tl = &m_hd; 512 while (sc->rxring_queued > 0 && 513 (sc->rxring[sc->rxring_tl_ptr].addr & CGEM_RXDESC_OWN) != 0) { 514 515 ctl = sc->rxring[sc->rxring_tl_ptr].ctl; 516 517 /* Grab filled mbuf. */ 518 m = sc->rxring_m[sc->rxring_tl_ptr]; 519 sc->rxring_m[sc->rxring_tl_ptr] = NULL; 520 521 /* Sync cache with receive buffer. */ 522 bus_dmamap_sync(sc->mbuf_dma_tag, 523 sc->rxring_m_dmamap[sc->rxring_tl_ptr], 524 BUS_DMASYNC_POSTREAD); 525 526 /* Unload and destroy dmamap. */ 527 bus_dmamap_unload(sc->mbuf_dma_tag, 528 sc->rxring_m_dmamap[sc->rxring_tl_ptr]); 529 bus_dmamap_destroy(sc->mbuf_dma_tag, 530 sc->rxring_m_dmamap[sc->rxring_tl_ptr]); 531 sc->rxring_m_dmamap[sc->rxring_tl_ptr] = NULL; 532 533 /* Increment tail pointer. */ 534 if (++sc->rxring_tl_ptr == CGEM_NUM_RX_DESCS) 535 sc->rxring_tl_ptr = 0; 536 sc->rxring_queued--; 537 538 /* 539 * Check FCS and make sure entire packet landed in one mbuf 540 * cluster (which is much bigger than the largest ethernet 541 * packet). 542 */ 543 if ((ctl & CGEM_RXDESC_BAD_FCS) != 0 || 544 (ctl & (CGEM_RXDESC_SOF | CGEM_RXDESC_EOF)) != 545 (CGEM_RXDESC_SOF | CGEM_RXDESC_EOF)) { 546 /* discard. */ 547 m_free(m); 548 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 549 continue; 550 } 551 552 /* Ready it to hand off to upper layers. */ 553 m->m_data += ETHER_ALIGN; 554 m->m_len = (ctl & CGEM_RXDESC_LENGTH_MASK); 555 m->m_pkthdr.rcvif = ifp; 556 m->m_pkthdr.len = m->m_len; 557 558 /* 559 * Are we using hardware checksumming? Check the status in the 560 * receive descriptor. 561 */ 562 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 563 /* TCP or UDP checks out, IP checks out too. */ 564 if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) == 565 CGEM_RXDESC_CKSUM_STAT_TCP_GOOD || 566 (ctl & CGEM_RXDESC_CKSUM_STAT_MASK) == 567 CGEM_RXDESC_CKSUM_STAT_UDP_GOOD) { 568 m->m_pkthdr.csum_flags |= 569 CSUM_IP_CHECKED | CSUM_IP_VALID | 570 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 571 m->m_pkthdr.csum_data = 0xffff; 572 } else if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) == 573 CGEM_RXDESC_CKSUM_STAT_IP_GOOD) { 574 /* Only IP checks out. */ 575 m->m_pkthdr.csum_flags |= 576 CSUM_IP_CHECKED | CSUM_IP_VALID; 577 m->m_pkthdr.csum_data = 0xffff; 578 } 579 } 580 581 /* Queue it up for delivery below. */ 582 *m_tl = m; 583 m_tl = &m->m_next; 584 } 585 586 /* Replenish receive buffers. */ 587 cgem_fill_rqueue(sc); 588 589 /* Unlock and send up packets. */ 590 CGEM_UNLOCK(sc); 591 while (m_hd != NULL) { 592 m = m_hd; 593 m_hd = m_hd->m_next; 594 m->m_next = NULL; 595 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 596 if_input(ifp, m); 597 } 598 CGEM_LOCK(sc); 599 } 600 601 /* Find completed transmits and free their mbufs. */ 602 static void 603 cgem_clean_tx(struct cgem_softc *sc) 604 { 605 struct mbuf *m; 606 uint32_t ctl; 607 608 CGEM_ASSERT_LOCKED(sc); 609 610 /* free up finished transmits. */ 611 while (sc->txring_queued > 0 && 612 ((ctl = sc->txring[sc->txring_tl_ptr].ctl) & 613 CGEM_TXDESC_USED) != 0) { 614 615 /* Sync cache. */ 616 bus_dmamap_sync(sc->mbuf_dma_tag, 617 sc->txring_m_dmamap[sc->txring_tl_ptr], 618 BUS_DMASYNC_POSTWRITE); 619 620 /* Unload and destroy DMA map. */ 621 bus_dmamap_unload(sc->mbuf_dma_tag, 622 sc->txring_m_dmamap[sc->txring_tl_ptr]); 623 bus_dmamap_destroy(sc->mbuf_dma_tag, 624 sc->txring_m_dmamap[sc->txring_tl_ptr]); 625 sc->txring_m_dmamap[sc->txring_tl_ptr] = NULL; 626 627 /* Free up the mbuf. */ 628 m = sc->txring_m[sc->txring_tl_ptr]; 629 sc->txring_m[sc->txring_tl_ptr] = NULL; 630 m_freem(m); 631 632 /* Check the status. */ 633 if ((ctl & CGEM_TXDESC_AHB_ERR) != 0) { 634 /* Serious bus error. log to console. */ 635 device_printf(sc->dev, 636 "cgem_clean_tx: AHB error, addr=0x%x\n", 637 sc->txring[sc->txring_tl_ptr].addr); 638 } else if ((ctl & (CGEM_TXDESC_RETRY_ERR | 639 CGEM_TXDESC_LATE_COLL)) != 0) { 640 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1); 641 } else 642 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, 1); 643 644 /* 645 * If the packet spanned more than one tx descriptor, skip 646 * descriptors until we find the end so that only start-of-frame 647 * descriptors are processed. 648 */ 649 while ((ctl & CGEM_TXDESC_LAST_BUF) == 0) { 650 if ((ctl & CGEM_TXDESC_WRAP) != 0) 651 sc->txring_tl_ptr = 0; 652 else 653 sc->txring_tl_ptr++; 654 sc->txring_queued--; 655 656 ctl = sc->txring[sc->txring_tl_ptr].ctl; 657 658 sc->txring[sc->txring_tl_ptr].ctl = 659 ctl | CGEM_TXDESC_USED; 660 } 661 662 /* Next descriptor. */ 663 if ((ctl & CGEM_TXDESC_WRAP) != 0) 664 sc->txring_tl_ptr = 0; 665 else 666 sc->txring_tl_ptr++; 667 sc->txring_queued--; 668 669 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_OACTIVE); 670 } 671 } 672 673 /* Start transmits. */ 674 static void 675 cgem_start_locked(if_t ifp) 676 { 677 struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp); 678 struct mbuf *m; 679 bus_dma_segment_t segs[TX_MAX_DMA_SEGS]; 680 uint32_t ctl; 681 int i, nsegs, wrap, err; 682 683 CGEM_ASSERT_LOCKED(sc); 684 685 if ((if_getdrvflags(ifp) & IFF_DRV_OACTIVE) != 0) 686 return; 687 688 for (;;) { 689 /* Check that there is room in the descriptor ring. */ 690 if (sc->txring_queued >= 691 CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) { 692 693 /* Try to make room. */ 694 cgem_clean_tx(sc); 695 696 /* Still no room? */ 697 if (sc->txring_queued >= 698 CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) { 699 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 700 sc->txfull++; 701 break; 702 } 703 } 704 705 /* Grab next transmit packet. */ 706 m = if_dequeue(ifp); 707 if (m == NULL) 708 break; 709 710 /* Create and load DMA map. */ 711 if (bus_dmamap_create(sc->mbuf_dma_tag, 0, 712 &sc->txring_m_dmamap[sc->txring_hd_ptr])) { 713 m_freem(m); 714 sc->txdmamapfails++; 715 continue; 716 } 717 err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag, 718 sc->txring_m_dmamap[sc->txring_hd_ptr], m, segs, &nsegs, 719 BUS_DMA_NOWAIT); 720 if (err == EFBIG) { 721 /* Too many segments! defrag and try again. */ 722 struct mbuf *m2 = m_defrag(m, M_NOWAIT); 723 724 if (m2 == NULL) { 725 sc->txdefragfails++; 726 m_freem(m); 727 bus_dmamap_destroy(sc->mbuf_dma_tag, 728 sc->txring_m_dmamap[sc->txring_hd_ptr]); 729 sc->txring_m_dmamap[sc->txring_hd_ptr] = NULL; 730 continue; 731 } 732 m = m2; 733 err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag, 734 sc->txring_m_dmamap[sc->txring_hd_ptr], m, segs, 735 &nsegs, BUS_DMA_NOWAIT); 736 sc->txdefrags++; 737 } 738 if (err) { 739 /* Give up. */ 740 m_freem(m); 741 bus_dmamap_destroy(sc->mbuf_dma_tag, 742 sc->txring_m_dmamap[sc->txring_hd_ptr]); 743 sc->txring_m_dmamap[sc->txring_hd_ptr] = NULL; 744 sc->txdmamapfails++; 745 continue; 746 } 747 sc->txring_m[sc->txring_hd_ptr] = m; 748 749 /* Sync tx buffer with cache. */ 750 bus_dmamap_sync(sc->mbuf_dma_tag, 751 sc->txring_m_dmamap[sc->txring_hd_ptr], 752 BUS_DMASYNC_PREWRITE); 753 754 /* Set wrap flag if next packet might run off end of ring. */ 755 wrap = sc->txring_hd_ptr + nsegs + TX_MAX_DMA_SEGS >= 756 CGEM_NUM_TX_DESCS; 757 758 /* 759 * Fill in the TX descriptors back to front so that USED bit in 760 * first descriptor is cleared last. 761 */ 762 for (i = nsegs - 1; i >= 0; i--) { 763 /* Descriptor address. */ 764 sc->txring[sc->txring_hd_ptr + i].addr = 765 segs[i].ds_addr; 766 767 /* Descriptor control word. */ 768 ctl = segs[i].ds_len; 769 if (i == nsegs - 1) { 770 ctl |= CGEM_TXDESC_LAST_BUF; 771 if (wrap) 772 ctl |= CGEM_TXDESC_WRAP; 773 } 774 sc->txring[sc->txring_hd_ptr + i].ctl = ctl; 775 776 if (i != 0) 777 sc->txring_m[sc->txring_hd_ptr + i] = NULL; 778 } 779 780 if (wrap) 781 sc->txring_hd_ptr = 0; 782 else 783 sc->txring_hd_ptr += nsegs; 784 sc->txring_queued += nsegs; 785 786 /* Kick the transmitter. */ 787 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow | 788 CGEM_NET_CTRL_START_TX); 789 790 /* If there is a BPF listener, bounce a copy to him. */ 791 ETHER_BPF_MTAP(ifp, m); 792 } 793 } 794 795 static void 796 cgem_start(if_t ifp) 797 { 798 struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp); 799 800 CGEM_LOCK(sc); 801 cgem_start_locked(ifp); 802 CGEM_UNLOCK(sc); 803 } 804 805 static void 806 cgem_poll_hw_stats(struct cgem_softc *sc) 807 { 808 uint32_t n; 809 810 CGEM_ASSERT_LOCKED(sc); 811 812 sc->stats.tx_bytes += RD4(sc, CGEM_OCTETS_TX_BOT); 813 sc->stats.tx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_TX_TOP) << 32; 814 815 sc->stats.tx_frames += RD4(sc, CGEM_FRAMES_TX); 816 sc->stats.tx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_TX); 817 sc->stats.tx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_TX); 818 sc->stats.tx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_TX); 819 sc->stats.tx_frames_64b += RD4(sc, CGEM_FRAMES_64B_TX); 820 sc->stats.tx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_TX); 821 sc->stats.tx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_TX); 822 sc->stats.tx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_TX); 823 sc->stats.tx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_TX); 824 sc->stats.tx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_TX); 825 sc->stats.tx_under_runs += RD4(sc, CGEM_TX_UNDERRUNS); 826 827 n = RD4(sc, CGEM_SINGLE_COLL_FRAMES); 828 sc->stats.tx_single_collisn += n; 829 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n); 830 n = RD4(sc, CGEM_MULTI_COLL_FRAMES); 831 sc->stats.tx_multi_collisn += n; 832 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n); 833 n = RD4(sc, CGEM_EXCESSIVE_COLL_FRAMES); 834 sc->stats.tx_excsv_collisn += n; 835 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n); 836 n = RD4(sc, CGEM_LATE_COLL); 837 sc->stats.tx_late_collisn += n; 838 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n); 839 840 sc->stats.tx_deferred_frames += RD4(sc, CGEM_DEFERRED_TX_FRAMES); 841 sc->stats.tx_carrier_sense_errs += RD4(sc, CGEM_CARRIER_SENSE_ERRS); 842 843 sc->stats.rx_bytes += RD4(sc, CGEM_OCTETS_RX_BOT); 844 sc->stats.rx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_RX_TOP) << 32; 845 846 sc->stats.rx_frames += RD4(sc, CGEM_FRAMES_RX); 847 sc->stats.rx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_RX); 848 sc->stats.rx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_RX); 849 sc->stats.rx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_RX); 850 sc->stats.rx_frames_64b += RD4(sc, CGEM_FRAMES_64B_RX); 851 sc->stats.rx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_RX); 852 sc->stats.rx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_RX); 853 sc->stats.rx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_RX); 854 sc->stats.rx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_RX); 855 sc->stats.rx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_RX); 856 sc->stats.rx_frames_undersize += RD4(sc, CGEM_UNDERSZ_RX); 857 sc->stats.rx_frames_oversize += RD4(sc, CGEM_OVERSZ_RX); 858 sc->stats.rx_frames_jabber += RD4(sc, CGEM_JABBERS_RX); 859 sc->stats.rx_frames_fcs_errs += RD4(sc, CGEM_FCS_ERRS); 860 sc->stats.rx_frames_length_errs += RD4(sc, CGEM_LENGTH_FIELD_ERRS); 861 sc->stats.rx_symbol_errs += RD4(sc, CGEM_RX_SYMBOL_ERRS); 862 sc->stats.rx_align_errs += RD4(sc, CGEM_ALIGN_ERRS); 863 sc->stats.rx_resource_errs += RD4(sc, CGEM_RX_RESOURCE_ERRS); 864 sc->stats.rx_overrun_errs += RD4(sc, CGEM_RX_OVERRUN_ERRS); 865 sc->stats.rx_ip_hdr_csum_errs += RD4(sc, CGEM_IP_HDR_CKSUM_ERRS); 866 sc->stats.rx_tcp_csum_errs += RD4(sc, CGEM_TCP_CKSUM_ERRS); 867 sc->stats.rx_udp_csum_errs += RD4(sc, CGEM_UDP_CKSUM_ERRS); 868 } 869 870 static void 871 cgem_tick(void *arg) 872 { 873 struct cgem_softc *sc = (struct cgem_softc *)arg; 874 struct mii_data *mii; 875 876 CGEM_ASSERT_LOCKED(sc); 877 878 /* Poll the phy. */ 879 if (sc->miibus != NULL) { 880 mii = device_get_softc(sc->miibus); 881 mii_tick(mii); 882 } 883 884 /* Poll statistics registers. */ 885 cgem_poll_hw_stats(sc); 886 887 /* Check for receiver hang. */ 888 if (sc->rxhangwar && sc->rx_frames_prev == sc->stats.rx_frames) { 889 /* 890 * Reset receiver logic by toggling RX_EN bit. 1usec 891 * delay is necessary especially when operating at 100mbps 892 * and 10mbps speeds. 893 */ 894 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow & 895 ~CGEM_NET_CTRL_RX_EN); 896 DELAY(1); 897 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow); 898 } 899 sc->rx_frames_prev = sc->stats.rx_frames; 900 901 /* Next callout in one second. */ 902 callout_reset(&sc->tick_ch, hz, cgem_tick, sc); 903 } 904 905 /* Interrupt handler. */ 906 static void 907 cgem_intr(void *arg) 908 { 909 struct cgem_softc *sc = (struct cgem_softc *)arg; 910 if_t ifp = sc->ifp; 911 uint32_t istatus; 912 913 CGEM_LOCK(sc); 914 915 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 916 CGEM_UNLOCK(sc); 917 return; 918 } 919 920 /* Read interrupt status and immediately clear the bits. */ 921 istatus = RD4(sc, CGEM_INTR_STAT); 922 WR4(sc, CGEM_INTR_STAT, istatus); 923 924 /* Packets received. */ 925 if ((istatus & CGEM_INTR_RX_COMPLETE) != 0) 926 cgem_recv(sc); 927 928 /* Free up any completed transmit buffers. */ 929 cgem_clean_tx(sc); 930 931 /* Hresp not ok. Something is very bad with DMA. Try to clear. */ 932 if ((istatus & CGEM_INTR_HRESP_NOT_OK) != 0) { 933 device_printf(sc->dev, 934 "cgem_intr: hresp not okay! rx_status=0x%x\n", 935 RD4(sc, CGEM_RX_STAT)); 936 WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_HRESP_NOT_OK); 937 } 938 939 /* Receiver overrun. */ 940 if ((istatus & CGEM_INTR_RX_OVERRUN) != 0) { 941 /* Clear status bit. */ 942 WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_OVERRUN); 943 sc->rxoverruns++; 944 } 945 946 /* Receiver ran out of bufs. */ 947 if ((istatus & CGEM_INTR_RX_USED_READ) != 0) { 948 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow | 949 CGEM_NET_CTRL_FLUSH_DPRAM_PKT); 950 cgem_fill_rqueue(sc); 951 sc->rxnobufs++; 952 } 953 954 /* Restart transmitter if needed. */ 955 if (!if_sendq_empty(ifp)) 956 cgem_start_locked(ifp); 957 958 CGEM_UNLOCK(sc); 959 } 960 961 /* Reset hardware. */ 962 static void 963 cgem_reset(struct cgem_softc *sc) 964 { 965 966 CGEM_ASSERT_LOCKED(sc); 967 968 WR4(sc, CGEM_NET_CTRL, 0); 969 WR4(sc, CGEM_NET_CFG, 0); 970 WR4(sc, CGEM_NET_CTRL, CGEM_NET_CTRL_CLR_STAT_REGS); 971 WR4(sc, CGEM_TX_STAT, CGEM_TX_STAT_ALL); 972 WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_ALL); 973 WR4(sc, CGEM_INTR_DIS, CGEM_INTR_ALL); 974 WR4(sc, CGEM_HASH_BOT, 0); 975 WR4(sc, CGEM_HASH_TOP, 0); 976 WR4(sc, CGEM_TX_QBAR, 0); /* manual says do this. */ 977 WR4(sc, CGEM_RX_QBAR, 0); 978 979 /* Get management port running even if interface is down. */ 980 WR4(sc, CGEM_NET_CFG, CGEM_NET_CFG_DBUS_WIDTH_32 | 981 CGEM_NET_CFG_MDC_CLK_DIV_64); 982 983 sc->net_ctl_shadow = CGEM_NET_CTRL_MGMT_PORT_EN; 984 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow); 985 } 986 987 /* Bring up the hardware. */ 988 static void 989 cgem_config(struct cgem_softc *sc) 990 { 991 if_t ifp = sc->ifp; 992 uint32_t net_cfg; 993 uint32_t dma_cfg; 994 u_char *eaddr = if_getlladdr(ifp); 995 996 CGEM_ASSERT_LOCKED(sc); 997 998 /* Program Net Config Register. */ 999 net_cfg = CGEM_NET_CFG_DBUS_WIDTH_32 | 1000 CGEM_NET_CFG_MDC_CLK_DIV_64 | 1001 CGEM_NET_CFG_FCS_REMOVE | 1002 CGEM_NET_CFG_RX_BUF_OFFSET(ETHER_ALIGN) | 1003 CGEM_NET_CFG_GIGE_EN | 1004 CGEM_NET_CFG_1536RXEN | 1005 CGEM_NET_CFG_FULL_DUPLEX | 1006 CGEM_NET_CFG_SPEED100; 1007 1008 /* Enable receive checksum offloading? */ 1009 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1010 net_cfg |= CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN; 1011 1012 WR4(sc, CGEM_NET_CFG, net_cfg); 1013 1014 /* Program DMA Config Register. */ 1015 dma_cfg = CGEM_DMA_CFG_RX_BUF_SIZE(MCLBYTES) | 1016 CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_8K | 1017 CGEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 1018 CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_16 | 1019 CGEM_DMA_CFG_DISC_WHEN_NO_AHB; 1020 1021 /* Enable transmit checksum offloading? */ 1022 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1023 dma_cfg |= CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 1024 1025 WR4(sc, CGEM_DMA_CFG, dma_cfg); 1026 1027 /* Write the rx and tx descriptor ring addresses to the QBAR regs. */ 1028 WR4(sc, CGEM_RX_QBAR, (uint32_t) sc->rxring_physaddr); 1029 WR4(sc, CGEM_TX_QBAR, (uint32_t) sc->txring_physaddr); 1030 1031 /* Enable rx and tx. */ 1032 sc->net_ctl_shadow |= (CGEM_NET_CTRL_TX_EN | CGEM_NET_CTRL_RX_EN); 1033 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow); 1034 1035 /* Set receive address in case it changed. */ 1036 WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) | 1037 (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0]); 1038 WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]); 1039 1040 /* Set up interrupts. */ 1041 WR4(sc, CGEM_INTR_EN, CGEM_INTR_RX_COMPLETE | CGEM_INTR_RX_OVERRUN | 1042 CGEM_INTR_TX_USED_READ | CGEM_INTR_RX_USED_READ | 1043 CGEM_INTR_HRESP_NOT_OK); 1044 } 1045 1046 /* Turn on interface and load up receive ring with buffers. */ 1047 static void 1048 cgem_init_locked(struct cgem_softc *sc) 1049 { 1050 struct mii_data *mii; 1051 1052 CGEM_ASSERT_LOCKED(sc); 1053 1054 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) != 0) 1055 return; 1056 1057 cgem_config(sc); 1058 cgem_fill_rqueue(sc); 1059 1060 if_setdrvflagbits(sc->ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 1061 1062 mii = device_get_softc(sc->miibus); 1063 mii_mediachg(mii); 1064 1065 callout_reset(&sc->tick_ch, hz, cgem_tick, sc); 1066 } 1067 1068 static void 1069 cgem_init(void *arg) 1070 { 1071 struct cgem_softc *sc = (struct cgem_softc *)arg; 1072 1073 CGEM_LOCK(sc); 1074 cgem_init_locked(sc); 1075 CGEM_UNLOCK(sc); 1076 } 1077 1078 /* Turn off interface. Free up any buffers in transmit or receive queues. */ 1079 static void 1080 cgem_stop(struct cgem_softc *sc) 1081 { 1082 int i; 1083 1084 CGEM_ASSERT_LOCKED(sc); 1085 1086 callout_stop(&sc->tick_ch); 1087 1088 /* Shut down hardware. */ 1089 cgem_reset(sc); 1090 1091 /* Clear out transmit queue. */ 1092 for (i = 0; i < CGEM_NUM_TX_DESCS; i++) { 1093 sc->txring[i].ctl = CGEM_TXDESC_USED; 1094 sc->txring[i].addr = 0; 1095 if (sc->txring_m[i]) { 1096 /* Unload and destroy dmamap. */ 1097 bus_dmamap_unload(sc->mbuf_dma_tag, 1098 sc->txring_m_dmamap[i]); 1099 bus_dmamap_destroy(sc->mbuf_dma_tag, 1100 sc->txring_m_dmamap[i]); 1101 sc->txring_m_dmamap[i] = NULL; 1102 m_freem(sc->txring_m[i]); 1103 sc->txring_m[i] = NULL; 1104 } 1105 } 1106 sc->txring[CGEM_NUM_TX_DESCS - 1].ctl |= CGEM_TXDESC_WRAP; 1107 1108 sc->txring_hd_ptr = 0; 1109 sc->txring_tl_ptr = 0; 1110 sc->txring_queued = 0; 1111 1112 /* Clear out receive queue. */ 1113 for (i = 0; i < CGEM_NUM_RX_DESCS; i++) { 1114 sc->rxring[i].addr = CGEM_RXDESC_OWN; 1115 sc->rxring[i].ctl = 0; 1116 if (sc->rxring_m[i]) { 1117 /* Unload and destroy dmamap. */ 1118 bus_dmamap_unload(sc->mbuf_dma_tag, 1119 sc->rxring_m_dmamap[i]); 1120 bus_dmamap_destroy(sc->mbuf_dma_tag, 1121 sc->rxring_m_dmamap[i]); 1122 sc->rxring_m_dmamap[i] = NULL; 1123 1124 m_freem(sc->rxring_m[i]); 1125 sc->rxring_m[i] = NULL; 1126 } 1127 } 1128 sc->rxring[CGEM_NUM_RX_DESCS - 1].addr |= CGEM_RXDESC_WRAP; 1129 1130 sc->rxring_hd_ptr = 0; 1131 sc->rxring_tl_ptr = 0; 1132 sc->rxring_queued = 0; 1133 1134 /* Force next statchg or linkchg to program net config register. */ 1135 sc->mii_media_active = 0; 1136 } 1137 1138 1139 static int 1140 cgem_ioctl(if_t ifp, u_long cmd, caddr_t data) 1141 { 1142 struct cgem_softc *sc = if_getsoftc(ifp); 1143 struct ifreq *ifr = (struct ifreq *)data; 1144 struct mii_data *mii; 1145 int error = 0, mask; 1146 1147 switch (cmd) { 1148 case SIOCSIFFLAGS: 1149 CGEM_LOCK(sc); 1150 if ((if_getflags(ifp) & IFF_UP) != 0) { 1151 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1152 if (((if_getflags(ifp) ^ sc->if_old_flags) & 1153 (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1154 cgem_rx_filter(sc); 1155 } 1156 } else { 1157 cgem_init_locked(sc); 1158 } 1159 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1160 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1161 cgem_stop(sc); 1162 } 1163 sc->if_old_flags = if_getflags(ifp); 1164 CGEM_UNLOCK(sc); 1165 break; 1166 1167 case SIOCADDMULTI: 1168 case SIOCDELMULTI: 1169 /* Set up multi-cast filters. */ 1170 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1171 CGEM_LOCK(sc); 1172 cgem_rx_filter(sc); 1173 CGEM_UNLOCK(sc); 1174 } 1175 break; 1176 1177 case SIOCSIFMEDIA: 1178 case SIOCGIFMEDIA: 1179 mii = device_get_softc(sc->miibus); 1180 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1181 break; 1182 1183 case SIOCSIFCAP: 1184 CGEM_LOCK(sc); 1185 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap; 1186 1187 if ((mask & IFCAP_TXCSUM) != 0) { 1188 if ((ifr->ifr_reqcap & IFCAP_TXCSUM) != 0) { 1189 /* Turn on TX checksumming. */ 1190 if_setcapenablebit(ifp, IFCAP_TXCSUM | 1191 IFCAP_TXCSUM_IPV6, 0); 1192 if_sethwassistbits(ifp, CGEM_CKSUM_ASSIST, 0); 1193 1194 WR4(sc, CGEM_DMA_CFG, 1195 RD4(sc, CGEM_DMA_CFG) | 1196 CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN); 1197 } else { 1198 /* Turn off TX checksumming. */ 1199 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM | 1200 IFCAP_TXCSUM_IPV6); 1201 if_sethwassistbits(ifp, 0, CGEM_CKSUM_ASSIST); 1202 1203 WR4(sc, CGEM_DMA_CFG, 1204 RD4(sc, CGEM_DMA_CFG) & 1205 ~CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN); 1206 } 1207 } 1208 if ((mask & IFCAP_RXCSUM) != 0) { 1209 if ((ifr->ifr_reqcap & IFCAP_RXCSUM) != 0) { 1210 /* Turn on RX checksumming. */ 1211 if_setcapenablebit(ifp, IFCAP_RXCSUM | 1212 IFCAP_RXCSUM_IPV6, 0); 1213 WR4(sc, CGEM_NET_CFG, 1214 RD4(sc, CGEM_NET_CFG) | 1215 CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN); 1216 } else { 1217 /* Turn off RX checksumming. */ 1218 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM | 1219 IFCAP_RXCSUM_IPV6); 1220 WR4(sc, CGEM_NET_CFG, 1221 RD4(sc, CGEM_NET_CFG) & 1222 ~CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN); 1223 } 1224 } 1225 if ((if_getcapenable(ifp) & (IFCAP_RXCSUM | IFCAP_TXCSUM)) == 1226 (IFCAP_RXCSUM | IFCAP_TXCSUM)) 1227 if_setcapenablebit(ifp, IFCAP_VLAN_HWCSUM, 0); 1228 else 1229 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWCSUM); 1230 1231 CGEM_UNLOCK(sc); 1232 break; 1233 default: 1234 error = ether_ioctl(ifp, cmd, data); 1235 break; 1236 } 1237 1238 return (error); 1239 } 1240 1241 /* MII bus support routines. 1242 */ 1243 static void 1244 cgem_child_detached(device_t dev, device_t child) 1245 { 1246 struct cgem_softc *sc = device_get_softc(dev); 1247 1248 if (child == sc->miibus) 1249 sc->miibus = NULL; 1250 } 1251 1252 static int 1253 cgem_ifmedia_upd(if_t ifp) 1254 { 1255 struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp); 1256 struct mii_data *mii; 1257 struct mii_softc *miisc; 1258 int error = 0; 1259 1260 mii = device_get_softc(sc->miibus); 1261 CGEM_LOCK(sc); 1262 if ((if_getflags(ifp) & IFF_UP) != 0) { 1263 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1264 PHY_RESET(miisc); 1265 error = mii_mediachg(mii); 1266 } 1267 CGEM_UNLOCK(sc); 1268 1269 return (error); 1270 } 1271 1272 static void 1273 cgem_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1274 { 1275 struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp); 1276 struct mii_data *mii; 1277 1278 mii = device_get_softc(sc->miibus); 1279 CGEM_LOCK(sc); 1280 mii_pollstat(mii); 1281 ifmr->ifm_active = mii->mii_media_active; 1282 ifmr->ifm_status = mii->mii_media_status; 1283 CGEM_UNLOCK(sc); 1284 } 1285 1286 static int 1287 cgem_miibus_readreg(device_t dev, int phy, int reg) 1288 { 1289 struct cgem_softc *sc = device_get_softc(dev); 1290 int tries, val; 1291 1292 WR4(sc, CGEM_PHY_MAINT, CGEM_PHY_MAINT_CLAUSE_22 | 1293 CGEM_PHY_MAINT_MUST_10 | CGEM_PHY_MAINT_OP_READ | 1294 (phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) | 1295 (reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT)); 1296 1297 /* Wait for completion. */ 1298 tries=0; 1299 while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) { 1300 DELAY(5); 1301 if (++tries > 200) { 1302 device_printf(dev, "phy read timeout: %d\n", reg); 1303 return (-1); 1304 } 1305 } 1306 1307 val = RD4(sc, CGEM_PHY_MAINT) & CGEM_PHY_MAINT_DATA_MASK; 1308 1309 if (reg == MII_EXTSR) 1310 /* 1311 * MAC does not support half-duplex at gig speeds. 1312 * Let mii(4) exclude the capability. 1313 */ 1314 val &= ~(EXTSR_1000XHDX | EXTSR_1000THDX); 1315 1316 return (val); 1317 } 1318 1319 static int 1320 cgem_miibus_writereg(device_t dev, int phy, int reg, int data) 1321 { 1322 struct cgem_softc *sc = device_get_softc(dev); 1323 int tries; 1324 1325 WR4(sc, CGEM_PHY_MAINT, CGEM_PHY_MAINT_CLAUSE_22 | 1326 CGEM_PHY_MAINT_MUST_10 | CGEM_PHY_MAINT_OP_WRITE | 1327 (phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) | 1328 (reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT) | 1329 (data & CGEM_PHY_MAINT_DATA_MASK)); 1330 1331 /* Wait for completion. */ 1332 tries = 0; 1333 while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) { 1334 DELAY(5); 1335 if (++tries > 200) { 1336 device_printf(dev, "phy write timeout: %d\n", reg); 1337 return (-1); 1338 } 1339 } 1340 1341 return (0); 1342 } 1343 1344 static void 1345 cgem_miibus_statchg(device_t dev) 1346 { 1347 struct cgem_softc *sc = device_get_softc(dev); 1348 struct mii_data *mii = device_get_softc(sc->miibus); 1349 1350 CGEM_ASSERT_LOCKED(sc); 1351 1352 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1353 (IFM_ACTIVE | IFM_AVALID) && 1354 sc->mii_media_active != mii->mii_media_active) 1355 cgem_mediachange(sc, mii); 1356 } 1357 1358 static void 1359 cgem_miibus_linkchg(device_t dev) 1360 { 1361 struct cgem_softc *sc = device_get_softc(dev); 1362 struct mii_data *mii = device_get_softc(sc->miibus); 1363 1364 CGEM_ASSERT_LOCKED(sc); 1365 1366 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1367 (IFM_ACTIVE | IFM_AVALID) && 1368 sc->mii_media_active != mii->mii_media_active) 1369 cgem_mediachange(sc, mii); 1370 } 1371 1372 /* 1373 * Overridable weak symbol cgem_set_ref_clk(). This allows platforms to 1374 * provide a function to set the cgem's reference clock. 1375 */ 1376 static int __used 1377 cgem_default_set_ref_clk(int unit, int frequency) 1378 { 1379 1380 return 0; 1381 } 1382 __weak_reference(cgem_default_set_ref_clk, cgem_set_ref_clk); 1383 1384 /* Call to set reference clock and network config bits according to media. */ 1385 static void 1386 cgem_mediachange(struct cgem_softc *sc, struct mii_data *mii) 1387 { 1388 uint32_t net_cfg; 1389 int ref_clk_freq; 1390 1391 CGEM_ASSERT_LOCKED(sc); 1392 1393 /* Update hardware to reflect media. */ 1394 net_cfg = RD4(sc, CGEM_NET_CFG); 1395 net_cfg &= ~(CGEM_NET_CFG_SPEED100 | CGEM_NET_CFG_GIGE_EN | 1396 CGEM_NET_CFG_FULL_DUPLEX); 1397 1398 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1399 case IFM_1000_T: 1400 net_cfg |= (CGEM_NET_CFG_SPEED100 | 1401 CGEM_NET_CFG_GIGE_EN); 1402 ref_clk_freq = 125000000; 1403 break; 1404 case IFM_100_TX: 1405 net_cfg |= CGEM_NET_CFG_SPEED100; 1406 ref_clk_freq = 25000000; 1407 break; 1408 default: 1409 ref_clk_freq = 2500000; 1410 } 1411 1412 if ((mii->mii_media_active & IFM_FDX) != 0) 1413 net_cfg |= CGEM_NET_CFG_FULL_DUPLEX; 1414 1415 WR4(sc, CGEM_NET_CFG, net_cfg); 1416 1417 /* Set the reference clock if necessary. */ 1418 if (cgem_set_ref_clk(sc->ref_clk_num, ref_clk_freq)) 1419 device_printf(sc->dev, 1420 "cgem_mediachange: could not set ref clk%d to %d.\n", 1421 sc->ref_clk_num, ref_clk_freq); 1422 1423 sc->mii_media_active = mii->mii_media_active; 1424 } 1425 1426 static void 1427 cgem_add_sysctls(device_t dev) 1428 { 1429 struct cgem_softc *sc = device_get_softc(dev); 1430 struct sysctl_ctx_list *ctx; 1431 struct sysctl_oid_list *child; 1432 struct sysctl_oid *tree; 1433 1434 ctx = device_get_sysctl_ctx(dev); 1435 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 1436 1437 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rxbufs", CTLFLAG_RW, 1438 &sc->rxbufs, 0, "Number receive buffers to provide"); 1439 1440 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rxhangwar", CTLFLAG_RW, 1441 &sc->rxhangwar, 0, "Enable receive hang work-around"); 1442 1443 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxoverruns", CTLFLAG_RD, 1444 &sc->rxoverruns, 0, "Receive overrun events"); 1445 1446 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxnobufs", CTLFLAG_RD, 1447 &sc->rxnobufs, 0, "Receive buf queue empty events"); 1448 1449 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxdmamapfails", CTLFLAG_RD, 1450 &sc->rxdmamapfails, 0, "Receive DMA map failures"); 1451 1452 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txfull", CTLFLAG_RD, 1453 &sc->txfull, 0, "Transmit ring full events"); 1454 1455 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdmamapfails", CTLFLAG_RD, 1456 &sc->txdmamapfails, 0, "Transmit DMA map failures"); 1457 1458 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdefrags", CTLFLAG_RD, 1459 &sc->txdefrags, 0, "Transmit m_defrag() calls"); 1460 1461 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdefragfails", CTLFLAG_RD, 1462 &sc->txdefragfails, 0, "Transmit m_defrag() failures"); 1463 1464 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1465 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "GEM statistics"); 1466 child = SYSCTL_CHILDREN(tree); 1467 1468 SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "tx_bytes", CTLFLAG_RD, 1469 &sc->stats.tx_bytes, "Total bytes transmitted"); 1470 1471 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames", CTLFLAG_RD, 1472 &sc->stats.tx_frames, 0, "Total frames transmitted"); 1473 1474 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_bcast", CTLFLAG_RD, 1475 &sc->stats.tx_frames_bcast, 0, 1476 "Number broadcast frames transmitted"); 1477 1478 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_multi", CTLFLAG_RD, 1479 &sc->stats.tx_frames_multi, 0, 1480 "Number multicast frames transmitted"); 1481 1482 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_pause", 1483 CTLFLAG_RD, &sc->stats.tx_frames_pause, 0, 1484 "Number pause frames transmitted"); 1485 1486 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_64b", CTLFLAG_RD, 1487 &sc->stats.tx_frames_64b, 0, 1488 "Number frames transmitted of size 64 bytes or less"); 1489 1490 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_65to127b", CTLFLAG_RD, 1491 &sc->stats.tx_frames_65to127b, 0, 1492 "Number frames transmitted of size 65-127 bytes"); 1493 1494 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_128to255b", 1495 CTLFLAG_RD, &sc->stats.tx_frames_128to255b, 0, 1496 "Number frames transmitted of size 128-255 bytes"); 1497 1498 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_256to511b", 1499 CTLFLAG_RD, &sc->stats.tx_frames_256to511b, 0, 1500 "Number frames transmitted of size 256-511 bytes"); 1501 1502 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_512to1023b", 1503 CTLFLAG_RD, &sc->stats.tx_frames_512to1023b, 0, 1504 "Number frames transmitted of size 512-1023 bytes"); 1505 1506 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_1024to1536b", 1507 CTLFLAG_RD, &sc->stats.tx_frames_1024to1536b, 0, 1508 "Number frames transmitted of size 1024-1536 bytes"); 1509 1510 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_under_runs", 1511 CTLFLAG_RD, &sc->stats.tx_under_runs, 0, 1512 "Number transmit under-run events"); 1513 1514 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_single_collisn", 1515 CTLFLAG_RD, &sc->stats.tx_single_collisn, 0, 1516 "Number single-collision transmit frames"); 1517 1518 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_multi_collisn", 1519 CTLFLAG_RD, &sc->stats.tx_multi_collisn, 0, 1520 "Number multi-collision transmit frames"); 1521 1522 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_excsv_collisn", 1523 CTLFLAG_RD, &sc->stats.tx_excsv_collisn, 0, 1524 "Number excessive collision transmit frames"); 1525 1526 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_late_collisn", 1527 CTLFLAG_RD, &sc->stats.tx_late_collisn, 0, 1528 "Number late-collision transmit frames"); 1529 1530 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_deferred_frames", 1531 CTLFLAG_RD, &sc->stats.tx_deferred_frames, 0, 1532 "Number deferred transmit frames"); 1533 1534 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_carrier_sense_errs", 1535 CTLFLAG_RD, &sc->stats.tx_carrier_sense_errs, 0, 1536 "Number carrier sense errors on transmit"); 1537 1538 SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "rx_bytes", CTLFLAG_RD, 1539 &sc->stats.rx_bytes, "Total bytes received"); 1540 1541 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames", CTLFLAG_RD, 1542 &sc->stats.rx_frames, 0, "Total frames received"); 1543 1544 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_bcast", 1545 CTLFLAG_RD, &sc->stats.rx_frames_bcast, 0, 1546 "Number broadcast frames received"); 1547 1548 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_multi", 1549 CTLFLAG_RD, &sc->stats.rx_frames_multi, 0, 1550 "Number multicast frames received"); 1551 1552 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_pause", 1553 CTLFLAG_RD, &sc->stats.rx_frames_pause, 0, 1554 "Number pause frames received"); 1555 1556 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_64b", 1557 CTLFLAG_RD, &sc->stats.rx_frames_64b, 0, 1558 "Number frames received of size 64 bytes or less"); 1559 1560 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_65to127b", 1561 CTLFLAG_RD, &sc->stats.rx_frames_65to127b, 0, 1562 "Number frames received of size 65-127 bytes"); 1563 1564 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_128to255b", 1565 CTLFLAG_RD, &sc->stats.rx_frames_128to255b, 0, 1566 "Number frames received of size 128-255 bytes"); 1567 1568 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_256to511b", 1569 CTLFLAG_RD, &sc->stats.rx_frames_256to511b, 0, 1570 "Number frames received of size 256-511 bytes"); 1571 1572 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_512to1023b", 1573 CTLFLAG_RD, &sc->stats.rx_frames_512to1023b, 0, 1574 "Number frames received of size 512-1023 bytes"); 1575 1576 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_1024to1536b", 1577 CTLFLAG_RD, &sc->stats.rx_frames_1024to1536b, 0, 1578 "Number frames received of size 1024-1536 bytes"); 1579 1580 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_undersize", 1581 CTLFLAG_RD, &sc->stats.rx_frames_undersize, 0, 1582 "Number undersize frames received"); 1583 1584 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_oversize", 1585 CTLFLAG_RD, &sc->stats.rx_frames_oversize, 0, 1586 "Number oversize frames received"); 1587 1588 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_jabber", 1589 CTLFLAG_RD, &sc->stats.rx_frames_jabber, 0, 1590 "Number jabber frames received"); 1591 1592 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_fcs_errs", 1593 CTLFLAG_RD, &sc->stats.rx_frames_fcs_errs, 0, 1594 "Number frames received with FCS errors"); 1595 1596 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_length_errs", 1597 CTLFLAG_RD, &sc->stats.rx_frames_length_errs, 0, 1598 "Number frames received with length errors"); 1599 1600 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_symbol_errs", 1601 CTLFLAG_RD, &sc->stats.rx_symbol_errs, 0, 1602 "Number receive symbol errors"); 1603 1604 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_align_errs", 1605 CTLFLAG_RD, &sc->stats.rx_align_errs, 0, 1606 "Number receive alignment errors"); 1607 1608 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_resource_errs", 1609 CTLFLAG_RD, &sc->stats.rx_resource_errs, 0, 1610 "Number frames received when no rx buffer available"); 1611 1612 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_overrun_errs", 1613 CTLFLAG_RD, &sc->stats.rx_overrun_errs, 0, 1614 "Number frames received but not copied due to receive overrun"); 1615 1616 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_ip_hdr_csum_errs", 1617 CTLFLAG_RD, &sc->stats.rx_ip_hdr_csum_errs, 0, 1618 "Number frames received with IP header checksum errors"); 1619 1620 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_tcp_csum_errs", 1621 CTLFLAG_RD, &sc->stats.rx_tcp_csum_errs, 0, 1622 "Number frames received with TCP checksum errors"); 1623 1624 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_udp_csum_errs", 1625 CTLFLAG_RD, &sc->stats.rx_udp_csum_errs, 0, 1626 "Number frames received with UDP checksum errors"); 1627 } 1628 1629 1630 static int 1631 cgem_probe(device_t dev) 1632 { 1633 1634 if (!ofw_bus_status_okay(dev)) 1635 return (ENXIO); 1636 1637 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1638 return (ENXIO); 1639 1640 device_set_desc(dev, "Cadence CGEM Gigabit Ethernet Interface"); 1641 return (0); 1642 } 1643 1644 static int 1645 cgem_attach(device_t dev) 1646 { 1647 struct cgem_softc *sc = device_get_softc(dev); 1648 if_t ifp = NULL; 1649 phandle_t node; 1650 pcell_t cell; 1651 int rid, err; 1652 u_char eaddr[ETHER_ADDR_LEN]; 1653 1654 sc->dev = dev; 1655 CGEM_LOCK_INIT(sc); 1656 1657 /* Get reference clock number and base divider from fdt. */ 1658 node = ofw_bus_get_node(dev); 1659 sc->ref_clk_num = 0; 1660 if (OF_getprop(node, "ref-clock-num", &cell, sizeof(cell)) > 0) 1661 sc->ref_clk_num = fdt32_to_cpu(cell); 1662 1663 /* Get memory resource. */ 1664 rid = 0; 1665 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1666 RF_ACTIVE); 1667 if (sc->mem_res == NULL) { 1668 device_printf(dev, "could not allocate memory resources.\n"); 1669 return (ENOMEM); 1670 } 1671 1672 /* Get IRQ resource. */ 1673 rid = 0; 1674 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 1675 if (sc->irq_res == NULL) { 1676 device_printf(dev, "could not allocate interrupt resource.\n"); 1677 cgem_detach(dev); 1678 return (ENOMEM); 1679 } 1680 1681 /* Set up ifnet structure. */ 1682 ifp = sc->ifp = if_alloc(IFT_ETHER); 1683 if (ifp == NULL) { 1684 device_printf(dev, "could not allocate ifnet structure\n"); 1685 cgem_detach(dev); 1686 return (ENOMEM); 1687 } 1688 if_setsoftc(ifp, sc); 1689 if_initname(ifp, IF_CGEM_NAME, device_get_unit(dev)); 1690 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1691 if_setinitfn(ifp, cgem_init); 1692 if_setioctlfn(ifp, cgem_ioctl); 1693 if_setstartfn(ifp, cgem_start); 1694 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | 1695 IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM, 0); 1696 if_setsendqlen(ifp, CGEM_NUM_TX_DESCS); 1697 if_setsendqready(ifp); 1698 1699 /* Disable hardware checksumming by default. */ 1700 if_sethwassist(ifp, 0); 1701 if_setcapenable(ifp, if_getcapabilities(ifp) & 1702 ~(IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWCSUM)); 1703 1704 sc->if_old_flags = if_getflags(ifp); 1705 sc->rxbufs = DEFAULT_NUM_RX_BUFS; 1706 sc->rxhangwar = 1; 1707 1708 /* Reset hardware. */ 1709 CGEM_LOCK(sc); 1710 cgem_reset(sc); 1711 CGEM_UNLOCK(sc); 1712 1713 /* Attach phy to mii bus. */ 1714 err = mii_attach(dev, &sc->miibus, ifp, 1715 cgem_ifmedia_upd, cgem_ifmedia_sts, BMSR_DEFCAPMASK, 1716 MII_PHY_ANY, MII_OFFSET_ANY, 0); 1717 if (err) { 1718 device_printf(dev, "attaching PHYs failed\n"); 1719 cgem_detach(dev); 1720 return (err); 1721 } 1722 1723 /* Set up TX and RX descriptor area. */ 1724 err = cgem_setup_descs(sc); 1725 if (err) { 1726 device_printf(dev, "could not set up dma mem for descs.\n"); 1727 cgem_detach(dev); 1728 return (ENOMEM); 1729 } 1730 1731 /* Get a MAC address. */ 1732 cgem_get_mac(sc, eaddr); 1733 1734 /* Start ticks. */ 1735 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 1736 1737 ether_ifattach(ifp, eaddr); 1738 1739 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE | 1740 INTR_EXCL, NULL, cgem_intr, sc, &sc->intrhand); 1741 if (err) { 1742 device_printf(dev, "could not set interrupt handler.\n"); 1743 ether_ifdetach(ifp); 1744 cgem_detach(dev); 1745 return (err); 1746 } 1747 1748 cgem_add_sysctls(dev); 1749 1750 return (0); 1751 } 1752 1753 static int 1754 cgem_detach(device_t dev) 1755 { 1756 struct cgem_softc *sc = device_get_softc(dev); 1757 int i; 1758 1759 if (sc == NULL) 1760 return (ENODEV); 1761 1762 if (device_is_attached(dev)) { 1763 CGEM_LOCK(sc); 1764 cgem_stop(sc); 1765 CGEM_UNLOCK(sc); 1766 callout_drain(&sc->tick_ch); 1767 if_setflagbits(sc->ifp, 0, IFF_UP); 1768 ether_ifdetach(sc->ifp); 1769 } 1770 1771 if (sc->miibus != NULL) { 1772 device_delete_child(dev, sc->miibus); 1773 sc->miibus = NULL; 1774 } 1775 1776 /* Release resources. */ 1777 if (sc->mem_res != NULL) { 1778 bus_release_resource(dev, SYS_RES_MEMORY, 1779 rman_get_rid(sc->mem_res), sc->mem_res); 1780 sc->mem_res = NULL; 1781 } 1782 if (sc->irq_res != NULL) { 1783 if (sc->intrhand) 1784 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 1785 bus_release_resource(dev, SYS_RES_IRQ, 1786 rman_get_rid(sc->irq_res), sc->irq_res); 1787 sc->irq_res = NULL; 1788 } 1789 1790 /* Release DMA resources. */ 1791 if (sc->rxring != NULL) { 1792 if (sc->rxring_physaddr != 0) { 1793 bus_dmamap_unload(sc->desc_dma_tag, 1794 sc->rxring_dma_map); 1795 sc->rxring_physaddr = 0; 1796 } 1797 bus_dmamem_free(sc->desc_dma_tag, sc->rxring, 1798 sc->rxring_dma_map); 1799 sc->rxring = NULL; 1800 for (i = 0; i < CGEM_NUM_RX_DESCS; i++) 1801 if (sc->rxring_m_dmamap[i] != NULL) { 1802 bus_dmamap_destroy(sc->mbuf_dma_tag, 1803 sc->rxring_m_dmamap[i]); 1804 sc->rxring_m_dmamap[i] = NULL; 1805 } 1806 } 1807 if (sc->txring != NULL) { 1808 if (sc->txring_physaddr != 0) { 1809 bus_dmamap_unload(sc->desc_dma_tag, 1810 sc->txring_dma_map); 1811 sc->txring_physaddr = 0; 1812 } 1813 bus_dmamem_free(sc->desc_dma_tag, sc->txring, 1814 sc->txring_dma_map); 1815 sc->txring = NULL; 1816 for (i = 0; i < CGEM_NUM_TX_DESCS; i++) 1817 if (sc->txring_m_dmamap[i] != NULL) { 1818 bus_dmamap_destroy(sc->mbuf_dma_tag, 1819 sc->txring_m_dmamap[i]); 1820 sc->txring_m_dmamap[i] = NULL; 1821 } 1822 } 1823 if (sc->desc_dma_tag != NULL) { 1824 bus_dma_tag_destroy(sc->desc_dma_tag); 1825 sc->desc_dma_tag = NULL; 1826 } 1827 if (sc->mbuf_dma_tag != NULL) { 1828 bus_dma_tag_destroy(sc->mbuf_dma_tag); 1829 sc->mbuf_dma_tag = NULL; 1830 } 1831 1832 bus_generic_detach(dev); 1833 1834 CGEM_LOCK_DESTROY(sc); 1835 1836 return (0); 1837 } 1838 1839 static device_method_t cgem_methods[] = { 1840 /* Device interface */ 1841 DEVMETHOD(device_probe, cgem_probe), 1842 DEVMETHOD(device_attach, cgem_attach), 1843 DEVMETHOD(device_detach, cgem_detach), 1844 1845 /* Bus interface */ 1846 DEVMETHOD(bus_child_detached, cgem_child_detached), 1847 1848 /* MII interface */ 1849 DEVMETHOD(miibus_readreg, cgem_miibus_readreg), 1850 DEVMETHOD(miibus_writereg, cgem_miibus_writereg), 1851 DEVMETHOD(miibus_statchg, cgem_miibus_statchg), 1852 DEVMETHOD(miibus_linkchg, cgem_miibus_linkchg), 1853 1854 DEVMETHOD_END 1855 }; 1856 1857 static driver_t cgem_driver = { 1858 "cgem", 1859 cgem_methods, 1860 sizeof(struct cgem_softc), 1861 }; 1862 1863 DRIVER_MODULE(cgem, simplebus, cgem_driver, cgem_devclass, NULL, NULL); 1864 DRIVER_MODULE(miibus, cgem, miibus_driver, miibus_devclass, NULL, NULL); 1865 MODULE_DEPEND(cgem, miibus, 1, 1, 1); 1866 MODULE_DEPEND(cgem, ether, 1, 1, 1); 1867