1 /*- 2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef __BXE_H__ 28 #define __BXE_H__ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/sx.h> 39 #include <sys/module.h> 40 #include <sys/endian.h> 41 #include <sys/types.h> 42 #include <sys/malloc.h> 43 #include <sys/kobj.h> 44 #include <sys/bus.h> 45 #include <sys/rman.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/bitstring.h> 51 #include <sys/limits.h> 52 #include <sys/queue.h> 53 #include <sys/taskqueue.h> 54 #include <sys/zlib.h> 55 56 #include <net/if.h> 57 #include <net/if_types.h> 58 #include <net/if_arp.h> 59 #include <net/ethernet.h> 60 #include <net/if_dl.h> 61 #include <net/if_var.h> 62 #include <net/if_media.h> 63 #include <net/if_vlan_var.h> 64 #include <net/bpf.h> 65 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #include <netinet/ip6.h> 69 #include <netinet/tcp.h> 70 #include <netinet/udp.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 75 #include <machine/atomic.h> 76 #include <machine/resource.h> 77 #include <machine/endian.h> 78 #include <machine/bus.h> 79 #include <machine/in_cksum.h> 80 81 #include "device_if.h" 82 #include "bus_if.h" 83 #include "pci_if.h" 84 85 #if _BYTE_ORDER == _LITTLE_ENDIAN 86 #ifndef LITTLE_ENDIAN 87 #define LITTLE_ENDIAN 88 #endif 89 #ifndef __LITTLE_ENDIAN 90 #define __LITTLE_ENDIAN 91 #endif 92 #undef BIG_ENDIAN 93 #undef __BIG_ENDIAN 94 #else /* _BIG_ENDIAN */ 95 #ifndef BIG_ENDIAN 96 #define BIG_ENDIAN 97 #endif 98 #ifndef __BIG_ENDIAN 99 #define __BIG_ENDIAN 100 #endif 101 #undef LITTLE_ENDIAN 102 #undef __LITTLE_ENDIAN 103 #endif 104 105 #include "ecore_mfw_req.h" 106 #include "ecore_fw_defs.h" 107 #include "ecore_hsi.h" 108 #include "ecore_reg.h" 109 #include "bxe_dcb.h" 110 #include "bxe_stats.h" 111 112 #include "bxe_elink.h" 113 114 #define VF_MAC_CREDIT_CNT 0 115 #define VF_VLAN_CREDIT_CNT (0) 116 117 #if __FreeBSD_version < 800054 118 #if defined(__i386__) || defined(__amd64__) 119 #define mb() __asm volatile("mfence;" : : : "memory") 120 #define wmb() __asm volatile("sfence;" : : : "memory") 121 #define rmb() __asm volatile("lfence;" : : : "memory") 122 static __inline void prefetch(void *x) 123 { 124 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 125 } 126 #else 127 #define mb() 128 #define rmb() 129 #define wmb() 130 #define prefetch(x) 131 #endif 132 #endif 133 134 #if __FreeBSD_version >= 1000000 135 #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA 136 #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND 137 #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA 138 #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH 139 #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED 140 #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL 141 #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 142 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST 143 #endif 144 145 #ifndef ARRAY_SIZE 146 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 147 #endif 148 #ifndef ARRSIZE 149 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 150 #endif 151 #ifndef DIV_ROUND_UP 152 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 153 #endif 154 #ifndef roundup 155 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 156 #endif 157 #ifndef ilog2 158 static inline 159 int bxe_ilog2(int x) 160 { 161 int log = 0; 162 while (x >>= 1) log++; 163 return (log); 164 } 165 #define ilog2(x) bxe_ilog2(x) 166 #endif 167 168 #include "ecore_sp.h" 169 170 #define BRCM_VENDORID 0x14e4 171 #define PCI_ANY_ID (uint16_t)(~0U) 172 173 struct bxe_device_type 174 { 175 uint16_t bxe_vid; 176 uint16_t bxe_did; 177 uint16_t bxe_svid; 178 uint16_t bxe_sdid; 179 char *bxe_name; 180 }; 181 182 #define BCM_PAGE_SHIFT 12 183 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 184 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 185 #define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 186 187 #if BCM_PAGE_SIZE != 4096 188 #error Page sizes other than 4KB are unsupported! 189 #endif 190 191 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 192 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) 193 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 194 #else 195 #define U64_LO(addr) ((uint32_t)(addr)) 196 #define U64_HI(addr) (0) 197 #endif 198 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) 199 200 #define SET_FLAG(value, mask, flag) \ 201 do { \ 202 (value) &= ~(mask); \ 203 (value) |= ((flag) << (mask##_SHIFT)); \ 204 } while (0) 205 206 #define GET_FLAG(value, mask) \ 207 (((value) & (mask)) >> (mask##_SHIFT)) 208 209 #define GET_FIELD(value, fname) \ 210 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 211 212 #define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ 213 #define BXE_TSO_MAX_SEGMENTS 32 214 #define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) 215 #define BXE_TSO_MAX_SEG_SIZE 4096 216 217 /* dropless fc FW/HW related params */ 218 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) 219 #define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ 220 ETH_MAX_AGGREGATION_QUEUES_E1 : \ 221 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 222 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) 223 #define FW_PREFETCH_CNT 16 224 #define DROPLESS_FC_HEADROOM 100 225 226 /******************/ 227 /* RX SGE defines */ 228 /******************/ 229 230 #define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ 231 #define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 232 #define RX_SGE_NEXT_PAGE_DESC_CNT 2 233 #define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) 234 #define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) 235 #define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) 236 #define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) 237 #define RX_SGE_MAX (RX_SGE_TOTAL - 1) 238 #define RX_SGE(x) ((x) & RX_SGE_MAX) 239 240 #define RX_SGE_NEXT(x) \ 241 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \ 242 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1) 243 244 #define RX_SGE_MASK_ELEM_SZ 64 245 #define RX_SGE_MASK_ELEM_SHIFT 6 246 #define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) 247 248 /* 249 * Creates a bitmask of all ones in less significant bits. 250 * idx - index of the most significant bit in the created mask. 251 */ 252 #define RX_SGE_ONES_MASK(idx) \ 253 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) 254 #define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) 255 256 /* Number of uint64_t elements in SGE mask array. */ 257 #define RX_SGE_MASK_LEN \ 258 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) 259 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 260 #define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 261 262 /* 263 * dropless fc calculations for SGEs 264 * Number of required SGEs is the sum of two: 265 * 1. Number of possible opened aggregations (next packet for 266 * these aggregations will probably consume SGE immidiatelly) 267 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 268 * after placement on BD for new TPA aggregation) 269 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page 270 */ 271 #define NUM_SGE_REQ(sc) \ 272 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) 273 #define NUM_SGE_PG_REQ(sc) \ 274 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) 275 #define SGE_TH_LO(sc) \ 276 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) 277 #define SGE_TH_HI(sc) \ 278 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) 279 280 #define PAGES_PER_SGE_SHIFT 0 281 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 282 #define SGE_PAGE_SIZE BCM_PAGE_SIZE 283 #define SGE_PAGE_SHIFT BCM_PAGE_SHIFT 284 #define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) 285 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 286 #define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) 287 288 /*****************/ 289 /* TX BD defines */ 290 /*****************/ 291 292 #define TX_BD_NUM_PAGES 16 /* must be a power of 2 */ 293 #define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 294 #define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) 295 #define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) 296 #define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) 297 #define TX_BD_MAX (TX_BD_TOTAL - 1) 298 299 #define TX_BD_NEXT(x) \ 300 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \ 301 ((x) + 2) : ((x) + 1)) 302 #define TX_BD(x) ((x) & TX_BD_MAX) 303 #define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) 304 #define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) 305 306 /* 307 * Trigger pending transmits when the number of available BDs is greater 308 * than 1/8 of the total number of usable BDs. 309 */ 310 #define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) 311 #define BXE_TX_TIMEOUT 5 312 313 /*****************/ 314 /* RX BD defines */ 315 /*****************/ 316 317 #define RX_BD_NUM_PAGES 8 /* power of 2 */ 318 #define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 319 #define RX_BD_NEXT_PAGE_DESC_CNT 2 320 #define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) 321 #define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) 322 #define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) 323 #define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) 324 #define RX_BD_MAX (RX_BD_TOTAL - 1) 325 326 #define RX_BD_NEXT(x) \ 327 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \ 328 ((x) + 3) : ((x) + 1)) 329 #define RX_BD(x) ((x) & RX_BD_MAX) 330 #define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) 331 #define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) 332 333 /* 334 * dropless fc calculations for BDs 335 * Number of BDs should be as number of buffers in BRB: 336 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT 337 * "next" elements on each page 338 */ 339 #define NUM_BD_REQ(sc) \ 340 BRB_SIZE(sc) 341 #define NUM_BD_PG_REQ(sc) \ 342 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) 343 #define BD_TH_LO(sc) \ 344 (NUM_BD_REQ(sc) + \ 345 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ 346 FW_DROP_LEVEL(sc)) 347 #define BD_TH_HI(sc) \ 348 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) 349 #define MIN_RX_AVAIL(sc) \ 350 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) 351 #define MIN_RX_SIZE_TPA_HW(sc) \ 352 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 353 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 354 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 355 #define MIN_RX_SIZE_TPA(sc) \ 356 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) 357 #define MIN_RX_SIZE_NONTPA(sc) \ 358 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) 359 360 /***************/ 361 /* RCQ defines */ 362 /***************/ 363 364 /* 365 * As long as CQE is X times bigger than BD entry we have to allocate X times 366 * more pages for CQ ring in order to keep it balanced with BD ring 367 */ 368 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / \ 369 sizeof(struct eth_rx_bd)) 370 #define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ 371 #define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 372 #define RCQ_NEXT_PAGE_DESC_CNT 1 373 #define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) 374 #define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) 375 #define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) 376 #define RCQ_MAX (RCQ_TOTAL - 1) 377 378 #define RCQ_NEXT(x) \ 379 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \ 380 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1)) 381 #define RCQ(x) ((x) & RCQ_MAX) 382 #define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) 383 #define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) 384 385 /* 386 * dropless fc calculations for RCQs 387 * Number of RCQs should be as number of buffers in BRB: 388 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT 389 * "next" elements on each page 390 */ 391 #define NUM_RCQ_REQ(sc) \ 392 BRB_SIZE(sc) 393 #define NUM_RCQ_PG_REQ(sc) \ 394 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) 395 #define RCQ_TH_LO(sc) \ 396 (NUM_RCQ_REQ(sc) + \ 397 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ 398 FW_DROP_LEVEL(sc)) 399 #define RCQ_TH_HI(sc) \ 400 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) 401 402 /* This is needed for determening of last_max */ 403 #define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) 404 405 #define __SGE_MASK_SET_BIT(el, bit) \ 406 do { \ 407 (el) = ((el) | ((uint64_t)0x1 << (bit))); \ 408 } while (0) 409 410 #define __SGE_MASK_CLEAR_BIT(el, bit) \ 411 do { \ 412 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \ 413 } while (0) 414 415 #define SGE_MASK_SET_BIT(fp, idx) \ 416 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 417 ((idx) & RX_SGE_MASK_ELEM_MASK)) 418 419 #define SGE_MASK_CLEAR_BIT(fp, idx) \ 420 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 421 ((idx) & RX_SGE_MASK_ELEM_MASK)) 422 423 /* Load / Unload modes */ 424 #define LOAD_NORMAL 0 425 #define LOAD_OPEN 1 426 #define LOAD_DIAG 2 427 #define LOAD_LOOPBACK_EXT 3 428 #define UNLOAD_NORMAL 0 429 #define UNLOAD_CLOSE 1 430 #define UNLOAD_RECOVERY 2 431 432 /* Some constants... */ 433 //#define MAX_PATH_NUM 2 434 //#define E2_MAX_NUM_OF_VFS 64 435 //#define E1H_FUNC_MAX 8 436 //#define E2_FUNC_MAX 4 /* per path */ 437 #define MAX_VNIC_NUM 4 438 #define MAX_FUNC_NUM 8 /* common to all chips */ 439 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ 440 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */ 441 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */ 442 443 #define ILT_NUM_PAGE_ENTRIES 3072 444 /* 445 * 57710/11 we use whole table since we have 8 functions. 446 * 57712 we have only 4 functions, but use same size per func, so only half 447 * of the table is used. 448 */ 449 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) 450 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 451 /* 452 * the phys address is shifted right 12 bits and has an added 453 * 1=valid bit added to the 53rd bit 454 * then since this is a wide register(TM) 455 * we split it into two 32 bit writes 456 */ 457 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 458 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 459 460 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 461 #define ETH_HLEN 14 462 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 463 #define ETH_MIN_PACKET_SIZE 60 464 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ 465 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 466 /* TCP with Timestamp Option (32) + IPv6 (40) */ 467 #define ETH_MAX_TPA_HEADER_SIZE 72 468 469 /* max supported alignment is 256 (8 shift) */ 470 //#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8) 471 #define BXE_RX_ALIGN_SHIFT 8 472 /* FW uses 2 cache lines alignment for start packet and size */ 473 #define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) 474 #define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) 475 476 #define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ 477 478 struct bxe_bar { 479 struct resource *resource; 480 int rid; 481 bus_space_tag_t tag; 482 bus_space_handle_t handle; 483 vm_offset_t kva; 484 }; 485 486 struct bxe_intr { 487 struct resource *resource; 488 int rid; 489 void *tag; 490 }; 491 492 /* Used to manage DMA allocations. */ 493 struct bxe_dma { 494 struct bxe_softc *sc; 495 bus_addr_t paddr; 496 void *vaddr; 497 bus_dma_tag_t tag; 498 bus_dmamap_t map; 499 bus_dma_segment_t seg; 500 bus_size_t size; 501 int nseg; 502 char msg[32]; 503 }; 504 505 /* attn group wiring */ 506 #define MAX_DYNAMIC_ATTN_GRPS 8 507 508 struct attn_route { 509 uint32_t sig[5]; 510 }; 511 512 struct iro { 513 uint32_t base; 514 uint16_t m1; 515 uint16_t m2; 516 uint16_t m3; 517 uint16_t size; 518 }; 519 520 union bxe_host_hc_status_block { 521 /* pointer to fp status block e2 */ 522 struct host_hc_status_block_e2 *e2_sb; 523 /* pointer to fp status block e1x */ 524 struct host_hc_status_block_e1x *e1x_sb; 525 }; 526 527 union bxe_db_prod { 528 struct doorbell_set_prod data; 529 uint32_t raw; 530 }; 531 532 struct bxe_sw_tx_bd { 533 struct mbuf *m; 534 bus_dmamap_t m_map; 535 uint16_t first_bd; 536 uint8_t flags; 537 /* set on the first BD descriptor when there is a split BD */ 538 #define BXE_TSO_SPLIT_BD (1 << 0) 539 }; 540 541 struct bxe_sw_rx_bd { 542 struct mbuf *m; 543 bus_dmamap_t m_map; 544 }; 545 546 struct bxe_sw_tpa_info { 547 struct bxe_sw_rx_bd bd; 548 bus_dma_segment_t seg; 549 uint8_t state; 550 #define BXE_TPA_STATE_START 1 551 #define BXE_TPA_STATE_STOP 2 552 uint8_t placement_offset; 553 uint16_t parsing_flags; 554 uint16_t vlan_tag; 555 uint16_t len_on_bd; 556 }; 557 558 /* 559 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN 560 * instances of the fastpath structure when using multiple queues. 561 */ 562 struct bxe_fastpath { 563 /* pointer back to parent structure */ 564 struct bxe_softc *sc; 565 566 struct mtx tx_mtx; 567 char tx_mtx_name[32]; 568 struct mtx rx_mtx; 569 char rx_mtx_name[32]; 570 571 #define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) 572 #define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) 573 #define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) 574 #define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx) 575 576 #define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) 577 #define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) 578 #define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) 579 580 /* status block */ 581 struct bxe_dma sb_dma; 582 union bxe_host_hc_status_block status_block; 583 584 /* transmit chain (tx bds) */ 585 struct bxe_dma tx_dma; 586 union eth_tx_bd_types *tx_chain; 587 588 /* receive chain (rx bds) */ 589 struct bxe_dma rx_dma; 590 struct eth_rx_bd *rx_chain; 591 592 /* receive completion queue chain (rcq bds) */ 593 struct bxe_dma rcq_dma; 594 union eth_rx_cqe *rcq_chain; 595 596 /* receive scatter/gather entry chain (for TPA) */ 597 struct bxe_dma rx_sge_dma; 598 struct eth_rx_sge *rx_sge_chain; 599 600 /* tx mbufs */ 601 bus_dma_tag_t tx_mbuf_tag; 602 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]; 603 604 /* rx mbufs */ 605 bus_dma_tag_t rx_mbuf_tag; 606 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]; 607 bus_dmamap_t rx_mbuf_spare_map; 608 609 /* rx sge mbufs */ 610 bus_dma_tag_t rx_sge_mbuf_tag; 611 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]; 612 bus_dmamap_t rx_sge_mbuf_spare_map; 613 614 /* rx tpa mbufs (use the larger size for TPA queue length) */ 615 int tpa_enable; /* disabled per fastpath upon error */ 616 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 617 bus_dmamap_t rx_tpa_info_mbuf_spare_map; 618 uint64_t rx_tpa_queue_used; 619 620 uint16_t *sb_index_values; 621 uint16_t *sb_running_index; 622 uint32_t ustorm_rx_prods_offset; 623 624 uint8_t igu_sb_id; /* status block number in HW */ 625 uint8_t fw_sb_id; /* status block number in FW */ 626 627 uint32_t rx_buf_size; 628 int mbuf_alloc_size; 629 630 int state; 631 #define BXE_FP_STATE_CLOSED 0x01 632 #define BXE_FP_STATE_IRQ 0x02 633 #define BXE_FP_STATE_OPENING 0x04 634 #define BXE_FP_STATE_OPEN 0x08 635 #define BXE_FP_STATE_HALTING 0x10 636 #define BXE_FP_STATE_HALTED 0x20 637 638 /* reference back to this fastpath queue number */ 639 uint8_t index; /* this is also the 'cid' */ 640 #define FP_IDX(fp) (fp->index) 641 642 /* interrupt taskqueue (fast) */ 643 struct task tq_task; 644 struct taskqueue *tq; 645 char tq_name[32]; 646 647 struct task tx_task; 648 struct timeout_task tx_timeout_task; 649 650 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ 651 uint8_t cl_id; 652 #define FP_CL_ID(fp) (fp->cl_id) 653 uint8_t cl_qzone_id; 654 655 uint16_t fp_hc_idx; 656 657 /* driver copy of the receive buffer descriptor prod/cons indices */ 658 uint16_t rx_bd_prod; 659 uint16_t rx_bd_cons; 660 661 /* driver copy of the receive completion queue prod/cons indices */ 662 uint16_t rx_cq_prod; 663 uint16_t rx_cq_cons; 664 665 union bxe_db_prod tx_db; 666 667 /* Transmit packet producer index (used in eth_tx_bd). */ 668 uint16_t tx_pkt_prod; 669 uint16_t tx_pkt_cons; 670 671 /* Transmit buffer descriptor producer index. */ 672 uint16_t tx_bd_prod; 673 uint16_t tx_bd_cons; 674 675 uint64_t sge_mask[RX_SGE_MASK_LEN]; 676 uint16_t rx_sge_prod; 677 678 struct tstorm_per_queue_stats old_tclient; 679 struct ustorm_per_queue_stats old_uclient; 680 struct xstorm_per_queue_stats old_xclient; 681 struct bxe_eth_q_stats eth_q_stats; 682 struct bxe_eth_q_stats_old eth_q_stats_old; 683 684 /* Pointer to the receive consumer in the status block */ 685 uint16_t *rx_cq_cons_sb; 686 687 /* Pointer to the transmit consumer in the status block */ 688 uint16_t *tx_cons_sb; 689 690 /* transmit timeout until chip reset */ 691 int watchdog_timer; 692 693 /* Free/used buffer descriptor counters. */ 694 //uint16_t used_tx_bd; 695 696 /* Last maximal completed SGE */ 697 uint16_t last_max_sge; 698 699 //uint16_t rx_sge_free_idx; 700 701 //uint8_t segs; 702 703 #if __FreeBSD_version >= 800000 704 #define BXE_BR_SIZE 4096 705 struct buf_ring *tx_br; 706 #endif 707 }; /* struct bxe_fastpath */ 708 709 /* sriov XXX */ 710 #define BXE_MAX_NUM_OF_VFS 64 711 #define BXE_VF_CID_WND 0 712 #define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) 713 #define BXE_CLIENTS_PER_VF 1 714 #define BXE_FIRST_VF_CID 256 715 #define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) 716 #define BXE_VF_ID_INVALID 0xFF 717 #define IS_SRIOV(sc) 0 718 719 #define GET_NUM_VFS_PER_PATH(sc) 0 720 #define GET_NUM_VFS_PER_PF(sc) 0 721 722 /* maximum number of fast-path interrupt contexts */ 723 #define FP_SB_MAX_E1x 16 724 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 725 726 union cdu_context { 727 struct eth_context eth; 728 char pad[1024]; 729 }; 730 731 /* CDU host DB constants */ 732 #define CDU_ILT_PAGE_SZ_HW 2 733 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 734 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 735 736 #define CNIC_ISCSI_CID_MAX 256 737 #define CNIC_FCOE_CID_MAX 2048 738 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 739 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 740 741 #define QM_ILT_PAGE_SZ_HW 0 742 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 743 #define QM_CID_ROUND 1024 744 745 /* TM (timers) host DB constants */ 746 #define TM_ILT_PAGE_SZ_HW 0 747 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 748 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 749 #define TM_CONN_NUM 1024 750 #define TM_ILT_SZ (8 * TM_CONN_NUM) 751 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 752 753 /* SRC (Searcher) host DB constants */ 754 #define SRC_ILT_PAGE_SZ_HW 0 755 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 756 #define SRC_HASH_BITS 10 757 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 758 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 759 #define SRC_T2_SZ SRC_ILT_SZ 760 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 761 762 struct hw_context { 763 struct bxe_dma vcxt_dma; 764 union cdu_context *vcxt; 765 //bus_addr_t cxt_mapping; 766 size_t size; 767 }; 768 769 #define SM_RX_ID 0 770 #define SM_TX_ID 1 771 772 /* defines for multiple tx priority indices */ 773 #define FIRST_TX_ONLY_COS_INDEX 1 774 #define FIRST_TX_COS_INDEX 0 775 776 #define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) 777 778 #define HC_INDEX_ETH_RX_CQ_CONS 1 779 #define HC_INDEX_OOO_TX_CQ_CONS 4 780 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 781 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 782 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 783 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 784 785 /* congestion management fairness mode */ 786 #define CMNG_FNS_NONE 0 787 #define CMNG_FNS_MINMAX 1 788 789 /* CMNG constants, as derived from system spec calculations */ 790 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 791 #define DEF_MIN_RATE 100 792 /* resolution of the rate shaping timer - 400 usec */ 793 #define RS_PERIODIC_TIMEOUT_USEC 400 794 /* number of bytes in single QM arbitration cycle - 795 * coefficient for calculating the fairness timer */ 796 #define QM_ARB_BYTES 160000 797 /* resolution of Min algorithm 1:100 */ 798 #define MIN_RES 100 799 /* how many bytes above threshold for the minimal credit of Min algorithm*/ 800 #define MIN_ABOVE_THRESH 32768 801 /* fairness algorithm integration time coefficient - 802 * for calculating the actual Tfair */ 803 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 804 /* memory of fairness algorithm - 2 cycles */ 805 #define FAIR_MEM 2 806 807 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ 808 #define HC_SEG_ACCESS_ATTN 4 809 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ 810 811 /* 812 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 813 * control by the number of fast-path status blocks supported by the 814 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 815 * status block represents an independent interrupts context that can 816 * serve a regular L2 networking queue. However special L2 queues such 817 * as the FCoE queue do not require a FP-SB and other components like 818 * the CNIC may consume FP-SB reducing the number of possible L2 queues 819 * 820 * If the maximum number of FP-SB available is X then: 821 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 822 * regular L2 queues is Y=X-1 823 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 824 * c. If the FCoE L2 queue is supported the actual number of L2 queues 825 * is Y+1 826 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 827 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 828 * FP interrupt context for the CNIC). 829 * e. The number of HW context (CID count) is always X or X+1 if FCoE 830 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 831 * 832 * So this is quite simple for now as no ULPs are supported yet. :-) 833 */ 834 #define BXE_NUM_QUEUES(sc) ((sc)->num_queues) 835 #define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) 836 #define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) 837 #define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) 838 839 #define FOR_EACH_QUEUE(sc, var) \ 840 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) 841 842 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ 843 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) 844 845 #define FOR_EACH_ETH_QUEUE(sc, var) \ 846 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 847 848 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ 849 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 850 851 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ 852 for ((var) = 0; (var) < (sc)->max_cos; (var)++) 853 854 #define FOR_EACH_CNIC_QUEUE(sc, var) \ 855 for ((var) = BXE_NUM_ETH_QUEUES(sc); \ 856 (var) < BXE_NUM_QUEUES(sc); \ 857 (var)++) 858 859 enum { 860 OOO_IDX_OFFSET, 861 FCOE_IDX_OFFSET, 862 FWD_IDX_OFFSET, 863 }; 864 865 #define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) 866 #define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) 867 #define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) 868 #define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) 869 #define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) 870 #define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) 871 872 #define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) 873 #define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) 874 #define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) 875 #define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) 876 #define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) 877 878 #define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) 879 #define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) 880 #define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) 881 #define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) 882 #define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) 883 #define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) 884 885 #define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) 886 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) 887 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) 888 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) 889 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) 890 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) 891 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) 892 893 enum { 894 BXE_PORT_QUERY_IDX, 895 BXE_PF_QUERY_IDX, 896 BXE_FCOE_QUERY_IDX, 897 BXE_FIRST_QUEUE_QUERY_IDX, 898 }; 899 900 struct bxe_fw_stats_req { 901 struct stats_query_header hdr; 902 struct stats_query_entry query[FP_SB_MAX_E1x + 903 BXE_FIRST_QUEUE_QUERY_IDX]; 904 }; 905 906 struct bxe_fw_stats_data { 907 struct stats_counter storm_counters; 908 struct per_port_stats port; 909 struct per_pf_stats pf; 910 //struct fcoe_statistics_params fcoe; 911 struct per_queue_stats queue_stats[1]; 912 }; 913 914 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 915 #define BXE_IGU_STAS_MSG_VF_CNT 64 916 #define BXE_IGU_STAS_MSG_PF_CNT 4 917 918 #define MAX_DMAE_C 8 919 920 /* 921 * For the main interface up/down code paths, a not-so-fine-grained CORE 922 * mutex lock is used. Inside this code are various calls to kernel routines 923 * that can cause a sleep to occur. Namely memory allocations and taskqueue 924 * handling. If using an MTX lock we are *not* allowed to sleep but we can 925 * with an SX lock. This define forces the CORE lock to use and SX lock. 926 * Undefine this and an MTX lock will be used instead. Note that the IOCTL 927 * path can cause problems since it's called by a non-sleepable thread. To 928 * alleviate a potential sleep, any IOCTL processing that results in the 929 * chip/interface being started/stopped/reinitialized, the actual work is 930 * offloaded to a taskqueue. 931 */ 932 #define BXE_CORE_LOCK_SX 933 934 /* 935 * This is the slowpath data structure. It is mapped into non-paged memory 936 * so that the hardware can access it's contents directly and must be page 937 * aligned. 938 */ 939 struct bxe_slowpath { 940 941 /* used by the DMAE command executer */ 942 struct dmae_cmd dmae[MAX_DMAE_C]; 943 944 /* statistics completion */ 945 uint32_t stats_comp; 946 947 /* firmware defined statistics blocks */ 948 union mac_stats mac_stats; 949 struct nig_stats nig_stats; 950 struct host_port_stats port_stats; 951 struct host_func_stats func_stats; 952 //struct host_func_stats func_stats_base; 953 954 /* DMAE completion value and data source/sink */ 955 uint32_t wb_comp; 956 uint32_t wb_data[4]; 957 958 union { 959 struct mac_configuration_cmd e1x; 960 struct eth_classify_rules_ramrod_data e2; 961 } mac_rdata; 962 963 union { 964 struct tstorm_eth_mac_filter_config e1x; 965 struct eth_filter_rules_ramrod_data e2; 966 } rx_mode_rdata; 967 968 struct eth_rss_update_ramrod_data rss_rdata; 969 970 union { 971 struct mac_configuration_cmd e1; 972 struct eth_multicast_rules_ramrod_data e2; 973 } mcast_rdata; 974 975 union { 976 struct function_start_data func_start; 977 struct flow_control_configuration pfc_config; /* for DCBX ramrod */ 978 } func_rdata; 979 980 /* Queue State related ramrods */ 981 union { 982 struct client_init_ramrod_data init_data; 983 struct client_update_ramrod_data update_data; 984 } q_rdata; 985 986 /* 987 * AFEX ramrod can not be a part of func_rdata union because these 988 * events might arrive in parallel to other events from func_rdata. 989 * If they were defined in the same union the data can get corrupted. 990 */ 991 struct afex_vif_list_ramrod_data func_afex_rdata; 992 993 union drv_info_to_mcp drv_info_to_mcp; 994 }; /* struct bxe_slowpath */ 995 996 /* 997 * Port specifc data structure. 998 */ 999 struct bxe_port { 1000 /* 1001 * Port Management Function (for 57711E only). 1002 * When this field is set the driver instance is 1003 * responsible for managing port specifc 1004 * configurations such as handling link attentions. 1005 */ 1006 uint32_t pmf; 1007 1008 /* Ethernet maximum transmission unit. */ 1009 uint16_t ether_mtu; 1010 1011 uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; 1012 1013 uint32_t ext_phy_config; 1014 1015 /* Port feature config.*/ 1016 uint32_t config; 1017 1018 /* Defines the features supported by the PHY. */ 1019 uint32_t supported[ELINK_LINK_CONFIG_SIZE]; 1020 1021 /* Defines the features advertised by the PHY. */ 1022 uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; 1023 #define ADVERTISED_10baseT_Half (1 << 1) 1024 #define ADVERTISED_10baseT_Full (1 << 2) 1025 #define ADVERTISED_100baseT_Half (1 << 3) 1026 #define ADVERTISED_100baseT_Full (1 << 4) 1027 #define ADVERTISED_1000baseT_Half (1 << 5) 1028 #define ADVERTISED_1000baseT_Full (1 << 6) 1029 #define ADVERTISED_TP (1 << 7) 1030 #define ADVERTISED_FIBRE (1 << 8) 1031 #define ADVERTISED_Autoneg (1 << 9) 1032 #define ADVERTISED_Asym_Pause (1 << 10) 1033 #define ADVERTISED_Pause (1 << 11) 1034 #define ADVERTISED_2500baseX_Full (1 << 15) 1035 #define ADVERTISED_10000baseT_Full (1 << 16) 1036 1037 uint32_t phy_addr; 1038 1039 /* Used to synchronize phy accesses. */ 1040 struct mtx phy_mtx; 1041 char phy_mtx_name[32]; 1042 1043 #define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) 1044 #define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) 1045 #define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) 1046 1047 /* 1048 * MCP scratchpad address for port specific statistics. 1049 * The device is responsible for writing statistcss 1050 * back to the MCP for use with management firmware such 1051 * as UMP/NC-SI. 1052 */ 1053 uint32_t port_stx; 1054 1055 struct nig_stats old_nig_stats; 1056 }; /* struct bxe_port */ 1057 1058 struct bxe_mf_info { 1059 uint32_t mf_config[E1HVN_MAX]; 1060 1061 uint32_t vnics_per_port; /* 1, 2 or 4 */ 1062 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ 1063 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ 1064 1065 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) 1066 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) 1067 #define VNICS_PER_PATH(sc) \ 1068 ((sc)->devinfo.mf_info.vnics_per_port * \ 1069 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) 1070 1071 uint8_t min_bw[MAX_VNIC_NUM]; 1072 uint8_t max_bw[MAX_VNIC_NUM]; 1073 1074 uint16_t ext_id; /* vnic outer vlan or VIF ID */ 1075 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096) 1076 #define INVALID_VIF_ID 0xFFFF 1077 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) 1078 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) 1079 1080 uint16_t default_vlan; 1081 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) 1082 1083 uint8_t niv_allowed_priorities; 1084 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) 1085 1086 uint8_t niv_default_cos; 1087 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) 1088 1089 uint8_t niv_mba_enabled; 1090 1091 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1092 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) 1093 int afex_def_vlan_tag; 1094 uint32_t pending_max; 1095 1096 uint16_t flags; 1097 #define MF_INFO_VALID_MAC 0x0001 1098 1099 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ 1100 #define IS_MF(sc) \ 1101 (IS_MULTI_VNIC(sc) && \ 1102 ((sc)->devinfo.mf_info.mf_mode != 0)) 1103 #define IS_MF_SD(sc) \ 1104 (IS_MULTI_VNIC(sc) && \ 1105 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) 1106 #define IS_MF_SI(sc) \ 1107 (IS_MULTI_VNIC(sc) && \ 1108 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) 1109 #define IS_MF_AFEX(sc) \ 1110 (IS_MULTI_VNIC(sc) && \ 1111 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) 1112 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc) 1113 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc) 1114 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) 1115 1116 uint32_t mf_protos_supported; 1117 #define MF_PROTO_SUPPORT_ETHERNET 0x1 1118 #define MF_PROTO_SUPPORT_ISCSI 0x2 1119 #define MF_PROTO_SUPPORT_FCOE 0x4 1120 }; /* struct bxe_mf_info */ 1121 1122 /* Device information data structure. */ 1123 struct bxe_devinfo { 1124 /* PCIe info */ 1125 uint16_t vendor_id; 1126 uint16_t device_id; 1127 uint16_t subvendor_id; 1128 uint16_t subdevice_id; 1129 1130 /* 1131 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' 1132 * C = Chip Number (bits 16-31) 1133 * R = Chip Revision (bits 12-15) 1134 * M = Chip Metal (bits 4-11) 1135 * B = Chip Bond ID (bits 0-3) 1136 */ 1137 uint32_t chip_id; 1138 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) 1139 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) 1140 /* device ids */ 1141 #define CHIP_NUM_57710 0x164e 1142 #define CHIP_NUM_57711 0x164f 1143 #define CHIP_NUM_57711E 0x1650 1144 #define CHIP_NUM_57712 0x1662 1145 #define CHIP_NUM_57712_MF 0x1663 1146 #define CHIP_NUM_57712_VF 0x166f 1147 #define CHIP_NUM_57800 0x168a 1148 #define CHIP_NUM_57800_MF 0x16a5 1149 #define CHIP_NUM_57800_VF 0x16a9 1150 #define CHIP_NUM_57810 0x168e 1151 #define CHIP_NUM_57810_MF 0x16ae 1152 #define CHIP_NUM_57810_VF 0x16af 1153 #define CHIP_NUM_57811 0x163d 1154 #define CHIP_NUM_57811_MF 0x163e 1155 #define CHIP_NUM_57811_VF 0x163f 1156 #define CHIP_NUM_57840_OBS 0x168d 1157 #define CHIP_NUM_57840_OBS_MF 0x16ab 1158 #define CHIP_NUM_57840_4_10 0x16a1 1159 #define CHIP_NUM_57840_2_20 0x16a2 1160 #define CHIP_NUM_57840_MF 0x16a4 1161 #define CHIP_NUM_57840_VF 0x16ad 1162 1163 #define CHIP_REV_SHIFT 12 1164 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1165 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) 1166 1167 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1168 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1169 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) 1170 1171 #define CHIP_REV_IS_SLOW(sc) \ 1172 (CHIP_REV(sc) > 0x00005000) 1173 #define CHIP_REV_IS_FPGA(sc) \ 1174 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) 1175 #define CHIP_REV_IS_EMUL(sc) \ 1176 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) 1177 #define CHIP_REV_IS_ASIC(sc) \ 1178 (!CHIP_REV_IS_SLOW(sc)) 1179 1180 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) 1181 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) 1182 1183 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1184 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1185 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) 1186 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) 1187 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ 1188 (CHIP_IS_57711E(sc))) 1189 #define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ 1190 CHIP_IS_E1H((sc))) 1191 1192 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) 1193 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) 1194 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) 1195 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ 1196 CHIP_IS_57712_MF(sc)) 1197 1198 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) 1199 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) 1200 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) 1201 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) 1202 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) 1203 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) 1204 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) 1205 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) 1206 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) 1207 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ 1208 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ 1209 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) 1210 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ 1211 (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) 1212 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) 1213 1214 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ 1215 CHIP_IS_57800_MF(sc) || \ 1216 CHIP_IS_57800_VF(sc) || \ 1217 CHIP_IS_57810(sc) || \ 1218 CHIP_IS_57810_MF(sc) || \ 1219 CHIP_IS_57810_VF(sc) || \ 1220 CHIP_IS_57811(sc) || \ 1221 CHIP_IS_57811_MF(sc) || \ 1222 CHIP_IS_57811_VF(sc) || \ 1223 CHIP_IS_57840(sc) || \ 1224 CHIP_IS_57840_MF(sc) || \ 1225 CHIP_IS_57840_VF(sc)) 1226 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ 1227 (CHIP_REV(sc) == CHIP_REV_Ax)) 1228 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ 1229 (CHIP_REV(sc) == CHIP_REV_Bx)) 1230 1231 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) 1232 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ 1233 CHIP_IS_E3(sc)) 1234 1235 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ 1236 CHIP_IS_57712_MF(sc) || \ 1237 CHIP_IS_E3(sc)) 1238 1239 #define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ 1240 CHIP_IS_57800_VF(sc) || \ 1241 CHIP_IS_57810_VF(sc) || \ 1242 CHIP_IS_57840_VF(sc)) 1243 #define IS_PF(sc) (!IS_VF(sc)) 1244 1245 /* 1246 * This define is used in two main places: 1247 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher 1248 * to nic-only mode or to offload mode. Offload mode is configured if either 1249 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic 1250 * already registered for this port (which means that the user wants storage 1251 * services). 1252 * 2. During cnic-related load, to know if offload mode is already configured 1253 * in the HW or needs to be configrued. Since the transition from nic-mode to 1254 * offload-mode in HW causes traffic coruption, nic-mode is configured only 1255 * in ports on which storage services where never requested. 1256 */ 1257 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) 1258 1259 uint8_t chip_port_mode; 1260 #define CHIP_4_PORT_MODE 0x0 1261 #define CHIP_2_PORT_MODE 0x1 1262 #define CHIP_PORT_MODE_NONE 0x2 1263 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) 1264 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) 1265 1266 uint8_t int_block; 1267 #define INT_BLOCK_HC 0 1268 #define INT_BLOCK_IGU 1 1269 #define INT_BLOCK_MODE_NORMAL 0 1270 #define INT_BLOCK_MODE_BW_COMP 2 1271 #define CHIP_INT_MODE_IS_NBC(sc) \ 1272 (!CHIP_IS_E1x(sc) && \ 1273 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) 1274 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) 1275 1276 uint32_t shmem_base; 1277 uint32_t shmem2_base; 1278 uint32_t bc_ver; 1279 char bc_ver_str[32]; 1280 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ 1281 struct bxe_mf_info mf_info; 1282 1283 int flash_size; 1284 #define NVRAM_1MB_SIZE 0x20000 1285 #define NVRAM_TIMEOUT_COUNT 30000 1286 #define NVRAM_PAGE_SIZE 256 1287 1288 /* PCIe capability information */ 1289 uint32_t pcie_cap_flags; 1290 #define BXE_PM_CAPABLE_FLAG 0x00000001 1291 #define BXE_PCIE_CAPABLE_FLAG 0x00000002 1292 #define BXE_MSI_CAPABLE_FLAG 0x00000004 1293 #define BXE_MSIX_CAPABLE_FLAG 0x00000008 1294 uint16_t pcie_pm_cap_reg; 1295 uint16_t pcie_pcie_cap_reg; 1296 //uint16_t pcie_devctl; 1297 uint16_t pcie_link_width; 1298 uint16_t pcie_link_speed; 1299 uint16_t pcie_msi_cap_reg; 1300 uint16_t pcie_msix_cap_reg; 1301 1302 /* device configuration read from bootcode shared memory */ 1303 uint32_t hw_config; 1304 uint32_t hw_config2; 1305 }; /* struct bxe_devinfo */ 1306 1307 struct bxe_sp_objs { 1308 struct ecore_vlan_mac_obj mac_obj; /* MACs object */ 1309 struct ecore_queue_sp_obj q_obj; /* Queue State object */ 1310 }; /* struct bxe_sp_objs */ 1311 1312 /* 1313 * Data that will be used to create a link report message. We will keep the 1314 * data used for the last link report in order to prevent reporting the same 1315 * link parameters twice. 1316 */ 1317 struct bxe_link_report_data { 1318 uint16_t line_speed; /* Effective line speed */ 1319 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */ 1320 }; 1321 enum { 1322 BXE_LINK_REPORT_FULL_DUPLEX, 1323 BXE_LINK_REPORT_LINK_DOWN, 1324 BXE_LINK_REPORT_RX_FC_ON, 1325 BXE_LINK_REPORT_TX_FC_ON 1326 }; 1327 1328 /* Top level device private data structure. */ 1329 struct bxe_softc { 1330 /* 1331 * First entry must be a pointer to the BSD ifnet struct which 1332 * has a first element of 'void *if_softc' (which is us). XXX 1333 */ 1334 if_t ifp; 1335 struct ifmedia ifmedia; /* network interface media structure */ 1336 int media; 1337 1338 int state; /* device state */ 1339 #define BXE_STATE_CLOSED 0x0000 1340 #define BXE_STATE_OPENING_WAITING_LOAD 0x1000 1341 #define BXE_STATE_OPENING_WAITING_PORT 0x2000 1342 #define BXE_STATE_OPEN 0x3000 1343 #define BXE_STATE_CLOSING_WAITING_HALT 0x4000 1344 #define BXE_STATE_CLOSING_WAITING_DELETE 0x5000 1345 #define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 1346 #define BXE_STATE_DISABLED 0xD000 1347 #define BXE_STATE_DIAG 0xE000 1348 #define BXE_STATE_ERROR 0xF000 1349 1350 int flags; 1351 #define BXE_ONE_PORT_FLAG 0x00000001 1352 #define BXE_NO_ISCSI 0x00000002 1353 #define BXE_NO_FCOE 0x00000004 1354 #define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) 1355 //#define BXE_NO_WOL_FLAG 0x00000008 1356 //#define BXE_USING_DAC_FLAG 0x00000010 1357 //#define BXE_USING_MSIX_FLAG 0x00000020 1358 //#define BXE_USING_MSI_FLAG 0x00000040 1359 //#define BXE_DISABLE_MSI_FLAG 0x00000080 1360 #define BXE_NO_MCP_FLAG 0x00000200 1361 #define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) 1362 //#define BXE_SAFC_TX_FLAG 0x00000400 1363 #define BXE_MF_FUNC_DIS 0x00000800 1364 #define BXE_TX_SWITCHING 0x00001000 1365 #define BXE_NO_PULSE 0x00002000 1366 1367 unsigned long debug; /* per-instance debug logging config */ 1368 1369 #define MAX_BARS 5 1370 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ 1371 1372 uint16_t doorbell_size; 1373 1374 /* periodic timer callout */ 1375 #define PERIODIC_STOP 0 1376 #define PERIODIC_GO 1 1377 volatile unsigned long periodic_flags; 1378 struct callout periodic_callout; 1379 1380 /* chip start/stop/reset taskqueue */ 1381 #define CHIP_TQ_NONE 0 1382 #define CHIP_TQ_START 1 1383 #define CHIP_TQ_STOP 2 1384 #define CHIP_TQ_REINIT 3 1385 volatile unsigned long chip_tq_flags; 1386 struct task chip_tq_task; 1387 struct taskqueue *chip_tq; 1388 char chip_tq_name[32]; 1389 1390 /* slowpath interrupt taskqueue */ 1391 struct task sp_tq_task; 1392 struct taskqueue *sp_tq; 1393 char sp_tq_name[32]; 1394 1395 struct bxe_fastpath fp[MAX_RSS_CHAINS]; 1396 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]; 1397 1398 device_t dev; /* parent device handle */ 1399 uint8_t unit; /* driver instance number */ 1400 1401 int pcie_bus; /* PCIe bus number */ 1402 int pcie_device; /* PCIe device/slot number */ 1403 int pcie_func; /* PCIe function number */ 1404 1405 uint8_t pfunc_rel; /* function relative */ 1406 uint8_t pfunc_abs; /* function absolute */ 1407 uint8_t path_id; /* function absolute */ 1408 #define SC_PATH(sc) (sc->path_id) 1409 #define SC_PORT(sc) (sc->pfunc_rel & 1) 1410 #define SC_FUNC(sc) (sc->pfunc_rel) 1411 #define SC_ABS_FUNC(sc) (sc->pfunc_abs) 1412 #define SC_VN(sc) (sc->pfunc_rel >> 1) 1413 #define SC_L_ID(sc) (SC_VN(sc) << 2) 1414 #define PORT_ID(sc) SC_PORT(sc) 1415 #define PATH_ID(sc) SC_PATH(sc) 1416 #define VNIC_ID(sc) SC_VN(sc) 1417 #define FUNC_ID(sc) SC_FUNC(sc) 1418 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) 1419 #define SC_FW_MB_IDX_VN(sc, vn) \ 1420 (SC_PORT(sc) + (vn) * \ 1421 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) 1422 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) 1423 1424 int if_capen; /* enabled interface capabilities */ 1425 1426 struct bxe_devinfo devinfo; 1427 char fw_ver_str[32]; 1428 char mf_mode_str[32]; 1429 char pci_link_str[32]; 1430 1431 const struct iro *iro_array; 1432 1433 #ifdef BXE_CORE_LOCK_SX 1434 struct sx core_sx; 1435 char core_sx_name[32]; 1436 #else 1437 struct mtx core_mtx; 1438 char core_mtx_name[32]; 1439 #endif 1440 struct mtx sp_mtx; 1441 char sp_mtx_name[32]; 1442 struct mtx dmae_mtx; 1443 char dmae_mtx_name[32]; 1444 struct mtx fwmb_mtx; 1445 char fwmb_mtx_name[32]; 1446 struct mtx print_mtx; 1447 char print_mtx_name[32]; 1448 struct mtx stats_mtx; 1449 char stats_mtx_name[32]; 1450 struct mtx mcast_mtx; 1451 char mcast_mtx_name[32]; 1452 1453 #ifdef BXE_CORE_LOCK_SX 1454 #define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) 1455 #define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) 1456 #define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) 1457 #define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) 1458 #else 1459 #define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) 1460 #define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) 1461 #define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) 1462 #define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) 1463 #endif 1464 1465 #define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) 1466 #define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) 1467 #define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) 1468 1469 #define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) 1470 #define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) 1471 #define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) 1472 1473 #define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) 1474 #define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) 1475 #define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) 1476 1477 #define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) 1478 #define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) 1479 #define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) 1480 1481 #define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) 1482 #define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) 1483 #define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) 1484 1485 #if __FreeBSD_version < 800000 1486 #define BXE_MCAST_LOCK(sc) \ 1487 do { \ 1488 mtx_lock(&sc->mcast_mtx); \ 1489 IF_ADDR_LOCK(sc->ifp); \ 1490 } while (0) 1491 #define BXE_MCAST_UNLOCK(sc) \ 1492 do { \ 1493 IF_ADDR_UNLOCK(sc->ifp); \ 1494 mtx_unlock(&sc->mcast_mtx); \ 1495 } while (0) 1496 #else 1497 #define BXE_MCAST_LOCK(sc) \ 1498 do { \ 1499 mtx_lock(&sc->mcast_mtx); \ 1500 if_maddr_rlock(sc->ifp); \ 1501 } while (0) 1502 #define BXE_MCAST_UNLOCK(sc) \ 1503 do { \ 1504 if_maddr_runlock(sc->ifp); \ 1505 mtx_unlock(&sc->mcast_mtx); \ 1506 } while (0) 1507 #endif 1508 #define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) 1509 1510 int dmae_ready; 1511 #define DMAE_READY(sc) (sc->dmae_ready) 1512 1513 struct ecore_credit_pool_obj vlans_pool; 1514 struct ecore_credit_pool_obj macs_pool; 1515 struct ecore_rx_mode_obj rx_mode_obj; 1516 struct ecore_mcast_obj mcast_obj; 1517 struct ecore_rss_config_obj rss_conf_obj; 1518 struct ecore_func_sp_obj func_obj; 1519 1520 uint16_t fw_seq; 1521 uint16_t fw_drv_pulse_wr_seq; 1522 uint32_t func_stx; 1523 1524 struct elink_params link_params; 1525 struct elink_vars link_vars; 1526 uint32_t link_cnt; 1527 struct bxe_link_report_data last_reported_link; 1528 char mac_addr_str[32]; 1529 1530 int last_reported_link_state; 1531 1532 int tx_ring_size; 1533 int rx_ring_size; 1534 int wol; 1535 1536 int is_leader; 1537 int recovery_state; 1538 #define BXE_RECOVERY_DONE 1 1539 #define BXE_RECOVERY_INIT 2 1540 #define BXE_RECOVERY_WAIT 3 1541 #define BXE_RECOVERY_FAILED 4 1542 #define BXE_RECOVERY_NIC_LOADING 5 1543 1544 uint32_t rx_mode; 1545 #define BXE_RX_MODE_NONE 0 1546 #define BXE_RX_MODE_NORMAL 1 1547 #define BXE_RX_MODE_ALLMULTI 2 1548 #define BXE_RX_MODE_PROMISC 3 1549 #define BXE_MAX_MULTICAST 64 1550 1551 struct bxe_port port; 1552 1553 struct cmng_init cmng; 1554 1555 /* user configs */ 1556 int num_queues; 1557 int max_rx_bufs; 1558 int hc_rx_ticks; 1559 int hc_tx_ticks; 1560 int rx_budget; 1561 int max_aggregation_size; 1562 int mrrs; 1563 int autogreeen; 1564 #define AUTO_GREEN_HW_DEFAULT 0 1565 #define AUTO_GREEN_FORCE_ON 1 1566 #define AUTO_GREEN_FORCE_OFF 2 1567 int interrupt_mode; 1568 #define INTR_MODE_INTX 0 1569 #define INTR_MODE_MSI 1 1570 #define INTR_MODE_MSIX 2 1571 int udp_rss; 1572 1573 /* interrupt allocations */ 1574 struct bxe_intr intr[MAX_RSS_CHAINS+1]; 1575 int intr_count; 1576 uint8_t igu_dsb_id; 1577 uint8_t igu_base_sb; 1578 uint8_t igu_sb_cnt; 1579 //uint8_t min_msix_vec_cnt; 1580 uint32_t igu_base_addr; 1581 //bus_addr_t def_status_blk_mapping; 1582 uint8_t base_fw_ndsb; 1583 #define DEF_SB_IGU_ID 16 1584 #define DEF_SB_ID HC_SP_SB_ID 1585 1586 /* parent bus DMA tag */ 1587 bus_dma_tag_t parent_dma_tag; 1588 1589 /* default status block */ 1590 struct bxe_dma def_sb_dma; 1591 struct host_sp_status_block *def_sb; 1592 uint16_t def_idx; 1593 uint16_t def_att_idx; 1594 uint32_t attn_state; 1595 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1596 1597 /* general SP events - stats query, cfc delete, etc */ 1598 #define HC_SP_INDEX_ETH_DEF_CONS 3 1599 /* EQ completions */ 1600 #define HC_SP_INDEX_EQ_CONS 7 1601 /* FCoE L2 connection completions */ 1602 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 1603 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 1604 /* iSCSI L2 */ 1605 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 1606 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 1607 1608 /* event queue */ 1609 struct bxe_dma eq_dma; 1610 union event_ring_elem *eq; 1611 uint16_t eq_prod; 1612 uint16_t eq_cons; 1613 uint16_t *eq_cons_sb; 1614 #define NUM_EQ_PAGES 1 /* must be a power of 2 */ 1615 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1616 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1617 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1618 #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1619 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1620 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1621 #define NEXT_EQ_IDX(x) \ 1622 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ 1623 ((x) + 2) : ((x) + 1)) 1624 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1625 #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1626 1627 /* slow path */ 1628 struct bxe_dma sp_dma; 1629 struct bxe_slowpath *sp; 1630 unsigned long sp_state; 1631 1632 /* slow path queue */ 1633 struct bxe_dma spq_dma; 1634 struct eth_spe *spq; 1635 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1636 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1637 #define MAX_SPQ_PENDING 8 1638 1639 uint16_t spq_prod_idx; 1640 struct eth_spe *spq_prod_bd; 1641 struct eth_spe *spq_last_bd; 1642 uint16_t *dsb_sp_prod; 1643 //uint16_t *spq_hw_con; 1644 //uint16_t spq_left; 1645 1646 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ 1647 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ 1648 1649 /* fw decompression buffer */ 1650 struct bxe_dma gz_buf_dma; 1651 void *gz_buf; 1652 z_streamp gz_strm; 1653 uint32_t gz_outlen; 1654 #define GUNZIP_BUF(sc) (sc->gz_buf) 1655 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen) 1656 #define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) 1657 #define FW_BUF_SIZE 0x40000 1658 1659 const struct raw_op *init_ops; 1660 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ 1661 const uint32_t *init_data; /* data blob, 32 bit granularity */ 1662 uint32_t init_mode_flags; 1663 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) 1664 /* PRAM blobs - raw data */ 1665 const uint8_t *tsem_int_table_data; 1666 const uint8_t *tsem_pram_data; 1667 const uint8_t *usem_int_table_data; 1668 const uint8_t *usem_pram_data; 1669 const uint8_t *xsem_int_table_data; 1670 const uint8_t *xsem_pram_data; 1671 const uint8_t *csem_int_table_data; 1672 const uint8_t *csem_pram_data; 1673 #define INIT_OPS(sc) (sc->init_ops) 1674 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) 1675 #define INIT_DATA(sc) (sc->init_data) 1676 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) 1677 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) 1678 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) 1679 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) 1680 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) 1681 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) 1682 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) 1683 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) 1684 1685 /* ILT 1686 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1687 * context size we need 8 ILT entries. 1688 */ 1689 #define ILT_MAX_L2_LINES 8 1690 struct hw_context context[ILT_MAX_L2_LINES]; 1691 struct ecore_ilt *ilt; 1692 #define ILT_MAX_LINES 256 1693 1694 /* max supported number of RSS queues: IGU SBs minus one for CNIC */ 1695 #define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) 1696 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ 1697 #if 1 1698 #define BXE_L2_MAX_CID(sc) \ 1699 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1700 #else 1701 #define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ 1702 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1703 #endif 1704 #if 1 1705 #define BXE_L2_CID_COUNT(sc) \ 1706 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1707 #else 1708 #define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ 1709 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1710 #endif 1711 #define L2_ILT_LINES(sc) \ 1712 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) 1713 1714 int qm_cid_count; 1715 1716 uint8_t dropless_fc; 1717 1718 /* total number of FW statistics requests */ 1719 uint8_t fw_stats_num; 1720 /* 1721 * This is a memory buffer that will contain both statistics ramrod 1722 * request and data. 1723 */ 1724 struct bxe_dma fw_stats_dma; 1725 /* 1726 * FW statistics request shortcut (points at the beginning of fw_stats 1727 * buffer). 1728 */ 1729 int fw_stats_req_size; 1730 struct bxe_fw_stats_req *fw_stats_req; 1731 bus_addr_t fw_stats_req_mapping; 1732 /* 1733 * FW statistics data shortcut (points at the beginning of fw_stats 1734 * buffer + fw_stats_req_size). 1735 */ 1736 int fw_stats_data_size; 1737 struct bxe_fw_stats_data *fw_stats_data; 1738 bus_addr_t fw_stats_data_mapping; 1739 1740 /* tracking a pending STAT_QUERY ramrod */ 1741 uint16_t stats_pending; 1742 /* number of completed statistics ramrods */ 1743 uint16_t stats_comp; 1744 uint16_t stats_counter; 1745 uint8_t stats_init; 1746 int stats_state; 1747 1748 struct bxe_eth_stats eth_stats; 1749 struct host_func_stats func_stats; 1750 struct bxe_eth_stats_old eth_stats_old; 1751 struct bxe_net_stats_old net_stats_old; 1752 struct bxe_fw_port_stats_old fw_stats_old; 1753 1754 struct dmae_cmd stats_dmae; /* used by dmae command loader */ 1755 int executer_idx; 1756 1757 int mtu; 1758 1759 /* LLDP params */ 1760 struct bxe_config_lldp_params lldp_config_params; 1761 /* DCB support on/off */ 1762 int dcb_state; 1763 #define BXE_DCB_STATE_OFF 0 1764 #define BXE_DCB_STATE_ON 1 1765 /* DCBX engine mode */ 1766 int dcbx_enabled; 1767 #define BXE_DCBX_ENABLED_OFF 0 1768 #define BXE_DCBX_ENABLED_ON_NEG_OFF 1 1769 #define BXE_DCBX_ENABLED_ON_NEG_ON 2 1770 #define BXE_DCBX_ENABLED_INVALID -1 1771 uint8_t dcbx_mode_uset; 1772 struct bxe_config_dcbx_params dcbx_config_params; 1773 struct bxe_dcbx_port_params dcbx_port_params; 1774 int dcb_version; 1775 1776 uint8_t cnic_support; 1777 uint8_t cnic_enabled; 1778 uint8_t cnic_loaded; 1779 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ 1780 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ 1781 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ 1782 1783 /* multiple tx classes of service */ 1784 uint8_t max_cos; 1785 #define BXE_MAX_PRIORITY 8 1786 /* priority to cos mapping */ 1787 uint8_t prio_to_cos[BXE_MAX_PRIORITY]; 1788 1789 int panic; 1790 1791 struct cdev *ioctl_dev; 1792 1793 void *grc_dump; 1794 unsigned int trigger_grcdump; 1795 unsigned int grcdump_done; 1796 unsigned int grcdump_started; 1797 1798 void *eeprom; 1799 }; /* struct bxe_softc */ 1800 1801 /* IOCTL sub-commands for edebug and firmware upgrade */ 1802 #define BXE_IOC_RD_NVRAM 1 1803 #define BXE_IOC_WR_NVRAM 2 1804 #define BXE_IOC_STATS_SHOW_NUM 3 1805 #define BXE_IOC_STATS_SHOW_STR 4 1806 #define BXE_IOC_STATS_SHOW_CNT 5 1807 1808 struct bxe_nvram_data { 1809 uint32_t op; /* ioctl sub-command */ 1810 uint32_t offset; 1811 uint32_t len; 1812 uint32_t value[1]; /* variable */ 1813 }; 1814 1815 union bxe_stats_show_data { 1816 uint32_t op; /* ioctl sub-command */ 1817 1818 struct { 1819 uint32_t num; /* return number of stats */ 1820 uint32_t len; /* length of each string item */ 1821 } desc; 1822 1823 /* variable length... */ 1824 char str[1]; /* holds names of desc.num stats, each desc.len in length */ 1825 1826 /* variable length... */ 1827 uint64_t stats[1]; /* holds all stats */ 1828 }; 1829 1830 /* function init flags */ 1831 #define FUNC_FLG_RSS 0x0001 1832 #define FUNC_FLG_STATS 0x0002 1833 /* FUNC_FLG_UNMATCHED 0x0004 */ 1834 #define FUNC_FLG_TPA 0x0008 1835 #define FUNC_FLG_SPQ 0x0010 1836 #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1837 1838 struct bxe_func_init_params { 1839 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ 1840 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ 1841 uint16_t func_flgs; 1842 uint16_t func_id; /* abs function id */ 1843 uint16_t pf_id; 1844 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ 1845 }; 1846 1847 /* memory resources reside at BARs 0, 2, 4 */ 1848 /* Run `pciconf -lb` to see mappings */ 1849 #define BAR0 0 1850 #define BAR1 2 1851 #define BAR2 4 1852 1853 #ifdef BXE_REG_NO_INLINE 1854 1855 uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset); 1856 uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset); 1857 uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset); 1858 1859 void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val); 1860 void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val); 1861 void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val); 1862 1863 #define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) 1864 #define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) 1865 #define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) 1866 1867 #define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) 1868 #define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) 1869 #define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) 1870 1871 #else /* not BXE_REG_NO_INLINE */ 1872 1873 #define REG_WR8(sc, offset, val) \ 1874 bus_space_write_1(sc->bar[BAR0].tag, \ 1875 sc->bar[BAR0].handle, \ 1876 offset, val) 1877 1878 #define REG_WR16(sc, offset, val) \ 1879 bus_space_write_2(sc->bar[BAR0].tag, \ 1880 sc->bar[BAR0].handle, \ 1881 offset, val) 1882 1883 #define REG_WR32(sc, offset, val) \ 1884 bus_space_write_4(sc->bar[BAR0].tag, \ 1885 sc->bar[BAR0].handle, \ 1886 offset, val) 1887 1888 #define REG_RD8(sc, offset) \ 1889 bus_space_read_1(sc->bar[BAR0].tag, \ 1890 sc->bar[BAR0].handle, \ 1891 offset) 1892 1893 #define REG_RD16(sc, offset) \ 1894 bus_space_read_2(sc->bar[BAR0].tag, \ 1895 sc->bar[BAR0].handle, \ 1896 offset) 1897 1898 #define REG_RD32(sc, offset) \ 1899 bus_space_read_4(sc->bar[BAR0].tag, \ 1900 sc->bar[BAR0].handle, \ 1901 offset) 1902 1903 #endif /* BXE_REG_NO_INLINE */ 1904 1905 #define REG_RD(sc, offset) REG_RD32(sc, offset) 1906 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) 1907 1908 #define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) 1909 #define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) 1910 1911 #define BXE_SP(sc, var) (&(sc)->sp->var) 1912 #define BXE_SP_MAPPING(sc, var) \ 1913 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) 1914 1915 #define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) 1916 #define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) 1917 1918 #define REG_RD_DMAE(sc, offset, valp, len32) \ 1919 do { \ 1920 bxe_read_dmae(sc, offset, len32); \ 1921 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \ 1922 } while (0) 1923 1924 #define REG_WR_DMAE(sc, offset, valp, len32) \ 1925 do { \ 1926 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \ 1927 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \ 1928 } while (0) 1929 1930 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ 1931 REG_WR_DMAE(sc, offset, valp, len32) 1932 1933 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ 1934 REG_RD_DMAE(sc, offset, valp, len32) 1935 1936 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ 1937 do { \ 1938 /* if (le32_swap) { */ \ 1939 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \ 1940 /* } */ \ 1941 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ 1942 ecore_write_big_buf_wb(sc, addr, len32); \ 1943 } while (0) 1944 1945 #define BXE_DB_MIN_SHIFT 3 /* 8 bytes */ 1946 #define BXE_DB_SHIFT 7 /* 128 bytes */ 1947 #if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT) 1948 #error "Minimum DB doorbell stride is 8" 1949 #endif 1950 #define DPM_TRIGGER_TYPE 0x40 1951 #define DOORBELL(sc, cid, val) \ 1952 do { \ 1953 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \ 1954 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \ 1955 (uint32_t)val); \ 1956 } while(0) 1957 1958 #define SHMEM_ADDR(sc, field) \ 1959 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) 1960 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) 1961 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) 1962 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) 1963 1964 #define SHMEM2_ADDR(sc, field) \ 1965 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) 1966 #define SHMEM2_HAS(sc, field) \ 1967 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ 1968 offsetof(struct shmem2_region, field))) 1969 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) 1970 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) 1971 1972 #define MFCFG_ADDR(sc, field) \ 1973 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) 1974 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) 1975 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) 1976 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) 1977 1978 /* DMAE command defines */ 1979 1980 #define DMAE_TIMEOUT -1 1981 #define DMAE_PCI_ERROR -2 /* E2 and onward */ 1982 #define DMAE_NOT_RDY -3 1983 #define DMAE_PCI_ERR_FLAG 0x80000000 1984 1985 #define DMAE_SRC_PCI 0 1986 #define DMAE_SRC_GRC 1 1987 1988 #define DMAE_DST_NONE 0 1989 #define DMAE_DST_PCI 1 1990 #define DMAE_DST_GRC 2 1991 1992 #define DMAE_COMP_PCI 0 1993 #define DMAE_COMP_GRC 1 1994 1995 #define DMAE_COMP_REGULAR 0 1996 #define DMAE_COM_SET_ERR 1 1997 1998 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT) 1999 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT) 2000 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT) 2001 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT) 2002 2003 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT) 2004 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT) 2005 2006 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT) 2007 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT) 2008 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT) 2009 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT) 2010 2011 #define DMAE_CMD_PORT_0 0 2012 #define DMAE_CMD_PORT_1 DMAE_CMD_PORT 2013 2014 #define DMAE_SRC_PF 0 2015 #define DMAE_SRC_VF 1 2016 2017 #define DMAE_DST_PF 0 2018 #define DMAE_DST_VF 1 2019 2020 #define DMAE_C_SRC 0 2021 #define DMAE_C_DST 1 2022 2023 #define DMAE_LEN32_RD_MAX 0x80 2024 #define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) 2025 2026 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ 2027 2028 #define MAX_DMAE_C_PER_PORT 8 2029 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) 2030 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) 2031 2032 static const uint32_t dmae_reg_go_c[] = { 2033 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2034 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2035 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2036 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2037 }; 2038 2039 #define ATTN_NIG_FOR_FUNC (1L << 8) 2040 #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2041 #define GPIO_2_FUNC (1L << 10) 2042 #define GPIO_3_FUNC (1L << 11) 2043 #define GPIO_4_FUNC (1L << 12) 2044 #define ATTN_GENERAL_ATTN_1 (1L << 13) 2045 #define ATTN_GENERAL_ATTN_2 (1L << 14) 2046 #define ATTN_GENERAL_ATTN_3 (1L << 15) 2047 #define ATTN_GENERAL_ATTN_4 (1L << 13) 2048 #define ATTN_GENERAL_ATTN_5 (1L << 14) 2049 #define ATTN_GENERAL_ATTN_6 (1L << 15) 2050 #define ATTN_HARD_WIRED_MASK 0xff00 2051 #define ATTENTION_ID 4 2052 2053 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 2054 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 2055 2056 #define MAX_IGU_ATTN_ACK_TO 100 2057 2058 #define STORM_ASSERT_ARRAY_SIZE 50 2059 2060 #define BXE_PMF_LINK_ASSERT(sc) \ 2061 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) 2062 2063 #define BXE_MC_ASSERT_BITS \ 2064 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2065 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2066 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2067 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2068 2069 #define BXE_MCP_ASSERT \ 2070 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2071 2072 #define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2073 #define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2074 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2075 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2076 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2077 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2078 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2079 2080 #define MULTI_MASK 0x7f 2081 2082 #define PFS_PER_PORT(sc) \ 2083 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) 2084 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) 2085 2086 #define FIRST_ABS_FUNC_IN_PORT(sc) \ 2087 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ 2088 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) 2089 2090 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ 2091 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ 2092 (i) < MAX_FUNC_NUM; \ 2093 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) 2094 2095 #define BXE_SWCID_SHIFT 17 2096 #define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) 2097 2098 #define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) 2099 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 2100 2101 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 2102 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 2103 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 2104 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 2105 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 2106 2107 /* must be used on a CID before placing it on a HW ring */ 2108 #define HW_CID(sc, x) \ 2109 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) 2110 2111 #define SPEED_10 10 2112 #define SPEED_100 100 2113 #define SPEED_1000 1000 2114 #define SPEED_2500 2500 2115 #define SPEED_10000 10000 2116 2117 #define PCI_PM_D0 1 2118 #define PCI_PM_D3hot 2 2119 2120 #ifndef DUPLEX_UNKNOWN 2121 #define DUPLEX_UNKNOWN (0xff) 2122 #endif 2123 2124 #ifndef SPEED_UNKNOWN 2125 #define SPEED_UNKNOWN (-1) 2126 #endif 2127 2128 /* Enable or disable autonegotiation. */ 2129 #define AUTONEG_DISABLE 0x00 2130 #define AUTONEG_ENABLE 0x01 2131 2132 /* Which connector port. */ 2133 #define PORT_TP 0x00 2134 #define PORT_AUI 0x01 2135 #define PORT_MII 0x02 2136 #define PORT_FIBRE 0x03 2137 #define PORT_BNC 0x04 2138 #define PORT_DA 0x05 2139 #define PORT_NONE 0xef 2140 #define PORT_OTHER 0xff 2141 2142 int bxe_test_bit(int nr, volatile unsigned long * addr); 2143 void bxe_set_bit(unsigned int nr, volatile unsigned long * addr); 2144 void bxe_clear_bit(int nr, volatile unsigned long * addr); 2145 int bxe_test_and_set_bit(int nr, volatile unsigned long * addr); 2146 int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr); 2147 int bxe_cmpxchg(volatile int *addr, int old, int new); 2148 2149 void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, 2150 uint32_t val); 2151 uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr); 2152 2153 2154 int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, 2155 struct bxe_dma *dma, const char *msg); 2156 void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma); 2157 2158 uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); 2159 uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode); 2160 uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, 2161 uint8_t dst_type, uint8_t with_comp, 2162 uint8_t comp_type); 2163 void bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx); 2164 void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32); 2165 void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, 2166 uint32_t dst_addr, uint32_t len32); 2167 void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, 2168 uint32_t addr, uint32_t len); 2169 2170 void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, 2171 uint32_t cid); 2172 void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, 2173 uint8_t sb_index, uint8_t disable, 2174 uint16_t usec); 2175 2176 int bxe_sp_post(struct bxe_softc *sc, int command, int cid, 2177 uint32_t data_hi, uint32_t data_lo, int cmd_type); 2178 2179 void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, 2180 uint8_t segment, uint16_t index, uint8_t op, 2181 uint8_t update); 2182 2183 void ecore_init_e1_firmware(struct bxe_softc *sc); 2184 void ecore_init_e1h_firmware(struct bxe_softc *sc); 2185 void ecore_init_e2_firmware(struct bxe_softc *sc); 2186 2187 void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, 2188 size_t size, uint32_t *data); 2189 2190 /*********************/ 2191 /* LOGGING AND DEBUG */ 2192 /*********************/ 2193 2194 /* debug logging codepaths */ 2195 #define DBG_LOAD 0x00000001 /* load and unload */ 2196 #define DBG_INTR 0x00000002 /* interrupt handling */ 2197 #define DBG_SP 0x00000004 /* slowpath handling */ 2198 #define DBG_STATS 0x00000008 /* stats updates */ 2199 #define DBG_TX 0x00000010 /* packet transmit */ 2200 #define DBG_RX 0x00000020 /* packet receive */ 2201 #define DBG_PHY 0x00000040 /* phy/link handling */ 2202 #define DBG_IOCTL 0x00000080 /* ioctl handling */ 2203 #define DBG_MBUF 0x00000100 /* dumping mbuf info */ 2204 #define DBG_REGS 0x00000200 /* register access */ 2205 #define DBG_LRO 0x00000400 /* lro processing */ 2206 #define DBG_ASSERT 0x80000000 /* debug assert */ 2207 #define DBG_ALL 0xFFFFFFFF /* flying monkeys */ 2208 2209 #define DBASSERT(sc, exp, msg) \ 2210 do { \ 2211 if (__predict_false(sc->debug & DBG_ASSERT)) { \ 2212 if (__predict_false(!(exp))) { \ 2213 panic msg; \ 2214 } \ 2215 } \ 2216 } while (0) 2217 2218 /* log a debug message */ 2219 #define BLOGD(sc, codepath, format, args...) \ 2220 do { \ 2221 if (__predict_false(sc->debug & (codepath))) { \ 2222 device_printf((sc)->dev, \ 2223 "%s(%s:%d) " format, \ 2224 __FUNCTION__, \ 2225 __FILE__, \ 2226 __LINE__, \ 2227 ## args); \ 2228 } \ 2229 } while(0) 2230 2231 /* log a info message */ 2232 #define BLOGI(sc, format, args...) \ 2233 do { \ 2234 if (__predict_false(sc->debug)) { \ 2235 device_printf((sc)->dev, \ 2236 "%s(%s:%d) " format, \ 2237 __FUNCTION__, \ 2238 __FILE__, \ 2239 __LINE__, \ 2240 ## args); \ 2241 } else { \ 2242 device_printf((sc)->dev, \ 2243 format, \ 2244 ## args); \ 2245 } \ 2246 } while(0) 2247 2248 /* log a warning message */ 2249 #define BLOGW(sc, format, args...) \ 2250 do { \ 2251 if (__predict_false(sc->debug)) { \ 2252 device_printf((sc)->dev, \ 2253 "%s(%s:%d) WARNING: " format, \ 2254 __FUNCTION__, \ 2255 __FILE__, \ 2256 __LINE__, \ 2257 ## args); \ 2258 } else { \ 2259 device_printf((sc)->dev, \ 2260 "WARNING: " format, \ 2261 ## args); \ 2262 } \ 2263 } while(0) 2264 2265 /* log a error message */ 2266 #define BLOGE(sc, format, args...) \ 2267 do { \ 2268 if (__predict_false(sc->debug)) { \ 2269 device_printf((sc)->dev, \ 2270 "%s(%s:%d) ERROR: " format, \ 2271 __FUNCTION__, \ 2272 __FILE__, \ 2273 __LINE__, \ 2274 ## args); \ 2275 } else { \ 2276 device_printf((sc)->dev, \ 2277 "ERROR: " format, \ 2278 ## args); \ 2279 } \ 2280 } while(0) 2281 2282 #ifdef ECORE_STOP_ON_ERROR 2283 2284 #define bxe_panic(sc, msg) \ 2285 do { \ 2286 panic msg; \ 2287 } while (0) 2288 2289 #else 2290 2291 #define bxe_panic(sc, msg) \ 2292 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 2293 2294 #endif 2295 2296 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); 2297 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) 2298 2299 void bxe_dump_mem(struct bxe_softc *sc, char *tag, 2300 uint8_t *mem, uint32_t len); 2301 void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, 2302 struct mbuf *m, uint8_t contents); 2303 extern int bxe_grc_dump(struct bxe_softc *sc); 2304 2305 #if __FreeBSD_version >= 800000 2306 #if (__FreeBSD_version >= 1001513 && __FreeBSD_version < 1100000) ||\ 2307 __FreeBSD_version >= 1100048 2308 #define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE) 2309 #define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2310 #else 2311 #define BXE_VALID_FLOWID(m) ((m->m_flags & M_FLOWID) != 0) 2312 #define BXE_SET_FLOWID(m) m->m_flags |= M_FLOWID 2313 #endif 2314 #endif /* #if __FreeBSD_version >= 800000 */ 2315 2316 /***********/ 2317 /* INLINES */ 2318 /***********/ 2319 2320 static inline uint32_t 2321 reg_poll(struct bxe_softc *sc, 2322 uint32_t reg, 2323 uint32_t expected, 2324 int ms, 2325 int wait) 2326 { 2327 uint32_t val; 2328 2329 do { 2330 val = REG_RD(sc, reg); 2331 if (val == expected) { 2332 break; 2333 } 2334 ms -= wait; 2335 DELAY(wait * 1000); 2336 } while (ms > 0); 2337 2338 return (val); 2339 } 2340 2341 static inline void 2342 bxe_update_fp_sb_idx(struct bxe_fastpath *fp) 2343 { 2344 mb(); /* status block is written to by the chip */ 2345 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 2346 } 2347 2348 static inline void 2349 bxe_igu_ack_sb_gen(struct bxe_softc *sc, 2350 uint8_t igu_sb_id, 2351 uint8_t segment, 2352 uint16_t index, 2353 uint8_t op, 2354 uint8_t update, 2355 uint32_t igu_addr) 2356 { 2357 struct igu_regular cmd_data = {0}; 2358 2359 cmd_data.sb_id_and_flags = 2360 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 2361 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 2362 (update << IGU_REGULAR_BUPDATE_SHIFT) | 2363 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 2364 2365 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2366 cmd_data.sb_id_and_flags, igu_addr); 2367 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); 2368 2369 /* Make sure that ACK is written */ 2370 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2371 BUS_SPACE_BARRIER_WRITE); 2372 mb(); 2373 } 2374 2375 static inline void 2376 bxe_hc_ack_sb(struct bxe_softc *sc, 2377 uint8_t sb_id, 2378 uint8_t storm, 2379 uint16_t index, 2380 uint8_t op, 2381 uint8_t update) 2382 { 2383 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2384 COMMAND_REG_INT_ACK); 2385 struct igu_ack_register igu_ack; 2386 2387 igu_ack.status_block_index = index; 2388 igu_ack.sb_id_and_flags = 2389 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 2390 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 2391 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 2392 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 2393 2394 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack)); 2395 2396 /* Make sure that ACK is written */ 2397 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2398 BUS_SPACE_BARRIER_WRITE); 2399 mb(); 2400 } 2401 2402 static inline void 2403 bxe_ack_sb(struct bxe_softc *sc, 2404 uint8_t igu_sb_id, 2405 uint8_t storm, 2406 uint16_t index, 2407 uint8_t op, 2408 uint8_t update) 2409 { 2410 if (sc->devinfo.int_block == INT_BLOCK_HC) 2411 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update); 2412 else { 2413 uint8_t segment; 2414 if (CHIP_INT_MODE_IS_BC(sc)) { 2415 segment = storm; 2416 } else if (igu_sb_id != sc->igu_dsb_id) { 2417 segment = IGU_SEG_ACCESS_DEF; 2418 } else if (storm == ATTENTION_ID) { 2419 segment = IGU_SEG_ACCESS_ATTN; 2420 } else { 2421 segment = IGU_SEG_ACCESS_DEF; 2422 } 2423 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update); 2424 } 2425 } 2426 2427 static inline uint16_t 2428 bxe_hc_ack_int(struct bxe_softc *sc) 2429 { 2430 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2431 COMMAND_REG_SIMD_MASK); 2432 uint32_t result = REG_RD(sc, hc_addr); 2433 2434 mb(); 2435 return (result); 2436 } 2437 2438 static inline uint16_t 2439 bxe_igu_ack_int(struct bxe_softc *sc) 2440 { 2441 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 2442 uint32_t result = REG_RD(sc, igu_addr); 2443 2444 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n", 2445 result, igu_addr); 2446 2447 mb(); 2448 return (result); 2449 } 2450 2451 static inline uint16_t 2452 bxe_ack_int(struct bxe_softc *sc) 2453 { 2454 mb(); 2455 if (sc->devinfo.int_block == INT_BLOCK_HC) { 2456 return (bxe_hc_ack_int(sc)); 2457 } else { 2458 return (bxe_igu_ack_int(sc)); 2459 } 2460 } 2461 2462 static inline int 2463 func_by_vn(struct bxe_softc *sc, 2464 int vn) 2465 { 2466 return (2 * vn + SC_PORT(sc)); 2467 } 2468 2469 /* 2470 * Statistics ID are global per chip/path, while Client IDs for E1x 2471 * are per port. 2472 */ 2473 static inline uint8_t 2474 bxe_stats_id(struct bxe_fastpath *fp) 2475 { 2476 struct bxe_softc *sc = fp->sc; 2477 2478 if (!CHIP_IS_E1x(sc)) { 2479 return (fp->cl_id); 2480 } 2481 2482 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x); 2483 } 2484 2485 #endif /* __BXE_H__ */ 2486 2487