1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 */ 5 6 /* 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/sockio.h> 36 #include <sys/mbuf.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/socket.h> 41 #include <sys/queue.h> 42 43 #include <net/if.h> 44 #include <net/if_arp.h> 45 #include <net/ethernet.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <net/bpf.h> 50 51 #include <net/if_types.h> 52 #include <net/if_vlan_var.h> 53 54 #include <netinet/in_systm.h> 55 #include <netinet/in.h> 56 #include <netinet/ip.h> 57 58 #include <machine/clock.h> /* for DELAY */ 59 #include <machine/bus_memio.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 #include "miidevs.h" 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <dev/bfe/if_bfereg.h> 73 74 MODULE_DEPEND(bfe, pci, 1, 1, 1); 75 MODULE_DEPEND(bfe, ether, 1, 1, 1); 76 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 77 78 /* "controller miibus0" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 81 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 82 83 static struct bfe_type bfe_devs[] = { 84 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 85 "Broadcom BCM4401 Fast Ethernet" }, 86 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 87 "Broadcom BCM4401-B0 Fast Ethernet" }, 88 { 0, 0, NULL } 89 }; 90 91 static int bfe_probe (device_t); 92 static int bfe_attach (device_t); 93 static int bfe_detach (device_t); 94 static void bfe_release_resources (struct bfe_softc *); 95 static void bfe_intr (void *); 96 static void bfe_start (struct ifnet *); 97 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 98 static void bfe_init (void *); 99 static void bfe_stop (struct bfe_softc *); 100 static void bfe_watchdog (struct ifnet *); 101 static void bfe_shutdown (device_t); 102 static void bfe_tick (void *); 103 static void bfe_txeof (struct bfe_softc *); 104 static void bfe_rxeof (struct bfe_softc *); 105 static void bfe_set_rx_mode (struct bfe_softc *); 106 static int bfe_list_rx_init (struct bfe_softc *); 107 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 108 static void bfe_rx_ring_free (struct bfe_softc *); 109 110 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 111 static int bfe_ifmedia_upd (struct ifnet *); 112 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 113 static int bfe_miibus_readreg (device_t, int, int); 114 static int bfe_miibus_writereg (device_t, int, int, int); 115 static void bfe_miibus_statchg (device_t); 116 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 117 u_long, const int); 118 static void bfe_get_config (struct bfe_softc *sc); 119 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 120 static void bfe_stats_update (struct bfe_softc *); 121 static void bfe_clear_stats (struct bfe_softc *); 122 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 123 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 124 static int bfe_resetphy (struct bfe_softc *); 125 static int bfe_setupphy (struct bfe_softc *); 126 static void bfe_chip_reset (struct bfe_softc *); 127 static void bfe_chip_halt (struct bfe_softc *); 128 static void bfe_core_reset (struct bfe_softc *); 129 static void bfe_core_disable (struct bfe_softc *); 130 static int bfe_dma_alloc (device_t); 131 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 132 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 133 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 134 135 static device_method_t bfe_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, bfe_probe), 138 DEVMETHOD(device_attach, bfe_attach), 139 DEVMETHOD(device_detach, bfe_detach), 140 DEVMETHOD(device_shutdown, bfe_shutdown), 141 142 /* bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 145 146 /* MII interface */ 147 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 148 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 149 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 150 151 { 0, 0 } 152 }; 153 154 static driver_t bfe_driver = { 155 "bfe", 156 bfe_methods, 157 sizeof(struct bfe_softc) 158 }; 159 160 static devclass_t bfe_devclass; 161 162 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 163 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 164 165 /* 166 * Probe for a Broadcom 4401 chip. 167 */ 168 static int 169 bfe_probe(device_t dev) 170 { 171 struct bfe_type *t; 172 struct bfe_softc *sc; 173 174 t = bfe_devs; 175 176 sc = device_get_softc(dev); 177 bzero(sc, sizeof(struct bfe_softc)); 178 sc->bfe_unit = device_get_unit(dev); 179 sc->bfe_dev = dev; 180 181 while(t->bfe_name != NULL) { 182 if ((pci_get_vendor(dev) == t->bfe_vid) && 183 (pci_get_device(dev) == t->bfe_did)) { 184 device_set_desc_copy(dev, t->bfe_name); 185 return (0); 186 } 187 t++; 188 } 189 190 return (ENXIO); 191 } 192 193 static int 194 bfe_dma_alloc(device_t dev) 195 { 196 struct bfe_softc *sc; 197 int error, i; 198 199 sc = device_get_softc(dev); 200 201 /* parent tag */ 202 error = bus_dma_tag_create(NULL, /* parent */ 203 PAGE_SIZE, 0, /* alignment, boundary */ 204 BUS_SPACE_MAXADDR, /* lowaddr */ 205 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 206 NULL, NULL, /* filter, filterarg */ 207 MAXBSIZE, /* maxsize */ 208 BUS_SPACE_UNRESTRICTED, /* num of segments */ 209 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 210 BUS_DMA_ALLOCNOW, /* flags */ 211 NULL, NULL, /* lockfunc, lockarg */ 212 &sc->bfe_parent_tag); 213 214 /* tag for TX ring */ 215 error = bus_dma_tag_create(sc->bfe_parent_tag, 216 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 217 BUS_SPACE_MAXADDR, 218 BUS_SPACE_MAXADDR, 219 NULL, NULL, 220 BFE_TX_LIST_SIZE, 221 1, 222 BUS_SPACE_MAXSIZE_32BIT, 223 0, 224 NULL, NULL, 225 &sc->bfe_tx_tag); 226 227 if (error) { 228 device_printf(dev, "could not allocate dma tag\n"); 229 return (ENOMEM); 230 } 231 232 /* tag for RX ring */ 233 error = bus_dma_tag_create(sc->bfe_parent_tag, 234 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 235 BUS_SPACE_MAXADDR, 236 BUS_SPACE_MAXADDR, 237 NULL, NULL, 238 BFE_RX_LIST_SIZE, 239 1, 240 BUS_SPACE_MAXSIZE_32BIT, 241 0, 242 NULL, NULL, 243 &sc->bfe_rx_tag); 244 245 if (error) { 246 device_printf(dev, "could not allocate dma tag\n"); 247 return (ENOMEM); 248 } 249 250 /* tag for mbufs */ 251 error = bus_dma_tag_create(sc->bfe_parent_tag, 252 ETHER_ALIGN, 0, 253 BUS_SPACE_MAXADDR, 254 BUS_SPACE_MAXADDR, 255 NULL, NULL, 256 MCLBYTES, 257 1, 258 BUS_SPACE_MAXSIZE_32BIT, 259 0, 260 NULL, NULL, 261 &sc->bfe_tag); 262 263 if (error) { 264 device_printf(dev, "could not allocate dma tag\n"); 265 return (ENOMEM); 266 } 267 268 /* pre allocate dmamaps for RX list */ 269 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 270 error = bus_dmamap_create(sc->bfe_tag, 0, 271 &sc->bfe_rx_ring[i].bfe_map); 272 if (error) { 273 device_printf(dev, "cannot create DMA map for RX\n"); 274 return (ENOMEM); 275 } 276 } 277 278 /* pre allocate dmamaps for TX list */ 279 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 280 error = bus_dmamap_create(sc->bfe_tag, 0, 281 &sc->bfe_tx_ring[i].bfe_map); 282 if (error) { 283 device_printf(dev, "cannot create DMA map for TX\n"); 284 return (ENOMEM); 285 } 286 } 287 288 /* Alloc dma for rx ring */ 289 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 290 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 291 292 if(error) 293 return (ENOMEM); 294 295 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 296 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 297 sc->bfe_rx_list, sizeof(struct bfe_desc), 298 bfe_dma_map, &sc->bfe_rx_dma, 0); 299 300 if(error) 301 return (ENOMEM); 302 303 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 304 305 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 306 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 307 if (error) 308 return (ENOMEM); 309 310 311 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 312 sc->bfe_tx_list, sizeof(struct bfe_desc), 313 bfe_dma_map, &sc->bfe_tx_dma, 0); 314 if(error) 315 return (ENOMEM); 316 317 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 318 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 319 320 return (0); 321 } 322 323 static int 324 bfe_attach(device_t dev) 325 { 326 struct ifnet *ifp; 327 struct bfe_softc *sc; 328 int unit, error = 0, rid; 329 330 sc = device_get_softc(dev); 331 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 332 MTX_DEF | MTX_RECURSE); 333 334 unit = device_get_unit(dev); 335 sc->bfe_dev = dev; 336 sc->bfe_unit = unit; 337 338 /* 339 * Handle power management nonsense. 340 */ 341 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 342 u_int32_t membase, irq; 343 344 /* Save important PCI config data. */ 345 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 346 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 347 348 /* Reset the power state. */ 349 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 350 sc->bfe_unit, pci_get_powerstate(dev)); 351 352 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 353 354 /* Restore PCI config data. */ 355 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 356 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 357 } 358 359 /* 360 * Map control/status registers. 361 */ 362 pci_enable_busmaster(dev); 363 364 rid = BFE_PCI_MEMLO; 365 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 366 RF_ACTIVE); 367 if (sc->bfe_res == NULL) { 368 printf ("bfe%d: couldn't map memory\n", unit); 369 error = ENXIO; 370 goto fail; 371 } 372 373 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 374 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 375 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 376 377 /* Allocate interrupt */ 378 rid = 0; 379 380 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 381 RF_SHAREABLE | RF_ACTIVE); 382 if (sc->bfe_irq == NULL) { 383 printf("bfe%d: couldn't map interrupt\n", unit); 384 error = ENXIO; 385 goto fail; 386 } 387 388 if (bfe_dma_alloc(dev)) { 389 printf("bfe%d: failed to allocate DMA resources\n", 390 sc->bfe_unit); 391 bfe_release_resources(sc); 392 error = ENXIO; 393 goto fail; 394 } 395 396 /* Set up ifnet structure */ 397 ifp = &sc->arpcom.ac_if; 398 ifp->if_softc = sc; 399 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 400 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 401 ifp->if_ioctl = bfe_ioctl; 402 ifp->if_start = bfe_start; 403 ifp->if_watchdog = bfe_watchdog; 404 ifp->if_init = bfe_init; 405 ifp->if_mtu = ETHERMTU; 406 ifp->if_baudrate = 100000000; 407 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 408 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 409 IFQ_SET_READY(&ifp->if_snd); 410 411 bfe_get_config(sc); 412 413 /* Reset the chip and turn on the PHY */ 414 bfe_chip_reset(sc); 415 416 if (mii_phy_probe(dev, &sc->bfe_miibus, 417 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 418 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 419 error = ENXIO; 420 goto fail; 421 } 422 423 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 424 callout_handle_init(&sc->bfe_stat_ch); 425 426 /* 427 * Tell the upper layer(s) we support long frames. 428 */ 429 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 430 ifp->if_capabilities |= IFCAP_VLAN_MTU; 431 ifp->if_capenable |= IFCAP_VLAN_MTU; 432 433 /* 434 * Hook interrupt last to avoid having to lock softc 435 */ 436 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 437 bfe_intr, sc, &sc->bfe_intrhand); 438 439 if (error) { 440 bfe_release_resources(sc); 441 printf("bfe%d: couldn't set up irq\n", unit); 442 goto fail; 443 } 444 fail: 445 if(error) 446 bfe_release_resources(sc); 447 return (error); 448 } 449 450 static int 451 bfe_detach(device_t dev) 452 { 453 struct bfe_softc *sc; 454 struct ifnet *ifp; 455 456 sc = device_get_softc(dev); 457 458 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 459 BFE_LOCK(scp); 460 461 ifp = &sc->arpcom.ac_if; 462 463 if (device_is_attached(dev)) { 464 bfe_stop(sc); 465 ether_ifdetach(ifp); 466 } 467 468 bfe_chip_reset(sc); 469 470 bus_generic_detach(dev); 471 if(sc->bfe_miibus != NULL) 472 device_delete_child(dev, sc->bfe_miibus); 473 474 bfe_release_resources(sc); 475 BFE_UNLOCK(sc); 476 mtx_destroy(&sc->bfe_mtx); 477 478 return (0); 479 } 480 481 /* 482 * Stop all chip I/O so that the kernel's probe routines don't 483 * get confused by errant DMAs when rebooting. 484 */ 485 static void 486 bfe_shutdown(device_t dev) 487 { 488 struct bfe_softc *sc; 489 490 sc = device_get_softc(dev); 491 BFE_LOCK(sc); 492 bfe_stop(sc); 493 494 BFE_UNLOCK(sc); 495 return; 496 } 497 498 static int 499 bfe_miibus_readreg(device_t dev, int phy, int reg) 500 { 501 struct bfe_softc *sc; 502 u_int32_t ret; 503 504 sc = device_get_softc(dev); 505 if(phy != sc->bfe_phyaddr) 506 return (0); 507 bfe_readphy(sc, reg, &ret); 508 509 return (ret); 510 } 511 512 static int 513 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 514 { 515 struct bfe_softc *sc; 516 517 sc = device_get_softc(dev); 518 if(phy != sc->bfe_phyaddr) 519 return (0); 520 bfe_writephy(sc, reg, val); 521 522 return (0); 523 } 524 525 static void 526 bfe_miibus_statchg(device_t dev) 527 { 528 return; 529 } 530 531 static void 532 bfe_tx_ring_free(struct bfe_softc *sc) 533 { 534 int i; 535 536 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 537 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 538 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 539 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 540 bus_dmamap_unload(sc->bfe_tag, 541 sc->bfe_tx_ring[i].bfe_map); 542 bus_dmamap_destroy(sc->bfe_tag, 543 sc->bfe_tx_ring[i].bfe_map); 544 } 545 } 546 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 547 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 548 } 549 550 static void 551 bfe_rx_ring_free(struct bfe_softc *sc) 552 { 553 int i; 554 555 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 556 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 557 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 558 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 559 bus_dmamap_unload(sc->bfe_tag, 560 sc->bfe_rx_ring[i].bfe_map); 561 bus_dmamap_destroy(sc->bfe_tag, 562 sc->bfe_rx_ring[i].bfe_map); 563 } 564 } 565 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 566 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 567 } 568 569 570 static int 571 bfe_list_rx_init(struct bfe_softc *sc) 572 { 573 int i; 574 575 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 576 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 577 return (ENOBUFS); 578 } 579 580 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 581 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 582 583 sc->bfe_rx_cons = 0; 584 585 return (0); 586 } 587 588 static int 589 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 590 { 591 struct bfe_rxheader *rx_header; 592 struct bfe_desc *d; 593 struct bfe_data *r; 594 u_int32_t ctrl; 595 596 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 597 return (EINVAL); 598 599 if(m == NULL) { 600 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 601 if(m == NULL) 602 return (ENOBUFS); 603 m->m_len = m->m_pkthdr.len = MCLBYTES; 604 } 605 else 606 m->m_data = m->m_ext.ext_buf; 607 608 rx_header = mtod(m, struct bfe_rxheader *); 609 rx_header->len = 0; 610 rx_header->flags = 0; 611 612 /* Map the mbuf into DMA */ 613 sc->bfe_rx_cnt = c; 614 d = &sc->bfe_rx_list[c]; 615 r = &sc->bfe_rx_ring[c]; 616 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 617 MCLBYTES, bfe_dma_map_desc, d, 0); 618 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 619 620 ctrl = ETHER_MAX_LEN + 32; 621 622 if(c == BFE_RX_LIST_CNT - 1) 623 ctrl |= BFE_DESC_EOT; 624 625 d->bfe_ctrl = ctrl; 626 r->bfe_mbuf = m; 627 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 628 return (0); 629 } 630 631 static void 632 bfe_get_config(struct bfe_softc *sc) 633 { 634 u_int8_t eeprom[128]; 635 636 bfe_read_eeprom(sc, eeprom); 637 638 sc->arpcom.ac_enaddr[0] = eeprom[79]; 639 sc->arpcom.ac_enaddr[1] = eeprom[78]; 640 sc->arpcom.ac_enaddr[2] = eeprom[81]; 641 sc->arpcom.ac_enaddr[3] = eeprom[80]; 642 sc->arpcom.ac_enaddr[4] = eeprom[83]; 643 sc->arpcom.ac_enaddr[5] = eeprom[82]; 644 645 sc->bfe_phyaddr = eeprom[90] & 0x1f; 646 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 647 648 sc->bfe_core_unit = 0; 649 sc->bfe_dma_offset = BFE_PCI_DMA; 650 } 651 652 static void 653 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 654 { 655 u_int32_t bar_orig, pci_rev, val; 656 657 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 658 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 659 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 660 661 val = CSR_READ_4(sc, BFE_SBINTVEC); 662 val |= cores; 663 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 664 665 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 666 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 667 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 668 669 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 670 } 671 672 static void 673 bfe_clear_stats(struct bfe_softc *sc) 674 { 675 u_long reg; 676 677 BFE_LOCK(sc); 678 679 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 680 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 681 CSR_READ_4(sc, reg); 682 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 683 CSR_READ_4(sc, reg); 684 685 BFE_UNLOCK(sc); 686 } 687 688 static int 689 bfe_resetphy(struct bfe_softc *sc) 690 { 691 u_int32_t val; 692 693 BFE_LOCK(sc); 694 bfe_writephy(sc, 0, BMCR_RESET); 695 DELAY(100); 696 bfe_readphy(sc, 0, &val); 697 if (val & BMCR_RESET) { 698 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 699 BFE_UNLOCK(sc); 700 return (ENXIO); 701 } 702 BFE_UNLOCK(sc); 703 return (0); 704 } 705 706 static void 707 bfe_chip_halt(struct bfe_softc *sc) 708 { 709 BFE_LOCK(sc); 710 /* disable interrupts - not that it actually does..*/ 711 CSR_WRITE_4(sc, BFE_IMASK, 0); 712 CSR_READ_4(sc, BFE_IMASK); 713 714 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 715 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 716 717 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 718 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 719 DELAY(10); 720 721 BFE_UNLOCK(sc); 722 } 723 724 static void 725 bfe_chip_reset(struct bfe_softc *sc) 726 { 727 u_int32_t val; 728 729 BFE_LOCK(sc); 730 731 /* Set the interrupt vector for the enet core */ 732 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 733 734 /* is core up? */ 735 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 736 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 737 if (val == BFE_CLOCK) { 738 /* It is, so shut it down */ 739 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 740 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 741 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 742 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 743 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 744 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 745 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 746 100, 0); 747 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 748 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 749 } 750 751 bfe_core_reset(sc); 752 bfe_clear_stats(sc); 753 754 /* 755 * We want the phy registers to be accessible even when 756 * the driver is "downed" so initialize MDC preamble, frequency, 757 * and whether internal or external phy here. 758 */ 759 760 /* 4402 has 62.5Mhz SB clock and internal phy */ 761 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 762 763 /* Internal or external PHY? */ 764 val = CSR_READ_4(sc, BFE_DEVCTRL); 765 if(!(val & BFE_IPP)) 766 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 767 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 768 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 769 DELAY(100); 770 } 771 772 /* Enable CRC32 generation and set proper LED modes */ 773 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 774 775 /* Reset or clear powerdown control bit */ 776 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 777 778 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 779 BFE_LAZY_FC_MASK)); 780 781 /* 782 * We don't want lazy interrupts, so just send them at 783 * the end of a frame, please 784 */ 785 BFE_OR(sc, BFE_RCV_LAZY, 0); 786 787 /* Set max lengths, accounting for VLAN tags */ 788 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 789 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 790 791 /* Set watermark XXX - magic */ 792 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 793 794 /* 795 * Initialise DMA channels 796 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 797 */ 798 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 799 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 800 801 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 802 BFE_RX_CTRL_ENABLE); 803 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 804 805 bfe_resetphy(sc); 806 bfe_setupphy(sc); 807 808 BFE_UNLOCK(sc); 809 } 810 811 static void 812 bfe_core_disable(struct bfe_softc *sc) 813 { 814 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 815 return; 816 817 /* 818 * Set reject, wait for it set, then wait for the core to stop 819 * being busy, then set reset and reject and enable the clocks. 820 */ 821 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 822 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 823 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 824 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 825 BFE_RESET)); 826 CSR_READ_4(sc, BFE_SBTMSLOW); 827 DELAY(10); 828 /* Leave reset and reject set */ 829 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 830 DELAY(10); 831 } 832 833 static void 834 bfe_core_reset(struct bfe_softc *sc) 835 { 836 u_int32_t val; 837 838 /* Disable the core */ 839 bfe_core_disable(sc); 840 841 /* and bring it back up */ 842 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 843 CSR_READ_4(sc, BFE_SBTMSLOW); 844 DELAY(10); 845 846 /* Chip bug, clear SERR, IB and TO if they are set. */ 847 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 848 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 849 val = CSR_READ_4(sc, BFE_SBIMSTATE); 850 if (val & (BFE_IBE | BFE_TO)) 851 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 852 853 /* Clear reset and allow it to move through the core */ 854 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 855 CSR_READ_4(sc, BFE_SBTMSLOW); 856 DELAY(10); 857 858 /* Leave the clock set */ 859 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 860 CSR_READ_4(sc, BFE_SBTMSLOW); 861 DELAY(10); 862 } 863 864 static void 865 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 866 { 867 u_int32_t val; 868 869 val = ((u_int32_t) data[2]) << 24; 870 val |= ((u_int32_t) data[3]) << 16; 871 val |= ((u_int32_t) data[4]) << 8; 872 val |= ((u_int32_t) data[5]); 873 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 874 val = (BFE_CAM_HI_VALID | 875 (((u_int32_t) data[0]) << 8) | 876 (((u_int32_t) data[1]))); 877 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 878 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 879 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 880 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 881 } 882 883 static void 884 bfe_set_rx_mode(struct bfe_softc *sc) 885 { 886 struct ifnet *ifp = &sc->arpcom.ac_if; 887 struct ifmultiaddr *ifma; 888 u_int32_t val; 889 int i = 0; 890 891 val = CSR_READ_4(sc, BFE_RXCONF); 892 893 if (ifp->if_flags & IFF_PROMISC) 894 val |= BFE_RXCONF_PROMISC; 895 else 896 val &= ~BFE_RXCONF_PROMISC; 897 898 if (ifp->if_flags & IFF_BROADCAST) 899 val &= ~BFE_RXCONF_DBCAST; 900 else 901 val |= BFE_RXCONF_DBCAST; 902 903 904 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 905 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 906 907 if (ifp->if_flags & IFF_ALLMULTI) 908 val |= BFE_RXCONF_ALLMULTI; 909 else { 910 val &= ~BFE_RXCONF_ALLMULTI; 911 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 912 if (ifma->ifma_addr->sa_family != AF_LINK) 913 continue; 914 bfe_cam_write(sc, 915 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 916 } 917 } 918 919 CSR_WRITE_4(sc, BFE_RXCONF, val); 920 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 921 } 922 923 static void 924 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 925 { 926 u_int32_t *ptr; 927 928 ptr = arg; 929 *ptr = segs->ds_addr; 930 } 931 932 static void 933 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 934 { 935 struct bfe_desc *d; 936 937 d = arg; 938 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 939 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 940 } 941 942 static void 943 bfe_release_resources(struct bfe_softc *sc) 944 { 945 device_t dev; 946 int i; 947 948 dev = sc->bfe_dev; 949 950 if (sc->bfe_vpd_prodname != NULL) 951 free(sc->bfe_vpd_prodname, M_DEVBUF); 952 953 if (sc->bfe_vpd_readonly != NULL) 954 free(sc->bfe_vpd_readonly, M_DEVBUF); 955 956 if (sc->bfe_intrhand != NULL) 957 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 958 959 if (sc->bfe_irq != NULL) 960 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 961 962 if (sc->bfe_res != NULL) 963 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 964 965 if(sc->bfe_tx_tag != NULL) { 966 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 967 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 968 sc->bfe_tx_map); 969 bus_dma_tag_destroy(sc->bfe_tx_tag); 970 sc->bfe_tx_tag = NULL; 971 } 972 973 if(sc->bfe_rx_tag != NULL) { 974 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 975 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 976 sc->bfe_rx_map); 977 bus_dma_tag_destroy(sc->bfe_rx_tag); 978 sc->bfe_rx_tag = NULL; 979 } 980 981 if(sc->bfe_tag != NULL) { 982 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 983 bus_dmamap_destroy(sc->bfe_tag, 984 sc->bfe_tx_ring[i].bfe_map); 985 } 986 bus_dma_tag_destroy(sc->bfe_tag); 987 sc->bfe_tag = NULL; 988 } 989 990 if(sc->bfe_parent_tag != NULL) 991 bus_dma_tag_destroy(sc->bfe_parent_tag); 992 993 return; 994 } 995 996 static void 997 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 998 { 999 long i; 1000 u_int16_t *ptr = (u_int16_t *)data; 1001 1002 for(i = 0; i < 128; i += 2) 1003 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1004 } 1005 1006 static int 1007 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1008 u_long timeout, const int clear) 1009 { 1010 u_long i; 1011 1012 for (i = 0; i < timeout; i++) { 1013 u_int32_t val = CSR_READ_4(sc, reg); 1014 1015 if (clear && !(val & bit)) 1016 break; 1017 if (!clear && (val & bit)) 1018 break; 1019 DELAY(10); 1020 } 1021 if (i == timeout) { 1022 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1023 "%x to %s.\n", sc->bfe_unit, bit, reg, 1024 (clear ? "clear" : "set")); 1025 return (-1); 1026 } 1027 return (0); 1028 } 1029 1030 static int 1031 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1032 { 1033 int err; 1034 1035 BFE_LOCK(sc); 1036 /* Clear MII ISR */ 1037 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1038 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1039 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1040 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1041 (reg << BFE_MDIO_RA_SHIFT) | 1042 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1043 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1044 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1045 1046 BFE_UNLOCK(sc); 1047 return (err); 1048 } 1049 1050 static int 1051 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1052 { 1053 int status; 1054 1055 BFE_LOCK(sc); 1056 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1057 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1058 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1059 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1060 (reg << BFE_MDIO_RA_SHIFT) | 1061 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1062 (val & BFE_MDIO_DATA_DATA))); 1063 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1064 BFE_UNLOCK(sc); 1065 1066 return (status); 1067 } 1068 1069 /* 1070 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1071 * twice 1072 */ 1073 static int 1074 bfe_setupphy(struct bfe_softc *sc) 1075 { 1076 u_int32_t val; 1077 BFE_LOCK(sc); 1078 1079 /* Enable activity LED */ 1080 bfe_readphy(sc, 26, &val); 1081 bfe_writephy(sc, 26, val & 0x7fff); 1082 bfe_readphy(sc, 26, &val); 1083 1084 /* Enable traffic meter LED mode */ 1085 bfe_readphy(sc, 27, &val); 1086 bfe_writephy(sc, 27, val | (1 << 6)); 1087 1088 BFE_UNLOCK(sc); 1089 return (0); 1090 } 1091 1092 static void 1093 bfe_stats_update(struct bfe_softc *sc) 1094 { 1095 u_long reg; 1096 u_int32_t *val; 1097 1098 val = &sc->bfe_hwstats.tx_good_octets; 1099 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1100 *val++ += CSR_READ_4(sc, reg); 1101 } 1102 val = &sc->bfe_hwstats.rx_good_octets; 1103 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1104 *val++ += CSR_READ_4(sc, reg); 1105 } 1106 } 1107 1108 static void 1109 bfe_txeof(struct bfe_softc *sc) 1110 { 1111 struct ifnet *ifp; 1112 int i, chipidx; 1113 1114 BFE_LOCK(sc); 1115 1116 ifp = &sc->arpcom.ac_if; 1117 1118 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1119 chipidx /= sizeof(struct bfe_desc); 1120 1121 i = sc->bfe_tx_cons; 1122 /* Go through the mbufs and free those that have been transmitted */ 1123 while(i != chipidx) { 1124 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1125 if(r->bfe_mbuf != NULL) { 1126 ifp->if_opackets++; 1127 m_freem(r->bfe_mbuf); 1128 r->bfe_mbuf = NULL; 1129 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1130 } 1131 sc->bfe_tx_cnt--; 1132 BFE_INC(i, BFE_TX_LIST_CNT); 1133 } 1134 1135 if(i != sc->bfe_tx_cons) { 1136 /* we freed up some mbufs */ 1137 sc->bfe_tx_cons = i; 1138 ifp->if_flags &= ~IFF_OACTIVE; 1139 } 1140 if(sc->bfe_tx_cnt == 0) 1141 ifp->if_timer = 0; 1142 else 1143 ifp->if_timer = 5; 1144 1145 BFE_UNLOCK(sc); 1146 } 1147 1148 /* Pass a received packet up the stack */ 1149 static void 1150 bfe_rxeof(struct bfe_softc *sc) 1151 { 1152 struct mbuf *m; 1153 struct ifnet *ifp; 1154 struct bfe_rxheader *rxheader; 1155 struct bfe_data *r; 1156 int cons; 1157 u_int32_t status, current, len, flags; 1158 1159 BFE_LOCK(sc); 1160 cons = sc->bfe_rx_cons; 1161 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1162 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1163 1164 ifp = &sc->arpcom.ac_if; 1165 1166 while(current != cons) { 1167 r = &sc->bfe_rx_ring[cons]; 1168 m = r->bfe_mbuf; 1169 rxheader = mtod(m, struct bfe_rxheader*); 1170 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1171 len = rxheader->len; 1172 r->bfe_mbuf = NULL; 1173 1174 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1175 flags = rxheader->flags; 1176 1177 len -= ETHER_CRC_LEN; 1178 1179 /* flag an error and try again */ 1180 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1181 ifp->if_ierrors++; 1182 if (flags & BFE_RX_FLAG_SERR) 1183 ifp->if_collisions++; 1184 bfe_list_newbuf(sc, cons, m); 1185 BFE_INC(cons, BFE_RX_LIST_CNT); 1186 continue; 1187 } 1188 1189 /* Go past the rx header */ 1190 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1191 m_adj(m, BFE_RX_OFFSET); 1192 m->m_len = m->m_pkthdr.len = len; 1193 } else { 1194 bfe_list_newbuf(sc, cons, m); 1195 ifp->if_ierrors++; 1196 BFE_INC(cons, BFE_RX_LIST_CNT); 1197 continue; 1198 } 1199 1200 ifp->if_ipackets++; 1201 m->m_pkthdr.rcvif = ifp; 1202 BFE_UNLOCK(sc); 1203 (*ifp->if_input)(ifp, m); 1204 BFE_LOCK(sc); 1205 1206 BFE_INC(cons, BFE_RX_LIST_CNT); 1207 } 1208 sc->bfe_rx_cons = cons; 1209 BFE_UNLOCK(sc); 1210 } 1211 1212 static void 1213 bfe_intr(void *xsc) 1214 { 1215 struct bfe_softc *sc = xsc; 1216 struct ifnet *ifp; 1217 u_int32_t istat, imask, flag; 1218 1219 ifp = &sc->arpcom.ac_if; 1220 1221 BFE_LOCK(sc); 1222 1223 istat = CSR_READ_4(sc, BFE_ISTAT); 1224 imask = CSR_READ_4(sc, BFE_IMASK); 1225 1226 /* 1227 * Defer unsolicited interrupts - This is necessary because setting the 1228 * chips interrupt mask register to 0 doesn't actually stop the 1229 * interrupts 1230 */ 1231 istat &= imask; 1232 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1233 CSR_READ_4(sc, BFE_ISTAT); 1234 1235 /* not expecting this interrupt, disregard it */ 1236 if(istat == 0) { 1237 BFE_UNLOCK(sc); 1238 return; 1239 } 1240 1241 if(istat & BFE_ISTAT_ERRORS) { 1242 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1243 if(flag & BFE_STAT_EMASK) 1244 ifp->if_oerrors++; 1245 1246 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1247 if(flag & BFE_RX_FLAG_ERRORS) 1248 ifp->if_ierrors++; 1249 1250 ifp->if_flags &= ~IFF_RUNNING; 1251 bfe_init(sc); 1252 } 1253 1254 /* A packet was received */ 1255 if(istat & BFE_ISTAT_RX) 1256 bfe_rxeof(sc); 1257 1258 /* A packet was sent */ 1259 if(istat & BFE_ISTAT_TX) 1260 bfe_txeof(sc); 1261 1262 /* We have packets pending, fire them out */ 1263 if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1264 bfe_start(ifp); 1265 1266 BFE_UNLOCK(sc); 1267 } 1268 1269 static int 1270 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1271 { 1272 struct bfe_desc *d = NULL; 1273 struct bfe_data *r = NULL; 1274 struct mbuf *m; 1275 u_int32_t frag, cur, cnt = 0; 1276 int chainlen = 0; 1277 1278 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1279 return (ENOBUFS); 1280 1281 /* 1282 * Count the number of frags in this chain to see if 1283 * we need to m_defrag. Since the descriptor list is shared 1284 * by all packets, we'll m_defrag long chains so that they 1285 * do not use up the entire list, even if they would fit. 1286 */ 1287 for(m = m_head; m != NULL; m = m->m_next) 1288 chainlen++; 1289 1290 1291 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1292 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1293 m = m_defrag(m_head, M_DONTWAIT); 1294 if (m == NULL) 1295 return (ENOBUFS); 1296 m_head = m; 1297 } 1298 1299 /* 1300 * Start packing the mbufs in this chain into 1301 * the fragment pointers. Stop when we run out 1302 * of fragments or hit the end of the mbuf chain. 1303 */ 1304 m = m_head; 1305 cur = frag = *txidx; 1306 cnt = 0; 1307 1308 for(m = m_head; m != NULL; m = m->m_next) { 1309 if(m->m_len != 0) { 1310 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1311 return (ENOBUFS); 1312 1313 d = &sc->bfe_tx_list[cur]; 1314 r = &sc->bfe_tx_ring[cur]; 1315 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1316 /* always intterupt on completion */ 1317 d->bfe_ctrl |= BFE_DESC_IOC; 1318 if(cnt == 0) 1319 /* Set start of frame */ 1320 d->bfe_ctrl |= BFE_DESC_SOF; 1321 if(cur == BFE_TX_LIST_CNT - 1) 1322 /* 1323 * Tell the chip to wrap to the start of 1324 * the descriptor list 1325 */ 1326 d->bfe_ctrl |= BFE_DESC_EOT; 1327 1328 bus_dmamap_load(sc->bfe_tag, 1329 r->bfe_map, mtod(m, void*), m->m_len, 1330 bfe_dma_map_desc, d, 0); 1331 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1332 BUS_DMASYNC_PREREAD); 1333 1334 frag = cur; 1335 BFE_INC(cur, BFE_TX_LIST_CNT); 1336 cnt++; 1337 } 1338 } 1339 1340 if (m != NULL) 1341 return (ENOBUFS); 1342 1343 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1344 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1345 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1346 1347 *txidx = cur; 1348 sc->bfe_tx_cnt += cnt; 1349 return (0); 1350 } 1351 1352 /* 1353 * Set up to transmit a packet 1354 */ 1355 static void 1356 bfe_start(struct ifnet *ifp) 1357 { 1358 struct bfe_softc *sc; 1359 struct mbuf *m_head = NULL; 1360 int idx; 1361 1362 sc = ifp->if_softc; 1363 idx = sc->bfe_tx_prod; 1364 1365 BFE_LOCK(sc); 1366 1367 /* 1368 * Not much point trying to send if the link is down 1369 * or we have nothing to send. 1370 */ 1371 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1372 BFE_UNLOCK(sc); 1373 return; 1374 } 1375 1376 if (ifp->if_flags & IFF_OACTIVE) { 1377 BFE_UNLOCK(sc); 1378 return; 1379 } 1380 1381 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1382 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1383 if(m_head == NULL) 1384 break; 1385 1386 /* 1387 * Pack the data into the tx ring. If we dont have 1388 * enough room, let the chip drain the ring. 1389 */ 1390 if(bfe_encap(sc, m_head, &idx)) { 1391 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1392 ifp->if_flags |= IFF_OACTIVE; 1393 break; 1394 } 1395 1396 /* 1397 * If there's a BPF listener, bounce a copy of this frame 1398 * to him. 1399 */ 1400 BPF_MTAP(ifp, m_head); 1401 } 1402 1403 sc->bfe_tx_prod = idx; 1404 /* Transmit - twice due to apparent hardware bug */ 1405 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1406 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1407 1408 /* 1409 * Set a timeout in case the chip goes out to lunch. 1410 */ 1411 ifp->if_timer = 5; 1412 BFE_UNLOCK(sc); 1413 } 1414 1415 static void 1416 bfe_init(void *xsc) 1417 { 1418 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1419 struct ifnet *ifp = &sc->arpcom.ac_if; 1420 1421 BFE_LOCK(sc); 1422 1423 if (ifp->if_flags & IFF_RUNNING) { 1424 BFE_UNLOCK(sc); 1425 return; 1426 } 1427 1428 bfe_stop(sc); 1429 bfe_chip_reset(sc); 1430 1431 if (bfe_list_rx_init(sc) == ENOBUFS) { 1432 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1433 sc->bfe_unit); 1434 bfe_stop(sc); 1435 return; 1436 } 1437 1438 bfe_set_rx_mode(sc); 1439 1440 /* Enable the chip and core */ 1441 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1442 /* Enable interrupts */ 1443 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1444 1445 bfe_ifmedia_upd(ifp); 1446 ifp->if_flags |= IFF_RUNNING; 1447 ifp->if_flags &= ~IFF_OACTIVE; 1448 1449 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1450 BFE_UNLOCK(sc); 1451 } 1452 1453 /* 1454 * Set media options. 1455 */ 1456 static int 1457 bfe_ifmedia_upd(struct ifnet *ifp) 1458 { 1459 struct bfe_softc *sc; 1460 struct mii_data *mii; 1461 1462 sc = ifp->if_softc; 1463 1464 BFE_LOCK(sc); 1465 1466 mii = device_get_softc(sc->bfe_miibus); 1467 sc->bfe_link = 0; 1468 if (mii->mii_instance) { 1469 struct mii_softc *miisc; 1470 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1471 miisc = LIST_NEXT(miisc, mii_list)) 1472 mii_phy_reset(miisc); 1473 } 1474 mii_mediachg(mii); 1475 1476 BFE_UNLOCK(sc); 1477 return (0); 1478 } 1479 1480 /* 1481 * Report current media status. 1482 */ 1483 static void 1484 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1485 { 1486 struct bfe_softc *sc = ifp->if_softc; 1487 struct mii_data *mii; 1488 1489 BFE_LOCK(sc); 1490 1491 mii = device_get_softc(sc->bfe_miibus); 1492 mii_pollstat(mii); 1493 ifmr->ifm_active = mii->mii_media_active; 1494 ifmr->ifm_status = mii->mii_media_status; 1495 1496 BFE_UNLOCK(sc); 1497 } 1498 1499 static int 1500 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1501 { 1502 struct bfe_softc *sc = ifp->if_softc; 1503 struct ifreq *ifr = (struct ifreq *) data; 1504 struct mii_data *mii; 1505 int error = 0; 1506 1507 BFE_LOCK(sc); 1508 1509 switch(command) { 1510 case SIOCSIFFLAGS: 1511 if(ifp->if_flags & IFF_UP) 1512 if(ifp->if_flags & IFF_RUNNING) 1513 bfe_set_rx_mode(sc); 1514 else 1515 bfe_init(sc); 1516 else if(ifp->if_flags & IFF_RUNNING) 1517 bfe_stop(sc); 1518 break; 1519 case SIOCADDMULTI: 1520 case SIOCDELMULTI: 1521 if(ifp->if_flags & IFF_RUNNING) 1522 bfe_set_rx_mode(sc); 1523 break; 1524 case SIOCGIFMEDIA: 1525 case SIOCSIFMEDIA: 1526 mii = device_get_softc(sc->bfe_miibus); 1527 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1528 command); 1529 break; 1530 default: 1531 error = ether_ioctl(ifp, command, data); 1532 break; 1533 } 1534 1535 BFE_UNLOCK(sc); 1536 return (error); 1537 } 1538 1539 static void 1540 bfe_watchdog(struct ifnet *ifp) 1541 { 1542 struct bfe_softc *sc; 1543 1544 sc = ifp->if_softc; 1545 1546 BFE_LOCK(sc); 1547 1548 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1549 1550 ifp->if_flags &= ~IFF_RUNNING; 1551 bfe_init(sc); 1552 1553 ifp->if_oerrors++; 1554 1555 BFE_UNLOCK(sc); 1556 } 1557 1558 static void 1559 bfe_tick(void *xsc) 1560 { 1561 struct bfe_softc *sc = xsc; 1562 struct mii_data *mii; 1563 1564 if (sc == NULL) 1565 return; 1566 1567 BFE_LOCK(sc); 1568 1569 mii = device_get_softc(sc->bfe_miibus); 1570 1571 bfe_stats_update(sc); 1572 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1573 1574 if(sc->bfe_link) { 1575 BFE_UNLOCK(sc); 1576 return; 1577 } 1578 1579 mii_tick(mii); 1580 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1581 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1582 sc->bfe_link++; 1583 1584 BFE_UNLOCK(sc); 1585 } 1586 1587 /* 1588 * Stop the adapter and free any mbufs allocated to the 1589 * RX and TX lists. 1590 */ 1591 static void 1592 bfe_stop(struct bfe_softc *sc) 1593 { 1594 struct ifnet *ifp; 1595 1596 BFE_LOCK(sc); 1597 1598 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1599 1600 ifp = &sc->arpcom.ac_if; 1601 1602 bfe_chip_halt(sc); 1603 bfe_tx_ring_free(sc); 1604 bfe_rx_ring_free(sc); 1605 1606 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1607 1608 BFE_UNLOCK(sc); 1609 } 1610