1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006-2014 QLogic Corporation 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * The following controllers are supported by this driver: 34 * BCM5706C A2, A3 35 * BCM5706S A2, A3 36 * BCM5708C B1, B2 37 * BCM5708S B1, B2 38 * BCM5709C A1, C0 39 * BCM5709S A1, C0 40 * BCM5716C C0 41 * BCM5716S C0 42 * 43 * The following controllers are not supported by this driver: 44 * BCM5706C A0, A1 (pre-production) 45 * BCM5706S A0, A1 (pre-production) 46 * BCM5708C A0, B0 (pre-production) 47 * BCM5708S A0, B0 (pre-production) 48 * BCM5709C A0 B0, B1, B2 (pre-production) 49 * BCM5709S A0, B0, B1, B2 (pre-production) 50 */ 51 52 #include "opt_bce.h" 53 54 #include <sys/param.h> 55 #include <sys/endian.h> 56 #include <sys/systm.h> 57 #include <sys/sockio.h> 58 #include <sys/lock.h> 59 #include <sys/mbuf.h> 60 #include <sys/malloc.h> 61 #include <sys/mutex.h> 62 #include <sys/kernel.h> 63 #include <sys/module.h> 64 #include <sys/socket.h> 65 #include <sys/sysctl.h> 66 #include <sys/queue.h> 67 68 #include <net/bpf.h> 69 #include <net/ethernet.h> 70 #include <net/if.h> 71 #include <net/if_var.h> 72 #include <net/if_arp.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <net/if_types.h> 77 #include <net/if_vlan_var.h> 78 79 #include <netinet/in_systm.h> 80 #include <netinet/in.h> 81 #include <netinet/if_ether.h> 82 #include <netinet/ip.h> 83 #include <netinet/ip6.h> 84 #include <netinet/tcp.h> 85 #include <netinet/udp.h> 86 87 #include <machine/bus.h> 88 #include <machine/resource.h> 89 #include <sys/bus.h> 90 #include <sys/rman.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include "miidevs.h" 95 #include <dev/mii/brgphyreg.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 100 #include "miibus_if.h" 101 102 #include <dev/bce/if_bcereg.h> 103 #include <dev/bce/if_bcefw.h> 104 105 /****************************************************************************/ 106 /* BCE Debug Options */ 107 /****************************************************************************/ 108 #ifdef BCE_DEBUG 109 u32 bce_debug = BCE_WARN; 110 111 /* 0 = Never */ 112 /* 1 = 1 in 2,147,483,648 */ 113 /* 256 = 1 in 8,388,608 */ 114 /* 2048 = 1 in 1,048,576 */ 115 /* 65536 = 1 in 32,768 */ 116 /* 1048576 = 1 in 2,048 */ 117 /* 268435456 = 1 in 8 */ 118 /* 536870912 = 1 in 4 */ 119 /* 1073741824 = 1 in 2 */ 120 121 /* Controls how often the l2_fhdr frame error check will fail. */ 122 int l2fhdr_error_sim_control = 0; 123 124 /* Controls how often the unexpected attention check will fail. */ 125 int unexpected_attention_sim_control = 0; 126 127 /* Controls how often to simulate an mbuf allocation failure. */ 128 int mbuf_alloc_failed_sim_control = 0; 129 130 /* Controls how often to simulate a DMA mapping failure. */ 131 int dma_map_addr_failed_sim_control = 0; 132 133 /* Controls how often to simulate a bootcode failure. */ 134 int bootcode_running_failure_sim_control = 0; 135 #endif 136 137 /****************************************************************************/ 138 /* PCI Device ID Table */ 139 /* */ 140 /* Used by bce_probe() to identify the devices supported by this driver. */ 141 /****************************************************************************/ 142 #define BCE_DEVDESC_MAX 64 143 144 static const struct bce_type bce_devs[] = { 145 /* BCM5706C Controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 147 "HP NC370T Multifunction Gigabit Server Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 149 "HP NC370i Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 151 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 153 "HP NC371i Multifunction Gigabit Server Adapter" }, 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 155 "QLogic NetXtreme II BCM5706 1000Base-T" }, 156 157 /* BCM5706S controllers and OEM boards. */ 158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 159 "HP NC370F Multifunction Gigabit Server Adapter" }, 160 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 161 "QLogic NetXtreme II BCM5706 1000Base-SX" }, 162 163 /* BCM5708C controllers and OEM boards. */ 164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 165 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 167 "HP NC373i Multifunction Gigabit Server Adapter" }, 168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 169 "HP NC374m PCIe Multifunction Adapter" }, 170 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 171 "QLogic NetXtreme II BCM5708 1000Base-T" }, 172 173 /* BCM5708S controllers and OEM boards. */ 174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 175 "HP NC373m Multifunction Gigabit Server Adapter" }, 176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 177 "HP NC373i Multifunction Gigabit Server Adapter" }, 178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 179 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 180 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 181 "QLogic NetXtreme II BCM5708 1000Base-SX" }, 182 183 /* BCM5709C controllers and OEM boards. */ 184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 185 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 187 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 188 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 189 "QLogic NetXtreme II BCM5709 1000Base-T" }, 190 191 /* BCM5709S controllers and OEM boards. */ 192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 193 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 195 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 196 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 197 "QLogic NetXtreme II BCM5709 1000Base-SX" }, 198 199 /* BCM5716 controllers and OEM boards. */ 200 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 201 "QLogic NetXtreme II BCM5716 1000Base-T" }, 202 { 0, 0, 0, 0, NULL } 203 }; 204 205 /****************************************************************************/ 206 /* Supported Flash NVRAM device data. */ 207 /****************************************************************************/ 208 static const struct flash_spec flash_table[] = 209 { 210 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 211 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 212 213 /* Slow EEPROM */ 214 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 215 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 216 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 217 "EEPROM - slow"}, 218 /* Expansion entry 0001 */ 219 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 222 "Entry 0001"}, 223 /* Saifun SA25F010 (non-buffered flash) */ 224 /* strap, cfg1, & write1 need updates */ 225 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 228 "Non-buffered flash (128kB)"}, 229 /* Saifun SA25F020 (non-buffered flash) */ 230 /* strap, cfg1, & write1 need updates */ 231 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 232 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 233 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 234 "Non-buffered flash (256kB)"}, 235 /* Expansion entry 0100 */ 236 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 239 "Entry 0100"}, 240 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 241 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 242 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 243 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 244 "Entry 0101: ST M45PE10 (128kB non-buffered)"}, 245 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 246 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 247 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 248 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 249 "Entry 0110: ST M45PE20 (256kB non-buffered)"}, 250 /* Saifun SA25F005 (non-buffered flash) */ 251 /* strap, cfg1, & write1 need updates */ 252 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 254 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 255 "Non-buffered flash (64kB)"}, 256 /* Fast EEPROM */ 257 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 258 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 259 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 260 "EEPROM - fast"}, 261 /* Expansion entry 1001 */ 262 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 263 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 264 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 265 "Entry 1001"}, 266 /* Expansion entry 1010 */ 267 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 268 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 269 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 270 "Entry 1010"}, 271 /* ATMEL AT45DB011B (buffered flash) */ 272 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 273 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 274 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 275 "Buffered flash (128kB)"}, 276 /* Expansion entry 1100 */ 277 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 278 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 279 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 280 "Entry 1100"}, 281 /* Expansion entry 1101 */ 282 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 283 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 284 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 285 "Entry 1101"}, 286 /* Ateml Expansion entry 1110 */ 287 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 288 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 289 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 290 "Entry 1110 (Atmel)"}, 291 /* ATMEL AT45DB021B (buffered flash) */ 292 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 293 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 294 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 295 "Buffered flash (256kB)"}, 296 }; 297 298 /* 299 * The BCM5709 controllers transparently handle the 300 * differences between Atmel 264 byte pages and all 301 * flash devices which use 256 byte pages, so no 302 * logical-to-physical mapping is required in the 303 * driver. 304 */ 305 static const struct flash_spec flash_5709 = { 306 .flags = BCE_NV_BUFFERED, 307 .page_bits = BCM5709_FLASH_PAGE_BITS, 308 .page_size = BCM5709_FLASH_PAGE_SIZE, 309 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 310 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 311 .name = "5709/5716 buffered flash (256kB)", 312 }; 313 314 /****************************************************************************/ 315 /* FreeBSD device entry points. */ 316 /****************************************************************************/ 317 static int bce_probe (device_t); 318 static int bce_attach (device_t); 319 static int bce_detach (device_t); 320 static int bce_shutdown (device_t); 321 322 /****************************************************************************/ 323 /* BCE Debug Data Structure Dump Routines */ 324 /****************************************************************************/ 325 #ifdef BCE_DEBUG 326 static u32 bce_reg_rd (struct bce_softc *, u32); 327 static void bce_reg_wr (struct bce_softc *, u32, u32); 328 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 329 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 330 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 331 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 332 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 333 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 334 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 335 static void bce_dump_txbd (struct bce_softc *, 336 int, struct tx_bd *); 337 static void bce_dump_rxbd (struct bce_softc *, 338 int, struct rx_bd *); 339 static void bce_dump_pgbd (struct bce_softc *, 340 int, struct rx_bd *); 341 static void bce_dump_l2fhdr (struct bce_softc *, 342 int, struct l2_fhdr *); 343 static void bce_dump_ctx (struct bce_softc *, u16); 344 static void bce_dump_ftqs (struct bce_softc *); 345 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 346 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 347 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 348 static void bce_dump_status_block (struct bce_softc *); 349 static void bce_dump_stats_block (struct bce_softc *); 350 static void bce_dump_driver_state (struct bce_softc *); 351 static void bce_dump_hw_state (struct bce_softc *); 352 static void bce_dump_shmem_state (struct bce_softc *); 353 static void bce_dump_mq_regs (struct bce_softc *); 354 static void bce_dump_bc_state (struct bce_softc *); 355 static void bce_dump_txp_state (struct bce_softc *, int); 356 static void bce_dump_rxp_state (struct bce_softc *, int); 357 static void bce_dump_tpat_state (struct bce_softc *, int); 358 static void bce_dump_cp_state (struct bce_softc *, int); 359 static void bce_dump_com_state (struct bce_softc *, int); 360 static void bce_dump_rv2p_state (struct bce_softc *); 361 static void bce_breakpoint (struct bce_softc *); 362 #endif /*BCE_DEBUG */ 363 364 /****************************************************************************/ 365 /* BCE Register/Memory Access Routines */ 366 /****************************************************************************/ 367 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 368 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 369 static void bce_shmem_wr (struct bce_softc *, u32, u32); 370 static u32 bce_shmem_rd (struct bce_softc *, u32); 371 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 372 static int bce_miibus_read_reg (device_t, int, int); 373 static int bce_miibus_write_reg (device_t, int, int, int); 374 static void bce_miibus_statchg (device_t); 375 376 #ifdef BCE_DEBUG 377 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 378 #ifdef BCE_NVRAM_WRITE_SUPPORT 379 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 380 #endif 381 #endif 382 383 /****************************************************************************/ 384 /* BCE NVRAM Access Routines */ 385 /****************************************************************************/ 386 static int bce_acquire_nvram_lock (struct bce_softc *); 387 static int bce_release_nvram_lock (struct bce_softc *); 388 static void bce_enable_nvram_access(struct bce_softc *); 389 static void bce_disable_nvram_access(struct bce_softc *); 390 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 391 static int bce_init_nvram (struct bce_softc *); 392 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 393 static int bce_nvram_test (struct bce_softc *); 394 #ifdef BCE_NVRAM_WRITE_SUPPORT 395 static int bce_enable_nvram_write (struct bce_softc *); 396 static void bce_disable_nvram_write(struct bce_softc *); 397 static int bce_nvram_erase_page (struct bce_softc *, u32); 398 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 399 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 400 #endif 401 402 /****************************************************************************/ 403 /* */ 404 /****************************************************************************/ 405 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 406 static void bce_get_media (struct bce_softc *); 407 static void bce_init_media (struct bce_softc *); 408 static u32 bce_get_rphy_link (struct bce_softc *); 409 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 410 static int bce_dma_alloc (device_t); 411 static void bce_dma_free (struct bce_softc *); 412 static void bce_release_resources (struct bce_softc *); 413 414 /****************************************************************************/ 415 /* BCE Firmware Synchronization and Load */ 416 /****************************************************************************/ 417 static void bce_fw_cap_init (struct bce_softc *); 418 static int bce_fw_sync (struct bce_softc *, u32); 419 static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32, 420 u32); 421 static void bce_load_cpu_fw (struct bce_softc *, 422 struct cpu_reg *, struct fw_info *); 423 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 424 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 425 static void bce_start_rxp_cpu (struct bce_softc *); 426 static void bce_init_rxp_cpu (struct bce_softc *); 427 static void bce_init_txp_cpu (struct bce_softc *); 428 static void bce_init_tpat_cpu (struct bce_softc *); 429 static void bce_init_cp_cpu (struct bce_softc *); 430 static void bce_init_com_cpu (struct bce_softc *); 431 static void bce_init_cpus (struct bce_softc *); 432 433 static void bce_print_adapter_info (struct bce_softc *); 434 static void bce_probe_pci_caps (device_t, struct bce_softc *); 435 static void bce_stop (struct bce_softc *); 436 static int bce_reset (struct bce_softc *, u32); 437 static int bce_chipinit (struct bce_softc *); 438 static int bce_blockinit (struct bce_softc *); 439 440 static int bce_init_tx_chain (struct bce_softc *); 441 static void bce_free_tx_chain (struct bce_softc *); 442 443 static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *); 444 static int bce_init_rx_chain (struct bce_softc *); 445 static void bce_fill_rx_chain (struct bce_softc *); 446 static void bce_free_rx_chain (struct bce_softc *); 447 448 static int bce_get_pg_buf (struct bce_softc *, u16, u16); 449 static int bce_init_pg_chain (struct bce_softc *); 450 static void bce_fill_pg_chain (struct bce_softc *); 451 static void bce_free_pg_chain (struct bce_softc *); 452 453 static struct mbuf *bce_tso_setup (struct bce_softc *, 454 struct mbuf **, u16 *); 455 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 456 static void bce_start_locked (if_t); 457 static void bce_start (if_t); 458 static int bce_ioctl (if_t, u_long, caddr_t); 459 static uint64_t bce_get_counter (if_t, ift_counter); 460 static void bce_watchdog (struct bce_softc *); 461 static int bce_ifmedia_upd (if_t); 462 static int bce_ifmedia_upd_locked (if_t); 463 static void bce_ifmedia_sts (if_t, struct ifmediareq *); 464 static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *); 465 static void bce_init_locked (struct bce_softc *); 466 static void bce_init (void *); 467 static void bce_mgmt_init_locked (struct bce_softc *sc); 468 469 static int bce_init_ctx (struct bce_softc *); 470 static void bce_get_mac_addr (struct bce_softc *); 471 static void bce_set_mac_addr (struct bce_softc *); 472 static void bce_phy_intr (struct bce_softc *); 473 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 474 static void bce_rx_intr (struct bce_softc *); 475 static void bce_tx_intr (struct bce_softc *); 476 static void bce_disable_intr (struct bce_softc *); 477 static void bce_enable_intr (struct bce_softc *, int); 478 479 static void bce_intr (void *); 480 static void bce_set_rx_mode (struct bce_softc *); 481 static void bce_stats_update (struct bce_softc *); 482 static void bce_tick (void *); 483 static void bce_pulse (void *); 484 static void bce_add_sysctls (struct bce_softc *); 485 486 /****************************************************************************/ 487 /* FreeBSD device dispatch table. */ 488 /****************************************************************************/ 489 static device_method_t bce_methods[] = { 490 /* Device interface (device_if.h) */ 491 DEVMETHOD(device_probe, bce_probe), 492 DEVMETHOD(device_attach, bce_attach), 493 DEVMETHOD(device_detach, bce_detach), 494 DEVMETHOD(device_shutdown, bce_shutdown), 495 /* Supported by device interface but not used here. */ 496 /* DEVMETHOD(device_identify, bce_identify), */ 497 /* DEVMETHOD(device_suspend, bce_suspend), */ 498 /* DEVMETHOD(device_resume, bce_resume), */ 499 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 500 501 /* MII interface (miibus_if.h) */ 502 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 503 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 504 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 505 /* Supported by MII interface but not used here. */ 506 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 507 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 508 509 DEVMETHOD_END 510 }; 511 512 static driver_t bce_driver = { 513 "bce", 514 bce_methods, 515 sizeof(struct bce_softc) 516 }; 517 518 MODULE_DEPEND(bce, pci, 1, 1, 1); 519 MODULE_DEPEND(bce, ether, 1, 1, 1); 520 MODULE_DEPEND(bce, miibus, 1, 1, 1); 521 522 DRIVER_MODULE(bce, pci, bce_driver, NULL, NULL); 523 DRIVER_MODULE(miibus, bce, miibus_driver, NULL, NULL); 524 MODULE_PNP_INFO("U16:vendor;U16:device;U16:#;U16:#;D:#", pci, bce, 525 bce_devs, nitems(bce_devs) - 1); 526 527 /****************************************************************************/ 528 /* Tunable device values */ 529 /****************************************************************************/ 530 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 531 "bce driver parameters"); 532 533 /* Allowable values are TRUE or FALSE */ 534 static int bce_verbose = TRUE; 535 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 536 "Verbose output enable/disable"); 537 538 /* Allowable values are TRUE or FALSE */ 539 static int bce_tso_enable = TRUE; 540 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 541 "TSO Enable/Disable"); 542 543 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 544 /* ToDo: Add MSI-X support. */ 545 static int bce_msi_enable = 1; 546 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 547 "MSI-X|MSI|INTx selector"); 548 549 /* Allowable values are 1, 2, 4, 8. */ 550 static int bce_rx_pages = DEFAULT_RX_PAGES; 551 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 552 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 553 554 /* Allowable values are 1, 2, 4, 8. */ 555 static int bce_tx_pages = DEFAULT_TX_PAGES; 556 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 557 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 558 559 /* Allowable values are TRUE or FALSE. */ 560 static int bce_hdr_split = TRUE; 561 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 562 "Frame header/payload splitting Enable/Disable"); 563 564 /* Allowable values are TRUE or FALSE. */ 565 static int bce_strict_rx_mtu = FALSE; 566 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN, 567 &bce_strict_rx_mtu, 0, 568 "Enable/Disable strict RX frame size checking"); 569 570 /* Allowable values are 0 ... 100 */ 571 #ifdef BCE_DEBUG 572 /* Generate 1 interrupt for every transmit completion. */ 573 static int bce_tx_quick_cons_trip_int = 1; 574 #else 575 /* Generate 1 interrupt for every 20 transmit completions. */ 576 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 577 #endif 578 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 579 &bce_tx_quick_cons_trip_int, 0, 580 "Transmit BD trip point during interrupts"); 581 582 /* Allowable values are 0 ... 100 */ 583 /* Generate 1 interrupt for every transmit completion. */ 584 #ifdef BCE_DEBUG 585 static int bce_tx_quick_cons_trip = 1; 586 #else 587 /* Generate 1 interrupt for every 20 transmit completions. */ 588 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 589 #endif 590 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 591 &bce_tx_quick_cons_trip, 0, 592 "Transmit BD trip point"); 593 594 /* Allowable values are 0 ... 100 */ 595 #ifdef BCE_DEBUG 596 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 597 static int bce_tx_ticks_int = 0; 598 #else 599 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 600 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 601 #endif 602 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 603 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 604 605 /* Allowable values are 0 ... 100 */ 606 #ifdef BCE_DEBUG 607 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 608 static int bce_tx_ticks = 0; 609 #else 610 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 611 static int bce_tx_ticks = DEFAULT_TX_TICKS; 612 #endif 613 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 614 &bce_tx_ticks, 0, "Transmit ticks count"); 615 616 /* Allowable values are 1 ... 100 */ 617 #ifdef BCE_DEBUG 618 /* Generate 1 interrupt for every received frame. */ 619 static int bce_rx_quick_cons_trip_int = 1; 620 #else 621 /* Generate 1 interrupt for every 6 received frames. */ 622 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 623 #endif 624 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 625 &bce_rx_quick_cons_trip_int, 0, 626 "Receive BD trip point during interrupts"); 627 628 /* Allowable values are 1 ... 100 */ 629 #ifdef BCE_DEBUG 630 /* Generate 1 interrupt for every received frame. */ 631 static int bce_rx_quick_cons_trip = 1; 632 #else 633 /* Generate 1 interrupt for every 6 received frames. */ 634 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 635 #endif 636 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 637 &bce_rx_quick_cons_trip, 0, 638 "Receive BD trip point"); 639 640 /* Allowable values are 0 ... 100 */ 641 #ifdef BCE_DEBUG 642 /* Generate an int. if 0us have elapsed since the last received frame. */ 643 static int bce_rx_ticks_int = 0; 644 #else 645 /* Generate an int. if 18us have elapsed since the last received frame. */ 646 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 647 #endif 648 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 649 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 650 651 /* Allowable values are 0 ... 100 */ 652 #ifdef BCE_DEBUG 653 /* Generate an int. if 0us have elapsed since the last received frame. */ 654 static int bce_rx_ticks = 0; 655 #else 656 /* Generate an int. if 18us have elapsed since the last received frame. */ 657 static int bce_rx_ticks = DEFAULT_RX_TICKS; 658 #endif 659 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 660 &bce_rx_ticks, 0, "Receive ticks count"); 661 662 /****************************************************************************/ 663 /* Device probe function. */ 664 /* */ 665 /* Compares the device to the driver's list of supported devices and */ 666 /* reports back to the OS whether this is the right driver for the device. */ 667 /* */ 668 /* Returns: */ 669 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 670 /****************************************************************************/ 671 static int 672 bce_probe(device_t dev) 673 { 674 const struct bce_type *t; 675 struct bce_softc *sc; 676 char *descbuf; 677 u16 vid = 0, did = 0, svid = 0, sdid = 0; 678 679 t = bce_devs; 680 681 sc = device_get_softc(dev); 682 sc->bce_unit = device_get_unit(dev); 683 sc->bce_dev = dev; 684 685 /* Get the data for the device to be probed. */ 686 vid = pci_get_vendor(dev); 687 did = pci_get_device(dev); 688 svid = pci_get_subvendor(dev); 689 sdid = pci_get_subdevice(dev); 690 691 DBPRINT(sc, BCE_EXTREME_LOAD, 692 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 693 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 694 695 /* Look through the list of known devices for a match. */ 696 while(t->bce_name != NULL) { 697 if ((vid == t->bce_vid) && (did == t->bce_did) && 698 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 699 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 700 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 701 702 if (descbuf == NULL) 703 return(ENOMEM); 704 705 /* Print out the device identity. */ 706 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 707 t->bce_name, (((pci_read_config(dev, 708 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 709 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 710 711 device_set_desc_copy(dev, descbuf); 712 free(descbuf, M_TEMP); 713 return(BUS_PROBE_DEFAULT); 714 } 715 t++; 716 } 717 718 return(ENXIO); 719 } 720 721 /****************************************************************************/ 722 /* PCI Capabilities Probe Function. */ 723 /* */ 724 /* Walks the PCI capabiites list for the device to find what features are */ 725 /* supported. */ 726 /* */ 727 /* Returns: */ 728 /* None. */ 729 /****************************************************************************/ 730 static void 731 bce_print_adapter_info(struct bce_softc *sc) 732 { 733 int i = 0; 734 735 DBENTER(BCE_VERBOSE_LOAD); 736 737 if (bce_verbose || bootverbose) { 738 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 739 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 740 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 741 742 /* Bus info. */ 743 if (sc->bce_flags & BCE_PCIE_FLAG) { 744 printf("Bus (PCIe x%d, ", sc->link_width); 745 switch (sc->link_speed) { 746 case 1: printf("2.5Gbps); "); break; 747 case 2: printf("5Gbps); "); break; 748 default: printf("Unknown link speed); "); 749 } 750 } else { 751 printf("Bus (PCI%s, %s, %dMHz); ", 752 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 753 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 754 "32-bit" : "64-bit"), sc->bus_speed_mhz); 755 } 756 757 /* Firmware version and device features. */ 758 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 759 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 760 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 761 762 if (bce_hdr_split == TRUE) { 763 printf("SPLT"); 764 i++; 765 } 766 767 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 768 if (i > 0) printf("|"); 769 printf("MSI"); i++; 770 } 771 772 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 773 if (i > 0) printf("|"); 774 printf("MSI-X"); i++; 775 } 776 777 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 778 if (i > 0) printf("|"); 779 printf("2.5G"); i++; 780 } 781 782 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) { 783 if (i > 0) printf("|"); 784 printf("Remote PHY(%s)", 785 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ? 786 "FIBER" : "TP"); i++; 787 } 788 789 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 790 if (i > 0) printf("|"); 791 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 792 } else { 793 printf(")\n"); 794 } 795 796 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 797 sc->bce_rx_quick_cons_trip_int, 798 sc->bce_rx_quick_cons_trip, 799 sc->bce_rx_ticks_int, 800 sc->bce_rx_ticks, 801 sc->bce_tx_quick_cons_trip_int, 802 sc->bce_tx_quick_cons_trip, 803 sc->bce_tx_ticks_int, 804 sc->bce_tx_ticks); 805 } 806 807 DBEXIT(BCE_VERBOSE_LOAD); 808 } 809 810 /****************************************************************************/ 811 /* PCI Capabilities Probe Function. */ 812 /* */ 813 /* Walks the PCI capabiites list for the device to find what features are */ 814 /* supported. */ 815 /* */ 816 /* Returns: */ 817 /* None. */ 818 /****************************************************************************/ 819 static void 820 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 821 { 822 u32 reg; 823 824 DBENTER(BCE_VERBOSE_LOAD); 825 826 /* Check if PCI-X capability is enabled. */ 827 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 828 if (reg != 0) 829 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 830 } 831 832 /* Check if PCIe capability is enabled. */ 833 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 834 if (reg != 0) { 835 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 836 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 837 "0x%08X\n", link_status); 838 sc->link_speed = link_status & 0xf; 839 sc->link_width = (link_status >> 4) & 0x3f; 840 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 841 sc->bce_flags |= BCE_PCIE_FLAG; 842 } 843 } 844 845 /* Check if MSI capability is enabled. */ 846 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 847 if (reg != 0) 848 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 849 } 850 851 /* Check if MSI-X capability is enabled. */ 852 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 853 if (reg != 0) 854 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 855 } 856 857 DBEXIT(BCE_VERBOSE_LOAD); 858 } 859 860 /****************************************************************************/ 861 /* Load and validate user tunable settings. */ 862 /* */ 863 /* Returns: */ 864 /* Nothing. */ 865 /****************************************************************************/ 866 static void 867 bce_set_tunables(struct bce_softc *sc) 868 { 869 /* Set sysctl values for RX page count. */ 870 switch (bce_rx_pages) { 871 case 1: 872 /* fall-through */ 873 case 2: 874 /* fall-through */ 875 case 4: 876 /* fall-through */ 877 case 8: 878 sc->rx_pages = bce_rx_pages; 879 break; 880 default: 881 sc->rx_pages = DEFAULT_RX_PAGES; 882 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 883 "hw.bce.rx_pages! Setting default of %d.\n", 884 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 885 } 886 887 /* ToDo: Consider allowing user setting for pg_pages. */ 888 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 889 890 /* Set sysctl values for TX page count. */ 891 switch (bce_tx_pages) { 892 case 1: 893 /* fall-through */ 894 case 2: 895 /* fall-through */ 896 case 4: 897 /* fall-through */ 898 case 8: 899 sc->tx_pages = bce_tx_pages; 900 break; 901 default: 902 sc->tx_pages = DEFAULT_TX_PAGES; 903 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 904 "hw.bce.tx_pages! Setting default of %d.\n", 905 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 906 } 907 908 /* 909 * Validate the TX trip point (i.e. the number of 910 * TX completions before a status block update is 911 * generated and an interrupt is asserted. 912 */ 913 if (bce_tx_quick_cons_trip_int <= 100) { 914 sc->bce_tx_quick_cons_trip_int = 915 bce_tx_quick_cons_trip_int; 916 } else { 917 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 918 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 919 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 920 DEFAULT_TX_QUICK_CONS_TRIP_INT); 921 sc->bce_tx_quick_cons_trip_int = 922 DEFAULT_TX_QUICK_CONS_TRIP_INT; 923 } 924 925 if (bce_tx_quick_cons_trip <= 100) { 926 sc->bce_tx_quick_cons_trip = 927 bce_tx_quick_cons_trip; 928 } else { 929 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 930 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 931 __FILE__, __LINE__, bce_tx_quick_cons_trip, 932 DEFAULT_TX_QUICK_CONS_TRIP); 933 sc->bce_tx_quick_cons_trip = 934 DEFAULT_TX_QUICK_CONS_TRIP; 935 } 936 937 /* 938 * Validate the TX ticks count (i.e. the maximum amount 939 * of time to wait after the last TX completion has 940 * occurred before a status block update is generated 941 * and an interrupt is asserted. 942 */ 943 if (bce_tx_ticks_int <= 100) { 944 sc->bce_tx_ticks_int = 945 bce_tx_ticks_int; 946 } else { 947 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 948 "hw.bce.tx_ticks_int! Setting default of %d.\n", 949 __FILE__, __LINE__, bce_tx_ticks_int, 950 DEFAULT_TX_TICKS_INT); 951 sc->bce_tx_ticks_int = 952 DEFAULT_TX_TICKS_INT; 953 } 954 955 if (bce_tx_ticks <= 100) { 956 sc->bce_tx_ticks = 957 bce_tx_ticks; 958 } else { 959 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 960 "hw.bce.tx_ticks! Setting default of %d.\n", 961 __FILE__, __LINE__, bce_tx_ticks, 962 DEFAULT_TX_TICKS); 963 sc->bce_tx_ticks = 964 DEFAULT_TX_TICKS; 965 } 966 967 /* 968 * Validate the RX trip point (i.e. the number of 969 * RX frames received before a status block update is 970 * generated and an interrupt is asserted. 971 */ 972 if (bce_rx_quick_cons_trip_int <= 100) { 973 sc->bce_rx_quick_cons_trip_int = 974 bce_rx_quick_cons_trip_int; 975 } else { 976 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 977 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 978 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 979 DEFAULT_RX_QUICK_CONS_TRIP_INT); 980 sc->bce_rx_quick_cons_trip_int = 981 DEFAULT_RX_QUICK_CONS_TRIP_INT; 982 } 983 984 if (bce_rx_quick_cons_trip <= 100) { 985 sc->bce_rx_quick_cons_trip = 986 bce_rx_quick_cons_trip; 987 } else { 988 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 989 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 990 __FILE__, __LINE__, bce_rx_quick_cons_trip, 991 DEFAULT_RX_QUICK_CONS_TRIP); 992 sc->bce_rx_quick_cons_trip = 993 DEFAULT_RX_QUICK_CONS_TRIP; 994 } 995 996 /* 997 * Validate the RX ticks count (i.e. the maximum amount 998 * of time to wait after the last RX frame has been 999 * received before a status block update is generated 1000 * and an interrupt is asserted. 1001 */ 1002 if (bce_rx_ticks_int <= 100) { 1003 sc->bce_rx_ticks_int = bce_rx_ticks_int; 1004 } else { 1005 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1006 "hw.bce.rx_ticks_int! Setting default of %d.\n", 1007 __FILE__, __LINE__, bce_rx_ticks_int, 1008 DEFAULT_RX_TICKS_INT); 1009 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 1010 } 1011 1012 if (bce_rx_ticks <= 100) { 1013 sc->bce_rx_ticks = bce_rx_ticks; 1014 } else { 1015 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1016 "hw.bce.rx_ticks! Setting default of %d.\n", 1017 __FILE__, __LINE__, bce_rx_ticks, 1018 DEFAULT_RX_TICKS); 1019 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1020 } 1021 1022 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1023 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1024 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1025 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1026 __FILE__, __LINE__); 1027 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1028 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1029 } 1030 1031 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1032 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1033 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1034 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1035 __FILE__, __LINE__); 1036 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1037 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1038 } 1039 } 1040 1041 /****************************************************************************/ 1042 /* Device attach function. */ 1043 /* */ 1044 /* Allocates device resources, performs secondary chip identification, */ 1045 /* resets and initializes the hardware, and initializes driver instance */ 1046 /* variables. */ 1047 /* */ 1048 /* Returns: */ 1049 /* 0 on success, positive value on failure. */ 1050 /****************************************************************************/ 1051 static int 1052 bce_attach(device_t dev) 1053 { 1054 struct bce_softc *sc; 1055 if_t ifp; 1056 u32 val; 1057 int count, error, rc = 0, rid; 1058 1059 sc = device_get_softc(dev); 1060 sc->bce_dev = dev; 1061 1062 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1063 1064 sc->bce_unit = device_get_unit(dev); 1065 1066 /* Set initial device and PHY flags */ 1067 sc->bce_flags = 0; 1068 sc->bce_phy_flags = 0; 1069 1070 bce_set_tunables(sc); 1071 1072 pci_enable_busmaster(dev); 1073 1074 /* Allocate PCI memory resources. */ 1075 rid = PCIR_BAR(0); 1076 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1077 &rid, RF_ACTIVE); 1078 1079 if (sc->bce_res_mem == NULL) { 1080 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1081 __FILE__, __LINE__); 1082 rc = ENXIO; 1083 goto bce_attach_fail; 1084 } 1085 1086 /* Get various resource handles. */ 1087 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1088 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1089 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1090 1091 bce_probe_pci_caps(dev, sc); 1092 1093 rid = 1; 1094 count = 0; 1095 #if 0 1096 /* Try allocating MSI-X interrupts. */ 1097 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1098 (bce_msi_enable >= 2) && 1099 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1100 &rid, RF_ACTIVE)) != NULL)) { 1101 msi_needed = count = 1; 1102 1103 if (((error = pci_alloc_msix(dev, &count)) != 0) || 1104 (count != msi_needed)) { 1105 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1106 "Received = %d, error = %d\n", __FILE__, __LINE__, 1107 msi_needed, count, error); 1108 count = 0; 1109 pci_release_msi(dev); 1110 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1111 sc->bce_res_irq); 1112 sc->bce_res_irq = NULL; 1113 } else { 1114 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1115 __FUNCTION__); 1116 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1117 } 1118 } 1119 #endif 1120 1121 /* Try allocating a MSI interrupt. */ 1122 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1123 (bce_msi_enable >= 1) && (count == 0)) { 1124 count = 1; 1125 if ((error = pci_alloc_msi(dev, &count)) != 0) { 1126 BCE_PRINTF("%s(%d): MSI allocation failed! " 1127 "error = %d\n", __FILE__, __LINE__, error); 1128 count = 0; 1129 pci_release_msi(dev); 1130 } else { 1131 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1132 "interrupt.\n", __FUNCTION__); 1133 sc->bce_flags |= BCE_USING_MSI_FLAG; 1134 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1135 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1136 rid = 1; 1137 } 1138 } 1139 1140 /* Try allocating a legacy interrupt. */ 1141 if (count == 0) { 1142 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1143 __FUNCTION__); 1144 rid = 0; 1145 } 1146 1147 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1148 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE)); 1149 1150 /* Report any IRQ allocation errors. */ 1151 if (sc->bce_res_irq == NULL) { 1152 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1153 __FILE__, __LINE__); 1154 rc = ENXIO; 1155 goto bce_attach_fail; 1156 } 1157 1158 /* Initialize mutex for the current device instance. */ 1159 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1160 1161 /* 1162 * Configure byte swap and enable indirect register access. 1163 * Rely on CPU to do target byte swapping on big endian systems. 1164 * Access to registers outside of PCI configurtion space are not 1165 * valid until this is done. 1166 */ 1167 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1168 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1169 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1170 1171 /* Save ASIC revsion info. */ 1172 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1173 1174 /* Weed out any non-production controller revisions. */ 1175 switch(BCE_CHIP_ID(sc)) { 1176 case BCE_CHIP_ID_5706_A0: 1177 case BCE_CHIP_ID_5706_A1: 1178 case BCE_CHIP_ID_5708_A0: 1179 case BCE_CHIP_ID_5708_B0: 1180 case BCE_CHIP_ID_5709_A0: 1181 case BCE_CHIP_ID_5709_B0: 1182 case BCE_CHIP_ID_5709_B1: 1183 case BCE_CHIP_ID_5709_B2: 1184 BCE_PRINTF("%s(%d): Unsupported controller " 1185 "revision (%c%d)!\n", __FILE__, __LINE__, 1186 (((pci_read_config(dev, PCIR_REVID, 4) & 1187 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1188 PCIR_REVID, 4) & 0xf)); 1189 rc = ENODEV; 1190 goto bce_attach_fail; 1191 } 1192 1193 /* 1194 * The embedded PCIe to PCI-X bridge (EPB) 1195 * in the 5708 cannot address memory above 1196 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1197 */ 1198 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1199 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1200 else 1201 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1202 1203 /* 1204 * Find the base address for shared memory access. 1205 * Newer versions of bootcode use a signature and offset 1206 * while older versions use a fixed address. 1207 */ 1208 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1209 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1210 /* Multi-port devices use different offsets in shared memory. */ 1211 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1212 (pci_get_function(sc->bce_dev) << 2)); 1213 else 1214 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1215 1216 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1217 __FUNCTION__, sc->bce_shmem_base); 1218 1219 /* Fetch the bootcode revision. */ 1220 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1221 for (int i = 0, j = 0; i < 3; i++) { 1222 u8 num; 1223 1224 num = (u8) (val >> (24 - (i * 8))); 1225 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1226 if (num >= k || !skip0 || k == 1) { 1227 sc->bce_bc_ver[j++] = (num / k) + '0'; 1228 skip0 = 0; 1229 } 1230 } 1231 1232 if (i != 2) 1233 sc->bce_bc_ver[j++] = '.'; 1234 } 1235 1236 /* Check if any management firwmare is enabled. */ 1237 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1238 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1239 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1240 1241 /* Allow time for firmware to enter the running state. */ 1242 for (int i = 0; i < 30; i++) { 1243 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1244 if (val & BCE_CONDITION_MFW_RUN_MASK) 1245 break; 1246 DELAY(10000); 1247 } 1248 1249 /* Check if management firmware is running. */ 1250 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1251 val &= BCE_CONDITION_MFW_RUN_MASK; 1252 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1253 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1254 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1255 int i = 0; 1256 1257 /* Read the management firmware version string. */ 1258 for (int j = 0; j < 3; j++) { 1259 val = bce_reg_rd_ind(sc, addr + j * 4); 1260 val = bswap32(val); 1261 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1262 i += 4; 1263 } 1264 } else { 1265 /* May cause firmware synchronization timeouts. */ 1266 BCE_PRINTF("%s(%d): Management firmware enabled " 1267 "but not running!\n", __FILE__, __LINE__); 1268 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1269 1270 /* ToDo: Any action the driver should take? */ 1271 } 1272 } 1273 1274 /* Get PCI bus information (speed and type). */ 1275 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1276 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1277 u32 clkreg; 1278 1279 sc->bce_flags |= BCE_PCIX_FLAG; 1280 1281 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1282 1283 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1284 switch (clkreg) { 1285 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1286 sc->bus_speed_mhz = 133; 1287 break; 1288 1289 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1290 sc->bus_speed_mhz = 100; 1291 break; 1292 1293 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1294 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1295 sc->bus_speed_mhz = 66; 1296 break; 1297 1298 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1299 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1300 sc->bus_speed_mhz = 50; 1301 break; 1302 1303 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1304 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1305 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1306 sc->bus_speed_mhz = 33; 1307 break; 1308 } 1309 } else { 1310 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1311 sc->bus_speed_mhz = 66; 1312 else 1313 sc->bus_speed_mhz = 33; 1314 } 1315 1316 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1317 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1318 1319 /* Find the media type for the adapter. */ 1320 bce_get_media(sc); 1321 1322 /* Reset controller and announce to bootcode that driver is present. */ 1323 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1324 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1325 __FILE__, __LINE__); 1326 rc = ENXIO; 1327 goto bce_attach_fail; 1328 } 1329 1330 /* Initialize the controller. */ 1331 if (bce_chipinit(sc)) { 1332 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1333 __FILE__, __LINE__); 1334 rc = ENXIO; 1335 goto bce_attach_fail; 1336 } 1337 1338 /* Perform NVRAM test. */ 1339 if (bce_nvram_test(sc)) { 1340 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1341 __FILE__, __LINE__); 1342 rc = ENXIO; 1343 goto bce_attach_fail; 1344 } 1345 1346 /* Fetch the permanent Ethernet MAC address. */ 1347 bce_get_mac_addr(sc); 1348 1349 /* Update statistics once every second. */ 1350 sc->bce_stats_ticks = 1000000 & 0xffff00; 1351 1352 /* Store data needed by PHY driver for backplane applications */ 1353 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1354 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1355 1356 /* Allocate DMA memory resources. */ 1357 if (bce_dma_alloc(dev)) { 1358 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1359 __FILE__, __LINE__); 1360 rc = ENXIO; 1361 goto bce_attach_fail; 1362 } 1363 1364 /* Allocate an ifnet structure. */ 1365 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1366 if (ifp == NULL) { 1367 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1368 __FILE__, __LINE__); 1369 rc = ENXIO; 1370 goto bce_attach_fail; 1371 } 1372 1373 /* Initialize the ifnet interface. */ 1374 if_setsoftc(ifp, sc); 1375 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1376 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1377 if_setioctlfn(ifp, bce_ioctl); 1378 if_setstartfn(ifp, bce_start); 1379 if_setgetcounterfn(ifp, bce_get_counter); 1380 if_setinitfn(ifp, bce_init); 1381 if_setmtu(ifp, ETHERMTU); 1382 1383 if (bce_tso_enable) { 1384 if_sethwassist(ifp, BCE_IF_HWASSIST | CSUM_TSO); 1385 if_setcapabilities(ifp, BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1386 IFCAP_VLAN_HWTSO); 1387 } else { 1388 if_sethwassist(ifp, BCE_IF_HWASSIST); 1389 if_setcapabilities(ifp, BCE_IF_CAPABILITIES); 1390 } 1391 1392 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1393 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE, 0); 1394 1395 if_setcapenable(ifp, if_getcapabilities(ifp)); 1396 1397 /* 1398 * Assume standard mbuf sizes for buffer allocation. 1399 * This may change later if the MTU size is set to 1400 * something other than 1500. 1401 */ 1402 bce_get_rx_buffer_sizes(sc, 1403 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1404 1405 /* Recalculate our buffer allocation sizes. */ 1406 if_setsendqlen(ifp, USABLE_TX_BD_ALLOC); 1407 if_setsendqready(ifp); 1408 1409 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1410 if_setbaudrate(ifp, IF_Mbps(2500ULL)); 1411 else 1412 if_setbaudrate(ifp, IF_Mbps(1000)); 1413 1414 /* Handle any special PHY initialization for SerDes PHYs. */ 1415 bce_init_media(sc); 1416 1417 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 1418 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd, 1419 bce_ifmedia_sts); 1420 /* 1421 * We can't manually override remote PHY's link and assume 1422 * PHY port configuration(Fiber or TP) is not changed after 1423 * device attach. This may not be correct though. 1424 */ 1425 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) { 1426 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 1427 ifmedia_add(&sc->bce_ifmedia, 1428 IFM_ETHER | IFM_2500_SX, 0, NULL); 1429 ifmedia_add(&sc->bce_ifmedia, 1430 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL); 1431 } 1432 ifmedia_add(&sc->bce_ifmedia, 1433 IFM_ETHER | IFM_1000_SX, 0, NULL); 1434 ifmedia_add(&sc->bce_ifmedia, 1435 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1436 } else { 1437 ifmedia_add(&sc->bce_ifmedia, 1438 IFM_ETHER | IFM_10_T, 0, NULL); 1439 ifmedia_add(&sc->bce_ifmedia, 1440 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1441 ifmedia_add(&sc->bce_ifmedia, 1442 IFM_ETHER | IFM_100_TX, 0, NULL); 1443 ifmedia_add(&sc->bce_ifmedia, 1444 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1445 ifmedia_add(&sc->bce_ifmedia, 1446 IFM_ETHER | IFM_1000_T, 0, NULL); 1447 ifmedia_add(&sc->bce_ifmedia, 1448 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1449 } 1450 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1451 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO); 1452 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media; 1453 } else { 1454 /* MII child bus by attaching the PHY. */ 1455 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1456 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1457 MII_OFFSET_ANY, MIIF_DOPAUSE); 1458 if (rc != 0) { 1459 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1460 __LINE__); 1461 goto bce_attach_fail; 1462 } 1463 } 1464 1465 /* Attach to the Ethernet interface list. */ 1466 ether_ifattach(ifp, sc->eaddr); 1467 1468 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1469 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1470 1471 /* Hookup IRQ last. */ 1472 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1473 NULL, bce_intr, sc, &sc->bce_intrhand); 1474 1475 if (rc) { 1476 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1477 __FILE__, __LINE__); 1478 bce_detach(dev); 1479 goto bce_attach_exit; 1480 } 1481 1482 /* 1483 * At this point we've acquired all the resources 1484 * we need to run so there's no turning back, we're 1485 * cleared for launch. 1486 */ 1487 1488 /* Print some important debugging info. */ 1489 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1490 1491 /* Add the supported sysctls to the kernel. */ 1492 bce_add_sysctls(sc); 1493 1494 BCE_LOCK(sc); 1495 1496 /* 1497 * The chip reset earlier notified the bootcode that 1498 * a driver is present. We now need to start our pulse 1499 * routine so that the bootcode is reminded that we're 1500 * still running. 1501 */ 1502 bce_pulse(sc); 1503 1504 bce_mgmt_init_locked(sc); 1505 BCE_UNLOCK(sc); 1506 1507 /* Finally, print some useful adapter info */ 1508 bce_print_adapter_info(sc); 1509 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1510 __FUNCTION__, sc); 1511 1512 goto bce_attach_exit; 1513 1514 bce_attach_fail: 1515 bce_release_resources(sc); 1516 1517 bce_attach_exit: 1518 1519 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1520 1521 return(rc); 1522 } 1523 1524 /****************************************************************************/ 1525 /* Device detach function. */ 1526 /* */ 1527 /* Stops the controller, resets the controller, and releases resources. */ 1528 /* */ 1529 /* Returns: */ 1530 /* 0 on success, positive value on failure. */ 1531 /****************************************************************************/ 1532 static int 1533 bce_detach(device_t dev) 1534 { 1535 struct bce_softc *sc = device_get_softc(dev); 1536 if_t ifp; 1537 u32 msg; 1538 1539 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1540 1541 ifp = sc->bce_ifp; 1542 1543 /* Stop and reset the controller. */ 1544 BCE_LOCK(sc); 1545 1546 /* Stop the pulse so the bootcode can go to driver absent state. */ 1547 callout_stop(&sc->bce_pulse_callout); 1548 1549 bce_stop(sc); 1550 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1551 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1552 else 1553 msg = BCE_DRV_MSG_CODE_UNLOAD; 1554 bce_reset(sc, msg); 1555 1556 BCE_UNLOCK(sc); 1557 1558 ether_ifdetach(ifp); 1559 1560 /* If we have a child device on the MII bus remove it too. */ 1561 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1562 ifmedia_removeall(&sc->bce_ifmedia); 1563 else { 1564 bus_generic_detach(dev); 1565 device_delete_child(dev, sc->bce_miibus); 1566 } 1567 1568 /* Release all remaining resources. */ 1569 bce_release_resources(sc); 1570 1571 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1572 1573 return(0); 1574 } 1575 1576 /****************************************************************************/ 1577 /* Device shutdown function. */ 1578 /* */ 1579 /* Stops and resets the controller. */ 1580 /* */ 1581 /* Returns: */ 1582 /* 0 on success, positive value on failure. */ 1583 /****************************************************************************/ 1584 static int 1585 bce_shutdown(device_t dev) 1586 { 1587 struct bce_softc *sc = device_get_softc(dev); 1588 u32 msg; 1589 1590 DBENTER(BCE_VERBOSE); 1591 1592 BCE_LOCK(sc); 1593 bce_stop(sc); 1594 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1595 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1596 else 1597 msg = BCE_DRV_MSG_CODE_UNLOAD; 1598 bce_reset(sc, msg); 1599 BCE_UNLOCK(sc); 1600 1601 DBEXIT(BCE_VERBOSE); 1602 1603 return (0); 1604 } 1605 1606 #ifdef BCE_DEBUG 1607 /****************************************************************************/ 1608 /* Register read. */ 1609 /* */ 1610 /* Returns: */ 1611 /* The value of the register. */ 1612 /****************************************************************************/ 1613 static u32 1614 bce_reg_rd(struct bce_softc *sc, u32 offset) 1615 { 1616 u32 val = REG_RD(sc, offset); 1617 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1618 __FUNCTION__, offset, val); 1619 return val; 1620 } 1621 1622 /****************************************************************************/ 1623 /* Register write (16 bit). */ 1624 /* */ 1625 /* Returns: */ 1626 /* Nothing. */ 1627 /****************************************************************************/ 1628 static void 1629 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1630 { 1631 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1632 __FUNCTION__, offset, val); 1633 REG_WR16(sc, offset, val); 1634 } 1635 1636 /****************************************************************************/ 1637 /* Register write. */ 1638 /* */ 1639 /* Returns: */ 1640 /* Nothing. */ 1641 /****************************************************************************/ 1642 static void 1643 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1644 { 1645 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1646 __FUNCTION__, offset, val); 1647 REG_WR(sc, offset, val); 1648 } 1649 #endif 1650 1651 /****************************************************************************/ 1652 /* Indirect register read. */ 1653 /* */ 1654 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1655 /* configuration space. Using this mechanism avoids issues with posted */ 1656 /* reads but is much slower than memory-mapped I/O. */ 1657 /* */ 1658 /* Returns: */ 1659 /* The value of the register. */ 1660 /****************************************************************************/ 1661 static u32 1662 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1663 { 1664 device_t dev; 1665 dev = sc->bce_dev; 1666 1667 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1668 #ifdef BCE_DEBUG 1669 { 1670 u32 val; 1671 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1672 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1673 __FUNCTION__, offset, val); 1674 return val; 1675 } 1676 #else 1677 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1678 #endif 1679 } 1680 1681 /****************************************************************************/ 1682 /* Indirect register write. */ 1683 /* */ 1684 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1685 /* configuration space. Using this mechanism avoids issues with posted */ 1686 /* writes but is muchh slower than memory-mapped I/O. */ 1687 /* */ 1688 /* Returns: */ 1689 /* Nothing. */ 1690 /****************************************************************************/ 1691 static void 1692 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1693 { 1694 device_t dev; 1695 dev = sc->bce_dev; 1696 1697 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1698 __FUNCTION__, offset, val); 1699 1700 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1701 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1702 } 1703 1704 /****************************************************************************/ 1705 /* Shared memory write. */ 1706 /* */ 1707 /* Writes NetXtreme II shared memory region. */ 1708 /* */ 1709 /* Returns: */ 1710 /* Nothing. */ 1711 /****************************************************************************/ 1712 static void 1713 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1714 { 1715 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1716 "0x%08X\n", __FUNCTION__, val, offset); 1717 1718 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1719 } 1720 1721 /****************************************************************************/ 1722 /* Shared memory read. */ 1723 /* */ 1724 /* Reads NetXtreme II shared memory region. */ 1725 /* */ 1726 /* Returns: */ 1727 /* The 32 bit value read. */ 1728 /****************************************************************************/ 1729 static u32 1730 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1731 { 1732 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1733 1734 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1735 "0x%08X\n", __FUNCTION__, val, offset); 1736 1737 return val; 1738 } 1739 1740 #ifdef BCE_DEBUG 1741 /****************************************************************************/ 1742 /* Context memory read. */ 1743 /* */ 1744 /* The NetXtreme II controller uses context memory to track connection */ 1745 /* information for L2 and higher network protocols. */ 1746 /* */ 1747 /* Returns: */ 1748 /* The requested 32 bit value of context memory. */ 1749 /****************************************************************************/ 1750 static u32 1751 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1752 { 1753 u32 idx, offset, retry_cnt = 5, val; 1754 1755 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1756 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1757 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1758 1759 offset = ctx_offset + cid_addr; 1760 1761 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1762 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1763 1764 for (idx = 0; idx < retry_cnt; idx++) { 1765 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1766 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1767 break; 1768 DELAY(5); 1769 } 1770 1771 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1772 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1773 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1774 __FILE__, __LINE__, cid_addr, ctx_offset); 1775 1776 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1777 } else { 1778 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1779 val = REG_RD(sc, BCE_CTX_DATA); 1780 } 1781 1782 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1783 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1784 1785 return(val); 1786 } 1787 #endif 1788 1789 /****************************************************************************/ 1790 /* Context memory write. */ 1791 /* */ 1792 /* The NetXtreme II controller uses context memory to track connection */ 1793 /* information for L2 and higher network protocols. */ 1794 /* */ 1795 /* Returns: */ 1796 /* Nothing. */ 1797 /****************************************************************************/ 1798 static void 1799 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1800 { 1801 u32 idx, offset = ctx_offset + cid_addr; 1802 u32 val, retry_cnt = 5; 1803 1804 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1805 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1806 1807 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1808 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1809 __FUNCTION__, cid_addr)); 1810 1811 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1812 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1813 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1814 1815 for (idx = 0; idx < retry_cnt; idx++) { 1816 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1817 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1818 break; 1819 DELAY(5); 1820 } 1821 1822 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1823 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1824 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1825 __FILE__, __LINE__, cid_addr, ctx_offset); 1826 1827 } else { 1828 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1829 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1830 } 1831 } 1832 1833 /****************************************************************************/ 1834 /* PHY register read. */ 1835 /* */ 1836 /* Implements register reads on the MII bus. */ 1837 /* */ 1838 /* Returns: */ 1839 /* The value of the register. */ 1840 /****************************************************************************/ 1841 static int 1842 bce_miibus_read_reg(device_t dev, int phy, int reg) 1843 { 1844 struct bce_softc *sc; 1845 u32 val; 1846 int i; 1847 1848 sc = device_get_softc(dev); 1849 1850 /* 1851 * The 5709S PHY is an IEEE Clause 45 PHY 1852 * with special mappings to work with IEEE 1853 * Clause 22 register accesses. 1854 */ 1855 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1856 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1857 reg += 0x10; 1858 } 1859 1860 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1861 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1862 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1863 1864 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1865 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1866 1867 DELAY(40); 1868 } 1869 1870 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1871 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1872 BCE_EMAC_MDIO_COMM_START_BUSY; 1873 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1874 1875 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1876 DELAY(10); 1877 1878 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1879 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1880 DELAY(5); 1881 1882 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1883 val &= BCE_EMAC_MDIO_COMM_DATA; 1884 1885 break; 1886 } 1887 } 1888 1889 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1890 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1891 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1892 val = 0x0; 1893 } else { 1894 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1895 } 1896 1897 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1898 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1899 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1900 1901 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1902 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1903 1904 DELAY(40); 1905 } 1906 1907 DB_PRINT_PHY_REG(reg, val); 1908 return (val & 0xffff); 1909 } 1910 1911 /****************************************************************************/ 1912 /* PHY register write. */ 1913 /* */ 1914 /* Implements register writes on the MII bus. */ 1915 /* */ 1916 /* Returns: */ 1917 /* The value of the register. */ 1918 /****************************************************************************/ 1919 static int 1920 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1921 { 1922 struct bce_softc *sc; 1923 u32 val1; 1924 int i; 1925 1926 sc = device_get_softc(dev); 1927 1928 DB_PRINT_PHY_REG(reg, val); 1929 1930 /* 1931 * The 5709S PHY is an IEEE Clause 45 PHY 1932 * with special mappings to work with IEEE 1933 * Clause 22 register accesses. 1934 */ 1935 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1936 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1937 reg += 0x10; 1938 } 1939 1940 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1941 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1942 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1943 1944 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1945 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1946 1947 DELAY(40); 1948 } 1949 1950 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1951 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1952 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1953 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1954 1955 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1956 DELAY(10); 1957 1958 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1959 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1960 DELAY(5); 1961 break; 1962 } 1963 } 1964 1965 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1966 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1967 __FILE__, __LINE__); 1968 1969 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1970 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1971 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1972 1973 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1974 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1975 1976 DELAY(40); 1977 } 1978 1979 return 0; 1980 } 1981 1982 /****************************************************************************/ 1983 /* MII bus status change. */ 1984 /* */ 1985 /* Called by the MII bus driver when the PHY establishes link to set the */ 1986 /* MAC interface registers. */ 1987 /* */ 1988 /* Returns: */ 1989 /* Nothing. */ 1990 /****************************************************************************/ 1991 static void 1992 bce_miibus_statchg(device_t dev) 1993 { 1994 struct bce_softc *sc; 1995 struct mii_data *mii; 1996 struct ifmediareq ifmr; 1997 int media_active, media_status, val; 1998 1999 sc = device_get_softc(dev); 2000 2001 DBENTER(BCE_VERBOSE_PHY); 2002 2003 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 2004 bzero(&ifmr, sizeof(ifmr)); 2005 bce_ifmedia_sts_rphy(sc, &ifmr); 2006 media_active = ifmr.ifm_active; 2007 media_status = ifmr.ifm_status; 2008 } else { 2009 mii = device_get_softc(sc->bce_miibus); 2010 media_active = mii->mii_media_active; 2011 media_status = mii->mii_media_status; 2012 } 2013 2014 /* Ignore invalid media status. */ 2015 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) != 2016 (IFM_ACTIVE | IFM_AVALID)) 2017 goto bce_miibus_statchg_exit; 2018 2019 val = REG_RD(sc, BCE_EMAC_MODE); 2020 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2021 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2022 BCE_EMAC_MODE_25G); 2023 2024 /* Set MII or GMII interface based on the PHY speed. */ 2025 switch (IFM_SUBTYPE(media_active)) { 2026 case IFM_10_T: 2027 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2028 DBPRINT(sc, BCE_INFO_PHY, 2029 "Enabling 10Mb interface.\n"); 2030 val |= BCE_EMAC_MODE_PORT_MII_10; 2031 break; 2032 } 2033 /* fall-through */ 2034 case IFM_100_TX: 2035 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2036 val |= BCE_EMAC_MODE_PORT_MII; 2037 break; 2038 case IFM_2500_SX: 2039 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2040 val |= BCE_EMAC_MODE_25G; 2041 /* fall-through */ 2042 case IFM_1000_T: 2043 case IFM_1000_SX: 2044 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2045 val |= BCE_EMAC_MODE_PORT_GMII; 2046 break; 2047 default: 2048 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2049 "default GMII interface.\n"); 2050 val |= BCE_EMAC_MODE_PORT_GMII; 2051 } 2052 2053 /* Set half or full duplex based on PHY settings. */ 2054 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) { 2055 DBPRINT(sc, BCE_INFO_PHY, 2056 "Setting Half-Duplex interface.\n"); 2057 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2058 } else 2059 DBPRINT(sc, BCE_INFO_PHY, 2060 "Setting Full-Duplex interface.\n"); 2061 2062 REG_WR(sc, BCE_EMAC_MODE, val); 2063 2064 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) { 2065 DBPRINT(sc, BCE_INFO_PHY, 2066 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2067 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2068 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL; 2069 } else { 2070 DBPRINT(sc, BCE_INFO_PHY, 2071 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2072 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2073 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL; 2074 } 2075 2076 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) { 2077 DBPRINT(sc, BCE_INFO_PHY, 2078 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2079 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2080 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2081 } else { 2082 DBPRINT(sc, BCE_INFO_PHY, 2083 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2084 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2085 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2086 } 2087 2088 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2089 2090 bce_miibus_statchg_exit: 2091 DBEXIT(BCE_VERBOSE_PHY); 2092 } 2093 2094 /****************************************************************************/ 2095 /* Acquire NVRAM lock. */ 2096 /* */ 2097 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2098 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2099 /* for use by the driver. */ 2100 /* */ 2101 /* Returns: */ 2102 /* 0 on success, positive value on failure. */ 2103 /****************************************************************************/ 2104 static int 2105 bce_acquire_nvram_lock(struct bce_softc *sc) 2106 { 2107 u32 val; 2108 int j, rc = 0; 2109 2110 DBENTER(BCE_VERBOSE_NVRAM); 2111 2112 /* Request access to the flash interface. */ 2113 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2114 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2115 val = REG_RD(sc, BCE_NVM_SW_ARB); 2116 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2117 break; 2118 2119 DELAY(5); 2120 } 2121 2122 if (j >= NVRAM_TIMEOUT_COUNT) { 2123 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2124 rc = EBUSY; 2125 } 2126 2127 DBEXIT(BCE_VERBOSE_NVRAM); 2128 return (rc); 2129 } 2130 2131 /****************************************************************************/ 2132 /* Release NVRAM lock. */ 2133 /* */ 2134 /* When the caller is finished accessing NVRAM the lock must be released. */ 2135 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2136 /* for use by the driver. */ 2137 /* */ 2138 /* Returns: */ 2139 /* 0 on success, positive value on failure. */ 2140 /****************************************************************************/ 2141 static int 2142 bce_release_nvram_lock(struct bce_softc *sc) 2143 { 2144 u32 val; 2145 int j, rc = 0; 2146 2147 DBENTER(BCE_VERBOSE_NVRAM); 2148 2149 /* 2150 * Relinquish nvram interface. 2151 */ 2152 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2153 2154 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2155 val = REG_RD(sc, BCE_NVM_SW_ARB); 2156 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2157 break; 2158 2159 DELAY(5); 2160 } 2161 2162 if (j >= NVRAM_TIMEOUT_COUNT) { 2163 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2164 rc = EBUSY; 2165 } 2166 2167 DBEXIT(BCE_VERBOSE_NVRAM); 2168 return (rc); 2169 } 2170 2171 #ifdef BCE_NVRAM_WRITE_SUPPORT 2172 /****************************************************************************/ 2173 /* Enable NVRAM write access. */ 2174 /* */ 2175 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2176 /* */ 2177 /* Returns: */ 2178 /* 0 on success, positive value on failure. */ 2179 /****************************************************************************/ 2180 static int 2181 bce_enable_nvram_write(struct bce_softc *sc) 2182 { 2183 u32 val; 2184 int rc = 0; 2185 2186 DBENTER(BCE_VERBOSE_NVRAM); 2187 2188 val = REG_RD(sc, BCE_MISC_CFG); 2189 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2190 2191 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2192 int j; 2193 2194 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2195 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2196 2197 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2198 DELAY(5); 2199 2200 val = REG_RD(sc, BCE_NVM_COMMAND); 2201 if (val & BCE_NVM_COMMAND_DONE) 2202 break; 2203 } 2204 2205 if (j >= NVRAM_TIMEOUT_COUNT) { 2206 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2207 rc = EBUSY; 2208 } 2209 } 2210 2211 DBENTER(BCE_VERBOSE_NVRAM); 2212 return (rc); 2213 } 2214 2215 /****************************************************************************/ 2216 /* Disable NVRAM write access. */ 2217 /* */ 2218 /* When the caller is finished writing to NVRAM write access must be */ 2219 /* disabled. */ 2220 /* */ 2221 /* Returns: */ 2222 /* Nothing. */ 2223 /****************************************************************************/ 2224 static void 2225 bce_disable_nvram_write(struct bce_softc *sc) 2226 { 2227 u32 val; 2228 2229 DBENTER(BCE_VERBOSE_NVRAM); 2230 2231 val = REG_RD(sc, BCE_MISC_CFG); 2232 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2233 2234 DBEXIT(BCE_VERBOSE_NVRAM); 2235 2236 } 2237 #endif 2238 2239 /****************************************************************************/ 2240 /* Enable NVRAM access. */ 2241 /* */ 2242 /* Before accessing NVRAM for read or write operations the caller must */ 2243 /* enabled NVRAM access. */ 2244 /* */ 2245 /* Returns: */ 2246 /* Nothing. */ 2247 /****************************************************************************/ 2248 static void 2249 bce_enable_nvram_access(struct bce_softc *sc) 2250 { 2251 u32 val; 2252 2253 DBENTER(BCE_VERBOSE_NVRAM); 2254 2255 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2256 /* Enable both bits, even on read. */ 2257 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2258 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2259 2260 DBEXIT(BCE_VERBOSE_NVRAM); 2261 } 2262 2263 /****************************************************************************/ 2264 /* Disable NVRAM access. */ 2265 /* */ 2266 /* When the caller is finished accessing NVRAM access must be disabled. */ 2267 /* */ 2268 /* Returns: */ 2269 /* Nothing. */ 2270 /****************************************************************************/ 2271 static void 2272 bce_disable_nvram_access(struct bce_softc *sc) 2273 { 2274 u32 val; 2275 2276 DBENTER(BCE_VERBOSE_NVRAM); 2277 2278 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2279 2280 /* Disable both bits, even after read. */ 2281 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2282 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2283 2284 DBEXIT(BCE_VERBOSE_NVRAM); 2285 } 2286 2287 #ifdef BCE_NVRAM_WRITE_SUPPORT 2288 /****************************************************************************/ 2289 /* Erase NVRAM page before writing. */ 2290 /* */ 2291 /* Non-buffered flash parts require that a page be erased before it is */ 2292 /* written. */ 2293 /* */ 2294 /* Returns: */ 2295 /* 0 on success, positive value on failure. */ 2296 /****************************************************************************/ 2297 static int 2298 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2299 { 2300 u32 cmd; 2301 int j, rc = 0; 2302 2303 DBENTER(BCE_VERBOSE_NVRAM); 2304 2305 /* Buffered flash doesn't require an erase. */ 2306 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2307 goto bce_nvram_erase_page_exit; 2308 2309 /* Build an erase command. */ 2310 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2311 BCE_NVM_COMMAND_DOIT; 2312 2313 /* 2314 * Clear the DONE bit separately, set the NVRAM address to erase, 2315 * and issue the erase command. 2316 */ 2317 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2318 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2319 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2320 2321 /* Wait for completion. */ 2322 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2323 u32 val; 2324 2325 DELAY(5); 2326 2327 val = REG_RD(sc, BCE_NVM_COMMAND); 2328 if (val & BCE_NVM_COMMAND_DONE) 2329 break; 2330 } 2331 2332 if (j >= NVRAM_TIMEOUT_COUNT) { 2333 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2334 rc = EBUSY; 2335 } 2336 2337 bce_nvram_erase_page_exit: 2338 DBEXIT(BCE_VERBOSE_NVRAM); 2339 return (rc); 2340 } 2341 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2342 2343 /****************************************************************************/ 2344 /* Read a dword (32 bits) from NVRAM. */ 2345 /* */ 2346 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2347 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2348 /* */ 2349 /* Returns: */ 2350 /* 0 on success and the 32 bit value read, positive value on failure. */ 2351 /****************************************************************************/ 2352 static int 2353 bce_nvram_read_dword(struct bce_softc *sc, 2354 u32 offset, u8 *ret_val, u32 cmd_flags) 2355 { 2356 u32 cmd; 2357 int i, rc = 0; 2358 2359 DBENTER(BCE_EXTREME_NVRAM); 2360 2361 /* Build the command word. */ 2362 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2363 2364 /* Calculate the offset for buffered flash if translation is used. */ 2365 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2366 offset = ((offset / sc->bce_flash_info->page_size) << 2367 sc->bce_flash_info->page_bits) + 2368 (offset % sc->bce_flash_info->page_size); 2369 } 2370 2371 /* 2372 * Clear the DONE bit separately, set the address to read, 2373 * and issue the read. 2374 */ 2375 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2376 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2377 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2378 2379 /* Wait for completion. */ 2380 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2381 u32 val; 2382 2383 DELAY(5); 2384 2385 val = REG_RD(sc, BCE_NVM_COMMAND); 2386 if (val & BCE_NVM_COMMAND_DONE) { 2387 val = REG_RD(sc, BCE_NVM_READ); 2388 2389 val = bce_be32toh(val); 2390 memcpy(ret_val, &val, 4); 2391 break; 2392 } 2393 } 2394 2395 /* Check for errors. */ 2396 if (i >= NVRAM_TIMEOUT_COUNT) { 2397 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2398 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2399 rc = EBUSY; 2400 } 2401 2402 DBEXIT(BCE_EXTREME_NVRAM); 2403 return(rc); 2404 } 2405 2406 #ifdef BCE_NVRAM_WRITE_SUPPORT 2407 /****************************************************************************/ 2408 /* Write a dword (32 bits) to NVRAM. */ 2409 /* */ 2410 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2411 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2412 /* enabled NVRAM write access. */ 2413 /* */ 2414 /* Returns: */ 2415 /* 0 on success, positive value on failure. */ 2416 /****************************************************************************/ 2417 static int 2418 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2419 u32 cmd_flags) 2420 { 2421 u32 cmd, val32; 2422 int j, rc = 0; 2423 2424 DBENTER(BCE_VERBOSE_NVRAM); 2425 2426 /* Build the command word. */ 2427 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2428 2429 /* Calculate the offset for buffered flash if translation is used. */ 2430 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2431 offset = ((offset / sc->bce_flash_info->page_size) << 2432 sc->bce_flash_info->page_bits) + 2433 (offset % sc->bce_flash_info->page_size); 2434 } 2435 2436 /* 2437 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2438 * set the NVRAM address to write, and issue the write command 2439 */ 2440 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2441 memcpy(&val32, val, 4); 2442 val32 = htobe32(val32); 2443 REG_WR(sc, BCE_NVM_WRITE, val32); 2444 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2445 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2446 2447 /* Wait for completion. */ 2448 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2449 DELAY(5); 2450 2451 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2452 break; 2453 } 2454 if (j >= NVRAM_TIMEOUT_COUNT) { 2455 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2456 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2457 rc = EBUSY; 2458 } 2459 2460 DBEXIT(BCE_VERBOSE_NVRAM); 2461 return (rc); 2462 } 2463 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2464 2465 /****************************************************************************/ 2466 /* Initialize NVRAM access. */ 2467 /* */ 2468 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2469 /* access that device. */ 2470 /* */ 2471 /* Returns: */ 2472 /* 0 on success, positive value on failure. */ 2473 /****************************************************************************/ 2474 static int 2475 bce_init_nvram(struct bce_softc *sc) 2476 { 2477 u32 val; 2478 int j, entry_count, rc = 0; 2479 const struct flash_spec *flash; 2480 2481 DBENTER(BCE_VERBOSE_NVRAM); 2482 2483 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2484 sc->bce_flash_info = &flash_5709; 2485 goto bce_init_nvram_get_flash_size; 2486 } 2487 2488 /* Determine the selected interface. */ 2489 val = REG_RD(sc, BCE_NVM_CFG1); 2490 2491 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2492 2493 /* 2494 * Flash reconfiguration is required to support additional 2495 * NVRAM devices not directly supported in hardware. 2496 * Check if the flash interface was reconfigured 2497 * by the bootcode. 2498 */ 2499 2500 if (val & 0x40000000) { 2501 /* Flash interface reconfigured by bootcode. */ 2502 2503 DBPRINT(sc,BCE_INFO_LOAD, 2504 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2505 2506 for (j = 0, flash = &flash_table[0]; j < entry_count; 2507 j++, flash++) { 2508 if ((val & FLASH_BACKUP_STRAP_MASK) == 2509 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2510 sc->bce_flash_info = flash; 2511 break; 2512 } 2513 } 2514 } else { 2515 /* Flash interface not yet reconfigured. */ 2516 u32 mask; 2517 2518 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2519 __FUNCTION__); 2520 2521 if (val & (1 << 23)) 2522 mask = FLASH_BACKUP_STRAP_MASK; 2523 else 2524 mask = FLASH_STRAP_MASK; 2525 2526 /* Look for the matching NVRAM device configuration data. */ 2527 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2528 /* Check if the device matches any of the known devices. */ 2529 if ((val & mask) == (flash->strapping & mask)) { 2530 /* Found a device match. */ 2531 sc->bce_flash_info = flash; 2532 2533 /* Request access to the flash interface. */ 2534 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2535 return rc; 2536 2537 /* Reconfigure the flash interface. */ 2538 bce_enable_nvram_access(sc); 2539 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2540 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2541 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2542 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2543 bce_disable_nvram_access(sc); 2544 bce_release_nvram_lock(sc); 2545 2546 break; 2547 } 2548 } 2549 } 2550 2551 /* Check if a matching device was found. */ 2552 if (j == entry_count) { 2553 sc->bce_flash_info = NULL; 2554 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2555 __FILE__, __LINE__); 2556 DBEXIT(BCE_VERBOSE_NVRAM); 2557 return (ENODEV); 2558 } 2559 2560 bce_init_nvram_get_flash_size: 2561 /* Write the flash config data to the shared memory interface. */ 2562 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2563 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2564 if (val) 2565 sc->bce_flash_size = val; 2566 else 2567 sc->bce_flash_size = sc->bce_flash_info->total_size; 2568 2569 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2570 __FUNCTION__, sc->bce_flash_info->name, 2571 sc->bce_flash_info->total_size); 2572 2573 DBEXIT(BCE_VERBOSE_NVRAM); 2574 return rc; 2575 } 2576 2577 /****************************************************************************/ 2578 /* Read an arbitrary range of data from NVRAM. */ 2579 /* */ 2580 /* Prepares the NVRAM interface for access and reads the requested data */ 2581 /* into the supplied buffer. */ 2582 /* */ 2583 /* Returns: */ 2584 /* 0 on success and the data read, positive value on failure. */ 2585 /****************************************************************************/ 2586 static int 2587 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2588 int buf_size) 2589 { 2590 int rc = 0; 2591 u32 cmd_flags, offset32, len32, extra; 2592 2593 DBENTER(BCE_VERBOSE_NVRAM); 2594 2595 if (buf_size == 0) 2596 goto bce_nvram_read_exit; 2597 2598 /* Request access to the flash interface. */ 2599 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2600 goto bce_nvram_read_exit; 2601 2602 /* Enable access to flash interface */ 2603 bce_enable_nvram_access(sc); 2604 2605 len32 = buf_size; 2606 offset32 = offset; 2607 extra = 0; 2608 2609 cmd_flags = 0; 2610 2611 if (offset32 & 3) { 2612 u8 buf[4]; 2613 u32 pre_len; 2614 2615 offset32 &= ~3; 2616 pre_len = 4 - (offset & 3); 2617 2618 if (pre_len >= len32) { 2619 pre_len = len32; 2620 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2621 } 2622 else { 2623 cmd_flags = BCE_NVM_COMMAND_FIRST; 2624 } 2625 2626 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2627 2628 if (rc) 2629 return rc; 2630 2631 memcpy(ret_buf, buf + (offset & 3), pre_len); 2632 2633 offset32 += 4; 2634 ret_buf += pre_len; 2635 len32 -= pre_len; 2636 } 2637 2638 if (len32 & 3) { 2639 extra = 4 - (len32 & 3); 2640 len32 = (len32 + 4) & ~3; 2641 } 2642 2643 if (len32 == 4) { 2644 u8 buf[4]; 2645 2646 if (cmd_flags) 2647 cmd_flags = BCE_NVM_COMMAND_LAST; 2648 else 2649 cmd_flags = BCE_NVM_COMMAND_FIRST | 2650 BCE_NVM_COMMAND_LAST; 2651 2652 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2653 2654 memcpy(ret_buf, buf, 4 - extra); 2655 } 2656 else if (len32 > 0) { 2657 u8 buf[4]; 2658 2659 /* Read the first word. */ 2660 if (cmd_flags) 2661 cmd_flags = 0; 2662 else 2663 cmd_flags = BCE_NVM_COMMAND_FIRST; 2664 2665 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2666 2667 /* Advance to the next dword. */ 2668 offset32 += 4; 2669 ret_buf += 4; 2670 len32 -= 4; 2671 2672 while (len32 > 4 && rc == 0) { 2673 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2674 2675 /* Advance to the next dword. */ 2676 offset32 += 4; 2677 ret_buf += 4; 2678 len32 -= 4; 2679 } 2680 2681 if (rc) 2682 goto bce_nvram_read_locked_exit; 2683 2684 cmd_flags = BCE_NVM_COMMAND_LAST; 2685 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2686 2687 memcpy(ret_buf, buf, 4 - extra); 2688 } 2689 2690 bce_nvram_read_locked_exit: 2691 /* Disable access to flash interface and release the lock. */ 2692 bce_disable_nvram_access(sc); 2693 bce_release_nvram_lock(sc); 2694 2695 bce_nvram_read_exit: 2696 DBEXIT(BCE_VERBOSE_NVRAM); 2697 return rc; 2698 } 2699 2700 #ifdef BCE_NVRAM_WRITE_SUPPORT 2701 /****************************************************************************/ 2702 /* Write an arbitrary range of data from NVRAM. */ 2703 /* */ 2704 /* Prepares the NVRAM interface for write access and writes the requested */ 2705 /* data from the supplied buffer. The caller is responsible for */ 2706 /* calculating any appropriate CRCs. */ 2707 /* */ 2708 /* Returns: */ 2709 /* 0 on success, positive value on failure. */ 2710 /****************************************************************************/ 2711 static int 2712 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2713 int buf_size) 2714 { 2715 u32 written, offset32, len32; 2716 u8 *buf, start[4], end[4]; 2717 int rc = 0; 2718 int align_start, align_end; 2719 2720 DBENTER(BCE_VERBOSE_NVRAM); 2721 2722 buf = data_buf; 2723 offset32 = offset; 2724 len32 = buf_size; 2725 align_start = align_end = 0; 2726 2727 if ((align_start = (offset32 & 3))) { 2728 offset32 &= ~3; 2729 len32 += align_start; 2730 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2731 goto bce_nvram_write_exit; 2732 } 2733 2734 if (len32 & 3) { 2735 if ((len32 > 4) || !align_start) { 2736 align_end = 4 - (len32 & 3); 2737 len32 += align_end; 2738 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2739 end, 4))) { 2740 goto bce_nvram_write_exit; 2741 } 2742 } 2743 } 2744 2745 if (align_start || align_end) { 2746 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2747 if (buf == NULL) { 2748 rc = ENOMEM; 2749 goto bce_nvram_write_exit; 2750 } 2751 2752 if (align_start) { 2753 memcpy(buf, start, 4); 2754 } 2755 2756 if (align_end) { 2757 memcpy(buf + len32 - 4, end, 4); 2758 } 2759 memcpy(buf + align_start, data_buf, buf_size); 2760 } 2761 2762 written = 0; 2763 while ((written < len32) && (rc == 0)) { 2764 u32 page_start, page_end, data_start, data_end; 2765 u32 addr, cmd_flags; 2766 int i; 2767 u8 flash_buffer[264]; 2768 2769 /* Find the page_start addr */ 2770 page_start = offset32 + written; 2771 page_start -= (page_start % sc->bce_flash_info->page_size); 2772 /* Find the page_end addr */ 2773 page_end = page_start + sc->bce_flash_info->page_size; 2774 /* Find the data_start addr */ 2775 data_start = (written == 0) ? offset32 : page_start; 2776 /* Find the data_end addr */ 2777 data_end = (page_end > offset32 + len32) ? 2778 (offset32 + len32) : page_end; 2779 2780 /* Request access to the flash interface. */ 2781 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2782 goto bce_nvram_write_exit; 2783 2784 /* Enable access to flash interface */ 2785 bce_enable_nvram_access(sc); 2786 2787 cmd_flags = BCE_NVM_COMMAND_FIRST; 2788 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2789 int j; 2790 2791 /* Read the whole page into the buffer 2792 * (non-buffer flash only) */ 2793 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2794 if (j == (sc->bce_flash_info->page_size - 4)) { 2795 cmd_flags |= BCE_NVM_COMMAND_LAST; 2796 } 2797 rc = bce_nvram_read_dword(sc, 2798 page_start + j, 2799 &flash_buffer[j], 2800 cmd_flags); 2801 2802 if (rc) 2803 goto bce_nvram_write_locked_exit; 2804 2805 cmd_flags = 0; 2806 } 2807 } 2808 2809 /* Enable writes to flash interface (unlock write-protect) */ 2810 if ((rc = bce_enable_nvram_write(sc)) != 0) 2811 goto bce_nvram_write_locked_exit; 2812 2813 /* Erase the page */ 2814 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2815 goto bce_nvram_write_locked_exit; 2816 2817 /* Re-enable the write again for the actual write */ 2818 bce_enable_nvram_write(sc); 2819 2820 /* Loop to write back the buffer data from page_start to 2821 * data_start */ 2822 i = 0; 2823 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2824 for (addr = page_start; addr < data_start; 2825 addr += 4, i += 4) { 2826 rc = bce_nvram_write_dword(sc, addr, 2827 &flash_buffer[i], cmd_flags); 2828 2829 if (rc != 0) 2830 goto bce_nvram_write_locked_exit; 2831 2832 cmd_flags = 0; 2833 } 2834 } 2835 2836 /* Loop to write the new data from data_start to data_end */ 2837 for (addr = data_start; addr < data_end; addr += 4, i++) { 2838 if ((addr == page_end - 4) || 2839 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2840 (addr == data_end - 4))) { 2841 cmd_flags |= BCE_NVM_COMMAND_LAST; 2842 } 2843 rc = bce_nvram_write_dword(sc, addr, buf, 2844 cmd_flags); 2845 2846 if (rc != 0) 2847 goto bce_nvram_write_locked_exit; 2848 2849 cmd_flags = 0; 2850 buf += 4; 2851 } 2852 2853 /* Loop to write back the buffer data from data_end 2854 * to page_end */ 2855 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2856 for (addr = data_end; addr < page_end; 2857 addr += 4, i += 4) { 2858 if (addr == page_end-4) { 2859 cmd_flags = BCE_NVM_COMMAND_LAST; 2860 } 2861 rc = bce_nvram_write_dword(sc, addr, 2862 &flash_buffer[i], cmd_flags); 2863 2864 if (rc != 0) 2865 goto bce_nvram_write_locked_exit; 2866 2867 cmd_flags = 0; 2868 } 2869 } 2870 2871 /* Disable writes to flash interface (lock write-protect) */ 2872 bce_disable_nvram_write(sc); 2873 2874 /* Disable access to flash interface */ 2875 bce_disable_nvram_access(sc); 2876 bce_release_nvram_lock(sc); 2877 2878 /* Increment written */ 2879 written += data_end - data_start; 2880 } 2881 2882 goto bce_nvram_write_exit; 2883 2884 bce_nvram_write_locked_exit: 2885 bce_disable_nvram_write(sc); 2886 bce_disable_nvram_access(sc); 2887 bce_release_nvram_lock(sc); 2888 2889 bce_nvram_write_exit: 2890 if (align_start || align_end) 2891 free(buf, M_DEVBUF); 2892 2893 DBEXIT(BCE_VERBOSE_NVRAM); 2894 return (rc); 2895 } 2896 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2897 2898 /****************************************************************************/ 2899 /* Verifies that NVRAM is accessible and contains valid data. */ 2900 /* */ 2901 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2902 /* correct. */ 2903 /* */ 2904 /* Returns: */ 2905 /* 0 on success, positive value on failure. */ 2906 /****************************************************************************/ 2907 static int 2908 bce_nvram_test(struct bce_softc *sc) 2909 { 2910 u32 buf[BCE_NVRAM_SIZE / 4]; 2911 u8 *data = (u8 *) buf; 2912 int rc = 0; 2913 u32 magic, csum; 2914 2915 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2916 2917 /* 2918 * Check that the device NVRAM is valid by reading 2919 * the magic value at offset 0. 2920 */ 2921 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2922 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2923 __FILE__, __LINE__); 2924 goto bce_nvram_test_exit; 2925 } 2926 2927 /* 2928 * Verify that offset 0 of the NVRAM contains 2929 * a valid magic number. 2930 */ 2931 magic = bce_be32toh(buf[0]); 2932 if (magic != BCE_NVRAM_MAGIC) { 2933 rc = ENODEV; 2934 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2935 "Expected: 0x%08X, Found: 0x%08X\n", 2936 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2937 goto bce_nvram_test_exit; 2938 } 2939 2940 /* 2941 * Verify that the device NVRAM includes valid 2942 * configuration data. 2943 */ 2944 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2945 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2946 "Information from NVRAM!\n", __FILE__, __LINE__); 2947 goto bce_nvram_test_exit; 2948 } 2949 2950 csum = ether_crc32_le(data, 0x100); 2951 if (csum != BCE_CRC32_RESIDUAL) { 2952 rc = ENODEV; 2953 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2954 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2955 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2956 goto bce_nvram_test_exit; 2957 } 2958 2959 csum = ether_crc32_le(data + 0x100, 0x100); 2960 if (csum != BCE_CRC32_RESIDUAL) { 2961 rc = ENODEV; 2962 BCE_PRINTF("%s(%d): Invalid feature configuration " 2963 "information NVRAM CRC! Expected: 0x%08X, " 2964 "Found: 08%08X\n", __FILE__, __LINE__, 2965 BCE_CRC32_RESIDUAL, csum); 2966 } 2967 2968 bce_nvram_test_exit: 2969 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2970 return rc; 2971 } 2972 2973 /****************************************************************************/ 2974 /* Calculates the size of the buffers to allocate based on the MTU. */ 2975 /* */ 2976 /* Returns: */ 2977 /* Nothing. */ 2978 /****************************************************************************/ 2979 static void 2980 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 2981 { 2982 DBENTER(BCE_VERBOSE_LOAD); 2983 2984 /* Use a single allocation type when header splitting enabled. */ 2985 if (bce_hdr_split == TRUE) { 2986 sc->rx_bd_mbuf_alloc_size = MHLEN; 2987 /* Make sure offset is 16 byte aligned for hardware. */ 2988 sc->rx_bd_mbuf_align_pad = 2989 roundup2(MSIZE - MHLEN, 16) - (MSIZE - MHLEN); 2990 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 2991 sc->rx_bd_mbuf_align_pad; 2992 } else { 2993 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2994 ETHER_CRC_LEN) > MCLBYTES) { 2995 /* Setup for jumbo RX buffer allocations. */ 2996 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 2997 sc->rx_bd_mbuf_align_pad = 2998 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 2999 sc->rx_bd_mbuf_data_len = 3000 sc->rx_bd_mbuf_alloc_size - 3001 sc->rx_bd_mbuf_align_pad; 3002 } else { 3003 /* Setup for standard RX buffer allocations. */ 3004 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3005 sc->rx_bd_mbuf_align_pad = 3006 roundup2(MCLBYTES, 16) - MCLBYTES; 3007 sc->rx_bd_mbuf_data_len = 3008 sc->rx_bd_mbuf_alloc_size - 3009 sc->rx_bd_mbuf_align_pad; 3010 } 3011 } 3012 3013 // DBPRINT(sc, BCE_INFO_LOAD, 3014 DBPRINT(sc, BCE_WARN, 3015 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3016 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3017 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3018 sc->rx_bd_mbuf_align_pad); 3019 3020 DBEXIT(BCE_VERBOSE_LOAD); 3021 } 3022 3023 /****************************************************************************/ 3024 /* Identifies the current media type of the controller and sets the PHY */ 3025 /* address. */ 3026 /* */ 3027 /* Returns: */ 3028 /* Nothing. */ 3029 /****************************************************************************/ 3030 static void 3031 bce_get_media(struct bce_softc *sc) 3032 { 3033 u32 val; 3034 3035 DBENTER(BCE_VERBOSE_PHY); 3036 3037 /* Assume PHY address for copper controllers. */ 3038 sc->bce_phy_addr = 1; 3039 3040 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3041 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3042 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3043 u32 strap; 3044 3045 /* 3046 * The BCM5709S is software configurable 3047 * for Copper or SerDes operation. 3048 */ 3049 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3050 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3051 "for copper.\n"); 3052 goto bce_get_media_exit; 3053 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3054 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3055 "for dual media.\n"); 3056 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3057 goto bce_get_media_exit; 3058 } 3059 3060 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3061 strap = (val & 3062 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3063 else 3064 strap = (val & 3065 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3066 3067 if (pci_get_function(sc->bce_dev) == 0) { 3068 switch (strap) { 3069 case 0x4: 3070 case 0x5: 3071 case 0x6: 3072 DBPRINT(sc, BCE_INFO_LOAD, 3073 "BCM5709 s/w configured for SerDes.\n"); 3074 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3075 break; 3076 default: 3077 DBPRINT(sc, BCE_INFO_LOAD, 3078 "BCM5709 s/w configured for Copper.\n"); 3079 break; 3080 } 3081 } else { 3082 switch (strap) { 3083 case 0x1: 3084 case 0x2: 3085 case 0x4: 3086 DBPRINT(sc, BCE_INFO_LOAD, 3087 "BCM5709 s/w configured for SerDes.\n"); 3088 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3089 break; 3090 default: 3091 DBPRINT(sc, BCE_INFO_LOAD, 3092 "BCM5709 s/w configured for Copper.\n"); 3093 break; 3094 } 3095 } 3096 3097 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3098 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3099 3100 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3101 sc->bce_flags |= BCE_NO_WOL_FLAG; 3102 3103 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3104 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3105 3106 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3107 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3108 sc->bce_phy_addr = 2; 3109 3110 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3111 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3112 sc->bce_phy_flags |= 3113 BCE_PHY_2_5G_CAPABLE_FLAG; 3114 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3115 "capable adapter\n"); 3116 } 3117 } 3118 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3119 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3120 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3121 3122 bce_get_media_exit: 3123 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3124 "Using PHY address %d.\n", sc->bce_phy_addr); 3125 3126 DBEXIT(BCE_VERBOSE_PHY); 3127 } 3128 3129 /****************************************************************************/ 3130 /* Performs PHY initialization required before MII drivers access the */ 3131 /* device. */ 3132 /* */ 3133 /* Returns: */ 3134 /* Nothing. */ 3135 /****************************************************************************/ 3136 static void 3137 bce_init_media(struct bce_softc *sc) 3138 { 3139 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG | 3140 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) { 3141 /* 3142 * Configure 5709S/5716S PHYs to use traditional IEEE 3143 * Clause 22 method. Otherwise we have no way to attach 3144 * the PHY in mii(4) layer. PHY specific configuration 3145 * is done in mii layer. 3146 */ 3147 3148 /* Select auto-negotiation MMD of the PHY. */ 3149 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3150 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3151 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3152 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3153 3154 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3155 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3156 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3157 } 3158 } 3159 3160 /****************************************************************************/ 3161 /* Free any DMA memory owned by the driver. */ 3162 /* */ 3163 /* Scans through each data structure that requires DMA memory and frees */ 3164 /* the memory if allocated. */ 3165 /* */ 3166 /* Returns: */ 3167 /* Nothing. */ 3168 /****************************************************************************/ 3169 static void 3170 bce_dma_free(struct bce_softc *sc) 3171 { 3172 int i; 3173 3174 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3175 3176 /* Free, unmap, and destroy the status block. */ 3177 if (sc->status_block_paddr != 0) { 3178 bus_dmamap_unload( 3179 sc->status_tag, 3180 sc->status_map); 3181 sc->status_block_paddr = 0; 3182 } 3183 3184 if (sc->status_block != NULL) { 3185 bus_dmamem_free( 3186 sc->status_tag, 3187 sc->status_block, 3188 sc->status_map); 3189 sc->status_block = NULL; 3190 } 3191 3192 if (sc->status_tag != NULL) { 3193 bus_dma_tag_destroy(sc->status_tag); 3194 sc->status_tag = NULL; 3195 } 3196 3197 /* Free, unmap, and destroy the statistics block. */ 3198 if (sc->stats_block_paddr != 0) { 3199 bus_dmamap_unload( 3200 sc->stats_tag, 3201 sc->stats_map); 3202 sc->stats_block_paddr = 0; 3203 } 3204 3205 if (sc->stats_block != NULL) { 3206 bus_dmamem_free( 3207 sc->stats_tag, 3208 sc->stats_block, 3209 sc->stats_map); 3210 sc->stats_block = NULL; 3211 } 3212 3213 if (sc->stats_tag != NULL) { 3214 bus_dma_tag_destroy(sc->stats_tag); 3215 sc->stats_tag = NULL; 3216 } 3217 3218 /* Free, unmap and destroy all context memory pages. */ 3219 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3220 for (i = 0; i < sc->ctx_pages; i++ ) { 3221 if (sc->ctx_paddr[i] != 0) { 3222 bus_dmamap_unload( 3223 sc->ctx_tag, 3224 sc->ctx_map[i]); 3225 sc->ctx_paddr[i] = 0; 3226 } 3227 3228 if (sc->ctx_block[i] != NULL) { 3229 bus_dmamem_free( 3230 sc->ctx_tag, 3231 sc->ctx_block[i], 3232 sc->ctx_map[i]); 3233 sc->ctx_block[i] = NULL; 3234 } 3235 } 3236 3237 /* Destroy the context memory tag. */ 3238 if (sc->ctx_tag != NULL) { 3239 bus_dma_tag_destroy(sc->ctx_tag); 3240 sc->ctx_tag = NULL; 3241 } 3242 } 3243 3244 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3245 for (i = 0; i < sc->tx_pages; i++ ) { 3246 if (sc->tx_bd_chain_paddr[i] != 0) { 3247 bus_dmamap_unload( 3248 sc->tx_bd_chain_tag, 3249 sc->tx_bd_chain_map[i]); 3250 sc->tx_bd_chain_paddr[i] = 0; 3251 } 3252 3253 if (sc->tx_bd_chain[i] != NULL) { 3254 bus_dmamem_free( 3255 sc->tx_bd_chain_tag, 3256 sc->tx_bd_chain[i], 3257 sc->tx_bd_chain_map[i]); 3258 sc->tx_bd_chain[i] = NULL; 3259 } 3260 } 3261 3262 /* Destroy the TX buffer descriptor tag. */ 3263 if (sc->tx_bd_chain_tag != NULL) { 3264 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3265 sc->tx_bd_chain_tag = NULL; 3266 } 3267 3268 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3269 for (i = 0; i < sc->rx_pages; i++ ) { 3270 if (sc->rx_bd_chain_paddr[i] != 0) { 3271 bus_dmamap_unload( 3272 sc->rx_bd_chain_tag, 3273 sc->rx_bd_chain_map[i]); 3274 sc->rx_bd_chain_paddr[i] = 0; 3275 } 3276 3277 if (sc->rx_bd_chain[i] != NULL) { 3278 bus_dmamem_free( 3279 sc->rx_bd_chain_tag, 3280 sc->rx_bd_chain[i], 3281 sc->rx_bd_chain_map[i]); 3282 sc->rx_bd_chain[i] = NULL; 3283 } 3284 } 3285 3286 /* Destroy the RX buffer descriptor tag. */ 3287 if (sc->rx_bd_chain_tag != NULL) { 3288 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3289 sc->rx_bd_chain_tag = NULL; 3290 } 3291 3292 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3293 if (bce_hdr_split == TRUE) { 3294 for (i = 0; i < sc->pg_pages; i++ ) { 3295 if (sc->pg_bd_chain_paddr[i] != 0) { 3296 bus_dmamap_unload( 3297 sc->pg_bd_chain_tag, 3298 sc->pg_bd_chain_map[i]); 3299 sc->pg_bd_chain_paddr[i] = 0; 3300 } 3301 3302 if (sc->pg_bd_chain[i] != NULL) { 3303 bus_dmamem_free( 3304 sc->pg_bd_chain_tag, 3305 sc->pg_bd_chain[i], 3306 sc->pg_bd_chain_map[i]); 3307 sc->pg_bd_chain[i] = NULL; 3308 } 3309 } 3310 3311 /* Destroy the page buffer descriptor tag. */ 3312 if (sc->pg_bd_chain_tag != NULL) { 3313 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3314 sc->pg_bd_chain_tag = NULL; 3315 } 3316 } 3317 3318 /* Unload and destroy the TX mbuf maps. */ 3319 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3320 if (sc->tx_mbuf_map[i] != NULL) { 3321 bus_dmamap_unload(sc->tx_mbuf_tag, 3322 sc->tx_mbuf_map[i]); 3323 bus_dmamap_destroy(sc->tx_mbuf_tag, 3324 sc->tx_mbuf_map[i]); 3325 sc->tx_mbuf_map[i] = NULL; 3326 } 3327 } 3328 3329 /* Destroy the TX mbuf tag. */ 3330 if (sc->tx_mbuf_tag != NULL) { 3331 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3332 sc->tx_mbuf_tag = NULL; 3333 } 3334 3335 /* Unload and destroy the RX mbuf maps. */ 3336 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3337 if (sc->rx_mbuf_map[i] != NULL) { 3338 bus_dmamap_unload(sc->rx_mbuf_tag, 3339 sc->rx_mbuf_map[i]); 3340 bus_dmamap_destroy(sc->rx_mbuf_tag, 3341 sc->rx_mbuf_map[i]); 3342 sc->rx_mbuf_map[i] = NULL; 3343 } 3344 } 3345 3346 /* Destroy the RX mbuf tag. */ 3347 if (sc->rx_mbuf_tag != NULL) { 3348 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3349 sc->rx_mbuf_tag = NULL; 3350 } 3351 3352 /* Unload and destroy the page mbuf maps. */ 3353 if (bce_hdr_split == TRUE) { 3354 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3355 if (sc->pg_mbuf_map[i] != NULL) { 3356 bus_dmamap_unload(sc->pg_mbuf_tag, 3357 sc->pg_mbuf_map[i]); 3358 bus_dmamap_destroy(sc->pg_mbuf_tag, 3359 sc->pg_mbuf_map[i]); 3360 sc->pg_mbuf_map[i] = NULL; 3361 } 3362 } 3363 3364 /* Destroy the page mbuf tag. */ 3365 if (sc->pg_mbuf_tag != NULL) { 3366 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3367 sc->pg_mbuf_tag = NULL; 3368 } 3369 } 3370 3371 /* Destroy the parent tag */ 3372 if (sc->parent_tag != NULL) { 3373 bus_dma_tag_destroy(sc->parent_tag); 3374 sc->parent_tag = NULL; 3375 } 3376 3377 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3378 } 3379 3380 /****************************************************************************/ 3381 /* Get DMA memory from the OS. */ 3382 /* */ 3383 /* Validates that the OS has provided DMA buffers in response to a */ 3384 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3385 /* When the callback is used the OS will return 0 for the mapping function */ 3386 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3387 /* failures back to the caller. */ 3388 /* */ 3389 /* Returns: */ 3390 /* Nothing. */ 3391 /****************************************************************************/ 3392 static void 3393 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3394 { 3395 bus_addr_t *busaddr = arg; 3396 3397 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3398 __FUNCTION__, nseg)); 3399 /* Simulate a mapping failure. */ 3400 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3401 error = ENOMEM); 3402 3403 /* ToDo: How to increment debug sim_count variable here? */ 3404 3405 /* Check for an error and signal the caller that an error occurred. */ 3406 if (error) { 3407 *busaddr = 0; 3408 } else { 3409 *busaddr = segs->ds_addr; 3410 } 3411 } 3412 3413 /****************************************************************************/ 3414 /* Allocate any DMA memory needed by the driver. */ 3415 /* */ 3416 /* Allocates DMA memory needed for the various global structures needed by */ 3417 /* hardware. */ 3418 /* */ 3419 /* Memory alignment requirements: */ 3420 /* +-----------------+----------+----------+----------+----------+ */ 3421 /* | | 5706 | 5708 | 5709 | 5716 | */ 3422 /* +-----------------+----------+----------+----------+----------+ */ 3423 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3424 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3425 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3426 /* |PG Buffers | none | none | none | none | */ 3427 /* |TX Buffers | none | none | none | none | */ 3428 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3429 /* |Context Memory | | | | | */ 3430 /* +-----------------+----------+----------+----------+----------+ */ 3431 /* */ 3432 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3433 /* */ 3434 /* Returns: */ 3435 /* 0 for success, positive value for failure. */ 3436 /****************************************************************************/ 3437 static int 3438 bce_dma_alloc(device_t dev) 3439 { 3440 struct bce_softc *sc; 3441 int i, error, rc = 0; 3442 bus_size_t max_size, max_seg_size; 3443 int max_segments; 3444 3445 sc = device_get_softc(dev); 3446 3447 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3448 3449 /* 3450 * Allocate the parent bus DMA tag appropriate for PCI. 3451 */ 3452 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3453 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3454 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3455 &sc->parent_tag)) { 3456 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3457 __FILE__, __LINE__); 3458 rc = ENOMEM; 3459 goto bce_dma_alloc_exit; 3460 } 3461 3462 /* 3463 * Create a DMA tag for the status block, allocate and clear the 3464 * memory, map the memory into DMA space, and fetch the physical 3465 * address of the block. 3466 */ 3467 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3468 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3469 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3470 0, NULL, NULL, &sc->status_tag)) { 3471 BCE_PRINTF("%s(%d): Could not allocate status block " 3472 "DMA tag!\n", __FILE__, __LINE__); 3473 rc = ENOMEM; 3474 goto bce_dma_alloc_exit; 3475 } 3476 3477 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3478 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3479 &sc->status_map)) { 3480 BCE_PRINTF("%s(%d): Could not allocate status block " 3481 "DMA memory!\n", __FILE__, __LINE__); 3482 rc = ENOMEM; 3483 goto bce_dma_alloc_exit; 3484 } 3485 3486 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3487 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3488 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3489 3490 if (error || sc->status_block_paddr == 0) { 3491 BCE_PRINTF("%s(%d): Could not map status block " 3492 "DMA memory!\n", __FILE__, __LINE__); 3493 rc = ENOMEM; 3494 goto bce_dma_alloc_exit; 3495 } 3496 3497 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3498 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3499 3500 /* 3501 * Create a DMA tag for the statistics block, allocate and clear the 3502 * memory, map the memory into DMA space, and fetch the physical 3503 * address of the block. 3504 */ 3505 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3506 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3507 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3508 0, NULL, NULL, &sc->stats_tag)) { 3509 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3510 "DMA tag!\n", __FILE__, __LINE__); 3511 rc = ENOMEM; 3512 goto bce_dma_alloc_exit; 3513 } 3514 3515 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3516 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3517 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3518 "DMA memory!\n", __FILE__, __LINE__); 3519 rc = ENOMEM; 3520 goto bce_dma_alloc_exit; 3521 } 3522 3523 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3524 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3525 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3526 3527 if (error || sc->stats_block_paddr == 0) { 3528 BCE_PRINTF("%s(%d): Could not map statistics block " 3529 "DMA memory!\n", __FILE__, __LINE__); 3530 rc = ENOMEM; 3531 goto bce_dma_alloc_exit; 3532 } 3533 3534 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3535 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3536 3537 /* BCM5709 uses host memory as cache for context memory. */ 3538 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3539 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3540 if (sc->ctx_pages == 0) 3541 sc->ctx_pages = 1; 3542 3543 DBRUNIF((sc->ctx_pages > 512), 3544 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3545 __FILE__, __LINE__, sc->ctx_pages)); 3546 3547 /* 3548 * Create a DMA tag for the context pages, 3549 * allocate and clear the memory, map the 3550 * memory into DMA space, and fetch the 3551 * physical address of the block. 3552 */ 3553 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3554 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3555 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3556 0, NULL, NULL, &sc->ctx_tag)) { 3557 BCE_PRINTF("%s(%d): Could not allocate CTX " 3558 "DMA tag!\n", __FILE__, __LINE__); 3559 rc = ENOMEM; 3560 goto bce_dma_alloc_exit; 3561 } 3562 3563 for (i = 0; i < sc->ctx_pages; i++) { 3564 if(bus_dmamem_alloc(sc->ctx_tag, 3565 (void **)&sc->ctx_block[i], 3566 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3567 &sc->ctx_map[i])) { 3568 BCE_PRINTF("%s(%d): Could not allocate CTX " 3569 "DMA memory!\n", __FILE__, __LINE__); 3570 rc = ENOMEM; 3571 goto bce_dma_alloc_exit; 3572 } 3573 3574 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3575 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3576 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3577 3578 if (error || sc->ctx_paddr[i] == 0) { 3579 BCE_PRINTF("%s(%d): Could not map CTX " 3580 "DMA memory!\n", __FILE__, __LINE__); 3581 rc = ENOMEM; 3582 goto bce_dma_alloc_exit; 3583 } 3584 3585 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3586 "= 0x%jX\n", __FUNCTION__, i, 3587 (uintmax_t) sc->ctx_paddr[i]); 3588 } 3589 } 3590 3591 /* 3592 * Create a DMA tag for the TX buffer descriptor chain, 3593 * allocate and clear the memory, and fetch the 3594 * physical address of the block. 3595 */ 3596 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3597 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3598 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3599 NULL, NULL, &sc->tx_bd_chain_tag)) { 3600 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3601 "chain DMA tag!\n", __FILE__, __LINE__); 3602 rc = ENOMEM; 3603 goto bce_dma_alloc_exit; 3604 } 3605 3606 for (i = 0; i < sc->tx_pages; i++) { 3607 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3608 (void **)&sc->tx_bd_chain[i], 3609 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3610 &sc->tx_bd_chain_map[i])) { 3611 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3612 "chain DMA memory!\n", __FILE__, __LINE__); 3613 rc = ENOMEM; 3614 goto bce_dma_alloc_exit; 3615 } 3616 3617 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3618 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3619 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3620 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3621 3622 if (error || sc->tx_bd_chain_paddr[i] == 0) { 3623 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3624 "chain DMA memory!\n", __FILE__, __LINE__); 3625 rc = ENOMEM; 3626 goto bce_dma_alloc_exit; 3627 } 3628 3629 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3630 "0x%jX\n", __FUNCTION__, i, 3631 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3632 } 3633 3634 /* Check the required size before mapping to conserve resources. */ 3635 if (bce_tso_enable) { 3636 max_size = BCE_TSO_MAX_SIZE; 3637 max_segments = BCE_MAX_SEGMENTS; 3638 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3639 } else { 3640 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3641 max_segments = BCE_MAX_SEGMENTS; 3642 max_seg_size = MCLBYTES; 3643 } 3644 3645 /* Create a DMA tag for TX mbufs. */ 3646 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3647 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3648 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3649 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3650 __FILE__, __LINE__); 3651 rc = ENOMEM; 3652 goto bce_dma_alloc_exit; 3653 } 3654 3655 /* Create DMA maps for the TX mbufs clusters. */ 3656 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3657 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3658 &sc->tx_mbuf_map[i])) { 3659 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3660 "map!\n", __FILE__, __LINE__); 3661 rc = ENOMEM; 3662 goto bce_dma_alloc_exit; 3663 } 3664 } 3665 3666 /* 3667 * Create a DMA tag for the RX buffer descriptor chain, 3668 * allocate and clear the memory, and fetch the physical 3669 * address of the blocks. 3670 */ 3671 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3672 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3673 sc->max_bus_addr, NULL, NULL, 3674 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3675 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3676 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3677 "DMA tag!\n", __FILE__, __LINE__); 3678 rc = ENOMEM; 3679 goto bce_dma_alloc_exit; 3680 } 3681 3682 for (i = 0; i < sc->rx_pages; i++) { 3683 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3684 (void **)&sc->rx_bd_chain[i], 3685 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3686 &sc->rx_bd_chain_map[i])) { 3687 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3688 "chain DMA memory!\n", __FILE__, __LINE__); 3689 rc = ENOMEM; 3690 goto bce_dma_alloc_exit; 3691 } 3692 3693 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3694 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3695 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3696 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3697 3698 if (error || sc->rx_bd_chain_paddr[i] == 0) { 3699 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3700 "chain DMA memory!\n", __FILE__, __LINE__); 3701 rc = ENOMEM; 3702 goto bce_dma_alloc_exit; 3703 } 3704 3705 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3706 "0x%jX\n", __FUNCTION__, i, 3707 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3708 } 3709 3710 /* 3711 * Create a DMA tag for RX mbufs. 3712 */ 3713 if (bce_hdr_split == TRUE) 3714 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3715 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3716 else 3717 max_size = MJUM9BYTES; 3718 3719 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3720 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size); 3721 3722 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3723 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3724 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) { 3725 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3726 __FILE__, __LINE__); 3727 rc = ENOMEM; 3728 goto bce_dma_alloc_exit; 3729 } 3730 3731 /* Create DMA maps for the RX mbuf clusters. */ 3732 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3733 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3734 &sc->rx_mbuf_map[i])) { 3735 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3736 "DMA map!\n", __FILE__, __LINE__); 3737 rc = ENOMEM; 3738 goto bce_dma_alloc_exit; 3739 } 3740 } 3741 3742 if (bce_hdr_split == TRUE) { 3743 /* 3744 * Create a DMA tag for the page buffer descriptor chain, 3745 * allocate and clear the memory, and fetch the physical 3746 * address of the blocks. 3747 */ 3748 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3749 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3750 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3751 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3752 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3753 "chain DMA tag!\n", __FILE__, __LINE__); 3754 rc = ENOMEM; 3755 goto bce_dma_alloc_exit; 3756 } 3757 3758 for (i = 0; i < sc->pg_pages; i++) { 3759 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3760 (void **)&sc->pg_bd_chain[i], 3761 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3762 &sc->pg_bd_chain_map[i])) { 3763 BCE_PRINTF("%s(%d): Could not allocate page " 3764 "descriptor chain DMA memory!\n", 3765 __FILE__, __LINE__); 3766 rc = ENOMEM; 3767 goto bce_dma_alloc_exit; 3768 } 3769 3770 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3771 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3772 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3773 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3774 3775 if (error || sc->pg_bd_chain_paddr[i] == 0) { 3776 BCE_PRINTF("%s(%d): Could not map page descriptor " 3777 "chain DMA memory!\n", __FILE__, __LINE__); 3778 rc = ENOMEM; 3779 goto bce_dma_alloc_exit; 3780 } 3781 3782 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3783 "0x%jX\n", __FUNCTION__, i, 3784 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3785 } 3786 3787 /* 3788 * Create a DMA tag for page mbufs. 3789 */ 3790 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3791 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 3792 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3793 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3794 "DMA tag!\n", __FILE__, __LINE__); 3795 rc = ENOMEM; 3796 goto bce_dma_alloc_exit; 3797 } 3798 3799 /* Create DMA maps for the page mbuf clusters. */ 3800 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3801 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3802 &sc->pg_mbuf_map[i])) { 3803 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3804 "DMA map!\n", __FILE__, __LINE__); 3805 rc = ENOMEM; 3806 goto bce_dma_alloc_exit; 3807 } 3808 } 3809 } 3810 3811 bce_dma_alloc_exit: 3812 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3813 return(rc); 3814 } 3815 3816 /****************************************************************************/ 3817 /* Release all resources used by the driver. */ 3818 /* */ 3819 /* Releases all resources acquired by the driver including interrupts, */ 3820 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3821 /* */ 3822 /* Returns: */ 3823 /* Nothing. */ 3824 /****************************************************************************/ 3825 static void 3826 bce_release_resources(struct bce_softc *sc) 3827 { 3828 device_t dev; 3829 3830 DBENTER(BCE_VERBOSE_RESET); 3831 3832 dev = sc->bce_dev; 3833 3834 bce_dma_free(sc); 3835 3836 if (sc->bce_intrhand != NULL) { 3837 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3838 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3839 } 3840 3841 if (sc->bce_res_irq != NULL) { 3842 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3843 bus_release_resource(dev, SYS_RES_IRQ, 3844 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq); 3845 } 3846 3847 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3848 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3849 pci_release_msi(dev); 3850 } 3851 3852 if (sc->bce_res_mem != NULL) { 3853 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3854 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3855 sc->bce_res_mem); 3856 } 3857 3858 if (sc->bce_ifp != NULL) { 3859 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3860 if_free(sc->bce_ifp); 3861 } 3862 3863 if (mtx_initialized(&sc->bce_mtx)) 3864 BCE_LOCK_DESTROY(sc); 3865 3866 DBEXIT(BCE_VERBOSE_RESET); 3867 } 3868 3869 /****************************************************************************/ 3870 /* Firmware synchronization. */ 3871 /* */ 3872 /* Before performing certain events such as a chip reset, synchronize with */ 3873 /* the firmware first. */ 3874 /* */ 3875 /* Returns: */ 3876 /* 0 for success, positive value for failure. */ 3877 /****************************************************************************/ 3878 static int 3879 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3880 { 3881 int i, rc = 0; 3882 u32 val; 3883 3884 DBENTER(BCE_VERBOSE_RESET); 3885 3886 /* Don't waste any time if we've timed out before. */ 3887 if (sc->bce_fw_timed_out == TRUE) { 3888 rc = EBUSY; 3889 goto bce_fw_sync_exit; 3890 } 3891 3892 /* Increment the message sequence number. */ 3893 sc->bce_fw_wr_seq++; 3894 msg_data |= sc->bce_fw_wr_seq; 3895 3896 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3897 "0x%08X\n", msg_data); 3898 3899 /* Send the message to the bootcode driver mailbox. */ 3900 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3901 3902 /* Wait for the bootcode to acknowledge the message. */ 3903 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3904 /* Check for a response in the bootcode firmware mailbox. */ 3905 val = bce_shmem_rd(sc, BCE_FW_MB); 3906 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3907 break; 3908 DELAY(1000); 3909 } 3910 3911 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3912 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3913 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3914 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3915 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3916 3917 msg_data &= ~BCE_DRV_MSG_CODE; 3918 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3919 3920 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3921 3922 sc->bce_fw_timed_out = TRUE; 3923 rc = EBUSY; 3924 } 3925 3926 bce_fw_sync_exit: 3927 DBEXIT(BCE_VERBOSE_RESET); 3928 return (rc); 3929 } 3930 3931 /****************************************************************************/ 3932 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3933 /* */ 3934 /* Returns: */ 3935 /* Nothing. */ 3936 /****************************************************************************/ 3937 static void 3938 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code, 3939 u32 rv2p_code_len, u32 rv2p_proc) 3940 { 3941 int i; 3942 u32 val; 3943 3944 DBENTER(BCE_VERBOSE_RESET); 3945 3946 /* Set the page size used by RV2P. */ 3947 if (rv2p_proc == RV2P_PROC2) { 3948 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3949 } 3950 3951 for (i = 0; i < rv2p_code_len; i += 8) { 3952 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3953 rv2p_code++; 3954 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3955 rv2p_code++; 3956 3957 if (rv2p_proc == RV2P_PROC1) { 3958 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 3959 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 3960 } 3961 else { 3962 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 3963 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 3964 } 3965 } 3966 3967 /* Reset the processor, un-stall is done later. */ 3968 if (rv2p_proc == RV2P_PROC1) { 3969 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 3970 } 3971 else { 3972 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 3973 } 3974 3975 DBEXIT(BCE_VERBOSE_RESET); 3976 } 3977 3978 /****************************************************************************/ 3979 /* Load RISC processor firmware. */ 3980 /* */ 3981 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 3982 /* associated with a particular processor. */ 3983 /* */ 3984 /* Returns: */ 3985 /* Nothing. */ 3986 /****************************************************************************/ 3987 static void 3988 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 3989 struct fw_info *fw) 3990 { 3991 u32 offset; 3992 3993 DBENTER(BCE_VERBOSE_RESET); 3994 3995 bce_halt_cpu(sc, cpu_reg); 3996 3997 /* Load the Text area. */ 3998 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 3999 if (fw->text) { 4000 int j; 4001 4002 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4003 REG_WR_IND(sc, offset, fw->text[j]); 4004 } 4005 } 4006 4007 /* Load the Data area. */ 4008 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4009 if (fw->data) { 4010 int j; 4011 4012 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4013 REG_WR_IND(sc, offset, fw->data[j]); 4014 } 4015 } 4016 4017 /* Load the SBSS area. */ 4018 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4019 if (fw->sbss) { 4020 int j; 4021 4022 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4023 REG_WR_IND(sc, offset, fw->sbss[j]); 4024 } 4025 } 4026 4027 /* Load the BSS area. */ 4028 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4029 if (fw->bss) { 4030 int j; 4031 4032 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4033 REG_WR_IND(sc, offset, fw->bss[j]); 4034 } 4035 } 4036 4037 /* Load the Read-Only area. */ 4038 offset = cpu_reg->spad_base + 4039 (fw->rodata_addr - cpu_reg->mips_view_base); 4040 if (fw->rodata) { 4041 int j; 4042 4043 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4044 REG_WR_IND(sc, offset, fw->rodata[j]); 4045 } 4046 } 4047 4048 /* Clear the pre-fetch instruction and set the FW start address. */ 4049 REG_WR_IND(sc, cpu_reg->inst, 0); 4050 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4051 4052 DBEXIT(BCE_VERBOSE_RESET); 4053 } 4054 4055 /****************************************************************************/ 4056 /* Starts the RISC processor. */ 4057 /* */ 4058 /* Assumes the CPU starting address has already been set. */ 4059 /* */ 4060 /* Returns: */ 4061 /* Nothing. */ 4062 /****************************************************************************/ 4063 static void 4064 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4065 { 4066 u32 val; 4067 4068 DBENTER(BCE_VERBOSE_RESET); 4069 4070 /* Start the CPU. */ 4071 val = REG_RD_IND(sc, cpu_reg->mode); 4072 val &= ~cpu_reg->mode_value_halt; 4073 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4074 REG_WR_IND(sc, cpu_reg->mode, val); 4075 4076 DBEXIT(BCE_VERBOSE_RESET); 4077 } 4078 4079 /****************************************************************************/ 4080 /* Halts the RISC processor. */ 4081 /* */ 4082 /* Returns: */ 4083 /* Nothing. */ 4084 /****************************************************************************/ 4085 static void 4086 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4087 { 4088 u32 val; 4089 4090 DBENTER(BCE_VERBOSE_RESET); 4091 4092 /* Halt the CPU. */ 4093 val = REG_RD_IND(sc, cpu_reg->mode); 4094 val |= cpu_reg->mode_value_halt; 4095 REG_WR_IND(sc, cpu_reg->mode, val); 4096 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4097 4098 DBEXIT(BCE_VERBOSE_RESET); 4099 } 4100 4101 /****************************************************************************/ 4102 /* Initialize the RX CPU. */ 4103 /* */ 4104 /* Returns: */ 4105 /* Nothing. */ 4106 /****************************************************************************/ 4107 static void 4108 bce_start_rxp_cpu(struct bce_softc *sc) 4109 { 4110 struct cpu_reg cpu_reg; 4111 4112 DBENTER(BCE_VERBOSE_RESET); 4113 4114 cpu_reg.mode = BCE_RXP_CPU_MODE; 4115 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4116 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4117 cpu_reg.state = BCE_RXP_CPU_STATE; 4118 cpu_reg.state_value_clear = 0xffffff; 4119 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4120 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4121 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4122 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4123 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4124 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4125 cpu_reg.mips_view_base = 0x8000000; 4126 4127 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4128 bce_start_cpu(sc, &cpu_reg); 4129 4130 DBEXIT(BCE_VERBOSE_RESET); 4131 } 4132 4133 /****************************************************************************/ 4134 /* Initialize the RX CPU. */ 4135 /* */ 4136 /* Returns: */ 4137 /* Nothing. */ 4138 /****************************************************************************/ 4139 static void 4140 bce_init_rxp_cpu(struct bce_softc *sc) 4141 { 4142 struct cpu_reg cpu_reg; 4143 struct fw_info fw; 4144 4145 DBENTER(BCE_VERBOSE_RESET); 4146 4147 cpu_reg.mode = BCE_RXP_CPU_MODE; 4148 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4149 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4150 cpu_reg.state = BCE_RXP_CPU_STATE; 4151 cpu_reg.state_value_clear = 0xffffff; 4152 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4153 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4154 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4155 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4156 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4157 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4158 cpu_reg.mips_view_base = 0x8000000; 4159 4160 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4161 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4162 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4163 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4164 fw.start_addr = bce_RXP_b09FwStartAddr; 4165 4166 fw.text_addr = bce_RXP_b09FwTextAddr; 4167 fw.text_len = bce_RXP_b09FwTextLen; 4168 fw.text_index = 0; 4169 fw.text = bce_RXP_b09FwText; 4170 4171 fw.data_addr = bce_RXP_b09FwDataAddr; 4172 fw.data_len = bce_RXP_b09FwDataLen; 4173 fw.data_index = 0; 4174 fw.data = bce_RXP_b09FwData; 4175 4176 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4177 fw.sbss_len = bce_RXP_b09FwSbssLen; 4178 fw.sbss_index = 0; 4179 fw.sbss = bce_RXP_b09FwSbss; 4180 4181 fw.bss_addr = bce_RXP_b09FwBssAddr; 4182 fw.bss_len = bce_RXP_b09FwBssLen; 4183 fw.bss_index = 0; 4184 fw.bss = bce_RXP_b09FwBss; 4185 4186 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4187 fw.rodata_len = bce_RXP_b09FwRodataLen; 4188 fw.rodata_index = 0; 4189 fw.rodata = bce_RXP_b09FwRodata; 4190 } else { 4191 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4192 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4193 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4194 fw.start_addr = bce_RXP_b06FwStartAddr; 4195 4196 fw.text_addr = bce_RXP_b06FwTextAddr; 4197 fw.text_len = bce_RXP_b06FwTextLen; 4198 fw.text_index = 0; 4199 fw.text = bce_RXP_b06FwText; 4200 4201 fw.data_addr = bce_RXP_b06FwDataAddr; 4202 fw.data_len = bce_RXP_b06FwDataLen; 4203 fw.data_index = 0; 4204 fw.data = bce_RXP_b06FwData; 4205 4206 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4207 fw.sbss_len = bce_RXP_b06FwSbssLen; 4208 fw.sbss_index = 0; 4209 fw.sbss = bce_RXP_b06FwSbss; 4210 4211 fw.bss_addr = bce_RXP_b06FwBssAddr; 4212 fw.bss_len = bce_RXP_b06FwBssLen; 4213 fw.bss_index = 0; 4214 fw.bss = bce_RXP_b06FwBss; 4215 4216 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4217 fw.rodata_len = bce_RXP_b06FwRodataLen; 4218 fw.rodata_index = 0; 4219 fw.rodata = bce_RXP_b06FwRodata; 4220 } 4221 4222 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4223 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4224 4225 /* Delay RXP start until initialization is complete. */ 4226 4227 DBEXIT(BCE_VERBOSE_RESET); 4228 } 4229 4230 /****************************************************************************/ 4231 /* Initialize the TX CPU. */ 4232 /* */ 4233 /* Returns: */ 4234 /* Nothing. */ 4235 /****************************************************************************/ 4236 static void 4237 bce_init_txp_cpu(struct bce_softc *sc) 4238 { 4239 struct cpu_reg cpu_reg; 4240 struct fw_info fw; 4241 4242 DBENTER(BCE_VERBOSE_RESET); 4243 4244 cpu_reg.mode = BCE_TXP_CPU_MODE; 4245 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4246 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4247 cpu_reg.state = BCE_TXP_CPU_STATE; 4248 cpu_reg.state_value_clear = 0xffffff; 4249 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4250 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4251 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4252 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4253 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4254 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4255 cpu_reg.mips_view_base = 0x8000000; 4256 4257 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4258 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4259 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4260 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4261 fw.start_addr = bce_TXP_b09FwStartAddr; 4262 4263 fw.text_addr = bce_TXP_b09FwTextAddr; 4264 fw.text_len = bce_TXP_b09FwTextLen; 4265 fw.text_index = 0; 4266 fw.text = bce_TXP_b09FwText; 4267 4268 fw.data_addr = bce_TXP_b09FwDataAddr; 4269 fw.data_len = bce_TXP_b09FwDataLen; 4270 fw.data_index = 0; 4271 fw.data = bce_TXP_b09FwData; 4272 4273 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4274 fw.sbss_len = bce_TXP_b09FwSbssLen; 4275 fw.sbss_index = 0; 4276 fw.sbss = bce_TXP_b09FwSbss; 4277 4278 fw.bss_addr = bce_TXP_b09FwBssAddr; 4279 fw.bss_len = bce_TXP_b09FwBssLen; 4280 fw.bss_index = 0; 4281 fw.bss = bce_TXP_b09FwBss; 4282 4283 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4284 fw.rodata_len = bce_TXP_b09FwRodataLen; 4285 fw.rodata_index = 0; 4286 fw.rodata = bce_TXP_b09FwRodata; 4287 } else { 4288 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4289 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4290 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4291 fw.start_addr = bce_TXP_b06FwStartAddr; 4292 4293 fw.text_addr = bce_TXP_b06FwTextAddr; 4294 fw.text_len = bce_TXP_b06FwTextLen; 4295 fw.text_index = 0; 4296 fw.text = bce_TXP_b06FwText; 4297 4298 fw.data_addr = bce_TXP_b06FwDataAddr; 4299 fw.data_len = bce_TXP_b06FwDataLen; 4300 fw.data_index = 0; 4301 fw.data = bce_TXP_b06FwData; 4302 4303 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4304 fw.sbss_len = bce_TXP_b06FwSbssLen; 4305 fw.sbss_index = 0; 4306 fw.sbss = bce_TXP_b06FwSbss; 4307 4308 fw.bss_addr = bce_TXP_b06FwBssAddr; 4309 fw.bss_len = bce_TXP_b06FwBssLen; 4310 fw.bss_index = 0; 4311 fw.bss = bce_TXP_b06FwBss; 4312 4313 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4314 fw.rodata_len = bce_TXP_b06FwRodataLen; 4315 fw.rodata_index = 0; 4316 fw.rodata = bce_TXP_b06FwRodata; 4317 } 4318 4319 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4320 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4321 bce_start_cpu(sc, &cpu_reg); 4322 4323 DBEXIT(BCE_VERBOSE_RESET); 4324 } 4325 4326 /****************************************************************************/ 4327 /* Initialize the TPAT CPU. */ 4328 /* */ 4329 /* Returns: */ 4330 /* Nothing. */ 4331 /****************************************************************************/ 4332 static void 4333 bce_init_tpat_cpu(struct bce_softc *sc) 4334 { 4335 struct cpu_reg cpu_reg; 4336 struct fw_info fw; 4337 4338 DBENTER(BCE_VERBOSE_RESET); 4339 4340 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4341 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4342 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4343 cpu_reg.state = BCE_TPAT_CPU_STATE; 4344 cpu_reg.state_value_clear = 0xffffff; 4345 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4346 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4347 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4348 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4349 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4350 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4351 cpu_reg.mips_view_base = 0x8000000; 4352 4353 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4354 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4355 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4356 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4357 fw.start_addr = bce_TPAT_b09FwStartAddr; 4358 4359 fw.text_addr = bce_TPAT_b09FwTextAddr; 4360 fw.text_len = bce_TPAT_b09FwTextLen; 4361 fw.text_index = 0; 4362 fw.text = bce_TPAT_b09FwText; 4363 4364 fw.data_addr = bce_TPAT_b09FwDataAddr; 4365 fw.data_len = bce_TPAT_b09FwDataLen; 4366 fw.data_index = 0; 4367 fw.data = bce_TPAT_b09FwData; 4368 4369 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4370 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4371 fw.sbss_index = 0; 4372 fw.sbss = bce_TPAT_b09FwSbss; 4373 4374 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4375 fw.bss_len = bce_TPAT_b09FwBssLen; 4376 fw.bss_index = 0; 4377 fw.bss = bce_TPAT_b09FwBss; 4378 4379 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4380 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4381 fw.rodata_index = 0; 4382 fw.rodata = bce_TPAT_b09FwRodata; 4383 } else { 4384 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4385 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4386 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4387 fw.start_addr = bce_TPAT_b06FwStartAddr; 4388 4389 fw.text_addr = bce_TPAT_b06FwTextAddr; 4390 fw.text_len = bce_TPAT_b06FwTextLen; 4391 fw.text_index = 0; 4392 fw.text = bce_TPAT_b06FwText; 4393 4394 fw.data_addr = bce_TPAT_b06FwDataAddr; 4395 fw.data_len = bce_TPAT_b06FwDataLen; 4396 fw.data_index = 0; 4397 fw.data = bce_TPAT_b06FwData; 4398 4399 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4400 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4401 fw.sbss_index = 0; 4402 fw.sbss = bce_TPAT_b06FwSbss; 4403 4404 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4405 fw.bss_len = bce_TPAT_b06FwBssLen; 4406 fw.bss_index = 0; 4407 fw.bss = bce_TPAT_b06FwBss; 4408 4409 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4410 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4411 fw.rodata_index = 0; 4412 fw.rodata = bce_TPAT_b06FwRodata; 4413 } 4414 4415 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4416 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4417 bce_start_cpu(sc, &cpu_reg); 4418 4419 DBEXIT(BCE_VERBOSE_RESET); 4420 } 4421 4422 /****************************************************************************/ 4423 /* Initialize the CP CPU. */ 4424 /* */ 4425 /* Returns: */ 4426 /* Nothing. */ 4427 /****************************************************************************/ 4428 static void 4429 bce_init_cp_cpu(struct bce_softc *sc) 4430 { 4431 struct cpu_reg cpu_reg; 4432 struct fw_info fw; 4433 4434 DBENTER(BCE_VERBOSE_RESET); 4435 4436 cpu_reg.mode = BCE_CP_CPU_MODE; 4437 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4438 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4439 cpu_reg.state = BCE_CP_CPU_STATE; 4440 cpu_reg.state_value_clear = 0xffffff; 4441 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4442 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4443 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4444 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4445 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4446 cpu_reg.spad_base = BCE_CP_SCRATCH; 4447 cpu_reg.mips_view_base = 0x8000000; 4448 4449 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4450 fw.ver_major = bce_CP_b09FwReleaseMajor; 4451 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4452 fw.ver_fix = bce_CP_b09FwReleaseFix; 4453 fw.start_addr = bce_CP_b09FwStartAddr; 4454 4455 fw.text_addr = bce_CP_b09FwTextAddr; 4456 fw.text_len = bce_CP_b09FwTextLen; 4457 fw.text_index = 0; 4458 fw.text = bce_CP_b09FwText; 4459 4460 fw.data_addr = bce_CP_b09FwDataAddr; 4461 fw.data_len = bce_CP_b09FwDataLen; 4462 fw.data_index = 0; 4463 fw.data = bce_CP_b09FwData; 4464 4465 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4466 fw.sbss_len = bce_CP_b09FwSbssLen; 4467 fw.sbss_index = 0; 4468 fw.sbss = bce_CP_b09FwSbss; 4469 4470 fw.bss_addr = bce_CP_b09FwBssAddr; 4471 fw.bss_len = bce_CP_b09FwBssLen; 4472 fw.bss_index = 0; 4473 fw.bss = bce_CP_b09FwBss; 4474 4475 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4476 fw.rodata_len = bce_CP_b09FwRodataLen; 4477 fw.rodata_index = 0; 4478 fw.rodata = bce_CP_b09FwRodata; 4479 } else { 4480 fw.ver_major = bce_CP_b06FwReleaseMajor; 4481 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4482 fw.ver_fix = bce_CP_b06FwReleaseFix; 4483 fw.start_addr = bce_CP_b06FwStartAddr; 4484 4485 fw.text_addr = bce_CP_b06FwTextAddr; 4486 fw.text_len = bce_CP_b06FwTextLen; 4487 fw.text_index = 0; 4488 fw.text = bce_CP_b06FwText; 4489 4490 fw.data_addr = bce_CP_b06FwDataAddr; 4491 fw.data_len = bce_CP_b06FwDataLen; 4492 fw.data_index = 0; 4493 fw.data = bce_CP_b06FwData; 4494 4495 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4496 fw.sbss_len = bce_CP_b06FwSbssLen; 4497 fw.sbss_index = 0; 4498 fw.sbss = bce_CP_b06FwSbss; 4499 4500 fw.bss_addr = bce_CP_b06FwBssAddr; 4501 fw.bss_len = bce_CP_b06FwBssLen; 4502 fw.bss_index = 0; 4503 fw.bss = bce_CP_b06FwBss; 4504 4505 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4506 fw.rodata_len = bce_CP_b06FwRodataLen; 4507 fw.rodata_index = 0; 4508 fw.rodata = bce_CP_b06FwRodata; 4509 } 4510 4511 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4512 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4513 bce_start_cpu(sc, &cpu_reg); 4514 4515 DBEXIT(BCE_VERBOSE_RESET); 4516 } 4517 4518 /****************************************************************************/ 4519 /* Initialize the COM CPU. */ 4520 /* */ 4521 /* Returns: */ 4522 /* Nothing. */ 4523 /****************************************************************************/ 4524 static void 4525 bce_init_com_cpu(struct bce_softc *sc) 4526 { 4527 struct cpu_reg cpu_reg; 4528 struct fw_info fw; 4529 4530 DBENTER(BCE_VERBOSE_RESET); 4531 4532 cpu_reg.mode = BCE_COM_CPU_MODE; 4533 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4534 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4535 cpu_reg.state = BCE_COM_CPU_STATE; 4536 cpu_reg.state_value_clear = 0xffffff; 4537 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4538 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4539 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4540 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4541 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4542 cpu_reg.spad_base = BCE_COM_SCRATCH; 4543 cpu_reg.mips_view_base = 0x8000000; 4544 4545 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4546 fw.ver_major = bce_COM_b09FwReleaseMajor; 4547 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4548 fw.ver_fix = bce_COM_b09FwReleaseFix; 4549 fw.start_addr = bce_COM_b09FwStartAddr; 4550 4551 fw.text_addr = bce_COM_b09FwTextAddr; 4552 fw.text_len = bce_COM_b09FwTextLen; 4553 fw.text_index = 0; 4554 fw.text = bce_COM_b09FwText; 4555 4556 fw.data_addr = bce_COM_b09FwDataAddr; 4557 fw.data_len = bce_COM_b09FwDataLen; 4558 fw.data_index = 0; 4559 fw.data = bce_COM_b09FwData; 4560 4561 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4562 fw.sbss_len = bce_COM_b09FwSbssLen; 4563 fw.sbss_index = 0; 4564 fw.sbss = bce_COM_b09FwSbss; 4565 4566 fw.bss_addr = bce_COM_b09FwBssAddr; 4567 fw.bss_len = bce_COM_b09FwBssLen; 4568 fw.bss_index = 0; 4569 fw.bss = bce_COM_b09FwBss; 4570 4571 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4572 fw.rodata_len = bce_COM_b09FwRodataLen; 4573 fw.rodata_index = 0; 4574 fw.rodata = bce_COM_b09FwRodata; 4575 } else { 4576 fw.ver_major = bce_COM_b06FwReleaseMajor; 4577 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4578 fw.ver_fix = bce_COM_b06FwReleaseFix; 4579 fw.start_addr = bce_COM_b06FwStartAddr; 4580 4581 fw.text_addr = bce_COM_b06FwTextAddr; 4582 fw.text_len = bce_COM_b06FwTextLen; 4583 fw.text_index = 0; 4584 fw.text = bce_COM_b06FwText; 4585 4586 fw.data_addr = bce_COM_b06FwDataAddr; 4587 fw.data_len = bce_COM_b06FwDataLen; 4588 fw.data_index = 0; 4589 fw.data = bce_COM_b06FwData; 4590 4591 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4592 fw.sbss_len = bce_COM_b06FwSbssLen; 4593 fw.sbss_index = 0; 4594 fw.sbss = bce_COM_b06FwSbss; 4595 4596 fw.bss_addr = bce_COM_b06FwBssAddr; 4597 fw.bss_len = bce_COM_b06FwBssLen; 4598 fw.bss_index = 0; 4599 fw.bss = bce_COM_b06FwBss; 4600 4601 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4602 fw.rodata_len = bce_COM_b06FwRodataLen; 4603 fw.rodata_index = 0; 4604 fw.rodata = bce_COM_b06FwRodata; 4605 } 4606 4607 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4608 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4609 bce_start_cpu(sc, &cpu_reg); 4610 4611 DBEXIT(BCE_VERBOSE_RESET); 4612 } 4613 4614 /****************************************************************************/ 4615 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4616 /* */ 4617 /* Loads the firmware for each CPU and starts the CPU. */ 4618 /* */ 4619 /* Returns: */ 4620 /* Nothing. */ 4621 /****************************************************************************/ 4622 static void 4623 bce_init_cpus(struct bce_softc *sc) 4624 { 4625 DBENTER(BCE_VERBOSE_RESET); 4626 4627 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4628 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4629 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4630 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4631 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4632 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4633 } else { 4634 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4635 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4636 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4637 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4638 } 4639 4640 } else { 4641 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4642 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4643 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4644 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4645 } 4646 4647 bce_init_rxp_cpu(sc); 4648 bce_init_txp_cpu(sc); 4649 bce_init_tpat_cpu(sc); 4650 bce_init_com_cpu(sc); 4651 bce_init_cp_cpu(sc); 4652 4653 DBEXIT(BCE_VERBOSE_RESET); 4654 } 4655 4656 /****************************************************************************/ 4657 /* Initialize context memory. */ 4658 /* */ 4659 /* Clears the memory associated with each Context ID (CID). */ 4660 /* */ 4661 /* Returns: */ 4662 /* Nothing. */ 4663 /****************************************************************************/ 4664 static int 4665 bce_init_ctx(struct bce_softc *sc) 4666 { 4667 u32 offset, val, vcid_addr; 4668 int i, j, rc, retry_cnt; 4669 4670 rc = 0; 4671 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4672 4673 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4674 retry_cnt = CTX_INIT_RETRY_COUNT; 4675 4676 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4677 4678 /* 4679 * BCM5709 context memory may be cached 4680 * in host memory so prepare the host memory 4681 * for access. 4682 */ 4683 val = BCE_CTX_COMMAND_ENABLED | 4684 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4685 val |= (BCM_PAGE_BITS - 8) << 16; 4686 REG_WR(sc, BCE_CTX_COMMAND, val); 4687 4688 /* Wait for mem init command to complete. */ 4689 for (i = 0; i < retry_cnt; i++) { 4690 val = REG_RD(sc, BCE_CTX_COMMAND); 4691 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4692 break; 4693 DELAY(2); 4694 } 4695 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4696 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4697 __FUNCTION__); 4698 rc = EBUSY; 4699 goto init_ctx_fail; 4700 } 4701 4702 for (i = 0; i < sc->ctx_pages; i++) { 4703 /* Set the physical address of the context memory. */ 4704 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4705 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4706 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4707 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4708 BCE_ADDR_HI(sc->ctx_paddr[i])); 4709 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4710 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4711 4712 /* Verify the context memory write was successful. */ 4713 for (j = 0; j < retry_cnt; j++) { 4714 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4715 if ((val & 4716 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4717 break; 4718 DELAY(5); 4719 } 4720 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4721 BCE_PRINTF("%s(): Failed to initialize " 4722 "context page %d!\n", __FUNCTION__, i); 4723 rc = EBUSY; 4724 goto init_ctx_fail; 4725 } 4726 } 4727 } else { 4728 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4729 4730 /* 4731 * For the 5706/5708, context memory is local to 4732 * the controller, so initialize the controller 4733 * context memory. 4734 */ 4735 4736 vcid_addr = GET_CID_ADDR(96); 4737 while (vcid_addr) { 4738 vcid_addr -= PHY_CTX_SIZE; 4739 4740 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4741 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4742 4743 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4744 CTX_WR(sc, 0x00, offset, 0); 4745 } 4746 4747 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4748 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4749 } 4750 } 4751 init_ctx_fail: 4752 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4753 return (rc); 4754 } 4755 4756 /****************************************************************************/ 4757 /* Fetch the permanent MAC address of the controller. */ 4758 /* */ 4759 /* Returns: */ 4760 /* Nothing. */ 4761 /****************************************************************************/ 4762 static void 4763 bce_get_mac_addr(struct bce_softc *sc) 4764 { 4765 u32 mac_lo = 0, mac_hi = 0; 4766 4767 DBENTER(BCE_VERBOSE_RESET); 4768 4769 /* 4770 * The NetXtreme II bootcode populates various NIC 4771 * power-on and runtime configuration items in a 4772 * shared memory area. The factory configured MAC 4773 * address is available from both NVRAM and the 4774 * shared memory area so we'll read the value from 4775 * shared memory for speed. 4776 */ 4777 4778 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4779 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4780 4781 if ((mac_lo == 0) && (mac_hi == 0)) { 4782 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4783 __FILE__, __LINE__); 4784 } else { 4785 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4786 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4787 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4788 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4789 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4790 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4791 } 4792 4793 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4794 "address = %6D\n", sc->eaddr, ":"); 4795 DBEXIT(BCE_VERBOSE_RESET); 4796 } 4797 4798 /****************************************************************************/ 4799 /* Program the MAC address. */ 4800 /* */ 4801 /* Returns: */ 4802 /* Nothing. */ 4803 /****************************************************************************/ 4804 static void 4805 bce_set_mac_addr(struct bce_softc *sc) 4806 { 4807 u32 val; 4808 u8 *mac_addr = sc->eaddr; 4809 4810 /* ToDo: Add support for setting multiple MAC addresses. */ 4811 4812 DBENTER(BCE_VERBOSE_RESET); 4813 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4814 "%6D\n", sc->eaddr, ":"); 4815 4816 val = (mac_addr[0] << 8) | mac_addr[1]; 4817 4818 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4819 4820 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4821 (mac_addr[4] << 8) | mac_addr[5]; 4822 4823 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4824 4825 DBEXIT(BCE_VERBOSE_RESET); 4826 } 4827 4828 /****************************************************************************/ 4829 /* Stop the controller. */ 4830 /* */ 4831 /* Returns: */ 4832 /* Nothing. */ 4833 /****************************************************************************/ 4834 static void 4835 bce_stop(struct bce_softc *sc) 4836 { 4837 if_t ifp; 4838 4839 DBENTER(BCE_VERBOSE_RESET); 4840 4841 BCE_LOCK_ASSERT(sc); 4842 4843 ifp = sc->bce_ifp; 4844 4845 callout_stop(&sc->bce_tick_callout); 4846 4847 /* Disable the transmit/receive blocks. */ 4848 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4849 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4850 DELAY(20); 4851 4852 bce_disable_intr(sc); 4853 4854 /* Free RX buffers. */ 4855 if (bce_hdr_split == TRUE) { 4856 bce_free_pg_chain(sc); 4857 } 4858 bce_free_rx_chain(sc); 4859 4860 /* Free TX buffers. */ 4861 bce_free_tx_chain(sc); 4862 4863 sc->watchdog_timer = 0; 4864 4865 sc->bce_link_up = FALSE; 4866 4867 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4868 4869 DBEXIT(BCE_VERBOSE_RESET); 4870 } 4871 4872 static int 4873 bce_reset(struct bce_softc *sc, u32 reset_code) 4874 { 4875 u32 emac_mode_save, val; 4876 int i, rc = 0; 4877 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT | 4878 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G; 4879 4880 DBENTER(BCE_VERBOSE_RESET); 4881 4882 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4883 __FUNCTION__, reset_code); 4884 4885 /* 4886 * If ASF/IPMI is operational, then the EMAC Mode register already 4887 * contains appropriate values for the link settings that have 4888 * been auto-negotiated. Resetting the chip will clobber those 4889 * values. Save the important bits so we can restore them after 4890 * the reset. 4891 */ 4892 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask; 4893 4894 /* Wait for pending PCI transactions to complete. */ 4895 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4896 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4897 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4898 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4899 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4900 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4901 DELAY(5); 4902 4903 /* Disable DMA */ 4904 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4905 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4906 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4907 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4908 } 4909 4910 /* Assume bootcode is running. */ 4911 sc->bce_fw_timed_out = FALSE; 4912 sc->bce_drv_cardiac_arrest = FALSE; 4913 4914 /* Give the firmware a chance to prepare for the reset. */ 4915 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4916 if (rc) 4917 goto bce_reset_exit; 4918 4919 /* Set a firmware reminder that this is a soft reset. */ 4920 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4921 4922 /* Dummy read to force the chip to complete all current transactions. */ 4923 val = REG_RD(sc, BCE_MISC_ID); 4924 4925 /* Chip reset. */ 4926 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4927 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4928 REG_RD(sc, BCE_MISC_COMMAND); 4929 DELAY(5); 4930 4931 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4932 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4933 4934 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4935 } else { 4936 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4937 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4938 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4939 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4940 4941 /* Allow up to 30us for reset to complete. */ 4942 for (i = 0; i < 10; i++) { 4943 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 4944 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4945 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 4946 break; 4947 } 4948 DELAY(10); 4949 } 4950 4951 /* Check that reset completed successfully. */ 4952 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4953 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4954 BCE_PRINTF("%s(%d): Reset failed!\n", 4955 __FILE__, __LINE__); 4956 rc = EBUSY; 4957 goto bce_reset_exit; 4958 } 4959 } 4960 4961 /* Make sure byte swapping is properly configured. */ 4962 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 4963 if (val != 0x01020304) { 4964 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 4965 __FILE__, __LINE__); 4966 rc = ENODEV; 4967 goto bce_reset_exit; 4968 } 4969 4970 /* Just completed a reset, assume that firmware is running again. */ 4971 sc->bce_fw_timed_out = FALSE; 4972 sc->bce_drv_cardiac_arrest = FALSE; 4973 4974 /* Wait for the firmware to finish its initialization. */ 4975 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 4976 if (rc) 4977 BCE_PRINTF("%s(%d): Firmware did not complete " 4978 "initialization!\n", __FILE__, __LINE__); 4979 /* Get firmware capabilities. */ 4980 bce_fw_cap_init(sc); 4981 4982 bce_reset_exit: 4983 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */ 4984 if (reset_code == BCE_DRV_MSG_CODE_RESET) { 4985 val = REG_RD(sc, BCE_EMAC_MODE); 4986 val = (val & ~emac_mode_mask) | emac_mode_save; 4987 REG_WR(sc, BCE_EMAC_MODE, val); 4988 } 4989 4990 DBEXIT(BCE_VERBOSE_RESET); 4991 return (rc); 4992 } 4993 4994 static int 4995 bce_chipinit(struct bce_softc *sc) 4996 { 4997 u32 val; 4998 int rc = 0; 4999 5000 DBENTER(BCE_VERBOSE_RESET); 5001 5002 bce_disable_intr(sc); 5003 5004 /* 5005 * Initialize DMA byte/word swapping, configure the number of DMA 5006 * channels and PCI clock compensation delay. 5007 */ 5008 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5009 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5010 #if BYTE_ORDER == BIG_ENDIAN 5011 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5012 #endif 5013 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5014 DMA_READ_CHANS << 12 | 5015 DMA_WRITE_CHANS << 16; 5016 5017 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5018 5019 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5020 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5021 5022 /* 5023 * This setting resolves a problem observed on certain Intel PCI 5024 * chipsets that cannot handle multiple outstanding DMA operations. 5025 * See errata E9_5706A1_65. 5026 */ 5027 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5028 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5029 !(sc->bce_flags & BCE_PCIX_FLAG)) 5030 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5031 5032 REG_WR(sc, BCE_DMA_CONFIG, val); 5033 5034 /* Enable the RX_V2P and Context state machines before access. */ 5035 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5036 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5037 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5038 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5039 5040 /* Initialize context mapping and zero out the quick contexts. */ 5041 if ((rc = bce_init_ctx(sc)) != 0) 5042 goto bce_chipinit_exit; 5043 5044 /* Initialize the on-boards CPUs */ 5045 bce_init_cpus(sc); 5046 5047 /* Enable management frames (NC-SI) to flow to the MCP. */ 5048 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5049 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5050 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5051 } 5052 5053 /* Prepare NVRAM for access. */ 5054 if ((rc = bce_init_nvram(sc)) != 0) 5055 goto bce_chipinit_exit; 5056 5057 /* Set the kernel bypass block size */ 5058 val = REG_RD(sc, BCE_MQ_CONFIG); 5059 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5060 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5061 5062 /* Enable bins used on the 5709. */ 5063 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5064 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5065 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5066 val |= BCE_MQ_CONFIG_HALT_DIS; 5067 } 5068 5069 REG_WR(sc, BCE_MQ_CONFIG, val); 5070 5071 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5072 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5073 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5074 5075 /* Set the page size and clear the RV2P processor stall bits. */ 5076 val = (BCM_PAGE_BITS - 8) << 24; 5077 REG_WR(sc, BCE_RV2P_CONFIG, val); 5078 5079 /* Configure page size. */ 5080 val = REG_RD(sc, BCE_TBDR_CONFIG); 5081 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5082 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5083 REG_WR(sc, BCE_TBDR_CONFIG, val); 5084 5085 /* Set the perfect match control register to default. */ 5086 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5087 5088 bce_chipinit_exit: 5089 DBEXIT(BCE_VERBOSE_RESET); 5090 5091 return(rc); 5092 } 5093 5094 /****************************************************************************/ 5095 /* Initialize the controller in preparation to send/receive traffic. */ 5096 /* */ 5097 /* Returns: */ 5098 /* 0 for success, positive value for failure. */ 5099 /****************************************************************************/ 5100 static int 5101 bce_blockinit(struct bce_softc *sc) 5102 { 5103 u32 reg, val; 5104 int rc = 0; 5105 5106 DBENTER(BCE_VERBOSE_RESET); 5107 5108 /* Load the hardware default MAC address. */ 5109 bce_set_mac_addr(sc); 5110 5111 /* Set the Ethernet backoff seed value */ 5112 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5113 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5114 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5115 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5116 5117 sc->last_status_idx = 0; 5118 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5119 5120 /* Set up link change interrupt generation. */ 5121 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5122 5123 /* Program the physical address of the status block. */ 5124 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5125 BCE_ADDR_LO(sc->status_block_paddr)); 5126 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5127 BCE_ADDR_HI(sc->status_block_paddr)); 5128 5129 /* Program the physical address of the statistics block. */ 5130 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5131 BCE_ADDR_LO(sc->stats_block_paddr)); 5132 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5133 BCE_ADDR_HI(sc->stats_block_paddr)); 5134 5135 /* 5136 * Program various host coalescing parameters. 5137 * Trip points control how many BDs should be ready before generating 5138 * an interrupt while ticks control how long a BD can sit in the chain 5139 * before generating an interrupt. 5140 */ 5141 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5142 (sc->bce_tx_quick_cons_trip_int << 16) | 5143 sc->bce_tx_quick_cons_trip); 5144 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5145 (sc->bce_rx_quick_cons_trip_int << 16) | 5146 sc->bce_rx_quick_cons_trip); 5147 REG_WR(sc, BCE_HC_TX_TICKS, 5148 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5149 REG_WR(sc, BCE_HC_RX_TICKS, 5150 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5151 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00); 5152 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5153 /* Not used for L2. */ 5154 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0); 5155 REG_WR(sc, BCE_HC_COM_TICKS, 0); 5156 REG_WR(sc, BCE_HC_CMD_TICKS, 0); 5157 5158 /* Configure the Host Coalescing block. */ 5159 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5160 BCE_HC_CONFIG_COLLECT_STATS; 5161 5162 #if 0 5163 /* ToDo: Add MSI-X support. */ 5164 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5165 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5166 BCE_HC_SB_CONFIG_1; 5167 5168 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5169 5170 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5171 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5172 5173 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5174 (sc->tx_quick_cons_trip_int << 16) | 5175 sc->tx_quick_cons_trip); 5176 5177 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5178 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5179 5180 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5181 } 5182 5183 /* 5184 * Tell the HC block to automatically set the 5185 * INT_MASK bit after an MSI/MSI-X interrupt 5186 * is generated so the driver doesn't have to. 5187 */ 5188 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5189 val |= BCE_HC_CONFIG_ONE_SHOT; 5190 5191 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5192 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5193 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5194 #endif 5195 5196 REG_WR(sc, BCE_HC_CONFIG, val); 5197 5198 /* Clear the internal statistics counters. */ 5199 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5200 5201 /* Verify that bootcode is running. */ 5202 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5203 5204 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5205 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5206 __FILE__, __LINE__); 5207 reg = 0); 5208 5209 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5210 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5211 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5212 "Expected: 08%08X\n", __FILE__, __LINE__, 5213 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5214 BCE_DEV_INFO_SIGNATURE_MAGIC); 5215 rc = ENODEV; 5216 goto bce_blockinit_exit; 5217 } 5218 5219 /* Enable DMA */ 5220 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5221 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5222 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5223 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5224 } 5225 5226 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5227 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5228 BCE_DRV_MSG_CODE_RESET); 5229 5230 /* Enable link state change interrupt generation. */ 5231 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5232 5233 /* Enable the RXP. */ 5234 bce_start_rxp_cpu(sc); 5235 5236 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5237 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5238 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5239 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5240 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5241 } 5242 5243 /* Enable all remaining blocks in the MAC. */ 5244 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5245 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5246 BCE_MISC_ENABLE_DEFAULT_XI); 5247 else 5248 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5249 BCE_MISC_ENABLE_DEFAULT); 5250 5251 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5252 DELAY(20); 5253 5254 /* Save the current host coalescing block settings. */ 5255 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5256 5257 bce_blockinit_exit: 5258 DBEXIT(BCE_VERBOSE_RESET); 5259 5260 return (rc); 5261 } 5262 5263 /****************************************************************************/ 5264 /* Encapsulate an mbuf into the rx_bd chain. */ 5265 /* */ 5266 /* Returns: */ 5267 /* 0 for success, positive value for failure. */ 5268 /****************************************************************************/ 5269 static int 5270 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq) 5271 { 5272 bus_dma_segment_t segs[1]; 5273 struct mbuf *m_new = NULL; 5274 struct rx_bd *rxbd; 5275 int nsegs, error, rc = 0; 5276 #ifdef BCE_DEBUG 5277 u16 debug_chain_prod = chain_prod; 5278 #endif 5279 5280 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5281 5282 /* Make sure the inputs are valid. */ 5283 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC), 5284 BCE_PRINTF("%s(%d): RX producer out of range: " 5285 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5286 chain_prod, (u16)MAX_RX_BD_ALLOC)); 5287 5288 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5289 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5290 prod, chain_prod, *prod_bseq); 5291 5292 /* Update some debug statistic counters */ 5293 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5294 sc->rx_low_watermark = sc->free_rx_bd); 5295 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5296 sc->rx_empty_count++); 5297 5298 /* Simulate an mbuf allocation failure. */ 5299 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5300 sc->mbuf_alloc_failed_count++; 5301 sc->mbuf_alloc_failed_sim_count++; 5302 rc = ENOBUFS; 5303 goto bce_get_rx_buf_exit); 5304 5305 /* This is a new mbuf allocation. */ 5306 if (bce_hdr_split == TRUE) 5307 MGETHDR(m_new, M_NOWAIT, MT_DATA); 5308 else 5309 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 5310 sc->rx_bd_mbuf_alloc_size); 5311 5312 if (m_new == NULL) { 5313 sc->mbuf_alloc_failed_count++; 5314 rc = ENOBUFS; 5315 goto bce_get_rx_buf_exit; 5316 } 5317 5318 DBRUN(sc->debug_rx_mbuf_alloc++); 5319 5320 /* Make sure we have a valid packet header. */ 5321 M_ASSERTPKTHDR(m_new); 5322 5323 /* Initialize the mbuf size and pad if necessary for alignment. */ 5324 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5325 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5326 5327 /* ToDo: Consider calling m_fragment() to test error handling. */ 5328 5329 /* Map the mbuf cluster into device memory. */ 5330 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, 5331 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5332 5333 /* Handle any mapping errors. */ 5334 if (error) { 5335 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5336 "chain (%d)!\n", __FILE__, __LINE__, error); 5337 5338 sc->dma_map_addr_rx_failed_count++; 5339 m_freem(m_new); 5340 5341 DBRUN(sc->debug_rx_mbuf_alloc--); 5342 5343 rc = ENOBUFS; 5344 goto bce_get_rx_buf_exit; 5345 } 5346 5347 /* All mbufs must map to a single segment. */ 5348 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5349 __FUNCTION__, nsegs)); 5350 5351 /* Setup the rx_bd for the segment. */ 5352 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)]; 5353 5354 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5355 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5356 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5357 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5358 *prod_bseq += segs[0].ds_len; 5359 5360 /* Save the mbuf and update our counter. */ 5361 sc->rx_mbuf_ptr[chain_prod] = m_new; 5362 sc->free_rx_bd -= nsegs; 5363 5364 DBRUNMSG(BCE_INSANE_RECV, 5365 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5366 5367 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5368 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod, 5369 chain_prod, *prod_bseq); 5370 5371 bce_get_rx_buf_exit: 5372 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5373 5374 return(rc); 5375 } 5376 5377 /****************************************************************************/ 5378 /* Encapsulate an mbuf cluster into the page chain. */ 5379 /* */ 5380 /* Returns: */ 5381 /* 0 for success, positive value for failure. */ 5382 /****************************************************************************/ 5383 static int 5384 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx) 5385 { 5386 bus_dma_segment_t segs[1]; 5387 struct mbuf *m_new = NULL; 5388 struct rx_bd *pgbd; 5389 int error, nsegs, rc = 0; 5390 #ifdef BCE_DEBUG 5391 u16 debug_prod_idx = prod_idx; 5392 #endif 5393 5394 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5395 5396 /* Make sure the inputs are valid. */ 5397 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC), 5398 BCE_PRINTF("%s(%d): page producer out of range: " 5399 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5400 prod_idx, (u16)MAX_PG_BD_ALLOC)); 5401 5402 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5403 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5404 5405 /* Update counters if we've hit a new low or run out of pages. */ 5406 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5407 sc->pg_low_watermark = sc->free_pg_bd); 5408 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5409 5410 /* Simulate an mbuf allocation failure. */ 5411 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5412 sc->mbuf_alloc_failed_count++; 5413 sc->mbuf_alloc_failed_sim_count++; 5414 rc = ENOBUFS; 5415 goto bce_get_pg_buf_exit); 5416 5417 /* This is a new mbuf allocation. */ 5418 m_new = m_getcl(M_NOWAIT, MT_DATA, 0); 5419 if (m_new == NULL) { 5420 sc->mbuf_alloc_failed_count++; 5421 rc = ENOBUFS; 5422 goto bce_get_pg_buf_exit; 5423 } 5424 5425 DBRUN(sc->debug_pg_mbuf_alloc++); 5426 5427 m_new->m_len = MCLBYTES; 5428 5429 /* ToDo: Consider calling m_fragment() to test error handling. */ 5430 5431 /* Map the mbuf cluster into device memory. */ 5432 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag, 5433 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5434 5435 /* Handle any mapping errors. */ 5436 if (error) { 5437 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5438 __FILE__, __LINE__); 5439 5440 m_freem(m_new); 5441 DBRUN(sc->debug_pg_mbuf_alloc--); 5442 5443 rc = ENOBUFS; 5444 goto bce_get_pg_buf_exit; 5445 } 5446 5447 /* All mbufs must map to a single segment. */ 5448 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5449 __FUNCTION__, nsegs)); 5450 5451 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5452 5453 /* 5454 * The page chain uses the same rx_bd data structure 5455 * as the receive chain but doesn't require a byte sequence (bseq). 5456 */ 5457 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)]; 5458 5459 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5460 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5461 pgbd->rx_bd_len = htole32(MCLBYTES); 5462 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5463 5464 /* Save the mbuf and update our counter. */ 5465 sc->pg_mbuf_ptr[prod_idx] = m_new; 5466 sc->free_pg_bd--; 5467 5468 DBRUNMSG(BCE_INSANE_RECV, 5469 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5470 5471 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5472 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5473 5474 bce_get_pg_buf_exit: 5475 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5476 5477 return(rc); 5478 } 5479 5480 /****************************************************************************/ 5481 /* Initialize the TX context memory. */ 5482 /* */ 5483 /* Returns: */ 5484 /* Nothing */ 5485 /****************************************************************************/ 5486 static void 5487 bce_init_tx_context(struct bce_softc *sc) 5488 { 5489 u32 val; 5490 5491 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5492 5493 /* Initialize the context ID for an L2 TX chain. */ 5494 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5495 /* Set the CID type to support an L2 connection. */ 5496 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5497 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5498 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5499 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5500 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5501 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5502 5503 /* Point the hardware to the first page in the chain. */ 5504 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5505 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5506 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5507 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5508 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5509 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5510 } else { 5511 /* Set the CID type to support an L2 connection. */ 5512 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5513 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5514 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5515 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5516 5517 /* Point the hardware to the first page in the chain. */ 5518 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5519 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5520 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5521 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5522 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5523 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5524 } 5525 5526 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5527 } 5528 5529 /****************************************************************************/ 5530 /* Allocate memory and initialize the TX data structures. */ 5531 /* */ 5532 /* Returns: */ 5533 /* 0 for success, positive value for failure. */ 5534 /****************************************************************************/ 5535 static int 5536 bce_init_tx_chain(struct bce_softc *sc) 5537 { 5538 struct tx_bd *txbd; 5539 int i, rc = 0; 5540 5541 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5542 5543 /* Set the initial TX producer/consumer indices. */ 5544 sc->tx_prod = 0; 5545 sc->tx_cons = 0; 5546 sc->tx_prod_bseq = 0; 5547 sc->used_tx_bd = 0; 5548 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5549 DBRUN(sc->tx_hi_watermark = 0); 5550 DBRUN(sc->tx_full_count = 0); 5551 5552 /* 5553 * The NetXtreme II supports a linked-list structure called 5554 * a Buffer Descriptor Chain (or BD chain). A BD chain 5555 * consists of a series of 1 or more chain pages, each of which 5556 * consists of a fixed number of BD entries. 5557 * The last BD entry on each page is a pointer to the next page 5558 * in the chain, and the last pointer in the BD chain 5559 * points back to the beginning of the chain. 5560 */ 5561 5562 /* Set the TX next pointer chain entries. */ 5563 for (i = 0; i < sc->tx_pages; i++) { 5564 int j; 5565 5566 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5567 5568 /* Check if we've reached the last page. */ 5569 if (i == (sc->tx_pages - 1)) 5570 j = 0; 5571 else 5572 j = i + 1; 5573 5574 txbd->tx_bd_haddr_hi = 5575 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5576 txbd->tx_bd_haddr_lo = 5577 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5578 } 5579 5580 bce_init_tx_context(sc); 5581 5582 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5583 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5584 5585 return(rc); 5586 } 5587 5588 /****************************************************************************/ 5589 /* Free memory and clear the TX data structures. */ 5590 /* */ 5591 /* Returns: */ 5592 /* Nothing. */ 5593 /****************************************************************************/ 5594 static void 5595 bce_free_tx_chain(struct bce_softc *sc) 5596 { 5597 int i; 5598 5599 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5600 5601 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5602 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5603 if (sc->tx_mbuf_ptr[i] != NULL) { 5604 if (sc->tx_mbuf_map[i] != NULL) 5605 bus_dmamap_sync(sc->tx_mbuf_tag, 5606 sc->tx_mbuf_map[i], 5607 BUS_DMASYNC_POSTWRITE); 5608 m_freem(sc->tx_mbuf_ptr[i]); 5609 sc->tx_mbuf_ptr[i] = NULL; 5610 DBRUN(sc->debug_tx_mbuf_alloc--); 5611 } 5612 } 5613 5614 /* Clear each TX chain page. */ 5615 for (i = 0; i < sc->tx_pages; i++) 5616 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5617 5618 sc->used_tx_bd = 0; 5619 5620 /* Check if we lost any mbufs in the process. */ 5621 DBRUNIF((sc->debug_tx_mbuf_alloc), 5622 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5623 "from tx chain!\n", __FILE__, __LINE__, 5624 sc->debug_tx_mbuf_alloc)); 5625 5626 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5627 } 5628 5629 /****************************************************************************/ 5630 /* Initialize the RX context memory. */ 5631 /* */ 5632 /* Returns: */ 5633 /* Nothing */ 5634 /****************************************************************************/ 5635 static void 5636 bce_init_rx_context(struct bce_softc *sc) 5637 { 5638 u32 val; 5639 5640 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5641 5642 /* Init the type, size, and BD cache levels for the RX context. */ 5643 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5644 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5645 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5646 5647 /* 5648 * Set the level for generating pause frames 5649 * when the number of available rx_bd's gets 5650 * too low (the low watermark) and the level 5651 * when pause frames can be stopped (the high 5652 * watermark). 5653 */ 5654 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5655 u32 lo_water, hi_water; 5656 5657 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5658 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5659 } else { 5660 lo_water = 0; 5661 } 5662 5663 if (lo_water >= USABLE_RX_BD_ALLOC) { 5664 lo_water = 0; 5665 } 5666 5667 hi_water = USABLE_RX_BD_ALLOC / 4; 5668 5669 if (hi_water <= lo_water) { 5670 lo_water = 0; 5671 } 5672 5673 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5674 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5675 5676 if (hi_water > 0xf) 5677 hi_water = 0xf; 5678 else if (hi_water == 0) 5679 lo_water = 0; 5680 5681 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5682 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5683 } 5684 5685 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5686 5687 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5688 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5689 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5690 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5691 } 5692 5693 /* Point the hardware to the first page in the chain. */ 5694 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5695 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5696 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5697 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5698 5699 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5700 } 5701 5702 /****************************************************************************/ 5703 /* Allocate memory and initialize the RX data structures. */ 5704 /* */ 5705 /* Returns: */ 5706 /* 0 for success, positive value for failure. */ 5707 /****************************************************************************/ 5708 static int 5709 bce_init_rx_chain(struct bce_softc *sc) 5710 { 5711 struct rx_bd *rxbd; 5712 int i, rc = 0; 5713 5714 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5715 BCE_VERBOSE_CTX); 5716 5717 /* Initialize the RX producer and consumer indices. */ 5718 sc->rx_prod = 0; 5719 sc->rx_cons = 0; 5720 sc->rx_prod_bseq = 0; 5721 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5722 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5723 5724 /* Initialize the RX next pointer chain entries. */ 5725 for (i = 0; i < sc->rx_pages; i++) { 5726 int j; 5727 5728 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5729 5730 /* Check if we've reached the last page. */ 5731 if (i == (sc->rx_pages - 1)) 5732 j = 0; 5733 else 5734 j = i + 1; 5735 5736 /* Setup the chain page pointers. */ 5737 rxbd->rx_bd_haddr_hi = 5738 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5739 rxbd->rx_bd_haddr_lo = 5740 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5741 } 5742 5743 /* Fill up the RX chain. */ 5744 bce_fill_rx_chain(sc); 5745 5746 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5747 DBRUN(sc->rx_empty_count = 0); 5748 for (i = 0; i < sc->rx_pages; i++) { 5749 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5750 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5751 } 5752 5753 bce_init_rx_context(sc); 5754 5755 DBRUNMSG(BCE_EXTREME_RECV, 5756 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5757 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5758 BCE_VERBOSE_CTX); 5759 5760 /* ToDo: Are there possible failure modes here? */ 5761 5762 return(rc); 5763 } 5764 5765 /****************************************************************************/ 5766 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5767 /* occurs. */ 5768 /* */ 5769 /* Returns: */ 5770 /* Nothing */ 5771 /****************************************************************************/ 5772 static void 5773 bce_fill_rx_chain(struct bce_softc *sc) 5774 { 5775 u16 prod, prod_idx; 5776 u32 prod_bseq; 5777 5778 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5779 BCE_VERBOSE_CTX); 5780 5781 /* Get the RX chain producer indices. */ 5782 prod = sc->rx_prod; 5783 prod_bseq = sc->rx_prod_bseq; 5784 5785 /* Keep filling the RX chain until it's full. */ 5786 while (sc->free_rx_bd > 0) { 5787 prod_idx = RX_CHAIN_IDX(prod); 5788 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) { 5789 /* Bail out if we can't add an mbuf to the chain. */ 5790 break; 5791 } 5792 prod = NEXT_RX_BD(prod); 5793 } 5794 5795 /* Save the RX chain producer indices. */ 5796 sc->rx_prod = prod; 5797 sc->rx_prod_bseq = prod_bseq; 5798 5799 /* We should never end up pointing to a next page pointer. */ 5800 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5801 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5802 __FUNCTION__, rx_prod)); 5803 5804 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5805 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod); 5806 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq); 5807 5808 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5809 BCE_VERBOSE_CTX); 5810 } 5811 5812 /****************************************************************************/ 5813 /* Free memory and clear the RX data structures. */ 5814 /* */ 5815 /* Returns: */ 5816 /* Nothing. */ 5817 /****************************************************************************/ 5818 static void 5819 bce_free_rx_chain(struct bce_softc *sc) 5820 { 5821 int i; 5822 5823 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5824 5825 /* Free any mbufs still in the RX mbuf chain. */ 5826 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5827 if (sc->rx_mbuf_ptr[i] != NULL) { 5828 if (sc->rx_mbuf_map[i] != NULL) 5829 bus_dmamap_sync(sc->rx_mbuf_tag, 5830 sc->rx_mbuf_map[i], 5831 BUS_DMASYNC_POSTREAD); 5832 m_freem(sc->rx_mbuf_ptr[i]); 5833 sc->rx_mbuf_ptr[i] = NULL; 5834 DBRUN(sc->debug_rx_mbuf_alloc--); 5835 } 5836 } 5837 5838 /* Clear each RX chain page. */ 5839 for (i = 0; i < sc->rx_pages; i++) 5840 if (sc->rx_bd_chain[i] != NULL) 5841 bzero((char *)sc->rx_bd_chain[i], 5842 BCE_RX_CHAIN_PAGE_SZ); 5843 5844 sc->free_rx_bd = sc->max_rx_bd; 5845 5846 /* Check if we lost any mbufs in the process. */ 5847 DBRUNIF((sc->debug_rx_mbuf_alloc), 5848 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5849 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5850 5851 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5852 } 5853 5854 /****************************************************************************/ 5855 /* Allocate memory and initialize the page data structures. */ 5856 /* Assumes that bce_init_rx_chain() has not already been called. */ 5857 /* */ 5858 /* Returns: */ 5859 /* 0 for success, positive value for failure. */ 5860 /****************************************************************************/ 5861 static int 5862 bce_init_pg_chain(struct bce_softc *sc) 5863 { 5864 struct rx_bd *pgbd; 5865 int i, rc = 0; 5866 u32 val; 5867 5868 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5869 BCE_VERBOSE_CTX); 5870 5871 /* Initialize the page producer and consumer indices. */ 5872 sc->pg_prod = 0; 5873 sc->pg_cons = 0; 5874 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5875 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5876 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5877 DBRUN(sc->pg_empty_count = 0); 5878 5879 /* Initialize the page next pointer chain entries. */ 5880 for (i = 0; i < sc->pg_pages; i++) { 5881 int j; 5882 5883 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5884 5885 /* Check if we've reached the last page. */ 5886 if (i == (sc->pg_pages - 1)) 5887 j = 0; 5888 else 5889 j = i + 1; 5890 5891 /* Setup the chain page pointers. */ 5892 pgbd->rx_bd_haddr_hi = 5893 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5894 pgbd->rx_bd_haddr_lo = 5895 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5896 } 5897 5898 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5899 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5900 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5901 5902 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5903 5904 /* Configure the rx_bd and page chain mbuf cluster size. */ 5905 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES; 5906 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5907 5908 /* Configure the context reserved for jumbo support. */ 5909 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5910 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5911 5912 /* Point the hardware to the first page in the page chain. */ 5913 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5914 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 5915 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5916 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 5917 5918 /* Fill up the page chain. */ 5919 bce_fill_pg_chain(sc); 5920 5921 for (i = 0; i < sc->pg_pages; i++) { 5922 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 5923 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5924 } 5925 5926 DBRUNMSG(BCE_EXTREME_RECV, 5927 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 5928 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5929 BCE_VERBOSE_CTX); 5930 return(rc); 5931 } 5932 5933 /****************************************************************************/ 5934 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 5935 /* occurs. */ 5936 /* */ 5937 /* Returns: */ 5938 /* Nothing */ 5939 /****************************************************************************/ 5940 static void 5941 bce_fill_pg_chain(struct bce_softc *sc) 5942 { 5943 u16 prod, prod_idx; 5944 5945 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5946 BCE_VERBOSE_CTX); 5947 5948 /* Get the page chain prodcuer index. */ 5949 prod = sc->pg_prod; 5950 5951 /* Keep filling the page chain until it's full. */ 5952 while (sc->free_pg_bd > 0) { 5953 prod_idx = PG_CHAIN_IDX(prod); 5954 if (bce_get_pg_buf(sc, prod, prod_idx)) { 5955 /* Bail out if we can't add an mbuf to the chain. */ 5956 break; 5957 } 5958 prod = NEXT_PG_BD(prod); 5959 } 5960 5961 /* Save the page chain producer index. */ 5962 sc->pg_prod = prod; 5963 5964 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5965 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 5966 __FUNCTION__, pg_prod)); 5967 5968 /* 5969 * Write the mailbox and tell the chip about 5970 * the new rx_bd's in the page chain. 5971 */ 5972 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX, 5973 prod); 5974 5975 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5976 BCE_VERBOSE_CTX); 5977 } 5978 5979 /****************************************************************************/ 5980 /* Free memory and clear the RX data structures. */ 5981 /* */ 5982 /* Returns: */ 5983 /* Nothing. */ 5984 /****************************************************************************/ 5985 static void 5986 bce_free_pg_chain(struct bce_softc *sc) 5987 { 5988 int i; 5989 5990 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5991 5992 /* Free any mbufs still in the mbuf page chain. */ 5993 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 5994 if (sc->pg_mbuf_ptr[i] != NULL) { 5995 if (sc->pg_mbuf_map[i] != NULL) 5996 bus_dmamap_sync(sc->pg_mbuf_tag, 5997 sc->pg_mbuf_map[i], 5998 BUS_DMASYNC_POSTREAD); 5999 m_freem(sc->pg_mbuf_ptr[i]); 6000 sc->pg_mbuf_ptr[i] = NULL; 6001 DBRUN(sc->debug_pg_mbuf_alloc--); 6002 } 6003 } 6004 6005 /* Clear each page chain pages. */ 6006 for (i = 0; i < sc->pg_pages; i++) 6007 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6008 6009 sc->free_pg_bd = sc->max_pg_bd; 6010 6011 /* Check if we lost any mbufs in the process. */ 6012 DBRUNIF((sc->debug_pg_mbuf_alloc), 6013 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6014 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6015 6016 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6017 } 6018 6019 static u32 6020 bce_get_rphy_link(struct bce_softc *sc) 6021 { 6022 u32 advertise, link; 6023 int fdpx; 6024 6025 advertise = 0; 6026 fdpx = 0; 6027 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) 6028 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK); 6029 else 6030 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK); 6031 if (link & BCE_NETLINK_ANEG_ENB) 6032 advertise |= BCE_NETLINK_ANEG_ENB; 6033 if (link & BCE_NETLINK_SPEED_10HALF) 6034 advertise |= BCE_NETLINK_SPEED_10HALF; 6035 if (link & BCE_NETLINK_SPEED_10FULL) { 6036 advertise |= BCE_NETLINK_SPEED_10FULL; 6037 fdpx++; 6038 } 6039 if (link & BCE_NETLINK_SPEED_100HALF) 6040 advertise |= BCE_NETLINK_SPEED_100HALF; 6041 if (link & BCE_NETLINK_SPEED_100FULL) { 6042 advertise |= BCE_NETLINK_SPEED_100FULL; 6043 fdpx++; 6044 } 6045 if (link & BCE_NETLINK_SPEED_1000HALF) 6046 advertise |= BCE_NETLINK_SPEED_1000HALF; 6047 if (link & BCE_NETLINK_SPEED_1000FULL) { 6048 advertise |= BCE_NETLINK_SPEED_1000FULL; 6049 fdpx++; 6050 } 6051 if (link & BCE_NETLINK_SPEED_2500HALF) 6052 advertise |= BCE_NETLINK_SPEED_2500HALF; 6053 if (link & BCE_NETLINK_SPEED_2500FULL) { 6054 advertise |= BCE_NETLINK_SPEED_2500FULL; 6055 fdpx++; 6056 } 6057 if (fdpx) 6058 advertise |= BCE_NETLINK_FC_PAUSE_SYM | 6059 BCE_NETLINK_FC_PAUSE_ASYM; 6060 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6061 advertise |= BCE_NETLINK_PHY_APP_REMOTE | 6062 BCE_NETLINK_ETH_AT_WIRESPEED; 6063 6064 return (advertise); 6065 } 6066 6067 /****************************************************************************/ 6068 /* Set media options. */ 6069 /* */ 6070 /* Returns: */ 6071 /* 0 for success, positive value for failure. */ 6072 /****************************************************************************/ 6073 static int 6074 bce_ifmedia_upd(if_t ifp) 6075 { 6076 struct bce_softc *sc = if_getsoftc(ifp); 6077 int error; 6078 6079 DBENTER(BCE_VERBOSE); 6080 6081 BCE_LOCK(sc); 6082 error = bce_ifmedia_upd_locked(ifp); 6083 BCE_UNLOCK(sc); 6084 6085 DBEXIT(BCE_VERBOSE); 6086 return (error); 6087 } 6088 6089 /****************************************************************************/ 6090 /* Set media options. */ 6091 /* */ 6092 /* Returns: */ 6093 /* Nothing. */ 6094 /****************************************************************************/ 6095 static int 6096 bce_ifmedia_upd_locked(if_t ifp) 6097 { 6098 struct bce_softc *sc = if_getsoftc(ifp); 6099 struct mii_data *mii; 6100 struct mii_softc *miisc; 6101 struct ifmedia *ifm; 6102 u32 link; 6103 int error, fdx; 6104 6105 DBENTER(BCE_VERBOSE_PHY); 6106 6107 error = 0; 6108 BCE_LOCK_ASSERT(sc); 6109 6110 sc->bce_link_up = FALSE; 6111 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6112 ifm = &sc->bce_ifmedia; 6113 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 6114 return (EINVAL); 6115 link = 0; 6116 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX; 6117 switch(IFM_SUBTYPE(ifm->ifm_media)) { 6118 case IFM_AUTO: 6119 /* 6120 * Check advertised link of remote PHY by reading 6121 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK. 6122 * Always use the same link type of remote PHY. 6123 */ 6124 link = bce_get_rphy_link(sc); 6125 break; 6126 case IFM_2500_SX: 6127 if ((sc->bce_phy_flags & 6128 (BCE_PHY_REMOTE_PORT_FIBER_FLAG | 6129 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0) 6130 return (EINVAL); 6131 /* 6132 * XXX 6133 * Have to enable forced 2.5Gbps configuration. 6134 */ 6135 if (fdx != 0) 6136 link |= BCE_NETLINK_SPEED_2500FULL; 6137 else 6138 link |= BCE_NETLINK_SPEED_2500HALF; 6139 break; 6140 case IFM_1000_SX: 6141 if ((sc->bce_phy_flags & 6142 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6143 return (EINVAL); 6144 /* 6145 * XXX 6146 * Have to disable 2.5Gbps configuration. 6147 */ 6148 if (fdx != 0) 6149 link = BCE_NETLINK_SPEED_1000FULL; 6150 else 6151 link = BCE_NETLINK_SPEED_1000HALF; 6152 break; 6153 case IFM_1000_T: 6154 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6155 return (EINVAL); 6156 if (fdx != 0) 6157 link = BCE_NETLINK_SPEED_1000FULL; 6158 else 6159 link = BCE_NETLINK_SPEED_1000HALF; 6160 break; 6161 case IFM_100_TX: 6162 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6163 return (EINVAL); 6164 if (fdx != 0) 6165 link = BCE_NETLINK_SPEED_100FULL; 6166 else 6167 link = BCE_NETLINK_SPEED_100HALF; 6168 break; 6169 case IFM_10_T: 6170 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6171 return (EINVAL); 6172 if (fdx != 0) 6173 link = BCE_NETLINK_SPEED_10FULL; 6174 else 6175 link = BCE_NETLINK_SPEED_10HALF; 6176 break; 6177 default: 6178 return (EINVAL); 6179 } 6180 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) { 6181 /* 6182 * XXX 6183 * Advertise pause capability for full-duplex media. 6184 */ 6185 if (fdx != 0) 6186 link |= BCE_NETLINK_FC_PAUSE_SYM | 6187 BCE_NETLINK_FC_PAUSE_ASYM; 6188 if ((sc->bce_phy_flags & 6189 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6190 link |= BCE_NETLINK_PHY_APP_REMOTE | 6191 BCE_NETLINK_ETH_AT_WIRESPEED; 6192 } 6193 6194 bce_shmem_wr(sc, BCE_MB_ARGS_0, link); 6195 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK); 6196 } else { 6197 mii = device_get_softc(sc->bce_miibus); 6198 6199 /* Make sure the MII bus has been enumerated. */ 6200 if (mii) { 6201 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6202 PHY_RESET(miisc); 6203 error = mii_mediachg(mii); 6204 } 6205 } 6206 6207 DBEXIT(BCE_VERBOSE_PHY); 6208 return (error); 6209 } 6210 6211 static void 6212 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr) 6213 { 6214 if_t ifp; 6215 u32 link; 6216 6217 ifp = sc->bce_ifp; 6218 BCE_LOCK_ASSERT(sc); 6219 6220 ifmr->ifm_status = IFM_AVALID; 6221 ifmr->ifm_active = IFM_ETHER; 6222 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 6223 /* XXX Handle heart beat status? */ 6224 if ((link & BCE_LINK_STATUS_LINK_UP) != 0) 6225 ifmr->ifm_status |= IFM_ACTIVE; 6226 else { 6227 ifmr->ifm_active |= IFM_NONE; 6228 if_setbaudrate(ifp, 0); 6229 return; 6230 } 6231 switch (link & BCE_LINK_STATUS_SPEED_MASK) { 6232 case BCE_LINK_STATUS_10HALF: 6233 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 6234 if_setbaudrate(ifp, IF_Mbps(10UL)); 6235 break; 6236 case BCE_LINK_STATUS_10FULL: 6237 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 6238 if_setbaudrate(ifp, IF_Mbps(10UL)); 6239 break; 6240 case BCE_LINK_STATUS_100HALF: 6241 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 6242 if_setbaudrate(ifp, IF_Mbps(100UL)); 6243 break; 6244 case BCE_LINK_STATUS_100FULL: 6245 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 6246 if_setbaudrate(ifp, IF_Mbps(100UL)); 6247 break; 6248 case BCE_LINK_STATUS_1000HALF: 6249 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6250 ifmr->ifm_active |= IFM_1000_T | IFM_HDX; 6251 else 6252 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX; 6253 if_setbaudrate(ifp, IF_Mbps(1000UL)); 6254 break; 6255 case BCE_LINK_STATUS_1000FULL: 6256 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6257 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 6258 else 6259 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 6260 if_setbaudrate(ifp, IF_Mbps(1000UL)); 6261 break; 6262 case BCE_LINK_STATUS_2500HALF: 6263 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6264 ifmr->ifm_active |= IFM_NONE; 6265 return; 6266 } else 6267 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX; 6268 if_setbaudrate(ifp, IF_Mbps(2500UL)); 6269 break; 6270 case BCE_LINK_STATUS_2500FULL: 6271 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6272 ifmr->ifm_active |= IFM_NONE; 6273 return; 6274 } else 6275 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 6276 if_setbaudrate(ifp, IF_Mbps(2500UL)); 6277 break; 6278 default: 6279 ifmr->ifm_active |= IFM_NONE; 6280 return; 6281 } 6282 6283 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0) 6284 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 6285 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0) 6286 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 6287 } 6288 6289 /****************************************************************************/ 6290 /* Reports current media status. */ 6291 /* */ 6292 /* Returns: */ 6293 /* Nothing. */ 6294 /****************************************************************************/ 6295 static void 6296 bce_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 6297 { 6298 struct bce_softc *sc = if_getsoftc(ifp); 6299 struct mii_data *mii; 6300 6301 DBENTER(BCE_VERBOSE_PHY); 6302 6303 BCE_LOCK(sc); 6304 6305 if ((if_getflags(ifp) & IFF_UP) == 0) { 6306 BCE_UNLOCK(sc); 6307 return; 6308 } 6309 6310 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 6311 bce_ifmedia_sts_rphy(sc, ifmr); 6312 else { 6313 mii = device_get_softc(sc->bce_miibus); 6314 mii_pollstat(mii); 6315 ifmr->ifm_active = mii->mii_media_active; 6316 ifmr->ifm_status = mii->mii_media_status; 6317 } 6318 6319 BCE_UNLOCK(sc); 6320 6321 DBEXIT(BCE_VERBOSE_PHY); 6322 } 6323 6324 /****************************************************************************/ 6325 /* Handles PHY generated interrupt events. */ 6326 /* */ 6327 /* Returns: */ 6328 /* Nothing. */ 6329 /****************************************************************************/ 6330 static void 6331 bce_phy_intr(struct bce_softc *sc) 6332 { 6333 u32 new_link_state, old_link_state; 6334 6335 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6336 6337 DBRUN(sc->phy_interrupts++); 6338 6339 new_link_state = sc->status_block->status_attn_bits & 6340 STATUS_ATTN_BITS_LINK_STATE; 6341 old_link_state = sc->status_block->status_attn_bits_ack & 6342 STATUS_ATTN_BITS_LINK_STATE; 6343 6344 /* Handle any changes if the link state has changed. */ 6345 if (new_link_state != old_link_state) { 6346 /* Update the status_attn_bits_ack field. */ 6347 if (new_link_state) { 6348 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6349 STATUS_ATTN_BITS_LINK_STATE); 6350 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6351 __FUNCTION__); 6352 } else { 6353 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6354 STATUS_ATTN_BITS_LINK_STATE); 6355 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6356 __FUNCTION__); 6357 } 6358 6359 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6360 if (new_link_state) { 6361 if (bootverbose) 6362 if_printf(sc->bce_ifp, "link UP\n"); 6363 if_link_state_change(sc->bce_ifp, 6364 LINK_STATE_UP); 6365 } else { 6366 if (bootverbose) 6367 if_printf(sc->bce_ifp, "link DOWN\n"); 6368 if_link_state_change(sc->bce_ifp, 6369 LINK_STATE_DOWN); 6370 } 6371 } 6372 /* 6373 * Assume link is down and allow 6374 * tick routine to update the state 6375 * based on the actual media state. 6376 */ 6377 sc->bce_link_up = FALSE; 6378 callout_stop(&sc->bce_tick_callout); 6379 bce_tick(sc); 6380 } 6381 6382 /* Acknowledge the link change interrupt. */ 6383 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6384 6385 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6386 } 6387 6388 /****************************************************************************/ 6389 /* Reads the receive consumer value from the status block (skipping over */ 6390 /* chain page pointer if necessary). */ 6391 /* */ 6392 /* Returns: */ 6393 /* hw_cons */ 6394 /****************************************************************************/ 6395 static inline u16 6396 bce_get_hw_rx_cons(struct bce_softc *sc) 6397 { 6398 u16 hw_cons; 6399 6400 rmb(); 6401 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6402 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6403 hw_cons++; 6404 6405 return hw_cons; 6406 } 6407 6408 /****************************************************************************/ 6409 /* Handles received frame interrupt events. */ 6410 /* */ 6411 /* Returns: */ 6412 /* Nothing. */ 6413 /****************************************************************************/ 6414 static void 6415 bce_rx_intr(struct bce_softc *sc) 6416 { 6417 if_t ifp = sc->bce_ifp; 6418 struct l2_fhdr *l2fhdr; 6419 struct ether_vlan_header *vh; 6420 unsigned int pkt_len; 6421 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6422 u32 status; 6423 unsigned int rem_len; 6424 u16 sw_pg_cons, sw_pg_cons_idx; 6425 6426 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6427 DBRUN(sc->interrupts_rx++); 6428 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6429 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6430 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6431 6432 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6433 for (int i = 0; i < sc->rx_pages; i++) 6434 bus_dmamap_sync(sc->rx_bd_chain_tag, 6435 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6436 6437 /* Prepare the page chain pages to be accessed by the host CPU. */ 6438 if (bce_hdr_split == TRUE) { 6439 for (int i = 0; i < sc->pg_pages; i++) 6440 bus_dmamap_sync(sc->pg_bd_chain_tag, 6441 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6442 } 6443 6444 /* Get the hardware's view of the RX consumer index. */ 6445 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6446 6447 /* Get working copies of the driver's view of the consumer indices. */ 6448 sw_rx_cons = sc->rx_cons; 6449 sw_pg_cons = sc->pg_cons; 6450 6451 /* Update some debug statistics counters */ 6452 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6453 sc->rx_low_watermark = sc->free_rx_bd); 6454 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6455 sc->rx_empty_count++); 6456 6457 /* Scan through the receive chain as long as there is work to do */ 6458 /* ToDo: Consider setting a limit on the number of packets processed. */ 6459 rmb(); 6460 while (sw_rx_cons != hw_rx_cons) { 6461 struct mbuf *m0; 6462 6463 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6464 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6465 6466 /* Unmap the mbuf from DMA space. */ 6467 bus_dmamap_sync(sc->rx_mbuf_tag, 6468 sc->rx_mbuf_map[sw_rx_cons_idx], 6469 BUS_DMASYNC_POSTREAD); 6470 bus_dmamap_unload(sc->rx_mbuf_tag, 6471 sc->rx_mbuf_map[sw_rx_cons_idx]); 6472 6473 /* Remove the mbuf from the RX chain. */ 6474 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6475 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6476 DBRUN(sc->debug_rx_mbuf_alloc--); 6477 sc->free_rx_bd++; 6478 6479 /* 6480 * Frames received on the NetXteme II are prepended 6481 * with an l2_fhdr structure which provides status 6482 * information about the received frame (including 6483 * VLAN tags and checksum info). The frames are 6484 * also automatically adjusted to word align the IP 6485 * header (i.e. two null bytes are inserted before 6486 * the Ethernet header). As a result the data 6487 * DMA'd by the controller into the mbuf looks 6488 * like this: 6489 * 6490 * +---------+-----+---------------------+-----+ 6491 * | l2_fhdr | pad | packet data | FCS | 6492 * +---------+-----+---------------------+-----+ 6493 * 6494 * The l2_fhdr needs to be checked and skipped and 6495 * the FCS needs to be stripped before sending the 6496 * packet up the stack. 6497 */ 6498 l2fhdr = mtod(m0, struct l2_fhdr *); 6499 6500 /* Get the packet data + FCS length and the status. */ 6501 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6502 status = l2fhdr->l2_fhdr_status; 6503 6504 /* 6505 * Skip over the l2_fhdr and pad, resulting in the 6506 * following data in the mbuf: 6507 * +---------------------+-----+ 6508 * | packet data | FCS | 6509 * +---------------------+-----+ 6510 */ 6511 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6512 6513 /* 6514 * When split header mode is used, an ethernet frame 6515 * may be split across the receive chain and the 6516 * page chain. If that occurs an mbuf cluster must be 6517 * reassembled from the individual mbuf pieces. 6518 */ 6519 if (bce_hdr_split == TRUE) { 6520 /* 6521 * Check whether the received frame fits in a single 6522 * mbuf or not (i.e. packet data + FCS <= 6523 * sc->rx_bd_mbuf_data_len bytes). 6524 */ 6525 if (pkt_len > m0->m_len) { 6526 /* 6527 * The received frame is larger than a single mbuf. 6528 * If the frame was a TCP frame then only the TCP 6529 * header is placed in the mbuf, the remaining 6530 * payload (including FCS) is placed in the page 6531 * chain, the SPLIT flag is set, and the header 6532 * length is placed in the IP checksum field. 6533 * If the frame is not a TCP frame then the mbuf 6534 * is filled and the remaining bytes are placed 6535 * in the page chain. 6536 */ 6537 6538 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6539 "packet.\n", __FUNCTION__); 6540 DBRUN(sc->split_header_frames_rcvd++); 6541 6542 /* 6543 * When the page chain is enabled and the TCP 6544 * header has been split from the TCP payload, 6545 * the ip_xsum structure will reflect the length 6546 * of the TCP header, not the IP checksum. Set 6547 * the packet length of the mbuf accordingly. 6548 */ 6549 if (status & L2_FHDR_STATUS_SPLIT) { 6550 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6551 DBRUN(sc->split_header_tcp_frames_rcvd++); 6552 } 6553 6554 rem_len = pkt_len - m0->m_len; 6555 6556 /* Pull mbufs off the page chain for any remaining data. */ 6557 while (rem_len > 0) { 6558 struct mbuf *m_pg; 6559 6560 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6561 6562 /* Remove the mbuf from the page chain. */ 6563 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6564 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6565 DBRUN(sc->debug_pg_mbuf_alloc--); 6566 sc->free_pg_bd++; 6567 6568 /* Unmap the page chain mbuf from DMA space. */ 6569 bus_dmamap_sync(sc->pg_mbuf_tag, 6570 sc->pg_mbuf_map[sw_pg_cons_idx], 6571 BUS_DMASYNC_POSTREAD); 6572 bus_dmamap_unload(sc->pg_mbuf_tag, 6573 sc->pg_mbuf_map[sw_pg_cons_idx]); 6574 6575 /* Adjust the mbuf length. */ 6576 if (rem_len < m_pg->m_len) { 6577 /* The mbuf chain is complete. */ 6578 m_pg->m_len = rem_len; 6579 rem_len = 0; 6580 } else { 6581 /* More packet data is waiting. */ 6582 rem_len -= m_pg->m_len; 6583 } 6584 6585 /* Concatenate the mbuf cluster to the mbuf. */ 6586 m_cat(m0, m_pg); 6587 6588 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6589 } 6590 6591 /* Set the total packet length. */ 6592 m0->m_pkthdr.len = pkt_len; 6593 6594 } else { 6595 /* 6596 * The received packet is small and fits in a 6597 * single mbuf (i.e. the l2_fhdr + pad + packet + 6598 * FCS <= MHLEN). In other words, the packet is 6599 * 154 bytes or less in size. 6600 */ 6601 6602 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6603 "packet.\n", __FUNCTION__); 6604 6605 /* Set the total packet length. */ 6606 m0->m_pkthdr.len = m0->m_len = pkt_len; 6607 } 6608 } else 6609 /* Set the total packet length. */ 6610 m0->m_pkthdr.len = m0->m_len = pkt_len; 6611 6612 /* Remove the trailing Ethernet FCS. */ 6613 m_adj(m0, -ETHER_CRC_LEN); 6614 6615 /* Check that the resulting mbuf chain is valid. */ 6616 DBRUN(m_sanity(m0, FALSE)); 6617 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6618 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6619 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6620 m_print(m0, 128)); 6621 6622 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6623 sc->l2fhdr_error_sim_count++; 6624 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6625 6626 /* Check the received frame for errors. */ 6627 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6628 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6629 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6630 /* Log the error and release the mbuf. */ 6631 sc->l2fhdr_error_count++; 6632 m_freem(m0); 6633 m0 = NULL; 6634 goto bce_rx_intr_next_rx; 6635 } 6636 6637 /* Send the packet to the appropriate interface. */ 6638 m0->m_pkthdr.rcvif = ifp; 6639 6640 /* Assume no hardware checksum. */ 6641 m0->m_pkthdr.csum_flags = 0; 6642 6643 /* Validate the checksum if offload enabled. */ 6644 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 6645 /* Check for an IP datagram. */ 6646 if (!(status & L2_FHDR_STATUS_SPLIT) && 6647 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6648 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6649 DBRUN(sc->csum_offload_ip++); 6650 /* Check if the IP checksum is valid. */ 6651 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6652 m0->m_pkthdr.csum_flags |= 6653 CSUM_IP_VALID; 6654 } 6655 6656 /* Check for a valid TCP/UDP frame. */ 6657 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6658 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6659 /* Check for a good TCP/UDP checksum. */ 6660 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6661 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6662 DBRUN(sc->csum_offload_tcp_udp++); 6663 m0->m_pkthdr.csum_data = 6664 l2fhdr->l2_fhdr_tcp_udp_xsum; 6665 m0->m_pkthdr.csum_flags |= 6666 (CSUM_DATA_VALID 6667 | CSUM_PSEUDO_HDR); 6668 } 6669 } 6670 } 6671 6672 /* Attach the VLAN tag. */ 6673 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 6674 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 6675 DBRUN(sc->vlan_tagged_frames_rcvd++); 6676 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 6677 DBRUN(sc->vlan_tagged_frames_stripped++); 6678 m0->m_pkthdr.ether_vtag = 6679 l2fhdr->l2_fhdr_vlan_tag; 6680 m0->m_flags |= M_VLANTAG; 6681 } else { 6682 /* 6683 * bce(4) controllers can't disable VLAN 6684 * tag stripping if management firmware 6685 * (ASF/IPMI/UMP) is running. So we always 6686 * strip VLAN tag and manually reconstruct 6687 * the VLAN frame by appending stripped 6688 * VLAN tag in driver if VLAN tag stripping 6689 * was disabled. 6690 * 6691 * TODO: LLC SNAP handling. 6692 */ 6693 bcopy(mtod(m0, uint8_t *), 6694 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6695 ETHER_ADDR_LEN * 2); 6696 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6697 vh = mtod(m0, struct ether_vlan_header *); 6698 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6699 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6700 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6701 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6702 } 6703 } 6704 6705 /* Increment received packet statistics. */ 6706 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 6707 6708 bce_rx_intr_next_rx: 6709 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6710 6711 /* If we have a packet, pass it up the stack */ 6712 if (m0) { 6713 /* Make sure we don't lose our place when we release the lock. */ 6714 sc->rx_cons = sw_rx_cons; 6715 sc->pg_cons = sw_pg_cons; 6716 6717 BCE_UNLOCK(sc); 6718 if_input(ifp, m0); 6719 BCE_LOCK(sc); 6720 6721 /* Recover our place. */ 6722 sw_rx_cons = sc->rx_cons; 6723 sw_pg_cons = sc->pg_cons; 6724 } 6725 6726 /* Refresh hw_cons to see if there's new work */ 6727 if (sw_rx_cons == hw_rx_cons) 6728 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6729 } 6730 6731 /* No new packets. Refill the page chain. */ 6732 if (bce_hdr_split == TRUE) { 6733 sc->pg_cons = sw_pg_cons; 6734 bce_fill_pg_chain(sc); 6735 } 6736 6737 /* No new packets. Refill the RX chain. */ 6738 sc->rx_cons = sw_rx_cons; 6739 bce_fill_rx_chain(sc); 6740 6741 /* Prepare the page chain pages to be accessed by the NIC. */ 6742 for (int i = 0; i < sc->rx_pages; i++) 6743 bus_dmamap_sync(sc->rx_bd_chain_tag, 6744 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6745 6746 if (bce_hdr_split == TRUE) { 6747 for (int i = 0; i < sc->pg_pages; i++) 6748 bus_dmamap_sync(sc->pg_bd_chain_tag, 6749 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6750 } 6751 6752 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6753 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6754 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6755 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6756 } 6757 6758 /****************************************************************************/ 6759 /* Reads the transmit consumer value from the status block (skipping over */ 6760 /* chain page pointer if necessary). */ 6761 /* */ 6762 /* Returns: */ 6763 /* hw_cons */ 6764 /****************************************************************************/ 6765 static inline u16 6766 bce_get_hw_tx_cons(struct bce_softc *sc) 6767 { 6768 u16 hw_cons; 6769 6770 mb(); 6771 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6772 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6773 hw_cons++; 6774 6775 return hw_cons; 6776 } 6777 6778 /****************************************************************************/ 6779 /* Handles transmit completion interrupt events. */ 6780 /* */ 6781 /* Returns: */ 6782 /* Nothing. */ 6783 /****************************************************************************/ 6784 static void 6785 bce_tx_intr(struct bce_softc *sc) 6786 { 6787 if_t ifp = sc->bce_ifp; 6788 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6789 6790 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6791 DBRUN(sc->interrupts_tx++); 6792 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6793 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6794 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6795 6796 BCE_LOCK_ASSERT(sc); 6797 6798 /* Get the hardware's view of the TX consumer index. */ 6799 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6800 sw_tx_cons = sc->tx_cons; 6801 6802 /* Prevent speculative reads of the status block. */ 6803 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6804 BUS_SPACE_BARRIER_READ); 6805 6806 /* Cycle through any completed TX chain page entries. */ 6807 while (sw_tx_cons != hw_tx_cons) { 6808 #ifdef BCE_DEBUG 6809 struct tx_bd *txbd = NULL; 6810 #endif 6811 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6812 6813 DBPRINT(sc, BCE_INFO_SEND, 6814 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6815 "sw_tx_chain_cons = 0x%04X\n", 6816 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6817 6818 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6819 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6820 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6821 (int) MAX_TX_BD_ALLOC); 6822 bce_breakpoint(sc)); 6823 6824 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6825 [TX_IDX(sw_tx_chain_cons)]); 6826 6827 DBRUNIF((txbd == NULL), 6828 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6829 __FILE__, __LINE__, sw_tx_chain_cons); 6830 bce_breakpoint(sc)); 6831 6832 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6833 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6834 6835 /* 6836 * Free the associated mbuf. Remember 6837 * that only the last tx_bd of a packet 6838 * has an mbuf pointer and DMA map. 6839 */ 6840 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6841 /* Validate that this is the last tx_bd. */ 6842 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6843 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6844 "txmbuf == NULL!\n", __FILE__, __LINE__); 6845 bce_breakpoint(sc)); 6846 6847 DBRUNMSG(BCE_INFO_SEND, 6848 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6849 "from tx_bd[0x%04X]\n", __FUNCTION__, 6850 sw_tx_chain_cons)); 6851 6852 /* Unmap the mbuf. */ 6853 bus_dmamap_unload(sc->tx_mbuf_tag, 6854 sc->tx_mbuf_map[sw_tx_chain_cons]); 6855 6856 /* Free the mbuf. */ 6857 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6858 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6859 DBRUN(sc->debug_tx_mbuf_alloc--); 6860 6861 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 6862 } 6863 6864 sc->used_tx_bd--; 6865 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6866 6867 /* Refresh hw_cons to see if there's new work. */ 6868 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6869 6870 /* Prevent speculative reads of the status block. */ 6871 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6872 BUS_SPACE_BARRIER_READ); 6873 } 6874 6875 /* Clear the TX timeout timer. */ 6876 sc->watchdog_timer = 0; 6877 6878 /* Clear the tx hardware queue full flag. */ 6879 if (sc->used_tx_bd < sc->max_tx_bd) { 6880 DBRUNIF((if_getdrvflags(ifp) & IFF_DRV_OACTIVE), 6881 DBPRINT(sc, BCE_INFO_SEND, 6882 "%s(): Open TX chain! %d/%d (used/total)\n", 6883 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6884 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 6885 } 6886 6887 sc->tx_cons = sw_tx_cons; 6888 6889 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6890 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6891 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6892 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6893 } 6894 6895 /****************************************************************************/ 6896 /* Disables interrupt generation. */ 6897 /* */ 6898 /* Returns: */ 6899 /* Nothing. */ 6900 /****************************************************************************/ 6901 static void 6902 bce_disable_intr(struct bce_softc *sc) 6903 { 6904 DBENTER(BCE_VERBOSE_INTR); 6905 6906 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6907 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6908 6909 DBEXIT(BCE_VERBOSE_INTR); 6910 } 6911 6912 /****************************************************************************/ 6913 /* Enables interrupt generation. */ 6914 /* */ 6915 /* Returns: */ 6916 /* Nothing. */ 6917 /****************************************************************************/ 6918 static void 6919 bce_enable_intr(struct bce_softc *sc, int coal_now) 6920 { 6921 DBENTER(BCE_VERBOSE_INTR); 6922 6923 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6924 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6925 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6926 6927 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6928 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6929 6930 /* Force an immediate interrupt (whether there is new data or not). */ 6931 if (coal_now) 6932 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6933 6934 DBEXIT(BCE_VERBOSE_INTR); 6935 } 6936 6937 /****************************************************************************/ 6938 /* Handles controller initialization. */ 6939 /* */ 6940 /* Returns: */ 6941 /* Nothing. */ 6942 /****************************************************************************/ 6943 static void 6944 bce_init_locked(struct bce_softc *sc) 6945 { 6946 if_t ifp; 6947 u32 ether_mtu = 0; 6948 6949 DBENTER(BCE_VERBOSE_RESET); 6950 6951 BCE_LOCK_ASSERT(sc); 6952 6953 ifp = sc->bce_ifp; 6954 6955 /* Check if the driver is still running and bail out if it is. */ 6956 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 6957 goto bce_init_locked_exit; 6958 6959 bce_stop(sc); 6960 6961 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6962 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6963 __FILE__, __LINE__); 6964 goto bce_init_locked_exit; 6965 } 6966 6967 if (bce_chipinit(sc)) { 6968 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6969 __FILE__, __LINE__); 6970 goto bce_init_locked_exit; 6971 } 6972 6973 if (bce_blockinit(sc)) { 6974 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6975 __FILE__, __LINE__); 6976 goto bce_init_locked_exit; 6977 } 6978 6979 /* Load our MAC address. */ 6980 bcopy(if_getlladdr(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6981 bce_set_mac_addr(sc); 6982 6983 if (bce_hdr_split == FALSE) 6984 bce_get_rx_buffer_sizes(sc, if_getmtu(ifp)); 6985 /* 6986 * Calculate and program the hardware Ethernet MTU 6987 * size. Be generous on the receive if we have room 6988 * and allowed by the user. 6989 */ 6990 if (bce_strict_rx_mtu == TRUE) 6991 ether_mtu = if_getmtu(ifp); 6992 else { 6993 if (bce_hdr_split == TRUE) { 6994 if (if_getmtu(ifp) <= sc->rx_bd_mbuf_data_len + MCLBYTES) 6995 ether_mtu = sc->rx_bd_mbuf_data_len + 6996 MCLBYTES; 6997 else 6998 ether_mtu = if_getmtu(ifp); 6999 } else { 7000 if (if_getmtu(ifp) <= sc->rx_bd_mbuf_data_len) 7001 ether_mtu = sc->rx_bd_mbuf_data_len; 7002 else 7003 ether_mtu = if_getmtu(ifp); 7004 } 7005 } 7006 7007 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 7008 7009 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 7010 __FUNCTION__, ether_mtu); 7011 7012 /* Program the mtu, enabling jumbo frame support if necessary. */ 7013 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 7014 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 7015 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 7016 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 7017 else 7018 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 7019 7020 /* Program appropriate promiscuous/multicast filtering. */ 7021 bce_set_rx_mode(sc); 7022 7023 if (bce_hdr_split == TRUE) { 7024 /* Init page buffer descriptor chain. */ 7025 bce_init_pg_chain(sc); 7026 } 7027 7028 /* Init RX buffer descriptor chain. */ 7029 bce_init_rx_chain(sc); 7030 7031 /* Init TX buffer descriptor chain. */ 7032 bce_init_tx_chain(sc); 7033 7034 /* Enable host interrupts. */ 7035 bce_enable_intr(sc, 1); 7036 7037 bce_ifmedia_upd_locked(ifp); 7038 7039 /* Let the OS know the driver is up and running. */ 7040 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 7041 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 7042 7043 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7044 7045 bce_init_locked_exit: 7046 DBEXIT(BCE_VERBOSE_RESET); 7047 } 7048 7049 /****************************************************************************/ 7050 /* Initialize the controller just enough so that any management firmware */ 7051 /* running on the device will continue to operate correctly. */ 7052 /* */ 7053 /* Returns: */ 7054 /* Nothing. */ 7055 /****************************************************************************/ 7056 static void 7057 bce_mgmt_init_locked(struct bce_softc *sc) 7058 { 7059 if_t ifp; 7060 7061 DBENTER(BCE_VERBOSE_RESET); 7062 7063 BCE_LOCK_ASSERT(sc); 7064 7065 /* Bail out if management firmware is not running. */ 7066 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 7067 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 7068 "No management firmware running...\n"); 7069 goto bce_mgmt_init_locked_exit; 7070 } 7071 7072 ifp = sc->bce_ifp; 7073 7074 /* Enable all critical blocks in the MAC. */ 7075 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 7076 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 7077 DELAY(20); 7078 7079 bce_ifmedia_upd_locked(ifp); 7080 7081 bce_mgmt_init_locked_exit: 7082 DBEXIT(BCE_VERBOSE_RESET); 7083 } 7084 7085 /****************************************************************************/ 7086 /* Handles controller initialization when called from an unlocked routine. */ 7087 /* */ 7088 /* Returns: */ 7089 /* Nothing. */ 7090 /****************************************************************************/ 7091 static void 7092 bce_init(void *xsc) 7093 { 7094 struct bce_softc *sc = xsc; 7095 7096 DBENTER(BCE_VERBOSE_RESET); 7097 7098 BCE_LOCK(sc); 7099 bce_init_locked(sc); 7100 BCE_UNLOCK(sc); 7101 7102 DBEXIT(BCE_VERBOSE_RESET); 7103 } 7104 7105 /****************************************************************************/ 7106 /* Modifies an mbuf for TSO on the hardware. */ 7107 /* */ 7108 /* Returns: */ 7109 /* Pointer to a modified mbuf. */ 7110 /****************************************************************************/ 7111 static struct mbuf * 7112 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7113 { 7114 struct mbuf *m; 7115 struct ether_header *eh; 7116 struct ip *ip; 7117 struct tcphdr *th; 7118 u16 etype; 7119 int hdr_len __unused, ip_len __unused, ip_hlen = 0, tcp_hlen = 0; 7120 7121 DBRUN(sc->tso_frames_requested++); 7122 7123 ip_len = 0; 7124 /* Controller may modify mbuf chains. */ 7125 if (M_WRITABLE(*m_head) == 0) { 7126 m = m_dup(*m_head, M_NOWAIT); 7127 m_freem(*m_head); 7128 if (m == NULL) { 7129 sc->mbuf_alloc_failed_count++; 7130 *m_head = NULL; 7131 return (NULL); 7132 } 7133 *m_head = m; 7134 } 7135 7136 /* 7137 * For TSO the controller needs two pieces of info, 7138 * the MSS and the IP+TCP options length. 7139 */ 7140 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7141 if (m == NULL) { 7142 *m_head = NULL; 7143 return (NULL); 7144 } 7145 eh = mtod(m, struct ether_header *); 7146 etype = ntohs(eh->ether_type); 7147 7148 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7149 switch (etype) { 7150 case ETHERTYPE_IP: 7151 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7152 /* TSO only supported for TCP protocol. */ 7153 if (ip->ip_p != IPPROTO_TCP) { 7154 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7155 __FILE__, __LINE__); 7156 m_freem(*m_head); 7157 *m_head = NULL; 7158 return (NULL); 7159 } 7160 7161 /* Get IP header length in bytes (min 20) */ 7162 ip_hlen = ip->ip_hl << 2; 7163 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7164 sizeof(struct tcphdr)); 7165 if (m == NULL) { 7166 *m_head = NULL; 7167 return (NULL); 7168 } 7169 7170 /* Get the TCP header length in bytes (min 20) */ 7171 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7172 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7173 tcp_hlen = (th->th_off << 2); 7174 7175 /* Make sure all IP/TCP options live in the same buffer. */ 7176 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7177 tcp_hlen); 7178 if (m == NULL) { 7179 *m_head = NULL; 7180 return (NULL); 7181 } 7182 7183 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7184 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7185 ip_len = ip->ip_len; 7186 ip->ip_len = 0; 7187 ip->ip_sum = 0; 7188 break; 7189 case ETHERTYPE_IPV6: 7190 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7191 __FILE__, __LINE__); 7192 m_freem(*m_head); 7193 *m_head = NULL; 7194 return (NULL); 7195 /* NOT REACHED */ 7196 default: 7197 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7198 __FILE__, __LINE__); 7199 m_freem(*m_head); 7200 *m_head = NULL; 7201 return (NULL); 7202 } 7203 7204 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7205 7206 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7207 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7208 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7209 tcp_hlen, ip_len); 7210 7211 /* Set the LSO flag in the TX BD */ 7212 *flags |= TX_BD_FLAGS_SW_LSO; 7213 7214 /* Set the length of IP + TCP options (in 32 bit words) */ 7215 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7216 sizeof(struct tcphdr)) >> 2) << 8); 7217 7218 DBRUN(sc->tso_frames_completed++); 7219 return (*m_head); 7220 } 7221 7222 /****************************************************************************/ 7223 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7224 /* memory visible to the controller. */ 7225 /* */ 7226 /* Returns: */ 7227 /* 0 for success, positive value for failure. */ 7228 /* Modified: */ 7229 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7230 /****************************************************************************/ 7231 static int 7232 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7233 { 7234 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7235 bus_dmamap_t map; 7236 struct tx_bd *txbd = NULL; 7237 struct mbuf *m0; 7238 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7239 u32 prod_bseq; 7240 7241 #ifdef BCE_DEBUG 7242 u16 debug_prod; 7243 #endif 7244 7245 int i, error, nsegs, rc = 0; 7246 7247 DBENTER(BCE_VERBOSE_SEND); 7248 7249 /* Make sure we have room in the TX chain. */ 7250 if (sc->used_tx_bd >= sc->max_tx_bd) 7251 goto bce_tx_encap_exit; 7252 7253 /* Transfer any checksum offload flags to the bd. */ 7254 m0 = *m_head; 7255 if (m0->m_pkthdr.csum_flags) { 7256 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7257 m0 = bce_tso_setup(sc, m_head, &flags); 7258 if (m0 == NULL) { 7259 DBRUN(sc->tso_frames_failed++); 7260 goto bce_tx_encap_exit; 7261 } 7262 mss = htole16(m0->m_pkthdr.tso_segsz); 7263 } else { 7264 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7265 flags |= TX_BD_FLAGS_IP_CKSUM; 7266 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7267 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7268 } 7269 } 7270 7271 /* Transfer any VLAN tags to the bd. */ 7272 if (m0->m_flags & M_VLANTAG) { 7273 flags |= TX_BD_FLAGS_VLAN_TAG; 7274 vlan_tag = m0->m_pkthdr.ether_vtag; 7275 } 7276 7277 /* Map the mbuf into DMAable memory. */ 7278 prod = sc->tx_prod; 7279 chain_prod = TX_CHAIN_IDX(prod); 7280 map = sc->tx_mbuf_map[chain_prod]; 7281 7282 /* Map the mbuf into our DMA address space. */ 7283 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7284 segs, &nsegs, BUS_DMA_NOWAIT); 7285 7286 /* Check if the DMA mapping was successful */ 7287 if (error == EFBIG) { 7288 sc->mbuf_frag_count++; 7289 7290 /* Try to defrag the mbuf. */ 7291 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS); 7292 if (m0 == NULL) { 7293 /* Defrag was unsuccessful */ 7294 m_freem(*m_head); 7295 *m_head = NULL; 7296 sc->mbuf_alloc_failed_count++; 7297 rc = ENOBUFS; 7298 goto bce_tx_encap_exit; 7299 } 7300 7301 /* Defrag was successful, try mapping again */ 7302 *m_head = m0; 7303 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7304 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7305 7306 /* Still getting an error after a defrag. */ 7307 if (error == ENOMEM) { 7308 /* Insufficient DMA buffers available. */ 7309 sc->dma_map_addr_tx_failed_count++; 7310 rc = error; 7311 goto bce_tx_encap_exit; 7312 } else if (error != 0) { 7313 /* Release it and return an error. */ 7314 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7315 "TX chain!\n", __FILE__, __LINE__); 7316 m_freem(m0); 7317 *m_head = NULL; 7318 sc->dma_map_addr_tx_failed_count++; 7319 rc = ENOBUFS; 7320 goto bce_tx_encap_exit; 7321 } 7322 } else if (error == ENOMEM) { 7323 /* Insufficient DMA buffers available. */ 7324 sc->dma_map_addr_tx_failed_count++; 7325 rc = error; 7326 goto bce_tx_encap_exit; 7327 } else if (error != 0) { 7328 m_freem(m0); 7329 *m_head = NULL; 7330 sc->dma_map_addr_tx_failed_count++; 7331 rc = error; 7332 goto bce_tx_encap_exit; 7333 } 7334 7335 /* Make sure there's room in the chain */ 7336 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7337 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7338 rc = ENOBUFS; 7339 goto bce_tx_encap_exit; 7340 } 7341 7342 /* prod points to an empty tx_bd at this point. */ 7343 prod_bseq = sc->tx_prod_bseq; 7344 7345 #ifdef BCE_DEBUG 7346 debug_prod = chain_prod; 7347 #endif 7348 7349 DBPRINT(sc, BCE_INFO_SEND, 7350 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7351 "prod_bseq = 0x%08X\n", 7352 __FUNCTION__, prod, chain_prod, prod_bseq); 7353 7354 /* 7355 * Cycle through each mbuf segment that makes up 7356 * the outgoing frame, gathering the mapping info 7357 * for that segment and creating a tx_bd for 7358 * the mbuf. 7359 */ 7360 for (i = 0; i < nsegs ; i++) { 7361 chain_prod = TX_CHAIN_IDX(prod); 7362 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7363 [TX_IDX(chain_prod)]; 7364 7365 txbd->tx_bd_haddr_lo = 7366 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7367 txbd->tx_bd_haddr_hi = 7368 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7369 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7370 htole16(segs[i].ds_len); 7371 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7372 txbd->tx_bd_flags = htole16(flags); 7373 prod_bseq += segs[i].ds_len; 7374 if (i == 0) 7375 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7376 prod = NEXT_TX_BD(prod); 7377 } 7378 7379 /* Set the END flag on the last TX buffer descriptor. */ 7380 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7381 7382 DBRUNMSG(BCE_EXTREME_SEND, 7383 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7384 7385 /* 7386 * Ensure that the mbuf pointer for this transmission 7387 * is placed at the array index of the last 7388 * descriptor in this chain. This is done 7389 * because a single map is used for all 7390 * segments of the mbuf and we don't want to 7391 * unload the map before all of the segments 7392 * have been freed. 7393 */ 7394 sc->tx_mbuf_ptr[chain_prod] = m0; 7395 sc->used_tx_bd += nsegs; 7396 7397 /* Update some debug statistic counters */ 7398 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7399 sc->tx_hi_watermark = sc->used_tx_bd); 7400 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7401 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7402 7403 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7404 7405 /* prod points to the next free tx_bd at this point. */ 7406 sc->tx_prod = prod; 7407 sc->tx_prod_bseq = prod_bseq; 7408 7409 /* Tell the chip about the waiting TX frames. */ 7410 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7411 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7412 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7413 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7414 7415 bce_tx_encap_exit: 7416 DBEXIT(BCE_VERBOSE_SEND); 7417 return(rc); 7418 } 7419 7420 /****************************************************************************/ 7421 /* Main transmit routine when called from another routine with a lock. */ 7422 /* */ 7423 /* Returns: */ 7424 /* Nothing. */ 7425 /****************************************************************************/ 7426 static void 7427 bce_start_locked(if_t ifp) 7428 { 7429 struct bce_softc *sc = if_getsoftc(ifp); 7430 struct mbuf *m_head = NULL; 7431 int count = 0; 7432 u16 tx_prod, tx_chain_prod __unused; 7433 7434 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7435 7436 BCE_LOCK_ASSERT(sc); 7437 7438 /* prod points to the next free tx_bd. */ 7439 tx_prod = sc->tx_prod; 7440 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7441 7442 DBPRINT(sc, BCE_INFO_SEND, 7443 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7444 "tx_prod_bseq = 0x%08X\n", 7445 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7446 7447 /* If there's no link or the transmit queue is empty then just exit. */ 7448 if (sc->bce_link_up == FALSE) { 7449 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7450 __FUNCTION__); 7451 goto bce_start_locked_exit; 7452 } 7453 7454 if (if_sendq_empty(ifp)) { 7455 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7456 __FUNCTION__); 7457 goto bce_start_locked_exit; 7458 } 7459 7460 /* 7461 * Keep adding entries while there is space in the ring. 7462 */ 7463 while (sc->used_tx_bd < sc->max_tx_bd) { 7464 /* Check for any frames to send. */ 7465 m_head = if_dequeue(ifp); 7466 7467 /* Stop when the transmit queue is empty. */ 7468 if (m_head == NULL) 7469 break; 7470 7471 /* 7472 * Pack the data into the transmit ring. If we 7473 * don't have room, place the mbuf back at the 7474 * head of the queue and set the OACTIVE flag 7475 * to wait for the NIC to drain the chain. 7476 */ 7477 if (bce_tx_encap(sc, &m_head)) { 7478 if (m_head != NULL) 7479 if_sendq_prepend(ifp, m_head); 7480 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 7481 DBPRINT(sc, BCE_INFO_SEND, 7482 "TX chain is closed for business! Total " 7483 "tx_bd used = %d\n", sc->used_tx_bd); 7484 break; 7485 } 7486 7487 count++; 7488 7489 /* Send a copy of the frame to any BPF listeners. */ 7490 ETHER_BPF_MTAP(ifp, m_head); 7491 } 7492 7493 /* Exit if no packets were dequeued. */ 7494 if (count == 0) { 7495 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7496 "dequeued\n", __FUNCTION__); 7497 goto bce_start_locked_exit; 7498 } 7499 7500 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7501 "send queue.\n", __FUNCTION__, count); 7502 7503 /* Set the tx timeout. */ 7504 sc->watchdog_timer = BCE_TX_TIMEOUT; 7505 7506 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7507 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7508 7509 bce_start_locked_exit: 7510 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7511 } 7512 7513 /****************************************************************************/ 7514 /* Main transmit routine when called from another routine without a lock. */ 7515 /* */ 7516 /* Returns: */ 7517 /* Nothing. */ 7518 /****************************************************************************/ 7519 static void 7520 bce_start(if_t ifp) 7521 { 7522 struct bce_softc *sc = if_getsoftc(ifp); 7523 7524 DBENTER(BCE_VERBOSE_SEND); 7525 7526 BCE_LOCK(sc); 7527 bce_start_locked(ifp); 7528 BCE_UNLOCK(sc); 7529 7530 DBEXIT(BCE_VERBOSE_SEND); 7531 } 7532 7533 /****************************************************************************/ 7534 /* Handles any IOCTL calls from the operating system. */ 7535 /* */ 7536 /* Returns: */ 7537 /* 0 for success, positive value for failure. */ 7538 /****************************************************************************/ 7539 static int 7540 bce_ioctl(if_t ifp, u_long command, caddr_t data) 7541 { 7542 struct bce_softc *sc = if_getsoftc(ifp); 7543 struct ifreq *ifr = (struct ifreq *) data; 7544 struct mii_data *mii; 7545 int mask, error = 0; 7546 7547 DBENTER(BCE_VERBOSE_MISC); 7548 7549 switch(command) { 7550 /* Set the interface MTU. */ 7551 case SIOCSIFMTU: 7552 /* Check that the MTU setting is supported. */ 7553 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7554 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7555 error = EINVAL; 7556 break; 7557 } 7558 7559 DBPRINT(sc, BCE_INFO_MISC, 7560 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7561 (int) if_getmtu(ifp), (int) ifr->ifr_mtu); 7562 7563 BCE_LOCK(sc); 7564 if_setmtu(ifp, ifr->ifr_mtu); 7565 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 7566 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 7567 bce_init_locked(sc); 7568 } 7569 BCE_UNLOCK(sc); 7570 break; 7571 7572 /* Set interface flags. */ 7573 case SIOCSIFFLAGS: 7574 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7575 7576 BCE_LOCK(sc); 7577 7578 /* Check if the interface is up. */ 7579 if (if_getflags(ifp) & IFF_UP) { 7580 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 7581 /* Change promiscuous/multicast flags as necessary. */ 7582 bce_set_rx_mode(sc); 7583 } else { 7584 /* Start the HW */ 7585 bce_init_locked(sc); 7586 } 7587 } else { 7588 /* The interface is down, check if driver is running. */ 7589 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 7590 bce_stop(sc); 7591 7592 /* If MFW is running, restart the controller a bit. */ 7593 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7594 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7595 bce_chipinit(sc); 7596 bce_mgmt_init_locked(sc); 7597 } 7598 } 7599 } 7600 7601 BCE_UNLOCK(sc); 7602 break; 7603 7604 /* Add/Delete multicast address */ 7605 case SIOCADDMULTI: 7606 case SIOCDELMULTI: 7607 DBPRINT(sc, BCE_VERBOSE_MISC, 7608 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7609 7610 BCE_LOCK(sc); 7611 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 7612 bce_set_rx_mode(sc); 7613 BCE_UNLOCK(sc); 7614 7615 break; 7616 7617 /* Set/Get Interface media */ 7618 case SIOCSIFMEDIA: 7619 case SIOCGIFMEDIA: 7620 DBPRINT(sc, BCE_VERBOSE_MISC, 7621 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7622 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 7623 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia, 7624 command); 7625 else { 7626 mii = device_get_softc(sc->bce_miibus); 7627 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 7628 command); 7629 } 7630 break; 7631 7632 /* Set interface capability */ 7633 case SIOCSIFCAP: 7634 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 7635 DBPRINT(sc, BCE_INFO_MISC, 7636 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7637 7638 /* Toggle the TX checksum capabilities enable flag. */ 7639 if (mask & IFCAP_TXCSUM && 7640 if_getcapabilities(ifp) & IFCAP_TXCSUM) { 7641 if_togglecapenable(ifp, IFCAP_TXCSUM); 7642 if (IFCAP_TXCSUM & if_getcapenable(ifp)) 7643 if_sethwassistbits(ifp, BCE_IF_HWASSIST, 0); 7644 else 7645 if_sethwassistbits(ifp, 0, BCE_IF_HWASSIST); 7646 } 7647 7648 /* Toggle the RX checksum capabilities enable flag. */ 7649 if (mask & IFCAP_RXCSUM && 7650 if_getcapabilities(ifp) & IFCAP_RXCSUM) 7651 if_togglecapenable(ifp, IFCAP_RXCSUM); 7652 7653 /* Toggle the TSO capabilities enable flag. */ 7654 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7655 if_getcapabilities(ifp) & IFCAP_TSO4) { 7656 if_togglecapenable(ifp, IFCAP_TSO4); 7657 if (IFCAP_TSO4 & if_getcapenable(ifp)) 7658 if_sethwassistbits(ifp, CSUM_TSO, 0); 7659 else 7660 if_sethwassistbits(ifp, 0, CSUM_TSO); 7661 } 7662 7663 if (mask & IFCAP_VLAN_HWCSUM && 7664 if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) 7665 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 7666 7667 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7668 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 7669 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 7670 /* 7671 * Don't actually disable VLAN tag stripping as 7672 * management firmware (ASF/IPMI/UMP) requires the 7673 * feature. If VLAN tag stripping is disabled driver 7674 * will manually reconstruct the VLAN frame by 7675 * appending stripped VLAN tag. 7676 */ 7677 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7678 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING)) { 7679 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 7680 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 7681 == 0) 7682 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 7683 } 7684 VLAN_CAPABILITIES(ifp); 7685 break; 7686 default: 7687 /* We don't know how to handle the IOCTL, pass it on. */ 7688 error = ether_ioctl(ifp, command, data); 7689 break; 7690 } 7691 7692 DBEXIT(BCE_VERBOSE_MISC); 7693 return(error); 7694 } 7695 7696 /****************************************************************************/ 7697 /* Transmit timeout handler. */ 7698 /* */ 7699 /* Returns: */ 7700 /* Nothing. */ 7701 /****************************************************************************/ 7702 static void 7703 bce_watchdog(struct bce_softc *sc) 7704 { 7705 uint32_t status; 7706 7707 DBENTER(BCE_EXTREME_SEND); 7708 7709 BCE_LOCK_ASSERT(sc); 7710 7711 status = 0; 7712 /* If the watchdog timer hasn't expired then just exit. */ 7713 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7714 goto bce_watchdog_exit; 7715 7716 status = REG_RD(sc, BCE_EMAC_RX_STATUS); 7717 /* If pause frames are active then don't reset the hardware. */ 7718 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) { 7719 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) { 7720 /* 7721 * If link partner has us in XOFF state then wait for 7722 * the condition to clear. 7723 */ 7724 sc->watchdog_timer = BCE_TX_TIMEOUT; 7725 goto bce_watchdog_exit; 7726 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 && 7727 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) { 7728 /* 7729 * If we're not currently XOFF'ed but have recently 7730 * been XOFF'd/XON'd then assume that's delaying TX 7731 * this time around. 7732 */ 7733 sc->watchdog_timer = BCE_TX_TIMEOUT; 7734 goto bce_watchdog_exit; 7735 } 7736 /* 7737 * Any other condition is unexpected and the controller 7738 * should be reset. 7739 */ 7740 } 7741 7742 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7743 __FILE__, __LINE__); 7744 7745 DBRUNMSG(BCE_INFO, 7746 bce_dump_driver_state(sc); 7747 bce_dump_status_block(sc); 7748 bce_dump_stats_block(sc); 7749 bce_dump_ftqs(sc); 7750 bce_dump_txp_state(sc, 0); 7751 bce_dump_rxp_state(sc, 0); 7752 bce_dump_tpat_state(sc, 0); 7753 bce_dump_cp_state(sc, 0); 7754 bce_dump_com_state(sc, 0)); 7755 7756 DBRUN(bce_breakpoint(sc)); 7757 7758 if_setdrvflagbits(sc->bce_ifp, 0, IFF_DRV_RUNNING); 7759 7760 bce_init_locked(sc); 7761 sc->watchdog_timeouts++; 7762 7763 bce_watchdog_exit: 7764 REG_WR(sc, BCE_EMAC_RX_STATUS, status); 7765 DBEXIT(BCE_EXTREME_SEND); 7766 } 7767 7768 /* 7769 * Interrupt handler. 7770 */ 7771 /****************************************************************************/ 7772 /* Main interrupt entry point. Verifies that the controller generated the */ 7773 /* interrupt and then calls a separate routine for handle the various */ 7774 /* interrupt causes (PHY, TX, RX). */ 7775 /* */ 7776 /* Returns: */ 7777 /* Nothing. */ 7778 /****************************************************************************/ 7779 static void 7780 bce_intr(void *xsc) 7781 { 7782 struct bce_softc *sc; 7783 if_t ifp; 7784 u32 status_attn_bits; 7785 u16 hw_rx_cons, hw_tx_cons; 7786 7787 sc = xsc; 7788 ifp = sc->bce_ifp; 7789 7790 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7791 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7792 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7793 7794 BCE_LOCK(sc); 7795 7796 DBRUN(sc->interrupts_generated++); 7797 7798 /* Synchnorize before we read from interface's status block */ 7799 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 7800 7801 /* 7802 * If the hardware status block index matches the last value read 7803 * by the driver and we haven't asserted our interrupt then there's 7804 * nothing to do. This may only happen in case of INTx due to the 7805 * interrupt arriving at the CPU before the status block is updated. 7806 */ 7807 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 && 7808 sc->status_block->status_idx == sc->last_status_idx && 7809 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7810 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7811 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7812 __FUNCTION__); 7813 goto bce_intr_exit; 7814 } 7815 7816 /* Ack the interrupt and stop others from occurring. */ 7817 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7818 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7819 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7820 7821 /* Check if the hardware has finished any work. */ 7822 hw_rx_cons = bce_get_hw_rx_cons(sc); 7823 hw_tx_cons = bce_get_hw_tx_cons(sc); 7824 7825 /* Keep processing data as long as there is work to do. */ 7826 for (;;) { 7827 status_attn_bits = sc->status_block->status_attn_bits; 7828 7829 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7830 BCE_PRINTF("Simulating unexpected status attention " 7831 "bit set."); 7832 sc->unexpected_attention_sim_count++; 7833 status_attn_bits = status_attn_bits | 7834 STATUS_ATTN_BITS_PARITY_ERROR); 7835 7836 /* Was it a link change interrupt? */ 7837 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7838 (sc->status_block->status_attn_bits_ack & 7839 STATUS_ATTN_BITS_LINK_STATE)) { 7840 bce_phy_intr(sc); 7841 7842 /* Clear transient updates during link state change. */ 7843 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7844 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7845 REG_RD(sc, BCE_HC_COMMAND); 7846 } 7847 7848 /* If any other attention is asserted, the chip is toast. */ 7849 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7850 (sc->status_block->status_attn_bits_ack & 7851 ~STATUS_ATTN_BITS_LINK_STATE))) { 7852 sc->unexpected_attention_count++; 7853 7854 BCE_PRINTF("%s(%d): Fatal attention detected: " 7855 "0x%08X\n", __FILE__, __LINE__, 7856 sc->status_block->status_attn_bits); 7857 7858 DBRUNMSG(BCE_FATAL, 7859 if (unexpected_attention_sim_control == 0) 7860 bce_breakpoint(sc)); 7861 7862 bce_init_locked(sc); 7863 goto bce_intr_exit; 7864 } 7865 7866 /* Check for any completed RX frames. */ 7867 if (hw_rx_cons != sc->hw_rx_cons) 7868 bce_rx_intr(sc); 7869 7870 /* Check for any completed TX frames. */ 7871 if (hw_tx_cons != sc->hw_tx_cons) 7872 bce_tx_intr(sc); 7873 7874 /* Save status block index value for the next interrupt. */ 7875 sc->last_status_idx = sc->status_block->status_idx; 7876 7877 /* 7878 * Prevent speculative reads from getting 7879 * ahead of the status block. 7880 */ 7881 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7882 BUS_SPACE_BARRIER_READ); 7883 7884 /* 7885 * If there's no work left then exit the 7886 * interrupt service routine. 7887 */ 7888 hw_rx_cons = bce_get_hw_rx_cons(sc); 7889 hw_tx_cons = bce_get_hw_tx_cons(sc); 7890 7891 if ((hw_rx_cons == sc->hw_rx_cons) && 7892 (hw_tx_cons == sc->hw_tx_cons)) 7893 break; 7894 } 7895 7896 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD); 7897 7898 /* Re-enable interrupts. */ 7899 bce_enable_intr(sc, 0); 7900 7901 /* Handle any frames that arrived while handling the interrupt. */ 7902 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 7903 !if_sendq_empty(ifp)) 7904 bce_start_locked(ifp); 7905 7906 bce_intr_exit: 7907 BCE_UNLOCK(sc); 7908 7909 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7910 } 7911 7912 /****************************************************************************/ 7913 /* Programs the various packet receive modes (broadcast and multicast). */ 7914 /* */ 7915 /* Returns: */ 7916 /* Nothing. */ 7917 /****************************************************************************/ 7918 static u_int 7919 bce_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 7920 { 7921 u32 *hashes = arg; 7922 int h; 7923 7924 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF; 7925 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7926 7927 return (1); 7928 } 7929 7930 static void 7931 bce_set_rx_mode(struct bce_softc *sc) 7932 { 7933 if_t ifp; 7934 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7935 u32 rx_mode, sort_mode; 7936 int i; 7937 7938 DBENTER(BCE_VERBOSE_MISC); 7939 7940 BCE_LOCK_ASSERT(sc); 7941 7942 ifp = sc->bce_ifp; 7943 7944 /* Initialize receive mode default settings. */ 7945 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7946 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7947 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7948 7949 /* 7950 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7951 * be enbled. 7952 */ 7953 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7954 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7955 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7956 7957 /* 7958 * Check for promiscuous, all multicast, or selected 7959 * multicast address filtering. 7960 */ 7961 if (if_getflags(ifp) & IFF_PROMISC) { 7962 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7963 7964 /* Enable promiscuous mode. */ 7965 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7966 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7967 } else if (if_getflags(ifp) & IFF_ALLMULTI) { 7968 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7969 7970 /* Enable all multicast addresses. */ 7971 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7972 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 7973 0xffffffff); 7974 } 7975 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7976 } else { 7977 /* Accept one or more multicast(s). */ 7978 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7979 if_foreach_llmaddr(ifp, bce_hash_maddr, hashes); 7980 7981 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7982 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7983 7984 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7985 } 7986 7987 /* Only make changes if the recive mode has actually changed. */ 7988 if (rx_mode != sc->rx_mode) { 7989 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 7990 "0x%08X\n", rx_mode); 7991 7992 sc->rx_mode = rx_mode; 7993 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7994 } 7995 7996 /* Disable and clear the existing sort before enabling a new sort. */ 7997 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7998 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7999 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 8000 8001 DBEXIT(BCE_VERBOSE_MISC); 8002 } 8003 8004 /****************************************************************************/ 8005 /* Called periodically to updates statistics from the controllers */ 8006 /* statistics block. */ 8007 /* */ 8008 /* Returns: */ 8009 /* Nothing. */ 8010 /****************************************************************************/ 8011 static void 8012 bce_stats_update(struct bce_softc *sc) 8013 { 8014 struct statistics_block *stats; 8015 8016 DBENTER(BCE_EXTREME_MISC); 8017 8018 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 8019 8020 stats = (struct statistics_block *) sc->stats_block; 8021 8022 /* 8023 * Update the sysctl statistics from the 8024 * hardware statistics. 8025 */ 8026 sc->stat_IfHCInOctets = 8027 ((u64) stats->stat_IfHCInOctets_hi << 32) + 8028 (u64) stats->stat_IfHCInOctets_lo; 8029 8030 sc->stat_IfHCInBadOctets = 8031 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 8032 (u64) stats->stat_IfHCInBadOctets_lo; 8033 8034 sc->stat_IfHCOutOctets = 8035 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 8036 (u64) stats->stat_IfHCOutOctets_lo; 8037 8038 sc->stat_IfHCOutBadOctets = 8039 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 8040 (u64) stats->stat_IfHCOutBadOctets_lo; 8041 8042 sc->stat_IfHCInUcastPkts = 8043 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 8044 (u64) stats->stat_IfHCInUcastPkts_lo; 8045 8046 sc->stat_IfHCInMulticastPkts = 8047 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 8048 (u64) stats->stat_IfHCInMulticastPkts_lo; 8049 8050 sc->stat_IfHCInBroadcastPkts = 8051 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 8052 (u64) stats->stat_IfHCInBroadcastPkts_lo; 8053 8054 sc->stat_IfHCOutUcastPkts = 8055 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 8056 (u64) stats->stat_IfHCOutUcastPkts_lo; 8057 8058 sc->stat_IfHCOutMulticastPkts = 8059 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 8060 (u64) stats->stat_IfHCOutMulticastPkts_lo; 8061 8062 sc->stat_IfHCOutBroadcastPkts = 8063 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 8064 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 8065 8066 /* ToDo: Preserve counters beyond 32 bits? */ 8067 /* ToDo: Read the statistics from auto-clear regs? */ 8068 8069 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 8070 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 8071 8072 sc->stat_Dot3StatsCarrierSenseErrors = 8073 stats->stat_Dot3StatsCarrierSenseErrors; 8074 8075 sc->stat_Dot3StatsFCSErrors = 8076 stats->stat_Dot3StatsFCSErrors; 8077 8078 sc->stat_Dot3StatsAlignmentErrors = 8079 stats->stat_Dot3StatsAlignmentErrors; 8080 8081 sc->stat_Dot3StatsSingleCollisionFrames = 8082 stats->stat_Dot3StatsSingleCollisionFrames; 8083 8084 sc->stat_Dot3StatsMultipleCollisionFrames = 8085 stats->stat_Dot3StatsMultipleCollisionFrames; 8086 8087 sc->stat_Dot3StatsDeferredTransmissions = 8088 stats->stat_Dot3StatsDeferredTransmissions; 8089 8090 sc->stat_Dot3StatsExcessiveCollisions = 8091 stats->stat_Dot3StatsExcessiveCollisions; 8092 8093 sc->stat_Dot3StatsLateCollisions = 8094 stats->stat_Dot3StatsLateCollisions; 8095 8096 sc->stat_EtherStatsCollisions = 8097 stats->stat_EtherStatsCollisions; 8098 8099 sc->stat_EtherStatsFragments = 8100 stats->stat_EtherStatsFragments; 8101 8102 sc->stat_EtherStatsJabbers = 8103 stats->stat_EtherStatsJabbers; 8104 8105 sc->stat_EtherStatsUndersizePkts = 8106 stats->stat_EtherStatsUndersizePkts; 8107 8108 sc->stat_EtherStatsOversizePkts = 8109 stats->stat_EtherStatsOversizePkts; 8110 8111 sc->stat_EtherStatsPktsRx64Octets = 8112 stats->stat_EtherStatsPktsRx64Octets; 8113 8114 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8115 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8116 8117 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8118 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8119 8120 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8121 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8122 8123 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8124 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8125 8126 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8127 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8128 8129 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8130 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8131 8132 sc->stat_EtherStatsPktsTx64Octets = 8133 stats->stat_EtherStatsPktsTx64Octets; 8134 8135 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8136 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8137 8138 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8139 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8140 8141 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8142 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8143 8144 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8145 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8146 8147 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8148 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8149 8150 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8151 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8152 8153 sc->stat_XonPauseFramesReceived = 8154 stats->stat_XonPauseFramesReceived; 8155 8156 sc->stat_XoffPauseFramesReceived = 8157 stats->stat_XoffPauseFramesReceived; 8158 8159 sc->stat_OutXonSent = 8160 stats->stat_OutXonSent; 8161 8162 sc->stat_OutXoffSent = 8163 stats->stat_OutXoffSent; 8164 8165 sc->stat_FlowControlDone = 8166 stats->stat_FlowControlDone; 8167 8168 sc->stat_MacControlFramesReceived = 8169 stats->stat_MacControlFramesReceived; 8170 8171 sc->stat_XoffStateEntered = 8172 stats->stat_XoffStateEntered; 8173 8174 sc->stat_IfInFramesL2FilterDiscards = 8175 stats->stat_IfInFramesL2FilterDiscards; 8176 8177 sc->stat_IfInRuleCheckerDiscards = 8178 stats->stat_IfInRuleCheckerDiscards; 8179 8180 sc->stat_IfInFTQDiscards = 8181 stats->stat_IfInFTQDiscards; 8182 8183 sc->stat_IfInMBUFDiscards = 8184 stats->stat_IfInMBUFDiscards; 8185 8186 sc->stat_IfInRuleCheckerP4Hit = 8187 stats->stat_IfInRuleCheckerP4Hit; 8188 8189 sc->stat_CatchupInRuleCheckerDiscards = 8190 stats->stat_CatchupInRuleCheckerDiscards; 8191 8192 sc->stat_CatchupInFTQDiscards = 8193 stats->stat_CatchupInFTQDiscards; 8194 8195 sc->stat_CatchupInMBUFDiscards = 8196 stats->stat_CatchupInMBUFDiscards; 8197 8198 sc->stat_CatchupInRuleCheckerP4Hit = 8199 stats->stat_CatchupInRuleCheckerP4Hit; 8200 8201 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8202 8203 /* ToDo: Add additional statistics? */ 8204 8205 DBEXIT(BCE_EXTREME_MISC); 8206 } 8207 8208 static uint64_t 8209 bce_get_counter(if_t ifp, ift_counter cnt) 8210 { 8211 struct bce_softc *sc; 8212 uint64_t rv; 8213 8214 sc = if_getsoftc(ifp); 8215 8216 switch (cnt) { 8217 case IFCOUNTER_COLLISIONS: 8218 return (sc->stat_EtherStatsCollisions); 8219 case IFCOUNTER_IERRORS: 8220 return (sc->stat_EtherStatsUndersizePkts + 8221 sc->stat_EtherStatsOversizePkts + 8222 sc->stat_IfInMBUFDiscards + 8223 sc->stat_Dot3StatsAlignmentErrors + 8224 sc->stat_Dot3StatsFCSErrors + 8225 sc->stat_IfInRuleCheckerDiscards + 8226 sc->stat_IfInFTQDiscards + 8227 sc->l2fhdr_error_count + 8228 sc->com_no_buffers); 8229 case IFCOUNTER_OERRORS: 8230 rv = sc->stat_Dot3StatsExcessiveCollisions + 8231 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8232 sc->stat_Dot3StatsLateCollisions + 8233 sc->watchdog_timeouts; 8234 /* 8235 * Certain controllers don't report 8236 * carrier sense errors correctly. 8237 * See errata E11_5708CA0_1165. 8238 */ 8239 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 8240 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 8241 rv += sc->stat_Dot3StatsCarrierSenseErrors; 8242 return (rv); 8243 default: 8244 return (if_get_counter_default(ifp, cnt)); 8245 } 8246 } 8247 8248 /****************************************************************************/ 8249 /* Periodic function to notify the bootcode that the driver is still */ 8250 /* present. */ 8251 /* */ 8252 /* Returns: */ 8253 /* Nothing. */ 8254 /****************************************************************************/ 8255 static void 8256 bce_pulse(void *xsc) 8257 { 8258 struct bce_softc *sc = xsc; 8259 u32 msg; 8260 8261 DBENTER(BCE_EXTREME_MISC); 8262 8263 BCE_LOCK_ASSERT(sc); 8264 8265 /* Tell the firmware that the driver is still running. */ 8266 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8267 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8268 8269 /* Update the bootcode condition. */ 8270 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8271 8272 /* Report whether the bootcode still knows the driver is running. */ 8273 if (bce_verbose || bootverbose) { 8274 if (sc->bce_drv_cardiac_arrest == FALSE) { 8275 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8276 sc->bce_drv_cardiac_arrest = TRUE; 8277 BCE_PRINTF("%s(): Warning: bootcode " 8278 "thinks driver is absent! " 8279 "(bc_state = 0x%08X)\n", 8280 __FUNCTION__, sc->bc_state); 8281 } 8282 } else { 8283 /* 8284 * Not supported by all bootcode versions. 8285 * (v5.0.11+ and v5.2.1+) Older bootcode 8286 * will require the driver to reset the 8287 * controller to clear this condition. 8288 */ 8289 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8290 sc->bce_drv_cardiac_arrest = FALSE; 8291 BCE_PRINTF("%s(): Bootcode found the " 8292 "driver pulse! (bc_state = 0x%08X)\n", 8293 __FUNCTION__, sc->bc_state); 8294 } 8295 } 8296 } 8297 8298 /* Schedule the next pulse. */ 8299 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8300 8301 DBEXIT(BCE_EXTREME_MISC); 8302 } 8303 8304 /****************************************************************************/ 8305 /* Periodic function to perform maintenance tasks. */ 8306 /* */ 8307 /* Returns: */ 8308 /* Nothing. */ 8309 /****************************************************************************/ 8310 static void 8311 bce_tick(void *xsc) 8312 { 8313 struct bce_softc *sc = xsc; 8314 struct mii_data *mii; 8315 if_t ifp; 8316 struct ifmediareq ifmr; 8317 8318 ifp = sc->bce_ifp; 8319 8320 DBENTER(BCE_EXTREME_MISC); 8321 8322 BCE_LOCK_ASSERT(sc); 8323 8324 /* Schedule the next tick. */ 8325 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8326 8327 /* Update the statistics from the hardware statistics block. */ 8328 bce_stats_update(sc); 8329 8330 /* Ensure page and RX chains get refilled in low-memory situations. */ 8331 if (bce_hdr_split == TRUE) 8332 bce_fill_pg_chain(sc); 8333 bce_fill_rx_chain(sc); 8334 8335 /* Check that chip hasn't hung. */ 8336 bce_watchdog(sc); 8337 8338 /* If link is up already up then we're done. */ 8339 if (sc->bce_link_up == TRUE) 8340 goto bce_tick_exit; 8341 8342 /* Link is down. Check what the PHY's doing. */ 8343 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 8344 bzero(&ifmr, sizeof(ifmr)); 8345 bce_ifmedia_sts_rphy(sc, &ifmr); 8346 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) == 8347 (IFM_ACTIVE | IFM_AVALID)) { 8348 sc->bce_link_up = TRUE; 8349 bce_miibus_statchg(sc->bce_dev); 8350 } 8351 } else { 8352 mii = device_get_softc(sc->bce_miibus); 8353 mii_tick(mii); 8354 /* Check if the link has come up. */ 8355 if ((mii->mii_media_status & IFM_ACTIVE) && 8356 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8357 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", 8358 __FUNCTION__); 8359 sc->bce_link_up = TRUE; 8360 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8361 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8362 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8363 (bce_verbose || bootverbose)) 8364 BCE_PRINTF("Gigabit link up!\n"); 8365 } 8366 } 8367 if (sc->bce_link_up == TRUE) { 8368 /* Now that link is up, handle any outstanding TX traffic. */ 8369 if (!if_sendq_empty(ifp)) { 8370 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8371 "pending TX traffic.\n", __FUNCTION__); 8372 bce_start_locked(ifp); 8373 } 8374 } 8375 8376 bce_tick_exit: 8377 DBEXIT(BCE_EXTREME_MISC); 8378 } 8379 8380 static void 8381 bce_fw_cap_init(struct bce_softc *sc) 8382 { 8383 u32 ack, cap, link; 8384 8385 ack = 0; 8386 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB); 8387 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) != 8388 BCE_FW_CAP_SIGNATURE_MAGIC) 8389 return; 8390 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) == 8391 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) 8392 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8393 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN; 8394 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 && 8395 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) { 8396 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8397 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG; 8398 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 8399 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0) 8400 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8401 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8402 BCE_FW_CAP_REMOTE_PHY_CAP; 8403 } 8404 8405 if (ack != 0) 8406 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack); 8407 } 8408 8409 #ifdef BCE_DEBUG 8410 /****************************************************************************/ 8411 /* Allows the driver state to be dumped through the sysctl interface. */ 8412 /* */ 8413 /* Returns: */ 8414 /* 0 for success, positive value for failure. */ 8415 /****************************************************************************/ 8416 static int 8417 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8418 { 8419 int error; 8420 int result; 8421 struct bce_softc *sc; 8422 8423 result = -1; 8424 error = sysctl_handle_int(oidp, &result, 0, req); 8425 8426 if (error || !req->newptr) 8427 return (error); 8428 8429 if (result == 1) { 8430 sc = (struct bce_softc *)arg1; 8431 bce_dump_driver_state(sc); 8432 } 8433 8434 return error; 8435 } 8436 8437 /****************************************************************************/ 8438 /* Allows the hardware state to be dumped through the sysctl interface. */ 8439 /* */ 8440 /* Returns: */ 8441 /* 0 for success, positive value for failure. */ 8442 /****************************************************************************/ 8443 static int 8444 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8445 { 8446 int error; 8447 int result; 8448 struct bce_softc *sc; 8449 8450 result = -1; 8451 error = sysctl_handle_int(oidp, &result, 0, req); 8452 8453 if (error || !req->newptr) 8454 return (error); 8455 8456 if (result == 1) { 8457 sc = (struct bce_softc *)arg1; 8458 bce_dump_hw_state(sc); 8459 } 8460 8461 return error; 8462 } 8463 8464 /****************************************************************************/ 8465 /* Allows the status block to be dumped through the sysctl interface. */ 8466 /* */ 8467 /* Returns: */ 8468 /* 0 for success, positive value for failure. */ 8469 /****************************************************************************/ 8470 static int 8471 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8472 { 8473 int error; 8474 int result; 8475 struct bce_softc *sc; 8476 8477 result = -1; 8478 error = sysctl_handle_int(oidp, &result, 0, req); 8479 8480 if (error || !req->newptr) 8481 return (error); 8482 8483 if (result == 1) { 8484 sc = (struct bce_softc *)arg1; 8485 bce_dump_status_block(sc); 8486 } 8487 8488 return error; 8489 } 8490 8491 /****************************************************************************/ 8492 /* Allows the stats block to be dumped through the sysctl interface. */ 8493 /* */ 8494 /* Returns: */ 8495 /* 0 for success, positive value for failure. */ 8496 /****************************************************************************/ 8497 static int 8498 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8499 { 8500 int error; 8501 int result; 8502 struct bce_softc *sc; 8503 8504 result = -1; 8505 error = sysctl_handle_int(oidp, &result, 0, req); 8506 8507 if (error || !req->newptr) 8508 return (error); 8509 8510 if (result == 1) { 8511 sc = (struct bce_softc *)arg1; 8512 bce_dump_stats_block(sc); 8513 } 8514 8515 return error; 8516 } 8517 8518 /****************************************************************************/ 8519 /* Allows the stat counters to be cleared without unloading/reloading the */ 8520 /* driver. */ 8521 /* */ 8522 /* Returns: */ 8523 /* 0 for success, positive value for failure. */ 8524 /****************************************************************************/ 8525 static int 8526 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8527 { 8528 int error; 8529 int result; 8530 struct bce_softc *sc; 8531 8532 result = -1; 8533 error = sysctl_handle_int(oidp, &result, 0, req); 8534 8535 if (error || !req->newptr) 8536 return (error); 8537 8538 if (result == 1) { 8539 sc = (struct bce_softc *)arg1; 8540 struct statistics_block *stats; 8541 8542 stats = (struct statistics_block *) sc->stats_block; 8543 bzero(stats, sizeof(struct statistics_block)); 8544 bus_dmamap_sync(sc->stats_tag, sc->stats_map, 8545 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 8546 8547 /* Clear the internal H/W statistics counters. */ 8548 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8549 8550 /* Reset the driver maintained statistics. */ 8551 sc->interrupts_rx = 8552 sc->interrupts_tx = 0; 8553 sc->tso_frames_requested = 8554 sc->tso_frames_completed = 8555 sc->tso_frames_failed = 0; 8556 sc->rx_empty_count = 8557 sc->tx_full_count = 0; 8558 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8559 sc->tx_hi_watermark = 0; 8560 sc->l2fhdr_error_count = 8561 sc->l2fhdr_error_sim_count = 0; 8562 sc->mbuf_alloc_failed_count = 8563 sc->mbuf_alloc_failed_sim_count = 0; 8564 sc->dma_map_addr_rx_failed_count = 8565 sc->dma_map_addr_tx_failed_count = 0; 8566 sc->mbuf_frag_count = 0; 8567 sc->csum_offload_tcp_udp = 8568 sc->csum_offload_ip = 0; 8569 sc->vlan_tagged_frames_rcvd = 8570 sc->vlan_tagged_frames_stripped = 0; 8571 sc->split_header_frames_rcvd = 8572 sc->split_header_tcp_frames_rcvd = 0; 8573 8574 /* Clear firmware maintained statistics. */ 8575 REG_WR_IND(sc, 0x120084, 0); 8576 } 8577 8578 return error; 8579 } 8580 8581 /****************************************************************************/ 8582 /* Allows the shared memory contents to be dumped through the sysctl . */ 8583 /* interface. */ 8584 /* */ 8585 /* Returns: */ 8586 /* 0 for success, positive value for failure. */ 8587 /****************************************************************************/ 8588 static int 8589 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8590 { 8591 int error; 8592 int result; 8593 struct bce_softc *sc; 8594 8595 result = -1; 8596 error = sysctl_handle_int(oidp, &result, 0, req); 8597 8598 if (error || !req->newptr) 8599 return (error); 8600 8601 if (result == 1) { 8602 sc = (struct bce_softc *)arg1; 8603 bce_dump_shmem_state(sc); 8604 } 8605 8606 return error; 8607 } 8608 8609 /****************************************************************************/ 8610 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8611 /* */ 8612 /* Returns: */ 8613 /* 0 for success, positive value for failure. */ 8614 /****************************************************************************/ 8615 static int 8616 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8617 { 8618 int error; 8619 int result; 8620 struct bce_softc *sc; 8621 8622 result = -1; 8623 error = sysctl_handle_int(oidp, &result, 0, req); 8624 8625 if (error || !req->newptr) 8626 return (error); 8627 8628 if (result == 1) { 8629 sc = (struct bce_softc *)arg1; 8630 bce_dump_bc_state(sc); 8631 } 8632 8633 return error; 8634 } 8635 8636 /****************************************************************************/ 8637 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8638 /* */ 8639 /* Returns: */ 8640 /* 0 for success, positive value for failure. */ 8641 /****************************************************************************/ 8642 static int 8643 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8644 { 8645 int error; 8646 int result; 8647 struct bce_softc *sc; 8648 8649 result = -1; 8650 error = sysctl_handle_int(oidp, &result, 0, req); 8651 8652 if (error || !req->newptr) 8653 return (error); 8654 8655 if (result == 1) { 8656 sc = (struct bce_softc *)arg1; 8657 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8658 } 8659 8660 return error; 8661 } 8662 8663 /****************************************************************************/ 8664 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8665 /* */ 8666 /* Returns: */ 8667 /* 0 for success, positive value for failure. */ 8668 /****************************************************************************/ 8669 static int 8670 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8671 { 8672 int error; 8673 int result; 8674 struct bce_softc *sc; 8675 8676 result = -1; 8677 error = sysctl_handle_int(oidp, &result, 0, req); 8678 8679 if (error || !req->newptr) 8680 return (error); 8681 8682 if (result == 1) { 8683 sc = (struct bce_softc *)arg1; 8684 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8685 } 8686 8687 return error; 8688 } 8689 8690 /****************************************************************************/ 8691 /* Provides a sysctl interface to allow dumping the TX chain. */ 8692 /* */ 8693 /* Returns: */ 8694 /* 0 for success, positive value for failure. */ 8695 /****************************************************************************/ 8696 static int 8697 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8698 { 8699 int error; 8700 int result; 8701 struct bce_softc *sc; 8702 8703 result = -1; 8704 error = sysctl_handle_int(oidp, &result, 0, req); 8705 8706 if (error || !req->newptr) 8707 return (error); 8708 8709 if (result == 1) { 8710 sc = (struct bce_softc *)arg1; 8711 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8712 } 8713 8714 return error; 8715 } 8716 8717 /****************************************************************************/ 8718 /* Provides a sysctl interface to allow dumping the page chain. */ 8719 /* */ 8720 /* Returns: */ 8721 /* 0 for success, positive value for failure. */ 8722 /****************************************************************************/ 8723 static int 8724 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8725 { 8726 int error; 8727 int result; 8728 struct bce_softc *sc; 8729 8730 result = -1; 8731 error = sysctl_handle_int(oidp, &result, 0, req); 8732 8733 if (error || !req->newptr) 8734 return (error); 8735 8736 if (result == 1) { 8737 sc = (struct bce_softc *)arg1; 8738 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8739 } 8740 8741 return error; 8742 } 8743 8744 /****************************************************************************/ 8745 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8746 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8747 /* */ 8748 /* Returns: */ 8749 /* 0 for success, positive value for failure. */ 8750 /****************************************************************************/ 8751 static int 8752 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8753 { 8754 struct bce_softc *sc = (struct bce_softc *)arg1; 8755 int error; 8756 u32 result; 8757 u32 val[1]; 8758 u8 *data = (u8 *) val; 8759 8760 result = -1; 8761 error = sysctl_handle_int(oidp, &result, 0, req); 8762 if (error || (req->newptr == NULL)) 8763 return (error); 8764 8765 error = bce_nvram_read(sc, result, data, 4); 8766 8767 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8768 8769 return (error); 8770 } 8771 8772 /****************************************************************************/ 8773 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8774 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8775 /* */ 8776 /* Returns: */ 8777 /* 0 for success, positive value for failure. */ 8778 /****************************************************************************/ 8779 static int 8780 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8781 { 8782 struct bce_softc *sc = (struct bce_softc *)arg1; 8783 int error; 8784 u32 val, result; 8785 8786 result = -1; 8787 error = sysctl_handle_int(oidp, &result, 0, req); 8788 if (error || (req->newptr == NULL)) 8789 return (error); 8790 8791 /* Make sure the register is accessible. */ 8792 if (result < 0x8000) { 8793 val = REG_RD(sc, result); 8794 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8795 } else if (result < 0x0280000) { 8796 val = REG_RD_IND(sc, result); 8797 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8798 } 8799 8800 return (error); 8801 } 8802 8803 /****************************************************************************/ 8804 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8805 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8806 /* */ 8807 /* Returns: */ 8808 /* 0 for success, positive value for failure. */ 8809 /****************************************************************************/ 8810 static int 8811 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8812 { 8813 struct bce_softc *sc; 8814 device_t dev; 8815 int error, result; 8816 u16 val; 8817 8818 result = -1; 8819 error = sysctl_handle_int(oidp, &result, 0, req); 8820 if (error || (req->newptr == NULL)) 8821 return (error); 8822 8823 /* Make sure the register is accessible. */ 8824 if (result < 0x20) { 8825 sc = (struct bce_softc *)arg1; 8826 dev = sc->bce_dev; 8827 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8828 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8829 } 8830 return (error); 8831 } 8832 8833 /****************************************************************************/ 8834 /* Provides a sysctl interface for dumping the nvram contents. */ 8835 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8836 /* */ 8837 /* Returns: */ 8838 /* 0 for success, positive errno for failure. */ 8839 /****************************************************************************/ 8840 static int 8841 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 8842 { 8843 struct bce_softc *sc = (struct bce_softc *)arg1; 8844 int error, i; 8845 8846 if (sc->nvram_buf == NULL) 8847 sc->nvram_buf = malloc(sc->bce_flash_size, 8848 M_TEMP, M_ZERO | M_WAITOK); 8849 8850 error = 0; 8851 if (req->oldlen == sc->bce_flash_size) { 8852 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 8853 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 8854 } 8855 8856 if (error == 0) 8857 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 8858 8859 return error; 8860 } 8861 8862 #ifdef BCE_NVRAM_WRITE_SUPPORT 8863 /****************************************************************************/ 8864 /* Provides a sysctl interface for writing to nvram. */ 8865 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8866 /* */ 8867 /* Returns: */ 8868 /* 0 for success, positive errno for failure. */ 8869 /****************************************************************************/ 8870 static int 8871 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 8872 { 8873 struct bce_softc *sc = (struct bce_softc *)arg1; 8874 int error; 8875 8876 if (sc->nvram_buf == NULL) 8877 sc->nvram_buf = malloc(sc->bce_flash_size, 8878 M_TEMP, M_ZERO | M_WAITOK); 8879 else 8880 bzero(sc->nvram_buf, sc->bce_flash_size); 8881 8882 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 8883 if (error == 0) 8884 return (error); 8885 8886 if (req->newlen == sc->bce_flash_size) 8887 error = bce_nvram_write(sc, 0, sc->nvram_buf, 8888 sc->bce_flash_size); 8889 8890 return error; 8891 } 8892 #endif 8893 8894 /****************************************************************************/ 8895 /* Provides a sysctl interface to allow reading a CID. */ 8896 /* */ 8897 /* Returns: */ 8898 /* 0 for success, positive value for failure. */ 8899 /****************************************************************************/ 8900 static int 8901 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8902 { 8903 struct bce_softc *sc; 8904 int error, result; 8905 8906 result = -1; 8907 error = sysctl_handle_int(oidp, &result, 0, req); 8908 if (error || (req->newptr == NULL)) 8909 return (error); 8910 8911 /* Make sure the register is accessible. */ 8912 if (result <= TX_CID) { 8913 sc = (struct bce_softc *)arg1; 8914 bce_dump_ctx(sc, result); 8915 } 8916 8917 return (error); 8918 } 8919 8920 /****************************************************************************/ 8921 /* Provides a sysctl interface to forcing the driver to dump state and */ 8922 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8923 /* */ 8924 /* Returns: */ 8925 /* 0 for success, positive value for failure. */ 8926 /****************************************************************************/ 8927 static int 8928 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8929 { 8930 int error; 8931 int result; 8932 struct bce_softc *sc; 8933 8934 result = -1; 8935 error = sysctl_handle_int(oidp, &result, 0, req); 8936 8937 if (error || !req->newptr) 8938 return (error); 8939 8940 if (result == 1) { 8941 sc = (struct bce_softc *)arg1; 8942 bce_breakpoint(sc); 8943 } 8944 8945 return error; 8946 } 8947 #endif 8948 8949 /****************************************************************************/ 8950 /* Adds any sysctl parameters for tuning or debugging purposes. */ 8951 /* */ 8952 /* Returns: */ 8953 /* 0 for success, positive value for failure. */ 8954 /****************************************************************************/ 8955 static void 8956 bce_add_sysctls(struct bce_softc *sc) 8957 { 8958 struct sysctl_ctx_list *ctx; 8959 struct sysctl_oid_list *children; 8960 8961 DBENTER(BCE_VERBOSE_MISC); 8962 8963 ctx = device_get_sysctl_ctx(sc->bce_dev); 8964 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8965 8966 #ifdef BCE_DEBUG 8967 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8968 "l2fhdr_error_sim_control", 8969 CTLFLAG_RW, &l2fhdr_error_sim_control, 8970 0, "Debug control to force l2fhdr errors"); 8971 8972 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8973 "l2fhdr_error_sim_count", 8974 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8975 0, "Number of simulated l2_fhdr errors"); 8976 #endif 8977 8978 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8979 "l2fhdr_error_count", 8980 CTLFLAG_RD, &sc->l2fhdr_error_count, 8981 0, "Number of l2_fhdr errors"); 8982 8983 #ifdef BCE_DEBUG 8984 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8985 "mbuf_alloc_failed_sim_control", 8986 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8987 0, "Debug control to force mbuf allocation failures"); 8988 8989 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8990 "mbuf_alloc_failed_sim_count", 8991 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8992 0, "Number of simulated mbuf cluster allocation failures"); 8993 #endif 8994 8995 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8996 "mbuf_alloc_failed_count", 8997 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 8998 0, "Number of mbuf allocation failures"); 8999 9000 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9001 "mbuf_frag_count", 9002 CTLFLAG_RD, &sc->mbuf_frag_count, 9003 0, "Number of fragmented mbufs"); 9004 9005 #ifdef BCE_DEBUG 9006 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9007 "dma_map_addr_failed_sim_control", 9008 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 9009 0, "Debug control to force DMA mapping failures"); 9010 9011 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 9012 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9013 "dma_map_addr_failed_sim_count", 9014 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 9015 0, "Number of simulated DMA mapping failures"); 9016 9017 #endif 9018 9019 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9020 "dma_map_addr_rx_failed_count", 9021 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 9022 0, "Number of RX DMA mapping failures"); 9023 9024 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9025 "dma_map_addr_tx_failed_count", 9026 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 9027 0, "Number of TX DMA mapping failures"); 9028 9029 #ifdef BCE_DEBUG 9030 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9031 "unexpected_attention_sim_control", 9032 CTLFLAG_RW, &unexpected_attention_sim_control, 9033 0, "Debug control to simulate unexpected attentions"); 9034 9035 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9036 "unexpected_attention_sim_count", 9037 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 9038 0, "Number of simulated unexpected attentions"); 9039 #endif 9040 9041 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9042 "unexpected_attention_count", 9043 CTLFLAG_RW, &sc->unexpected_attention_count, 9044 0, "Number of unexpected attentions"); 9045 9046 #ifdef BCE_DEBUG 9047 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9048 "debug_bootcode_running_failure", 9049 CTLFLAG_RW, &bootcode_running_failure_sim_control, 9050 0, "Debug control to force bootcode running failures"); 9051 9052 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9053 "rx_low_watermark", 9054 CTLFLAG_RD, &sc->rx_low_watermark, 9055 0, "Lowest level of free rx_bd's"); 9056 9057 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9058 "rx_empty_count", 9059 CTLFLAG_RD, &sc->rx_empty_count, 9060 "Number of times the RX chain was empty"); 9061 9062 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9063 "tx_hi_watermark", 9064 CTLFLAG_RD, &sc->tx_hi_watermark, 9065 0, "Highest level of used tx_bd's"); 9066 9067 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9068 "tx_full_count", 9069 CTLFLAG_RD, &sc->tx_full_count, 9070 "Number of times the TX chain was full"); 9071 9072 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9073 "tso_frames_requested", 9074 CTLFLAG_RD, &sc->tso_frames_requested, 9075 "Number of TSO frames requested"); 9076 9077 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9078 "tso_frames_completed", 9079 CTLFLAG_RD, &sc->tso_frames_completed, 9080 "Number of TSO frames completed"); 9081 9082 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9083 "tso_frames_failed", 9084 CTLFLAG_RD, &sc->tso_frames_failed, 9085 "Number of TSO frames failed"); 9086 9087 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9088 "csum_offload_ip", 9089 CTLFLAG_RD, &sc->csum_offload_ip, 9090 "Number of IP checksum offload frames"); 9091 9092 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9093 "csum_offload_tcp_udp", 9094 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 9095 "Number of TCP/UDP checksum offload frames"); 9096 9097 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9098 "vlan_tagged_frames_rcvd", 9099 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 9100 "Number of VLAN tagged frames received"); 9101 9102 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9103 "vlan_tagged_frames_stripped", 9104 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 9105 "Number of VLAN tagged frames stripped"); 9106 9107 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9108 "interrupts_rx", 9109 CTLFLAG_RD, &sc->interrupts_rx, 9110 "Number of RX interrupts"); 9111 9112 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9113 "interrupts_tx", 9114 CTLFLAG_RD, &sc->interrupts_tx, 9115 "Number of TX interrupts"); 9116 9117 if (bce_hdr_split == TRUE) { 9118 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9119 "split_header_frames_rcvd", 9120 CTLFLAG_RD, &sc->split_header_frames_rcvd, 9121 "Number of split header frames received"); 9122 9123 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9124 "split_header_tcp_frames_rcvd", 9125 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 9126 "Number of split header TCP frames received"); 9127 } 9128 9129 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9130 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 9131 (void *)sc, 0, 9132 bce_sysctl_nvram_dump, "S", ""); 9133 9134 #ifdef BCE_NVRAM_WRITE_SUPPORT 9135 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9136 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR | CTLFLAG_NEEDGIANT, 9137 (void *)sc, 0, 9138 bce_sysctl_nvram_write, "S", ""); 9139 #endif 9140 #endif /* BCE_DEBUG */ 9141 9142 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9143 "stat_IfHcInOctets", 9144 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9145 "Bytes received"); 9146 9147 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9148 "stat_IfHCInBadOctets", 9149 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9150 "Bad bytes received"); 9151 9152 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9153 "stat_IfHCOutOctets", 9154 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9155 "Bytes sent"); 9156 9157 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9158 "stat_IfHCOutBadOctets", 9159 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9160 "Bad bytes sent"); 9161 9162 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9163 "stat_IfHCInUcastPkts", 9164 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9165 "Unicast packets received"); 9166 9167 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9168 "stat_IfHCInMulticastPkts", 9169 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9170 "Multicast packets received"); 9171 9172 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9173 "stat_IfHCInBroadcastPkts", 9174 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9175 "Broadcast packets received"); 9176 9177 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9178 "stat_IfHCOutUcastPkts", 9179 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9180 "Unicast packets sent"); 9181 9182 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9183 "stat_IfHCOutMulticastPkts", 9184 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9185 "Multicast packets sent"); 9186 9187 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9188 "stat_IfHCOutBroadcastPkts", 9189 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9190 "Broadcast packets sent"); 9191 9192 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9193 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9194 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9195 0, "Internal MAC transmit errors"); 9196 9197 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9198 "stat_Dot3StatsCarrierSenseErrors", 9199 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9200 0, "Carrier sense errors"); 9201 9202 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9203 "stat_Dot3StatsFCSErrors", 9204 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9205 0, "Frame check sequence errors"); 9206 9207 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9208 "stat_Dot3StatsAlignmentErrors", 9209 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9210 0, "Alignment errors"); 9211 9212 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9213 "stat_Dot3StatsSingleCollisionFrames", 9214 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9215 0, "Single Collision Frames"); 9216 9217 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9218 "stat_Dot3StatsMultipleCollisionFrames", 9219 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9220 0, "Multiple Collision Frames"); 9221 9222 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9223 "stat_Dot3StatsDeferredTransmissions", 9224 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9225 0, "Deferred Transmissions"); 9226 9227 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9228 "stat_Dot3StatsExcessiveCollisions", 9229 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9230 0, "Excessive Collisions"); 9231 9232 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9233 "stat_Dot3StatsLateCollisions", 9234 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9235 0, "Late Collisions"); 9236 9237 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9238 "stat_EtherStatsCollisions", 9239 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9240 0, "Collisions"); 9241 9242 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9243 "stat_EtherStatsFragments", 9244 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9245 0, "Fragments"); 9246 9247 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9248 "stat_EtherStatsJabbers", 9249 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9250 0, "Jabbers"); 9251 9252 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9253 "stat_EtherStatsUndersizePkts", 9254 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9255 0, "Undersize packets"); 9256 9257 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9258 "stat_EtherStatsOversizePkts", 9259 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9260 0, "stat_EtherStatsOversizePkts"); 9261 9262 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9263 "stat_EtherStatsPktsRx64Octets", 9264 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9265 0, "Bytes received in 64 byte packets"); 9266 9267 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9268 "stat_EtherStatsPktsRx65Octetsto127Octets", 9269 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9270 0, "Bytes received in 65 to 127 byte packets"); 9271 9272 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9273 "stat_EtherStatsPktsRx128Octetsto255Octets", 9274 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9275 0, "Bytes received in 128 to 255 byte packets"); 9276 9277 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9278 "stat_EtherStatsPktsRx256Octetsto511Octets", 9279 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9280 0, "Bytes received in 256 to 511 byte packets"); 9281 9282 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9283 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9284 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9285 0, "Bytes received in 512 to 1023 byte packets"); 9286 9287 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9288 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9289 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9290 0, "Bytes received in 1024 t0 1522 byte packets"); 9291 9292 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9293 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9294 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9295 0, "Bytes received in 1523 to 9022 byte packets"); 9296 9297 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9298 "stat_EtherStatsPktsTx64Octets", 9299 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9300 0, "Bytes sent in 64 byte packets"); 9301 9302 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9303 "stat_EtherStatsPktsTx65Octetsto127Octets", 9304 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9305 0, "Bytes sent in 65 to 127 byte packets"); 9306 9307 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9308 "stat_EtherStatsPktsTx128Octetsto255Octets", 9309 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9310 0, "Bytes sent in 128 to 255 byte packets"); 9311 9312 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9313 "stat_EtherStatsPktsTx256Octetsto511Octets", 9314 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9315 0, "Bytes sent in 256 to 511 byte packets"); 9316 9317 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9318 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9319 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9320 0, "Bytes sent in 512 to 1023 byte packets"); 9321 9322 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9323 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9324 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9325 0, "Bytes sent in 1024 to 1522 byte packets"); 9326 9327 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9328 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9329 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9330 0, "Bytes sent in 1523 to 9022 byte packets"); 9331 9332 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9333 "stat_XonPauseFramesReceived", 9334 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9335 0, "XON pause frames receved"); 9336 9337 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9338 "stat_XoffPauseFramesReceived", 9339 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9340 0, "XOFF pause frames received"); 9341 9342 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9343 "stat_OutXonSent", 9344 CTLFLAG_RD, &sc->stat_OutXonSent, 9345 0, "XON pause frames sent"); 9346 9347 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9348 "stat_OutXoffSent", 9349 CTLFLAG_RD, &sc->stat_OutXoffSent, 9350 0, "XOFF pause frames sent"); 9351 9352 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9353 "stat_FlowControlDone", 9354 CTLFLAG_RD, &sc->stat_FlowControlDone, 9355 0, "Flow control done"); 9356 9357 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9358 "stat_MacControlFramesReceived", 9359 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9360 0, "MAC control frames received"); 9361 9362 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9363 "stat_XoffStateEntered", 9364 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9365 0, "XOFF state entered"); 9366 9367 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9368 "stat_IfInFramesL2FilterDiscards", 9369 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9370 0, "Received L2 packets discarded"); 9371 9372 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9373 "stat_IfInRuleCheckerDiscards", 9374 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9375 0, "Received packets discarded by rule"); 9376 9377 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9378 "stat_IfInFTQDiscards", 9379 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9380 0, "Received packet FTQ discards"); 9381 9382 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9383 "stat_IfInMBUFDiscards", 9384 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9385 0, "Received packets discarded due to lack " 9386 "of controller buffer memory"); 9387 9388 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9389 "stat_IfInRuleCheckerP4Hit", 9390 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9391 0, "Received packets rule checker hits"); 9392 9393 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9394 "stat_CatchupInRuleCheckerDiscards", 9395 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9396 0, "Received packets discarded in Catchup path"); 9397 9398 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9399 "stat_CatchupInFTQDiscards", 9400 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9401 0, "Received packets discarded in FTQ in Catchup path"); 9402 9403 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9404 "stat_CatchupInMBUFDiscards", 9405 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9406 0, "Received packets discarded in controller " 9407 "buffer memory in Catchup path"); 9408 9409 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9410 "stat_CatchupInRuleCheckerP4Hit", 9411 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9412 0, "Received packets rule checker hits in Catchup path"); 9413 9414 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9415 "com_no_buffers", 9416 CTLFLAG_RD, &sc->com_no_buffers, 9417 0, "Valid packets received but no RX buffers available"); 9418 9419 #ifdef BCE_DEBUG 9420 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9421 "driver_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9422 (void *)sc, 0, 9423 bce_sysctl_driver_state, "I", "Drive state information"); 9424 9425 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9426 "hw_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9427 (void *)sc, 0, 9428 bce_sysctl_hw_state, "I", "Hardware state information"); 9429 9430 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9431 "status_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9432 (void *)sc, 0, 9433 bce_sysctl_status_block, "I", "Dump status block"); 9434 9435 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9436 "stats_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9437 (void *)sc, 0, 9438 bce_sysctl_stats_block, "I", "Dump statistics block"); 9439 9440 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9441 "stats_clear", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9442 (void *)sc, 0, 9443 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9444 9445 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9446 "shmem_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9447 (void *)sc, 0, 9448 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9449 9450 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9451 "bc_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9452 (void *)sc, 0, 9453 bce_sysctl_bc_state, "I", "Bootcode state information"); 9454 9455 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9456 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9457 (void *)sc, 0, 9458 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9459 9460 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9461 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9462 (void *)sc, 0, 9463 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9464 9465 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9466 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9467 (void *)sc, 0, 9468 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9469 9470 if (bce_hdr_split == TRUE) { 9471 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9472 "dump_pg_chain", 9473 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9474 (void *)sc, 0, 9475 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9476 } 9477 9478 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9479 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9480 (void *)sc, 0, 9481 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9482 9483 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9484 "breakpoint", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9485 (void *)sc, 0, 9486 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9487 9488 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9489 "reg_read", CTLTYPE_INT | CTLFLAG_RW| CTLFLAG_NEEDGIANT, 9490 (void *)sc, 0, 9491 bce_sysctl_reg_read, "I", "Register read"); 9492 9493 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9494 "nvram_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9495 (void *)sc, 0, 9496 bce_sysctl_nvram_read, "I", "NVRAM read"); 9497 9498 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9499 "phy_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9500 (void *)sc, 0, 9501 bce_sysctl_phy_read, "I", "PHY register read"); 9502 9503 #endif 9504 9505 DBEXIT(BCE_VERBOSE_MISC); 9506 } 9507 9508 /****************************************************************************/ 9509 /* BCE Debug Routines */ 9510 /****************************************************************************/ 9511 #ifdef BCE_DEBUG 9512 9513 /****************************************************************************/ 9514 /* Freezes the controller to allow for a cohesive state dump. */ 9515 /* */ 9516 /* Returns: */ 9517 /* Nothing. */ 9518 /****************************************************************************/ 9519 static __attribute__ ((noinline)) void 9520 bce_freeze_controller(struct bce_softc *sc) 9521 { 9522 u32 val; 9523 val = REG_RD(sc, BCE_MISC_COMMAND); 9524 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9525 REG_WR(sc, BCE_MISC_COMMAND, val); 9526 } 9527 9528 /****************************************************************************/ 9529 /* Unfreezes the controller after a freeze operation. This may not always */ 9530 /* work and the controller will require a reset! */ 9531 /* */ 9532 /* Returns: */ 9533 /* Nothing. */ 9534 /****************************************************************************/ 9535 static __attribute__ ((noinline)) void 9536 bce_unfreeze_controller(struct bce_softc *sc) 9537 { 9538 u32 val; 9539 val = REG_RD(sc, BCE_MISC_COMMAND); 9540 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9541 REG_WR(sc, BCE_MISC_COMMAND, val); 9542 } 9543 9544 /****************************************************************************/ 9545 /* Prints out Ethernet frame information from an mbuf. */ 9546 /* */ 9547 /* Partially decode an Ethernet frame to look at some important headers. */ 9548 /* */ 9549 /* Returns: */ 9550 /* Nothing. */ 9551 /****************************************************************************/ 9552 static __attribute__ ((noinline)) void 9553 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9554 { 9555 struct ether_vlan_header *eh; 9556 u16 etype; 9557 int ehlen; 9558 struct ip *ip; 9559 struct tcphdr *th; 9560 struct udphdr *uh; 9561 struct arphdr *ah; 9562 9563 BCE_PRINTF( 9564 "-----------------------------" 9565 " Frame Decode " 9566 "-----------------------------\n"); 9567 9568 eh = mtod(m, struct ether_vlan_header *); 9569 9570 /* Handle VLAN encapsulation if present. */ 9571 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9572 etype = ntohs(eh->evl_proto); 9573 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9574 } else { 9575 etype = ntohs(eh->evl_encap_proto); 9576 ehlen = ETHER_HDR_LEN; 9577 } 9578 9579 /* ToDo: Add VLAN output. */ 9580 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9581 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9582 9583 switch (etype) { 9584 case ETHERTYPE_IP: 9585 ip = (struct ip *)(m->m_data + ehlen); 9586 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9587 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9588 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9589 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9590 9591 switch (ip->ip_p) { 9592 case IPPROTO_TCP: 9593 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9594 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9595 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9596 ntohs(th->th_dport), ntohs(th->th_sport), 9597 (th->th_off << 2), th->th_flags, 9598 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9599 "\02SYN\01FIN", ntohs(th->th_sum)); 9600 break; 9601 case IPPROTO_UDP: 9602 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9603 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9604 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9605 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9606 ntohs(uh->uh_sum)); 9607 break; 9608 case IPPROTO_ICMP: 9609 BCE_PRINTF("icmp:\n"); 9610 break; 9611 default: 9612 BCE_PRINTF("----: Other IP protocol.\n"); 9613 } 9614 break; 9615 case ETHERTYPE_IPV6: 9616 BCE_PRINTF("ipv6: No decode supported.\n"); 9617 break; 9618 case ETHERTYPE_ARP: 9619 BCE_PRINTF("-arp: "); 9620 ah = (struct arphdr *) (m->m_data + ehlen); 9621 switch (ntohs(ah->ar_op)) { 9622 case ARPOP_REVREQUEST: 9623 printf("reverse ARP request\n"); 9624 break; 9625 case ARPOP_REVREPLY: 9626 printf("reverse ARP reply\n"); 9627 break; 9628 case ARPOP_REQUEST: 9629 printf("ARP request\n"); 9630 break; 9631 case ARPOP_REPLY: 9632 printf("ARP reply\n"); 9633 break; 9634 default: 9635 printf("other ARP operation\n"); 9636 } 9637 break; 9638 default: 9639 BCE_PRINTF("----: Other protocol.\n"); 9640 } 9641 9642 BCE_PRINTF( 9643 "-----------------------------" 9644 "--------------" 9645 "-----------------------------\n"); 9646 } 9647 9648 /****************************************************************************/ 9649 /* Prints out information about an mbuf. */ 9650 /* */ 9651 /* Returns: */ 9652 /* Nothing. */ 9653 /****************************************************************************/ 9654 static __attribute__ ((noinline)) void 9655 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9656 { 9657 struct mbuf *mp = m; 9658 9659 if (m == NULL) { 9660 BCE_PRINTF("mbuf: null pointer\n"); 9661 return; 9662 } 9663 9664 while (mp) { 9665 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9666 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9667 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9668 9669 if (mp->m_flags & M_PKTHDR) { 9670 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9671 "csum_flags = %b\n", mp->m_pkthdr.len, 9672 mp->m_flags, M_FLAG_PRINTF, 9673 mp->m_pkthdr.csum_flags, CSUM_BITS); 9674 } 9675 9676 if (mp->m_flags & M_EXT) { 9677 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9678 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9679 switch (mp->m_ext.ext_type) { 9680 case EXT_CLUSTER: 9681 printf("EXT_CLUSTER\n"); break; 9682 case EXT_SFBUF: 9683 printf("EXT_SFBUF\n"); break; 9684 case EXT_JUMBO9: 9685 printf("EXT_JUMBO9\n"); break; 9686 case EXT_JUMBO16: 9687 printf("EXT_JUMBO16\n"); break; 9688 case EXT_PACKET: 9689 printf("EXT_PACKET\n"); break; 9690 case EXT_MBUF: 9691 printf("EXT_MBUF\n"); break; 9692 case EXT_NET_DRV: 9693 printf("EXT_NET_DRV\n"); break; 9694 case EXT_MOD_TYPE: 9695 printf("EXT_MDD_TYPE\n"); break; 9696 case EXT_DISPOSABLE: 9697 printf("EXT_DISPOSABLE\n"); break; 9698 case EXT_EXTREF: 9699 printf("EXT_EXTREF\n"); break; 9700 default: 9701 printf("UNKNOWN\n"); 9702 } 9703 } 9704 9705 mp = mp->m_next; 9706 } 9707 } 9708 9709 /****************************************************************************/ 9710 /* Prints out the mbufs in the TX mbuf chain. */ 9711 /* */ 9712 /* Returns: */ 9713 /* Nothing. */ 9714 /****************************************************************************/ 9715 static __attribute__ ((noinline)) void 9716 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9717 { 9718 struct mbuf *m; 9719 9720 BCE_PRINTF( 9721 "----------------------------" 9722 " tx mbuf data " 9723 "----------------------------\n"); 9724 9725 for (int i = 0; i < count; i++) { 9726 m = sc->tx_mbuf_ptr[chain_prod]; 9727 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9728 bce_dump_mbuf(sc, m); 9729 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9730 } 9731 9732 BCE_PRINTF( 9733 "----------------------------" 9734 "----------------" 9735 "----------------------------\n"); 9736 } 9737 9738 /****************************************************************************/ 9739 /* Prints out the mbufs in the RX mbuf chain. */ 9740 /* */ 9741 /* Returns: */ 9742 /* Nothing. */ 9743 /****************************************************************************/ 9744 static __attribute__ ((noinline)) void 9745 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9746 { 9747 struct mbuf *m; 9748 9749 BCE_PRINTF( 9750 "----------------------------" 9751 " rx mbuf data " 9752 "----------------------------\n"); 9753 9754 for (int i = 0; i < count; i++) { 9755 m = sc->rx_mbuf_ptr[chain_prod]; 9756 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9757 bce_dump_mbuf(sc, m); 9758 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9759 } 9760 9761 BCE_PRINTF( 9762 "----------------------------" 9763 "----------------" 9764 "----------------------------\n"); 9765 } 9766 9767 /****************************************************************************/ 9768 /* Prints out the mbufs in the mbuf page chain. */ 9769 /* */ 9770 /* Returns: */ 9771 /* Nothing. */ 9772 /****************************************************************************/ 9773 static __attribute__ ((noinline)) void 9774 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9775 { 9776 struct mbuf *m; 9777 9778 BCE_PRINTF( 9779 "----------------------------" 9780 " pg mbuf data " 9781 "----------------------------\n"); 9782 9783 for (int i = 0; i < count; i++) { 9784 m = sc->pg_mbuf_ptr[chain_prod]; 9785 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9786 bce_dump_mbuf(sc, m); 9787 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9788 } 9789 9790 BCE_PRINTF( 9791 "----------------------------" 9792 "----------------" 9793 "----------------------------\n"); 9794 } 9795 9796 /****************************************************************************/ 9797 /* Prints out a tx_bd structure. */ 9798 /* */ 9799 /* Returns: */ 9800 /* Nothing. */ 9801 /****************************************************************************/ 9802 static __attribute__ ((noinline)) void 9803 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9804 { 9805 int i = 0; 9806 9807 if (idx > MAX_TX_BD_ALLOC) 9808 /* Index out of range. */ 9809 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9810 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9811 /* TX Chain page pointer. */ 9812 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9813 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9814 txbd->tx_bd_haddr_lo); 9815 else { 9816 /* Normal tx_bd entry. */ 9817 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9818 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9819 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9820 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9821 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9822 9823 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9824 if (i>0) 9825 printf("|"); 9826 printf("CONN_FAULT"); 9827 i++; 9828 } 9829 9830 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9831 if (i>0) 9832 printf("|"); 9833 printf("TCP_UDP_CKSUM"); 9834 i++; 9835 } 9836 9837 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9838 if (i>0) 9839 printf("|"); 9840 printf("IP_CKSUM"); 9841 i++; 9842 } 9843 9844 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9845 if (i>0) 9846 printf("|"); 9847 printf("VLAN"); 9848 i++; 9849 } 9850 9851 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9852 if (i>0) 9853 printf("|"); 9854 printf("COAL_NOW"); 9855 i++; 9856 } 9857 9858 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9859 if (i>0) 9860 printf("|"); 9861 printf("DONT_GEN_CRC"); 9862 i++; 9863 } 9864 9865 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 9866 if (i>0) 9867 printf("|"); 9868 printf("START"); 9869 i++; 9870 } 9871 9872 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 9873 if (i>0) 9874 printf("|"); 9875 printf("END"); 9876 i++; 9877 } 9878 9879 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 9880 if (i>0) 9881 printf("|"); 9882 printf("LSO"); 9883 i++; 9884 } 9885 9886 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 9887 if (i>0) 9888 printf("|"); 9889 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 9890 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 9891 } 9892 9893 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 9894 if (i>0) 9895 printf("|"); 9896 printf("SW_FLAGS"); 9897 i++; 9898 } 9899 9900 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 9901 if (i>0) 9902 printf("|"); 9903 printf("SNAP)"); 9904 } else { 9905 printf(")\n"); 9906 } 9907 } 9908 } 9909 9910 /****************************************************************************/ 9911 /* Prints out a rx_bd structure. */ 9912 /* */ 9913 /* Returns: */ 9914 /* Nothing. */ 9915 /****************************************************************************/ 9916 static __attribute__ ((noinline)) void 9917 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 9918 { 9919 if (idx > MAX_RX_BD_ALLOC) 9920 /* Index out of range. */ 9921 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 9922 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 9923 /* RX Chain page pointer. */ 9924 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9925 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 9926 rxbd->rx_bd_haddr_lo); 9927 else 9928 /* Normal rx_bd entry. */ 9929 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 9930 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 9931 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 9932 rxbd->rx_bd_flags); 9933 } 9934 9935 /****************************************************************************/ 9936 /* Prints out a rx_bd structure in the page chain. */ 9937 /* */ 9938 /* Returns: */ 9939 /* Nothing. */ 9940 /****************************************************************************/ 9941 static __attribute__ ((noinline)) void 9942 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9943 { 9944 if (idx > MAX_PG_BD_ALLOC) 9945 /* Index out of range. */ 9946 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9947 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9948 /* Page Chain page pointer. */ 9949 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9950 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9951 else 9952 /* Normal rx_bd entry. */ 9953 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9954 "flags = 0x%08X\n", idx, 9955 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9956 pgbd->rx_bd_len, pgbd->rx_bd_flags); 9957 } 9958 9959 /****************************************************************************/ 9960 /* Prints out a l2_fhdr structure. */ 9961 /* */ 9962 /* Returns: */ 9963 /* Nothing. */ 9964 /****************************************************************************/ 9965 static __attribute__ ((noinline)) void 9966 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9967 { 9968 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9969 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9970 "tcp_udp_xsum = 0x%04X\n", idx, 9971 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9972 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9973 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9974 } 9975 9976 /****************************************************************************/ 9977 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9978 /* */ 9979 /* Returns: */ 9980 /* Nothing. */ 9981 /****************************************************************************/ 9982 static __attribute__ ((noinline)) void 9983 bce_dump_ctx(struct bce_softc *sc, u16 cid) 9984 { 9985 if (cid > TX_CID) { 9986 BCE_PRINTF(" Unknown CID\n"); 9987 return; 9988 } 9989 9990 BCE_PRINTF( 9991 "----------------------------" 9992 " CTX Data " 9993 "----------------------------\n"); 9994 9995 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9996 9997 if (cid == RX_CID) { 9998 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 9999 "producer index\n", 10000 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 10001 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 10002 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10003 BCE_L2CTX_RX_HOST_BSEQ)); 10004 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 10005 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 10006 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 10007 "descriptor address\n", 10008 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 10009 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 10010 "descriptor address\n", 10011 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 10012 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 10013 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10014 BCE_L2CTX_RX_NX_BDIDX)); 10015 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 10016 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10017 BCE_L2CTX_RX_HOST_PG_BDIDX)); 10018 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 10019 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 10020 BCE_L2CTX_RX_PG_BUF_SIZE)); 10021 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 10022 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10023 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 10024 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 10025 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10026 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 10027 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 10028 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10029 BCE_L2CTX_RX_NX_PG_BDIDX)); 10030 } else if (cid == TX_CID) { 10031 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10032 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 10033 CTX_RD(sc, GET_CID_ADDR(cid), 10034 BCE_L2CTX_TX_TYPE_XI)); 10035 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 10036 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 10037 BCE_L2CTX_TX_CMD_TYPE_XI)); 10038 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 10039 "h/w buffer descriptor address\n", 10040 CTX_RD(sc, GET_CID_ADDR(cid), 10041 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 10042 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 10043 "h/w buffer descriptor address\n", 10044 CTX_RD(sc, GET_CID_ADDR(cid), 10045 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 10046 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 10047 "host producer index\n", 10048 CTX_RD(sc, GET_CID_ADDR(cid), 10049 BCE_L2CTX_TX_HOST_BIDX_XI)); 10050 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 10051 "host byte sequence\n", 10052 CTX_RD(sc, GET_CID_ADDR(cid), 10053 BCE_L2CTX_TX_HOST_BSEQ_XI)); 10054 } else { 10055 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 10056 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 10057 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 10058 CTX_RD(sc, GET_CID_ADDR(cid), 10059 BCE_L2CTX_TX_CMD_TYPE)); 10060 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 10061 "h/w buffer descriptor address\n", 10062 CTX_RD(sc, GET_CID_ADDR(cid), 10063 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 10064 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 10065 "h/w buffer descriptor address\n", 10066 CTX_RD(sc, GET_CID_ADDR(cid), 10067 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 10068 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 10069 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10070 BCE_L2CTX_TX_HOST_BIDX)); 10071 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 10072 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10073 BCE_L2CTX_TX_HOST_BSEQ)); 10074 } 10075 } 10076 10077 BCE_PRINTF( 10078 "----------------------------" 10079 " Raw CTX " 10080 "----------------------------\n"); 10081 10082 for (int i = 0x0; i < 0x300; i += 0x10) { 10083 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 10084 CTX_RD(sc, GET_CID_ADDR(cid), i), 10085 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 10086 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 10087 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 10088 } 10089 10090 BCE_PRINTF( 10091 "----------------------------" 10092 "----------------" 10093 "----------------------------\n"); 10094 } 10095 10096 /****************************************************************************/ 10097 /* Prints out the FTQ data. */ 10098 /* */ 10099 /* Returns: */ 10100 /* Nothing. */ 10101 /****************************************************************************/ 10102 static __attribute__ ((noinline)) void 10103 bce_dump_ftqs(struct bce_softc *sc) 10104 { 10105 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 10106 10107 BCE_PRINTF( 10108 "----------------------------" 10109 " FTQ Data " 10110 "----------------------------\n"); 10111 10112 BCE_PRINTF(" FTQ Command Control Depth_Now " 10113 "Max_Depth Valid_Cnt \n"); 10114 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10115 "---------- ----------\n"); 10116 10117 /* Setup the generic statistic counters for the FTQ valid count. */ 10118 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10119 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10120 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10121 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10122 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10123 10124 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10125 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10126 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10127 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10128 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10129 10130 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10131 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10132 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10133 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10134 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10135 10136 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10137 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10138 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10139 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10140 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10141 10142 /* Input queue to the Receive Lookup state machine */ 10143 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10144 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10145 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10146 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10147 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10148 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10149 cmd, ctl, cur_depth, max_depth, valid_cnt); 10150 10151 /* Input queue to the Receive Processor */ 10152 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10153 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10154 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10155 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10156 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10157 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10158 cmd, ctl, cur_depth, max_depth, valid_cnt); 10159 10160 /* Input queue to the Recevie Processor */ 10161 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10162 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10163 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10164 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10165 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10166 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10167 cmd, ctl, cur_depth, max_depth, valid_cnt); 10168 10169 /* Input queue to the Receive Virtual to Physical state machine */ 10170 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10171 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10172 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10173 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10174 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10175 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10176 cmd, ctl, cur_depth, max_depth, valid_cnt); 10177 10178 /* Input queue to the Recevie Virtual to Physical state machine */ 10179 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10180 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10181 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10182 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10183 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10184 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10185 cmd, ctl, cur_depth, max_depth, valid_cnt); 10186 10187 /* Input queue to the Receive Virtual to Physical state machine */ 10188 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10189 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10190 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10191 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10192 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10193 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10194 cmd, ctl, cur_depth, max_depth, valid_cnt); 10195 10196 /* Input queue to the Receive DMA state machine */ 10197 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10198 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10199 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10200 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10201 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10202 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10203 cmd, ctl, cur_depth, max_depth, valid_cnt); 10204 10205 /* Input queue to the Transmit Scheduler state machine */ 10206 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10207 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10208 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10209 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10210 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10211 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10212 cmd, ctl, cur_depth, max_depth, valid_cnt); 10213 10214 /* Input queue to the Transmit Buffer Descriptor state machine */ 10215 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10216 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10217 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10218 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10219 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10220 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10221 cmd, ctl, cur_depth, max_depth, valid_cnt); 10222 10223 /* Input queue to the Transmit Processor */ 10224 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10225 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10226 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10227 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10228 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10229 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10230 cmd, ctl, cur_depth, max_depth, valid_cnt); 10231 10232 /* Input queue to the Transmit DMA state machine */ 10233 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10234 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10235 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10236 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10237 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10238 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10239 cmd, ctl, cur_depth, max_depth, valid_cnt); 10240 10241 /* Input queue to the Transmit Patch-Up Processor */ 10242 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10243 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10244 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10245 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10246 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10247 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10248 cmd, ctl, cur_depth, max_depth, valid_cnt); 10249 10250 /* Input queue to the Transmit Assembler state machine */ 10251 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10252 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10253 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10254 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10255 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10256 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10257 cmd, ctl, cur_depth, max_depth, valid_cnt); 10258 10259 /* Input queue to the Completion Processor */ 10260 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10261 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10262 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10263 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10264 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10265 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10266 cmd, ctl, cur_depth, max_depth, valid_cnt); 10267 10268 /* Input queue to the Completion Processor */ 10269 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10270 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10271 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10272 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10273 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10274 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10275 cmd, ctl, cur_depth, max_depth, valid_cnt); 10276 10277 /* Input queue to the Completion Processor */ 10278 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10279 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10280 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10281 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10282 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10283 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10284 cmd, ctl, cur_depth, max_depth, valid_cnt); 10285 10286 /* Setup the generic statistic counters for the FTQ valid count. */ 10287 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10288 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10289 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10290 10291 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10292 val = val | 10293 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10294 24); 10295 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10296 10297 /* Input queue to the Management Control Processor */ 10298 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10299 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10300 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10301 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10302 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10303 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10304 cmd, ctl, cur_depth, max_depth, valid_cnt); 10305 10306 /* Input queue to the Command Processor */ 10307 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10308 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10309 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10310 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10311 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10312 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10313 cmd, ctl, cur_depth, max_depth, valid_cnt); 10314 10315 /* Input queue to the Completion Scheduler state machine */ 10316 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10317 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10318 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10319 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10320 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10321 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10322 cmd, ctl, cur_depth, max_depth, valid_cnt); 10323 10324 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10325 /* Input queue to the RV2P Command Scheduler */ 10326 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10327 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10328 cur_depth = (ctl & 0xFFC00000) >> 22; 10329 max_depth = (ctl & 0x003FF000) >> 12; 10330 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10331 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10332 cmd, ctl, cur_depth, max_depth, valid_cnt); 10333 } 10334 10335 BCE_PRINTF( 10336 "----------------------------" 10337 "----------------" 10338 "----------------------------\n"); 10339 } 10340 10341 /****************************************************************************/ 10342 /* Prints out the TX chain. */ 10343 /* */ 10344 /* Returns: */ 10345 /* Nothing. */ 10346 /****************************************************************************/ 10347 static __attribute__ ((noinline)) void 10348 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10349 { 10350 struct tx_bd *txbd; 10351 10352 /* First some info about the tx_bd chain structure. */ 10353 BCE_PRINTF( 10354 "----------------------------" 10355 " tx_bd chain " 10356 "----------------------------\n"); 10357 10358 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10359 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10360 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10361 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10362 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10363 10364 BCE_PRINTF( 10365 "----------------------------" 10366 " tx_bd data " 10367 "----------------------------\n"); 10368 10369 /* Now print out a decoded list of TX buffer descriptors. */ 10370 for (int i = 0; i < count; i++) { 10371 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10372 bce_dump_txbd(sc, tx_prod, txbd); 10373 tx_prod++; 10374 } 10375 10376 BCE_PRINTF( 10377 "----------------------------" 10378 "----------------" 10379 "----------------------------\n"); 10380 } 10381 10382 /****************************************************************************/ 10383 /* Prints out the RX chain. */ 10384 /* */ 10385 /* Returns: */ 10386 /* Nothing. */ 10387 /****************************************************************************/ 10388 static __attribute__ ((noinline)) void 10389 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10390 { 10391 struct rx_bd *rxbd; 10392 10393 /* First some info about the rx_bd chain structure. */ 10394 BCE_PRINTF( 10395 "----------------------------" 10396 " rx_bd chain " 10397 "----------------------------\n"); 10398 10399 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10400 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10401 10402 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10403 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10404 10405 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10406 10407 BCE_PRINTF( 10408 "----------------------------" 10409 " rx_bd data " 10410 "----------------------------\n"); 10411 10412 /* Now print out the rx_bd's themselves. */ 10413 for (int i = 0; i < count; i++) { 10414 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10415 bce_dump_rxbd(sc, rx_prod, rxbd); 10416 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10417 } 10418 10419 BCE_PRINTF( 10420 "----------------------------" 10421 "----------------" 10422 "----------------------------\n"); 10423 } 10424 10425 /****************************************************************************/ 10426 /* Prints out the page chain. */ 10427 /* */ 10428 /* Returns: */ 10429 /* Nothing. */ 10430 /****************************************************************************/ 10431 static __attribute__ ((noinline)) void 10432 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10433 { 10434 struct rx_bd *pgbd; 10435 10436 /* First some info about the page chain structure. */ 10437 BCE_PRINTF( 10438 "----------------------------" 10439 " page chain " 10440 "----------------------------\n"); 10441 10442 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10443 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10444 10445 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10446 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10447 10448 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10449 10450 BCE_PRINTF( 10451 "----------------------------" 10452 " page data " 10453 "----------------------------\n"); 10454 10455 /* Now print out the rx_bd's themselves. */ 10456 for (int i = 0; i < count; i++) { 10457 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10458 bce_dump_pgbd(sc, pg_prod, pgbd); 10459 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10460 } 10461 10462 BCE_PRINTF( 10463 "----------------------------" 10464 "----------------" 10465 "----------------------------\n"); 10466 } 10467 10468 #define BCE_PRINT_RX_CONS(arg) \ 10469 if (sblk->status_rx_quick_consumer_index##arg) \ 10470 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10471 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10472 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10473 arg); 10474 10475 #define BCE_PRINT_TX_CONS(arg) \ 10476 if (sblk->status_tx_quick_consumer_index##arg) \ 10477 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10478 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10479 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10480 arg); 10481 10482 /****************************************************************************/ 10483 /* Prints out the status block from host memory. */ 10484 /* */ 10485 /* Returns: */ 10486 /* Nothing. */ 10487 /****************************************************************************/ 10488 static __attribute__ ((noinline)) void 10489 bce_dump_status_block(struct bce_softc *sc) 10490 { 10491 struct status_block *sblk; 10492 10493 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 10494 10495 sblk = sc->status_block; 10496 10497 BCE_PRINTF( 10498 "----------------------------" 10499 " Status Block " 10500 "----------------------------\n"); 10501 10502 /* Theses indices are used for normal L2 drivers. */ 10503 BCE_PRINTF(" 0x%08X - attn_bits\n", 10504 sblk->status_attn_bits); 10505 10506 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10507 sblk->status_attn_bits_ack); 10508 10509 BCE_PRINT_RX_CONS(0); 10510 BCE_PRINT_TX_CONS(0) 10511 10512 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10513 10514 /* Theses indices are not used for normal L2 drivers. */ 10515 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10516 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10517 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10518 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10519 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10520 10521 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10522 10523 if (sblk->status_completion_producer_index || 10524 sblk->status_cmd_consumer_index) 10525 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10526 sblk->status_completion_producer_index, 10527 sblk->status_cmd_consumer_index); 10528 10529 BCE_PRINTF( 10530 "----------------------------" 10531 "----------------" 10532 "----------------------------\n"); 10533 } 10534 10535 #define BCE_PRINT_64BIT_STAT(arg) \ 10536 if (sblk->arg##_lo || sblk->arg##_hi) \ 10537 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10538 sblk->arg##_lo, #arg); 10539 10540 #define BCE_PRINT_32BIT_STAT(arg) \ 10541 if (sblk->arg) \ 10542 BCE_PRINTF(" 0x%08X : %s\n", \ 10543 sblk->arg, #arg); 10544 10545 /****************************************************************************/ 10546 /* Prints out the statistics block from host memory. */ 10547 /* */ 10548 /* Returns: */ 10549 /* Nothing. */ 10550 /****************************************************************************/ 10551 static __attribute__ ((noinline)) void 10552 bce_dump_stats_block(struct bce_softc *sc) 10553 { 10554 struct statistics_block *sblk; 10555 10556 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 10557 10558 sblk = sc->stats_block; 10559 10560 BCE_PRINTF( 10561 "---------------" 10562 " Stats Block (All Stats Not Shown Are 0) " 10563 "---------------\n"); 10564 10565 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10566 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10567 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10568 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10569 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10570 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10571 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10572 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10573 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10574 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10575 BCE_PRINT_32BIT_STAT( 10576 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10577 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10578 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10579 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10580 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10581 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10582 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10583 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10584 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10585 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10586 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10587 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10588 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10589 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10590 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10591 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10592 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10593 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10594 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10595 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10596 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10597 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10598 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10599 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10600 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10601 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10602 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10603 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10604 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10605 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10606 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10607 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10608 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10609 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10610 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10611 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10612 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10613 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10614 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10615 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10616 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10617 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10618 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10619 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10620 10621 BCE_PRINTF( 10622 "----------------------------" 10623 "----------------" 10624 "----------------------------\n"); 10625 } 10626 10627 /****************************************************************************/ 10628 /* Prints out a summary of the driver state. */ 10629 /* */ 10630 /* Returns: */ 10631 /* Nothing. */ 10632 /****************************************************************************/ 10633 static __attribute__ ((noinline)) void 10634 bce_dump_driver_state(struct bce_softc *sc) 10635 { 10636 u32 val_hi, val_lo; 10637 10638 BCE_PRINTF( 10639 "-----------------------------" 10640 " Driver State " 10641 "-----------------------------\n"); 10642 10643 val_hi = BCE_ADDR_HI(sc); 10644 val_lo = BCE_ADDR_LO(sc); 10645 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10646 "address\n", val_hi, val_lo); 10647 10648 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10649 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10650 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10651 "address\n", val_hi, val_lo); 10652 10653 val_hi = BCE_ADDR_HI(sc->status_block); 10654 val_lo = BCE_ADDR_LO(sc->status_block); 10655 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10656 "virtual address\n", val_hi, val_lo); 10657 10658 val_hi = BCE_ADDR_HI(sc->stats_block); 10659 val_lo = BCE_ADDR_LO(sc->stats_block); 10660 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10661 "virtual address\n", val_hi, val_lo); 10662 10663 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10664 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10665 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10666 "virtual adddress\n", val_hi, val_lo); 10667 10668 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10669 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10670 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10671 "virtual address\n", val_hi, val_lo); 10672 10673 if (bce_hdr_split == TRUE) { 10674 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10675 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10676 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10677 "virtual address\n", val_hi, val_lo); 10678 } 10679 10680 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10681 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10682 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10683 "virtual address\n", val_hi, val_lo); 10684 10685 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10686 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10687 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10688 "virtual address\n", val_hi, val_lo); 10689 10690 if (bce_hdr_split == TRUE) { 10691 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10692 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10693 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10694 "virtual address\n", val_hi, val_lo); 10695 } 10696 10697 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10698 "h/w intrs\n", 10699 (long long unsigned int) sc->interrupts_generated); 10700 10701 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10702 "rx interrupts handled\n", 10703 (long long unsigned int) sc->interrupts_rx); 10704 10705 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10706 "tx interrupts handled\n", 10707 (long long unsigned int) sc->interrupts_tx); 10708 10709 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10710 "phy interrupts handled\n", 10711 (long long unsigned int) sc->phy_interrupts); 10712 10713 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10714 "status block index\n", sc->last_status_idx); 10715 10716 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10717 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10718 10719 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10720 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10721 10722 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10723 "byte seq index\n", sc->tx_prod_bseq); 10724 10725 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10726 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10727 10728 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10729 "tx_bd's\n", sc->used_tx_bd); 10730 10731 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10732 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10733 10734 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10735 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10736 10737 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10738 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10739 10740 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10741 "byte seq index\n", sc->rx_prod_bseq); 10742 10743 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10744 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10745 10746 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10747 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10748 10749 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10750 "rx_bd's\n", sc->free_rx_bd); 10751 10752 if (bce_hdr_split == TRUE) { 10753 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10754 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10755 10756 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10757 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10758 10759 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10760 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10761 } 10762 10763 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10764 "rx_bd's\n", sc->free_pg_bd); 10765 10766 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10767 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10768 10769 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10770 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10771 10772 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10773 "bce mac flags\n", sc->bce_flags); 10774 10775 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10776 "bce phy flags\n", sc->bce_phy_flags); 10777 10778 BCE_PRINTF( 10779 "----------------------------" 10780 "----------------" 10781 "----------------------------\n"); 10782 } 10783 10784 /****************************************************************************/ 10785 /* Prints out the hardware state through a summary of important register, */ 10786 /* followed by a complete register dump. */ 10787 /* */ 10788 /* Returns: */ 10789 /* Nothing. */ 10790 /****************************************************************************/ 10791 static __attribute__ ((noinline)) void 10792 bce_dump_hw_state(struct bce_softc *sc) 10793 { 10794 u32 val; 10795 10796 BCE_PRINTF( 10797 "----------------------------" 10798 " Hardware State " 10799 "----------------------------\n"); 10800 10801 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10802 10803 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10804 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10805 val, BCE_MISC_ENABLE_STATUS_BITS); 10806 10807 val = REG_RD(sc, BCE_DMA_STATUS); 10808 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10809 val, BCE_DMA_STATUS); 10810 10811 val = REG_RD(sc, BCE_CTX_STATUS); 10812 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10813 val, BCE_CTX_STATUS); 10814 10815 val = REG_RD(sc, BCE_EMAC_STATUS); 10816 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10817 val, BCE_EMAC_STATUS); 10818 10819 val = REG_RD(sc, BCE_RPM_STATUS); 10820 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10821 val, BCE_RPM_STATUS); 10822 10823 /* ToDo: Create a #define for this constant. */ 10824 val = REG_RD(sc, 0x2004); 10825 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10826 val, 0x2004); 10827 10828 val = REG_RD(sc, BCE_RV2P_STATUS); 10829 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10830 val, BCE_RV2P_STATUS); 10831 10832 /* ToDo: Create a #define for this constant. */ 10833 val = REG_RD(sc, 0x2c04); 10834 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10835 val, 0x2c04); 10836 10837 val = REG_RD(sc, BCE_TBDR_STATUS); 10838 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10839 val, BCE_TBDR_STATUS); 10840 10841 val = REG_RD(sc, BCE_TDMA_STATUS); 10842 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10843 val, BCE_TDMA_STATUS); 10844 10845 val = REG_RD(sc, BCE_HC_STATUS); 10846 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10847 val, BCE_HC_STATUS); 10848 10849 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10850 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10851 val, BCE_TXP_CPU_STATE); 10852 10853 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10854 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10855 val, BCE_TPAT_CPU_STATE); 10856 10857 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10858 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10859 val, BCE_RXP_CPU_STATE); 10860 10861 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10862 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10863 val, BCE_COM_CPU_STATE); 10864 10865 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10866 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 10867 val, BCE_MCP_CPU_STATE); 10868 10869 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10870 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10871 val, BCE_CP_CPU_STATE); 10872 10873 BCE_PRINTF( 10874 "----------------------------" 10875 "----------------" 10876 "----------------------------\n"); 10877 10878 BCE_PRINTF( 10879 "----------------------------" 10880 " Register Dump " 10881 "----------------------------\n"); 10882 10883 for (int i = 0x400; i < 0x8000; i += 0x10) { 10884 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10885 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10886 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10887 } 10888 10889 BCE_PRINTF( 10890 "----------------------------" 10891 "----------------" 10892 "----------------------------\n"); 10893 } 10894 10895 /****************************************************************************/ 10896 /* Prints out the contentst of shared memory which is used for host driver */ 10897 /* to bootcode firmware communication. */ 10898 /* */ 10899 /* Returns: */ 10900 /* Nothing. */ 10901 /****************************************************************************/ 10902 static __attribute__ ((noinline)) void 10903 bce_dump_shmem_state(struct bce_softc *sc) 10904 { 10905 BCE_PRINTF( 10906 "----------------------------" 10907 " Hardware State " 10908 "----------------------------\n"); 10909 10910 BCE_PRINTF("0x%08X - Shared memory base address\n", 10911 sc->bce_shmem_base); 10912 BCE_PRINTF("%s - bootcode version\n", 10913 sc->bce_bc_ver); 10914 10915 BCE_PRINTF( 10916 "----------------------------" 10917 " Shared Mem " 10918 "----------------------------\n"); 10919 10920 for (int i = 0x0; i < 0x200; i += 0x10) { 10921 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10922 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 10923 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 10924 } 10925 10926 BCE_PRINTF( 10927 "----------------------------" 10928 "----------------" 10929 "----------------------------\n"); 10930 } 10931 10932 /****************************************************************************/ 10933 /* Prints out the mailbox queue registers. */ 10934 /* */ 10935 /* Returns: */ 10936 /* Nothing. */ 10937 /****************************************************************************/ 10938 static __attribute__ ((noinline)) void 10939 bce_dump_mq_regs(struct bce_softc *sc) 10940 { 10941 BCE_PRINTF( 10942 "----------------------------" 10943 " MQ Regs " 10944 "----------------------------\n"); 10945 10946 BCE_PRINTF( 10947 "----------------------------" 10948 "----------------" 10949 "----------------------------\n"); 10950 10951 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10952 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10953 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10954 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10955 } 10956 10957 BCE_PRINTF( 10958 "----------------------------" 10959 "----------------" 10960 "----------------------------\n"); 10961 } 10962 10963 /****************************************************************************/ 10964 /* Prints out the bootcode state. */ 10965 /* */ 10966 /* Returns: */ 10967 /* Nothing. */ 10968 /****************************************************************************/ 10969 static __attribute__ ((noinline)) void 10970 bce_dump_bc_state(struct bce_softc *sc) 10971 { 10972 u32 val; 10973 10974 BCE_PRINTF( 10975 "----------------------------" 10976 " Bootcode State " 10977 "----------------------------\n"); 10978 10979 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10980 10981 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10982 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10983 val, BCE_BC_RESET_TYPE); 10984 10985 val = bce_shmem_rd(sc, BCE_BC_STATE); 10986 BCE_PRINTF("0x%08X - (0x%06X) state\n", 10987 val, BCE_BC_STATE); 10988 10989 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10990 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10991 val, BCE_BC_STATE_CONDITION); 10992 10993 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10994 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10995 val, BCE_BC_STATE_DEBUG_CMD); 10996 10997 BCE_PRINTF( 10998 "----------------------------" 10999 "----------------" 11000 "----------------------------\n"); 11001 } 11002 11003 /****************************************************************************/ 11004 /* Prints out the TXP processor state. */ 11005 /* */ 11006 /* Returns: */ 11007 /* Nothing. */ 11008 /****************************************************************************/ 11009 static __attribute__ ((noinline)) void 11010 bce_dump_txp_state(struct bce_softc *sc, int regs) 11011 { 11012 u32 val; 11013 u32 fw_version[3]; 11014 11015 BCE_PRINTF( 11016 "----------------------------" 11017 " TXP State " 11018 "----------------------------\n"); 11019 11020 for (int i = 0; i < 3; i++) 11021 fw_version[i] = htonl(REG_RD_IND(sc, 11022 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 11023 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11024 11025 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 11026 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 11027 val, BCE_TXP_CPU_MODE); 11028 11029 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11030 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11031 val, BCE_TXP_CPU_STATE); 11032 11033 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 11034 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 11035 val, BCE_TXP_CPU_EVENT_MASK); 11036 11037 if (regs) { 11038 BCE_PRINTF( 11039 "----------------------------" 11040 " Register Dump " 11041 "----------------------------\n"); 11042 11043 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 11044 /* Skip the big blank spaces */ 11045 if (i < 0x454000 && i > 0x5ffff) 11046 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11047 "0x%08X 0x%08X\n", i, 11048 REG_RD_IND(sc, i), 11049 REG_RD_IND(sc, i + 0x4), 11050 REG_RD_IND(sc, i + 0x8), 11051 REG_RD_IND(sc, i + 0xC)); 11052 } 11053 } 11054 11055 BCE_PRINTF( 11056 "----------------------------" 11057 "----------------" 11058 "----------------------------\n"); 11059 } 11060 11061 /****************************************************************************/ 11062 /* Prints out the RXP processor state. */ 11063 /* */ 11064 /* Returns: */ 11065 /* Nothing. */ 11066 /****************************************************************************/ 11067 static __attribute__ ((noinline)) void 11068 bce_dump_rxp_state(struct bce_softc *sc, int regs) 11069 { 11070 u32 val; 11071 u32 fw_version[3]; 11072 11073 BCE_PRINTF( 11074 "----------------------------" 11075 " RXP State " 11076 "----------------------------\n"); 11077 11078 for (int i = 0; i < 3; i++) 11079 fw_version[i] = htonl(REG_RD_IND(sc, 11080 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 11081 11082 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11083 11084 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 11085 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 11086 val, BCE_RXP_CPU_MODE); 11087 11088 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11089 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11090 val, BCE_RXP_CPU_STATE); 11091 11092 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 11093 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 11094 val, BCE_RXP_CPU_EVENT_MASK); 11095 11096 if (regs) { 11097 BCE_PRINTF( 11098 "----------------------------" 11099 " Register Dump " 11100 "----------------------------\n"); 11101 11102 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11103 /* Skip the big blank sapces */ 11104 if (i < 0xc5400 && i > 0xdffff) 11105 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11106 "0x%08X 0x%08X\n", i, 11107 REG_RD_IND(sc, i), 11108 REG_RD_IND(sc, i + 0x4), 11109 REG_RD_IND(sc, i + 0x8), 11110 REG_RD_IND(sc, i + 0xC)); 11111 } 11112 } 11113 11114 BCE_PRINTF( 11115 "----------------------------" 11116 "----------------" 11117 "----------------------------\n"); 11118 } 11119 11120 /****************************************************************************/ 11121 /* Prints out the TPAT processor state. */ 11122 /* */ 11123 /* Returns: */ 11124 /* Nothing. */ 11125 /****************************************************************************/ 11126 static __attribute__ ((noinline)) void 11127 bce_dump_tpat_state(struct bce_softc *sc, int regs) 11128 { 11129 u32 val; 11130 u32 fw_version[3]; 11131 11132 BCE_PRINTF( 11133 "----------------------------" 11134 " TPAT State " 11135 "----------------------------\n"); 11136 11137 for (int i = 0; i < 3; i++) 11138 fw_version[i] = htonl(REG_RD_IND(sc, 11139 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11140 11141 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11142 11143 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11144 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11145 val, BCE_TPAT_CPU_MODE); 11146 11147 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11148 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11149 val, BCE_TPAT_CPU_STATE); 11150 11151 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11152 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11153 val, BCE_TPAT_CPU_EVENT_MASK); 11154 11155 if (regs) { 11156 BCE_PRINTF( 11157 "----------------------------" 11158 " Register Dump " 11159 "----------------------------\n"); 11160 11161 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11162 /* Skip the big blank spaces */ 11163 if (i < 0x854000 && i > 0x9ffff) 11164 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11165 "0x%08X 0x%08X\n", i, 11166 REG_RD_IND(sc, i), 11167 REG_RD_IND(sc, i + 0x4), 11168 REG_RD_IND(sc, i + 0x8), 11169 REG_RD_IND(sc, i + 0xC)); 11170 } 11171 } 11172 11173 BCE_PRINTF( 11174 "----------------------------" 11175 "----------------" 11176 "----------------------------\n"); 11177 } 11178 11179 /****************************************************************************/ 11180 /* Prints out the Command Procesor (CP) state. */ 11181 /* */ 11182 /* Returns: */ 11183 /* Nothing. */ 11184 /****************************************************************************/ 11185 static __attribute__ ((noinline)) void 11186 bce_dump_cp_state(struct bce_softc *sc, int regs) 11187 { 11188 u32 val; 11189 u32 fw_version[3]; 11190 11191 BCE_PRINTF( 11192 "----------------------------" 11193 " CP State " 11194 "----------------------------\n"); 11195 11196 for (int i = 0; i < 3; i++) 11197 fw_version[i] = htonl(REG_RD_IND(sc, 11198 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11199 11200 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11201 11202 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11203 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11204 val, BCE_CP_CPU_MODE); 11205 11206 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11207 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11208 val, BCE_CP_CPU_STATE); 11209 11210 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11211 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11212 BCE_CP_CPU_EVENT_MASK); 11213 11214 if (regs) { 11215 BCE_PRINTF( 11216 "----------------------------" 11217 " Register Dump " 11218 "----------------------------\n"); 11219 11220 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11221 /* Skip the big blank spaces */ 11222 if (i < 0x185400 && i > 0x19ffff) 11223 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11224 "0x%08X 0x%08X\n", i, 11225 REG_RD_IND(sc, i), 11226 REG_RD_IND(sc, i + 0x4), 11227 REG_RD_IND(sc, i + 0x8), 11228 REG_RD_IND(sc, i + 0xC)); 11229 } 11230 } 11231 11232 BCE_PRINTF( 11233 "----------------------------" 11234 "----------------" 11235 "----------------------------\n"); 11236 } 11237 11238 /****************************************************************************/ 11239 /* Prints out the Completion Procesor (COM) state. */ 11240 /* */ 11241 /* Returns: */ 11242 /* Nothing. */ 11243 /****************************************************************************/ 11244 static __attribute__ ((noinline)) void 11245 bce_dump_com_state(struct bce_softc *sc, int regs) 11246 { 11247 u32 val; 11248 u32 fw_version[4]; 11249 11250 BCE_PRINTF( 11251 "----------------------------" 11252 " COM State " 11253 "----------------------------\n"); 11254 11255 for (int i = 0; i < 3; i++) 11256 fw_version[i] = htonl(REG_RD_IND(sc, 11257 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11258 11259 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11260 11261 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11262 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11263 val, BCE_COM_CPU_MODE); 11264 11265 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11266 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11267 val, BCE_COM_CPU_STATE); 11268 11269 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11270 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11271 BCE_COM_CPU_EVENT_MASK); 11272 11273 if (regs) { 11274 BCE_PRINTF( 11275 "----------------------------" 11276 " Register Dump " 11277 "----------------------------\n"); 11278 11279 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11280 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11281 "0x%08X 0x%08X\n", i, 11282 REG_RD_IND(sc, i), 11283 REG_RD_IND(sc, i + 0x4), 11284 REG_RD_IND(sc, i + 0x8), 11285 REG_RD_IND(sc, i + 0xC)); 11286 } 11287 } 11288 11289 BCE_PRINTF( 11290 "----------------------------" 11291 "----------------" 11292 "----------------------------\n"); 11293 } 11294 11295 /****************************************************************************/ 11296 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11297 /* */ 11298 /* Returns: */ 11299 /* Nothing. */ 11300 /****************************************************************************/ 11301 static __attribute__ ((noinline)) void 11302 bce_dump_rv2p_state(struct bce_softc *sc) 11303 { 11304 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11305 11306 BCE_PRINTF( 11307 "----------------------------" 11308 " RV2P State " 11309 "----------------------------\n"); 11310 11311 /* Stall the RV2P processors. */ 11312 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11313 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11314 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11315 11316 /* Read the firmware version. */ 11317 val = 0x00000001; 11318 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11319 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11320 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11321 BCE_RV2P_INSTR_HIGH_HIGH; 11322 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11323 fw_ver_high, fw_ver_low); 11324 11325 val = 0x00000001; 11326 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11327 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11328 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11329 BCE_RV2P_INSTR_HIGH_HIGH; 11330 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11331 fw_ver_high, fw_ver_low); 11332 11333 /* Resume the RV2P processors. */ 11334 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11335 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11336 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11337 11338 /* Fetch the program counter value. */ 11339 val = 0x68007800; 11340 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11341 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11342 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11343 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11344 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11345 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11346 11347 /* Fetch the program counter value again to see if it is advancing. */ 11348 val = 0x68007800; 11349 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11350 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11351 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11352 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11353 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11354 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11355 11356 BCE_PRINTF( 11357 "----------------------------" 11358 "----------------" 11359 "----------------------------\n"); 11360 } 11361 11362 /****************************************************************************/ 11363 /* Prints out the driver state and then enters the debugger. */ 11364 /* */ 11365 /* Returns: */ 11366 /* Nothing. */ 11367 /****************************************************************************/ 11368 static __attribute__ ((noinline)) void 11369 bce_breakpoint(struct bce_softc *sc) 11370 { 11371 11372 /* 11373 * Unreachable code to silence compiler warnings 11374 * about unused functions. 11375 */ 11376 if (0) { 11377 bce_freeze_controller(sc); 11378 bce_unfreeze_controller(sc); 11379 bce_dump_enet(sc, NULL); 11380 bce_dump_txbd(sc, 0, NULL); 11381 bce_dump_rxbd(sc, 0, NULL); 11382 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11383 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11384 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11385 bce_dump_l2fhdr(sc, 0, NULL); 11386 bce_dump_ctx(sc, RX_CID); 11387 bce_dump_ftqs(sc); 11388 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11389 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11390 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11391 bce_dump_status_block(sc); 11392 bce_dump_stats_block(sc); 11393 bce_dump_driver_state(sc); 11394 bce_dump_hw_state(sc); 11395 bce_dump_bc_state(sc); 11396 bce_dump_txp_state(sc, 0); 11397 bce_dump_rxp_state(sc, 0); 11398 bce_dump_tpat_state(sc, 0); 11399 bce_dump_cp_state(sc, 0); 11400 bce_dump_com_state(sc, 0); 11401 bce_dump_rv2p_state(sc); 11402 bce_dump_pgbd(sc, 0, NULL); 11403 } 11404 11405 bce_dump_status_block(sc); 11406 bce_dump_driver_state(sc); 11407 11408 /* Call the debugger. */ 11409 breakpoint(); 11410 } 11411 #endif 11412