1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006-2014 QLogic Corporation 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * The following controllers are supported by this driver: 34 * BCM5706C A2, A3 35 * BCM5706S A2, A3 36 * BCM5708C B1, B2 37 * BCM5708S B1, B2 38 * BCM5709C A1, C0 39 * BCM5709S A1, C0 40 * BCM5716C C0 41 * BCM5716S C0 42 * 43 * The following controllers are not supported by this driver: 44 * BCM5706C A0, A1 (pre-production) 45 * BCM5706S A0, A1 (pre-production) 46 * BCM5708C A0, B0 (pre-production) 47 * BCM5708S A0, B0 (pre-production) 48 * BCM5709C A0 B0, B1, B2 (pre-production) 49 * BCM5709S A0, B0, B1, B2 (pre-production) 50 */ 51 52 #include "opt_bce.h" 53 54 #include <sys/param.h> 55 #include <sys/endian.h> 56 #include <sys/systm.h> 57 #include <sys/sockio.h> 58 #include <sys/lock.h> 59 #include <sys/mbuf.h> 60 #include <sys/malloc.h> 61 #include <sys/mutex.h> 62 #include <sys/kernel.h> 63 #include <sys/module.h> 64 #include <sys/socket.h> 65 #include <sys/sysctl.h> 66 #include <sys/queue.h> 67 68 #include <net/bpf.h> 69 #include <net/ethernet.h> 70 #include <net/if.h> 71 #include <net/if_var.h> 72 #include <net/if_arp.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <net/if_types.h> 77 #include <net/if_vlan_var.h> 78 79 #include <netinet/in_systm.h> 80 #include <netinet/in.h> 81 #include <netinet/if_ether.h> 82 #include <netinet/ip.h> 83 #include <netinet/ip6.h> 84 #include <netinet/tcp.h> 85 #include <netinet/udp.h> 86 87 #include <machine/bus.h> 88 #include <machine/resource.h> 89 #include <sys/bus.h> 90 #include <sys/rman.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include "miidevs.h" 95 #include <dev/mii/brgphyreg.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 100 #include "miibus_if.h" 101 102 #include <dev/bce/if_bcereg.h> 103 #include <dev/bce/if_bcefw.h> 104 105 /****************************************************************************/ 106 /* BCE Debug Options */ 107 /****************************************************************************/ 108 #ifdef BCE_DEBUG 109 u32 bce_debug = BCE_WARN; 110 111 /* 0 = Never */ 112 /* 1 = 1 in 2,147,483,648 */ 113 /* 256 = 1 in 8,388,608 */ 114 /* 2048 = 1 in 1,048,576 */ 115 /* 65536 = 1 in 32,768 */ 116 /* 1048576 = 1 in 2,048 */ 117 /* 268435456 = 1 in 8 */ 118 /* 536870912 = 1 in 4 */ 119 /* 1073741824 = 1 in 2 */ 120 121 /* Controls how often the l2_fhdr frame error check will fail. */ 122 int l2fhdr_error_sim_control = 0; 123 124 /* Controls how often the unexpected attention check will fail. */ 125 int unexpected_attention_sim_control = 0; 126 127 /* Controls how often to simulate an mbuf allocation failure. */ 128 int mbuf_alloc_failed_sim_control = 0; 129 130 /* Controls how often to simulate a DMA mapping failure. */ 131 int dma_map_addr_failed_sim_control = 0; 132 133 /* Controls how often to simulate a bootcode failure. */ 134 int bootcode_running_failure_sim_control = 0; 135 #endif 136 137 /****************************************************************************/ 138 /* PCI Device ID Table */ 139 /* */ 140 /* Used by bce_probe() to identify the devices supported by this driver. */ 141 /****************************************************************************/ 142 #define BCE_DEVDESC_MAX 64 143 144 static const struct bce_type bce_devs[] = { 145 /* BCM5706C Controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 147 "HP NC370T Multifunction Gigabit Server Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 149 "HP NC370i Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 151 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 153 "HP NC371i Multifunction Gigabit Server Adapter" }, 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 155 "QLogic NetXtreme II BCM5706 1000Base-T" }, 156 157 /* BCM5706S controllers and OEM boards. */ 158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 159 "HP NC370F Multifunction Gigabit Server Adapter" }, 160 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 161 "QLogic NetXtreme II BCM5706 1000Base-SX" }, 162 163 /* BCM5708C controllers and OEM boards. */ 164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 165 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 167 "HP NC373i Multifunction Gigabit Server Adapter" }, 168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 169 "HP NC374m PCIe Multifunction Adapter" }, 170 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 171 "QLogic NetXtreme II BCM5708 1000Base-T" }, 172 173 /* BCM5708S controllers and OEM boards. */ 174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 175 "HP NC373m Multifunction Gigabit Server Adapter" }, 176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 177 "HP NC373i Multifunction Gigabit Server Adapter" }, 178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 179 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 180 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 181 "QLogic NetXtreme II BCM5708 1000Base-SX" }, 182 183 /* BCM5709C controllers and OEM boards. */ 184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 185 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 187 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 188 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 189 "QLogic NetXtreme II BCM5709 1000Base-T" }, 190 191 /* BCM5709S controllers and OEM boards. */ 192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 193 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 195 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 196 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 197 "QLogic NetXtreme II BCM5709 1000Base-SX" }, 198 199 /* BCM5716 controllers and OEM boards. */ 200 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 201 "QLogic NetXtreme II BCM5716 1000Base-T" }, 202 { 0, 0, 0, 0, NULL } 203 }; 204 205 /****************************************************************************/ 206 /* Supported Flash NVRAM device data. */ 207 /****************************************************************************/ 208 static const struct flash_spec flash_table[] = 209 { 210 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 211 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 212 213 /* Slow EEPROM */ 214 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 215 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 216 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 217 "EEPROM - slow"}, 218 /* Expansion entry 0001 */ 219 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 222 "Entry 0001"}, 223 /* Saifun SA25F010 (non-buffered flash) */ 224 /* strap, cfg1, & write1 need updates */ 225 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 228 "Non-buffered flash (128kB)"}, 229 /* Saifun SA25F020 (non-buffered flash) */ 230 /* strap, cfg1, & write1 need updates */ 231 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 232 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 233 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 234 "Non-buffered flash (256kB)"}, 235 /* Expansion entry 0100 */ 236 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 239 "Entry 0100"}, 240 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 241 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 242 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 243 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 244 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 245 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 246 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 247 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 248 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 249 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 250 /* Saifun SA25F005 (non-buffered flash) */ 251 /* strap, cfg1, & write1 need updates */ 252 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 254 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 255 "Non-buffered flash (64kB)"}, 256 /* Fast EEPROM */ 257 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 258 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 259 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 260 "EEPROM - fast"}, 261 /* Expansion entry 1001 */ 262 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 263 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 264 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 265 "Entry 1001"}, 266 /* Expansion entry 1010 */ 267 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 268 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 269 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 270 "Entry 1010"}, 271 /* ATMEL AT45DB011B (buffered flash) */ 272 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 273 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 274 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 275 "Buffered flash (128kB)"}, 276 /* Expansion entry 1100 */ 277 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 278 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 279 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 280 "Entry 1100"}, 281 /* Expansion entry 1101 */ 282 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 283 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 284 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 285 "Entry 1101"}, 286 /* Ateml Expansion entry 1110 */ 287 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 288 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 289 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 290 "Entry 1110 (Atmel)"}, 291 /* ATMEL AT45DB021B (buffered flash) */ 292 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 293 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 294 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 295 "Buffered flash (256kB)"}, 296 }; 297 298 /* 299 * The BCM5709 controllers transparently handle the 300 * differences between Atmel 264 byte pages and all 301 * flash devices which use 256 byte pages, so no 302 * logical-to-physical mapping is required in the 303 * driver. 304 */ 305 static const struct flash_spec flash_5709 = { 306 .flags = BCE_NV_BUFFERED, 307 .page_bits = BCM5709_FLASH_PAGE_BITS, 308 .page_size = BCM5709_FLASH_PAGE_SIZE, 309 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 310 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 311 .name = "5709/5716 buffered flash (256kB)", 312 }; 313 314 /****************************************************************************/ 315 /* FreeBSD device entry points. */ 316 /****************************************************************************/ 317 static int bce_probe (device_t); 318 static int bce_attach (device_t); 319 static int bce_detach (device_t); 320 static int bce_shutdown (device_t); 321 322 /****************************************************************************/ 323 /* BCE Debug Data Structure Dump Routines */ 324 /****************************************************************************/ 325 #ifdef BCE_DEBUG 326 static u32 bce_reg_rd (struct bce_softc *, u32); 327 static void bce_reg_wr (struct bce_softc *, u32, u32); 328 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 329 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 330 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 331 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 332 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 333 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 334 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 335 static void bce_dump_txbd (struct bce_softc *, 336 int, struct tx_bd *); 337 static void bce_dump_rxbd (struct bce_softc *, 338 int, struct rx_bd *); 339 static void bce_dump_pgbd (struct bce_softc *, 340 int, struct rx_bd *); 341 static void bce_dump_l2fhdr (struct bce_softc *, 342 int, struct l2_fhdr *); 343 static void bce_dump_ctx (struct bce_softc *, u16); 344 static void bce_dump_ftqs (struct bce_softc *); 345 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 346 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 347 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 348 static void bce_dump_status_block (struct bce_softc *); 349 static void bce_dump_stats_block (struct bce_softc *); 350 static void bce_dump_driver_state (struct bce_softc *); 351 static void bce_dump_hw_state (struct bce_softc *); 352 static void bce_dump_shmem_state (struct bce_softc *); 353 static void bce_dump_mq_regs (struct bce_softc *); 354 static void bce_dump_bc_state (struct bce_softc *); 355 static void bce_dump_txp_state (struct bce_softc *, int); 356 static void bce_dump_rxp_state (struct bce_softc *, int); 357 static void bce_dump_tpat_state (struct bce_softc *, int); 358 static void bce_dump_cp_state (struct bce_softc *, int); 359 static void bce_dump_com_state (struct bce_softc *, int); 360 static void bce_dump_rv2p_state (struct bce_softc *); 361 static void bce_breakpoint (struct bce_softc *); 362 #endif /*BCE_DEBUG */ 363 364 /****************************************************************************/ 365 /* BCE Register/Memory Access Routines */ 366 /****************************************************************************/ 367 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 368 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 369 static void bce_shmem_wr (struct bce_softc *, u32, u32); 370 static u32 bce_shmem_rd (struct bce_softc *, u32); 371 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 372 static int bce_miibus_read_reg (device_t, int, int); 373 static int bce_miibus_write_reg (device_t, int, int, int); 374 static void bce_miibus_statchg (device_t); 375 376 #ifdef BCE_DEBUG 377 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 378 #ifdef BCE_NVRAM_WRITE_SUPPORT 379 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 380 #endif 381 #endif 382 383 /****************************************************************************/ 384 /* BCE NVRAM Access Routines */ 385 /****************************************************************************/ 386 static int bce_acquire_nvram_lock (struct bce_softc *); 387 static int bce_release_nvram_lock (struct bce_softc *); 388 static void bce_enable_nvram_access(struct bce_softc *); 389 static void bce_disable_nvram_access(struct bce_softc *); 390 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 391 static int bce_init_nvram (struct bce_softc *); 392 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 393 static int bce_nvram_test (struct bce_softc *); 394 #ifdef BCE_NVRAM_WRITE_SUPPORT 395 static int bce_enable_nvram_write (struct bce_softc *); 396 static void bce_disable_nvram_write(struct bce_softc *); 397 static int bce_nvram_erase_page (struct bce_softc *, u32); 398 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 399 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 400 #endif 401 402 /****************************************************************************/ 403 /* */ 404 /****************************************************************************/ 405 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 406 static void bce_get_media (struct bce_softc *); 407 static void bce_init_media (struct bce_softc *); 408 static u32 bce_get_rphy_link (struct bce_softc *); 409 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 410 static int bce_dma_alloc (device_t); 411 static void bce_dma_free (struct bce_softc *); 412 static void bce_release_resources (struct bce_softc *); 413 414 /****************************************************************************/ 415 /* BCE Firmware Synchronization and Load */ 416 /****************************************************************************/ 417 static void bce_fw_cap_init (struct bce_softc *); 418 static int bce_fw_sync (struct bce_softc *, u32); 419 static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32, 420 u32); 421 static void bce_load_cpu_fw (struct bce_softc *, 422 struct cpu_reg *, struct fw_info *); 423 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 424 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 425 static void bce_start_rxp_cpu (struct bce_softc *); 426 static void bce_init_rxp_cpu (struct bce_softc *); 427 static void bce_init_txp_cpu (struct bce_softc *); 428 static void bce_init_tpat_cpu (struct bce_softc *); 429 static void bce_init_cp_cpu (struct bce_softc *); 430 static void bce_init_com_cpu (struct bce_softc *); 431 static void bce_init_cpus (struct bce_softc *); 432 433 static void bce_print_adapter_info (struct bce_softc *); 434 static void bce_probe_pci_caps (device_t, struct bce_softc *); 435 static void bce_stop (struct bce_softc *); 436 static int bce_reset (struct bce_softc *, u32); 437 static int bce_chipinit (struct bce_softc *); 438 static int bce_blockinit (struct bce_softc *); 439 440 static int bce_init_tx_chain (struct bce_softc *); 441 static void bce_free_tx_chain (struct bce_softc *); 442 443 static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *); 444 static int bce_init_rx_chain (struct bce_softc *); 445 static void bce_fill_rx_chain (struct bce_softc *); 446 static void bce_free_rx_chain (struct bce_softc *); 447 448 static int bce_get_pg_buf (struct bce_softc *, u16, u16); 449 static int bce_init_pg_chain (struct bce_softc *); 450 static void bce_fill_pg_chain (struct bce_softc *); 451 static void bce_free_pg_chain (struct bce_softc *); 452 453 static struct mbuf *bce_tso_setup (struct bce_softc *, 454 struct mbuf **, u16 *); 455 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 456 static void bce_start_locked (struct ifnet *); 457 static void bce_start (struct ifnet *); 458 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 459 static uint64_t bce_get_counter (struct ifnet *, ift_counter); 460 static void bce_watchdog (struct bce_softc *); 461 static int bce_ifmedia_upd (struct ifnet *); 462 static int bce_ifmedia_upd_locked (struct ifnet *); 463 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 464 static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *); 465 static void bce_init_locked (struct bce_softc *); 466 static void bce_init (void *); 467 static void bce_mgmt_init_locked (struct bce_softc *sc); 468 469 static int bce_init_ctx (struct bce_softc *); 470 static void bce_get_mac_addr (struct bce_softc *); 471 static void bce_set_mac_addr (struct bce_softc *); 472 static void bce_phy_intr (struct bce_softc *); 473 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 474 static void bce_rx_intr (struct bce_softc *); 475 static void bce_tx_intr (struct bce_softc *); 476 static void bce_disable_intr (struct bce_softc *); 477 static void bce_enable_intr (struct bce_softc *, int); 478 479 static void bce_intr (void *); 480 static void bce_set_rx_mode (struct bce_softc *); 481 static void bce_stats_update (struct bce_softc *); 482 static void bce_tick (void *); 483 static void bce_pulse (void *); 484 static void bce_add_sysctls (struct bce_softc *); 485 486 /****************************************************************************/ 487 /* FreeBSD device dispatch table. */ 488 /****************************************************************************/ 489 static device_method_t bce_methods[] = { 490 /* Device interface (device_if.h) */ 491 DEVMETHOD(device_probe, bce_probe), 492 DEVMETHOD(device_attach, bce_attach), 493 DEVMETHOD(device_detach, bce_detach), 494 DEVMETHOD(device_shutdown, bce_shutdown), 495 /* Supported by device interface but not used here. */ 496 /* DEVMETHOD(device_identify, bce_identify), */ 497 /* DEVMETHOD(device_suspend, bce_suspend), */ 498 /* DEVMETHOD(device_resume, bce_resume), */ 499 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 500 501 /* MII interface (miibus_if.h) */ 502 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 503 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 504 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 505 /* Supported by MII interface but not used here. */ 506 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 507 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 508 509 DEVMETHOD_END 510 }; 511 512 static driver_t bce_driver = { 513 "bce", 514 bce_methods, 515 sizeof(struct bce_softc) 516 }; 517 518 static devclass_t bce_devclass; 519 520 MODULE_DEPEND(bce, pci, 1, 1, 1); 521 MODULE_DEPEND(bce, ether, 1, 1, 1); 522 MODULE_DEPEND(bce, miibus, 1, 1, 1); 523 524 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL); 525 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL); 526 MODULE_PNP_INFO("U16:vendor;U16:device;U16:#;U16:#;D:#", pci, bce, 527 bce_devs, nitems(bce_devs) - 1); 528 529 /****************************************************************************/ 530 /* Tunable device values */ 531 /****************************************************************************/ 532 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 533 "bce driver parameters"); 534 535 /* Allowable values are TRUE or FALSE */ 536 static int bce_verbose = TRUE; 537 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 538 "Verbose output enable/disable"); 539 540 /* Allowable values are TRUE or FALSE */ 541 static int bce_tso_enable = TRUE; 542 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 543 "TSO Enable/Disable"); 544 545 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 546 /* ToDo: Add MSI-X support. */ 547 static int bce_msi_enable = 1; 548 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 549 "MSI-X|MSI|INTx selector"); 550 551 /* Allowable values are 1, 2, 4, 8. */ 552 static int bce_rx_pages = DEFAULT_RX_PAGES; 553 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 554 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 555 556 /* Allowable values are 1, 2, 4, 8. */ 557 static int bce_tx_pages = DEFAULT_TX_PAGES; 558 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 559 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 560 561 /* Allowable values are TRUE or FALSE. */ 562 static int bce_hdr_split = TRUE; 563 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 564 "Frame header/payload splitting Enable/Disable"); 565 566 /* Allowable values are TRUE or FALSE. */ 567 static int bce_strict_rx_mtu = FALSE; 568 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN, 569 &bce_strict_rx_mtu, 0, 570 "Enable/Disable strict RX frame size checking"); 571 572 /* Allowable values are 0 ... 100 */ 573 #ifdef BCE_DEBUG 574 /* Generate 1 interrupt for every transmit completion. */ 575 static int bce_tx_quick_cons_trip_int = 1; 576 #else 577 /* Generate 1 interrupt for every 20 transmit completions. */ 578 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 579 #endif 580 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 581 &bce_tx_quick_cons_trip_int, 0, 582 "Transmit BD trip point during interrupts"); 583 584 /* Allowable values are 0 ... 100 */ 585 /* Generate 1 interrupt for every transmit completion. */ 586 #ifdef BCE_DEBUG 587 static int bce_tx_quick_cons_trip = 1; 588 #else 589 /* Generate 1 interrupt for every 20 transmit completions. */ 590 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 591 #endif 592 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 593 &bce_tx_quick_cons_trip, 0, 594 "Transmit BD trip point"); 595 596 /* Allowable values are 0 ... 100 */ 597 #ifdef BCE_DEBUG 598 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 599 static int bce_tx_ticks_int = 0; 600 #else 601 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 602 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 603 #endif 604 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 605 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 606 607 /* Allowable values are 0 ... 100 */ 608 #ifdef BCE_DEBUG 609 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 610 static int bce_tx_ticks = 0; 611 #else 612 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 613 static int bce_tx_ticks = DEFAULT_TX_TICKS; 614 #endif 615 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 616 &bce_tx_ticks, 0, "Transmit ticks count"); 617 618 /* Allowable values are 1 ... 100 */ 619 #ifdef BCE_DEBUG 620 /* Generate 1 interrupt for every received frame. */ 621 static int bce_rx_quick_cons_trip_int = 1; 622 #else 623 /* Generate 1 interrupt for every 6 received frames. */ 624 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 625 #endif 626 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 627 &bce_rx_quick_cons_trip_int, 0, 628 "Receive BD trip point duirng interrupts"); 629 630 /* Allowable values are 1 ... 100 */ 631 #ifdef BCE_DEBUG 632 /* Generate 1 interrupt for every received frame. */ 633 static int bce_rx_quick_cons_trip = 1; 634 #else 635 /* Generate 1 interrupt for every 6 received frames. */ 636 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 637 #endif 638 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 639 &bce_rx_quick_cons_trip, 0, 640 "Receive BD trip point"); 641 642 /* Allowable values are 0 ... 100 */ 643 #ifdef BCE_DEBUG 644 /* Generate an int. if 0us have elapsed since the last received frame. */ 645 static int bce_rx_ticks_int = 0; 646 #else 647 /* Generate an int. if 18us have elapsed since the last received frame. */ 648 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 649 #endif 650 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 651 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 652 653 /* Allowable values are 0 ... 100 */ 654 #ifdef BCE_DEBUG 655 /* Generate an int. if 0us have elapsed since the last received frame. */ 656 static int bce_rx_ticks = 0; 657 #else 658 /* Generate an int. if 18us have elapsed since the last received frame. */ 659 static int bce_rx_ticks = DEFAULT_RX_TICKS; 660 #endif 661 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 662 &bce_rx_ticks, 0, "Receive ticks count"); 663 664 /****************************************************************************/ 665 /* Device probe function. */ 666 /* */ 667 /* Compares the device to the driver's list of supported devices and */ 668 /* reports back to the OS whether this is the right driver for the device. */ 669 /* */ 670 /* Returns: */ 671 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 672 /****************************************************************************/ 673 static int 674 bce_probe(device_t dev) 675 { 676 const struct bce_type *t; 677 struct bce_softc *sc; 678 char *descbuf; 679 u16 vid = 0, did = 0, svid = 0, sdid = 0; 680 681 t = bce_devs; 682 683 sc = device_get_softc(dev); 684 sc->bce_unit = device_get_unit(dev); 685 sc->bce_dev = dev; 686 687 /* Get the data for the device to be probed. */ 688 vid = pci_get_vendor(dev); 689 did = pci_get_device(dev); 690 svid = pci_get_subvendor(dev); 691 sdid = pci_get_subdevice(dev); 692 693 DBPRINT(sc, BCE_EXTREME_LOAD, 694 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 695 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 696 697 /* Look through the list of known devices for a match. */ 698 while(t->bce_name != NULL) { 699 if ((vid == t->bce_vid) && (did == t->bce_did) && 700 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 701 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 702 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 703 704 if (descbuf == NULL) 705 return(ENOMEM); 706 707 /* Print out the device identity. */ 708 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 709 t->bce_name, (((pci_read_config(dev, 710 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 711 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 712 713 device_set_desc_copy(dev, descbuf); 714 free(descbuf, M_TEMP); 715 return(BUS_PROBE_DEFAULT); 716 } 717 t++; 718 } 719 720 return(ENXIO); 721 } 722 723 /****************************************************************************/ 724 /* PCI Capabilities Probe Function. */ 725 /* */ 726 /* Walks the PCI capabiites list for the device to find what features are */ 727 /* supported. */ 728 /* */ 729 /* Returns: */ 730 /* None. */ 731 /****************************************************************************/ 732 static void 733 bce_print_adapter_info(struct bce_softc *sc) 734 { 735 int i = 0; 736 737 DBENTER(BCE_VERBOSE_LOAD); 738 739 if (bce_verbose || bootverbose) { 740 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 741 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 742 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 743 744 /* Bus info. */ 745 if (sc->bce_flags & BCE_PCIE_FLAG) { 746 printf("Bus (PCIe x%d, ", sc->link_width); 747 switch (sc->link_speed) { 748 case 1: printf("2.5Gbps); "); break; 749 case 2: printf("5Gbps); "); break; 750 default: printf("Unknown link speed); "); 751 } 752 } else { 753 printf("Bus (PCI%s, %s, %dMHz); ", 754 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 755 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 756 "32-bit" : "64-bit"), sc->bus_speed_mhz); 757 } 758 759 /* Firmware version and device features. */ 760 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 761 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 762 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 763 764 if (bce_hdr_split == TRUE) { 765 printf("SPLT"); 766 i++; 767 } 768 769 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 770 if (i > 0) printf("|"); 771 printf("MSI"); i++; 772 } 773 774 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 775 if (i > 0) printf("|"); 776 printf("MSI-X"); i++; 777 } 778 779 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 780 if (i > 0) printf("|"); 781 printf("2.5G"); i++; 782 } 783 784 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) { 785 if (i > 0) printf("|"); 786 printf("Remote PHY(%s)", 787 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ? 788 "FIBER" : "TP"); i++; 789 } 790 791 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 792 if (i > 0) printf("|"); 793 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 794 } else { 795 printf(")\n"); 796 } 797 798 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 799 sc->bce_rx_quick_cons_trip_int, 800 sc->bce_rx_quick_cons_trip, 801 sc->bce_rx_ticks_int, 802 sc->bce_rx_ticks, 803 sc->bce_tx_quick_cons_trip_int, 804 sc->bce_tx_quick_cons_trip, 805 sc->bce_tx_ticks_int, 806 sc->bce_tx_ticks); 807 } 808 809 DBEXIT(BCE_VERBOSE_LOAD); 810 } 811 812 /****************************************************************************/ 813 /* PCI Capabilities Probe Function. */ 814 /* */ 815 /* Walks the PCI capabiites list for the device to find what features are */ 816 /* supported. */ 817 /* */ 818 /* Returns: */ 819 /* None. */ 820 /****************************************************************************/ 821 static void 822 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 823 { 824 u32 reg; 825 826 DBENTER(BCE_VERBOSE_LOAD); 827 828 /* Check if PCI-X capability is enabled. */ 829 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 830 if (reg != 0) 831 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 832 } 833 834 /* Check if PCIe capability is enabled. */ 835 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 836 if (reg != 0) { 837 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 838 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 839 "0x%08X\n", link_status); 840 sc->link_speed = link_status & 0xf; 841 sc->link_width = (link_status >> 4) & 0x3f; 842 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 843 sc->bce_flags |= BCE_PCIE_FLAG; 844 } 845 } 846 847 /* Check if MSI capability is enabled. */ 848 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 849 if (reg != 0) 850 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 851 } 852 853 /* Check if MSI-X capability is enabled. */ 854 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 855 if (reg != 0) 856 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 857 } 858 859 DBEXIT(BCE_VERBOSE_LOAD); 860 } 861 862 /****************************************************************************/ 863 /* Load and validate user tunable settings. */ 864 /* */ 865 /* Returns: */ 866 /* Nothing. */ 867 /****************************************************************************/ 868 static void 869 bce_set_tunables(struct bce_softc *sc) 870 { 871 /* Set sysctl values for RX page count. */ 872 switch (bce_rx_pages) { 873 case 1: 874 /* fall-through */ 875 case 2: 876 /* fall-through */ 877 case 4: 878 /* fall-through */ 879 case 8: 880 sc->rx_pages = bce_rx_pages; 881 break; 882 default: 883 sc->rx_pages = DEFAULT_RX_PAGES; 884 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 885 "hw.bce.rx_pages! Setting default of %d.\n", 886 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 887 } 888 889 /* ToDo: Consider allowing user setting for pg_pages. */ 890 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 891 892 /* Set sysctl values for TX page count. */ 893 switch (bce_tx_pages) { 894 case 1: 895 /* fall-through */ 896 case 2: 897 /* fall-through */ 898 case 4: 899 /* fall-through */ 900 case 8: 901 sc->tx_pages = bce_tx_pages; 902 break; 903 default: 904 sc->tx_pages = DEFAULT_TX_PAGES; 905 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 906 "hw.bce.tx_pages! Setting default of %d.\n", 907 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 908 } 909 910 /* 911 * Validate the TX trip point (i.e. the number of 912 * TX completions before a status block update is 913 * generated and an interrupt is asserted. 914 */ 915 if (bce_tx_quick_cons_trip_int <= 100) { 916 sc->bce_tx_quick_cons_trip_int = 917 bce_tx_quick_cons_trip_int; 918 } else { 919 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 920 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 921 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 922 DEFAULT_TX_QUICK_CONS_TRIP_INT); 923 sc->bce_tx_quick_cons_trip_int = 924 DEFAULT_TX_QUICK_CONS_TRIP_INT; 925 } 926 927 if (bce_tx_quick_cons_trip <= 100) { 928 sc->bce_tx_quick_cons_trip = 929 bce_tx_quick_cons_trip; 930 } else { 931 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 932 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 933 __FILE__, __LINE__, bce_tx_quick_cons_trip, 934 DEFAULT_TX_QUICK_CONS_TRIP); 935 sc->bce_tx_quick_cons_trip = 936 DEFAULT_TX_QUICK_CONS_TRIP; 937 } 938 939 /* 940 * Validate the TX ticks count (i.e. the maximum amount 941 * of time to wait after the last TX completion has 942 * occurred before a status block update is generated 943 * and an interrupt is asserted. 944 */ 945 if (bce_tx_ticks_int <= 100) { 946 sc->bce_tx_ticks_int = 947 bce_tx_ticks_int; 948 } else { 949 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 950 "hw.bce.tx_ticks_int! Setting default of %d.\n", 951 __FILE__, __LINE__, bce_tx_ticks_int, 952 DEFAULT_TX_TICKS_INT); 953 sc->bce_tx_ticks_int = 954 DEFAULT_TX_TICKS_INT; 955 } 956 957 if (bce_tx_ticks <= 100) { 958 sc->bce_tx_ticks = 959 bce_tx_ticks; 960 } else { 961 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 962 "hw.bce.tx_ticks! Setting default of %d.\n", 963 __FILE__, __LINE__, bce_tx_ticks, 964 DEFAULT_TX_TICKS); 965 sc->bce_tx_ticks = 966 DEFAULT_TX_TICKS; 967 } 968 969 /* 970 * Validate the RX trip point (i.e. the number of 971 * RX frames received before a status block update is 972 * generated and an interrupt is asserted. 973 */ 974 if (bce_rx_quick_cons_trip_int <= 100) { 975 sc->bce_rx_quick_cons_trip_int = 976 bce_rx_quick_cons_trip_int; 977 } else { 978 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 979 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 980 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 981 DEFAULT_RX_QUICK_CONS_TRIP_INT); 982 sc->bce_rx_quick_cons_trip_int = 983 DEFAULT_RX_QUICK_CONS_TRIP_INT; 984 } 985 986 if (bce_rx_quick_cons_trip <= 100) { 987 sc->bce_rx_quick_cons_trip = 988 bce_rx_quick_cons_trip; 989 } else { 990 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 991 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 992 __FILE__, __LINE__, bce_rx_quick_cons_trip, 993 DEFAULT_RX_QUICK_CONS_TRIP); 994 sc->bce_rx_quick_cons_trip = 995 DEFAULT_RX_QUICK_CONS_TRIP; 996 } 997 998 /* 999 * Validate the RX ticks count (i.e. the maximum amount 1000 * of time to wait after the last RX frame has been 1001 * received before a status block update is generated 1002 * and an interrupt is asserted. 1003 */ 1004 if (bce_rx_ticks_int <= 100) { 1005 sc->bce_rx_ticks_int = bce_rx_ticks_int; 1006 } else { 1007 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1008 "hw.bce.rx_ticks_int! Setting default of %d.\n", 1009 __FILE__, __LINE__, bce_rx_ticks_int, 1010 DEFAULT_RX_TICKS_INT); 1011 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 1012 } 1013 1014 if (bce_rx_ticks <= 100) { 1015 sc->bce_rx_ticks = bce_rx_ticks; 1016 } else { 1017 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1018 "hw.bce.rx_ticks! Setting default of %d.\n", 1019 __FILE__, __LINE__, bce_rx_ticks, 1020 DEFAULT_RX_TICKS); 1021 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1022 } 1023 1024 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1025 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1026 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1027 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1028 __FILE__, __LINE__); 1029 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1030 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1031 } 1032 1033 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1034 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1035 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1036 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1037 __FILE__, __LINE__); 1038 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1039 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1040 } 1041 } 1042 1043 /****************************************************************************/ 1044 /* Device attach function. */ 1045 /* */ 1046 /* Allocates device resources, performs secondary chip identification, */ 1047 /* resets and initializes the hardware, and initializes driver instance */ 1048 /* variables. */ 1049 /* */ 1050 /* Returns: */ 1051 /* 0 on success, positive value on failure. */ 1052 /****************************************************************************/ 1053 static int 1054 bce_attach(device_t dev) 1055 { 1056 struct bce_softc *sc; 1057 struct ifnet *ifp; 1058 u32 val; 1059 int count, error, rc = 0, rid; 1060 1061 sc = device_get_softc(dev); 1062 sc->bce_dev = dev; 1063 1064 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1065 1066 sc->bce_unit = device_get_unit(dev); 1067 1068 /* Set initial device and PHY flags */ 1069 sc->bce_flags = 0; 1070 sc->bce_phy_flags = 0; 1071 1072 bce_set_tunables(sc); 1073 1074 pci_enable_busmaster(dev); 1075 1076 /* Allocate PCI memory resources. */ 1077 rid = PCIR_BAR(0); 1078 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1079 &rid, RF_ACTIVE); 1080 1081 if (sc->bce_res_mem == NULL) { 1082 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1083 __FILE__, __LINE__); 1084 rc = ENXIO; 1085 goto bce_attach_fail; 1086 } 1087 1088 /* Get various resource handles. */ 1089 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1090 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1091 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1092 1093 bce_probe_pci_caps(dev, sc); 1094 1095 rid = 1; 1096 count = 0; 1097 #if 0 1098 /* Try allocating MSI-X interrupts. */ 1099 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1100 (bce_msi_enable >= 2) && 1101 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1102 &rid, RF_ACTIVE)) != NULL)) { 1103 msi_needed = count = 1; 1104 1105 if (((error = pci_alloc_msix(dev, &count)) != 0) || 1106 (count != msi_needed)) { 1107 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1108 "Received = %d, error = %d\n", __FILE__, __LINE__, 1109 msi_needed, count, error); 1110 count = 0; 1111 pci_release_msi(dev); 1112 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1113 sc->bce_res_irq); 1114 sc->bce_res_irq = NULL; 1115 } else { 1116 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1117 __FUNCTION__); 1118 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1119 } 1120 } 1121 #endif 1122 1123 /* Try allocating a MSI interrupt. */ 1124 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1125 (bce_msi_enable >= 1) && (count == 0)) { 1126 count = 1; 1127 if ((error = pci_alloc_msi(dev, &count)) != 0) { 1128 BCE_PRINTF("%s(%d): MSI allocation failed! " 1129 "error = %d\n", __FILE__, __LINE__, error); 1130 count = 0; 1131 pci_release_msi(dev); 1132 } else { 1133 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1134 "interrupt.\n", __FUNCTION__); 1135 sc->bce_flags |= BCE_USING_MSI_FLAG; 1136 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1137 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1138 rid = 1; 1139 } 1140 } 1141 1142 /* Try allocating a legacy interrupt. */ 1143 if (count == 0) { 1144 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1145 __FUNCTION__); 1146 rid = 0; 1147 } 1148 1149 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1150 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE)); 1151 1152 /* Report any IRQ allocation errors. */ 1153 if (sc->bce_res_irq == NULL) { 1154 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1155 __FILE__, __LINE__); 1156 rc = ENXIO; 1157 goto bce_attach_fail; 1158 } 1159 1160 /* Initialize mutex for the current device instance. */ 1161 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1162 1163 /* 1164 * Configure byte swap and enable indirect register access. 1165 * Rely on CPU to do target byte swapping on big endian systems. 1166 * Access to registers outside of PCI configurtion space are not 1167 * valid until this is done. 1168 */ 1169 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1170 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1171 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1172 1173 /* Save ASIC revsion info. */ 1174 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1175 1176 /* Weed out any non-production controller revisions. */ 1177 switch(BCE_CHIP_ID(sc)) { 1178 case BCE_CHIP_ID_5706_A0: 1179 case BCE_CHIP_ID_5706_A1: 1180 case BCE_CHIP_ID_5708_A0: 1181 case BCE_CHIP_ID_5708_B0: 1182 case BCE_CHIP_ID_5709_A0: 1183 case BCE_CHIP_ID_5709_B0: 1184 case BCE_CHIP_ID_5709_B1: 1185 case BCE_CHIP_ID_5709_B2: 1186 BCE_PRINTF("%s(%d): Unsupported controller " 1187 "revision (%c%d)!\n", __FILE__, __LINE__, 1188 (((pci_read_config(dev, PCIR_REVID, 4) & 1189 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1190 PCIR_REVID, 4) & 0xf)); 1191 rc = ENODEV; 1192 goto bce_attach_fail; 1193 } 1194 1195 /* 1196 * The embedded PCIe to PCI-X bridge (EPB) 1197 * in the 5708 cannot address memory above 1198 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1199 */ 1200 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1201 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1202 else 1203 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1204 1205 /* 1206 * Find the base address for shared memory access. 1207 * Newer versions of bootcode use a signature and offset 1208 * while older versions use a fixed address. 1209 */ 1210 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1211 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1212 /* Multi-port devices use different offsets in shared memory. */ 1213 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1214 (pci_get_function(sc->bce_dev) << 2)); 1215 else 1216 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1217 1218 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1219 __FUNCTION__, sc->bce_shmem_base); 1220 1221 /* Fetch the bootcode revision. */ 1222 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1223 for (int i = 0, j = 0; i < 3; i++) { 1224 u8 num; 1225 1226 num = (u8) (val >> (24 - (i * 8))); 1227 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1228 if (num >= k || !skip0 || k == 1) { 1229 sc->bce_bc_ver[j++] = (num / k) + '0'; 1230 skip0 = 0; 1231 } 1232 } 1233 1234 if (i != 2) 1235 sc->bce_bc_ver[j++] = '.'; 1236 } 1237 1238 /* Check if any management firwmare is enabled. */ 1239 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1240 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1241 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1242 1243 /* Allow time for firmware to enter the running state. */ 1244 for (int i = 0; i < 30; i++) { 1245 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1246 if (val & BCE_CONDITION_MFW_RUN_MASK) 1247 break; 1248 DELAY(10000); 1249 } 1250 1251 /* Check if management firmware is running. */ 1252 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1253 val &= BCE_CONDITION_MFW_RUN_MASK; 1254 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1255 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1256 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1257 int i = 0; 1258 1259 /* Read the management firmware version string. */ 1260 for (int j = 0; j < 3; j++) { 1261 val = bce_reg_rd_ind(sc, addr + j * 4); 1262 val = bswap32(val); 1263 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1264 i += 4; 1265 } 1266 } else { 1267 /* May cause firmware synchronization timeouts. */ 1268 BCE_PRINTF("%s(%d): Management firmware enabled " 1269 "but not running!\n", __FILE__, __LINE__); 1270 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1271 1272 /* ToDo: Any action the driver should take? */ 1273 } 1274 } 1275 1276 /* Get PCI bus information (speed and type). */ 1277 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1278 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1279 u32 clkreg; 1280 1281 sc->bce_flags |= BCE_PCIX_FLAG; 1282 1283 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1284 1285 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1286 switch (clkreg) { 1287 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1288 sc->bus_speed_mhz = 133; 1289 break; 1290 1291 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1292 sc->bus_speed_mhz = 100; 1293 break; 1294 1295 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1296 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1297 sc->bus_speed_mhz = 66; 1298 break; 1299 1300 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1301 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1302 sc->bus_speed_mhz = 50; 1303 break; 1304 1305 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1306 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1307 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1308 sc->bus_speed_mhz = 33; 1309 break; 1310 } 1311 } else { 1312 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1313 sc->bus_speed_mhz = 66; 1314 else 1315 sc->bus_speed_mhz = 33; 1316 } 1317 1318 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1319 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1320 1321 /* Find the media type for the adapter. */ 1322 bce_get_media(sc); 1323 1324 /* Reset controller and announce to bootcode that driver is present. */ 1325 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1326 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1327 __FILE__, __LINE__); 1328 rc = ENXIO; 1329 goto bce_attach_fail; 1330 } 1331 1332 /* Initialize the controller. */ 1333 if (bce_chipinit(sc)) { 1334 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1335 __FILE__, __LINE__); 1336 rc = ENXIO; 1337 goto bce_attach_fail; 1338 } 1339 1340 /* Perform NVRAM test. */ 1341 if (bce_nvram_test(sc)) { 1342 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1343 __FILE__, __LINE__); 1344 rc = ENXIO; 1345 goto bce_attach_fail; 1346 } 1347 1348 /* Fetch the permanent Ethernet MAC address. */ 1349 bce_get_mac_addr(sc); 1350 1351 /* Update statistics once every second. */ 1352 sc->bce_stats_ticks = 1000000 & 0xffff00; 1353 1354 /* Store data needed by PHY driver for backplane applications */ 1355 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1356 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1357 1358 /* Allocate DMA memory resources. */ 1359 if (bce_dma_alloc(dev)) { 1360 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1361 __FILE__, __LINE__); 1362 rc = ENXIO; 1363 goto bce_attach_fail; 1364 } 1365 1366 /* Allocate an ifnet structure. */ 1367 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1368 if (ifp == NULL) { 1369 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1370 __FILE__, __LINE__); 1371 rc = ENXIO; 1372 goto bce_attach_fail; 1373 } 1374 1375 /* Initialize the ifnet interface. */ 1376 ifp->if_softc = sc; 1377 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1378 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1379 ifp->if_ioctl = bce_ioctl; 1380 ifp->if_start = bce_start; 1381 ifp->if_get_counter = bce_get_counter; 1382 ifp->if_init = bce_init; 1383 ifp->if_mtu = ETHERMTU; 1384 1385 if (bce_tso_enable) { 1386 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1387 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1388 IFCAP_VLAN_HWTSO; 1389 } else { 1390 ifp->if_hwassist = BCE_IF_HWASSIST; 1391 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1392 } 1393 1394 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1395 ifp->if_capabilities |= IFCAP_LINKSTATE; 1396 1397 ifp->if_capenable = ifp->if_capabilities; 1398 1399 /* 1400 * Assume standard mbuf sizes for buffer allocation. 1401 * This may change later if the MTU size is set to 1402 * something other than 1500. 1403 */ 1404 bce_get_rx_buffer_sizes(sc, 1405 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1406 1407 /* Recalculate our buffer allocation sizes. */ 1408 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1409 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1410 IFQ_SET_READY(&ifp->if_snd); 1411 1412 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1413 ifp->if_baudrate = IF_Mbps(2500ULL); 1414 else 1415 ifp->if_baudrate = IF_Mbps(1000); 1416 1417 /* Handle any special PHY initialization for SerDes PHYs. */ 1418 bce_init_media(sc); 1419 1420 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 1421 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd, 1422 bce_ifmedia_sts); 1423 /* 1424 * We can't manually override remote PHY's link and assume 1425 * PHY port configuration(Fiber or TP) is not changed after 1426 * device attach. This may not be correct though. 1427 */ 1428 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) { 1429 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 1430 ifmedia_add(&sc->bce_ifmedia, 1431 IFM_ETHER | IFM_2500_SX, 0, NULL); 1432 ifmedia_add(&sc->bce_ifmedia, 1433 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL); 1434 } 1435 ifmedia_add(&sc->bce_ifmedia, 1436 IFM_ETHER | IFM_1000_SX, 0, NULL); 1437 ifmedia_add(&sc->bce_ifmedia, 1438 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1439 } else { 1440 ifmedia_add(&sc->bce_ifmedia, 1441 IFM_ETHER | IFM_10_T, 0, NULL); 1442 ifmedia_add(&sc->bce_ifmedia, 1443 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1444 ifmedia_add(&sc->bce_ifmedia, 1445 IFM_ETHER | IFM_100_TX, 0, NULL); 1446 ifmedia_add(&sc->bce_ifmedia, 1447 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1448 ifmedia_add(&sc->bce_ifmedia, 1449 IFM_ETHER | IFM_1000_T, 0, NULL); 1450 ifmedia_add(&sc->bce_ifmedia, 1451 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1452 } 1453 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1454 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO); 1455 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media; 1456 } else { 1457 /* MII child bus by attaching the PHY. */ 1458 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1459 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1460 MII_OFFSET_ANY, MIIF_DOPAUSE); 1461 if (rc != 0) { 1462 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1463 __LINE__); 1464 goto bce_attach_fail; 1465 } 1466 } 1467 1468 /* Attach to the Ethernet interface list. */ 1469 ether_ifattach(ifp, sc->eaddr); 1470 1471 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1472 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1473 1474 /* Hookup IRQ last. */ 1475 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1476 NULL, bce_intr, sc, &sc->bce_intrhand); 1477 1478 if (rc) { 1479 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1480 __FILE__, __LINE__); 1481 bce_detach(dev); 1482 goto bce_attach_exit; 1483 } 1484 1485 /* 1486 * At this point we've acquired all the resources 1487 * we need to run so there's no turning back, we're 1488 * cleared for launch. 1489 */ 1490 1491 /* Print some important debugging info. */ 1492 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1493 1494 /* Add the supported sysctls to the kernel. */ 1495 bce_add_sysctls(sc); 1496 1497 BCE_LOCK(sc); 1498 1499 /* 1500 * The chip reset earlier notified the bootcode that 1501 * a driver is present. We now need to start our pulse 1502 * routine so that the bootcode is reminded that we're 1503 * still running. 1504 */ 1505 bce_pulse(sc); 1506 1507 bce_mgmt_init_locked(sc); 1508 BCE_UNLOCK(sc); 1509 1510 /* Finally, print some useful adapter info */ 1511 bce_print_adapter_info(sc); 1512 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1513 __FUNCTION__, sc); 1514 1515 goto bce_attach_exit; 1516 1517 bce_attach_fail: 1518 bce_release_resources(sc); 1519 1520 bce_attach_exit: 1521 1522 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1523 1524 return(rc); 1525 } 1526 1527 /****************************************************************************/ 1528 /* Device detach function. */ 1529 /* */ 1530 /* Stops the controller, resets the controller, and releases resources. */ 1531 /* */ 1532 /* Returns: */ 1533 /* 0 on success, positive value on failure. */ 1534 /****************************************************************************/ 1535 static int 1536 bce_detach(device_t dev) 1537 { 1538 struct bce_softc *sc = device_get_softc(dev); 1539 struct ifnet *ifp; 1540 u32 msg; 1541 1542 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1543 1544 ifp = sc->bce_ifp; 1545 1546 /* Stop and reset the controller. */ 1547 BCE_LOCK(sc); 1548 1549 /* Stop the pulse so the bootcode can go to driver absent state. */ 1550 callout_stop(&sc->bce_pulse_callout); 1551 1552 bce_stop(sc); 1553 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1554 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1555 else 1556 msg = BCE_DRV_MSG_CODE_UNLOAD; 1557 bce_reset(sc, msg); 1558 1559 BCE_UNLOCK(sc); 1560 1561 ether_ifdetach(ifp); 1562 1563 /* If we have a child device on the MII bus remove it too. */ 1564 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1565 ifmedia_removeall(&sc->bce_ifmedia); 1566 else { 1567 bus_generic_detach(dev); 1568 device_delete_child(dev, sc->bce_miibus); 1569 } 1570 1571 /* Release all remaining resources. */ 1572 bce_release_resources(sc); 1573 1574 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1575 1576 return(0); 1577 } 1578 1579 /****************************************************************************/ 1580 /* Device shutdown function. */ 1581 /* */ 1582 /* Stops and resets the controller. */ 1583 /* */ 1584 /* Returns: */ 1585 /* 0 on success, positive value on failure. */ 1586 /****************************************************************************/ 1587 static int 1588 bce_shutdown(device_t dev) 1589 { 1590 struct bce_softc *sc = device_get_softc(dev); 1591 u32 msg; 1592 1593 DBENTER(BCE_VERBOSE); 1594 1595 BCE_LOCK(sc); 1596 bce_stop(sc); 1597 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1598 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1599 else 1600 msg = BCE_DRV_MSG_CODE_UNLOAD; 1601 bce_reset(sc, msg); 1602 BCE_UNLOCK(sc); 1603 1604 DBEXIT(BCE_VERBOSE); 1605 1606 return (0); 1607 } 1608 1609 #ifdef BCE_DEBUG 1610 /****************************************************************************/ 1611 /* Register read. */ 1612 /* */ 1613 /* Returns: */ 1614 /* The value of the register. */ 1615 /****************************************************************************/ 1616 static u32 1617 bce_reg_rd(struct bce_softc *sc, u32 offset) 1618 { 1619 u32 val = REG_RD(sc, offset); 1620 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1621 __FUNCTION__, offset, val); 1622 return val; 1623 } 1624 1625 /****************************************************************************/ 1626 /* Register write (16 bit). */ 1627 /* */ 1628 /* Returns: */ 1629 /* Nothing. */ 1630 /****************************************************************************/ 1631 static void 1632 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1633 { 1634 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1635 __FUNCTION__, offset, val); 1636 REG_WR16(sc, offset, val); 1637 } 1638 1639 /****************************************************************************/ 1640 /* Register write. */ 1641 /* */ 1642 /* Returns: */ 1643 /* Nothing. */ 1644 /****************************************************************************/ 1645 static void 1646 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1647 { 1648 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1649 __FUNCTION__, offset, val); 1650 REG_WR(sc, offset, val); 1651 } 1652 #endif 1653 1654 /****************************************************************************/ 1655 /* Indirect register read. */ 1656 /* */ 1657 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1658 /* configuration space. Using this mechanism avoids issues with posted */ 1659 /* reads but is much slower than memory-mapped I/O. */ 1660 /* */ 1661 /* Returns: */ 1662 /* The value of the register. */ 1663 /****************************************************************************/ 1664 static u32 1665 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1666 { 1667 device_t dev; 1668 dev = sc->bce_dev; 1669 1670 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1671 #ifdef BCE_DEBUG 1672 { 1673 u32 val; 1674 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1675 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1676 __FUNCTION__, offset, val); 1677 return val; 1678 } 1679 #else 1680 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1681 #endif 1682 } 1683 1684 /****************************************************************************/ 1685 /* Indirect register write. */ 1686 /* */ 1687 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1688 /* configuration space. Using this mechanism avoids issues with posted */ 1689 /* writes but is muchh slower than memory-mapped I/O. */ 1690 /* */ 1691 /* Returns: */ 1692 /* Nothing. */ 1693 /****************************************************************************/ 1694 static void 1695 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1696 { 1697 device_t dev; 1698 dev = sc->bce_dev; 1699 1700 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1701 __FUNCTION__, offset, val); 1702 1703 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1704 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1705 } 1706 1707 /****************************************************************************/ 1708 /* Shared memory write. */ 1709 /* */ 1710 /* Writes NetXtreme II shared memory region. */ 1711 /* */ 1712 /* Returns: */ 1713 /* Nothing. */ 1714 /****************************************************************************/ 1715 static void 1716 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1717 { 1718 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1719 "0x%08X\n", __FUNCTION__, val, offset); 1720 1721 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1722 } 1723 1724 /****************************************************************************/ 1725 /* Shared memory read. */ 1726 /* */ 1727 /* Reads NetXtreme II shared memory region. */ 1728 /* */ 1729 /* Returns: */ 1730 /* The 32 bit value read. */ 1731 /****************************************************************************/ 1732 static u32 1733 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1734 { 1735 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1736 1737 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1738 "0x%08X\n", __FUNCTION__, val, offset); 1739 1740 return val; 1741 } 1742 1743 #ifdef BCE_DEBUG 1744 /****************************************************************************/ 1745 /* Context memory read. */ 1746 /* */ 1747 /* The NetXtreme II controller uses context memory to track connection */ 1748 /* information for L2 and higher network protocols. */ 1749 /* */ 1750 /* Returns: */ 1751 /* The requested 32 bit value of context memory. */ 1752 /****************************************************************************/ 1753 static u32 1754 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1755 { 1756 u32 idx, offset, retry_cnt = 5, val; 1757 1758 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1759 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1760 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1761 1762 offset = ctx_offset + cid_addr; 1763 1764 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1765 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1766 1767 for (idx = 0; idx < retry_cnt; idx++) { 1768 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1769 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1770 break; 1771 DELAY(5); 1772 } 1773 1774 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1775 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1776 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1777 __FILE__, __LINE__, cid_addr, ctx_offset); 1778 1779 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1780 } else { 1781 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1782 val = REG_RD(sc, BCE_CTX_DATA); 1783 } 1784 1785 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1786 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1787 1788 return(val); 1789 } 1790 #endif 1791 1792 /****************************************************************************/ 1793 /* Context memory write. */ 1794 /* */ 1795 /* The NetXtreme II controller uses context memory to track connection */ 1796 /* information for L2 and higher network protocols. */ 1797 /* */ 1798 /* Returns: */ 1799 /* Nothing. */ 1800 /****************************************************************************/ 1801 static void 1802 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1803 { 1804 u32 idx, offset = ctx_offset + cid_addr; 1805 u32 val, retry_cnt = 5; 1806 1807 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1808 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1809 1810 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1811 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1812 __FUNCTION__, cid_addr)); 1813 1814 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1815 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1816 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1817 1818 for (idx = 0; idx < retry_cnt; idx++) { 1819 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1820 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1821 break; 1822 DELAY(5); 1823 } 1824 1825 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1826 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1827 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1828 __FILE__, __LINE__, cid_addr, ctx_offset); 1829 1830 } else { 1831 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1832 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1833 } 1834 } 1835 1836 /****************************************************************************/ 1837 /* PHY register read. */ 1838 /* */ 1839 /* Implements register reads on the MII bus. */ 1840 /* */ 1841 /* Returns: */ 1842 /* The value of the register. */ 1843 /****************************************************************************/ 1844 static int 1845 bce_miibus_read_reg(device_t dev, int phy, int reg) 1846 { 1847 struct bce_softc *sc; 1848 u32 val; 1849 int i; 1850 1851 sc = device_get_softc(dev); 1852 1853 /* 1854 * The 5709S PHY is an IEEE Clause 45 PHY 1855 * with special mappings to work with IEEE 1856 * Clause 22 register accesses. 1857 */ 1858 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1859 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1860 reg += 0x10; 1861 } 1862 1863 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1864 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1865 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1866 1867 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1868 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1869 1870 DELAY(40); 1871 } 1872 1873 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1874 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1875 BCE_EMAC_MDIO_COMM_START_BUSY; 1876 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1877 1878 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1879 DELAY(10); 1880 1881 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1882 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1883 DELAY(5); 1884 1885 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1886 val &= BCE_EMAC_MDIO_COMM_DATA; 1887 1888 break; 1889 } 1890 } 1891 1892 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1893 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1894 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1895 val = 0x0; 1896 } else { 1897 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1898 } 1899 1900 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1901 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1902 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1903 1904 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1905 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1906 1907 DELAY(40); 1908 } 1909 1910 DB_PRINT_PHY_REG(reg, val); 1911 return (val & 0xffff); 1912 } 1913 1914 /****************************************************************************/ 1915 /* PHY register write. */ 1916 /* */ 1917 /* Implements register writes on the MII bus. */ 1918 /* */ 1919 /* Returns: */ 1920 /* The value of the register. */ 1921 /****************************************************************************/ 1922 static int 1923 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1924 { 1925 struct bce_softc *sc; 1926 u32 val1; 1927 int i; 1928 1929 sc = device_get_softc(dev); 1930 1931 DB_PRINT_PHY_REG(reg, val); 1932 1933 /* 1934 * The 5709S PHY is an IEEE Clause 45 PHY 1935 * with special mappings to work with IEEE 1936 * Clause 22 register accesses. 1937 */ 1938 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1939 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1940 reg += 0x10; 1941 } 1942 1943 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1944 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1945 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1946 1947 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1948 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1949 1950 DELAY(40); 1951 } 1952 1953 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1954 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1955 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1956 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1957 1958 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1959 DELAY(10); 1960 1961 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1962 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1963 DELAY(5); 1964 break; 1965 } 1966 } 1967 1968 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1969 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1970 __FILE__, __LINE__); 1971 1972 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1973 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1974 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1975 1976 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1977 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1978 1979 DELAY(40); 1980 } 1981 1982 return 0; 1983 } 1984 1985 /****************************************************************************/ 1986 /* MII bus status change. */ 1987 /* */ 1988 /* Called by the MII bus driver when the PHY establishes link to set the */ 1989 /* MAC interface registers. */ 1990 /* */ 1991 /* Returns: */ 1992 /* Nothing. */ 1993 /****************************************************************************/ 1994 static void 1995 bce_miibus_statchg(device_t dev) 1996 { 1997 struct bce_softc *sc; 1998 struct mii_data *mii; 1999 struct ifmediareq ifmr; 2000 int media_active, media_status, val; 2001 2002 sc = device_get_softc(dev); 2003 2004 DBENTER(BCE_VERBOSE_PHY); 2005 2006 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 2007 bzero(&ifmr, sizeof(ifmr)); 2008 bce_ifmedia_sts_rphy(sc, &ifmr); 2009 media_active = ifmr.ifm_active; 2010 media_status = ifmr.ifm_status; 2011 } else { 2012 mii = device_get_softc(sc->bce_miibus); 2013 media_active = mii->mii_media_active; 2014 media_status = mii->mii_media_status; 2015 } 2016 2017 /* Ignore invalid media status. */ 2018 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) != 2019 (IFM_ACTIVE | IFM_AVALID)) 2020 goto bce_miibus_statchg_exit; 2021 2022 val = REG_RD(sc, BCE_EMAC_MODE); 2023 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2024 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2025 BCE_EMAC_MODE_25G); 2026 2027 /* Set MII or GMII interface based on the PHY speed. */ 2028 switch (IFM_SUBTYPE(media_active)) { 2029 case IFM_10_T: 2030 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2031 DBPRINT(sc, BCE_INFO_PHY, 2032 "Enabling 10Mb interface.\n"); 2033 val |= BCE_EMAC_MODE_PORT_MII_10; 2034 break; 2035 } 2036 /* fall-through */ 2037 case IFM_100_TX: 2038 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2039 val |= BCE_EMAC_MODE_PORT_MII; 2040 break; 2041 case IFM_2500_SX: 2042 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2043 val |= BCE_EMAC_MODE_25G; 2044 /* fall-through */ 2045 case IFM_1000_T: 2046 case IFM_1000_SX: 2047 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2048 val |= BCE_EMAC_MODE_PORT_GMII; 2049 break; 2050 default: 2051 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2052 "default GMII interface.\n"); 2053 val |= BCE_EMAC_MODE_PORT_GMII; 2054 } 2055 2056 /* Set half or full duplex based on PHY settings. */ 2057 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) { 2058 DBPRINT(sc, BCE_INFO_PHY, 2059 "Setting Half-Duplex interface.\n"); 2060 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2061 } else 2062 DBPRINT(sc, BCE_INFO_PHY, 2063 "Setting Full-Duplex interface.\n"); 2064 2065 REG_WR(sc, BCE_EMAC_MODE, val); 2066 2067 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) { 2068 DBPRINT(sc, BCE_INFO_PHY, 2069 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2070 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2071 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL; 2072 } else { 2073 DBPRINT(sc, BCE_INFO_PHY, 2074 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2075 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2076 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL; 2077 } 2078 2079 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) { 2080 DBPRINT(sc, BCE_INFO_PHY, 2081 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2082 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2083 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2084 } else { 2085 DBPRINT(sc, BCE_INFO_PHY, 2086 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2087 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2088 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2089 } 2090 2091 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2092 2093 bce_miibus_statchg_exit: 2094 DBEXIT(BCE_VERBOSE_PHY); 2095 } 2096 2097 /****************************************************************************/ 2098 /* Acquire NVRAM lock. */ 2099 /* */ 2100 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2101 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2102 /* for use by the driver. */ 2103 /* */ 2104 /* Returns: */ 2105 /* 0 on success, positive value on failure. */ 2106 /****************************************************************************/ 2107 static int 2108 bce_acquire_nvram_lock(struct bce_softc *sc) 2109 { 2110 u32 val; 2111 int j, rc = 0; 2112 2113 DBENTER(BCE_VERBOSE_NVRAM); 2114 2115 /* Request access to the flash interface. */ 2116 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2117 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2118 val = REG_RD(sc, BCE_NVM_SW_ARB); 2119 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2120 break; 2121 2122 DELAY(5); 2123 } 2124 2125 if (j >= NVRAM_TIMEOUT_COUNT) { 2126 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2127 rc = EBUSY; 2128 } 2129 2130 DBEXIT(BCE_VERBOSE_NVRAM); 2131 return (rc); 2132 } 2133 2134 /****************************************************************************/ 2135 /* Release NVRAM lock. */ 2136 /* */ 2137 /* When the caller is finished accessing NVRAM the lock must be released. */ 2138 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2139 /* for use by the driver. */ 2140 /* */ 2141 /* Returns: */ 2142 /* 0 on success, positive value on failure. */ 2143 /****************************************************************************/ 2144 static int 2145 bce_release_nvram_lock(struct bce_softc *sc) 2146 { 2147 u32 val; 2148 int j, rc = 0; 2149 2150 DBENTER(BCE_VERBOSE_NVRAM); 2151 2152 /* 2153 * Relinquish nvram interface. 2154 */ 2155 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2156 2157 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2158 val = REG_RD(sc, BCE_NVM_SW_ARB); 2159 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2160 break; 2161 2162 DELAY(5); 2163 } 2164 2165 if (j >= NVRAM_TIMEOUT_COUNT) { 2166 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2167 rc = EBUSY; 2168 } 2169 2170 DBEXIT(BCE_VERBOSE_NVRAM); 2171 return (rc); 2172 } 2173 2174 #ifdef BCE_NVRAM_WRITE_SUPPORT 2175 /****************************************************************************/ 2176 /* Enable NVRAM write access. */ 2177 /* */ 2178 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2179 /* */ 2180 /* Returns: */ 2181 /* 0 on success, positive value on failure. */ 2182 /****************************************************************************/ 2183 static int 2184 bce_enable_nvram_write(struct bce_softc *sc) 2185 { 2186 u32 val; 2187 int rc = 0; 2188 2189 DBENTER(BCE_VERBOSE_NVRAM); 2190 2191 val = REG_RD(sc, BCE_MISC_CFG); 2192 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2193 2194 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2195 int j; 2196 2197 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2198 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2199 2200 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2201 DELAY(5); 2202 2203 val = REG_RD(sc, BCE_NVM_COMMAND); 2204 if (val & BCE_NVM_COMMAND_DONE) 2205 break; 2206 } 2207 2208 if (j >= NVRAM_TIMEOUT_COUNT) { 2209 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2210 rc = EBUSY; 2211 } 2212 } 2213 2214 DBENTER(BCE_VERBOSE_NVRAM); 2215 return (rc); 2216 } 2217 2218 /****************************************************************************/ 2219 /* Disable NVRAM write access. */ 2220 /* */ 2221 /* When the caller is finished writing to NVRAM write access must be */ 2222 /* disabled. */ 2223 /* */ 2224 /* Returns: */ 2225 /* Nothing. */ 2226 /****************************************************************************/ 2227 static void 2228 bce_disable_nvram_write(struct bce_softc *sc) 2229 { 2230 u32 val; 2231 2232 DBENTER(BCE_VERBOSE_NVRAM); 2233 2234 val = REG_RD(sc, BCE_MISC_CFG); 2235 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2236 2237 DBEXIT(BCE_VERBOSE_NVRAM); 2238 2239 } 2240 #endif 2241 2242 /****************************************************************************/ 2243 /* Enable NVRAM access. */ 2244 /* */ 2245 /* Before accessing NVRAM for read or write operations the caller must */ 2246 /* enabled NVRAM access. */ 2247 /* */ 2248 /* Returns: */ 2249 /* Nothing. */ 2250 /****************************************************************************/ 2251 static void 2252 bce_enable_nvram_access(struct bce_softc *sc) 2253 { 2254 u32 val; 2255 2256 DBENTER(BCE_VERBOSE_NVRAM); 2257 2258 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2259 /* Enable both bits, even on read. */ 2260 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2261 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2262 2263 DBEXIT(BCE_VERBOSE_NVRAM); 2264 } 2265 2266 /****************************************************************************/ 2267 /* Disable NVRAM access. */ 2268 /* */ 2269 /* When the caller is finished accessing NVRAM access must be disabled. */ 2270 /* */ 2271 /* Returns: */ 2272 /* Nothing. */ 2273 /****************************************************************************/ 2274 static void 2275 bce_disable_nvram_access(struct bce_softc *sc) 2276 { 2277 u32 val; 2278 2279 DBENTER(BCE_VERBOSE_NVRAM); 2280 2281 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2282 2283 /* Disable both bits, even after read. */ 2284 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2285 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2286 2287 DBEXIT(BCE_VERBOSE_NVRAM); 2288 } 2289 2290 #ifdef BCE_NVRAM_WRITE_SUPPORT 2291 /****************************************************************************/ 2292 /* Erase NVRAM page before writing. */ 2293 /* */ 2294 /* Non-buffered flash parts require that a page be erased before it is */ 2295 /* written. */ 2296 /* */ 2297 /* Returns: */ 2298 /* 0 on success, positive value on failure. */ 2299 /****************************************************************************/ 2300 static int 2301 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2302 { 2303 u32 cmd; 2304 int j, rc = 0; 2305 2306 DBENTER(BCE_VERBOSE_NVRAM); 2307 2308 /* Buffered flash doesn't require an erase. */ 2309 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2310 goto bce_nvram_erase_page_exit; 2311 2312 /* Build an erase command. */ 2313 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2314 BCE_NVM_COMMAND_DOIT; 2315 2316 /* 2317 * Clear the DONE bit separately, set the NVRAM address to erase, 2318 * and issue the erase command. 2319 */ 2320 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2321 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2322 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2323 2324 /* Wait for completion. */ 2325 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2326 u32 val; 2327 2328 DELAY(5); 2329 2330 val = REG_RD(sc, BCE_NVM_COMMAND); 2331 if (val & BCE_NVM_COMMAND_DONE) 2332 break; 2333 } 2334 2335 if (j >= NVRAM_TIMEOUT_COUNT) { 2336 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2337 rc = EBUSY; 2338 } 2339 2340 bce_nvram_erase_page_exit: 2341 DBEXIT(BCE_VERBOSE_NVRAM); 2342 return (rc); 2343 } 2344 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2345 2346 /****************************************************************************/ 2347 /* Read a dword (32 bits) from NVRAM. */ 2348 /* */ 2349 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2350 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2351 /* */ 2352 /* Returns: */ 2353 /* 0 on success and the 32 bit value read, positive value on failure. */ 2354 /****************************************************************************/ 2355 static int 2356 bce_nvram_read_dword(struct bce_softc *sc, 2357 u32 offset, u8 *ret_val, u32 cmd_flags) 2358 { 2359 u32 cmd; 2360 int i, rc = 0; 2361 2362 DBENTER(BCE_EXTREME_NVRAM); 2363 2364 /* Build the command word. */ 2365 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2366 2367 /* Calculate the offset for buffered flash if translation is used. */ 2368 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2369 offset = ((offset / sc->bce_flash_info->page_size) << 2370 sc->bce_flash_info->page_bits) + 2371 (offset % sc->bce_flash_info->page_size); 2372 } 2373 2374 /* 2375 * Clear the DONE bit separately, set the address to read, 2376 * and issue the read. 2377 */ 2378 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2379 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2380 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2381 2382 /* Wait for completion. */ 2383 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2384 u32 val; 2385 2386 DELAY(5); 2387 2388 val = REG_RD(sc, BCE_NVM_COMMAND); 2389 if (val & BCE_NVM_COMMAND_DONE) { 2390 val = REG_RD(sc, BCE_NVM_READ); 2391 2392 val = bce_be32toh(val); 2393 memcpy(ret_val, &val, 4); 2394 break; 2395 } 2396 } 2397 2398 /* Check for errors. */ 2399 if (i >= NVRAM_TIMEOUT_COUNT) { 2400 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2401 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2402 rc = EBUSY; 2403 } 2404 2405 DBEXIT(BCE_EXTREME_NVRAM); 2406 return(rc); 2407 } 2408 2409 #ifdef BCE_NVRAM_WRITE_SUPPORT 2410 /****************************************************************************/ 2411 /* Write a dword (32 bits) to NVRAM. */ 2412 /* */ 2413 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2414 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2415 /* enabled NVRAM write access. */ 2416 /* */ 2417 /* Returns: */ 2418 /* 0 on success, positive value on failure. */ 2419 /****************************************************************************/ 2420 static int 2421 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2422 u32 cmd_flags) 2423 { 2424 u32 cmd, val32; 2425 int j, rc = 0; 2426 2427 DBENTER(BCE_VERBOSE_NVRAM); 2428 2429 /* Build the command word. */ 2430 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2431 2432 /* Calculate the offset for buffered flash if translation is used. */ 2433 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2434 offset = ((offset / sc->bce_flash_info->page_size) << 2435 sc->bce_flash_info->page_bits) + 2436 (offset % sc->bce_flash_info->page_size); 2437 } 2438 2439 /* 2440 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2441 * set the NVRAM address to write, and issue the write command 2442 */ 2443 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2444 memcpy(&val32, val, 4); 2445 val32 = htobe32(val32); 2446 REG_WR(sc, BCE_NVM_WRITE, val32); 2447 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2448 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2449 2450 /* Wait for completion. */ 2451 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2452 DELAY(5); 2453 2454 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2455 break; 2456 } 2457 if (j >= NVRAM_TIMEOUT_COUNT) { 2458 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2459 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2460 rc = EBUSY; 2461 } 2462 2463 DBEXIT(BCE_VERBOSE_NVRAM); 2464 return (rc); 2465 } 2466 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2467 2468 /****************************************************************************/ 2469 /* Initialize NVRAM access. */ 2470 /* */ 2471 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2472 /* access that device. */ 2473 /* */ 2474 /* Returns: */ 2475 /* 0 on success, positive value on failure. */ 2476 /****************************************************************************/ 2477 static int 2478 bce_init_nvram(struct bce_softc *sc) 2479 { 2480 u32 val; 2481 int j, entry_count, rc = 0; 2482 const struct flash_spec *flash; 2483 2484 DBENTER(BCE_VERBOSE_NVRAM); 2485 2486 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2487 sc->bce_flash_info = &flash_5709; 2488 goto bce_init_nvram_get_flash_size; 2489 } 2490 2491 /* Determine the selected interface. */ 2492 val = REG_RD(sc, BCE_NVM_CFG1); 2493 2494 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2495 2496 /* 2497 * Flash reconfiguration is required to support additional 2498 * NVRAM devices not directly supported in hardware. 2499 * Check if the flash interface was reconfigured 2500 * by the bootcode. 2501 */ 2502 2503 if (val & 0x40000000) { 2504 /* Flash interface reconfigured by bootcode. */ 2505 2506 DBPRINT(sc,BCE_INFO_LOAD, 2507 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2508 2509 for (j = 0, flash = &flash_table[0]; j < entry_count; 2510 j++, flash++) { 2511 if ((val & FLASH_BACKUP_STRAP_MASK) == 2512 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2513 sc->bce_flash_info = flash; 2514 break; 2515 } 2516 } 2517 } else { 2518 /* Flash interface not yet reconfigured. */ 2519 u32 mask; 2520 2521 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2522 __FUNCTION__); 2523 2524 if (val & (1 << 23)) 2525 mask = FLASH_BACKUP_STRAP_MASK; 2526 else 2527 mask = FLASH_STRAP_MASK; 2528 2529 /* Look for the matching NVRAM device configuration data. */ 2530 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2531 /* Check if the device matches any of the known devices. */ 2532 if ((val & mask) == (flash->strapping & mask)) { 2533 /* Found a device match. */ 2534 sc->bce_flash_info = flash; 2535 2536 /* Request access to the flash interface. */ 2537 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2538 return rc; 2539 2540 /* Reconfigure the flash interface. */ 2541 bce_enable_nvram_access(sc); 2542 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2543 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2544 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2545 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2546 bce_disable_nvram_access(sc); 2547 bce_release_nvram_lock(sc); 2548 2549 break; 2550 } 2551 } 2552 } 2553 2554 /* Check if a matching device was found. */ 2555 if (j == entry_count) { 2556 sc->bce_flash_info = NULL; 2557 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2558 __FILE__, __LINE__); 2559 DBEXIT(BCE_VERBOSE_NVRAM); 2560 return (ENODEV); 2561 } 2562 2563 bce_init_nvram_get_flash_size: 2564 /* Write the flash config data to the shared memory interface. */ 2565 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2566 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2567 if (val) 2568 sc->bce_flash_size = val; 2569 else 2570 sc->bce_flash_size = sc->bce_flash_info->total_size; 2571 2572 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2573 __FUNCTION__, sc->bce_flash_info->name, 2574 sc->bce_flash_info->total_size); 2575 2576 DBEXIT(BCE_VERBOSE_NVRAM); 2577 return rc; 2578 } 2579 2580 /****************************************************************************/ 2581 /* Read an arbitrary range of data from NVRAM. */ 2582 /* */ 2583 /* Prepares the NVRAM interface for access and reads the requested data */ 2584 /* into the supplied buffer. */ 2585 /* */ 2586 /* Returns: */ 2587 /* 0 on success and the data read, positive value on failure. */ 2588 /****************************************************************************/ 2589 static int 2590 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2591 int buf_size) 2592 { 2593 int rc = 0; 2594 u32 cmd_flags, offset32, len32, extra; 2595 2596 DBENTER(BCE_VERBOSE_NVRAM); 2597 2598 if (buf_size == 0) 2599 goto bce_nvram_read_exit; 2600 2601 /* Request access to the flash interface. */ 2602 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2603 goto bce_nvram_read_exit; 2604 2605 /* Enable access to flash interface */ 2606 bce_enable_nvram_access(sc); 2607 2608 len32 = buf_size; 2609 offset32 = offset; 2610 extra = 0; 2611 2612 cmd_flags = 0; 2613 2614 if (offset32 & 3) { 2615 u8 buf[4]; 2616 u32 pre_len; 2617 2618 offset32 &= ~3; 2619 pre_len = 4 - (offset & 3); 2620 2621 if (pre_len >= len32) { 2622 pre_len = len32; 2623 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2624 } 2625 else { 2626 cmd_flags = BCE_NVM_COMMAND_FIRST; 2627 } 2628 2629 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2630 2631 if (rc) 2632 return rc; 2633 2634 memcpy(ret_buf, buf + (offset & 3), pre_len); 2635 2636 offset32 += 4; 2637 ret_buf += pre_len; 2638 len32 -= pre_len; 2639 } 2640 2641 if (len32 & 3) { 2642 extra = 4 - (len32 & 3); 2643 len32 = (len32 + 4) & ~3; 2644 } 2645 2646 if (len32 == 4) { 2647 u8 buf[4]; 2648 2649 if (cmd_flags) 2650 cmd_flags = BCE_NVM_COMMAND_LAST; 2651 else 2652 cmd_flags = BCE_NVM_COMMAND_FIRST | 2653 BCE_NVM_COMMAND_LAST; 2654 2655 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2656 2657 memcpy(ret_buf, buf, 4 - extra); 2658 } 2659 else if (len32 > 0) { 2660 u8 buf[4]; 2661 2662 /* Read the first word. */ 2663 if (cmd_flags) 2664 cmd_flags = 0; 2665 else 2666 cmd_flags = BCE_NVM_COMMAND_FIRST; 2667 2668 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2669 2670 /* Advance to the next dword. */ 2671 offset32 += 4; 2672 ret_buf += 4; 2673 len32 -= 4; 2674 2675 while (len32 > 4 && rc == 0) { 2676 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2677 2678 /* Advance to the next dword. */ 2679 offset32 += 4; 2680 ret_buf += 4; 2681 len32 -= 4; 2682 } 2683 2684 if (rc) 2685 goto bce_nvram_read_locked_exit; 2686 2687 cmd_flags = BCE_NVM_COMMAND_LAST; 2688 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2689 2690 memcpy(ret_buf, buf, 4 - extra); 2691 } 2692 2693 bce_nvram_read_locked_exit: 2694 /* Disable access to flash interface and release the lock. */ 2695 bce_disable_nvram_access(sc); 2696 bce_release_nvram_lock(sc); 2697 2698 bce_nvram_read_exit: 2699 DBEXIT(BCE_VERBOSE_NVRAM); 2700 return rc; 2701 } 2702 2703 #ifdef BCE_NVRAM_WRITE_SUPPORT 2704 /****************************************************************************/ 2705 /* Write an arbitrary range of data from NVRAM. */ 2706 /* */ 2707 /* Prepares the NVRAM interface for write access and writes the requested */ 2708 /* data from the supplied buffer. The caller is responsible for */ 2709 /* calculating any appropriate CRCs. */ 2710 /* */ 2711 /* Returns: */ 2712 /* 0 on success, positive value on failure. */ 2713 /****************************************************************************/ 2714 static int 2715 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2716 int buf_size) 2717 { 2718 u32 written, offset32, len32; 2719 u8 *buf, start[4], end[4]; 2720 int rc = 0; 2721 int align_start, align_end; 2722 2723 DBENTER(BCE_VERBOSE_NVRAM); 2724 2725 buf = data_buf; 2726 offset32 = offset; 2727 len32 = buf_size; 2728 align_start = align_end = 0; 2729 2730 if ((align_start = (offset32 & 3))) { 2731 offset32 &= ~3; 2732 len32 += align_start; 2733 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2734 goto bce_nvram_write_exit; 2735 } 2736 2737 if (len32 & 3) { 2738 if ((len32 > 4) || !align_start) { 2739 align_end = 4 - (len32 & 3); 2740 len32 += align_end; 2741 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2742 end, 4))) { 2743 goto bce_nvram_write_exit; 2744 } 2745 } 2746 } 2747 2748 if (align_start || align_end) { 2749 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2750 if (buf == NULL) { 2751 rc = ENOMEM; 2752 goto bce_nvram_write_exit; 2753 } 2754 2755 if (align_start) { 2756 memcpy(buf, start, 4); 2757 } 2758 2759 if (align_end) { 2760 memcpy(buf + len32 - 4, end, 4); 2761 } 2762 memcpy(buf + align_start, data_buf, buf_size); 2763 } 2764 2765 written = 0; 2766 while ((written < len32) && (rc == 0)) { 2767 u32 page_start, page_end, data_start, data_end; 2768 u32 addr, cmd_flags; 2769 int i; 2770 u8 flash_buffer[264]; 2771 2772 /* Find the page_start addr */ 2773 page_start = offset32 + written; 2774 page_start -= (page_start % sc->bce_flash_info->page_size); 2775 /* Find the page_end addr */ 2776 page_end = page_start + sc->bce_flash_info->page_size; 2777 /* Find the data_start addr */ 2778 data_start = (written == 0) ? offset32 : page_start; 2779 /* Find the data_end addr */ 2780 data_end = (page_end > offset32 + len32) ? 2781 (offset32 + len32) : page_end; 2782 2783 /* Request access to the flash interface. */ 2784 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2785 goto bce_nvram_write_exit; 2786 2787 /* Enable access to flash interface */ 2788 bce_enable_nvram_access(sc); 2789 2790 cmd_flags = BCE_NVM_COMMAND_FIRST; 2791 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2792 int j; 2793 2794 /* Read the whole page into the buffer 2795 * (non-buffer flash only) */ 2796 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2797 if (j == (sc->bce_flash_info->page_size - 4)) { 2798 cmd_flags |= BCE_NVM_COMMAND_LAST; 2799 } 2800 rc = bce_nvram_read_dword(sc, 2801 page_start + j, 2802 &flash_buffer[j], 2803 cmd_flags); 2804 2805 if (rc) 2806 goto bce_nvram_write_locked_exit; 2807 2808 cmd_flags = 0; 2809 } 2810 } 2811 2812 /* Enable writes to flash interface (unlock write-protect) */ 2813 if ((rc = bce_enable_nvram_write(sc)) != 0) 2814 goto bce_nvram_write_locked_exit; 2815 2816 /* Erase the page */ 2817 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2818 goto bce_nvram_write_locked_exit; 2819 2820 /* Re-enable the write again for the actual write */ 2821 bce_enable_nvram_write(sc); 2822 2823 /* Loop to write back the buffer data from page_start to 2824 * data_start */ 2825 i = 0; 2826 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2827 for (addr = page_start; addr < data_start; 2828 addr += 4, i += 4) { 2829 rc = bce_nvram_write_dword(sc, addr, 2830 &flash_buffer[i], cmd_flags); 2831 2832 if (rc != 0) 2833 goto bce_nvram_write_locked_exit; 2834 2835 cmd_flags = 0; 2836 } 2837 } 2838 2839 /* Loop to write the new data from data_start to data_end */ 2840 for (addr = data_start; addr < data_end; addr += 4, i++) { 2841 if ((addr == page_end - 4) || 2842 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2843 (addr == data_end - 4))) { 2844 cmd_flags |= BCE_NVM_COMMAND_LAST; 2845 } 2846 rc = bce_nvram_write_dword(sc, addr, buf, 2847 cmd_flags); 2848 2849 if (rc != 0) 2850 goto bce_nvram_write_locked_exit; 2851 2852 cmd_flags = 0; 2853 buf += 4; 2854 } 2855 2856 /* Loop to write back the buffer data from data_end 2857 * to page_end */ 2858 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2859 for (addr = data_end; addr < page_end; 2860 addr += 4, i += 4) { 2861 if (addr == page_end-4) { 2862 cmd_flags = BCE_NVM_COMMAND_LAST; 2863 } 2864 rc = bce_nvram_write_dword(sc, addr, 2865 &flash_buffer[i], cmd_flags); 2866 2867 if (rc != 0) 2868 goto bce_nvram_write_locked_exit; 2869 2870 cmd_flags = 0; 2871 } 2872 } 2873 2874 /* Disable writes to flash interface (lock write-protect) */ 2875 bce_disable_nvram_write(sc); 2876 2877 /* Disable access to flash interface */ 2878 bce_disable_nvram_access(sc); 2879 bce_release_nvram_lock(sc); 2880 2881 /* Increment written */ 2882 written += data_end - data_start; 2883 } 2884 2885 goto bce_nvram_write_exit; 2886 2887 bce_nvram_write_locked_exit: 2888 bce_disable_nvram_write(sc); 2889 bce_disable_nvram_access(sc); 2890 bce_release_nvram_lock(sc); 2891 2892 bce_nvram_write_exit: 2893 if (align_start || align_end) 2894 free(buf, M_DEVBUF); 2895 2896 DBEXIT(BCE_VERBOSE_NVRAM); 2897 return (rc); 2898 } 2899 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2900 2901 /****************************************************************************/ 2902 /* Verifies that NVRAM is accessible and contains valid data. */ 2903 /* */ 2904 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2905 /* correct. */ 2906 /* */ 2907 /* Returns: */ 2908 /* 0 on success, positive value on failure. */ 2909 /****************************************************************************/ 2910 static int 2911 bce_nvram_test(struct bce_softc *sc) 2912 { 2913 u32 buf[BCE_NVRAM_SIZE / 4]; 2914 u8 *data = (u8 *) buf; 2915 int rc = 0; 2916 u32 magic, csum; 2917 2918 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2919 2920 /* 2921 * Check that the device NVRAM is valid by reading 2922 * the magic value at offset 0. 2923 */ 2924 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2925 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2926 __FILE__, __LINE__); 2927 goto bce_nvram_test_exit; 2928 } 2929 2930 /* 2931 * Verify that offset 0 of the NVRAM contains 2932 * a valid magic number. 2933 */ 2934 magic = bce_be32toh(buf[0]); 2935 if (magic != BCE_NVRAM_MAGIC) { 2936 rc = ENODEV; 2937 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2938 "Expected: 0x%08X, Found: 0x%08X\n", 2939 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2940 goto bce_nvram_test_exit; 2941 } 2942 2943 /* 2944 * Verify that the device NVRAM includes valid 2945 * configuration data. 2946 */ 2947 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2948 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2949 "Information from NVRAM!\n", __FILE__, __LINE__); 2950 goto bce_nvram_test_exit; 2951 } 2952 2953 csum = ether_crc32_le(data, 0x100); 2954 if (csum != BCE_CRC32_RESIDUAL) { 2955 rc = ENODEV; 2956 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2957 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2958 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2959 goto bce_nvram_test_exit; 2960 } 2961 2962 csum = ether_crc32_le(data + 0x100, 0x100); 2963 if (csum != BCE_CRC32_RESIDUAL) { 2964 rc = ENODEV; 2965 BCE_PRINTF("%s(%d): Invalid feature configuration " 2966 "information NVRAM CRC! Expected: 0x%08X, " 2967 "Found: 08%08X\n", __FILE__, __LINE__, 2968 BCE_CRC32_RESIDUAL, csum); 2969 } 2970 2971 bce_nvram_test_exit: 2972 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2973 return rc; 2974 } 2975 2976 /****************************************************************************/ 2977 /* Calculates the size of the buffers to allocate based on the MTU. */ 2978 /* */ 2979 /* Returns: */ 2980 /* Nothing. */ 2981 /****************************************************************************/ 2982 static void 2983 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 2984 { 2985 DBENTER(BCE_VERBOSE_LOAD); 2986 2987 /* Use a single allocation type when header splitting enabled. */ 2988 if (bce_hdr_split == TRUE) { 2989 sc->rx_bd_mbuf_alloc_size = MHLEN; 2990 /* Make sure offset is 16 byte aligned for hardware. */ 2991 sc->rx_bd_mbuf_align_pad = 2992 roundup2(MSIZE - MHLEN, 16) - (MSIZE - MHLEN); 2993 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 2994 sc->rx_bd_mbuf_align_pad; 2995 } else { 2996 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2997 ETHER_CRC_LEN) > MCLBYTES) { 2998 /* Setup for jumbo RX buffer allocations. */ 2999 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 3000 sc->rx_bd_mbuf_align_pad = 3001 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 3002 sc->rx_bd_mbuf_data_len = 3003 sc->rx_bd_mbuf_alloc_size - 3004 sc->rx_bd_mbuf_align_pad; 3005 } else { 3006 /* Setup for standard RX buffer allocations. */ 3007 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3008 sc->rx_bd_mbuf_align_pad = 3009 roundup2(MCLBYTES, 16) - MCLBYTES; 3010 sc->rx_bd_mbuf_data_len = 3011 sc->rx_bd_mbuf_alloc_size - 3012 sc->rx_bd_mbuf_align_pad; 3013 } 3014 } 3015 3016 // DBPRINT(sc, BCE_INFO_LOAD, 3017 DBPRINT(sc, BCE_WARN, 3018 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3019 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3020 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3021 sc->rx_bd_mbuf_align_pad); 3022 3023 DBEXIT(BCE_VERBOSE_LOAD); 3024 } 3025 3026 /****************************************************************************/ 3027 /* Identifies the current media type of the controller and sets the PHY */ 3028 /* address. */ 3029 /* */ 3030 /* Returns: */ 3031 /* Nothing. */ 3032 /****************************************************************************/ 3033 static void 3034 bce_get_media(struct bce_softc *sc) 3035 { 3036 u32 val; 3037 3038 DBENTER(BCE_VERBOSE_PHY); 3039 3040 /* Assume PHY address for copper controllers. */ 3041 sc->bce_phy_addr = 1; 3042 3043 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3044 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3045 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3046 u32 strap; 3047 3048 /* 3049 * The BCM5709S is software configurable 3050 * for Copper or SerDes operation. 3051 */ 3052 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3053 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3054 "for copper.\n"); 3055 goto bce_get_media_exit; 3056 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3057 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3058 "for dual media.\n"); 3059 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3060 goto bce_get_media_exit; 3061 } 3062 3063 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3064 strap = (val & 3065 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3066 else 3067 strap = (val & 3068 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3069 3070 if (pci_get_function(sc->bce_dev) == 0) { 3071 switch (strap) { 3072 case 0x4: 3073 case 0x5: 3074 case 0x6: 3075 DBPRINT(sc, BCE_INFO_LOAD, 3076 "BCM5709 s/w configured for SerDes.\n"); 3077 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3078 break; 3079 default: 3080 DBPRINT(sc, BCE_INFO_LOAD, 3081 "BCM5709 s/w configured for Copper.\n"); 3082 break; 3083 } 3084 } else { 3085 switch (strap) { 3086 case 0x1: 3087 case 0x2: 3088 case 0x4: 3089 DBPRINT(sc, BCE_INFO_LOAD, 3090 "BCM5709 s/w configured for SerDes.\n"); 3091 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3092 break; 3093 default: 3094 DBPRINT(sc, BCE_INFO_LOAD, 3095 "BCM5709 s/w configured for Copper.\n"); 3096 break; 3097 } 3098 } 3099 3100 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3101 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3102 3103 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3104 sc->bce_flags |= BCE_NO_WOL_FLAG; 3105 3106 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3107 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3108 3109 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3110 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3111 sc->bce_phy_addr = 2; 3112 3113 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3114 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3115 sc->bce_phy_flags |= 3116 BCE_PHY_2_5G_CAPABLE_FLAG; 3117 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3118 "capable adapter\n"); 3119 } 3120 } 3121 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3122 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3123 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3124 3125 bce_get_media_exit: 3126 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3127 "Using PHY address %d.\n", sc->bce_phy_addr); 3128 3129 DBEXIT(BCE_VERBOSE_PHY); 3130 } 3131 3132 /****************************************************************************/ 3133 /* Performs PHY initialization required before MII drivers access the */ 3134 /* device. */ 3135 /* */ 3136 /* Returns: */ 3137 /* Nothing. */ 3138 /****************************************************************************/ 3139 static void 3140 bce_init_media(struct bce_softc *sc) 3141 { 3142 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG | 3143 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) { 3144 /* 3145 * Configure 5709S/5716S PHYs to use traditional IEEE 3146 * Clause 22 method. Otherwise we have no way to attach 3147 * the PHY in mii(4) layer. PHY specific configuration 3148 * is done in mii layer. 3149 */ 3150 3151 /* Select auto-negotiation MMD of the PHY. */ 3152 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3153 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3154 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3155 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3156 3157 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3158 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3159 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3160 } 3161 } 3162 3163 /****************************************************************************/ 3164 /* Free any DMA memory owned by the driver. */ 3165 /* */ 3166 /* Scans through each data structure that requires DMA memory and frees */ 3167 /* the memory if allocated. */ 3168 /* */ 3169 /* Returns: */ 3170 /* Nothing. */ 3171 /****************************************************************************/ 3172 static void 3173 bce_dma_free(struct bce_softc *sc) 3174 { 3175 int i; 3176 3177 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3178 3179 /* Free, unmap, and destroy the status block. */ 3180 if (sc->status_block_paddr != 0) { 3181 bus_dmamap_unload( 3182 sc->status_tag, 3183 sc->status_map); 3184 sc->status_block_paddr = 0; 3185 } 3186 3187 if (sc->status_block != NULL) { 3188 bus_dmamem_free( 3189 sc->status_tag, 3190 sc->status_block, 3191 sc->status_map); 3192 sc->status_block = NULL; 3193 } 3194 3195 if (sc->status_tag != NULL) { 3196 bus_dma_tag_destroy(sc->status_tag); 3197 sc->status_tag = NULL; 3198 } 3199 3200 /* Free, unmap, and destroy the statistics block. */ 3201 if (sc->stats_block_paddr != 0) { 3202 bus_dmamap_unload( 3203 sc->stats_tag, 3204 sc->stats_map); 3205 sc->stats_block_paddr = 0; 3206 } 3207 3208 if (sc->stats_block != NULL) { 3209 bus_dmamem_free( 3210 sc->stats_tag, 3211 sc->stats_block, 3212 sc->stats_map); 3213 sc->stats_block = NULL; 3214 } 3215 3216 if (sc->stats_tag != NULL) { 3217 bus_dma_tag_destroy(sc->stats_tag); 3218 sc->stats_tag = NULL; 3219 } 3220 3221 /* Free, unmap and destroy all context memory pages. */ 3222 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3223 for (i = 0; i < sc->ctx_pages; i++ ) { 3224 if (sc->ctx_paddr[i] != 0) { 3225 bus_dmamap_unload( 3226 sc->ctx_tag, 3227 sc->ctx_map[i]); 3228 sc->ctx_paddr[i] = 0; 3229 } 3230 3231 if (sc->ctx_block[i] != NULL) { 3232 bus_dmamem_free( 3233 sc->ctx_tag, 3234 sc->ctx_block[i], 3235 sc->ctx_map[i]); 3236 sc->ctx_block[i] = NULL; 3237 } 3238 } 3239 3240 /* Destroy the context memory tag. */ 3241 if (sc->ctx_tag != NULL) { 3242 bus_dma_tag_destroy(sc->ctx_tag); 3243 sc->ctx_tag = NULL; 3244 } 3245 } 3246 3247 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3248 for (i = 0; i < sc->tx_pages; i++ ) { 3249 if (sc->tx_bd_chain_paddr[i] != 0) { 3250 bus_dmamap_unload( 3251 sc->tx_bd_chain_tag, 3252 sc->tx_bd_chain_map[i]); 3253 sc->tx_bd_chain_paddr[i] = 0; 3254 } 3255 3256 if (sc->tx_bd_chain[i] != NULL) { 3257 bus_dmamem_free( 3258 sc->tx_bd_chain_tag, 3259 sc->tx_bd_chain[i], 3260 sc->tx_bd_chain_map[i]); 3261 sc->tx_bd_chain[i] = NULL; 3262 } 3263 } 3264 3265 /* Destroy the TX buffer descriptor tag. */ 3266 if (sc->tx_bd_chain_tag != NULL) { 3267 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3268 sc->tx_bd_chain_tag = NULL; 3269 } 3270 3271 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3272 for (i = 0; i < sc->rx_pages; i++ ) { 3273 if (sc->rx_bd_chain_paddr[i] != 0) { 3274 bus_dmamap_unload( 3275 sc->rx_bd_chain_tag, 3276 sc->rx_bd_chain_map[i]); 3277 sc->rx_bd_chain_paddr[i] = 0; 3278 } 3279 3280 if (sc->rx_bd_chain[i] != NULL) { 3281 bus_dmamem_free( 3282 sc->rx_bd_chain_tag, 3283 sc->rx_bd_chain[i], 3284 sc->rx_bd_chain_map[i]); 3285 sc->rx_bd_chain[i] = NULL; 3286 } 3287 } 3288 3289 /* Destroy the RX buffer descriptor tag. */ 3290 if (sc->rx_bd_chain_tag != NULL) { 3291 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3292 sc->rx_bd_chain_tag = NULL; 3293 } 3294 3295 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3296 if (bce_hdr_split == TRUE) { 3297 for (i = 0; i < sc->pg_pages; i++ ) { 3298 if (sc->pg_bd_chain_paddr[i] != 0) { 3299 bus_dmamap_unload( 3300 sc->pg_bd_chain_tag, 3301 sc->pg_bd_chain_map[i]); 3302 sc->pg_bd_chain_paddr[i] = 0; 3303 } 3304 3305 if (sc->pg_bd_chain[i] != NULL) { 3306 bus_dmamem_free( 3307 sc->pg_bd_chain_tag, 3308 sc->pg_bd_chain[i], 3309 sc->pg_bd_chain_map[i]); 3310 sc->pg_bd_chain[i] = NULL; 3311 } 3312 } 3313 3314 /* Destroy the page buffer descriptor tag. */ 3315 if (sc->pg_bd_chain_tag != NULL) { 3316 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3317 sc->pg_bd_chain_tag = NULL; 3318 } 3319 } 3320 3321 /* Unload and destroy the TX mbuf maps. */ 3322 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3323 if (sc->tx_mbuf_map[i] != NULL) { 3324 bus_dmamap_unload(sc->tx_mbuf_tag, 3325 sc->tx_mbuf_map[i]); 3326 bus_dmamap_destroy(sc->tx_mbuf_tag, 3327 sc->tx_mbuf_map[i]); 3328 sc->tx_mbuf_map[i] = NULL; 3329 } 3330 } 3331 3332 /* Destroy the TX mbuf tag. */ 3333 if (sc->tx_mbuf_tag != NULL) { 3334 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3335 sc->tx_mbuf_tag = NULL; 3336 } 3337 3338 /* Unload and destroy the RX mbuf maps. */ 3339 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3340 if (sc->rx_mbuf_map[i] != NULL) { 3341 bus_dmamap_unload(sc->rx_mbuf_tag, 3342 sc->rx_mbuf_map[i]); 3343 bus_dmamap_destroy(sc->rx_mbuf_tag, 3344 sc->rx_mbuf_map[i]); 3345 sc->rx_mbuf_map[i] = NULL; 3346 } 3347 } 3348 3349 /* Destroy the RX mbuf tag. */ 3350 if (sc->rx_mbuf_tag != NULL) { 3351 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3352 sc->rx_mbuf_tag = NULL; 3353 } 3354 3355 /* Unload and destroy the page mbuf maps. */ 3356 if (bce_hdr_split == TRUE) { 3357 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3358 if (sc->pg_mbuf_map[i] != NULL) { 3359 bus_dmamap_unload(sc->pg_mbuf_tag, 3360 sc->pg_mbuf_map[i]); 3361 bus_dmamap_destroy(sc->pg_mbuf_tag, 3362 sc->pg_mbuf_map[i]); 3363 sc->pg_mbuf_map[i] = NULL; 3364 } 3365 } 3366 3367 /* Destroy the page mbuf tag. */ 3368 if (sc->pg_mbuf_tag != NULL) { 3369 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3370 sc->pg_mbuf_tag = NULL; 3371 } 3372 } 3373 3374 /* Destroy the parent tag */ 3375 if (sc->parent_tag != NULL) { 3376 bus_dma_tag_destroy(sc->parent_tag); 3377 sc->parent_tag = NULL; 3378 } 3379 3380 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3381 } 3382 3383 /****************************************************************************/ 3384 /* Get DMA memory from the OS. */ 3385 /* */ 3386 /* Validates that the OS has provided DMA buffers in response to a */ 3387 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3388 /* When the callback is used the OS will return 0 for the mapping function */ 3389 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3390 /* failures back to the caller. */ 3391 /* */ 3392 /* Returns: */ 3393 /* Nothing. */ 3394 /****************************************************************************/ 3395 static void 3396 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3397 { 3398 bus_addr_t *busaddr = arg; 3399 3400 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3401 __FUNCTION__, nseg)); 3402 /* Simulate a mapping failure. */ 3403 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3404 error = ENOMEM); 3405 3406 /* ToDo: How to increment debug sim_count variable here? */ 3407 3408 /* Check for an error and signal the caller that an error occurred. */ 3409 if (error) { 3410 *busaddr = 0; 3411 } else { 3412 *busaddr = segs->ds_addr; 3413 } 3414 } 3415 3416 /****************************************************************************/ 3417 /* Allocate any DMA memory needed by the driver. */ 3418 /* */ 3419 /* Allocates DMA memory needed for the various global structures needed by */ 3420 /* hardware. */ 3421 /* */ 3422 /* Memory alignment requirements: */ 3423 /* +-----------------+----------+----------+----------+----------+ */ 3424 /* | | 5706 | 5708 | 5709 | 5716 | */ 3425 /* +-----------------+----------+----------+----------+----------+ */ 3426 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3427 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3428 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3429 /* |PG Buffers | none | none | none | none | */ 3430 /* |TX Buffers | none | none | none | none | */ 3431 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3432 /* |Context Memory | | | | | */ 3433 /* +-----------------+----------+----------+----------+----------+ */ 3434 /* */ 3435 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3436 /* */ 3437 /* Returns: */ 3438 /* 0 for success, positive value for failure. */ 3439 /****************************************************************************/ 3440 static int 3441 bce_dma_alloc(device_t dev) 3442 { 3443 struct bce_softc *sc; 3444 int i, error, rc = 0; 3445 bus_size_t max_size, max_seg_size; 3446 int max_segments; 3447 3448 sc = device_get_softc(dev); 3449 3450 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3451 3452 /* 3453 * Allocate the parent bus DMA tag appropriate for PCI. 3454 */ 3455 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3456 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3457 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3458 &sc->parent_tag)) { 3459 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3460 __FILE__, __LINE__); 3461 rc = ENOMEM; 3462 goto bce_dma_alloc_exit; 3463 } 3464 3465 /* 3466 * Create a DMA tag for the status block, allocate and clear the 3467 * memory, map the memory into DMA space, and fetch the physical 3468 * address of the block. 3469 */ 3470 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3471 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3472 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3473 0, NULL, NULL, &sc->status_tag)) { 3474 BCE_PRINTF("%s(%d): Could not allocate status block " 3475 "DMA tag!\n", __FILE__, __LINE__); 3476 rc = ENOMEM; 3477 goto bce_dma_alloc_exit; 3478 } 3479 3480 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3481 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3482 &sc->status_map)) { 3483 BCE_PRINTF("%s(%d): Could not allocate status block " 3484 "DMA memory!\n", __FILE__, __LINE__); 3485 rc = ENOMEM; 3486 goto bce_dma_alloc_exit; 3487 } 3488 3489 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3490 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3491 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3492 3493 if (error || sc->status_block_paddr == 0) { 3494 BCE_PRINTF("%s(%d): Could not map status block " 3495 "DMA memory!\n", __FILE__, __LINE__); 3496 rc = ENOMEM; 3497 goto bce_dma_alloc_exit; 3498 } 3499 3500 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3501 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3502 3503 /* 3504 * Create a DMA tag for the statistics block, allocate and clear the 3505 * memory, map the memory into DMA space, and fetch the physical 3506 * address of the block. 3507 */ 3508 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3509 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3510 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3511 0, NULL, NULL, &sc->stats_tag)) { 3512 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3513 "DMA tag!\n", __FILE__, __LINE__); 3514 rc = ENOMEM; 3515 goto bce_dma_alloc_exit; 3516 } 3517 3518 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3519 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3520 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3521 "DMA memory!\n", __FILE__, __LINE__); 3522 rc = ENOMEM; 3523 goto bce_dma_alloc_exit; 3524 } 3525 3526 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3527 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3528 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3529 3530 if (error || sc->stats_block_paddr == 0) { 3531 BCE_PRINTF("%s(%d): Could not map statistics block " 3532 "DMA memory!\n", __FILE__, __LINE__); 3533 rc = ENOMEM; 3534 goto bce_dma_alloc_exit; 3535 } 3536 3537 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3538 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3539 3540 /* BCM5709 uses host memory as cache for context memory. */ 3541 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3542 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3543 if (sc->ctx_pages == 0) 3544 sc->ctx_pages = 1; 3545 3546 DBRUNIF((sc->ctx_pages > 512), 3547 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3548 __FILE__, __LINE__, sc->ctx_pages)); 3549 3550 /* 3551 * Create a DMA tag for the context pages, 3552 * allocate and clear the memory, map the 3553 * memory into DMA space, and fetch the 3554 * physical address of the block. 3555 */ 3556 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3557 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3558 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3559 0, NULL, NULL, &sc->ctx_tag)) { 3560 BCE_PRINTF("%s(%d): Could not allocate CTX " 3561 "DMA tag!\n", __FILE__, __LINE__); 3562 rc = ENOMEM; 3563 goto bce_dma_alloc_exit; 3564 } 3565 3566 for (i = 0; i < sc->ctx_pages; i++) { 3567 if(bus_dmamem_alloc(sc->ctx_tag, 3568 (void **)&sc->ctx_block[i], 3569 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3570 &sc->ctx_map[i])) { 3571 BCE_PRINTF("%s(%d): Could not allocate CTX " 3572 "DMA memory!\n", __FILE__, __LINE__); 3573 rc = ENOMEM; 3574 goto bce_dma_alloc_exit; 3575 } 3576 3577 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3578 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3579 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3580 3581 if (error || sc->ctx_paddr[i] == 0) { 3582 BCE_PRINTF("%s(%d): Could not map CTX " 3583 "DMA memory!\n", __FILE__, __LINE__); 3584 rc = ENOMEM; 3585 goto bce_dma_alloc_exit; 3586 } 3587 3588 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3589 "= 0x%jX\n", __FUNCTION__, i, 3590 (uintmax_t) sc->ctx_paddr[i]); 3591 } 3592 } 3593 3594 /* 3595 * Create a DMA tag for the TX buffer descriptor chain, 3596 * allocate and clear the memory, and fetch the 3597 * physical address of the block. 3598 */ 3599 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3600 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3601 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3602 NULL, NULL, &sc->tx_bd_chain_tag)) { 3603 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3604 "chain DMA tag!\n", __FILE__, __LINE__); 3605 rc = ENOMEM; 3606 goto bce_dma_alloc_exit; 3607 } 3608 3609 for (i = 0; i < sc->tx_pages; i++) { 3610 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3611 (void **)&sc->tx_bd_chain[i], 3612 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3613 &sc->tx_bd_chain_map[i])) { 3614 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3615 "chain DMA memory!\n", __FILE__, __LINE__); 3616 rc = ENOMEM; 3617 goto bce_dma_alloc_exit; 3618 } 3619 3620 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3621 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3622 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3623 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3624 3625 if (error || sc->tx_bd_chain_paddr[i] == 0) { 3626 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3627 "chain DMA memory!\n", __FILE__, __LINE__); 3628 rc = ENOMEM; 3629 goto bce_dma_alloc_exit; 3630 } 3631 3632 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3633 "0x%jX\n", __FUNCTION__, i, 3634 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3635 } 3636 3637 /* Check the required size before mapping to conserve resources. */ 3638 if (bce_tso_enable) { 3639 max_size = BCE_TSO_MAX_SIZE; 3640 max_segments = BCE_MAX_SEGMENTS; 3641 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3642 } else { 3643 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3644 max_segments = BCE_MAX_SEGMENTS; 3645 max_seg_size = MCLBYTES; 3646 } 3647 3648 /* Create a DMA tag for TX mbufs. */ 3649 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3650 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3651 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3652 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3653 __FILE__, __LINE__); 3654 rc = ENOMEM; 3655 goto bce_dma_alloc_exit; 3656 } 3657 3658 /* Create DMA maps for the TX mbufs clusters. */ 3659 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3660 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3661 &sc->tx_mbuf_map[i])) { 3662 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3663 "map!\n", __FILE__, __LINE__); 3664 rc = ENOMEM; 3665 goto bce_dma_alloc_exit; 3666 } 3667 } 3668 3669 /* 3670 * Create a DMA tag for the RX buffer descriptor chain, 3671 * allocate and clear the memory, and fetch the physical 3672 * address of the blocks. 3673 */ 3674 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3675 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3676 sc->max_bus_addr, NULL, NULL, 3677 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3678 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3679 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3680 "DMA tag!\n", __FILE__, __LINE__); 3681 rc = ENOMEM; 3682 goto bce_dma_alloc_exit; 3683 } 3684 3685 for (i = 0; i < sc->rx_pages; i++) { 3686 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3687 (void **)&sc->rx_bd_chain[i], 3688 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3689 &sc->rx_bd_chain_map[i])) { 3690 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3691 "chain DMA memory!\n", __FILE__, __LINE__); 3692 rc = ENOMEM; 3693 goto bce_dma_alloc_exit; 3694 } 3695 3696 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3697 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3698 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3699 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3700 3701 if (error || sc->rx_bd_chain_paddr[i] == 0) { 3702 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3703 "chain DMA memory!\n", __FILE__, __LINE__); 3704 rc = ENOMEM; 3705 goto bce_dma_alloc_exit; 3706 } 3707 3708 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3709 "0x%jX\n", __FUNCTION__, i, 3710 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3711 } 3712 3713 /* 3714 * Create a DMA tag for RX mbufs. 3715 */ 3716 if (bce_hdr_split == TRUE) 3717 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3718 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3719 else 3720 max_size = MJUM9BYTES; 3721 3722 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3723 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size); 3724 3725 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3726 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3727 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) { 3728 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3729 __FILE__, __LINE__); 3730 rc = ENOMEM; 3731 goto bce_dma_alloc_exit; 3732 } 3733 3734 /* Create DMA maps for the RX mbuf clusters. */ 3735 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3736 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3737 &sc->rx_mbuf_map[i])) { 3738 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3739 "DMA map!\n", __FILE__, __LINE__); 3740 rc = ENOMEM; 3741 goto bce_dma_alloc_exit; 3742 } 3743 } 3744 3745 if (bce_hdr_split == TRUE) { 3746 /* 3747 * Create a DMA tag for the page buffer descriptor chain, 3748 * allocate and clear the memory, and fetch the physical 3749 * address of the blocks. 3750 */ 3751 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3752 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3753 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3754 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3755 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3756 "chain DMA tag!\n", __FILE__, __LINE__); 3757 rc = ENOMEM; 3758 goto bce_dma_alloc_exit; 3759 } 3760 3761 for (i = 0; i < sc->pg_pages; i++) { 3762 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3763 (void **)&sc->pg_bd_chain[i], 3764 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3765 &sc->pg_bd_chain_map[i])) { 3766 BCE_PRINTF("%s(%d): Could not allocate page " 3767 "descriptor chain DMA memory!\n", 3768 __FILE__, __LINE__); 3769 rc = ENOMEM; 3770 goto bce_dma_alloc_exit; 3771 } 3772 3773 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3774 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3775 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3776 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3777 3778 if (error || sc->pg_bd_chain_paddr[i] == 0) { 3779 BCE_PRINTF("%s(%d): Could not map page descriptor " 3780 "chain DMA memory!\n", __FILE__, __LINE__); 3781 rc = ENOMEM; 3782 goto bce_dma_alloc_exit; 3783 } 3784 3785 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3786 "0x%jX\n", __FUNCTION__, i, 3787 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3788 } 3789 3790 /* 3791 * Create a DMA tag for page mbufs. 3792 */ 3793 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3794 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 3795 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3796 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3797 "DMA tag!\n", __FILE__, __LINE__); 3798 rc = ENOMEM; 3799 goto bce_dma_alloc_exit; 3800 } 3801 3802 /* Create DMA maps for the page mbuf clusters. */ 3803 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3804 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3805 &sc->pg_mbuf_map[i])) { 3806 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3807 "DMA map!\n", __FILE__, __LINE__); 3808 rc = ENOMEM; 3809 goto bce_dma_alloc_exit; 3810 } 3811 } 3812 } 3813 3814 bce_dma_alloc_exit: 3815 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3816 return(rc); 3817 } 3818 3819 /****************************************************************************/ 3820 /* Release all resources used by the driver. */ 3821 /* */ 3822 /* Releases all resources acquired by the driver including interrupts, */ 3823 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3824 /* */ 3825 /* Returns: */ 3826 /* Nothing. */ 3827 /****************************************************************************/ 3828 static void 3829 bce_release_resources(struct bce_softc *sc) 3830 { 3831 device_t dev; 3832 3833 DBENTER(BCE_VERBOSE_RESET); 3834 3835 dev = sc->bce_dev; 3836 3837 bce_dma_free(sc); 3838 3839 if (sc->bce_intrhand != NULL) { 3840 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3841 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3842 } 3843 3844 if (sc->bce_res_irq != NULL) { 3845 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3846 bus_release_resource(dev, SYS_RES_IRQ, 3847 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq); 3848 } 3849 3850 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3851 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3852 pci_release_msi(dev); 3853 } 3854 3855 if (sc->bce_res_mem != NULL) { 3856 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3857 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3858 sc->bce_res_mem); 3859 } 3860 3861 if (sc->bce_ifp != NULL) { 3862 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3863 if_free(sc->bce_ifp); 3864 } 3865 3866 if (mtx_initialized(&sc->bce_mtx)) 3867 BCE_LOCK_DESTROY(sc); 3868 3869 DBEXIT(BCE_VERBOSE_RESET); 3870 } 3871 3872 /****************************************************************************/ 3873 /* Firmware synchronization. */ 3874 /* */ 3875 /* Before performing certain events such as a chip reset, synchronize with */ 3876 /* the firmware first. */ 3877 /* */ 3878 /* Returns: */ 3879 /* 0 for success, positive value for failure. */ 3880 /****************************************************************************/ 3881 static int 3882 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3883 { 3884 int i, rc = 0; 3885 u32 val; 3886 3887 DBENTER(BCE_VERBOSE_RESET); 3888 3889 /* Don't waste any time if we've timed out before. */ 3890 if (sc->bce_fw_timed_out == TRUE) { 3891 rc = EBUSY; 3892 goto bce_fw_sync_exit; 3893 } 3894 3895 /* Increment the message sequence number. */ 3896 sc->bce_fw_wr_seq++; 3897 msg_data |= sc->bce_fw_wr_seq; 3898 3899 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3900 "0x%08X\n", msg_data); 3901 3902 /* Send the message to the bootcode driver mailbox. */ 3903 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3904 3905 /* Wait for the bootcode to acknowledge the message. */ 3906 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3907 /* Check for a response in the bootcode firmware mailbox. */ 3908 val = bce_shmem_rd(sc, BCE_FW_MB); 3909 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3910 break; 3911 DELAY(1000); 3912 } 3913 3914 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3915 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3916 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3917 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3918 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3919 3920 msg_data &= ~BCE_DRV_MSG_CODE; 3921 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3922 3923 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3924 3925 sc->bce_fw_timed_out = TRUE; 3926 rc = EBUSY; 3927 } 3928 3929 bce_fw_sync_exit: 3930 DBEXIT(BCE_VERBOSE_RESET); 3931 return (rc); 3932 } 3933 3934 /****************************************************************************/ 3935 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3936 /* */ 3937 /* Returns: */ 3938 /* Nothing. */ 3939 /****************************************************************************/ 3940 static void 3941 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code, 3942 u32 rv2p_code_len, u32 rv2p_proc) 3943 { 3944 int i; 3945 u32 val; 3946 3947 DBENTER(BCE_VERBOSE_RESET); 3948 3949 /* Set the page size used by RV2P. */ 3950 if (rv2p_proc == RV2P_PROC2) { 3951 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3952 } 3953 3954 for (i = 0; i < rv2p_code_len; i += 8) { 3955 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3956 rv2p_code++; 3957 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3958 rv2p_code++; 3959 3960 if (rv2p_proc == RV2P_PROC1) { 3961 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 3962 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 3963 } 3964 else { 3965 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 3966 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 3967 } 3968 } 3969 3970 /* Reset the processor, un-stall is done later. */ 3971 if (rv2p_proc == RV2P_PROC1) { 3972 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 3973 } 3974 else { 3975 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 3976 } 3977 3978 DBEXIT(BCE_VERBOSE_RESET); 3979 } 3980 3981 /****************************************************************************/ 3982 /* Load RISC processor firmware. */ 3983 /* */ 3984 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 3985 /* associated with a particular processor. */ 3986 /* */ 3987 /* Returns: */ 3988 /* Nothing. */ 3989 /****************************************************************************/ 3990 static void 3991 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 3992 struct fw_info *fw) 3993 { 3994 u32 offset; 3995 3996 DBENTER(BCE_VERBOSE_RESET); 3997 3998 bce_halt_cpu(sc, cpu_reg); 3999 4000 /* Load the Text area. */ 4001 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4002 if (fw->text) { 4003 int j; 4004 4005 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4006 REG_WR_IND(sc, offset, fw->text[j]); 4007 } 4008 } 4009 4010 /* Load the Data area. */ 4011 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4012 if (fw->data) { 4013 int j; 4014 4015 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4016 REG_WR_IND(sc, offset, fw->data[j]); 4017 } 4018 } 4019 4020 /* Load the SBSS area. */ 4021 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4022 if (fw->sbss) { 4023 int j; 4024 4025 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4026 REG_WR_IND(sc, offset, fw->sbss[j]); 4027 } 4028 } 4029 4030 /* Load the BSS area. */ 4031 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4032 if (fw->bss) { 4033 int j; 4034 4035 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4036 REG_WR_IND(sc, offset, fw->bss[j]); 4037 } 4038 } 4039 4040 /* Load the Read-Only area. */ 4041 offset = cpu_reg->spad_base + 4042 (fw->rodata_addr - cpu_reg->mips_view_base); 4043 if (fw->rodata) { 4044 int j; 4045 4046 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4047 REG_WR_IND(sc, offset, fw->rodata[j]); 4048 } 4049 } 4050 4051 /* Clear the pre-fetch instruction and set the FW start address. */ 4052 REG_WR_IND(sc, cpu_reg->inst, 0); 4053 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4054 4055 DBEXIT(BCE_VERBOSE_RESET); 4056 } 4057 4058 /****************************************************************************/ 4059 /* Starts the RISC processor. */ 4060 /* */ 4061 /* Assumes the CPU starting address has already been set. */ 4062 /* */ 4063 /* Returns: */ 4064 /* Nothing. */ 4065 /****************************************************************************/ 4066 static void 4067 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4068 { 4069 u32 val; 4070 4071 DBENTER(BCE_VERBOSE_RESET); 4072 4073 /* Start the CPU. */ 4074 val = REG_RD_IND(sc, cpu_reg->mode); 4075 val &= ~cpu_reg->mode_value_halt; 4076 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4077 REG_WR_IND(sc, cpu_reg->mode, val); 4078 4079 DBEXIT(BCE_VERBOSE_RESET); 4080 } 4081 4082 /****************************************************************************/ 4083 /* Halts the RISC processor. */ 4084 /* */ 4085 /* Returns: */ 4086 /* Nothing. */ 4087 /****************************************************************************/ 4088 static void 4089 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4090 { 4091 u32 val; 4092 4093 DBENTER(BCE_VERBOSE_RESET); 4094 4095 /* Halt the CPU. */ 4096 val = REG_RD_IND(sc, cpu_reg->mode); 4097 val |= cpu_reg->mode_value_halt; 4098 REG_WR_IND(sc, cpu_reg->mode, val); 4099 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4100 4101 DBEXIT(BCE_VERBOSE_RESET); 4102 } 4103 4104 /****************************************************************************/ 4105 /* Initialize the RX CPU. */ 4106 /* */ 4107 /* Returns: */ 4108 /* Nothing. */ 4109 /****************************************************************************/ 4110 static void 4111 bce_start_rxp_cpu(struct bce_softc *sc) 4112 { 4113 struct cpu_reg cpu_reg; 4114 4115 DBENTER(BCE_VERBOSE_RESET); 4116 4117 cpu_reg.mode = BCE_RXP_CPU_MODE; 4118 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4119 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4120 cpu_reg.state = BCE_RXP_CPU_STATE; 4121 cpu_reg.state_value_clear = 0xffffff; 4122 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4123 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4124 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4125 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4126 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4127 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4128 cpu_reg.mips_view_base = 0x8000000; 4129 4130 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4131 bce_start_cpu(sc, &cpu_reg); 4132 4133 DBEXIT(BCE_VERBOSE_RESET); 4134 } 4135 4136 /****************************************************************************/ 4137 /* Initialize the RX CPU. */ 4138 /* */ 4139 /* Returns: */ 4140 /* Nothing. */ 4141 /****************************************************************************/ 4142 static void 4143 bce_init_rxp_cpu(struct bce_softc *sc) 4144 { 4145 struct cpu_reg cpu_reg; 4146 struct fw_info fw; 4147 4148 DBENTER(BCE_VERBOSE_RESET); 4149 4150 cpu_reg.mode = BCE_RXP_CPU_MODE; 4151 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4152 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4153 cpu_reg.state = BCE_RXP_CPU_STATE; 4154 cpu_reg.state_value_clear = 0xffffff; 4155 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4156 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4157 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4158 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4159 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4160 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4161 cpu_reg.mips_view_base = 0x8000000; 4162 4163 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4164 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4165 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4166 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4167 fw.start_addr = bce_RXP_b09FwStartAddr; 4168 4169 fw.text_addr = bce_RXP_b09FwTextAddr; 4170 fw.text_len = bce_RXP_b09FwTextLen; 4171 fw.text_index = 0; 4172 fw.text = bce_RXP_b09FwText; 4173 4174 fw.data_addr = bce_RXP_b09FwDataAddr; 4175 fw.data_len = bce_RXP_b09FwDataLen; 4176 fw.data_index = 0; 4177 fw.data = bce_RXP_b09FwData; 4178 4179 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4180 fw.sbss_len = bce_RXP_b09FwSbssLen; 4181 fw.sbss_index = 0; 4182 fw.sbss = bce_RXP_b09FwSbss; 4183 4184 fw.bss_addr = bce_RXP_b09FwBssAddr; 4185 fw.bss_len = bce_RXP_b09FwBssLen; 4186 fw.bss_index = 0; 4187 fw.bss = bce_RXP_b09FwBss; 4188 4189 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4190 fw.rodata_len = bce_RXP_b09FwRodataLen; 4191 fw.rodata_index = 0; 4192 fw.rodata = bce_RXP_b09FwRodata; 4193 } else { 4194 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4195 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4196 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4197 fw.start_addr = bce_RXP_b06FwStartAddr; 4198 4199 fw.text_addr = bce_RXP_b06FwTextAddr; 4200 fw.text_len = bce_RXP_b06FwTextLen; 4201 fw.text_index = 0; 4202 fw.text = bce_RXP_b06FwText; 4203 4204 fw.data_addr = bce_RXP_b06FwDataAddr; 4205 fw.data_len = bce_RXP_b06FwDataLen; 4206 fw.data_index = 0; 4207 fw.data = bce_RXP_b06FwData; 4208 4209 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4210 fw.sbss_len = bce_RXP_b06FwSbssLen; 4211 fw.sbss_index = 0; 4212 fw.sbss = bce_RXP_b06FwSbss; 4213 4214 fw.bss_addr = bce_RXP_b06FwBssAddr; 4215 fw.bss_len = bce_RXP_b06FwBssLen; 4216 fw.bss_index = 0; 4217 fw.bss = bce_RXP_b06FwBss; 4218 4219 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4220 fw.rodata_len = bce_RXP_b06FwRodataLen; 4221 fw.rodata_index = 0; 4222 fw.rodata = bce_RXP_b06FwRodata; 4223 } 4224 4225 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4226 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4227 4228 /* Delay RXP start until initialization is complete. */ 4229 4230 DBEXIT(BCE_VERBOSE_RESET); 4231 } 4232 4233 /****************************************************************************/ 4234 /* Initialize the TX CPU. */ 4235 /* */ 4236 /* Returns: */ 4237 /* Nothing. */ 4238 /****************************************************************************/ 4239 static void 4240 bce_init_txp_cpu(struct bce_softc *sc) 4241 { 4242 struct cpu_reg cpu_reg; 4243 struct fw_info fw; 4244 4245 DBENTER(BCE_VERBOSE_RESET); 4246 4247 cpu_reg.mode = BCE_TXP_CPU_MODE; 4248 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4249 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4250 cpu_reg.state = BCE_TXP_CPU_STATE; 4251 cpu_reg.state_value_clear = 0xffffff; 4252 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4253 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4254 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4255 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4256 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4257 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4258 cpu_reg.mips_view_base = 0x8000000; 4259 4260 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4261 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4262 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4263 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4264 fw.start_addr = bce_TXP_b09FwStartAddr; 4265 4266 fw.text_addr = bce_TXP_b09FwTextAddr; 4267 fw.text_len = bce_TXP_b09FwTextLen; 4268 fw.text_index = 0; 4269 fw.text = bce_TXP_b09FwText; 4270 4271 fw.data_addr = bce_TXP_b09FwDataAddr; 4272 fw.data_len = bce_TXP_b09FwDataLen; 4273 fw.data_index = 0; 4274 fw.data = bce_TXP_b09FwData; 4275 4276 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4277 fw.sbss_len = bce_TXP_b09FwSbssLen; 4278 fw.sbss_index = 0; 4279 fw.sbss = bce_TXP_b09FwSbss; 4280 4281 fw.bss_addr = bce_TXP_b09FwBssAddr; 4282 fw.bss_len = bce_TXP_b09FwBssLen; 4283 fw.bss_index = 0; 4284 fw.bss = bce_TXP_b09FwBss; 4285 4286 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4287 fw.rodata_len = bce_TXP_b09FwRodataLen; 4288 fw.rodata_index = 0; 4289 fw.rodata = bce_TXP_b09FwRodata; 4290 } else { 4291 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4292 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4293 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4294 fw.start_addr = bce_TXP_b06FwStartAddr; 4295 4296 fw.text_addr = bce_TXP_b06FwTextAddr; 4297 fw.text_len = bce_TXP_b06FwTextLen; 4298 fw.text_index = 0; 4299 fw.text = bce_TXP_b06FwText; 4300 4301 fw.data_addr = bce_TXP_b06FwDataAddr; 4302 fw.data_len = bce_TXP_b06FwDataLen; 4303 fw.data_index = 0; 4304 fw.data = bce_TXP_b06FwData; 4305 4306 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4307 fw.sbss_len = bce_TXP_b06FwSbssLen; 4308 fw.sbss_index = 0; 4309 fw.sbss = bce_TXP_b06FwSbss; 4310 4311 fw.bss_addr = bce_TXP_b06FwBssAddr; 4312 fw.bss_len = bce_TXP_b06FwBssLen; 4313 fw.bss_index = 0; 4314 fw.bss = bce_TXP_b06FwBss; 4315 4316 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4317 fw.rodata_len = bce_TXP_b06FwRodataLen; 4318 fw.rodata_index = 0; 4319 fw.rodata = bce_TXP_b06FwRodata; 4320 } 4321 4322 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4323 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4324 bce_start_cpu(sc, &cpu_reg); 4325 4326 DBEXIT(BCE_VERBOSE_RESET); 4327 } 4328 4329 /****************************************************************************/ 4330 /* Initialize the TPAT CPU. */ 4331 /* */ 4332 /* Returns: */ 4333 /* Nothing. */ 4334 /****************************************************************************/ 4335 static void 4336 bce_init_tpat_cpu(struct bce_softc *sc) 4337 { 4338 struct cpu_reg cpu_reg; 4339 struct fw_info fw; 4340 4341 DBENTER(BCE_VERBOSE_RESET); 4342 4343 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4344 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4345 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4346 cpu_reg.state = BCE_TPAT_CPU_STATE; 4347 cpu_reg.state_value_clear = 0xffffff; 4348 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4349 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4350 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4351 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4352 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4353 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4354 cpu_reg.mips_view_base = 0x8000000; 4355 4356 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4357 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4358 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4359 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4360 fw.start_addr = bce_TPAT_b09FwStartAddr; 4361 4362 fw.text_addr = bce_TPAT_b09FwTextAddr; 4363 fw.text_len = bce_TPAT_b09FwTextLen; 4364 fw.text_index = 0; 4365 fw.text = bce_TPAT_b09FwText; 4366 4367 fw.data_addr = bce_TPAT_b09FwDataAddr; 4368 fw.data_len = bce_TPAT_b09FwDataLen; 4369 fw.data_index = 0; 4370 fw.data = bce_TPAT_b09FwData; 4371 4372 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4373 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4374 fw.sbss_index = 0; 4375 fw.sbss = bce_TPAT_b09FwSbss; 4376 4377 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4378 fw.bss_len = bce_TPAT_b09FwBssLen; 4379 fw.bss_index = 0; 4380 fw.bss = bce_TPAT_b09FwBss; 4381 4382 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4383 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4384 fw.rodata_index = 0; 4385 fw.rodata = bce_TPAT_b09FwRodata; 4386 } else { 4387 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4388 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4389 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4390 fw.start_addr = bce_TPAT_b06FwStartAddr; 4391 4392 fw.text_addr = bce_TPAT_b06FwTextAddr; 4393 fw.text_len = bce_TPAT_b06FwTextLen; 4394 fw.text_index = 0; 4395 fw.text = bce_TPAT_b06FwText; 4396 4397 fw.data_addr = bce_TPAT_b06FwDataAddr; 4398 fw.data_len = bce_TPAT_b06FwDataLen; 4399 fw.data_index = 0; 4400 fw.data = bce_TPAT_b06FwData; 4401 4402 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4403 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4404 fw.sbss_index = 0; 4405 fw.sbss = bce_TPAT_b06FwSbss; 4406 4407 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4408 fw.bss_len = bce_TPAT_b06FwBssLen; 4409 fw.bss_index = 0; 4410 fw.bss = bce_TPAT_b06FwBss; 4411 4412 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4413 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4414 fw.rodata_index = 0; 4415 fw.rodata = bce_TPAT_b06FwRodata; 4416 } 4417 4418 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4419 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4420 bce_start_cpu(sc, &cpu_reg); 4421 4422 DBEXIT(BCE_VERBOSE_RESET); 4423 } 4424 4425 /****************************************************************************/ 4426 /* Initialize the CP CPU. */ 4427 /* */ 4428 /* Returns: */ 4429 /* Nothing. */ 4430 /****************************************************************************/ 4431 static void 4432 bce_init_cp_cpu(struct bce_softc *sc) 4433 { 4434 struct cpu_reg cpu_reg; 4435 struct fw_info fw; 4436 4437 DBENTER(BCE_VERBOSE_RESET); 4438 4439 cpu_reg.mode = BCE_CP_CPU_MODE; 4440 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4441 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4442 cpu_reg.state = BCE_CP_CPU_STATE; 4443 cpu_reg.state_value_clear = 0xffffff; 4444 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4445 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4446 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4447 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4448 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4449 cpu_reg.spad_base = BCE_CP_SCRATCH; 4450 cpu_reg.mips_view_base = 0x8000000; 4451 4452 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4453 fw.ver_major = bce_CP_b09FwReleaseMajor; 4454 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4455 fw.ver_fix = bce_CP_b09FwReleaseFix; 4456 fw.start_addr = bce_CP_b09FwStartAddr; 4457 4458 fw.text_addr = bce_CP_b09FwTextAddr; 4459 fw.text_len = bce_CP_b09FwTextLen; 4460 fw.text_index = 0; 4461 fw.text = bce_CP_b09FwText; 4462 4463 fw.data_addr = bce_CP_b09FwDataAddr; 4464 fw.data_len = bce_CP_b09FwDataLen; 4465 fw.data_index = 0; 4466 fw.data = bce_CP_b09FwData; 4467 4468 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4469 fw.sbss_len = bce_CP_b09FwSbssLen; 4470 fw.sbss_index = 0; 4471 fw.sbss = bce_CP_b09FwSbss; 4472 4473 fw.bss_addr = bce_CP_b09FwBssAddr; 4474 fw.bss_len = bce_CP_b09FwBssLen; 4475 fw.bss_index = 0; 4476 fw.bss = bce_CP_b09FwBss; 4477 4478 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4479 fw.rodata_len = bce_CP_b09FwRodataLen; 4480 fw.rodata_index = 0; 4481 fw.rodata = bce_CP_b09FwRodata; 4482 } else { 4483 fw.ver_major = bce_CP_b06FwReleaseMajor; 4484 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4485 fw.ver_fix = bce_CP_b06FwReleaseFix; 4486 fw.start_addr = bce_CP_b06FwStartAddr; 4487 4488 fw.text_addr = bce_CP_b06FwTextAddr; 4489 fw.text_len = bce_CP_b06FwTextLen; 4490 fw.text_index = 0; 4491 fw.text = bce_CP_b06FwText; 4492 4493 fw.data_addr = bce_CP_b06FwDataAddr; 4494 fw.data_len = bce_CP_b06FwDataLen; 4495 fw.data_index = 0; 4496 fw.data = bce_CP_b06FwData; 4497 4498 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4499 fw.sbss_len = bce_CP_b06FwSbssLen; 4500 fw.sbss_index = 0; 4501 fw.sbss = bce_CP_b06FwSbss; 4502 4503 fw.bss_addr = bce_CP_b06FwBssAddr; 4504 fw.bss_len = bce_CP_b06FwBssLen; 4505 fw.bss_index = 0; 4506 fw.bss = bce_CP_b06FwBss; 4507 4508 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4509 fw.rodata_len = bce_CP_b06FwRodataLen; 4510 fw.rodata_index = 0; 4511 fw.rodata = bce_CP_b06FwRodata; 4512 } 4513 4514 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4515 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4516 bce_start_cpu(sc, &cpu_reg); 4517 4518 DBEXIT(BCE_VERBOSE_RESET); 4519 } 4520 4521 /****************************************************************************/ 4522 /* Initialize the COM CPU. */ 4523 /* */ 4524 /* Returns: */ 4525 /* Nothing. */ 4526 /****************************************************************************/ 4527 static void 4528 bce_init_com_cpu(struct bce_softc *sc) 4529 { 4530 struct cpu_reg cpu_reg; 4531 struct fw_info fw; 4532 4533 DBENTER(BCE_VERBOSE_RESET); 4534 4535 cpu_reg.mode = BCE_COM_CPU_MODE; 4536 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4537 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4538 cpu_reg.state = BCE_COM_CPU_STATE; 4539 cpu_reg.state_value_clear = 0xffffff; 4540 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4541 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4542 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4543 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4544 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4545 cpu_reg.spad_base = BCE_COM_SCRATCH; 4546 cpu_reg.mips_view_base = 0x8000000; 4547 4548 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4549 fw.ver_major = bce_COM_b09FwReleaseMajor; 4550 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4551 fw.ver_fix = bce_COM_b09FwReleaseFix; 4552 fw.start_addr = bce_COM_b09FwStartAddr; 4553 4554 fw.text_addr = bce_COM_b09FwTextAddr; 4555 fw.text_len = bce_COM_b09FwTextLen; 4556 fw.text_index = 0; 4557 fw.text = bce_COM_b09FwText; 4558 4559 fw.data_addr = bce_COM_b09FwDataAddr; 4560 fw.data_len = bce_COM_b09FwDataLen; 4561 fw.data_index = 0; 4562 fw.data = bce_COM_b09FwData; 4563 4564 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4565 fw.sbss_len = bce_COM_b09FwSbssLen; 4566 fw.sbss_index = 0; 4567 fw.sbss = bce_COM_b09FwSbss; 4568 4569 fw.bss_addr = bce_COM_b09FwBssAddr; 4570 fw.bss_len = bce_COM_b09FwBssLen; 4571 fw.bss_index = 0; 4572 fw.bss = bce_COM_b09FwBss; 4573 4574 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4575 fw.rodata_len = bce_COM_b09FwRodataLen; 4576 fw.rodata_index = 0; 4577 fw.rodata = bce_COM_b09FwRodata; 4578 } else { 4579 fw.ver_major = bce_COM_b06FwReleaseMajor; 4580 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4581 fw.ver_fix = bce_COM_b06FwReleaseFix; 4582 fw.start_addr = bce_COM_b06FwStartAddr; 4583 4584 fw.text_addr = bce_COM_b06FwTextAddr; 4585 fw.text_len = bce_COM_b06FwTextLen; 4586 fw.text_index = 0; 4587 fw.text = bce_COM_b06FwText; 4588 4589 fw.data_addr = bce_COM_b06FwDataAddr; 4590 fw.data_len = bce_COM_b06FwDataLen; 4591 fw.data_index = 0; 4592 fw.data = bce_COM_b06FwData; 4593 4594 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4595 fw.sbss_len = bce_COM_b06FwSbssLen; 4596 fw.sbss_index = 0; 4597 fw.sbss = bce_COM_b06FwSbss; 4598 4599 fw.bss_addr = bce_COM_b06FwBssAddr; 4600 fw.bss_len = bce_COM_b06FwBssLen; 4601 fw.bss_index = 0; 4602 fw.bss = bce_COM_b06FwBss; 4603 4604 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4605 fw.rodata_len = bce_COM_b06FwRodataLen; 4606 fw.rodata_index = 0; 4607 fw.rodata = bce_COM_b06FwRodata; 4608 } 4609 4610 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4611 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4612 bce_start_cpu(sc, &cpu_reg); 4613 4614 DBEXIT(BCE_VERBOSE_RESET); 4615 } 4616 4617 /****************************************************************************/ 4618 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4619 /* */ 4620 /* Loads the firmware for each CPU and starts the CPU. */ 4621 /* */ 4622 /* Returns: */ 4623 /* Nothing. */ 4624 /****************************************************************************/ 4625 static void 4626 bce_init_cpus(struct bce_softc *sc) 4627 { 4628 DBENTER(BCE_VERBOSE_RESET); 4629 4630 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4631 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4632 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4633 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4634 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4635 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4636 } else { 4637 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4638 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4639 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4640 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4641 } 4642 4643 } else { 4644 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4645 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4646 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4647 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4648 } 4649 4650 bce_init_rxp_cpu(sc); 4651 bce_init_txp_cpu(sc); 4652 bce_init_tpat_cpu(sc); 4653 bce_init_com_cpu(sc); 4654 bce_init_cp_cpu(sc); 4655 4656 DBEXIT(BCE_VERBOSE_RESET); 4657 } 4658 4659 /****************************************************************************/ 4660 /* Initialize context memory. */ 4661 /* */ 4662 /* Clears the memory associated with each Context ID (CID). */ 4663 /* */ 4664 /* Returns: */ 4665 /* Nothing. */ 4666 /****************************************************************************/ 4667 static int 4668 bce_init_ctx(struct bce_softc *sc) 4669 { 4670 u32 offset, val, vcid_addr; 4671 int i, j, rc, retry_cnt; 4672 4673 rc = 0; 4674 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4675 4676 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4677 retry_cnt = CTX_INIT_RETRY_COUNT; 4678 4679 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4680 4681 /* 4682 * BCM5709 context memory may be cached 4683 * in host memory so prepare the host memory 4684 * for access. 4685 */ 4686 val = BCE_CTX_COMMAND_ENABLED | 4687 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4688 val |= (BCM_PAGE_BITS - 8) << 16; 4689 REG_WR(sc, BCE_CTX_COMMAND, val); 4690 4691 /* Wait for mem init command to complete. */ 4692 for (i = 0; i < retry_cnt; i++) { 4693 val = REG_RD(sc, BCE_CTX_COMMAND); 4694 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4695 break; 4696 DELAY(2); 4697 } 4698 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4699 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4700 __FUNCTION__); 4701 rc = EBUSY; 4702 goto init_ctx_fail; 4703 } 4704 4705 for (i = 0; i < sc->ctx_pages; i++) { 4706 /* Set the physical address of the context memory. */ 4707 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4708 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4709 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4710 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4711 BCE_ADDR_HI(sc->ctx_paddr[i])); 4712 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4713 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4714 4715 /* Verify the context memory write was successful. */ 4716 for (j = 0; j < retry_cnt; j++) { 4717 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4718 if ((val & 4719 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4720 break; 4721 DELAY(5); 4722 } 4723 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4724 BCE_PRINTF("%s(): Failed to initialize " 4725 "context page %d!\n", __FUNCTION__, i); 4726 rc = EBUSY; 4727 goto init_ctx_fail; 4728 } 4729 } 4730 } else { 4731 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4732 4733 /* 4734 * For the 5706/5708, context memory is local to 4735 * the controller, so initialize the controller 4736 * context memory. 4737 */ 4738 4739 vcid_addr = GET_CID_ADDR(96); 4740 while (vcid_addr) { 4741 vcid_addr -= PHY_CTX_SIZE; 4742 4743 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4744 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4745 4746 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4747 CTX_WR(sc, 0x00, offset, 0); 4748 } 4749 4750 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4751 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4752 } 4753 } 4754 init_ctx_fail: 4755 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4756 return (rc); 4757 } 4758 4759 /****************************************************************************/ 4760 /* Fetch the permanent MAC address of the controller. */ 4761 /* */ 4762 /* Returns: */ 4763 /* Nothing. */ 4764 /****************************************************************************/ 4765 static void 4766 bce_get_mac_addr(struct bce_softc *sc) 4767 { 4768 u32 mac_lo = 0, mac_hi = 0; 4769 4770 DBENTER(BCE_VERBOSE_RESET); 4771 4772 /* 4773 * The NetXtreme II bootcode populates various NIC 4774 * power-on and runtime configuration items in a 4775 * shared memory area. The factory configured MAC 4776 * address is available from both NVRAM and the 4777 * shared memory area so we'll read the value from 4778 * shared memory for speed. 4779 */ 4780 4781 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4782 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4783 4784 if ((mac_lo == 0) && (mac_hi == 0)) { 4785 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4786 __FILE__, __LINE__); 4787 } else { 4788 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4789 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4790 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4791 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4792 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4793 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4794 } 4795 4796 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4797 "address = %6D\n", sc->eaddr, ":"); 4798 DBEXIT(BCE_VERBOSE_RESET); 4799 } 4800 4801 /****************************************************************************/ 4802 /* Program the MAC address. */ 4803 /* */ 4804 /* Returns: */ 4805 /* Nothing. */ 4806 /****************************************************************************/ 4807 static void 4808 bce_set_mac_addr(struct bce_softc *sc) 4809 { 4810 u32 val; 4811 u8 *mac_addr = sc->eaddr; 4812 4813 /* ToDo: Add support for setting multiple MAC addresses. */ 4814 4815 DBENTER(BCE_VERBOSE_RESET); 4816 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4817 "%6D\n", sc->eaddr, ":"); 4818 4819 val = (mac_addr[0] << 8) | mac_addr[1]; 4820 4821 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4822 4823 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4824 (mac_addr[4] << 8) | mac_addr[5]; 4825 4826 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4827 4828 DBEXIT(BCE_VERBOSE_RESET); 4829 } 4830 4831 /****************************************************************************/ 4832 /* Stop the controller. */ 4833 /* */ 4834 /* Returns: */ 4835 /* Nothing. */ 4836 /****************************************************************************/ 4837 static void 4838 bce_stop(struct bce_softc *sc) 4839 { 4840 struct ifnet *ifp; 4841 4842 DBENTER(BCE_VERBOSE_RESET); 4843 4844 BCE_LOCK_ASSERT(sc); 4845 4846 ifp = sc->bce_ifp; 4847 4848 callout_stop(&sc->bce_tick_callout); 4849 4850 /* Disable the transmit/receive blocks. */ 4851 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4852 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4853 DELAY(20); 4854 4855 bce_disable_intr(sc); 4856 4857 /* Free RX buffers. */ 4858 if (bce_hdr_split == TRUE) { 4859 bce_free_pg_chain(sc); 4860 } 4861 bce_free_rx_chain(sc); 4862 4863 /* Free TX buffers. */ 4864 bce_free_tx_chain(sc); 4865 4866 sc->watchdog_timer = 0; 4867 4868 sc->bce_link_up = FALSE; 4869 4870 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4871 4872 DBEXIT(BCE_VERBOSE_RESET); 4873 } 4874 4875 static int 4876 bce_reset(struct bce_softc *sc, u32 reset_code) 4877 { 4878 u32 emac_mode_save, val; 4879 int i, rc = 0; 4880 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT | 4881 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G; 4882 4883 DBENTER(BCE_VERBOSE_RESET); 4884 4885 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4886 __FUNCTION__, reset_code); 4887 4888 /* 4889 * If ASF/IPMI is operational, then the EMAC Mode register already 4890 * contains appropriate values for the link settings that have 4891 * been auto-negotiated. Resetting the chip will clobber those 4892 * values. Save the important bits so we can restore them after 4893 * the reset. 4894 */ 4895 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask; 4896 4897 /* Wait for pending PCI transactions to complete. */ 4898 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4899 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4900 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4901 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4902 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4903 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4904 DELAY(5); 4905 4906 /* Disable DMA */ 4907 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4908 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4909 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4910 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4911 } 4912 4913 /* Assume bootcode is running. */ 4914 sc->bce_fw_timed_out = FALSE; 4915 sc->bce_drv_cardiac_arrest = FALSE; 4916 4917 /* Give the firmware a chance to prepare for the reset. */ 4918 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4919 if (rc) 4920 goto bce_reset_exit; 4921 4922 /* Set a firmware reminder that this is a soft reset. */ 4923 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4924 4925 /* Dummy read to force the chip to complete all current transactions. */ 4926 val = REG_RD(sc, BCE_MISC_ID); 4927 4928 /* Chip reset. */ 4929 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4930 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4931 REG_RD(sc, BCE_MISC_COMMAND); 4932 DELAY(5); 4933 4934 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4935 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4936 4937 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4938 } else { 4939 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4940 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4941 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4942 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4943 4944 /* Allow up to 30us for reset to complete. */ 4945 for (i = 0; i < 10; i++) { 4946 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 4947 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4948 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 4949 break; 4950 } 4951 DELAY(10); 4952 } 4953 4954 /* Check that reset completed successfully. */ 4955 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4956 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4957 BCE_PRINTF("%s(%d): Reset failed!\n", 4958 __FILE__, __LINE__); 4959 rc = EBUSY; 4960 goto bce_reset_exit; 4961 } 4962 } 4963 4964 /* Make sure byte swapping is properly configured. */ 4965 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 4966 if (val != 0x01020304) { 4967 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 4968 __FILE__, __LINE__); 4969 rc = ENODEV; 4970 goto bce_reset_exit; 4971 } 4972 4973 /* Just completed a reset, assume that firmware is running again. */ 4974 sc->bce_fw_timed_out = FALSE; 4975 sc->bce_drv_cardiac_arrest = FALSE; 4976 4977 /* Wait for the firmware to finish its initialization. */ 4978 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 4979 if (rc) 4980 BCE_PRINTF("%s(%d): Firmware did not complete " 4981 "initialization!\n", __FILE__, __LINE__); 4982 /* Get firmware capabilities. */ 4983 bce_fw_cap_init(sc); 4984 4985 bce_reset_exit: 4986 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */ 4987 if (reset_code == BCE_DRV_MSG_CODE_RESET) { 4988 val = REG_RD(sc, BCE_EMAC_MODE); 4989 val = (val & ~emac_mode_mask) | emac_mode_save; 4990 REG_WR(sc, BCE_EMAC_MODE, val); 4991 } 4992 4993 DBEXIT(BCE_VERBOSE_RESET); 4994 return (rc); 4995 } 4996 4997 static int 4998 bce_chipinit(struct bce_softc *sc) 4999 { 5000 u32 val; 5001 int rc = 0; 5002 5003 DBENTER(BCE_VERBOSE_RESET); 5004 5005 bce_disable_intr(sc); 5006 5007 /* 5008 * Initialize DMA byte/word swapping, configure the number of DMA 5009 * channels and PCI clock compensation delay. 5010 */ 5011 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5012 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5013 #if BYTE_ORDER == BIG_ENDIAN 5014 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5015 #endif 5016 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5017 DMA_READ_CHANS << 12 | 5018 DMA_WRITE_CHANS << 16; 5019 5020 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5021 5022 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5023 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5024 5025 /* 5026 * This setting resolves a problem observed on certain Intel PCI 5027 * chipsets that cannot handle multiple outstanding DMA operations. 5028 * See errata E9_5706A1_65. 5029 */ 5030 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5031 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5032 !(sc->bce_flags & BCE_PCIX_FLAG)) 5033 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5034 5035 REG_WR(sc, BCE_DMA_CONFIG, val); 5036 5037 /* Enable the RX_V2P and Context state machines before access. */ 5038 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5039 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5040 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5041 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5042 5043 /* Initialize context mapping and zero out the quick contexts. */ 5044 if ((rc = bce_init_ctx(sc)) != 0) 5045 goto bce_chipinit_exit; 5046 5047 /* Initialize the on-boards CPUs */ 5048 bce_init_cpus(sc); 5049 5050 /* Enable management frames (NC-SI) to flow to the MCP. */ 5051 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5052 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5053 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5054 } 5055 5056 /* Prepare NVRAM for access. */ 5057 if ((rc = bce_init_nvram(sc)) != 0) 5058 goto bce_chipinit_exit; 5059 5060 /* Set the kernel bypass block size */ 5061 val = REG_RD(sc, BCE_MQ_CONFIG); 5062 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5063 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5064 5065 /* Enable bins used on the 5709. */ 5066 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5067 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5068 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5069 val |= BCE_MQ_CONFIG_HALT_DIS; 5070 } 5071 5072 REG_WR(sc, BCE_MQ_CONFIG, val); 5073 5074 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5075 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5076 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5077 5078 /* Set the page size and clear the RV2P processor stall bits. */ 5079 val = (BCM_PAGE_BITS - 8) << 24; 5080 REG_WR(sc, BCE_RV2P_CONFIG, val); 5081 5082 /* Configure page size. */ 5083 val = REG_RD(sc, BCE_TBDR_CONFIG); 5084 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5085 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5086 REG_WR(sc, BCE_TBDR_CONFIG, val); 5087 5088 /* Set the perfect match control register to default. */ 5089 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5090 5091 bce_chipinit_exit: 5092 DBEXIT(BCE_VERBOSE_RESET); 5093 5094 return(rc); 5095 } 5096 5097 /****************************************************************************/ 5098 /* Initialize the controller in preparation to send/receive traffic. */ 5099 /* */ 5100 /* Returns: */ 5101 /* 0 for success, positive value for failure. */ 5102 /****************************************************************************/ 5103 static int 5104 bce_blockinit(struct bce_softc *sc) 5105 { 5106 u32 reg, val; 5107 int rc = 0; 5108 5109 DBENTER(BCE_VERBOSE_RESET); 5110 5111 /* Load the hardware default MAC address. */ 5112 bce_set_mac_addr(sc); 5113 5114 /* Set the Ethernet backoff seed value */ 5115 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5116 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5117 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5118 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5119 5120 sc->last_status_idx = 0; 5121 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5122 5123 /* Set up link change interrupt generation. */ 5124 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5125 5126 /* Program the physical address of the status block. */ 5127 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5128 BCE_ADDR_LO(sc->status_block_paddr)); 5129 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5130 BCE_ADDR_HI(sc->status_block_paddr)); 5131 5132 /* Program the physical address of the statistics block. */ 5133 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5134 BCE_ADDR_LO(sc->stats_block_paddr)); 5135 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5136 BCE_ADDR_HI(sc->stats_block_paddr)); 5137 5138 /* 5139 * Program various host coalescing parameters. 5140 * Trip points control how many BDs should be ready before generating 5141 * an interrupt while ticks control how long a BD can sit in the chain 5142 * before generating an interrupt. 5143 */ 5144 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5145 (sc->bce_tx_quick_cons_trip_int << 16) | 5146 sc->bce_tx_quick_cons_trip); 5147 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5148 (sc->bce_rx_quick_cons_trip_int << 16) | 5149 sc->bce_rx_quick_cons_trip); 5150 REG_WR(sc, BCE_HC_TX_TICKS, 5151 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5152 REG_WR(sc, BCE_HC_RX_TICKS, 5153 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5154 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00); 5155 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5156 /* Not used for L2. */ 5157 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0); 5158 REG_WR(sc, BCE_HC_COM_TICKS, 0); 5159 REG_WR(sc, BCE_HC_CMD_TICKS, 0); 5160 5161 /* Configure the Host Coalescing block. */ 5162 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5163 BCE_HC_CONFIG_COLLECT_STATS; 5164 5165 #if 0 5166 /* ToDo: Add MSI-X support. */ 5167 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5168 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5169 BCE_HC_SB_CONFIG_1; 5170 5171 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5172 5173 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5174 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5175 5176 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5177 (sc->tx_quick_cons_trip_int << 16) | 5178 sc->tx_quick_cons_trip); 5179 5180 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5181 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5182 5183 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5184 } 5185 5186 /* 5187 * Tell the HC block to automatically set the 5188 * INT_MASK bit after an MSI/MSI-X interrupt 5189 * is generated so the driver doesn't have to. 5190 */ 5191 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5192 val |= BCE_HC_CONFIG_ONE_SHOT; 5193 5194 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5195 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5196 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5197 #endif 5198 5199 REG_WR(sc, BCE_HC_CONFIG, val); 5200 5201 /* Clear the internal statistics counters. */ 5202 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5203 5204 /* Verify that bootcode is running. */ 5205 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5206 5207 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5208 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5209 __FILE__, __LINE__); 5210 reg = 0); 5211 5212 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5213 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5214 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5215 "Expected: 08%08X\n", __FILE__, __LINE__, 5216 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5217 BCE_DEV_INFO_SIGNATURE_MAGIC); 5218 rc = ENODEV; 5219 goto bce_blockinit_exit; 5220 } 5221 5222 /* Enable DMA */ 5223 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5224 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5225 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5226 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5227 } 5228 5229 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5230 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5231 BCE_DRV_MSG_CODE_RESET); 5232 5233 /* Enable link state change interrupt generation. */ 5234 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5235 5236 /* Enable the RXP. */ 5237 bce_start_rxp_cpu(sc); 5238 5239 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5240 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5241 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5242 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5243 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5244 } 5245 5246 /* Enable all remaining blocks in the MAC. */ 5247 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5248 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5249 BCE_MISC_ENABLE_DEFAULT_XI); 5250 else 5251 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5252 BCE_MISC_ENABLE_DEFAULT); 5253 5254 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5255 DELAY(20); 5256 5257 /* Save the current host coalescing block settings. */ 5258 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5259 5260 bce_blockinit_exit: 5261 DBEXIT(BCE_VERBOSE_RESET); 5262 5263 return (rc); 5264 } 5265 5266 /****************************************************************************/ 5267 /* Encapsulate an mbuf into the rx_bd chain. */ 5268 /* */ 5269 /* Returns: */ 5270 /* 0 for success, positive value for failure. */ 5271 /****************************************************************************/ 5272 static int 5273 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq) 5274 { 5275 bus_dma_segment_t segs[1]; 5276 struct mbuf *m_new = NULL; 5277 struct rx_bd *rxbd; 5278 int nsegs, error, rc = 0; 5279 #ifdef BCE_DEBUG 5280 u16 debug_chain_prod = chain_prod; 5281 #endif 5282 5283 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5284 5285 /* Make sure the inputs are valid. */ 5286 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC), 5287 BCE_PRINTF("%s(%d): RX producer out of range: " 5288 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5289 chain_prod, (u16)MAX_RX_BD_ALLOC)); 5290 5291 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5292 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5293 prod, chain_prod, *prod_bseq); 5294 5295 /* Update some debug statistic counters */ 5296 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5297 sc->rx_low_watermark = sc->free_rx_bd); 5298 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5299 sc->rx_empty_count++); 5300 5301 /* Simulate an mbuf allocation failure. */ 5302 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5303 sc->mbuf_alloc_failed_count++; 5304 sc->mbuf_alloc_failed_sim_count++; 5305 rc = ENOBUFS; 5306 goto bce_get_rx_buf_exit); 5307 5308 /* This is a new mbuf allocation. */ 5309 if (bce_hdr_split == TRUE) 5310 MGETHDR(m_new, M_NOWAIT, MT_DATA); 5311 else 5312 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 5313 sc->rx_bd_mbuf_alloc_size); 5314 5315 if (m_new == NULL) { 5316 sc->mbuf_alloc_failed_count++; 5317 rc = ENOBUFS; 5318 goto bce_get_rx_buf_exit; 5319 } 5320 5321 DBRUN(sc->debug_rx_mbuf_alloc++); 5322 5323 /* Make sure we have a valid packet header. */ 5324 M_ASSERTPKTHDR(m_new); 5325 5326 /* Initialize the mbuf size and pad if necessary for alignment. */ 5327 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5328 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5329 5330 /* ToDo: Consider calling m_fragment() to test error handling. */ 5331 5332 /* Map the mbuf cluster into device memory. */ 5333 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, 5334 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5335 5336 /* Handle any mapping errors. */ 5337 if (error) { 5338 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5339 "chain (%d)!\n", __FILE__, __LINE__, error); 5340 5341 sc->dma_map_addr_rx_failed_count++; 5342 m_freem(m_new); 5343 5344 DBRUN(sc->debug_rx_mbuf_alloc--); 5345 5346 rc = ENOBUFS; 5347 goto bce_get_rx_buf_exit; 5348 } 5349 5350 /* All mbufs must map to a single segment. */ 5351 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5352 __FUNCTION__, nsegs)); 5353 5354 /* Setup the rx_bd for the segment. */ 5355 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)]; 5356 5357 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5358 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5359 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5360 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5361 *prod_bseq += segs[0].ds_len; 5362 5363 /* Save the mbuf and update our counter. */ 5364 sc->rx_mbuf_ptr[chain_prod] = m_new; 5365 sc->free_rx_bd -= nsegs; 5366 5367 DBRUNMSG(BCE_INSANE_RECV, 5368 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5369 5370 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5371 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod, 5372 chain_prod, *prod_bseq); 5373 5374 bce_get_rx_buf_exit: 5375 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5376 5377 return(rc); 5378 } 5379 5380 /****************************************************************************/ 5381 /* Encapsulate an mbuf cluster into the page chain. */ 5382 /* */ 5383 /* Returns: */ 5384 /* 0 for success, positive value for failure. */ 5385 /****************************************************************************/ 5386 static int 5387 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx) 5388 { 5389 bus_dma_segment_t segs[1]; 5390 struct mbuf *m_new = NULL; 5391 struct rx_bd *pgbd; 5392 int error, nsegs, rc = 0; 5393 #ifdef BCE_DEBUG 5394 u16 debug_prod_idx = prod_idx; 5395 #endif 5396 5397 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5398 5399 /* Make sure the inputs are valid. */ 5400 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC), 5401 BCE_PRINTF("%s(%d): page producer out of range: " 5402 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5403 prod_idx, (u16)MAX_PG_BD_ALLOC)); 5404 5405 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5406 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5407 5408 /* Update counters if we've hit a new low or run out of pages. */ 5409 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5410 sc->pg_low_watermark = sc->free_pg_bd); 5411 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5412 5413 /* Simulate an mbuf allocation failure. */ 5414 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5415 sc->mbuf_alloc_failed_count++; 5416 sc->mbuf_alloc_failed_sim_count++; 5417 rc = ENOBUFS; 5418 goto bce_get_pg_buf_exit); 5419 5420 /* This is a new mbuf allocation. */ 5421 m_new = m_getcl(M_NOWAIT, MT_DATA, 0); 5422 if (m_new == NULL) { 5423 sc->mbuf_alloc_failed_count++; 5424 rc = ENOBUFS; 5425 goto bce_get_pg_buf_exit; 5426 } 5427 5428 DBRUN(sc->debug_pg_mbuf_alloc++); 5429 5430 m_new->m_len = MCLBYTES; 5431 5432 /* ToDo: Consider calling m_fragment() to test error handling. */ 5433 5434 /* Map the mbuf cluster into device memory. */ 5435 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag, 5436 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5437 5438 /* Handle any mapping errors. */ 5439 if (error) { 5440 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5441 __FILE__, __LINE__); 5442 5443 m_freem(m_new); 5444 DBRUN(sc->debug_pg_mbuf_alloc--); 5445 5446 rc = ENOBUFS; 5447 goto bce_get_pg_buf_exit; 5448 } 5449 5450 /* All mbufs must map to a single segment. */ 5451 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5452 __FUNCTION__, nsegs)); 5453 5454 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5455 5456 /* 5457 * The page chain uses the same rx_bd data structure 5458 * as the receive chain but doesn't require a byte sequence (bseq). 5459 */ 5460 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)]; 5461 5462 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5463 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5464 pgbd->rx_bd_len = htole32(MCLBYTES); 5465 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5466 5467 /* Save the mbuf and update our counter. */ 5468 sc->pg_mbuf_ptr[prod_idx] = m_new; 5469 sc->free_pg_bd--; 5470 5471 DBRUNMSG(BCE_INSANE_RECV, 5472 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5473 5474 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5475 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5476 5477 bce_get_pg_buf_exit: 5478 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5479 5480 return(rc); 5481 } 5482 5483 /****************************************************************************/ 5484 /* Initialize the TX context memory. */ 5485 /* */ 5486 /* Returns: */ 5487 /* Nothing */ 5488 /****************************************************************************/ 5489 static void 5490 bce_init_tx_context(struct bce_softc *sc) 5491 { 5492 u32 val; 5493 5494 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5495 5496 /* Initialize the context ID for an L2 TX chain. */ 5497 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5498 /* Set the CID type to support an L2 connection. */ 5499 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5500 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5501 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5502 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5503 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5504 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5505 5506 /* Point the hardware to the first page in the chain. */ 5507 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5508 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5509 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5510 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5511 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5512 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5513 } else { 5514 /* Set the CID type to support an L2 connection. */ 5515 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5516 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5517 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5518 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5519 5520 /* Point the hardware to the first page in the chain. */ 5521 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5522 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5523 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5524 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5525 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5526 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5527 } 5528 5529 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5530 } 5531 5532 /****************************************************************************/ 5533 /* Allocate memory and initialize the TX data structures. */ 5534 /* */ 5535 /* Returns: */ 5536 /* 0 for success, positive value for failure. */ 5537 /****************************************************************************/ 5538 static int 5539 bce_init_tx_chain(struct bce_softc *sc) 5540 { 5541 struct tx_bd *txbd; 5542 int i, rc = 0; 5543 5544 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5545 5546 /* Set the initial TX producer/consumer indices. */ 5547 sc->tx_prod = 0; 5548 sc->tx_cons = 0; 5549 sc->tx_prod_bseq = 0; 5550 sc->used_tx_bd = 0; 5551 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5552 DBRUN(sc->tx_hi_watermark = 0); 5553 DBRUN(sc->tx_full_count = 0); 5554 5555 /* 5556 * The NetXtreme II supports a linked-list structure called 5557 * a Buffer Descriptor Chain (or BD chain). A BD chain 5558 * consists of a series of 1 or more chain pages, each of which 5559 * consists of a fixed number of BD entries. 5560 * The last BD entry on each page is a pointer to the next page 5561 * in the chain, and the last pointer in the BD chain 5562 * points back to the beginning of the chain. 5563 */ 5564 5565 /* Set the TX next pointer chain entries. */ 5566 for (i = 0; i < sc->tx_pages; i++) { 5567 int j; 5568 5569 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5570 5571 /* Check if we've reached the last page. */ 5572 if (i == (sc->tx_pages - 1)) 5573 j = 0; 5574 else 5575 j = i + 1; 5576 5577 txbd->tx_bd_haddr_hi = 5578 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5579 txbd->tx_bd_haddr_lo = 5580 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5581 } 5582 5583 bce_init_tx_context(sc); 5584 5585 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5586 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5587 5588 return(rc); 5589 } 5590 5591 /****************************************************************************/ 5592 /* Free memory and clear the TX data structures. */ 5593 /* */ 5594 /* Returns: */ 5595 /* Nothing. */ 5596 /****************************************************************************/ 5597 static void 5598 bce_free_tx_chain(struct bce_softc *sc) 5599 { 5600 int i; 5601 5602 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5603 5604 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5605 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5606 if (sc->tx_mbuf_ptr[i] != NULL) { 5607 if (sc->tx_mbuf_map[i] != NULL) 5608 bus_dmamap_sync(sc->tx_mbuf_tag, 5609 sc->tx_mbuf_map[i], 5610 BUS_DMASYNC_POSTWRITE); 5611 m_freem(sc->tx_mbuf_ptr[i]); 5612 sc->tx_mbuf_ptr[i] = NULL; 5613 DBRUN(sc->debug_tx_mbuf_alloc--); 5614 } 5615 } 5616 5617 /* Clear each TX chain page. */ 5618 for (i = 0; i < sc->tx_pages; i++) 5619 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5620 5621 sc->used_tx_bd = 0; 5622 5623 /* Check if we lost any mbufs in the process. */ 5624 DBRUNIF((sc->debug_tx_mbuf_alloc), 5625 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5626 "from tx chain!\n", __FILE__, __LINE__, 5627 sc->debug_tx_mbuf_alloc)); 5628 5629 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5630 } 5631 5632 /****************************************************************************/ 5633 /* Initialize the RX context memory. */ 5634 /* */ 5635 /* Returns: */ 5636 /* Nothing */ 5637 /****************************************************************************/ 5638 static void 5639 bce_init_rx_context(struct bce_softc *sc) 5640 { 5641 u32 val; 5642 5643 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5644 5645 /* Init the type, size, and BD cache levels for the RX context. */ 5646 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5647 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5648 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5649 5650 /* 5651 * Set the level for generating pause frames 5652 * when the number of available rx_bd's gets 5653 * too low (the low watermark) and the level 5654 * when pause frames can be stopped (the high 5655 * watermark). 5656 */ 5657 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5658 u32 lo_water, hi_water; 5659 5660 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5661 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5662 } else { 5663 lo_water = 0; 5664 } 5665 5666 if (lo_water >= USABLE_RX_BD_ALLOC) { 5667 lo_water = 0; 5668 } 5669 5670 hi_water = USABLE_RX_BD_ALLOC / 4; 5671 5672 if (hi_water <= lo_water) { 5673 lo_water = 0; 5674 } 5675 5676 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5677 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5678 5679 if (hi_water > 0xf) 5680 hi_water = 0xf; 5681 else if (hi_water == 0) 5682 lo_water = 0; 5683 5684 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5685 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5686 } 5687 5688 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5689 5690 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5691 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5692 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5693 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5694 } 5695 5696 /* Point the hardware to the first page in the chain. */ 5697 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5698 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5699 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5700 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5701 5702 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5703 } 5704 5705 /****************************************************************************/ 5706 /* Allocate memory and initialize the RX data structures. */ 5707 /* */ 5708 /* Returns: */ 5709 /* 0 for success, positive value for failure. */ 5710 /****************************************************************************/ 5711 static int 5712 bce_init_rx_chain(struct bce_softc *sc) 5713 { 5714 struct rx_bd *rxbd; 5715 int i, rc = 0; 5716 5717 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5718 BCE_VERBOSE_CTX); 5719 5720 /* Initialize the RX producer and consumer indices. */ 5721 sc->rx_prod = 0; 5722 sc->rx_cons = 0; 5723 sc->rx_prod_bseq = 0; 5724 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5725 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5726 5727 /* Initialize the RX next pointer chain entries. */ 5728 for (i = 0; i < sc->rx_pages; i++) { 5729 int j; 5730 5731 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5732 5733 /* Check if we've reached the last page. */ 5734 if (i == (sc->rx_pages - 1)) 5735 j = 0; 5736 else 5737 j = i + 1; 5738 5739 /* Setup the chain page pointers. */ 5740 rxbd->rx_bd_haddr_hi = 5741 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5742 rxbd->rx_bd_haddr_lo = 5743 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5744 } 5745 5746 /* Fill up the RX chain. */ 5747 bce_fill_rx_chain(sc); 5748 5749 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5750 DBRUN(sc->rx_empty_count = 0); 5751 for (i = 0; i < sc->rx_pages; i++) { 5752 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5753 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5754 } 5755 5756 bce_init_rx_context(sc); 5757 5758 DBRUNMSG(BCE_EXTREME_RECV, 5759 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5760 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5761 BCE_VERBOSE_CTX); 5762 5763 /* ToDo: Are there possible failure modes here? */ 5764 5765 return(rc); 5766 } 5767 5768 /****************************************************************************/ 5769 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5770 /* occurs. */ 5771 /* */ 5772 /* Returns: */ 5773 /* Nothing */ 5774 /****************************************************************************/ 5775 static void 5776 bce_fill_rx_chain(struct bce_softc *sc) 5777 { 5778 u16 prod, prod_idx; 5779 u32 prod_bseq; 5780 5781 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5782 BCE_VERBOSE_CTX); 5783 5784 /* Get the RX chain producer indices. */ 5785 prod = sc->rx_prod; 5786 prod_bseq = sc->rx_prod_bseq; 5787 5788 /* Keep filling the RX chain until it's full. */ 5789 while (sc->free_rx_bd > 0) { 5790 prod_idx = RX_CHAIN_IDX(prod); 5791 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) { 5792 /* Bail out if we can't add an mbuf to the chain. */ 5793 break; 5794 } 5795 prod = NEXT_RX_BD(prod); 5796 } 5797 5798 /* Save the RX chain producer indices. */ 5799 sc->rx_prod = prod; 5800 sc->rx_prod_bseq = prod_bseq; 5801 5802 /* We should never end up pointing to a next page pointer. */ 5803 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5804 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5805 __FUNCTION__, rx_prod)); 5806 5807 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5808 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod); 5809 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq); 5810 5811 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5812 BCE_VERBOSE_CTX); 5813 } 5814 5815 /****************************************************************************/ 5816 /* Free memory and clear the RX data structures. */ 5817 /* */ 5818 /* Returns: */ 5819 /* Nothing. */ 5820 /****************************************************************************/ 5821 static void 5822 bce_free_rx_chain(struct bce_softc *sc) 5823 { 5824 int i; 5825 5826 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5827 5828 /* Free any mbufs still in the RX mbuf chain. */ 5829 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5830 if (sc->rx_mbuf_ptr[i] != NULL) { 5831 if (sc->rx_mbuf_map[i] != NULL) 5832 bus_dmamap_sync(sc->rx_mbuf_tag, 5833 sc->rx_mbuf_map[i], 5834 BUS_DMASYNC_POSTREAD); 5835 m_freem(sc->rx_mbuf_ptr[i]); 5836 sc->rx_mbuf_ptr[i] = NULL; 5837 DBRUN(sc->debug_rx_mbuf_alloc--); 5838 } 5839 } 5840 5841 /* Clear each RX chain page. */ 5842 for (i = 0; i < sc->rx_pages; i++) 5843 if (sc->rx_bd_chain[i] != NULL) 5844 bzero((char *)sc->rx_bd_chain[i], 5845 BCE_RX_CHAIN_PAGE_SZ); 5846 5847 sc->free_rx_bd = sc->max_rx_bd; 5848 5849 /* Check if we lost any mbufs in the process. */ 5850 DBRUNIF((sc->debug_rx_mbuf_alloc), 5851 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5852 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5853 5854 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5855 } 5856 5857 /****************************************************************************/ 5858 /* Allocate memory and initialize the page data structures. */ 5859 /* Assumes that bce_init_rx_chain() has not already been called. */ 5860 /* */ 5861 /* Returns: */ 5862 /* 0 for success, positive value for failure. */ 5863 /****************************************************************************/ 5864 static int 5865 bce_init_pg_chain(struct bce_softc *sc) 5866 { 5867 struct rx_bd *pgbd; 5868 int i, rc = 0; 5869 u32 val; 5870 5871 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5872 BCE_VERBOSE_CTX); 5873 5874 /* Initialize the page producer and consumer indices. */ 5875 sc->pg_prod = 0; 5876 sc->pg_cons = 0; 5877 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5878 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5879 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5880 DBRUN(sc->pg_empty_count = 0); 5881 5882 /* Initialize the page next pointer chain entries. */ 5883 for (i = 0; i < sc->pg_pages; i++) { 5884 int j; 5885 5886 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5887 5888 /* Check if we've reached the last page. */ 5889 if (i == (sc->pg_pages - 1)) 5890 j = 0; 5891 else 5892 j = i + 1; 5893 5894 /* Setup the chain page pointers. */ 5895 pgbd->rx_bd_haddr_hi = 5896 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5897 pgbd->rx_bd_haddr_lo = 5898 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5899 } 5900 5901 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5902 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5903 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5904 5905 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5906 5907 /* Configure the rx_bd and page chain mbuf cluster size. */ 5908 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES; 5909 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5910 5911 /* Configure the context reserved for jumbo support. */ 5912 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5913 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5914 5915 /* Point the hardware to the first page in the page chain. */ 5916 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5917 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 5918 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5919 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 5920 5921 /* Fill up the page chain. */ 5922 bce_fill_pg_chain(sc); 5923 5924 for (i = 0; i < sc->pg_pages; i++) { 5925 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 5926 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5927 } 5928 5929 DBRUNMSG(BCE_EXTREME_RECV, 5930 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 5931 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5932 BCE_VERBOSE_CTX); 5933 return(rc); 5934 } 5935 5936 /****************************************************************************/ 5937 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 5938 /* occurs. */ 5939 /* */ 5940 /* Returns: */ 5941 /* Nothing */ 5942 /****************************************************************************/ 5943 static void 5944 bce_fill_pg_chain(struct bce_softc *sc) 5945 { 5946 u16 prod, prod_idx; 5947 5948 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5949 BCE_VERBOSE_CTX); 5950 5951 /* Get the page chain prodcuer index. */ 5952 prod = sc->pg_prod; 5953 5954 /* Keep filling the page chain until it's full. */ 5955 while (sc->free_pg_bd > 0) { 5956 prod_idx = PG_CHAIN_IDX(prod); 5957 if (bce_get_pg_buf(sc, prod, prod_idx)) { 5958 /* Bail out if we can't add an mbuf to the chain. */ 5959 break; 5960 } 5961 prod = NEXT_PG_BD(prod); 5962 } 5963 5964 /* Save the page chain producer index. */ 5965 sc->pg_prod = prod; 5966 5967 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5968 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 5969 __FUNCTION__, pg_prod)); 5970 5971 /* 5972 * Write the mailbox and tell the chip about 5973 * the new rx_bd's in the page chain. 5974 */ 5975 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX, 5976 prod); 5977 5978 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5979 BCE_VERBOSE_CTX); 5980 } 5981 5982 /****************************************************************************/ 5983 /* Free memory and clear the RX data structures. */ 5984 /* */ 5985 /* Returns: */ 5986 /* Nothing. */ 5987 /****************************************************************************/ 5988 static void 5989 bce_free_pg_chain(struct bce_softc *sc) 5990 { 5991 int i; 5992 5993 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5994 5995 /* Free any mbufs still in the mbuf page chain. */ 5996 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 5997 if (sc->pg_mbuf_ptr[i] != NULL) { 5998 if (sc->pg_mbuf_map[i] != NULL) 5999 bus_dmamap_sync(sc->pg_mbuf_tag, 6000 sc->pg_mbuf_map[i], 6001 BUS_DMASYNC_POSTREAD); 6002 m_freem(sc->pg_mbuf_ptr[i]); 6003 sc->pg_mbuf_ptr[i] = NULL; 6004 DBRUN(sc->debug_pg_mbuf_alloc--); 6005 } 6006 } 6007 6008 /* Clear each page chain pages. */ 6009 for (i = 0; i < sc->pg_pages; i++) 6010 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6011 6012 sc->free_pg_bd = sc->max_pg_bd; 6013 6014 /* Check if we lost any mbufs in the process. */ 6015 DBRUNIF((sc->debug_pg_mbuf_alloc), 6016 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6017 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6018 6019 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6020 } 6021 6022 static u32 6023 bce_get_rphy_link(struct bce_softc *sc) 6024 { 6025 u32 advertise, link; 6026 int fdpx; 6027 6028 advertise = 0; 6029 fdpx = 0; 6030 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) 6031 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK); 6032 else 6033 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK); 6034 if (link & BCE_NETLINK_ANEG_ENB) 6035 advertise |= BCE_NETLINK_ANEG_ENB; 6036 if (link & BCE_NETLINK_SPEED_10HALF) 6037 advertise |= BCE_NETLINK_SPEED_10HALF; 6038 if (link & BCE_NETLINK_SPEED_10FULL) { 6039 advertise |= BCE_NETLINK_SPEED_10FULL; 6040 fdpx++; 6041 } 6042 if (link & BCE_NETLINK_SPEED_100HALF) 6043 advertise |= BCE_NETLINK_SPEED_100HALF; 6044 if (link & BCE_NETLINK_SPEED_100FULL) { 6045 advertise |= BCE_NETLINK_SPEED_100FULL; 6046 fdpx++; 6047 } 6048 if (link & BCE_NETLINK_SPEED_1000HALF) 6049 advertise |= BCE_NETLINK_SPEED_1000HALF; 6050 if (link & BCE_NETLINK_SPEED_1000FULL) { 6051 advertise |= BCE_NETLINK_SPEED_1000FULL; 6052 fdpx++; 6053 } 6054 if (link & BCE_NETLINK_SPEED_2500HALF) 6055 advertise |= BCE_NETLINK_SPEED_2500HALF; 6056 if (link & BCE_NETLINK_SPEED_2500FULL) { 6057 advertise |= BCE_NETLINK_SPEED_2500FULL; 6058 fdpx++; 6059 } 6060 if (fdpx) 6061 advertise |= BCE_NETLINK_FC_PAUSE_SYM | 6062 BCE_NETLINK_FC_PAUSE_ASYM; 6063 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6064 advertise |= BCE_NETLINK_PHY_APP_REMOTE | 6065 BCE_NETLINK_ETH_AT_WIRESPEED; 6066 6067 return (advertise); 6068 } 6069 6070 /****************************************************************************/ 6071 /* Set media options. */ 6072 /* */ 6073 /* Returns: */ 6074 /* 0 for success, positive value for failure. */ 6075 /****************************************************************************/ 6076 static int 6077 bce_ifmedia_upd(struct ifnet *ifp) 6078 { 6079 struct bce_softc *sc = ifp->if_softc; 6080 int error; 6081 6082 DBENTER(BCE_VERBOSE); 6083 6084 BCE_LOCK(sc); 6085 error = bce_ifmedia_upd_locked(ifp); 6086 BCE_UNLOCK(sc); 6087 6088 DBEXIT(BCE_VERBOSE); 6089 return (error); 6090 } 6091 6092 /****************************************************************************/ 6093 /* Set media options. */ 6094 /* */ 6095 /* Returns: */ 6096 /* Nothing. */ 6097 /****************************************************************************/ 6098 static int 6099 bce_ifmedia_upd_locked(struct ifnet *ifp) 6100 { 6101 struct bce_softc *sc = ifp->if_softc; 6102 struct mii_data *mii; 6103 struct mii_softc *miisc; 6104 struct ifmedia *ifm; 6105 u32 link; 6106 int error, fdx; 6107 6108 DBENTER(BCE_VERBOSE_PHY); 6109 6110 error = 0; 6111 BCE_LOCK_ASSERT(sc); 6112 6113 sc->bce_link_up = FALSE; 6114 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6115 ifm = &sc->bce_ifmedia; 6116 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 6117 return (EINVAL); 6118 link = 0; 6119 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX; 6120 switch(IFM_SUBTYPE(ifm->ifm_media)) { 6121 case IFM_AUTO: 6122 /* 6123 * Check advertised link of remote PHY by reading 6124 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK. 6125 * Always use the same link type of remote PHY. 6126 */ 6127 link = bce_get_rphy_link(sc); 6128 break; 6129 case IFM_2500_SX: 6130 if ((sc->bce_phy_flags & 6131 (BCE_PHY_REMOTE_PORT_FIBER_FLAG | 6132 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0) 6133 return (EINVAL); 6134 /* 6135 * XXX 6136 * Have to enable forced 2.5Gbps configuration. 6137 */ 6138 if (fdx != 0) 6139 link |= BCE_NETLINK_SPEED_2500FULL; 6140 else 6141 link |= BCE_NETLINK_SPEED_2500HALF; 6142 break; 6143 case IFM_1000_SX: 6144 if ((sc->bce_phy_flags & 6145 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6146 return (EINVAL); 6147 /* 6148 * XXX 6149 * Have to disable 2.5Gbps configuration. 6150 */ 6151 if (fdx != 0) 6152 link = BCE_NETLINK_SPEED_1000FULL; 6153 else 6154 link = BCE_NETLINK_SPEED_1000HALF; 6155 break; 6156 case IFM_1000_T: 6157 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6158 return (EINVAL); 6159 if (fdx != 0) 6160 link = BCE_NETLINK_SPEED_1000FULL; 6161 else 6162 link = BCE_NETLINK_SPEED_1000HALF; 6163 break; 6164 case IFM_100_TX: 6165 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6166 return (EINVAL); 6167 if (fdx != 0) 6168 link = BCE_NETLINK_SPEED_100FULL; 6169 else 6170 link = BCE_NETLINK_SPEED_100HALF; 6171 break; 6172 case IFM_10_T: 6173 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6174 return (EINVAL); 6175 if (fdx != 0) 6176 link = BCE_NETLINK_SPEED_10FULL; 6177 else 6178 link = BCE_NETLINK_SPEED_10HALF; 6179 break; 6180 default: 6181 return (EINVAL); 6182 } 6183 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) { 6184 /* 6185 * XXX 6186 * Advertise pause capability for full-duplex media. 6187 */ 6188 if (fdx != 0) 6189 link |= BCE_NETLINK_FC_PAUSE_SYM | 6190 BCE_NETLINK_FC_PAUSE_ASYM; 6191 if ((sc->bce_phy_flags & 6192 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6193 link |= BCE_NETLINK_PHY_APP_REMOTE | 6194 BCE_NETLINK_ETH_AT_WIRESPEED; 6195 } 6196 6197 bce_shmem_wr(sc, BCE_MB_ARGS_0, link); 6198 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK); 6199 } else { 6200 mii = device_get_softc(sc->bce_miibus); 6201 6202 /* Make sure the MII bus has been enumerated. */ 6203 if (mii) { 6204 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6205 PHY_RESET(miisc); 6206 error = mii_mediachg(mii); 6207 } 6208 } 6209 6210 DBEXIT(BCE_VERBOSE_PHY); 6211 return (error); 6212 } 6213 6214 static void 6215 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr) 6216 { 6217 struct ifnet *ifp; 6218 u32 link; 6219 6220 ifp = sc->bce_ifp; 6221 BCE_LOCK_ASSERT(sc); 6222 6223 ifmr->ifm_status = IFM_AVALID; 6224 ifmr->ifm_active = IFM_ETHER; 6225 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 6226 /* XXX Handle heart beat status? */ 6227 if ((link & BCE_LINK_STATUS_LINK_UP) != 0) 6228 ifmr->ifm_status |= IFM_ACTIVE; 6229 else { 6230 ifmr->ifm_active |= IFM_NONE; 6231 ifp->if_baudrate = 0; 6232 return; 6233 } 6234 switch (link & BCE_LINK_STATUS_SPEED_MASK) { 6235 case BCE_LINK_STATUS_10HALF: 6236 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 6237 ifp->if_baudrate = IF_Mbps(10UL); 6238 break; 6239 case BCE_LINK_STATUS_10FULL: 6240 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 6241 ifp->if_baudrate = IF_Mbps(10UL); 6242 break; 6243 case BCE_LINK_STATUS_100HALF: 6244 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 6245 ifp->if_baudrate = IF_Mbps(100UL); 6246 break; 6247 case BCE_LINK_STATUS_100FULL: 6248 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 6249 ifp->if_baudrate = IF_Mbps(100UL); 6250 break; 6251 case BCE_LINK_STATUS_1000HALF: 6252 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6253 ifmr->ifm_active |= IFM_1000_T | IFM_HDX; 6254 else 6255 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX; 6256 ifp->if_baudrate = IF_Mbps(1000UL); 6257 break; 6258 case BCE_LINK_STATUS_1000FULL: 6259 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6260 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 6261 else 6262 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 6263 ifp->if_baudrate = IF_Mbps(1000UL); 6264 break; 6265 case BCE_LINK_STATUS_2500HALF: 6266 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6267 ifmr->ifm_active |= IFM_NONE; 6268 return; 6269 } else 6270 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX; 6271 ifp->if_baudrate = IF_Mbps(2500UL); 6272 break; 6273 case BCE_LINK_STATUS_2500FULL: 6274 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6275 ifmr->ifm_active |= IFM_NONE; 6276 return; 6277 } else 6278 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 6279 ifp->if_baudrate = IF_Mbps(2500UL); 6280 break; 6281 default: 6282 ifmr->ifm_active |= IFM_NONE; 6283 return; 6284 } 6285 6286 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0) 6287 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 6288 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0) 6289 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 6290 } 6291 6292 /****************************************************************************/ 6293 /* Reports current media status. */ 6294 /* */ 6295 /* Returns: */ 6296 /* Nothing. */ 6297 /****************************************************************************/ 6298 static void 6299 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6300 { 6301 struct bce_softc *sc = ifp->if_softc; 6302 struct mii_data *mii; 6303 6304 DBENTER(BCE_VERBOSE_PHY); 6305 6306 BCE_LOCK(sc); 6307 6308 if ((ifp->if_flags & IFF_UP) == 0) { 6309 BCE_UNLOCK(sc); 6310 return; 6311 } 6312 6313 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 6314 bce_ifmedia_sts_rphy(sc, ifmr); 6315 else { 6316 mii = device_get_softc(sc->bce_miibus); 6317 mii_pollstat(mii); 6318 ifmr->ifm_active = mii->mii_media_active; 6319 ifmr->ifm_status = mii->mii_media_status; 6320 } 6321 6322 BCE_UNLOCK(sc); 6323 6324 DBEXIT(BCE_VERBOSE_PHY); 6325 } 6326 6327 /****************************************************************************/ 6328 /* Handles PHY generated interrupt events. */ 6329 /* */ 6330 /* Returns: */ 6331 /* Nothing. */ 6332 /****************************************************************************/ 6333 static void 6334 bce_phy_intr(struct bce_softc *sc) 6335 { 6336 u32 new_link_state, old_link_state; 6337 6338 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6339 6340 DBRUN(sc->phy_interrupts++); 6341 6342 new_link_state = sc->status_block->status_attn_bits & 6343 STATUS_ATTN_BITS_LINK_STATE; 6344 old_link_state = sc->status_block->status_attn_bits_ack & 6345 STATUS_ATTN_BITS_LINK_STATE; 6346 6347 /* Handle any changes if the link state has changed. */ 6348 if (new_link_state != old_link_state) { 6349 /* Update the status_attn_bits_ack field. */ 6350 if (new_link_state) { 6351 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6352 STATUS_ATTN_BITS_LINK_STATE); 6353 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6354 __FUNCTION__); 6355 } else { 6356 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6357 STATUS_ATTN_BITS_LINK_STATE); 6358 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6359 __FUNCTION__); 6360 } 6361 6362 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6363 if (new_link_state) { 6364 if (bootverbose) 6365 if_printf(sc->bce_ifp, "link UP\n"); 6366 if_link_state_change(sc->bce_ifp, 6367 LINK_STATE_UP); 6368 } else { 6369 if (bootverbose) 6370 if_printf(sc->bce_ifp, "link DOWN\n"); 6371 if_link_state_change(sc->bce_ifp, 6372 LINK_STATE_DOWN); 6373 } 6374 } 6375 /* 6376 * Assume link is down and allow 6377 * tick routine to update the state 6378 * based on the actual media state. 6379 */ 6380 sc->bce_link_up = FALSE; 6381 callout_stop(&sc->bce_tick_callout); 6382 bce_tick(sc); 6383 } 6384 6385 /* Acknowledge the link change interrupt. */ 6386 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6387 6388 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6389 } 6390 6391 /****************************************************************************/ 6392 /* Reads the receive consumer value from the status block (skipping over */ 6393 /* chain page pointer if necessary). */ 6394 /* */ 6395 /* Returns: */ 6396 /* hw_cons */ 6397 /****************************************************************************/ 6398 static inline u16 6399 bce_get_hw_rx_cons(struct bce_softc *sc) 6400 { 6401 u16 hw_cons; 6402 6403 rmb(); 6404 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6405 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6406 hw_cons++; 6407 6408 return hw_cons; 6409 } 6410 6411 /****************************************************************************/ 6412 /* Handles received frame interrupt events. */ 6413 /* */ 6414 /* Returns: */ 6415 /* Nothing. */ 6416 /****************************************************************************/ 6417 static void 6418 bce_rx_intr(struct bce_softc *sc) 6419 { 6420 struct ifnet *ifp = sc->bce_ifp; 6421 struct l2_fhdr *l2fhdr; 6422 struct ether_vlan_header *vh; 6423 unsigned int pkt_len; 6424 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6425 u32 status; 6426 unsigned int rem_len; 6427 u16 sw_pg_cons, sw_pg_cons_idx; 6428 6429 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6430 DBRUN(sc->interrupts_rx++); 6431 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6432 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6433 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6434 6435 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6436 for (int i = 0; i < sc->rx_pages; i++) 6437 bus_dmamap_sync(sc->rx_bd_chain_tag, 6438 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6439 6440 /* Prepare the page chain pages to be accessed by the host CPU. */ 6441 if (bce_hdr_split == TRUE) { 6442 for (int i = 0; i < sc->pg_pages; i++) 6443 bus_dmamap_sync(sc->pg_bd_chain_tag, 6444 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6445 } 6446 6447 /* Get the hardware's view of the RX consumer index. */ 6448 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6449 6450 /* Get working copies of the driver's view of the consumer indices. */ 6451 sw_rx_cons = sc->rx_cons; 6452 sw_pg_cons = sc->pg_cons; 6453 6454 /* Update some debug statistics counters */ 6455 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6456 sc->rx_low_watermark = sc->free_rx_bd); 6457 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6458 sc->rx_empty_count++); 6459 6460 /* Scan through the receive chain as long as there is work to do */ 6461 /* ToDo: Consider setting a limit on the number of packets processed. */ 6462 rmb(); 6463 while (sw_rx_cons != hw_rx_cons) { 6464 struct mbuf *m0; 6465 6466 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6467 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6468 6469 /* Unmap the mbuf from DMA space. */ 6470 bus_dmamap_sync(sc->rx_mbuf_tag, 6471 sc->rx_mbuf_map[sw_rx_cons_idx], 6472 BUS_DMASYNC_POSTREAD); 6473 bus_dmamap_unload(sc->rx_mbuf_tag, 6474 sc->rx_mbuf_map[sw_rx_cons_idx]); 6475 6476 /* Remove the mbuf from the RX chain. */ 6477 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6478 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6479 DBRUN(sc->debug_rx_mbuf_alloc--); 6480 sc->free_rx_bd++; 6481 6482 /* 6483 * Frames received on the NetXteme II are prepended 6484 * with an l2_fhdr structure which provides status 6485 * information about the received frame (including 6486 * VLAN tags and checksum info). The frames are 6487 * also automatically adjusted to word align the IP 6488 * header (i.e. two null bytes are inserted before 6489 * the Ethernet header). As a result the data 6490 * DMA'd by the controller into the mbuf looks 6491 * like this: 6492 * 6493 * +---------+-----+---------------------+-----+ 6494 * | l2_fhdr | pad | packet data | FCS | 6495 * +---------+-----+---------------------+-----+ 6496 * 6497 * The l2_fhdr needs to be checked and skipped and 6498 * the FCS needs to be stripped before sending the 6499 * packet up the stack. 6500 */ 6501 l2fhdr = mtod(m0, struct l2_fhdr *); 6502 6503 /* Get the packet data + FCS length and the status. */ 6504 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6505 status = l2fhdr->l2_fhdr_status; 6506 6507 /* 6508 * Skip over the l2_fhdr and pad, resulting in the 6509 * following data in the mbuf: 6510 * +---------------------+-----+ 6511 * | packet data | FCS | 6512 * +---------------------+-----+ 6513 */ 6514 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6515 6516 /* 6517 * When split header mode is used, an ethernet frame 6518 * may be split across the receive chain and the 6519 * page chain. If that occurs an mbuf cluster must be 6520 * reassembled from the individual mbuf pieces. 6521 */ 6522 if (bce_hdr_split == TRUE) { 6523 /* 6524 * Check whether the received frame fits in a single 6525 * mbuf or not (i.e. packet data + FCS <= 6526 * sc->rx_bd_mbuf_data_len bytes). 6527 */ 6528 if (pkt_len > m0->m_len) { 6529 /* 6530 * The received frame is larger than a single mbuf. 6531 * If the frame was a TCP frame then only the TCP 6532 * header is placed in the mbuf, the remaining 6533 * payload (including FCS) is placed in the page 6534 * chain, the SPLIT flag is set, and the header 6535 * length is placed in the IP checksum field. 6536 * If the frame is not a TCP frame then the mbuf 6537 * is filled and the remaining bytes are placed 6538 * in the page chain. 6539 */ 6540 6541 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6542 "packet.\n", __FUNCTION__); 6543 DBRUN(sc->split_header_frames_rcvd++); 6544 6545 /* 6546 * When the page chain is enabled and the TCP 6547 * header has been split from the TCP payload, 6548 * the ip_xsum structure will reflect the length 6549 * of the TCP header, not the IP checksum. Set 6550 * the packet length of the mbuf accordingly. 6551 */ 6552 if (status & L2_FHDR_STATUS_SPLIT) { 6553 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6554 DBRUN(sc->split_header_tcp_frames_rcvd++); 6555 } 6556 6557 rem_len = pkt_len - m0->m_len; 6558 6559 /* Pull mbufs off the page chain for any remaining data. */ 6560 while (rem_len > 0) { 6561 struct mbuf *m_pg; 6562 6563 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6564 6565 /* Remove the mbuf from the page chain. */ 6566 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6567 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6568 DBRUN(sc->debug_pg_mbuf_alloc--); 6569 sc->free_pg_bd++; 6570 6571 /* Unmap the page chain mbuf from DMA space. */ 6572 bus_dmamap_sync(sc->pg_mbuf_tag, 6573 sc->pg_mbuf_map[sw_pg_cons_idx], 6574 BUS_DMASYNC_POSTREAD); 6575 bus_dmamap_unload(sc->pg_mbuf_tag, 6576 sc->pg_mbuf_map[sw_pg_cons_idx]); 6577 6578 /* Adjust the mbuf length. */ 6579 if (rem_len < m_pg->m_len) { 6580 /* The mbuf chain is complete. */ 6581 m_pg->m_len = rem_len; 6582 rem_len = 0; 6583 } else { 6584 /* More packet data is waiting. */ 6585 rem_len -= m_pg->m_len; 6586 } 6587 6588 /* Concatenate the mbuf cluster to the mbuf. */ 6589 m_cat(m0, m_pg); 6590 6591 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6592 } 6593 6594 /* Set the total packet length. */ 6595 m0->m_pkthdr.len = pkt_len; 6596 6597 } else { 6598 /* 6599 * The received packet is small and fits in a 6600 * single mbuf (i.e. the l2_fhdr + pad + packet + 6601 * FCS <= MHLEN). In other words, the packet is 6602 * 154 bytes or less in size. 6603 */ 6604 6605 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6606 "packet.\n", __FUNCTION__); 6607 6608 /* Set the total packet length. */ 6609 m0->m_pkthdr.len = m0->m_len = pkt_len; 6610 } 6611 } else 6612 /* Set the total packet length. */ 6613 m0->m_pkthdr.len = m0->m_len = pkt_len; 6614 6615 /* Remove the trailing Ethernet FCS. */ 6616 m_adj(m0, -ETHER_CRC_LEN); 6617 6618 /* Check that the resulting mbuf chain is valid. */ 6619 DBRUN(m_sanity(m0, FALSE)); 6620 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6621 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6622 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6623 m_print(m0, 128)); 6624 6625 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6626 sc->l2fhdr_error_sim_count++; 6627 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6628 6629 /* Check the received frame for errors. */ 6630 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6631 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6632 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6633 /* Log the error and release the mbuf. */ 6634 sc->l2fhdr_error_count++; 6635 m_freem(m0); 6636 m0 = NULL; 6637 goto bce_rx_intr_next_rx; 6638 } 6639 6640 /* Send the packet to the appropriate interface. */ 6641 m0->m_pkthdr.rcvif = ifp; 6642 6643 /* Assume no hardware checksum. */ 6644 m0->m_pkthdr.csum_flags = 0; 6645 6646 /* Validate the checksum if offload enabled. */ 6647 if (ifp->if_capenable & IFCAP_RXCSUM) { 6648 /* Check for an IP datagram. */ 6649 if (!(status & L2_FHDR_STATUS_SPLIT) && 6650 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6651 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6652 DBRUN(sc->csum_offload_ip++); 6653 /* Check if the IP checksum is valid. */ 6654 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6655 m0->m_pkthdr.csum_flags |= 6656 CSUM_IP_VALID; 6657 } 6658 6659 /* Check for a valid TCP/UDP frame. */ 6660 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6661 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6662 /* Check for a good TCP/UDP checksum. */ 6663 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6664 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6665 DBRUN(sc->csum_offload_tcp_udp++); 6666 m0->m_pkthdr.csum_data = 6667 l2fhdr->l2_fhdr_tcp_udp_xsum; 6668 m0->m_pkthdr.csum_flags |= 6669 (CSUM_DATA_VALID 6670 | CSUM_PSEUDO_HDR); 6671 } 6672 } 6673 } 6674 6675 /* Attach the VLAN tag. */ 6676 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 6677 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 6678 DBRUN(sc->vlan_tagged_frames_rcvd++); 6679 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6680 DBRUN(sc->vlan_tagged_frames_stripped++); 6681 m0->m_pkthdr.ether_vtag = 6682 l2fhdr->l2_fhdr_vlan_tag; 6683 m0->m_flags |= M_VLANTAG; 6684 } else { 6685 /* 6686 * bce(4) controllers can't disable VLAN 6687 * tag stripping if management firmware 6688 * (ASF/IPMI/UMP) is running. So we always 6689 * strip VLAN tag and manually reconstruct 6690 * the VLAN frame by appending stripped 6691 * VLAN tag in driver if VLAN tag stripping 6692 * was disabled. 6693 * 6694 * TODO: LLC SNAP handling. 6695 */ 6696 bcopy(mtod(m0, uint8_t *), 6697 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6698 ETHER_ADDR_LEN * 2); 6699 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6700 vh = mtod(m0, struct ether_vlan_header *); 6701 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6702 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6703 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6704 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6705 } 6706 } 6707 6708 /* Increment received packet statistics. */ 6709 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 6710 6711 bce_rx_intr_next_rx: 6712 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6713 6714 /* If we have a packet, pass it up the stack */ 6715 if (m0) { 6716 /* Make sure we don't lose our place when we release the lock. */ 6717 sc->rx_cons = sw_rx_cons; 6718 sc->pg_cons = sw_pg_cons; 6719 6720 BCE_UNLOCK(sc); 6721 (*ifp->if_input)(ifp, m0); 6722 BCE_LOCK(sc); 6723 6724 /* Recover our place. */ 6725 sw_rx_cons = sc->rx_cons; 6726 sw_pg_cons = sc->pg_cons; 6727 } 6728 6729 /* Refresh hw_cons to see if there's new work */ 6730 if (sw_rx_cons == hw_rx_cons) 6731 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6732 } 6733 6734 /* No new packets. Refill the page chain. */ 6735 if (bce_hdr_split == TRUE) { 6736 sc->pg_cons = sw_pg_cons; 6737 bce_fill_pg_chain(sc); 6738 } 6739 6740 /* No new packets. Refill the RX chain. */ 6741 sc->rx_cons = sw_rx_cons; 6742 bce_fill_rx_chain(sc); 6743 6744 /* Prepare the page chain pages to be accessed by the NIC. */ 6745 for (int i = 0; i < sc->rx_pages; i++) 6746 bus_dmamap_sync(sc->rx_bd_chain_tag, 6747 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6748 6749 if (bce_hdr_split == TRUE) { 6750 for (int i = 0; i < sc->pg_pages; i++) 6751 bus_dmamap_sync(sc->pg_bd_chain_tag, 6752 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6753 } 6754 6755 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6756 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6757 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6758 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6759 } 6760 6761 /****************************************************************************/ 6762 /* Reads the transmit consumer value from the status block (skipping over */ 6763 /* chain page pointer if necessary). */ 6764 /* */ 6765 /* Returns: */ 6766 /* hw_cons */ 6767 /****************************************************************************/ 6768 static inline u16 6769 bce_get_hw_tx_cons(struct bce_softc *sc) 6770 { 6771 u16 hw_cons; 6772 6773 mb(); 6774 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6775 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6776 hw_cons++; 6777 6778 return hw_cons; 6779 } 6780 6781 /****************************************************************************/ 6782 /* Handles transmit completion interrupt events. */ 6783 /* */ 6784 /* Returns: */ 6785 /* Nothing. */ 6786 /****************************************************************************/ 6787 static void 6788 bce_tx_intr(struct bce_softc *sc) 6789 { 6790 struct ifnet *ifp = sc->bce_ifp; 6791 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6792 6793 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6794 DBRUN(sc->interrupts_tx++); 6795 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6796 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6797 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6798 6799 BCE_LOCK_ASSERT(sc); 6800 6801 /* Get the hardware's view of the TX consumer index. */ 6802 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6803 sw_tx_cons = sc->tx_cons; 6804 6805 /* Prevent speculative reads of the status block. */ 6806 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6807 BUS_SPACE_BARRIER_READ); 6808 6809 /* Cycle through any completed TX chain page entries. */ 6810 while (sw_tx_cons != hw_tx_cons) { 6811 #ifdef BCE_DEBUG 6812 struct tx_bd *txbd = NULL; 6813 #endif 6814 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6815 6816 DBPRINT(sc, BCE_INFO_SEND, 6817 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6818 "sw_tx_chain_cons = 0x%04X\n", 6819 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6820 6821 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6822 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6823 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6824 (int) MAX_TX_BD_ALLOC); 6825 bce_breakpoint(sc)); 6826 6827 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6828 [TX_IDX(sw_tx_chain_cons)]); 6829 6830 DBRUNIF((txbd == NULL), 6831 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6832 __FILE__, __LINE__, sw_tx_chain_cons); 6833 bce_breakpoint(sc)); 6834 6835 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6836 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6837 6838 /* 6839 * Free the associated mbuf. Remember 6840 * that only the last tx_bd of a packet 6841 * has an mbuf pointer and DMA map. 6842 */ 6843 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6844 /* Validate that this is the last tx_bd. */ 6845 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6846 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6847 "txmbuf == NULL!\n", __FILE__, __LINE__); 6848 bce_breakpoint(sc)); 6849 6850 DBRUNMSG(BCE_INFO_SEND, 6851 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6852 "from tx_bd[0x%04X]\n", __FUNCTION__, 6853 sw_tx_chain_cons)); 6854 6855 /* Unmap the mbuf. */ 6856 bus_dmamap_unload(sc->tx_mbuf_tag, 6857 sc->tx_mbuf_map[sw_tx_chain_cons]); 6858 6859 /* Free the mbuf. */ 6860 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6861 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6862 DBRUN(sc->debug_tx_mbuf_alloc--); 6863 6864 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 6865 } 6866 6867 sc->used_tx_bd--; 6868 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6869 6870 /* Refresh hw_cons to see if there's new work. */ 6871 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6872 6873 /* Prevent speculative reads of the status block. */ 6874 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6875 BUS_SPACE_BARRIER_READ); 6876 } 6877 6878 /* Clear the TX timeout timer. */ 6879 sc->watchdog_timer = 0; 6880 6881 /* Clear the tx hardware queue full flag. */ 6882 if (sc->used_tx_bd < sc->max_tx_bd) { 6883 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6884 DBPRINT(sc, BCE_INFO_SEND, 6885 "%s(): Open TX chain! %d/%d (used/total)\n", 6886 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6887 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6888 } 6889 6890 sc->tx_cons = sw_tx_cons; 6891 6892 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6893 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6894 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6895 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6896 } 6897 6898 /****************************************************************************/ 6899 /* Disables interrupt generation. */ 6900 /* */ 6901 /* Returns: */ 6902 /* Nothing. */ 6903 /****************************************************************************/ 6904 static void 6905 bce_disable_intr(struct bce_softc *sc) 6906 { 6907 DBENTER(BCE_VERBOSE_INTR); 6908 6909 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6910 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6911 6912 DBEXIT(BCE_VERBOSE_INTR); 6913 } 6914 6915 /****************************************************************************/ 6916 /* Enables interrupt generation. */ 6917 /* */ 6918 /* Returns: */ 6919 /* Nothing. */ 6920 /****************************************************************************/ 6921 static void 6922 bce_enable_intr(struct bce_softc *sc, int coal_now) 6923 { 6924 DBENTER(BCE_VERBOSE_INTR); 6925 6926 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6927 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6928 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6929 6930 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6931 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6932 6933 /* Force an immediate interrupt (whether there is new data or not). */ 6934 if (coal_now) 6935 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6936 6937 DBEXIT(BCE_VERBOSE_INTR); 6938 } 6939 6940 /****************************************************************************/ 6941 /* Handles controller initialization. */ 6942 /* */ 6943 /* Returns: */ 6944 /* Nothing. */ 6945 /****************************************************************************/ 6946 static void 6947 bce_init_locked(struct bce_softc *sc) 6948 { 6949 struct ifnet *ifp; 6950 u32 ether_mtu = 0; 6951 6952 DBENTER(BCE_VERBOSE_RESET); 6953 6954 BCE_LOCK_ASSERT(sc); 6955 6956 ifp = sc->bce_ifp; 6957 6958 /* Check if the driver is still running and bail out if it is. */ 6959 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6960 goto bce_init_locked_exit; 6961 6962 bce_stop(sc); 6963 6964 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6965 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6966 __FILE__, __LINE__); 6967 goto bce_init_locked_exit; 6968 } 6969 6970 if (bce_chipinit(sc)) { 6971 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6972 __FILE__, __LINE__); 6973 goto bce_init_locked_exit; 6974 } 6975 6976 if (bce_blockinit(sc)) { 6977 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6978 __FILE__, __LINE__); 6979 goto bce_init_locked_exit; 6980 } 6981 6982 /* Load our MAC address. */ 6983 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6984 bce_set_mac_addr(sc); 6985 6986 if (bce_hdr_split == FALSE) 6987 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 6988 /* 6989 * Calculate and program the hardware Ethernet MTU 6990 * size. Be generous on the receive if we have room 6991 * and allowed by the user. 6992 */ 6993 if (bce_strict_rx_mtu == TRUE) 6994 ether_mtu = ifp->if_mtu; 6995 else { 6996 if (bce_hdr_split == TRUE) { 6997 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES) 6998 ether_mtu = sc->rx_bd_mbuf_data_len + 6999 MCLBYTES; 7000 else 7001 ether_mtu = ifp->if_mtu; 7002 } else { 7003 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 7004 ether_mtu = sc->rx_bd_mbuf_data_len; 7005 else 7006 ether_mtu = ifp->if_mtu; 7007 } 7008 } 7009 7010 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 7011 7012 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 7013 __FUNCTION__, ether_mtu); 7014 7015 /* Program the mtu, enabling jumbo frame support if necessary. */ 7016 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 7017 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 7018 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 7019 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 7020 else 7021 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 7022 7023 /* Program appropriate promiscuous/multicast filtering. */ 7024 bce_set_rx_mode(sc); 7025 7026 if (bce_hdr_split == TRUE) { 7027 /* Init page buffer descriptor chain. */ 7028 bce_init_pg_chain(sc); 7029 } 7030 7031 /* Init RX buffer descriptor chain. */ 7032 bce_init_rx_chain(sc); 7033 7034 /* Init TX buffer descriptor chain. */ 7035 bce_init_tx_chain(sc); 7036 7037 /* Enable host interrupts. */ 7038 bce_enable_intr(sc, 1); 7039 7040 bce_ifmedia_upd_locked(ifp); 7041 7042 /* Let the OS know the driver is up and running. */ 7043 ifp->if_drv_flags |= IFF_DRV_RUNNING; 7044 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7045 7046 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7047 7048 bce_init_locked_exit: 7049 DBEXIT(BCE_VERBOSE_RESET); 7050 } 7051 7052 /****************************************************************************/ 7053 /* Initialize the controller just enough so that any management firmware */ 7054 /* running on the device will continue to operate correctly. */ 7055 /* */ 7056 /* Returns: */ 7057 /* Nothing. */ 7058 /****************************************************************************/ 7059 static void 7060 bce_mgmt_init_locked(struct bce_softc *sc) 7061 { 7062 struct ifnet *ifp; 7063 7064 DBENTER(BCE_VERBOSE_RESET); 7065 7066 BCE_LOCK_ASSERT(sc); 7067 7068 /* Bail out if management firmware is not running. */ 7069 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 7070 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 7071 "No management firmware running...\n"); 7072 goto bce_mgmt_init_locked_exit; 7073 } 7074 7075 ifp = sc->bce_ifp; 7076 7077 /* Enable all critical blocks in the MAC. */ 7078 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 7079 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 7080 DELAY(20); 7081 7082 bce_ifmedia_upd_locked(ifp); 7083 7084 bce_mgmt_init_locked_exit: 7085 DBEXIT(BCE_VERBOSE_RESET); 7086 } 7087 7088 /****************************************************************************/ 7089 /* Handles controller initialization when called from an unlocked routine. */ 7090 /* */ 7091 /* Returns: */ 7092 /* Nothing. */ 7093 /****************************************************************************/ 7094 static void 7095 bce_init(void *xsc) 7096 { 7097 struct bce_softc *sc = xsc; 7098 7099 DBENTER(BCE_VERBOSE_RESET); 7100 7101 BCE_LOCK(sc); 7102 bce_init_locked(sc); 7103 BCE_UNLOCK(sc); 7104 7105 DBEXIT(BCE_VERBOSE_RESET); 7106 } 7107 7108 /****************************************************************************/ 7109 /* Modifies an mbuf for TSO on the hardware. */ 7110 /* */ 7111 /* Returns: */ 7112 /* Pointer to a modified mbuf. */ 7113 /****************************************************************************/ 7114 static struct mbuf * 7115 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7116 { 7117 struct mbuf *m; 7118 struct ether_header *eh; 7119 struct ip *ip; 7120 struct tcphdr *th; 7121 u16 etype; 7122 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 7123 7124 DBRUN(sc->tso_frames_requested++); 7125 7126 /* Controller may modify mbuf chains. */ 7127 if (M_WRITABLE(*m_head) == 0) { 7128 m = m_dup(*m_head, M_NOWAIT); 7129 m_freem(*m_head); 7130 if (m == NULL) { 7131 sc->mbuf_alloc_failed_count++; 7132 *m_head = NULL; 7133 return (NULL); 7134 } 7135 *m_head = m; 7136 } 7137 7138 /* 7139 * For TSO the controller needs two pieces of info, 7140 * the MSS and the IP+TCP options length. 7141 */ 7142 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7143 if (m == NULL) { 7144 *m_head = NULL; 7145 return (NULL); 7146 } 7147 eh = mtod(m, struct ether_header *); 7148 etype = ntohs(eh->ether_type); 7149 7150 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7151 switch (etype) { 7152 case ETHERTYPE_IP: 7153 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7154 /* TSO only supported for TCP protocol. */ 7155 if (ip->ip_p != IPPROTO_TCP) { 7156 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7157 __FILE__, __LINE__); 7158 m_freem(*m_head); 7159 *m_head = NULL; 7160 return (NULL); 7161 } 7162 7163 /* Get IP header length in bytes (min 20) */ 7164 ip_hlen = ip->ip_hl << 2; 7165 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7166 sizeof(struct tcphdr)); 7167 if (m == NULL) { 7168 *m_head = NULL; 7169 return (NULL); 7170 } 7171 7172 /* Get the TCP header length in bytes (min 20) */ 7173 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7174 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7175 tcp_hlen = (th->th_off << 2); 7176 7177 /* Make sure all IP/TCP options live in the same buffer. */ 7178 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7179 tcp_hlen); 7180 if (m == NULL) { 7181 *m_head = NULL; 7182 return (NULL); 7183 } 7184 7185 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7186 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7187 ip_len = ip->ip_len; 7188 ip->ip_len = 0; 7189 ip->ip_sum = 0; 7190 break; 7191 case ETHERTYPE_IPV6: 7192 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7193 __FILE__, __LINE__); 7194 m_freem(*m_head); 7195 *m_head = NULL; 7196 return (NULL); 7197 /* NOT REACHED */ 7198 default: 7199 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7200 __FILE__, __LINE__); 7201 m_freem(*m_head); 7202 *m_head = NULL; 7203 return (NULL); 7204 } 7205 7206 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7207 7208 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7209 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7210 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7211 tcp_hlen, ip_len); 7212 7213 /* Set the LSO flag in the TX BD */ 7214 *flags |= TX_BD_FLAGS_SW_LSO; 7215 7216 /* Set the length of IP + TCP options (in 32 bit words) */ 7217 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7218 sizeof(struct tcphdr)) >> 2) << 8); 7219 7220 DBRUN(sc->tso_frames_completed++); 7221 return (*m_head); 7222 } 7223 7224 /****************************************************************************/ 7225 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7226 /* memory visible to the controller. */ 7227 /* */ 7228 /* Returns: */ 7229 /* 0 for success, positive value for failure. */ 7230 /* Modified: */ 7231 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7232 /****************************************************************************/ 7233 static int 7234 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7235 { 7236 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7237 bus_dmamap_t map; 7238 struct tx_bd *txbd = NULL; 7239 struct mbuf *m0; 7240 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7241 u32 prod_bseq; 7242 7243 #ifdef BCE_DEBUG 7244 u16 debug_prod; 7245 #endif 7246 7247 int i, error, nsegs, rc = 0; 7248 7249 DBENTER(BCE_VERBOSE_SEND); 7250 7251 /* Make sure we have room in the TX chain. */ 7252 if (sc->used_tx_bd >= sc->max_tx_bd) 7253 goto bce_tx_encap_exit; 7254 7255 /* Transfer any checksum offload flags to the bd. */ 7256 m0 = *m_head; 7257 if (m0->m_pkthdr.csum_flags) { 7258 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7259 m0 = bce_tso_setup(sc, m_head, &flags); 7260 if (m0 == NULL) { 7261 DBRUN(sc->tso_frames_failed++); 7262 goto bce_tx_encap_exit; 7263 } 7264 mss = htole16(m0->m_pkthdr.tso_segsz); 7265 } else { 7266 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7267 flags |= TX_BD_FLAGS_IP_CKSUM; 7268 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7269 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7270 } 7271 } 7272 7273 /* Transfer any VLAN tags to the bd. */ 7274 if (m0->m_flags & M_VLANTAG) { 7275 flags |= TX_BD_FLAGS_VLAN_TAG; 7276 vlan_tag = m0->m_pkthdr.ether_vtag; 7277 } 7278 7279 /* Map the mbuf into DMAable memory. */ 7280 prod = sc->tx_prod; 7281 chain_prod = TX_CHAIN_IDX(prod); 7282 map = sc->tx_mbuf_map[chain_prod]; 7283 7284 /* Map the mbuf into our DMA address space. */ 7285 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7286 segs, &nsegs, BUS_DMA_NOWAIT); 7287 7288 /* Check if the DMA mapping was successful */ 7289 if (error == EFBIG) { 7290 sc->mbuf_frag_count++; 7291 7292 /* Try to defrag the mbuf. */ 7293 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS); 7294 if (m0 == NULL) { 7295 /* Defrag was unsuccessful */ 7296 m_freem(*m_head); 7297 *m_head = NULL; 7298 sc->mbuf_alloc_failed_count++; 7299 rc = ENOBUFS; 7300 goto bce_tx_encap_exit; 7301 } 7302 7303 /* Defrag was successful, try mapping again */ 7304 *m_head = m0; 7305 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7306 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7307 7308 /* Still getting an error after a defrag. */ 7309 if (error == ENOMEM) { 7310 /* Insufficient DMA buffers available. */ 7311 sc->dma_map_addr_tx_failed_count++; 7312 rc = error; 7313 goto bce_tx_encap_exit; 7314 } else if (error != 0) { 7315 /* Release it and return an error. */ 7316 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7317 "TX chain!\n", __FILE__, __LINE__); 7318 m_freem(m0); 7319 *m_head = NULL; 7320 sc->dma_map_addr_tx_failed_count++; 7321 rc = ENOBUFS; 7322 goto bce_tx_encap_exit; 7323 } 7324 } else if (error == ENOMEM) { 7325 /* Insufficient DMA buffers available. */ 7326 sc->dma_map_addr_tx_failed_count++; 7327 rc = error; 7328 goto bce_tx_encap_exit; 7329 } else if (error != 0) { 7330 m_freem(m0); 7331 *m_head = NULL; 7332 sc->dma_map_addr_tx_failed_count++; 7333 rc = error; 7334 goto bce_tx_encap_exit; 7335 } 7336 7337 /* Make sure there's room in the chain */ 7338 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7339 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7340 rc = ENOBUFS; 7341 goto bce_tx_encap_exit; 7342 } 7343 7344 /* prod points to an empty tx_bd at this point. */ 7345 prod_bseq = sc->tx_prod_bseq; 7346 7347 #ifdef BCE_DEBUG 7348 debug_prod = chain_prod; 7349 #endif 7350 7351 DBPRINT(sc, BCE_INFO_SEND, 7352 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7353 "prod_bseq = 0x%08X\n", 7354 __FUNCTION__, prod, chain_prod, prod_bseq); 7355 7356 /* 7357 * Cycle through each mbuf segment that makes up 7358 * the outgoing frame, gathering the mapping info 7359 * for that segment and creating a tx_bd for 7360 * the mbuf. 7361 */ 7362 for (i = 0; i < nsegs ; i++) { 7363 chain_prod = TX_CHAIN_IDX(prod); 7364 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7365 [TX_IDX(chain_prod)]; 7366 7367 txbd->tx_bd_haddr_lo = 7368 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7369 txbd->tx_bd_haddr_hi = 7370 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7371 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7372 htole16(segs[i].ds_len); 7373 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7374 txbd->tx_bd_flags = htole16(flags); 7375 prod_bseq += segs[i].ds_len; 7376 if (i == 0) 7377 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7378 prod = NEXT_TX_BD(prod); 7379 } 7380 7381 /* Set the END flag on the last TX buffer descriptor. */ 7382 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7383 7384 DBRUNMSG(BCE_EXTREME_SEND, 7385 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7386 7387 /* 7388 * Ensure that the mbuf pointer for this transmission 7389 * is placed at the array index of the last 7390 * descriptor in this chain. This is done 7391 * because a single map is used for all 7392 * segments of the mbuf and we don't want to 7393 * unload the map before all of the segments 7394 * have been freed. 7395 */ 7396 sc->tx_mbuf_ptr[chain_prod] = m0; 7397 sc->used_tx_bd += nsegs; 7398 7399 /* Update some debug statistic counters */ 7400 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7401 sc->tx_hi_watermark = sc->used_tx_bd); 7402 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7403 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7404 7405 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7406 7407 /* prod points to the next free tx_bd at this point. */ 7408 sc->tx_prod = prod; 7409 sc->tx_prod_bseq = prod_bseq; 7410 7411 /* Tell the chip about the waiting TX frames. */ 7412 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7413 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7414 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7415 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7416 7417 bce_tx_encap_exit: 7418 DBEXIT(BCE_VERBOSE_SEND); 7419 return(rc); 7420 } 7421 7422 /****************************************************************************/ 7423 /* Main transmit routine when called from another routine with a lock. */ 7424 /* */ 7425 /* Returns: */ 7426 /* Nothing. */ 7427 /****************************************************************************/ 7428 static void 7429 bce_start_locked(struct ifnet *ifp) 7430 { 7431 struct bce_softc *sc = ifp->if_softc; 7432 struct mbuf *m_head = NULL; 7433 int count = 0; 7434 u16 tx_prod, tx_chain_prod; 7435 7436 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7437 7438 BCE_LOCK_ASSERT(sc); 7439 7440 /* prod points to the next free tx_bd. */ 7441 tx_prod = sc->tx_prod; 7442 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7443 7444 DBPRINT(sc, BCE_INFO_SEND, 7445 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7446 "tx_prod_bseq = 0x%08X\n", 7447 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7448 7449 /* If there's no link or the transmit queue is empty then just exit. */ 7450 if (sc->bce_link_up == FALSE) { 7451 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7452 __FUNCTION__); 7453 goto bce_start_locked_exit; 7454 } 7455 7456 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7457 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7458 __FUNCTION__); 7459 goto bce_start_locked_exit; 7460 } 7461 7462 /* 7463 * Keep adding entries while there is space in the ring. 7464 */ 7465 while (sc->used_tx_bd < sc->max_tx_bd) { 7466 /* Check for any frames to send. */ 7467 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7468 7469 /* Stop when the transmit queue is empty. */ 7470 if (m_head == NULL) 7471 break; 7472 7473 /* 7474 * Pack the data into the transmit ring. If we 7475 * don't have room, place the mbuf back at the 7476 * head of the queue and set the OACTIVE flag 7477 * to wait for the NIC to drain the chain. 7478 */ 7479 if (bce_tx_encap(sc, &m_head)) { 7480 if (m_head != NULL) 7481 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7482 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7483 DBPRINT(sc, BCE_INFO_SEND, 7484 "TX chain is closed for business! Total " 7485 "tx_bd used = %d\n", sc->used_tx_bd); 7486 break; 7487 } 7488 7489 count++; 7490 7491 /* Send a copy of the frame to any BPF listeners. */ 7492 ETHER_BPF_MTAP(ifp, m_head); 7493 } 7494 7495 /* Exit if no packets were dequeued. */ 7496 if (count == 0) { 7497 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7498 "dequeued\n", __FUNCTION__); 7499 goto bce_start_locked_exit; 7500 } 7501 7502 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7503 "send queue.\n", __FUNCTION__, count); 7504 7505 /* Set the tx timeout. */ 7506 sc->watchdog_timer = BCE_TX_TIMEOUT; 7507 7508 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7509 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7510 7511 bce_start_locked_exit: 7512 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7513 } 7514 7515 /****************************************************************************/ 7516 /* Main transmit routine when called from another routine without a lock. */ 7517 /* */ 7518 /* Returns: */ 7519 /* Nothing. */ 7520 /****************************************************************************/ 7521 static void 7522 bce_start(struct ifnet *ifp) 7523 { 7524 struct bce_softc *sc = ifp->if_softc; 7525 7526 DBENTER(BCE_VERBOSE_SEND); 7527 7528 BCE_LOCK(sc); 7529 bce_start_locked(ifp); 7530 BCE_UNLOCK(sc); 7531 7532 DBEXIT(BCE_VERBOSE_SEND); 7533 } 7534 7535 /****************************************************************************/ 7536 /* Handles any IOCTL calls from the operating system. */ 7537 /* */ 7538 /* Returns: */ 7539 /* 0 for success, positive value for failure. */ 7540 /****************************************************************************/ 7541 static int 7542 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7543 { 7544 struct bce_softc *sc = ifp->if_softc; 7545 struct ifreq *ifr = (struct ifreq *) data; 7546 struct mii_data *mii; 7547 int mask, error = 0; 7548 7549 DBENTER(BCE_VERBOSE_MISC); 7550 7551 switch(command) { 7552 /* Set the interface MTU. */ 7553 case SIOCSIFMTU: 7554 /* Check that the MTU setting is supported. */ 7555 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7556 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7557 error = EINVAL; 7558 break; 7559 } 7560 7561 DBPRINT(sc, BCE_INFO_MISC, 7562 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7563 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7564 7565 BCE_LOCK(sc); 7566 ifp->if_mtu = ifr->ifr_mtu; 7567 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7568 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7569 bce_init_locked(sc); 7570 } 7571 BCE_UNLOCK(sc); 7572 break; 7573 7574 /* Set interface flags. */ 7575 case SIOCSIFFLAGS: 7576 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7577 7578 BCE_LOCK(sc); 7579 7580 /* Check if the interface is up. */ 7581 if (ifp->if_flags & IFF_UP) { 7582 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7583 /* Change promiscuous/multicast flags as necessary. */ 7584 bce_set_rx_mode(sc); 7585 } else { 7586 /* Start the HW */ 7587 bce_init_locked(sc); 7588 } 7589 } else { 7590 /* The interface is down, check if driver is running. */ 7591 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7592 bce_stop(sc); 7593 7594 /* If MFW is running, restart the controller a bit. */ 7595 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7596 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7597 bce_chipinit(sc); 7598 bce_mgmt_init_locked(sc); 7599 } 7600 } 7601 } 7602 7603 BCE_UNLOCK(sc); 7604 break; 7605 7606 /* Add/Delete multicast address */ 7607 case SIOCADDMULTI: 7608 case SIOCDELMULTI: 7609 DBPRINT(sc, BCE_VERBOSE_MISC, 7610 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7611 7612 BCE_LOCK(sc); 7613 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7614 bce_set_rx_mode(sc); 7615 BCE_UNLOCK(sc); 7616 7617 break; 7618 7619 /* Set/Get Interface media */ 7620 case SIOCSIFMEDIA: 7621 case SIOCGIFMEDIA: 7622 DBPRINT(sc, BCE_VERBOSE_MISC, 7623 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7624 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 7625 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia, 7626 command); 7627 else { 7628 mii = device_get_softc(sc->bce_miibus); 7629 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 7630 command); 7631 } 7632 break; 7633 7634 /* Set interface capability */ 7635 case SIOCSIFCAP: 7636 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7637 DBPRINT(sc, BCE_INFO_MISC, 7638 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7639 7640 /* Toggle the TX checksum capabilities enable flag. */ 7641 if (mask & IFCAP_TXCSUM && 7642 ifp->if_capabilities & IFCAP_TXCSUM) { 7643 ifp->if_capenable ^= IFCAP_TXCSUM; 7644 if (IFCAP_TXCSUM & ifp->if_capenable) 7645 ifp->if_hwassist |= BCE_IF_HWASSIST; 7646 else 7647 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7648 } 7649 7650 /* Toggle the RX checksum capabilities enable flag. */ 7651 if (mask & IFCAP_RXCSUM && 7652 ifp->if_capabilities & IFCAP_RXCSUM) 7653 ifp->if_capenable ^= IFCAP_RXCSUM; 7654 7655 /* Toggle the TSO capabilities enable flag. */ 7656 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7657 ifp->if_capabilities & IFCAP_TSO4) { 7658 ifp->if_capenable ^= IFCAP_TSO4; 7659 if (IFCAP_TSO4 & ifp->if_capenable) 7660 ifp->if_hwassist |= CSUM_TSO; 7661 else 7662 ifp->if_hwassist &= ~CSUM_TSO; 7663 } 7664 7665 if (mask & IFCAP_VLAN_HWCSUM && 7666 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7667 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7668 7669 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7670 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7671 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7672 /* 7673 * Don't actually disable VLAN tag stripping as 7674 * management firmware (ASF/IPMI/UMP) requires the 7675 * feature. If VLAN tag stripping is disabled driver 7676 * will manually reconstruct the VLAN frame by 7677 * appending stripped VLAN tag. 7678 */ 7679 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7680 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7681 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7682 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7683 == 0) 7684 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7685 } 7686 VLAN_CAPABILITIES(ifp); 7687 break; 7688 default: 7689 /* We don't know how to handle the IOCTL, pass it on. */ 7690 error = ether_ioctl(ifp, command, data); 7691 break; 7692 } 7693 7694 DBEXIT(BCE_VERBOSE_MISC); 7695 return(error); 7696 } 7697 7698 /****************************************************************************/ 7699 /* Transmit timeout handler. */ 7700 /* */ 7701 /* Returns: */ 7702 /* Nothing. */ 7703 /****************************************************************************/ 7704 static void 7705 bce_watchdog(struct bce_softc *sc) 7706 { 7707 uint32_t status; 7708 7709 DBENTER(BCE_EXTREME_SEND); 7710 7711 BCE_LOCK_ASSERT(sc); 7712 7713 status = 0; 7714 /* If the watchdog timer hasn't expired then just exit. */ 7715 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7716 goto bce_watchdog_exit; 7717 7718 status = REG_RD(sc, BCE_EMAC_RX_STATUS); 7719 /* If pause frames are active then don't reset the hardware. */ 7720 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) { 7721 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) { 7722 /* 7723 * If link partner has us in XOFF state then wait for 7724 * the condition to clear. 7725 */ 7726 sc->watchdog_timer = BCE_TX_TIMEOUT; 7727 goto bce_watchdog_exit; 7728 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 && 7729 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) { 7730 /* 7731 * If we're not currently XOFF'ed but have recently 7732 * been XOFF'd/XON'd then assume that's delaying TX 7733 * this time around. 7734 */ 7735 sc->watchdog_timer = BCE_TX_TIMEOUT; 7736 goto bce_watchdog_exit; 7737 } 7738 /* 7739 * Any other condition is unexpected and the controller 7740 * should be reset. 7741 */ 7742 } 7743 7744 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7745 __FILE__, __LINE__); 7746 7747 DBRUNMSG(BCE_INFO, 7748 bce_dump_driver_state(sc); 7749 bce_dump_status_block(sc); 7750 bce_dump_stats_block(sc); 7751 bce_dump_ftqs(sc); 7752 bce_dump_txp_state(sc, 0); 7753 bce_dump_rxp_state(sc, 0); 7754 bce_dump_tpat_state(sc, 0); 7755 bce_dump_cp_state(sc, 0); 7756 bce_dump_com_state(sc, 0)); 7757 7758 DBRUN(bce_breakpoint(sc)); 7759 7760 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7761 7762 bce_init_locked(sc); 7763 sc->watchdog_timeouts++; 7764 7765 bce_watchdog_exit: 7766 REG_WR(sc, BCE_EMAC_RX_STATUS, status); 7767 DBEXIT(BCE_EXTREME_SEND); 7768 } 7769 7770 /* 7771 * Interrupt handler. 7772 */ 7773 /****************************************************************************/ 7774 /* Main interrupt entry point. Verifies that the controller generated the */ 7775 /* interrupt and then calls a separate routine for handle the various */ 7776 /* interrupt causes (PHY, TX, RX). */ 7777 /* */ 7778 /* Returns: */ 7779 /* Nothing. */ 7780 /****************************************************************************/ 7781 static void 7782 bce_intr(void *xsc) 7783 { 7784 struct bce_softc *sc; 7785 struct ifnet *ifp; 7786 u32 status_attn_bits; 7787 u16 hw_rx_cons, hw_tx_cons; 7788 7789 sc = xsc; 7790 ifp = sc->bce_ifp; 7791 7792 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7793 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7794 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7795 7796 BCE_LOCK(sc); 7797 7798 DBRUN(sc->interrupts_generated++); 7799 7800 /* Synchnorize before we read from interface's status block */ 7801 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 7802 7803 /* 7804 * If the hardware status block index matches the last value read 7805 * by the driver and we haven't asserted our interrupt then there's 7806 * nothing to do. This may only happen in case of INTx due to the 7807 * interrupt arriving at the CPU before the status block is updated. 7808 */ 7809 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 && 7810 sc->status_block->status_idx == sc->last_status_idx && 7811 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7812 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7813 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7814 __FUNCTION__); 7815 goto bce_intr_exit; 7816 } 7817 7818 /* Ack the interrupt and stop others from occurring. */ 7819 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7820 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7821 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7822 7823 /* Check if the hardware has finished any work. */ 7824 hw_rx_cons = bce_get_hw_rx_cons(sc); 7825 hw_tx_cons = bce_get_hw_tx_cons(sc); 7826 7827 /* Keep processing data as long as there is work to do. */ 7828 for (;;) { 7829 status_attn_bits = sc->status_block->status_attn_bits; 7830 7831 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7832 BCE_PRINTF("Simulating unexpected status attention " 7833 "bit set."); 7834 sc->unexpected_attention_sim_count++; 7835 status_attn_bits = status_attn_bits | 7836 STATUS_ATTN_BITS_PARITY_ERROR); 7837 7838 /* Was it a link change interrupt? */ 7839 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7840 (sc->status_block->status_attn_bits_ack & 7841 STATUS_ATTN_BITS_LINK_STATE)) { 7842 bce_phy_intr(sc); 7843 7844 /* Clear transient updates during link state change. */ 7845 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7846 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7847 REG_RD(sc, BCE_HC_COMMAND); 7848 } 7849 7850 /* If any other attention is asserted, the chip is toast. */ 7851 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7852 (sc->status_block->status_attn_bits_ack & 7853 ~STATUS_ATTN_BITS_LINK_STATE))) { 7854 sc->unexpected_attention_count++; 7855 7856 BCE_PRINTF("%s(%d): Fatal attention detected: " 7857 "0x%08X\n", __FILE__, __LINE__, 7858 sc->status_block->status_attn_bits); 7859 7860 DBRUNMSG(BCE_FATAL, 7861 if (unexpected_attention_sim_control == 0) 7862 bce_breakpoint(sc)); 7863 7864 bce_init_locked(sc); 7865 goto bce_intr_exit; 7866 } 7867 7868 /* Check for any completed RX frames. */ 7869 if (hw_rx_cons != sc->hw_rx_cons) 7870 bce_rx_intr(sc); 7871 7872 /* Check for any completed TX frames. */ 7873 if (hw_tx_cons != sc->hw_tx_cons) 7874 bce_tx_intr(sc); 7875 7876 /* Save status block index value for the next interrupt. */ 7877 sc->last_status_idx = sc->status_block->status_idx; 7878 7879 /* 7880 * Prevent speculative reads from getting 7881 * ahead of the status block. 7882 */ 7883 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7884 BUS_SPACE_BARRIER_READ); 7885 7886 /* 7887 * If there's no work left then exit the 7888 * interrupt service routine. 7889 */ 7890 hw_rx_cons = bce_get_hw_rx_cons(sc); 7891 hw_tx_cons = bce_get_hw_tx_cons(sc); 7892 7893 if ((hw_rx_cons == sc->hw_rx_cons) && 7894 (hw_tx_cons == sc->hw_tx_cons)) 7895 break; 7896 } 7897 7898 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD); 7899 7900 /* Re-enable interrupts. */ 7901 bce_enable_intr(sc, 0); 7902 7903 /* Handle any frames that arrived while handling the interrupt. */ 7904 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 7905 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7906 bce_start_locked(ifp); 7907 7908 bce_intr_exit: 7909 BCE_UNLOCK(sc); 7910 7911 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7912 } 7913 7914 /****************************************************************************/ 7915 /* Programs the various packet receive modes (broadcast and multicast). */ 7916 /* */ 7917 /* Returns: */ 7918 /* Nothing. */ 7919 /****************************************************************************/ 7920 static u_int 7921 bce_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 7922 { 7923 u32 *hashes = arg; 7924 int h; 7925 7926 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF; 7927 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7928 7929 return (1); 7930 } 7931 7932 static void 7933 bce_set_rx_mode(struct bce_softc *sc) 7934 { 7935 struct ifnet *ifp; 7936 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7937 u32 rx_mode, sort_mode; 7938 int i; 7939 7940 DBENTER(BCE_VERBOSE_MISC); 7941 7942 BCE_LOCK_ASSERT(sc); 7943 7944 ifp = sc->bce_ifp; 7945 7946 /* Initialize receive mode default settings. */ 7947 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7948 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7949 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7950 7951 /* 7952 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7953 * be enbled. 7954 */ 7955 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7956 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7957 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7958 7959 /* 7960 * Check for promiscuous, all multicast, or selected 7961 * multicast address filtering. 7962 */ 7963 if (ifp->if_flags & IFF_PROMISC) { 7964 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7965 7966 /* Enable promiscuous mode. */ 7967 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7968 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7969 } else if (ifp->if_flags & IFF_ALLMULTI) { 7970 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7971 7972 /* Enable all multicast addresses. */ 7973 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7974 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 7975 0xffffffff); 7976 } 7977 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7978 } else { 7979 /* Accept one or more multicast(s). */ 7980 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7981 if_foreach_llmaddr(ifp, bce_hash_maddr, hashes); 7982 7983 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7984 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7985 7986 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7987 } 7988 7989 /* Only make changes if the recive mode has actually changed. */ 7990 if (rx_mode != sc->rx_mode) { 7991 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 7992 "0x%08X\n", rx_mode); 7993 7994 sc->rx_mode = rx_mode; 7995 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7996 } 7997 7998 /* Disable and clear the exisitng sort before enabling a new sort. */ 7999 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 8000 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 8001 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 8002 8003 DBEXIT(BCE_VERBOSE_MISC); 8004 } 8005 8006 /****************************************************************************/ 8007 /* Called periodically to updates statistics from the controllers */ 8008 /* statistics block. */ 8009 /* */ 8010 /* Returns: */ 8011 /* Nothing. */ 8012 /****************************************************************************/ 8013 static void 8014 bce_stats_update(struct bce_softc *sc) 8015 { 8016 struct statistics_block *stats; 8017 8018 DBENTER(BCE_EXTREME_MISC); 8019 8020 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 8021 8022 stats = (struct statistics_block *) sc->stats_block; 8023 8024 /* 8025 * Update the sysctl statistics from the 8026 * hardware statistics. 8027 */ 8028 sc->stat_IfHCInOctets = 8029 ((u64) stats->stat_IfHCInOctets_hi << 32) + 8030 (u64) stats->stat_IfHCInOctets_lo; 8031 8032 sc->stat_IfHCInBadOctets = 8033 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 8034 (u64) stats->stat_IfHCInBadOctets_lo; 8035 8036 sc->stat_IfHCOutOctets = 8037 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 8038 (u64) stats->stat_IfHCOutOctets_lo; 8039 8040 sc->stat_IfHCOutBadOctets = 8041 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 8042 (u64) stats->stat_IfHCOutBadOctets_lo; 8043 8044 sc->stat_IfHCInUcastPkts = 8045 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 8046 (u64) stats->stat_IfHCInUcastPkts_lo; 8047 8048 sc->stat_IfHCInMulticastPkts = 8049 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 8050 (u64) stats->stat_IfHCInMulticastPkts_lo; 8051 8052 sc->stat_IfHCInBroadcastPkts = 8053 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 8054 (u64) stats->stat_IfHCInBroadcastPkts_lo; 8055 8056 sc->stat_IfHCOutUcastPkts = 8057 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 8058 (u64) stats->stat_IfHCOutUcastPkts_lo; 8059 8060 sc->stat_IfHCOutMulticastPkts = 8061 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 8062 (u64) stats->stat_IfHCOutMulticastPkts_lo; 8063 8064 sc->stat_IfHCOutBroadcastPkts = 8065 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 8066 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 8067 8068 /* ToDo: Preserve counters beyond 32 bits? */ 8069 /* ToDo: Read the statistics from auto-clear regs? */ 8070 8071 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 8072 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 8073 8074 sc->stat_Dot3StatsCarrierSenseErrors = 8075 stats->stat_Dot3StatsCarrierSenseErrors; 8076 8077 sc->stat_Dot3StatsFCSErrors = 8078 stats->stat_Dot3StatsFCSErrors; 8079 8080 sc->stat_Dot3StatsAlignmentErrors = 8081 stats->stat_Dot3StatsAlignmentErrors; 8082 8083 sc->stat_Dot3StatsSingleCollisionFrames = 8084 stats->stat_Dot3StatsSingleCollisionFrames; 8085 8086 sc->stat_Dot3StatsMultipleCollisionFrames = 8087 stats->stat_Dot3StatsMultipleCollisionFrames; 8088 8089 sc->stat_Dot3StatsDeferredTransmissions = 8090 stats->stat_Dot3StatsDeferredTransmissions; 8091 8092 sc->stat_Dot3StatsExcessiveCollisions = 8093 stats->stat_Dot3StatsExcessiveCollisions; 8094 8095 sc->stat_Dot3StatsLateCollisions = 8096 stats->stat_Dot3StatsLateCollisions; 8097 8098 sc->stat_EtherStatsCollisions = 8099 stats->stat_EtherStatsCollisions; 8100 8101 sc->stat_EtherStatsFragments = 8102 stats->stat_EtherStatsFragments; 8103 8104 sc->stat_EtherStatsJabbers = 8105 stats->stat_EtherStatsJabbers; 8106 8107 sc->stat_EtherStatsUndersizePkts = 8108 stats->stat_EtherStatsUndersizePkts; 8109 8110 sc->stat_EtherStatsOversizePkts = 8111 stats->stat_EtherStatsOversizePkts; 8112 8113 sc->stat_EtherStatsPktsRx64Octets = 8114 stats->stat_EtherStatsPktsRx64Octets; 8115 8116 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8117 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8118 8119 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8120 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8121 8122 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8123 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8124 8125 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8126 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8127 8128 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8129 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8130 8131 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8132 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8133 8134 sc->stat_EtherStatsPktsTx64Octets = 8135 stats->stat_EtherStatsPktsTx64Octets; 8136 8137 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8138 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8139 8140 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8141 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8142 8143 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8144 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8145 8146 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8147 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8148 8149 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8150 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8151 8152 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8153 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8154 8155 sc->stat_XonPauseFramesReceived = 8156 stats->stat_XonPauseFramesReceived; 8157 8158 sc->stat_XoffPauseFramesReceived = 8159 stats->stat_XoffPauseFramesReceived; 8160 8161 sc->stat_OutXonSent = 8162 stats->stat_OutXonSent; 8163 8164 sc->stat_OutXoffSent = 8165 stats->stat_OutXoffSent; 8166 8167 sc->stat_FlowControlDone = 8168 stats->stat_FlowControlDone; 8169 8170 sc->stat_MacControlFramesReceived = 8171 stats->stat_MacControlFramesReceived; 8172 8173 sc->stat_XoffStateEntered = 8174 stats->stat_XoffStateEntered; 8175 8176 sc->stat_IfInFramesL2FilterDiscards = 8177 stats->stat_IfInFramesL2FilterDiscards; 8178 8179 sc->stat_IfInRuleCheckerDiscards = 8180 stats->stat_IfInRuleCheckerDiscards; 8181 8182 sc->stat_IfInFTQDiscards = 8183 stats->stat_IfInFTQDiscards; 8184 8185 sc->stat_IfInMBUFDiscards = 8186 stats->stat_IfInMBUFDiscards; 8187 8188 sc->stat_IfInRuleCheckerP4Hit = 8189 stats->stat_IfInRuleCheckerP4Hit; 8190 8191 sc->stat_CatchupInRuleCheckerDiscards = 8192 stats->stat_CatchupInRuleCheckerDiscards; 8193 8194 sc->stat_CatchupInFTQDiscards = 8195 stats->stat_CatchupInFTQDiscards; 8196 8197 sc->stat_CatchupInMBUFDiscards = 8198 stats->stat_CatchupInMBUFDiscards; 8199 8200 sc->stat_CatchupInRuleCheckerP4Hit = 8201 stats->stat_CatchupInRuleCheckerP4Hit; 8202 8203 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8204 8205 /* ToDo: Add additional statistics? */ 8206 8207 DBEXIT(BCE_EXTREME_MISC); 8208 } 8209 8210 static uint64_t 8211 bce_get_counter(struct ifnet *ifp, ift_counter cnt) 8212 { 8213 struct bce_softc *sc; 8214 uint64_t rv; 8215 8216 sc = if_getsoftc(ifp); 8217 8218 switch (cnt) { 8219 case IFCOUNTER_COLLISIONS: 8220 return (sc->stat_EtherStatsCollisions); 8221 case IFCOUNTER_IERRORS: 8222 return (sc->stat_EtherStatsUndersizePkts + 8223 sc->stat_EtherStatsOversizePkts + 8224 sc->stat_IfInMBUFDiscards + 8225 sc->stat_Dot3StatsAlignmentErrors + 8226 sc->stat_Dot3StatsFCSErrors + 8227 sc->stat_IfInRuleCheckerDiscards + 8228 sc->stat_IfInFTQDiscards + 8229 sc->l2fhdr_error_count + 8230 sc->com_no_buffers); 8231 case IFCOUNTER_OERRORS: 8232 rv = sc->stat_Dot3StatsExcessiveCollisions + 8233 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8234 sc->stat_Dot3StatsLateCollisions + 8235 sc->watchdog_timeouts; 8236 /* 8237 * Certain controllers don't report 8238 * carrier sense errors correctly. 8239 * See errata E11_5708CA0_1165. 8240 */ 8241 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 8242 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 8243 rv += sc->stat_Dot3StatsCarrierSenseErrors; 8244 return (rv); 8245 default: 8246 return (if_get_counter_default(ifp, cnt)); 8247 } 8248 } 8249 8250 /****************************************************************************/ 8251 /* Periodic function to notify the bootcode that the driver is still */ 8252 /* present. */ 8253 /* */ 8254 /* Returns: */ 8255 /* Nothing. */ 8256 /****************************************************************************/ 8257 static void 8258 bce_pulse(void *xsc) 8259 { 8260 struct bce_softc *sc = xsc; 8261 u32 msg; 8262 8263 DBENTER(BCE_EXTREME_MISC); 8264 8265 BCE_LOCK_ASSERT(sc); 8266 8267 /* Tell the firmware that the driver is still running. */ 8268 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8269 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8270 8271 /* Update the bootcode condition. */ 8272 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8273 8274 /* Report whether the bootcode still knows the driver is running. */ 8275 if (bce_verbose || bootverbose) { 8276 if (sc->bce_drv_cardiac_arrest == FALSE) { 8277 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8278 sc->bce_drv_cardiac_arrest = TRUE; 8279 BCE_PRINTF("%s(): Warning: bootcode " 8280 "thinks driver is absent! " 8281 "(bc_state = 0x%08X)\n", 8282 __FUNCTION__, sc->bc_state); 8283 } 8284 } else { 8285 /* 8286 * Not supported by all bootcode versions. 8287 * (v5.0.11+ and v5.2.1+) Older bootcode 8288 * will require the driver to reset the 8289 * controller to clear this condition. 8290 */ 8291 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8292 sc->bce_drv_cardiac_arrest = FALSE; 8293 BCE_PRINTF("%s(): Bootcode found the " 8294 "driver pulse! (bc_state = 0x%08X)\n", 8295 __FUNCTION__, sc->bc_state); 8296 } 8297 } 8298 } 8299 8300 /* Schedule the next pulse. */ 8301 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8302 8303 DBEXIT(BCE_EXTREME_MISC); 8304 } 8305 8306 /****************************************************************************/ 8307 /* Periodic function to perform maintenance tasks. */ 8308 /* */ 8309 /* Returns: */ 8310 /* Nothing. */ 8311 /****************************************************************************/ 8312 static void 8313 bce_tick(void *xsc) 8314 { 8315 struct bce_softc *sc = xsc; 8316 struct mii_data *mii; 8317 struct ifnet *ifp; 8318 struct ifmediareq ifmr; 8319 8320 ifp = sc->bce_ifp; 8321 8322 DBENTER(BCE_EXTREME_MISC); 8323 8324 BCE_LOCK_ASSERT(sc); 8325 8326 /* Schedule the next tick. */ 8327 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8328 8329 /* Update the statistics from the hardware statistics block. */ 8330 bce_stats_update(sc); 8331 8332 /* Ensure page and RX chains get refilled in low-memory situations. */ 8333 if (bce_hdr_split == TRUE) 8334 bce_fill_pg_chain(sc); 8335 bce_fill_rx_chain(sc); 8336 8337 /* Check that chip hasn't hung. */ 8338 bce_watchdog(sc); 8339 8340 /* If link is up already up then we're done. */ 8341 if (sc->bce_link_up == TRUE) 8342 goto bce_tick_exit; 8343 8344 /* Link is down. Check what the PHY's doing. */ 8345 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 8346 bzero(&ifmr, sizeof(ifmr)); 8347 bce_ifmedia_sts_rphy(sc, &ifmr); 8348 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) == 8349 (IFM_ACTIVE | IFM_AVALID)) { 8350 sc->bce_link_up = TRUE; 8351 bce_miibus_statchg(sc->bce_dev); 8352 } 8353 } else { 8354 mii = device_get_softc(sc->bce_miibus); 8355 mii_tick(mii); 8356 /* Check if the link has come up. */ 8357 if ((mii->mii_media_status & IFM_ACTIVE) && 8358 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8359 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", 8360 __FUNCTION__); 8361 sc->bce_link_up = TRUE; 8362 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8363 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8364 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8365 (bce_verbose || bootverbose)) 8366 BCE_PRINTF("Gigabit link up!\n"); 8367 } 8368 } 8369 if (sc->bce_link_up == TRUE) { 8370 /* Now that link is up, handle any outstanding TX traffic. */ 8371 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8372 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8373 "pending TX traffic.\n", __FUNCTION__); 8374 bce_start_locked(ifp); 8375 } 8376 } 8377 8378 bce_tick_exit: 8379 DBEXIT(BCE_EXTREME_MISC); 8380 } 8381 8382 static void 8383 bce_fw_cap_init(struct bce_softc *sc) 8384 { 8385 u32 ack, cap, link; 8386 8387 ack = 0; 8388 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB); 8389 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) != 8390 BCE_FW_CAP_SIGNATURE_MAGIC) 8391 return; 8392 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) == 8393 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) 8394 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8395 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN; 8396 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 && 8397 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) { 8398 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8399 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG; 8400 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 8401 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0) 8402 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8403 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8404 BCE_FW_CAP_REMOTE_PHY_CAP; 8405 } 8406 8407 if (ack != 0) 8408 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack); 8409 } 8410 8411 #ifdef BCE_DEBUG 8412 /****************************************************************************/ 8413 /* Allows the driver state to be dumped through the sysctl interface. */ 8414 /* */ 8415 /* Returns: */ 8416 /* 0 for success, positive value for failure. */ 8417 /****************************************************************************/ 8418 static int 8419 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8420 { 8421 int error; 8422 int result; 8423 struct bce_softc *sc; 8424 8425 result = -1; 8426 error = sysctl_handle_int(oidp, &result, 0, req); 8427 8428 if (error || !req->newptr) 8429 return (error); 8430 8431 if (result == 1) { 8432 sc = (struct bce_softc *)arg1; 8433 bce_dump_driver_state(sc); 8434 } 8435 8436 return error; 8437 } 8438 8439 /****************************************************************************/ 8440 /* Allows the hardware state to be dumped through the sysctl interface. */ 8441 /* */ 8442 /* Returns: */ 8443 /* 0 for success, positive value for failure. */ 8444 /****************************************************************************/ 8445 static int 8446 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8447 { 8448 int error; 8449 int result; 8450 struct bce_softc *sc; 8451 8452 result = -1; 8453 error = sysctl_handle_int(oidp, &result, 0, req); 8454 8455 if (error || !req->newptr) 8456 return (error); 8457 8458 if (result == 1) { 8459 sc = (struct bce_softc *)arg1; 8460 bce_dump_hw_state(sc); 8461 } 8462 8463 return error; 8464 } 8465 8466 /****************************************************************************/ 8467 /* Allows the status block to be dumped through the sysctl interface. */ 8468 /* */ 8469 /* Returns: */ 8470 /* 0 for success, positive value for failure. */ 8471 /****************************************************************************/ 8472 static int 8473 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8474 { 8475 int error; 8476 int result; 8477 struct bce_softc *sc; 8478 8479 result = -1; 8480 error = sysctl_handle_int(oidp, &result, 0, req); 8481 8482 if (error || !req->newptr) 8483 return (error); 8484 8485 if (result == 1) { 8486 sc = (struct bce_softc *)arg1; 8487 bce_dump_status_block(sc); 8488 } 8489 8490 return error; 8491 } 8492 8493 /****************************************************************************/ 8494 /* Allows the stats block to be dumped through the sysctl interface. */ 8495 /* */ 8496 /* Returns: */ 8497 /* 0 for success, positive value for failure. */ 8498 /****************************************************************************/ 8499 static int 8500 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8501 { 8502 int error; 8503 int result; 8504 struct bce_softc *sc; 8505 8506 result = -1; 8507 error = sysctl_handle_int(oidp, &result, 0, req); 8508 8509 if (error || !req->newptr) 8510 return (error); 8511 8512 if (result == 1) { 8513 sc = (struct bce_softc *)arg1; 8514 bce_dump_stats_block(sc); 8515 } 8516 8517 return error; 8518 } 8519 8520 /****************************************************************************/ 8521 /* Allows the stat counters to be cleared without unloading/reloading the */ 8522 /* driver. */ 8523 /* */ 8524 /* Returns: */ 8525 /* 0 for success, positive value for failure. */ 8526 /****************************************************************************/ 8527 static int 8528 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8529 { 8530 int error; 8531 int result; 8532 struct bce_softc *sc; 8533 8534 result = -1; 8535 error = sysctl_handle_int(oidp, &result, 0, req); 8536 8537 if (error || !req->newptr) 8538 return (error); 8539 8540 if (result == 1) { 8541 sc = (struct bce_softc *)arg1; 8542 struct statistics_block *stats; 8543 8544 stats = (struct statistics_block *) sc->stats_block; 8545 bzero(stats, sizeof(struct statistics_block)); 8546 bus_dmamap_sync(sc->stats_tag, sc->stats_map, 8547 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 8548 8549 /* Clear the internal H/W statistics counters. */ 8550 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8551 8552 /* Reset the driver maintained statistics. */ 8553 sc->interrupts_rx = 8554 sc->interrupts_tx = 0; 8555 sc->tso_frames_requested = 8556 sc->tso_frames_completed = 8557 sc->tso_frames_failed = 0; 8558 sc->rx_empty_count = 8559 sc->tx_full_count = 0; 8560 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8561 sc->tx_hi_watermark = 0; 8562 sc->l2fhdr_error_count = 8563 sc->l2fhdr_error_sim_count = 0; 8564 sc->mbuf_alloc_failed_count = 8565 sc->mbuf_alloc_failed_sim_count = 0; 8566 sc->dma_map_addr_rx_failed_count = 8567 sc->dma_map_addr_tx_failed_count = 0; 8568 sc->mbuf_frag_count = 0; 8569 sc->csum_offload_tcp_udp = 8570 sc->csum_offload_ip = 0; 8571 sc->vlan_tagged_frames_rcvd = 8572 sc->vlan_tagged_frames_stripped = 0; 8573 sc->split_header_frames_rcvd = 8574 sc->split_header_tcp_frames_rcvd = 0; 8575 8576 /* Clear firmware maintained statistics. */ 8577 REG_WR_IND(sc, 0x120084, 0); 8578 } 8579 8580 return error; 8581 } 8582 8583 /****************************************************************************/ 8584 /* Allows the shared memory contents to be dumped through the sysctl . */ 8585 /* interface. */ 8586 /* */ 8587 /* Returns: */ 8588 /* 0 for success, positive value for failure. */ 8589 /****************************************************************************/ 8590 static int 8591 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8592 { 8593 int error; 8594 int result; 8595 struct bce_softc *sc; 8596 8597 result = -1; 8598 error = sysctl_handle_int(oidp, &result, 0, req); 8599 8600 if (error || !req->newptr) 8601 return (error); 8602 8603 if (result == 1) { 8604 sc = (struct bce_softc *)arg1; 8605 bce_dump_shmem_state(sc); 8606 } 8607 8608 return error; 8609 } 8610 8611 /****************************************************************************/ 8612 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8613 /* */ 8614 /* Returns: */ 8615 /* 0 for success, positive value for failure. */ 8616 /****************************************************************************/ 8617 static int 8618 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8619 { 8620 int error; 8621 int result; 8622 struct bce_softc *sc; 8623 8624 result = -1; 8625 error = sysctl_handle_int(oidp, &result, 0, req); 8626 8627 if (error || !req->newptr) 8628 return (error); 8629 8630 if (result == 1) { 8631 sc = (struct bce_softc *)arg1; 8632 bce_dump_bc_state(sc); 8633 } 8634 8635 return error; 8636 } 8637 8638 /****************************************************************************/ 8639 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8640 /* */ 8641 /* Returns: */ 8642 /* 0 for success, positive value for failure. */ 8643 /****************************************************************************/ 8644 static int 8645 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8646 { 8647 int error; 8648 int result; 8649 struct bce_softc *sc; 8650 8651 result = -1; 8652 error = sysctl_handle_int(oidp, &result, 0, req); 8653 8654 if (error || !req->newptr) 8655 return (error); 8656 8657 if (result == 1) { 8658 sc = (struct bce_softc *)arg1; 8659 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8660 } 8661 8662 return error; 8663 } 8664 8665 /****************************************************************************/ 8666 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8667 /* */ 8668 /* Returns: */ 8669 /* 0 for success, positive value for failure. */ 8670 /****************************************************************************/ 8671 static int 8672 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8673 { 8674 int error; 8675 int result; 8676 struct bce_softc *sc; 8677 8678 result = -1; 8679 error = sysctl_handle_int(oidp, &result, 0, req); 8680 8681 if (error || !req->newptr) 8682 return (error); 8683 8684 if (result == 1) { 8685 sc = (struct bce_softc *)arg1; 8686 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8687 } 8688 8689 return error; 8690 } 8691 8692 /****************************************************************************/ 8693 /* Provides a sysctl interface to allow dumping the TX chain. */ 8694 /* */ 8695 /* Returns: */ 8696 /* 0 for success, positive value for failure. */ 8697 /****************************************************************************/ 8698 static int 8699 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8700 { 8701 int error; 8702 int result; 8703 struct bce_softc *sc; 8704 8705 result = -1; 8706 error = sysctl_handle_int(oidp, &result, 0, req); 8707 8708 if (error || !req->newptr) 8709 return (error); 8710 8711 if (result == 1) { 8712 sc = (struct bce_softc *)arg1; 8713 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8714 } 8715 8716 return error; 8717 } 8718 8719 /****************************************************************************/ 8720 /* Provides a sysctl interface to allow dumping the page chain. */ 8721 /* */ 8722 /* Returns: */ 8723 /* 0 for success, positive value for failure. */ 8724 /****************************************************************************/ 8725 static int 8726 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8727 { 8728 int error; 8729 int result; 8730 struct bce_softc *sc; 8731 8732 result = -1; 8733 error = sysctl_handle_int(oidp, &result, 0, req); 8734 8735 if (error || !req->newptr) 8736 return (error); 8737 8738 if (result == 1) { 8739 sc = (struct bce_softc *)arg1; 8740 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8741 } 8742 8743 return error; 8744 } 8745 8746 /****************************************************************************/ 8747 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8748 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8749 /* */ 8750 /* Returns: */ 8751 /* 0 for success, positive value for failure. */ 8752 /****************************************************************************/ 8753 static int 8754 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8755 { 8756 struct bce_softc *sc = (struct bce_softc *)arg1; 8757 int error; 8758 u32 result; 8759 u32 val[1]; 8760 u8 *data = (u8 *) val; 8761 8762 result = -1; 8763 error = sysctl_handle_int(oidp, &result, 0, req); 8764 if (error || (req->newptr == NULL)) 8765 return (error); 8766 8767 error = bce_nvram_read(sc, result, data, 4); 8768 8769 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8770 8771 return (error); 8772 } 8773 8774 /****************************************************************************/ 8775 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8776 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8777 /* */ 8778 /* Returns: */ 8779 /* 0 for success, positive value for failure. */ 8780 /****************************************************************************/ 8781 static int 8782 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8783 { 8784 struct bce_softc *sc = (struct bce_softc *)arg1; 8785 int error; 8786 u32 val, result; 8787 8788 result = -1; 8789 error = sysctl_handle_int(oidp, &result, 0, req); 8790 if (error || (req->newptr == NULL)) 8791 return (error); 8792 8793 /* Make sure the register is accessible. */ 8794 if (result < 0x8000) { 8795 val = REG_RD(sc, result); 8796 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8797 } else if (result < 0x0280000) { 8798 val = REG_RD_IND(sc, result); 8799 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8800 } 8801 8802 return (error); 8803 } 8804 8805 /****************************************************************************/ 8806 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8807 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8808 /* */ 8809 /* Returns: */ 8810 /* 0 for success, positive value for failure. */ 8811 /****************************************************************************/ 8812 static int 8813 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8814 { 8815 struct bce_softc *sc; 8816 device_t dev; 8817 int error, result; 8818 u16 val; 8819 8820 result = -1; 8821 error = sysctl_handle_int(oidp, &result, 0, req); 8822 if (error || (req->newptr == NULL)) 8823 return (error); 8824 8825 /* Make sure the register is accessible. */ 8826 if (result < 0x20) { 8827 sc = (struct bce_softc *)arg1; 8828 dev = sc->bce_dev; 8829 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8830 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8831 } 8832 return (error); 8833 } 8834 8835 /****************************************************************************/ 8836 /* Provides a sysctl interface for dumping the nvram contents. */ 8837 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8838 /* */ 8839 /* Returns: */ 8840 /* 0 for success, positive errno for failure. */ 8841 /****************************************************************************/ 8842 static int 8843 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 8844 { 8845 struct bce_softc *sc = (struct bce_softc *)arg1; 8846 int error, i; 8847 8848 if (sc->nvram_buf == NULL) 8849 sc->nvram_buf = malloc(sc->bce_flash_size, 8850 M_TEMP, M_ZERO | M_WAITOK); 8851 8852 error = 0; 8853 if (req->oldlen == sc->bce_flash_size) { 8854 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 8855 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 8856 } 8857 8858 if (error == 0) 8859 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 8860 8861 return error; 8862 } 8863 8864 #ifdef BCE_NVRAM_WRITE_SUPPORT 8865 /****************************************************************************/ 8866 /* Provides a sysctl interface for writing to nvram. */ 8867 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8868 /* */ 8869 /* Returns: */ 8870 /* 0 for success, positive errno for failure. */ 8871 /****************************************************************************/ 8872 static int 8873 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 8874 { 8875 struct bce_softc *sc = (struct bce_softc *)arg1; 8876 int error; 8877 8878 if (sc->nvram_buf == NULL) 8879 sc->nvram_buf = malloc(sc->bce_flash_size, 8880 M_TEMP, M_ZERO | M_WAITOK); 8881 else 8882 bzero(sc->nvram_buf, sc->bce_flash_size); 8883 8884 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 8885 if (error == 0) 8886 return (error); 8887 8888 if (req->newlen == sc->bce_flash_size) 8889 error = bce_nvram_write(sc, 0, sc->nvram_buf, 8890 sc->bce_flash_size); 8891 8892 return error; 8893 } 8894 #endif 8895 8896 /****************************************************************************/ 8897 /* Provides a sysctl interface to allow reading a CID. */ 8898 /* */ 8899 /* Returns: */ 8900 /* 0 for success, positive value for failure. */ 8901 /****************************************************************************/ 8902 static int 8903 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8904 { 8905 struct bce_softc *sc; 8906 int error, result; 8907 8908 result = -1; 8909 error = sysctl_handle_int(oidp, &result, 0, req); 8910 if (error || (req->newptr == NULL)) 8911 return (error); 8912 8913 /* Make sure the register is accessible. */ 8914 if (result <= TX_CID) { 8915 sc = (struct bce_softc *)arg1; 8916 bce_dump_ctx(sc, result); 8917 } 8918 8919 return (error); 8920 } 8921 8922 /****************************************************************************/ 8923 /* Provides a sysctl interface to forcing the driver to dump state and */ 8924 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8925 /* */ 8926 /* Returns: */ 8927 /* 0 for success, positive value for failure. */ 8928 /****************************************************************************/ 8929 static int 8930 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8931 { 8932 int error; 8933 int result; 8934 struct bce_softc *sc; 8935 8936 result = -1; 8937 error = sysctl_handle_int(oidp, &result, 0, req); 8938 8939 if (error || !req->newptr) 8940 return (error); 8941 8942 if (result == 1) { 8943 sc = (struct bce_softc *)arg1; 8944 bce_breakpoint(sc); 8945 } 8946 8947 return error; 8948 } 8949 #endif 8950 8951 /****************************************************************************/ 8952 /* Adds any sysctl parameters for tuning or debugging purposes. */ 8953 /* */ 8954 /* Returns: */ 8955 /* 0 for success, positive value for failure. */ 8956 /****************************************************************************/ 8957 static void 8958 bce_add_sysctls(struct bce_softc *sc) 8959 { 8960 struct sysctl_ctx_list *ctx; 8961 struct sysctl_oid_list *children; 8962 8963 DBENTER(BCE_VERBOSE_MISC); 8964 8965 ctx = device_get_sysctl_ctx(sc->bce_dev); 8966 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8967 8968 #ifdef BCE_DEBUG 8969 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8970 "l2fhdr_error_sim_control", 8971 CTLFLAG_RW, &l2fhdr_error_sim_control, 8972 0, "Debug control to force l2fhdr errors"); 8973 8974 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8975 "l2fhdr_error_sim_count", 8976 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8977 0, "Number of simulated l2_fhdr errors"); 8978 #endif 8979 8980 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8981 "l2fhdr_error_count", 8982 CTLFLAG_RD, &sc->l2fhdr_error_count, 8983 0, "Number of l2_fhdr errors"); 8984 8985 #ifdef BCE_DEBUG 8986 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8987 "mbuf_alloc_failed_sim_control", 8988 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8989 0, "Debug control to force mbuf allocation failures"); 8990 8991 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8992 "mbuf_alloc_failed_sim_count", 8993 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8994 0, "Number of simulated mbuf cluster allocation failures"); 8995 #endif 8996 8997 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8998 "mbuf_alloc_failed_count", 8999 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 9000 0, "Number of mbuf allocation failures"); 9001 9002 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9003 "mbuf_frag_count", 9004 CTLFLAG_RD, &sc->mbuf_frag_count, 9005 0, "Number of fragmented mbufs"); 9006 9007 #ifdef BCE_DEBUG 9008 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9009 "dma_map_addr_failed_sim_control", 9010 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 9011 0, "Debug control to force DMA mapping failures"); 9012 9013 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 9014 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9015 "dma_map_addr_failed_sim_count", 9016 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 9017 0, "Number of simulated DMA mapping failures"); 9018 9019 #endif 9020 9021 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9022 "dma_map_addr_rx_failed_count", 9023 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 9024 0, "Number of RX DMA mapping failures"); 9025 9026 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9027 "dma_map_addr_tx_failed_count", 9028 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 9029 0, "Number of TX DMA mapping failures"); 9030 9031 #ifdef BCE_DEBUG 9032 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9033 "unexpected_attention_sim_control", 9034 CTLFLAG_RW, &unexpected_attention_sim_control, 9035 0, "Debug control to simulate unexpected attentions"); 9036 9037 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9038 "unexpected_attention_sim_count", 9039 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 9040 0, "Number of simulated unexpected attentions"); 9041 #endif 9042 9043 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9044 "unexpected_attention_count", 9045 CTLFLAG_RW, &sc->unexpected_attention_count, 9046 0, "Number of unexpected attentions"); 9047 9048 #ifdef BCE_DEBUG 9049 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9050 "debug_bootcode_running_failure", 9051 CTLFLAG_RW, &bootcode_running_failure_sim_control, 9052 0, "Debug control to force bootcode running failures"); 9053 9054 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9055 "rx_low_watermark", 9056 CTLFLAG_RD, &sc->rx_low_watermark, 9057 0, "Lowest level of free rx_bd's"); 9058 9059 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9060 "rx_empty_count", 9061 CTLFLAG_RD, &sc->rx_empty_count, 9062 "Number of times the RX chain was empty"); 9063 9064 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9065 "tx_hi_watermark", 9066 CTLFLAG_RD, &sc->tx_hi_watermark, 9067 0, "Highest level of used tx_bd's"); 9068 9069 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9070 "tx_full_count", 9071 CTLFLAG_RD, &sc->tx_full_count, 9072 "Number of times the TX chain was full"); 9073 9074 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9075 "tso_frames_requested", 9076 CTLFLAG_RD, &sc->tso_frames_requested, 9077 "Number of TSO frames requested"); 9078 9079 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9080 "tso_frames_completed", 9081 CTLFLAG_RD, &sc->tso_frames_completed, 9082 "Number of TSO frames completed"); 9083 9084 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9085 "tso_frames_failed", 9086 CTLFLAG_RD, &sc->tso_frames_failed, 9087 "Number of TSO frames failed"); 9088 9089 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9090 "csum_offload_ip", 9091 CTLFLAG_RD, &sc->csum_offload_ip, 9092 "Number of IP checksum offload frames"); 9093 9094 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9095 "csum_offload_tcp_udp", 9096 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 9097 "Number of TCP/UDP checksum offload frames"); 9098 9099 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9100 "vlan_tagged_frames_rcvd", 9101 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 9102 "Number of VLAN tagged frames received"); 9103 9104 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9105 "vlan_tagged_frames_stripped", 9106 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 9107 "Number of VLAN tagged frames stripped"); 9108 9109 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9110 "interrupts_rx", 9111 CTLFLAG_RD, &sc->interrupts_rx, 9112 "Number of RX interrupts"); 9113 9114 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9115 "interrupts_tx", 9116 CTLFLAG_RD, &sc->interrupts_tx, 9117 "Number of TX interrupts"); 9118 9119 if (bce_hdr_split == TRUE) { 9120 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9121 "split_header_frames_rcvd", 9122 CTLFLAG_RD, &sc->split_header_frames_rcvd, 9123 "Number of split header frames received"); 9124 9125 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9126 "split_header_tcp_frames_rcvd", 9127 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 9128 "Number of split header TCP frames received"); 9129 } 9130 9131 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9132 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 9133 (void *)sc, 0, 9134 bce_sysctl_nvram_dump, "S", ""); 9135 9136 #ifdef BCE_NVRAM_WRITE_SUPPORT 9137 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9138 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR | CTLFLAG_NEEDGIANT, 9139 (void *)sc, 0, 9140 bce_sysctl_nvram_write, "S", ""); 9141 #endif 9142 #endif /* BCE_DEBUG */ 9143 9144 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9145 "stat_IfHcInOctets", 9146 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9147 "Bytes received"); 9148 9149 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9150 "stat_IfHCInBadOctets", 9151 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9152 "Bad bytes received"); 9153 9154 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9155 "stat_IfHCOutOctets", 9156 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9157 "Bytes sent"); 9158 9159 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9160 "stat_IfHCOutBadOctets", 9161 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9162 "Bad bytes sent"); 9163 9164 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9165 "stat_IfHCInUcastPkts", 9166 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9167 "Unicast packets received"); 9168 9169 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9170 "stat_IfHCInMulticastPkts", 9171 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9172 "Multicast packets received"); 9173 9174 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9175 "stat_IfHCInBroadcastPkts", 9176 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9177 "Broadcast packets received"); 9178 9179 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9180 "stat_IfHCOutUcastPkts", 9181 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9182 "Unicast packets sent"); 9183 9184 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9185 "stat_IfHCOutMulticastPkts", 9186 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9187 "Multicast packets sent"); 9188 9189 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9190 "stat_IfHCOutBroadcastPkts", 9191 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9192 "Broadcast packets sent"); 9193 9194 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9195 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9196 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9197 0, "Internal MAC transmit errors"); 9198 9199 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9200 "stat_Dot3StatsCarrierSenseErrors", 9201 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9202 0, "Carrier sense errors"); 9203 9204 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9205 "stat_Dot3StatsFCSErrors", 9206 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9207 0, "Frame check sequence errors"); 9208 9209 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9210 "stat_Dot3StatsAlignmentErrors", 9211 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9212 0, "Alignment errors"); 9213 9214 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9215 "stat_Dot3StatsSingleCollisionFrames", 9216 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9217 0, "Single Collision Frames"); 9218 9219 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9220 "stat_Dot3StatsMultipleCollisionFrames", 9221 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9222 0, "Multiple Collision Frames"); 9223 9224 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9225 "stat_Dot3StatsDeferredTransmissions", 9226 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9227 0, "Deferred Transmissions"); 9228 9229 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9230 "stat_Dot3StatsExcessiveCollisions", 9231 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9232 0, "Excessive Collisions"); 9233 9234 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9235 "stat_Dot3StatsLateCollisions", 9236 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9237 0, "Late Collisions"); 9238 9239 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9240 "stat_EtherStatsCollisions", 9241 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9242 0, "Collisions"); 9243 9244 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9245 "stat_EtherStatsFragments", 9246 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9247 0, "Fragments"); 9248 9249 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9250 "stat_EtherStatsJabbers", 9251 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9252 0, "Jabbers"); 9253 9254 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9255 "stat_EtherStatsUndersizePkts", 9256 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9257 0, "Undersize packets"); 9258 9259 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9260 "stat_EtherStatsOversizePkts", 9261 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9262 0, "stat_EtherStatsOversizePkts"); 9263 9264 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9265 "stat_EtherStatsPktsRx64Octets", 9266 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9267 0, "Bytes received in 64 byte packets"); 9268 9269 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9270 "stat_EtherStatsPktsRx65Octetsto127Octets", 9271 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9272 0, "Bytes received in 65 to 127 byte packets"); 9273 9274 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9275 "stat_EtherStatsPktsRx128Octetsto255Octets", 9276 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9277 0, "Bytes received in 128 to 255 byte packets"); 9278 9279 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9280 "stat_EtherStatsPktsRx256Octetsto511Octets", 9281 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9282 0, "Bytes received in 256 to 511 byte packets"); 9283 9284 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9285 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9286 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9287 0, "Bytes received in 512 to 1023 byte packets"); 9288 9289 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9290 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9291 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9292 0, "Bytes received in 1024 t0 1522 byte packets"); 9293 9294 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9295 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9296 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9297 0, "Bytes received in 1523 to 9022 byte packets"); 9298 9299 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9300 "stat_EtherStatsPktsTx64Octets", 9301 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9302 0, "Bytes sent in 64 byte packets"); 9303 9304 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9305 "stat_EtherStatsPktsTx65Octetsto127Octets", 9306 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9307 0, "Bytes sent in 65 to 127 byte packets"); 9308 9309 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9310 "stat_EtherStatsPktsTx128Octetsto255Octets", 9311 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9312 0, "Bytes sent in 128 to 255 byte packets"); 9313 9314 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9315 "stat_EtherStatsPktsTx256Octetsto511Octets", 9316 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9317 0, "Bytes sent in 256 to 511 byte packets"); 9318 9319 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9320 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9321 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9322 0, "Bytes sent in 512 to 1023 byte packets"); 9323 9324 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9325 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9326 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9327 0, "Bytes sent in 1024 to 1522 byte packets"); 9328 9329 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9330 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9331 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9332 0, "Bytes sent in 1523 to 9022 byte packets"); 9333 9334 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9335 "stat_XonPauseFramesReceived", 9336 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9337 0, "XON pause frames receved"); 9338 9339 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9340 "stat_XoffPauseFramesReceived", 9341 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9342 0, "XOFF pause frames received"); 9343 9344 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9345 "stat_OutXonSent", 9346 CTLFLAG_RD, &sc->stat_OutXonSent, 9347 0, "XON pause frames sent"); 9348 9349 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9350 "stat_OutXoffSent", 9351 CTLFLAG_RD, &sc->stat_OutXoffSent, 9352 0, "XOFF pause frames sent"); 9353 9354 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9355 "stat_FlowControlDone", 9356 CTLFLAG_RD, &sc->stat_FlowControlDone, 9357 0, "Flow control done"); 9358 9359 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9360 "stat_MacControlFramesReceived", 9361 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9362 0, "MAC control frames received"); 9363 9364 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9365 "stat_XoffStateEntered", 9366 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9367 0, "XOFF state entered"); 9368 9369 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9370 "stat_IfInFramesL2FilterDiscards", 9371 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9372 0, "Received L2 packets discarded"); 9373 9374 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9375 "stat_IfInRuleCheckerDiscards", 9376 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9377 0, "Received packets discarded by rule"); 9378 9379 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9380 "stat_IfInFTQDiscards", 9381 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9382 0, "Received packet FTQ discards"); 9383 9384 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9385 "stat_IfInMBUFDiscards", 9386 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9387 0, "Received packets discarded due to lack " 9388 "of controller buffer memory"); 9389 9390 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9391 "stat_IfInRuleCheckerP4Hit", 9392 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9393 0, "Received packets rule checker hits"); 9394 9395 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9396 "stat_CatchupInRuleCheckerDiscards", 9397 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9398 0, "Received packets discarded in Catchup path"); 9399 9400 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9401 "stat_CatchupInFTQDiscards", 9402 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9403 0, "Received packets discarded in FTQ in Catchup path"); 9404 9405 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9406 "stat_CatchupInMBUFDiscards", 9407 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9408 0, "Received packets discarded in controller " 9409 "buffer memory in Catchup path"); 9410 9411 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9412 "stat_CatchupInRuleCheckerP4Hit", 9413 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9414 0, "Received packets rule checker hits in Catchup path"); 9415 9416 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9417 "com_no_buffers", 9418 CTLFLAG_RD, &sc->com_no_buffers, 9419 0, "Valid packets received but no RX buffers available"); 9420 9421 #ifdef BCE_DEBUG 9422 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9423 "driver_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9424 (void *)sc, 0, 9425 bce_sysctl_driver_state, "I", "Drive state information"); 9426 9427 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9428 "hw_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9429 (void *)sc, 0, 9430 bce_sysctl_hw_state, "I", "Hardware state information"); 9431 9432 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9433 "status_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9434 (void *)sc, 0, 9435 bce_sysctl_status_block, "I", "Dump status block"); 9436 9437 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9438 "stats_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9439 (void *)sc, 0, 9440 bce_sysctl_stats_block, "I", "Dump statistics block"); 9441 9442 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9443 "stats_clear", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9444 (void *)sc, 0, 9445 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9446 9447 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9448 "shmem_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9449 (void *)sc, 0, 9450 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9451 9452 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9453 "bc_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9454 (void *)sc, 0, 9455 bce_sysctl_bc_state, "I", "Bootcode state information"); 9456 9457 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9458 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9459 (void *)sc, 0, 9460 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9461 9462 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9463 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9464 (void *)sc, 0, 9465 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9466 9467 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9468 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9469 (void *)sc, 0, 9470 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9471 9472 if (bce_hdr_split == TRUE) { 9473 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9474 "dump_pg_chain", 9475 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9476 (void *)sc, 0, 9477 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9478 } 9479 9480 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9481 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9482 (void *)sc, 0, 9483 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9484 9485 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9486 "breakpoint", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9487 (void *)sc, 0, 9488 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9489 9490 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9491 "reg_read", CTLTYPE_INT | CTLFLAG_RW| CTLFLAG_NEEDGIANT, 9492 (void *)sc, 0, 9493 bce_sysctl_reg_read, "I", "Register read"); 9494 9495 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9496 "nvram_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9497 (void *)sc, 0, 9498 bce_sysctl_nvram_read, "I", "NVRAM read"); 9499 9500 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9501 "phy_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9502 (void *)sc, 0, 9503 bce_sysctl_phy_read, "I", "PHY register read"); 9504 9505 #endif 9506 9507 DBEXIT(BCE_VERBOSE_MISC); 9508 } 9509 9510 /****************************************************************************/ 9511 /* BCE Debug Routines */ 9512 /****************************************************************************/ 9513 #ifdef BCE_DEBUG 9514 9515 /****************************************************************************/ 9516 /* Freezes the controller to allow for a cohesive state dump. */ 9517 /* */ 9518 /* Returns: */ 9519 /* Nothing. */ 9520 /****************************************************************************/ 9521 static __attribute__ ((noinline)) void 9522 bce_freeze_controller(struct bce_softc *sc) 9523 { 9524 u32 val; 9525 val = REG_RD(sc, BCE_MISC_COMMAND); 9526 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9527 REG_WR(sc, BCE_MISC_COMMAND, val); 9528 } 9529 9530 /****************************************************************************/ 9531 /* Unfreezes the controller after a freeze operation. This may not always */ 9532 /* work and the controller will require a reset! */ 9533 /* */ 9534 /* Returns: */ 9535 /* Nothing. */ 9536 /****************************************************************************/ 9537 static __attribute__ ((noinline)) void 9538 bce_unfreeze_controller(struct bce_softc *sc) 9539 { 9540 u32 val; 9541 val = REG_RD(sc, BCE_MISC_COMMAND); 9542 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9543 REG_WR(sc, BCE_MISC_COMMAND, val); 9544 } 9545 9546 /****************************************************************************/ 9547 /* Prints out Ethernet frame information from an mbuf. */ 9548 /* */ 9549 /* Partially decode an Ethernet frame to look at some important headers. */ 9550 /* */ 9551 /* Returns: */ 9552 /* Nothing. */ 9553 /****************************************************************************/ 9554 static __attribute__ ((noinline)) void 9555 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9556 { 9557 struct ether_vlan_header *eh; 9558 u16 etype; 9559 int ehlen; 9560 struct ip *ip; 9561 struct tcphdr *th; 9562 struct udphdr *uh; 9563 struct arphdr *ah; 9564 9565 BCE_PRINTF( 9566 "-----------------------------" 9567 " Frame Decode " 9568 "-----------------------------\n"); 9569 9570 eh = mtod(m, struct ether_vlan_header *); 9571 9572 /* Handle VLAN encapsulation if present. */ 9573 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9574 etype = ntohs(eh->evl_proto); 9575 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9576 } else { 9577 etype = ntohs(eh->evl_encap_proto); 9578 ehlen = ETHER_HDR_LEN; 9579 } 9580 9581 /* ToDo: Add VLAN output. */ 9582 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9583 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9584 9585 switch (etype) { 9586 case ETHERTYPE_IP: 9587 ip = (struct ip *)(m->m_data + ehlen); 9588 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9589 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9590 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9591 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9592 9593 switch (ip->ip_p) { 9594 case IPPROTO_TCP: 9595 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9596 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9597 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9598 ntohs(th->th_dport), ntohs(th->th_sport), 9599 (th->th_off << 2), th->th_flags, 9600 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9601 "\02SYN\01FIN", ntohs(th->th_sum)); 9602 break; 9603 case IPPROTO_UDP: 9604 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9605 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9606 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9607 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9608 ntohs(uh->uh_sum)); 9609 break; 9610 case IPPROTO_ICMP: 9611 BCE_PRINTF("icmp:\n"); 9612 break; 9613 default: 9614 BCE_PRINTF("----: Other IP protocol.\n"); 9615 } 9616 break; 9617 case ETHERTYPE_IPV6: 9618 BCE_PRINTF("ipv6: No decode supported.\n"); 9619 break; 9620 case ETHERTYPE_ARP: 9621 BCE_PRINTF("-arp: "); 9622 ah = (struct arphdr *) (m->m_data + ehlen); 9623 switch (ntohs(ah->ar_op)) { 9624 case ARPOP_REVREQUEST: 9625 printf("reverse ARP request\n"); 9626 break; 9627 case ARPOP_REVREPLY: 9628 printf("reverse ARP reply\n"); 9629 break; 9630 case ARPOP_REQUEST: 9631 printf("ARP request\n"); 9632 break; 9633 case ARPOP_REPLY: 9634 printf("ARP reply\n"); 9635 break; 9636 default: 9637 printf("other ARP operation\n"); 9638 } 9639 break; 9640 default: 9641 BCE_PRINTF("----: Other protocol.\n"); 9642 } 9643 9644 BCE_PRINTF( 9645 "-----------------------------" 9646 "--------------" 9647 "-----------------------------\n"); 9648 } 9649 9650 /****************************************************************************/ 9651 /* Prints out information about an mbuf. */ 9652 /* */ 9653 /* Returns: */ 9654 /* Nothing. */ 9655 /****************************************************************************/ 9656 static __attribute__ ((noinline)) void 9657 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9658 { 9659 struct mbuf *mp = m; 9660 9661 if (m == NULL) { 9662 BCE_PRINTF("mbuf: null pointer\n"); 9663 return; 9664 } 9665 9666 while (mp) { 9667 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9668 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9669 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9670 9671 if (mp->m_flags & M_PKTHDR) { 9672 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9673 "csum_flags = %b\n", mp->m_pkthdr.len, 9674 mp->m_flags, M_FLAG_PRINTF, 9675 mp->m_pkthdr.csum_flags, CSUM_BITS); 9676 } 9677 9678 if (mp->m_flags & M_EXT) { 9679 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9680 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9681 switch (mp->m_ext.ext_type) { 9682 case EXT_CLUSTER: 9683 printf("EXT_CLUSTER\n"); break; 9684 case EXT_SFBUF: 9685 printf("EXT_SFBUF\n"); break; 9686 case EXT_JUMBO9: 9687 printf("EXT_JUMBO9\n"); break; 9688 case EXT_JUMBO16: 9689 printf("EXT_JUMBO16\n"); break; 9690 case EXT_PACKET: 9691 printf("EXT_PACKET\n"); break; 9692 case EXT_MBUF: 9693 printf("EXT_MBUF\n"); break; 9694 case EXT_NET_DRV: 9695 printf("EXT_NET_DRV\n"); break; 9696 case EXT_MOD_TYPE: 9697 printf("EXT_MDD_TYPE\n"); break; 9698 case EXT_DISPOSABLE: 9699 printf("EXT_DISPOSABLE\n"); break; 9700 case EXT_EXTREF: 9701 printf("EXT_EXTREF\n"); break; 9702 default: 9703 printf("UNKNOWN\n"); 9704 } 9705 } 9706 9707 mp = mp->m_next; 9708 } 9709 } 9710 9711 /****************************************************************************/ 9712 /* Prints out the mbufs in the TX mbuf chain. */ 9713 /* */ 9714 /* Returns: */ 9715 /* Nothing. */ 9716 /****************************************************************************/ 9717 static __attribute__ ((noinline)) void 9718 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9719 { 9720 struct mbuf *m; 9721 9722 BCE_PRINTF( 9723 "----------------------------" 9724 " tx mbuf data " 9725 "----------------------------\n"); 9726 9727 for (int i = 0; i < count; i++) { 9728 m = sc->tx_mbuf_ptr[chain_prod]; 9729 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9730 bce_dump_mbuf(sc, m); 9731 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9732 } 9733 9734 BCE_PRINTF( 9735 "----------------------------" 9736 "----------------" 9737 "----------------------------\n"); 9738 } 9739 9740 /****************************************************************************/ 9741 /* Prints out the mbufs in the RX mbuf chain. */ 9742 /* */ 9743 /* Returns: */ 9744 /* Nothing. */ 9745 /****************************************************************************/ 9746 static __attribute__ ((noinline)) void 9747 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9748 { 9749 struct mbuf *m; 9750 9751 BCE_PRINTF( 9752 "----------------------------" 9753 " rx mbuf data " 9754 "----------------------------\n"); 9755 9756 for (int i = 0; i < count; i++) { 9757 m = sc->rx_mbuf_ptr[chain_prod]; 9758 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9759 bce_dump_mbuf(sc, m); 9760 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9761 } 9762 9763 BCE_PRINTF( 9764 "----------------------------" 9765 "----------------" 9766 "----------------------------\n"); 9767 } 9768 9769 /****************************************************************************/ 9770 /* Prints out the mbufs in the mbuf page chain. */ 9771 /* */ 9772 /* Returns: */ 9773 /* Nothing. */ 9774 /****************************************************************************/ 9775 static __attribute__ ((noinline)) void 9776 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9777 { 9778 struct mbuf *m; 9779 9780 BCE_PRINTF( 9781 "----------------------------" 9782 " pg mbuf data " 9783 "----------------------------\n"); 9784 9785 for (int i = 0; i < count; i++) { 9786 m = sc->pg_mbuf_ptr[chain_prod]; 9787 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9788 bce_dump_mbuf(sc, m); 9789 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9790 } 9791 9792 BCE_PRINTF( 9793 "----------------------------" 9794 "----------------" 9795 "----------------------------\n"); 9796 } 9797 9798 /****************************************************************************/ 9799 /* Prints out a tx_bd structure. */ 9800 /* */ 9801 /* Returns: */ 9802 /* Nothing. */ 9803 /****************************************************************************/ 9804 static __attribute__ ((noinline)) void 9805 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9806 { 9807 int i = 0; 9808 9809 if (idx > MAX_TX_BD_ALLOC) 9810 /* Index out of range. */ 9811 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9812 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9813 /* TX Chain page pointer. */ 9814 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9815 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9816 txbd->tx_bd_haddr_lo); 9817 else { 9818 /* Normal tx_bd entry. */ 9819 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9820 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9821 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9822 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9823 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9824 9825 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9826 if (i>0) 9827 printf("|"); 9828 printf("CONN_FAULT"); 9829 i++; 9830 } 9831 9832 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9833 if (i>0) 9834 printf("|"); 9835 printf("TCP_UDP_CKSUM"); 9836 i++; 9837 } 9838 9839 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9840 if (i>0) 9841 printf("|"); 9842 printf("IP_CKSUM"); 9843 i++; 9844 } 9845 9846 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9847 if (i>0) 9848 printf("|"); 9849 printf("VLAN"); 9850 i++; 9851 } 9852 9853 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9854 if (i>0) 9855 printf("|"); 9856 printf("COAL_NOW"); 9857 i++; 9858 } 9859 9860 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9861 if (i>0) 9862 printf("|"); 9863 printf("DONT_GEN_CRC"); 9864 i++; 9865 } 9866 9867 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 9868 if (i>0) 9869 printf("|"); 9870 printf("START"); 9871 i++; 9872 } 9873 9874 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 9875 if (i>0) 9876 printf("|"); 9877 printf("END"); 9878 i++; 9879 } 9880 9881 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 9882 if (i>0) 9883 printf("|"); 9884 printf("LSO"); 9885 i++; 9886 } 9887 9888 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 9889 if (i>0) 9890 printf("|"); 9891 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 9892 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 9893 } 9894 9895 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 9896 if (i>0) 9897 printf("|"); 9898 printf("SW_FLAGS"); 9899 i++; 9900 } 9901 9902 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 9903 if (i>0) 9904 printf("|"); 9905 printf("SNAP)"); 9906 } else { 9907 printf(")\n"); 9908 } 9909 } 9910 } 9911 9912 /****************************************************************************/ 9913 /* Prints out a rx_bd structure. */ 9914 /* */ 9915 /* Returns: */ 9916 /* Nothing. */ 9917 /****************************************************************************/ 9918 static __attribute__ ((noinline)) void 9919 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 9920 { 9921 if (idx > MAX_RX_BD_ALLOC) 9922 /* Index out of range. */ 9923 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 9924 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 9925 /* RX Chain page pointer. */ 9926 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9927 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 9928 rxbd->rx_bd_haddr_lo); 9929 else 9930 /* Normal rx_bd entry. */ 9931 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 9932 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 9933 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 9934 rxbd->rx_bd_flags); 9935 } 9936 9937 /****************************************************************************/ 9938 /* Prints out a rx_bd structure in the page chain. */ 9939 /* */ 9940 /* Returns: */ 9941 /* Nothing. */ 9942 /****************************************************************************/ 9943 static __attribute__ ((noinline)) void 9944 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9945 { 9946 if (idx > MAX_PG_BD_ALLOC) 9947 /* Index out of range. */ 9948 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9949 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9950 /* Page Chain page pointer. */ 9951 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9952 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9953 else 9954 /* Normal rx_bd entry. */ 9955 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9956 "flags = 0x%08X\n", idx, 9957 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9958 pgbd->rx_bd_len, pgbd->rx_bd_flags); 9959 } 9960 9961 /****************************************************************************/ 9962 /* Prints out a l2_fhdr structure. */ 9963 /* */ 9964 /* Returns: */ 9965 /* Nothing. */ 9966 /****************************************************************************/ 9967 static __attribute__ ((noinline)) void 9968 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9969 { 9970 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9971 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9972 "tcp_udp_xsum = 0x%04X\n", idx, 9973 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9974 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9975 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9976 } 9977 9978 /****************************************************************************/ 9979 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9980 /* */ 9981 /* Returns: */ 9982 /* Nothing. */ 9983 /****************************************************************************/ 9984 static __attribute__ ((noinline)) void 9985 bce_dump_ctx(struct bce_softc *sc, u16 cid) 9986 { 9987 if (cid > TX_CID) { 9988 BCE_PRINTF(" Unknown CID\n"); 9989 return; 9990 } 9991 9992 BCE_PRINTF( 9993 "----------------------------" 9994 " CTX Data " 9995 "----------------------------\n"); 9996 9997 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9998 9999 if (cid == RX_CID) { 10000 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 10001 "producer index\n", 10002 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 10003 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 10004 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10005 BCE_L2CTX_RX_HOST_BSEQ)); 10006 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 10007 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 10008 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 10009 "descriptor address\n", 10010 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 10011 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 10012 "descriptor address\n", 10013 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 10014 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 10015 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10016 BCE_L2CTX_RX_NX_BDIDX)); 10017 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 10018 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10019 BCE_L2CTX_RX_HOST_PG_BDIDX)); 10020 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 10021 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 10022 BCE_L2CTX_RX_PG_BUF_SIZE)); 10023 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 10024 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10025 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 10026 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 10027 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10028 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 10029 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 10030 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10031 BCE_L2CTX_RX_NX_PG_BDIDX)); 10032 } else if (cid == TX_CID) { 10033 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10034 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 10035 CTX_RD(sc, GET_CID_ADDR(cid), 10036 BCE_L2CTX_TX_TYPE_XI)); 10037 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 10038 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 10039 BCE_L2CTX_TX_CMD_TYPE_XI)); 10040 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 10041 "h/w buffer descriptor address\n", 10042 CTX_RD(sc, GET_CID_ADDR(cid), 10043 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 10044 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 10045 "h/w buffer descriptor address\n", 10046 CTX_RD(sc, GET_CID_ADDR(cid), 10047 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 10048 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 10049 "host producer index\n", 10050 CTX_RD(sc, GET_CID_ADDR(cid), 10051 BCE_L2CTX_TX_HOST_BIDX_XI)); 10052 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 10053 "host byte sequence\n", 10054 CTX_RD(sc, GET_CID_ADDR(cid), 10055 BCE_L2CTX_TX_HOST_BSEQ_XI)); 10056 } else { 10057 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 10058 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 10059 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 10060 CTX_RD(sc, GET_CID_ADDR(cid), 10061 BCE_L2CTX_TX_CMD_TYPE)); 10062 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 10063 "h/w buffer descriptor address\n", 10064 CTX_RD(sc, GET_CID_ADDR(cid), 10065 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 10066 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 10067 "h/w buffer descriptor address\n", 10068 CTX_RD(sc, GET_CID_ADDR(cid), 10069 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 10070 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 10071 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10072 BCE_L2CTX_TX_HOST_BIDX)); 10073 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 10074 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10075 BCE_L2CTX_TX_HOST_BSEQ)); 10076 } 10077 } 10078 10079 BCE_PRINTF( 10080 "----------------------------" 10081 " Raw CTX " 10082 "----------------------------\n"); 10083 10084 for (int i = 0x0; i < 0x300; i += 0x10) { 10085 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 10086 CTX_RD(sc, GET_CID_ADDR(cid), i), 10087 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 10088 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 10089 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 10090 } 10091 10092 BCE_PRINTF( 10093 "----------------------------" 10094 "----------------" 10095 "----------------------------\n"); 10096 } 10097 10098 /****************************************************************************/ 10099 /* Prints out the FTQ data. */ 10100 /* */ 10101 /* Returns: */ 10102 /* Nothing. */ 10103 /****************************************************************************/ 10104 static __attribute__ ((noinline)) void 10105 bce_dump_ftqs(struct bce_softc *sc) 10106 { 10107 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 10108 10109 BCE_PRINTF( 10110 "----------------------------" 10111 " FTQ Data " 10112 "----------------------------\n"); 10113 10114 BCE_PRINTF(" FTQ Command Control Depth_Now " 10115 "Max_Depth Valid_Cnt \n"); 10116 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10117 "---------- ----------\n"); 10118 10119 /* Setup the generic statistic counters for the FTQ valid count. */ 10120 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10121 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10122 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10123 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10124 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10125 10126 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10127 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10128 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10129 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10130 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10131 10132 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10133 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10134 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10135 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10136 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10137 10138 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10139 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10140 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10141 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10142 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10143 10144 /* Input queue to the Receive Lookup state machine */ 10145 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10146 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10147 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10148 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10149 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10150 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10151 cmd, ctl, cur_depth, max_depth, valid_cnt); 10152 10153 /* Input queue to the Receive Processor */ 10154 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10155 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10156 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10157 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10158 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10159 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10160 cmd, ctl, cur_depth, max_depth, valid_cnt); 10161 10162 /* Input queue to the Recevie Processor */ 10163 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10164 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10165 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10166 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10167 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10168 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10169 cmd, ctl, cur_depth, max_depth, valid_cnt); 10170 10171 /* Input queue to the Receive Virtual to Physical state machine */ 10172 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10173 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10174 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10175 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10176 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10177 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10178 cmd, ctl, cur_depth, max_depth, valid_cnt); 10179 10180 /* Input queue to the Recevie Virtual to Physical state machine */ 10181 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10182 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10183 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10184 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10185 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10186 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10187 cmd, ctl, cur_depth, max_depth, valid_cnt); 10188 10189 /* Input queue to the Receive Virtual to Physical state machine */ 10190 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10191 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10192 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10193 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10194 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10195 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10196 cmd, ctl, cur_depth, max_depth, valid_cnt); 10197 10198 /* Input queue to the Receive DMA state machine */ 10199 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10200 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10201 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10202 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10203 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10204 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10205 cmd, ctl, cur_depth, max_depth, valid_cnt); 10206 10207 /* Input queue to the Transmit Scheduler state machine */ 10208 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10209 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10210 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10211 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10212 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10213 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10214 cmd, ctl, cur_depth, max_depth, valid_cnt); 10215 10216 /* Input queue to the Transmit Buffer Descriptor state machine */ 10217 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10218 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10219 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10220 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10221 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10222 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10223 cmd, ctl, cur_depth, max_depth, valid_cnt); 10224 10225 /* Input queue to the Transmit Processor */ 10226 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10227 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10228 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10229 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10230 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10231 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10232 cmd, ctl, cur_depth, max_depth, valid_cnt); 10233 10234 /* Input queue to the Transmit DMA state machine */ 10235 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10236 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10237 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10238 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10239 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10240 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10241 cmd, ctl, cur_depth, max_depth, valid_cnt); 10242 10243 /* Input queue to the Transmit Patch-Up Processor */ 10244 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10245 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10246 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10247 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10248 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10249 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10250 cmd, ctl, cur_depth, max_depth, valid_cnt); 10251 10252 /* Input queue to the Transmit Assembler state machine */ 10253 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10254 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10255 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10256 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10257 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10258 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10259 cmd, ctl, cur_depth, max_depth, valid_cnt); 10260 10261 /* Input queue to the Completion Processor */ 10262 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10263 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10264 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10265 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10266 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10267 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10268 cmd, ctl, cur_depth, max_depth, valid_cnt); 10269 10270 /* Input queue to the Completion Processor */ 10271 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10272 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10273 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10274 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10275 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10276 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10277 cmd, ctl, cur_depth, max_depth, valid_cnt); 10278 10279 /* Input queue to the Completion Processor */ 10280 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10281 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10282 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10283 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10284 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10285 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10286 cmd, ctl, cur_depth, max_depth, valid_cnt); 10287 10288 /* Setup the generic statistic counters for the FTQ valid count. */ 10289 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10290 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10291 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10292 10293 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10294 val = val | 10295 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10296 24); 10297 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10298 10299 /* Input queue to the Management Control Processor */ 10300 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10301 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10302 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10303 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10304 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10305 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10306 cmd, ctl, cur_depth, max_depth, valid_cnt); 10307 10308 /* Input queue to the Command Processor */ 10309 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10310 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10311 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10312 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10313 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10314 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10315 cmd, ctl, cur_depth, max_depth, valid_cnt); 10316 10317 /* Input queue to the Completion Scheduler state machine */ 10318 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10319 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10320 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10321 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10322 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10323 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10324 cmd, ctl, cur_depth, max_depth, valid_cnt); 10325 10326 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10327 /* Input queue to the RV2P Command Scheduler */ 10328 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10329 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10330 cur_depth = (ctl & 0xFFC00000) >> 22; 10331 max_depth = (ctl & 0x003FF000) >> 12; 10332 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10333 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10334 cmd, ctl, cur_depth, max_depth, valid_cnt); 10335 } 10336 10337 BCE_PRINTF( 10338 "----------------------------" 10339 "----------------" 10340 "----------------------------\n"); 10341 } 10342 10343 /****************************************************************************/ 10344 /* Prints out the TX chain. */ 10345 /* */ 10346 /* Returns: */ 10347 /* Nothing. */ 10348 /****************************************************************************/ 10349 static __attribute__ ((noinline)) void 10350 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10351 { 10352 struct tx_bd *txbd; 10353 10354 /* First some info about the tx_bd chain structure. */ 10355 BCE_PRINTF( 10356 "----------------------------" 10357 " tx_bd chain " 10358 "----------------------------\n"); 10359 10360 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10361 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10362 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10363 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10364 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10365 10366 BCE_PRINTF( 10367 "----------------------------" 10368 " tx_bd data " 10369 "----------------------------\n"); 10370 10371 /* Now print out a decoded list of TX buffer descriptors. */ 10372 for (int i = 0; i < count; i++) { 10373 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10374 bce_dump_txbd(sc, tx_prod, txbd); 10375 tx_prod++; 10376 } 10377 10378 BCE_PRINTF( 10379 "----------------------------" 10380 "----------------" 10381 "----------------------------\n"); 10382 } 10383 10384 /****************************************************************************/ 10385 /* Prints out the RX chain. */ 10386 /* */ 10387 /* Returns: */ 10388 /* Nothing. */ 10389 /****************************************************************************/ 10390 static __attribute__ ((noinline)) void 10391 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10392 { 10393 struct rx_bd *rxbd; 10394 10395 /* First some info about the rx_bd chain structure. */ 10396 BCE_PRINTF( 10397 "----------------------------" 10398 " rx_bd chain " 10399 "----------------------------\n"); 10400 10401 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10402 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10403 10404 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10405 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10406 10407 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10408 10409 BCE_PRINTF( 10410 "----------------------------" 10411 " rx_bd data " 10412 "----------------------------\n"); 10413 10414 /* Now print out the rx_bd's themselves. */ 10415 for (int i = 0; i < count; i++) { 10416 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10417 bce_dump_rxbd(sc, rx_prod, rxbd); 10418 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10419 } 10420 10421 BCE_PRINTF( 10422 "----------------------------" 10423 "----------------" 10424 "----------------------------\n"); 10425 } 10426 10427 /****************************************************************************/ 10428 /* Prints out the page chain. */ 10429 /* */ 10430 /* Returns: */ 10431 /* Nothing. */ 10432 /****************************************************************************/ 10433 static __attribute__ ((noinline)) void 10434 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10435 { 10436 struct rx_bd *pgbd; 10437 10438 /* First some info about the page chain structure. */ 10439 BCE_PRINTF( 10440 "----------------------------" 10441 " page chain " 10442 "----------------------------\n"); 10443 10444 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10445 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10446 10447 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10448 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10449 10450 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10451 10452 BCE_PRINTF( 10453 "----------------------------" 10454 " page data " 10455 "----------------------------\n"); 10456 10457 /* Now print out the rx_bd's themselves. */ 10458 for (int i = 0; i < count; i++) { 10459 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10460 bce_dump_pgbd(sc, pg_prod, pgbd); 10461 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10462 } 10463 10464 BCE_PRINTF( 10465 "----------------------------" 10466 "----------------" 10467 "----------------------------\n"); 10468 } 10469 10470 #define BCE_PRINT_RX_CONS(arg) \ 10471 if (sblk->status_rx_quick_consumer_index##arg) \ 10472 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10473 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10474 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10475 arg); 10476 10477 #define BCE_PRINT_TX_CONS(arg) \ 10478 if (sblk->status_tx_quick_consumer_index##arg) \ 10479 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10480 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10481 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10482 arg); 10483 10484 /****************************************************************************/ 10485 /* Prints out the status block from host memory. */ 10486 /* */ 10487 /* Returns: */ 10488 /* Nothing. */ 10489 /****************************************************************************/ 10490 static __attribute__ ((noinline)) void 10491 bce_dump_status_block(struct bce_softc *sc) 10492 { 10493 struct status_block *sblk; 10494 10495 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 10496 10497 sblk = sc->status_block; 10498 10499 BCE_PRINTF( 10500 "----------------------------" 10501 " Status Block " 10502 "----------------------------\n"); 10503 10504 /* Theses indices are used for normal L2 drivers. */ 10505 BCE_PRINTF(" 0x%08X - attn_bits\n", 10506 sblk->status_attn_bits); 10507 10508 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10509 sblk->status_attn_bits_ack); 10510 10511 BCE_PRINT_RX_CONS(0); 10512 BCE_PRINT_TX_CONS(0) 10513 10514 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10515 10516 /* Theses indices are not used for normal L2 drivers. */ 10517 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10518 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10519 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10520 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10521 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10522 10523 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10524 10525 if (sblk->status_completion_producer_index || 10526 sblk->status_cmd_consumer_index) 10527 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10528 sblk->status_completion_producer_index, 10529 sblk->status_cmd_consumer_index); 10530 10531 BCE_PRINTF( 10532 "----------------------------" 10533 "----------------" 10534 "----------------------------\n"); 10535 } 10536 10537 #define BCE_PRINT_64BIT_STAT(arg) \ 10538 if (sblk->arg##_lo || sblk->arg##_hi) \ 10539 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10540 sblk->arg##_lo, #arg); 10541 10542 #define BCE_PRINT_32BIT_STAT(arg) \ 10543 if (sblk->arg) \ 10544 BCE_PRINTF(" 0x%08X : %s\n", \ 10545 sblk->arg, #arg); 10546 10547 /****************************************************************************/ 10548 /* Prints out the statistics block from host memory. */ 10549 /* */ 10550 /* Returns: */ 10551 /* Nothing. */ 10552 /****************************************************************************/ 10553 static __attribute__ ((noinline)) void 10554 bce_dump_stats_block(struct bce_softc *sc) 10555 { 10556 struct statistics_block *sblk; 10557 10558 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 10559 10560 sblk = sc->stats_block; 10561 10562 BCE_PRINTF( 10563 "---------------" 10564 " Stats Block (All Stats Not Shown Are 0) " 10565 "---------------\n"); 10566 10567 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10568 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10569 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10570 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10571 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10572 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10573 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10574 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10575 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10576 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10577 BCE_PRINT_32BIT_STAT( 10578 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10579 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10580 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10581 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10582 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10583 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10584 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10585 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10586 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10587 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10588 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10589 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10590 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10591 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10592 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10593 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10594 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10595 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10596 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10597 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10598 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10599 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10600 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10601 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10602 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10603 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10604 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10605 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10606 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10607 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10608 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10609 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10610 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10611 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10612 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10613 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10614 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10615 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10616 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10617 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10618 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10619 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10620 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10621 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10622 10623 BCE_PRINTF( 10624 "----------------------------" 10625 "----------------" 10626 "----------------------------\n"); 10627 } 10628 10629 /****************************************************************************/ 10630 /* Prints out a summary of the driver state. */ 10631 /* */ 10632 /* Returns: */ 10633 /* Nothing. */ 10634 /****************************************************************************/ 10635 static __attribute__ ((noinline)) void 10636 bce_dump_driver_state(struct bce_softc *sc) 10637 { 10638 u32 val_hi, val_lo; 10639 10640 BCE_PRINTF( 10641 "-----------------------------" 10642 " Driver State " 10643 "-----------------------------\n"); 10644 10645 val_hi = BCE_ADDR_HI(sc); 10646 val_lo = BCE_ADDR_LO(sc); 10647 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10648 "address\n", val_hi, val_lo); 10649 10650 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10651 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10652 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10653 "address\n", val_hi, val_lo); 10654 10655 val_hi = BCE_ADDR_HI(sc->status_block); 10656 val_lo = BCE_ADDR_LO(sc->status_block); 10657 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10658 "virtual address\n", val_hi, val_lo); 10659 10660 val_hi = BCE_ADDR_HI(sc->stats_block); 10661 val_lo = BCE_ADDR_LO(sc->stats_block); 10662 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10663 "virtual address\n", val_hi, val_lo); 10664 10665 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10666 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10667 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10668 "virtual adddress\n", val_hi, val_lo); 10669 10670 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10671 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10672 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10673 "virtual address\n", val_hi, val_lo); 10674 10675 if (bce_hdr_split == TRUE) { 10676 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10677 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10678 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10679 "virtual address\n", val_hi, val_lo); 10680 } 10681 10682 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10683 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10684 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10685 "virtual address\n", val_hi, val_lo); 10686 10687 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10688 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10689 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10690 "virtual address\n", val_hi, val_lo); 10691 10692 if (bce_hdr_split == TRUE) { 10693 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10694 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10695 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10696 "virtual address\n", val_hi, val_lo); 10697 } 10698 10699 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10700 "h/w intrs\n", 10701 (long long unsigned int) sc->interrupts_generated); 10702 10703 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10704 "rx interrupts handled\n", 10705 (long long unsigned int) sc->interrupts_rx); 10706 10707 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10708 "tx interrupts handled\n", 10709 (long long unsigned int) sc->interrupts_tx); 10710 10711 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10712 "phy interrupts handled\n", 10713 (long long unsigned int) sc->phy_interrupts); 10714 10715 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10716 "status block index\n", sc->last_status_idx); 10717 10718 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10719 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10720 10721 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10722 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10723 10724 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10725 "byte seq index\n", sc->tx_prod_bseq); 10726 10727 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10728 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10729 10730 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10731 "tx_bd's\n", sc->used_tx_bd); 10732 10733 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10734 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10735 10736 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10737 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10738 10739 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10740 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10741 10742 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10743 "byte seq index\n", sc->rx_prod_bseq); 10744 10745 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10746 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10747 10748 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10749 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10750 10751 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10752 "rx_bd's\n", sc->free_rx_bd); 10753 10754 if (bce_hdr_split == TRUE) { 10755 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10756 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10757 10758 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10759 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10760 10761 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10762 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10763 } 10764 10765 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10766 "rx_bd's\n", sc->free_pg_bd); 10767 10768 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10769 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10770 10771 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10772 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10773 10774 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10775 "bce mac flags\n", sc->bce_flags); 10776 10777 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10778 "bce phy flags\n", sc->bce_phy_flags); 10779 10780 BCE_PRINTF( 10781 "----------------------------" 10782 "----------------" 10783 "----------------------------\n"); 10784 } 10785 10786 /****************************************************************************/ 10787 /* Prints out the hardware state through a summary of important register, */ 10788 /* followed by a complete register dump. */ 10789 /* */ 10790 /* Returns: */ 10791 /* Nothing. */ 10792 /****************************************************************************/ 10793 static __attribute__ ((noinline)) void 10794 bce_dump_hw_state(struct bce_softc *sc) 10795 { 10796 u32 val; 10797 10798 BCE_PRINTF( 10799 "----------------------------" 10800 " Hardware State " 10801 "----------------------------\n"); 10802 10803 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10804 10805 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10806 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10807 val, BCE_MISC_ENABLE_STATUS_BITS); 10808 10809 val = REG_RD(sc, BCE_DMA_STATUS); 10810 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10811 val, BCE_DMA_STATUS); 10812 10813 val = REG_RD(sc, BCE_CTX_STATUS); 10814 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10815 val, BCE_CTX_STATUS); 10816 10817 val = REG_RD(sc, BCE_EMAC_STATUS); 10818 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10819 val, BCE_EMAC_STATUS); 10820 10821 val = REG_RD(sc, BCE_RPM_STATUS); 10822 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10823 val, BCE_RPM_STATUS); 10824 10825 /* ToDo: Create a #define for this constant. */ 10826 val = REG_RD(sc, 0x2004); 10827 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10828 val, 0x2004); 10829 10830 val = REG_RD(sc, BCE_RV2P_STATUS); 10831 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10832 val, BCE_RV2P_STATUS); 10833 10834 /* ToDo: Create a #define for this constant. */ 10835 val = REG_RD(sc, 0x2c04); 10836 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10837 val, 0x2c04); 10838 10839 val = REG_RD(sc, BCE_TBDR_STATUS); 10840 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10841 val, BCE_TBDR_STATUS); 10842 10843 val = REG_RD(sc, BCE_TDMA_STATUS); 10844 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10845 val, BCE_TDMA_STATUS); 10846 10847 val = REG_RD(sc, BCE_HC_STATUS); 10848 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10849 val, BCE_HC_STATUS); 10850 10851 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10852 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10853 val, BCE_TXP_CPU_STATE); 10854 10855 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10856 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10857 val, BCE_TPAT_CPU_STATE); 10858 10859 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10860 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10861 val, BCE_RXP_CPU_STATE); 10862 10863 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10864 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10865 val, BCE_COM_CPU_STATE); 10866 10867 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10868 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 10869 val, BCE_MCP_CPU_STATE); 10870 10871 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10872 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10873 val, BCE_CP_CPU_STATE); 10874 10875 BCE_PRINTF( 10876 "----------------------------" 10877 "----------------" 10878 "----------------------------\n"); 10879 10880 BCE_PRINTF( 10881 "----------------------------" 10882 " Register Dump " 10883 "----------------------------\n"); 10884 10885 for (int i = 0x400; i < 0x8000; i += 0x10) { 10886 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10887 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10888 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10889 } 10890 10891 BCE_PRINTF( 10892 "----------------------------" 10893 "----------------" 10894 "----------------------------\n"); 10895 } 10896 10897 /****************************************************************************/ 10898 /* Prints out the contentst of shared memory which is used for host driver */ 10899 /* to bootcode firmware communication. */ 10900 /* */ 10901 /* Returns: */ 10902 /* Nothing. */ 10903 /****************************************************************************/ 10904 static __attribute__ ((noinline)) void 10905 bce_dump_shmem_state(struct bce_softc *sc) 10906 { 10907 BCE_PRINTF( 10908 "----------------------------" 10909 " Hardware State " 10910 "----------------------------\n"); 10911 10912 BCE_PRINTF("0x%08X - Shared memory base address\n", 10913 sc->bce_shmem_base); 10914 BCE_PRINTF("%s - bootcode version\n", 10915 sc->bce_bc_ver); 10916 10917 BCE_PRINTF( 10918 "----------------------------" 10919 " Shared Mem " 10920 "----------------------------\n"); 10921 10922 for (int i = 0x0; i < 0x200; i += 0x10) { 10923 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10924 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 10925 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 10926 } 10927 10928 BCE_PRINTF( 10929 "----------------------------" 10930 "----------------" 10931 "----------------------------\n"); 10932 } 10933 10934 /****************************************************************************/ 10935 /* Prints out the mailbox queue registers. */ 10936 /* */ 10937 /* Returns: */ 10938 /* Nothing. */ 10939 /****************************************************************************/ 10940 static __attribute__ ((noinline)) void 10941 bce_dump_mq_regs(struct bce_softc *sc) 10942 { 10943 BCE_PRINTF( 10944 "----------------------------" 10945 " MQ Regs " 10946 "----------------------------\n"); 10947 10948 BCE_PRINTF( 10949 "----------------------------" 10950 "----------------" 10951 "----------------------------\n"); 10952 10953 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10954 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10955 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10956 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10957 } 10958 10959 BCE_PRINTF( 10960 "----------------------------" 10961 "----------------" 10962 "----------------------------\n"); 10963 } 10964 10965 /****************************************************************************/ 10966 /* Prints out the bootcode state. */ 10967 /* */ 10968 /* Returns: */ 10969 /* Nothing. */ 10970 /****************************************************************************/ 10971 static __attribute__ ((noinline)) void 10972 bce_dump_bc_state(struct bce_softc *sc) 10973 { 10974 u32 val; 10975 10976 BCE_PRINTF( 10977 "----------------------------" 10978 " Bootcode State " 10979 "----------------------------\n"); 10980 10981 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10982 10983 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10984 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10985 val, BCE_BC_RESET_TYPE); 10986 10987 val = bce_shmem_rd(sc, BCE_BC_STATE); 10988 BCE_PRINTF("0x%08X - (0x%06X) state\n", 10989 val, BCE_BC_STATE); 10990 10991 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10992 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10993 val, BCE_BC_STATE_CONDITION); 10994 10995 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10996 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10997 val, BCE_BC_STATE_DEBUG_CMD); 10998 10999 BCE_PRINTF( 11000 "----------------------------" 11001 "----------------" 11002 "----------------------------\n"); 11003 } 11004 11005 /****************************************************************************/ 11006 /* Prints out the TXP processor state. */ 11007 /* */ 11008 /* Returns: */ 11009 /* Nothing. */ 11010 /****************************************************************************/ 11011 static __attribute__ ((noinline)) void 11012 bce_dump_txp_state(struct bce_softc *sc, int regs) 11013 { 11014 u32 val; 11015 u32 fw_version[3]; 11016 11017 BCE_PRINTF( 11018 "----------------------------" 11019 " TXP State " 11020 "----------------------------\n"); 11021 11022 for (int i = 0; i < 3; i++) 11023 fw_version[i] = htonl(REG_RD_IND(sc, 11024 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 11025 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11026 11027 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 11028 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 11029 val, BCE_TXP_CPU_MODE); 11030 11031 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11032 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11033 val, BCE_TXP_CPU_STATE); 11034 11035 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 11036 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 11037 val, BCE_TXP_CPU_EVENT_MASK); 11038 11039 if (regs) { 11040 BCE_PRINTF( 11041 "----------------------------" 11042 " Register Dump " 11043 "----------------------------\n"); 11044 11045 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 11046 /* Skip the big blank spaces */ 11047 if (i < 0x454000 && i > 0x5ffff) 11048 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11049 "0x%08X 0x%08X\n", i, 11050 REG_RD_IND(sc, i), 11051 REG_RD_IND(sc, i + 0x4), 11052 REG_RD_IND(sc, i + 0x8), 11053 REG_RD_IND(sc, i + 0xC)); 11054 } 11055 } 11056 11057 BCE_PRINTF( 11058 "----------------------------" 11059 "----------------" 11060 "----------------------------\n"); 11061 } 11062 11063 /****************************************************************************/ 11064 /* Prints out the RXP processor state. */ 11065 /* */ 11066 /* Returns: */ 11067 /* Nothing. */ 11068 /****************************************************************************/ 11069 static __attribute__ ((noinline)) void 11070 bce_dump_rxp_state(struct bce_softc *sc, int regs) 11071 { 11072 u32 val; 11073 u32 fw_version[3]; 11074 11075 BCE_PRINTF( 11076 "----------------------------" 11077 " RXP State " 11078 "----------------------------\n"); 11079 11080 for (int i = 0; i < 3; i++) 11081 fw_version[i] = htonl(REG_RD_IND(sc, 11082 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 11083 11084 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11085 11086 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 11087 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 11088 val, BCE_RXP_CPU_MODE); 11089 11090 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11091 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11092 val, BCE_RXP_CPU_STATE); 11093 11094 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 11095 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 11096 val, BCE_RXP_CPU_EVENT_MASK); 11097 11098 if (regs) { 11099 BCE_PRINTF( 11100 "----------------------------" 11101 " Register Dump " 11102 "----------------------------\n"); 11103 11104 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11105 /* Skip the big blank sapces */ 11106 if (i < 0xc5400 && i > 0xdffff) 11107 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11108 "0x%08X 0x%08X\n", i, 11109 REG_RD_IND(sc, i), 11110 REG_RD_IND(sc, i + 0x4), 11111 REG_RD_IND(sc, i + 0x8), 11112 REG_RD_IND(sc, i + 0xC)); 11113 } 11114 } 11115 11116 BCE_PRINTF( 11117 "----------------------------" 11118 "----------------" 11119 "----------------------------\n"); 11120 } 11121 11122 /****************************************************************************/ 11123 /* Prints out the TPAT processor state. */ 11124 /* */ 11125 /* Returns: */ 11126 /* Nothing. */ 11127 /****************************************************************************/ 11128 static __attribute__ ((noinline)) void 11129 bce_dump_tpat_state(struct bce_softc *sc, int regs) 11130 { 11131 u32 val; 11132 u32 fw_version[3]; 11133 11134 BCE_PRINTF( 11135 "----------------------------" 11136 " TPAT State " 11137 "----------------------------\n"); 11138 11139 for (int i = 0; i < 3; i++) 11140 fw_version[i] = htonl(REG_RD_IND(sc, 11141 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11142 11143 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11144 11145 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11146 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11147 val, BCE_TPAT_CPU_MODE); 11148 11149 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11150 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11151 val, BCE_TPAT_CPU_STATE); 11152 11153 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11154 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11155 val, BCE_TPAT_CPU_EVENT_MASK); 11156 11157 if (regs) { 11158 BCE_PRINTF( 11159 "----------------------------" 11160 " Register Dump " 11161 "----------------------------\n"); 11162 11163 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11164 /* Skip the big blank spaces */ 11165 if (i < 0x854000 && i > 0x9ffff) 11166 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11167 "0x%08X 0x%08X\n", i, 11168 REG_RD_IND(sc, i), 11169 REG_RD_IND(sc, i + 0x4), 11170 REG_RD_IND(sc, i + 0x8), 11171 REG_RD_IND(sc, i + 0xC)); 11172 } 11173 } 11174 11175 BCE_PRINTF( 11176 "----------------------------" 11177 "----------------" 11178 "----------------------------\n"); 11179 } 11180 11181 /****************************************************************************/ 11182 /* Prints out the Command Procesor (CP) state. */ 11183 /* */ 11184 /* Returns: */ 11185 /* Nothing. */ 11186 /****************************************************************************/ 11187 static __attribute__ ((noinline)) void 11188 bce_dump_cp_state(struct bce_softc *sc, int regs) 11189 { 11190 u32 val; 11191 u32 fw_version[3]; 11192 11193 BCE_PRINTF( 11194 "----------------------------" 11195 " CP State " 11196 "----------------------------\n"); 11197 11198 for (int i = 0; i < 3; i++) 11199 fw_version[i] = htonl(REG_RD_IND(sc, 11200 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11201 11202 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11203 11204 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11205 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11206 val, BCE_CP_CPU_MODE); 11207 11208 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11209 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11210 val, BCE_CP_CPU_STATE); 11211 11212 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11213 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11214 BCE_CP_CPU_EVENT_MASK); 11215 11216 if (regs) { 11217 BCE_PRINTF( 11218 "----------------------------" 11219 " Register Dump " 11220 "----------------------------\n"); 11221 11222 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11223 /* Skip the big blank spaces */ 11224 if (i < 0x185400 && i > 0x19ffff) 11225 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11226 "0x%08X 0x%08X\n", i, 11227 REG_RD_IND(sc, i), 11228 REG_RD_IND(sc, i + 0x4), 11229 REG_RD_IND(sc, i + 0x8), 11230 REG_RD_IND(sc, i + 0xC)); 11231 } 11232 } 11233 11234 BCE_PRINTF( 11235 "----------------------------" 11236 "----------------" 11237 "----------------------------\n"); 11238 } 11239 11240 /****************************************************************************/ 11241 /* Prints out the Completion Procesor (COM) state. */ 11242 /* */ 11243 /* Returns: */ 11244 /* Nothing. */ 11245 /****************************************************************************/ 11246 static __attribute__ ((noinline)) void 11247 bce_dump_com_state(struct bce_softc *sc, int regs) 11248 { 11249 u32 val; 11250 u32 fw_version[4]; 11251 11252 BCE_PRINTF( 11253 "----------------------------" 11254 " COM State " 11255 "----------------------------\n"); 11256 11257 for (int i = 0; i < 3; i++) 11258 fw_version[i] = htonl(REG_RD_IND(sc, 11259 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11260 11261 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11262 11263 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11264 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11265 val, BCE_COM_CPU_MODE); 11266 11267 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11268 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11269 val, BCE_COM_CPU_STATE); 11270 11271 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11272 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11273 BCE_COM_CPU_EVENT_MASK); 11274 11275 if (regs) { 11276 BCE_PRINTF( 11277 "----------------------------" 11278 " Register Dump " 11279 "----------------------------\n"); 11280 11281 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11282 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11283 "0x%08X 0x%08X\n", i, 11284 REG_RD_IND(sc, i), 11285 REG_RD_IND(sc, i + 0x4), 11286 REG_RD_IND(sc, i + 0x8), 11287 REG_RD_IND(sc, i + 0xC)); 11288 } 11289 } 11290 11291 BCE_PRINTF( 11292 "----------------------------" 11293 "----------------" 11294 "----------------------------\n"); 11295 } 11296 11297 /****************************************************************************/ 11298 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11299 /* */ 11300 /* Returns: */ 11301 /* Nothing. */ 11302 /****************************************************************************/ 11303 static __attribute__ ((noinline)) void 11304 bce_dump_rv2p_state(struct bce_softc *sc) 11305 { 11306 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11307 11308 BCE_PRINTF( 11309 "----------------------------" 11310 " RV2P State " 11311 "----------------------------\n"); 11312 11313 /* Stall the RV2P processors. */ 11314 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11315 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11316 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11317 11318 /* Read the firmware version. */ 11319 val = 0x00000001; 11320 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11321 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11322 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11323 BCE_RV2P_INSTR_HIGH_HIGH; 11324 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11325 fw_ver_high, fw_ver_low); 11326 11327 val = 0x00000001; 11328 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11329 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11330 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11331 BCE_RV2P_INSTR_HIGH_HIGH; 11332 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11333 fw_ver_high, fw_ver_low); 11334 11335 /* Resume the RV2P processors. */ 11336 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11337 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11338 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11339 11340 /* Fetch the program counter value. */ 11341 val = 0x68007800; 11342 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11343 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11344 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11345 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11346 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11347 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11348 11349 /* Fetch the program counter value again to see if it is advancing. */ 11350 val = 0x68007800; 11351 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11352 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11353 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11354 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11355 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11356 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11357 11358 BCE_PRINTF( 11359 "----------------------------" 11360 "----------------" 11361 "----------------------------\n"); 11362 } 11363 11364 /****************************************************************************/ 11365 /* Prints out the driver state and then enters the debugger. */ 11366 /* */ 11367 /* Returns: */ 11368 /* Nothing. */ 11369 /****************************************************************************/ 11370 static __attribute__ ((noinline)) void 11371 bce_breakpoint(struct bce_softc *sc) 11372 { 11373 11374 /* 11375 * Unreachable code to silence compiler warnings 11376 * about unused functions. 11377 */ 11378 if (0) { 11379 bce_freeze_controller(sc); 11380 bce_unfreeze_controller(sc); 11381 bce_dump_enet(sc, NULL); 11382 bce_dump_txbd(sc, 0, NULL); 11383 bce_dump_rxbd(sc, 0, NULL); 11384 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11385 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11386 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11387 bce_dump_l2fhdr(sc, 0, NULL); 11388 bce_dump_ctx(sc, RX_CID); 11389 bce_dump_ftqs(sc); 11390 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11391 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11392 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11393 bce_dump_status_block(sc); 11394 bce_dump_stats_block(sc); 11395 bce_dump_driver_state(sc); 11396 bce_dump_hw_state(sc); 11397 bce_dump_bc_state(sc); 11398 bce_dump_txp_state(sc, 0); 11399 bce_dump_rxp_state(sc, 0); 11400 bce_dump_tpat_state(sc, 0); 11401 bce_dump_cp_state(sc, 0); 11402 bce_dump_com_state(sc, 0); 11403 bce_dump_rv2p_state(sc); 11404 bce_dump_pgbd(sc, 0, NULL); 11405 } 11406 11407 bce_dump_status_block(sc); 11408 bce_dump_driver_state(sc); 11409 11410 /* Call the debugger. */ 11411 breakpoint(); 11412 } 11413 #endif 11414