xref: /freebsd/sys/dev/axgbe/xgbe-drv.c (revision 8ddb146abcdf061be9f2c0db7e391697dafad85c)
1 /*
2  * AMD 10Gb Ethernet driver
3  *
4  * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
5  *
6  * This file is available to you under your choice of the following two
7  * licenses:
8  *
9  * License 1: GPLv2
10  *
11  * This file is free software; you may copy, redistribute and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation, either version 2 of the License, or (at
14  * your option) any later version.
15  *
16  * This file is distributed in the hope that it will be useful, but
17  * WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19  * General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
23  *
24  * This file incorporates work covered by the following copyright and
25  * permission notice:
26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
29  *     and you.
30  *
31  *     The Software IS NOT an item of Licensed Software or Licensed Product
32  *     under any End User Software License Agreement or Agreement for Licensed
33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
34  *     granted, free of charge, to any person obtaining a copy of this software
35  *     annotated with this license and the Software, to deal in the Software
36  *     without restriction, including without limitation the rights to use,
37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38  *     of the Software, and to permit persons to whom the Software is furnished
39  *     to do so, subject to the following conditions:
40  *
41  *     The above copyright notice and this permission notice shall be included
42  *     in all copies or substantial portions of the Software.
43  *
44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54  *     THE POSSIBILITY OF SUCH DAMAGE.
55  *
56  *
57  * License 2: Modified BSD
58  *
59  * Redistribution and use in source and binary forms, with or without
60  * modification, are permitted provided that the following conditions are met:
61  *     * Redistributions of source code must retain the above copyright
62  *       notice, this list of conditions and the following disclaimer.
63  *     * Redistributions in binary form must reproduce the above copyright
64  *       notice, this list of conditions and the following disclaimer in the
65  *       documentation and/or other materials provided with the distribution.
66  *     * Neither the name of Advanced Micro Devices, Inc. nor the
67  *       names of its contributors may be used to endorse or promote products
68  *       derived from this software without specific prior written permission.
69  *
70  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
71  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
72  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
73  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
74  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
75  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
76  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
77  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80  *
81  * This file incorporates work covered by the following copyright and
82  * permission notice:
83  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
84  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
85  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
86  *     and you.
87  *
88  *     The Software IS NOT an item of Licensed Software or Licensed Product
89  *     under any End User Software License Agreement or Agreement for Licensed
90  *     Product with Synopsys or any supplement thereto.  Permission is hereby
91  *     granted, free of charge, to any person obtaining a copy of this software
92  *     annotated with this license and the Software, to deal in the Software
93  *     without restriction, including without limitation the rights to use,
94  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
95  *     of the Software, and to permit persons to whom the Software is furnished
96  *     to do so, subject to the following conditions:
97  *
98  *     The above copyright notice and this permission notice shall be included
99  *     in all copies or substantial portions of the Software.
100  *
101  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
102  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
103  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
104  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
105  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
106  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
107  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
108  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
109  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
110  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
111  *     THE POSSIBILITY OF SUCH DAMAGE.
112  */
113 
114 #include <sys/cdefs.h>
115 __FBSDID("$FreeBSD$");
116 
117 #include "xgbe.h"
118 #include "xgbe-common.h"
119 
120 int
121 xgbe_calc_rx_buf_size(struct ifnet *netdev, unsigned int mtu)
122 {
123 	unsigned int rx_buf_size;
124 
125 	if (mtu > XGMAC_JUMBO_PACKET_MTU)
126 		return (-EINVAL);
127 
128 	rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
129 	rx_buf_size = min(max(rx_buf_size, XGBE_RX_MIN_BUF_SIZE), PAGE_SIZE);
130 	rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
131 	    ~(XGBE_RX_BUF_ALIGN - 1);
132 
133 	return (rx_buf_size);
134 }
135 
136 void
137 xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
138 {
139 	unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
140 	struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
141 
142 	DBGPR("-->xgbe_get_all_hw_features\n");
143 
144 	mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
145 	mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
146 	mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
147 
148 	memset(hw_feat, 0, sizeof(*hw_feat));
149 
150 	hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
151 
152 	/* Hardware feature register 0 */
153 	hw_feat->gmii	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
154 	hw_feat->vlhash	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
155 	hw_feat->sma	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
156 	hw_feat->rwk	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
157 	hw_feat->mgk	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
158 	hw_feat->mmc	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
159 	hw_feat->aoe	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
160 	hw_feat->ts	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
161 	hw_feat->eee	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
162 	hw_feat->tx_coe	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
163 	hw_feat->rx_coe	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
164 	hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
165 					      ADDMACADRSEL);
166 	hw_feat->ts_src	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
167 	hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
168 	hw_feat->vxn	= XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
169 
170 	/* Hardware feature register 1 */
171 	hw_feat->rx_fifo_size	= XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
172 						RXFIFOSIZE);
173 	hw_feat->tx_fifo_size	= XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
174 						TXFIFOSIZE);
175 	hw_feat->adv_ts_hi	= XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
176 	hw_feat->dma_width	= XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
177 	hw_feat->dcb		= XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
178 	hw_feat->sph		= XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
179 	hw_feat->tso		= XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
180 	hw_feat->dma_debug	= XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
181 	hw_feat->rss		= XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
182 	hw_feat->tc_cnt		= XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
183 	hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
184 						  HASHTBLSZ);
185 	hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
186 						  L3L4FNUM);
187 
188 	/* Hardware feature register 2 */
189 	hw_feat->rx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
190 	hw_feat->tx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
191 	hw_feat->rx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
192 	hw_feat->tx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
193 	hw_feat->pps_out_num  = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
194 	hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
195 
196 	/* Translate the Hash Table size into actual number */
197 	switch (hw_feat->hash_table_size) {
198 	case 0:
199 		break;
200 	case 1:
201 		hw_feat->hash_table_size = 64;
202 		break;
203 	case 2:
204 		hw_feat->hash_table_size = 128;
205 		break;
206 	case 3:
207 		hw_feat->hash_table_size = 256;
208 		break;
209 	}
210 
211 	/* Translate the address width setting into actual number */
212 	switch (hw_feat->dma_width) {
213 	case 0:
214 		hw_feat->dma_width = 32;
215 		break;
216 	case 1:
217 		hw_feat->dma_width = 40;
218 		break;
219 	case 2:
220 		hw_feat->dma_width = 48;
221 		break;
222 	default:
223 		hw_feat->dma_width = 32;
224 	}
225 
226 	/* The Queue, Channel and TC counts are zero based so increment them
227 	 * to get the actual number
228 	 */
229 	hw_feat->rx_q_cnt++;
230 	hw_feat->tx_q_cnt++;
231 	hw_feat->rx_ch_cnt++;
232 	hw_feat->tx_ch_cnt++;
233 	hw_feat->tc_cnt++;
234 
235 	/* Translate the fifo sizes into actual numbers */
236 	hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
237 	hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
238 	DBGPR("%s: Tx fifo 0x%x Rx fifo 0x%x\n", __func__,
239 	    hw_feat->tx_fifo_size, hw_feat->rx_fifo_size);
240 
241 	DBGPR("Hardware features:\n");
242 
243 	/* Hardware feature register 0 */
244 	DBGPR("  1GbE support		   : %s\n",
245 	    hw_feat->gmii ? "yes" : "no");
246 	DBGPR("  VLAN hash filter	   : %s\n",
247 	    hw_feat->vlhash ? "yes" : "no");
248 	DBGPR("  MDIO interface		   : %s\n",
249 	    hw_feat->sma ? "yes" : "no");
250 	DBGPR("  Wake-up packet support    : %s\n",
251 	    hw_feat->rwk ? "yes" : "no");
252 	DBGPR("  Magic packet support      : %s\n",
253 	    hw_feat->mgk ? "yes" : "no");
254 	DBGPR("  Management counters       : %s\n",
255 	    hw_feat->mmc ? "yes" : "no");
256 	DBGPR("  ARP offload		   : %s\n",
257 	    hw_feat->aoe ? "yes" : "no");
258 	DBGPR("  IEEE 1588-2008 Timestamp  : %s\n",
259 	    hw_feat->ts ? "yes" : "no");
260 	DBGPR("  Energy Efficient Ethernet : %s\n",
261 	    hw_feat->eee ? "yes" : "no");
262 	DBGPR("  TX checksum offload       : %s\n",
263 	    hw_feat->tx_coe ? "yes" : "no");
264 	DBGPR("  RX checksum offload       : %s\n",
265 	    hw_feat->rx_coe ? "yes" : "no");
266 	DBGPR("  Additional MAC addresses  : %u\n",
267 	    hw_feat->addn_mac);
268 	DBGPR("  Timestamp source	   : %s\n",
269 	    (hw_feat->ts_src == 1) ? "internal" :
270 	    (hw_feat->ts_src == 2) ? "external" :
271 	    (hw_feat->ts_src == 3) ? "internal/external" : "n/a");
272 	DBGPR("  SA/VLAN insertion	   : %s\n",
273 	    hw_feat->sa_vlan_ins ? "yes" : "no");
274 
275 	/* Hardware feature register 1 */
276 	DBGPR("  RX fifo size		   : %u\n",
277 	    hw_feat->rx_fifo_size);
278 	DBGPR("  TX fifo size		   : %u\n",
279 	    hw_feat->tx_fifo_size);
280 	DBGPR("  IEEE 1588 high word       : %s\n",
281 	    hw_feat->adv_ts_hi ? "yes" : "no");
282 	DBGPR("  DMA width		   : %u\n",
283 	    hw_feat->dma_width);
284 	DBGPR("  Data Center Bridging      : %s\n",
285 	    hw_feat->dcb ? "yes" : "no");
286 	DBGPR("  Split header		   : %s\n",
287 	    hw_feat->sph ? "yes" : "no");
288 	DBGPR("  TCP Segmentation Offload  : %s\n",
289 	    hw_feat->tso ? "yes" : "no");
290 	DBGPR("  Debug memory interface    : %s\n",
291 	    hw_feat->dma_debug ? "yes" : "no");
292 	DBGPR("  Receive Side Scaling      : %s\n",
293 	    hw_feat->rss ? "yes" : "no");
294 	DBGPR("  Traffic Class count       : %u\n",
295 	    hw_feat->tc_cnt);
296 	DBGPR("  Hash table size	   : %u\n",
297 	    hw_feat->hash_table_size);
298 	DBGPR("  L3/L4 Filters		   : %u\n",
299 	    hw_feat->l3l4_filter_num);
300 
301 	/* Hardware feature register 2 */
302 	DBGPR("  RX queue count		   : %u\n",
303 	    hw_feat->rx_q_cnt);
304 	DBGPR("  TX queue count		   : %u\n",
305 	    hw_feat->tx_q_cnt);
306 	DBGPR("  RX DMA channel count      : %u\n",
307 	    hw_feat->rx_ch_cnt);
308 	DBGPR("  TX DMA channel count      : %u\n",
309 	    hw_feat->rx_ch_cnt);
310 	DBGPR("  PPS outputs		   : %u\n",
311 	    hw_feat->pps_out_num);
312 	DBGPR("  Auxiliary snapshot inputs : %u\n",
313 	    hw_feat->aux_snap_num);
314 
315 	DBGPR("<--xgbe_get_all_hw_features\n");
316 }
317 
318 void
319 xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
320 {
321 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
322 
323 	DBGPR("-->xgbe_init_tx_coalesce\n");
324 
325 	pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
326 	pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
327 
328 	hw_if->config_tx_coalesce(pdata);
329 
330 	DBGPR("<--xgbe_init_tx_coalesce\n");
331 }
332 
333 void
334 xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
335 {
336 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
337 
338 	DBGPR("-->xgbe_init_rx_coalesce\n");
339 
340 	pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
341 	pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
342 	pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
343 
344 	hw_if->config_rx_coalesce(pdata);
345 
346 	DBGPR("<--xgbe_init_rx_coalesce\n");
347 }
348