1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc. 5 * 6 * This file is available to you under your choice of the following two 7 * licenses: 8 * 9 * License 1: GPLv2 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Redistribution and use in source and binary forms, with or without 60 * modification, are permitted provided that the following conditions are met: 61 * * Redistributions of source code must retain the above copyright 62 * notice, this list of conditions and the following disclaimer. 63 * * Redistributions in binary form must reproduce the above copyright 64 * notice, this list of conditions and the following disclaimer in the 65 * documentation and/or other materials provided with the distribution. 66 * * Neither the name of Advanced Micro Devices, Inc. nor the 67 * names of its contributors may be used to endorse or promote products 68 * derived from this software without specific prior written permission. 69 * 70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 80 * 81 * This file incorporates work covered by the following copyright and 82 * permission notice: 83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 85 * Inc. unless otherwise expressly agreed to in writing between Synopsys 86 * and you. 87 * 88 * The Software IS NOT an item of Licensed Software or Licensed Product 89 * under any End User Software License Agreement or Agreement for Licensed 90 * Product with Synopsys or any supplement thereto. Permission is hereby 91 * granted, free of charge, to any person obtaining a copy of this software 92 * annotated with this license and the Software, to deal in the Software 93 * without restriction, including without limitation the rights to use, 94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 95 * of the Software, and to permit persons to whom the Software is furnished 96 * to do so, subject to the following conditions: 97 * 98 * The above copyright notice and this permission notice shall be included 99 * in all copies or substantial portions of the Software. 100 * 101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 111 * THE POSSIBILITY OF SUCH DAMAGE. 112 */ 113 114 #include <sys/cdefs.h> 115 #include "xgbe.h" 116 #include "xgbe-common.h" 117 118 #include <net/if_dl.h> 119 120 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata) 121 { 122 return (if_getmtu(pdata->netdev) + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); 123 } 124 125 static unsigned int 126 xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, unsigned int usec) 127 { 128 unsigned long rate; 129 unsigned int ret; 130 131 rate = pdata->sysclk_rate; 132 133 /* 134 * Convert the input usec value to the watchdog timer value. Each 135 * watchdog timer value is equivalent to 256 clock cycles. 136 * Calculate the required value as: 137 * ( usec * ( system_clock_mhz / 10^6 ) / 256 138 */ 139 ret = (usec * (rate / 1000000)) / 256; 140 141 return (ret); 142 } 143 144 static unsigned int 145 xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, unsigned int riwt) 146 { 147 unsigned long rate; 148 unsigned int ret; 149 150 rate = pdata->sysclk_rate; 151 152 /* 153 * Convert the input watchdog timer value to the usec value. Each 154 * watchdog timer value is equivalent to 256 clock cycles. 155 * Calculate the required value as: 156 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) 157 */ 158 ret = (riwt * 256) / (rate / 1000000); 159 160 return (ret); 161 } 162 163 static int 164 xgbe_config_pbl_val(struct xgbe_prv_data *pdata) 165 { 166 unsigned int pblx8, pbl; 167 unsigned int i; 168 169 pblx8 = DMA_PBL_X8_DISABLE; 170 pbl = pdata->pbl; 171 172 if (pdata->pbl > 32) { 173 pblx8 = DMA_PBL_X8_ENABLE; 174 pbl >>= 3; 175 } 176 177 for (i = 0; i < pdata->channel_count; i++) { 178 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, 179 pblx8); 180 181 if (pdata->channel[i]->tx_ring) 182 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, 183 PBL, pbl); 184 185 if (pdata->channel[i]->rx_ring) 186 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, 187 PBL, pbl); 188 } 189 190 return (0); 191 } 192 193 static int 194 xgbe_config_osp_mode(struct xgbe_prv_data *pdata) 195 { 196 unsigned int i; 197 198 for (i = 0; i < pdata->channel_count; i++) { 199 if (!pdata->channel[i]->tx_ring) 200 break; 201 202 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, 203 pdata->tx_osp_mode); 204 } 205 206 return (0); 207 } 208 209 static int 210 xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 211 { 212 unsigned int i; 213 214 for (i = 0; i < pdata->rx_q_count; i++) 215 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); 216 217 return (0); 218 } 219 220 static int 221 xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 222 { 223 unsigned int i; 224 225 for (i = 0; i < pdata->tx_q_count; i++) 226 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); 227 228 return (0); 229 } 230 231 static int 232 xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, unsigned int val) 233 { 234 unsigned int i; 235 236 for (i = 0; i < pdata->rx_q_count; i++) 237 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); 238 239 return (0); 240 } 241 242 static int 243 xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, unsigned int val) 244 { 245 unsigned int i; 246 247 for (i = 0; i < pdata->tx_q_count; i++) 248 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); 249 250 return (0); 251 } 252 253 static int 254 xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) 255 { 256 unsigned int i; 257 258 for (i = 0; i < pdata->channel_count; i++) { 259 if (!pdata->channel[i]->rx_ring) 260 break; 261 262 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, 263 pdata->rx_riwt); 264 } 265 266 return (0); 267 } 268 269 static int 270 xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) 271 { 272 return (0); 273 } 274 275 static void 276 xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) 277 { 278 unsigned int i; 279 280 for (i = 0; i < pdata->channel_count; i++) { 281 if (!pdata->channel[i]->rx_ring) 282 break; 283 284 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, 285 pdata->rx_buf_size); 286 } 287 } 288 289 static void 290 xgbe_config_tso_mode(struct xgbe_prv_data *pdata) 291 { 292 unsigned int i; 293 294 int tso_enabled = (if_getcapenable(pdata->netdev) & IFCAP_TSO); 295 296 for (i = 0; i < pdata->channel_count; i++) { 297 if (!pdata->channel[i]->tx_ring) 298 break; 299 300 axgbe_printf(1, "TSO in channel %d %s\n", i, tso_enabled ? "enabled" : "disabled"); 301 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, tso_enabled ? 1 : 0); 302 } 303 } 304 305 static void 306 xgbe_config_sph_mode(struct xgbe_prv_data *pdata) 307 { 308 unsigned int i; 309 int sph_enable_flag = XGMAC_IOREAD_BITS(pdata, MAC_HWF1R, SPHEN); 310 311 axgbe_printf(1, "sph_enable %d sph feature enabled?: %d\n", 312 pdata->sph_enable, sph_enable_flag); 313 314 if (pdata->sph_enable && sph_enable_flag) 315 axgbe_printf(0, "SPH Enabled\n"); 316 317 for (i = 0; i < pdata->channel_count; i++) { 318 if (!pdata->channel[i]->rx_ring) 319 break; 320 if (pdata->sph_enable && sph_enable_flag) { 321 /* Enable split header feature */ 322 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); 323 } else { 324 /* Disable split header feature */ 325 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 0); 326 } 327 328 /* per-channel confirmation of SPH being disabled/enabled */ 329 int val = XGMAC_DMA_IOREAD_BITS(pdata->channel[i], DMA_CH_CR, SPH); 330 axgbe_printf(0, "%s: SPH %s in channel %d\n", __func__, 331 (val ? "enabled" : "disabled"), i); 332 } 333 334 if (pdata->sph_enable && sph_enable_flag) 335 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); 336 } 337 338 static int 339 xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, 340 unsigned int index, unsigned int val) 341 { 342 unsigned int wait; 343 int ret = 0; 344 345 mtx_lock(&pdata->rss_mutex); 346 347 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { 348 ret = -EBUSY; 349 goto unlock; 350 } 351 352 XGMAC_IOWRITE(pdata, MAC_RSSDR, val); 353 354 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); 355 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); 356 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); 357 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); 358 359 wait = 1000; 360 while (wait--) { 361 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) 362 goto unlock; 363 364 DELAY(1000); 365 } 366 367 ret = -EBUSY; 368 369 unlock: 370 mtx_unlock(&pdata->rss_mutex); 371 372 return (ret); 373 } 374 375 static int 376 xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) 377 { 378 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(uint32_t); 379 unsigned int *key = (unsigned int *)&pdata->rss_key; 380 int ret; 381 382 while (key_regs--) { 383 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, 384 key_regs, *key++); 385 if (ret) 386 return (ret); 387 } 388 389 return (0); 390 } 391 392 static int 393 xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) 394 { 395 unsigned int i; 396 int ret; 397 398 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { 399 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_LOOKUP_TABLE_TYPE, i, 400 pdata->rss_table[i]); 401 if (ret) 402 return (ret); 403 } 404 405 return (0); 406 } 407 408 static int 409 xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const uint8_t *key) 410 { 411 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); 412 413 return (xgbe_write_rss_hash_key(pdata)); 414 } 415 416 static int 417 xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, const uint32_t *table) 418 { 419 unsigned int i; 420 421 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) 422 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); 423 424 return (xgbe_write_rss_lookup_table(pdata)); 425 } 426 427 static int 428 xgbe_enable_rss(struct xgbe_prv_data *pdata) 429 { 430 int ret; 431 432 if (!pdata->hw_feat.rss) 433 return (-EOPNOTSUPP); 434 435 /* Program the hash key */ 436 ret = xgbe_write_rss_hash_key(pdata); 437 if (ret) 438 return (ret); 439 440 /* Program the lookup table */ 441 ret = xgbe_write_rss_lookup_table(pdata); 442 if (ret) 443 return (ret); 444 445 /* Set the RSS options */ 446 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 447 448 /* Enable RSS */ 449 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); 450 451 axgbe_printf(0, "RSS Enabled\n"); 452 453 return (0); 454 } 455 456 static int 457 xgbe_disable_rss(struct xgbe_prv_data *pdata) 458 { 459 if (!pdata->hw_feat.rss) 460 return (-EOPNOTSUPP); 461 462 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); 463 464 axgbe_printf(0, "RSS Disabled\n"); 465 466 return (0); 467 } 468 469 static void 470 xgbe_config_rss(struct xgbe_prv_data *pdata) 471 { 472 int ret; 473 474 if (!pdata->hw_feat.rss) 475 return; 476 477 /* Check if the interface has RSS capability */ 478 if (pdata->enable_rss) 479 ret = xgbe_enable_rss(pdata); 480 else 481 ret = xgbe_disable_rss(pdata); 482 483 if (ret) 484 axgbe_error("error configuring RSS, RSS disabled\n"); 485 } 486 487 static int 488 xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) 489 { 490 unsigned int max_q_count, q_count; 491 unsigned int reg, reg_val; 492 unsigned int i; 493 494 /* Clear MTL flow control */ 495 for (i = 0; i < pdata->rx_q_count; i++) 496 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); 497 498 /* Clear MAC flow control */ 499 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 500 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 501 reg = MAC_Q0TFCR; 502 for (i = 0; i < q_count; i++) { 503 reg_val = XGMAC_IOREAD(pdata, reg); 504 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); 505 XGMAC_IOWRITE(pdata, reg, reg_val); 506 507 reg += MAC_QTFCR_INC; 508 } 509 510 return (0); 511 } 512 513 static int 514 xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) 515 { 516 unsigned int max_q_count, q_count; 517 unsigned int reg, reg_val; 518 unsigned int i; 519 520 /* Set MTL flow control */ 521 for (i = 0; i < pdata->rx_q_count; i++) { 522 unsigned int ehfc = 0; 523 524 if (pdata->rx_rfd[i]) { 525 /* Flow control thresholds are established */ 526 /* TODO - enable pfc/ets support */ 527 ehfc = 1; 528 } 529 530 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); 531 532 axgbe_printf(1, "flow control %s for RXq%u\n", 533 ehfc ? "enabled" : "disabled", i); 534 } 535 536 /* Set MAC flow control */ 537 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 538 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 539 reg = MAC_Q0TFCR; 540 for (i = 0; i < q_count; i++) { 541 reg_val = XGMAC_IOREAD(pdata, reg); 542 543 /* Enable transmit flow control */ 544 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); 545 546 /* Set pause time */ 547 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); 548 549 XGMAC_IOWRITE(pdata, reg, reg_val); 550 551 reg += MAC_QTFCR_INC; 552 } 553 554 return (0); 555 } 556 557 static int 558 xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) 559 { 560 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); 561 562 return (0); 563 } 564 565 static int 566 xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) 567 { 568 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); 569 570 return (0); 571 } 572 573 static int 574 xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) 575 { 576 if (pdata->tx_pause) 577 xgbe_enable_tx_flow_control(pdata); 578 else 579 xgbe_disable_tx_flow_control(pdata); 580 581 return (0); 582 } 583 584 static int 585 xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) 586 { 587 if (pdata->rx_pause) 588 xgbe_enable_rx_flow_control(pdata); 589 else 590 xgbe_disable_rx_flow_control(pdata); 591 592 return (0); 593 } 594 595 static void 596 xgbe_config_flow_control(struct xgbe_prv_data *pdata) 597 { 598 xgbe_config_tx_flow_control(pdata); 599 xgbe_config_rx_flow_control(pdata); 600 601 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 602 } 603 604 static void 605 xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) 606 { 607 struct xgbe_channel *channel; 608 unsigned int i, ver; 609 610 /* Set the interrupt mode if supported */ 611 if (pdata->channel_irq_mode) 612 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM, 613 pdata->channel_irq_mode); 614 615 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 616 617 for (i = 0; i < pdata->channel_count; i++) { 618 channel = pdata->channel[i]; 619 620 /* Clear all the interrupts which are set */ 621 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, 622 XGMAC_DMA_IOREAD(channel, DMA_CH_SR)); 623 624 /* Clear all interrupt enable bits */ 625 channel->curr_ier = 0; 626 627 /* Enable following interrupts 628 * NIE - Normal Interrupt Summary Enable 629 * AIE - Abnormal Interrupt Summary Enable 630 * FBEE - Fatal Bus Error Enable 631 */ 632 if (ver < 0x21) { 633 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1); 634 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1); 635 } else { 636 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1); 637 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1); 638 } 639 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); 640 641 if (channel->tx_ring) { 642 /* Enable the following Tx interrupts 643 * TIE - Transmit Interrupt Enable (unless using 644 * per channel interrupts in edge triggered 645 * mode) 646 */ 647 if (!pdata->per_channel_irq || pdata->channel_irq_mode) 648 XGMAC_SET_BITS(channel->curr_ier, 649 DMA_CH_IER, TIE, 1); 650 } 651 if (channel->rx_ring) { 652 /* Enable following Rx interrupts 653 * RBUE - Receive Buffer Unavailable Enable 654 * RIE - Receive Interrupt Enable (unless using 655 * per channel interrupts in edge triggered 656 * mode) 657 */ 658 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); 659 if (!pdata->per_channel_irq || pdata->channel_irq_mode) 660 XGMAC_SET_BITS(channel->curr_ier, 661 DMA_CH_IER, RIE, 1); 662 } 663 664 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 665 } 666 } 667 668 static void 669 xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) 670 { 671 unsigned int mtl_q_isr; 672 unsigned int q_count, i; 673 674 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); 675 for (i = 0; i < q_count; i++) { 676 /* Clear all the interrupts which are set */ 677 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); 678 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); 679 680 /* No MTL interrupts to be enabled */ 681 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); 682 } 683 } 684 685 static void 686 xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) 687 { 688 unsigned int mac_ier = 0; 689 690 /* Enable Timestamp interrupt */ 691 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); 692 693 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); 694 695 /* Enable all counter interrupts */ 696 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); 697 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); 698 699 /* Enable MDIO single command completion interrupt */ 700 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1); 701 } 702 703 static int 704 xgbe_set_speed(struct xgbe_prv_data *pdata, int speed) 705 { 706 unsigned int ss; 707 708 switch (speed) { 709 case SPEED_1000: 710 ss = 0x03; 711 break; 712 case SPEED_2500: 713 ss = 0x02; 714 break; 715 case SPEED_10000: 716 ss = 0x00; 717 break; 718 default: 719 return (-EINVAL); 720 } 721 722 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) 723 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); 724 725 return (0); 726 } 727 728 static int 729 xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 730 { 731 /* Put the VLAN tag in the Rx descriptor */ 732 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); 733 734 /* Don't check the VLAN type */ 735 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); 736 737 /* Check only C-TAG (0x8100) packets */ 738 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); 739 740 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ 741 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); 742 743 /* Enable VLAN tag stripping */ 744 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); 745 746 axgbe_printf(0, "VLAN Stripping Enabled\n"); 747 748 return (0); 749 } 750 751 static int 752 xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 753 { 754 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); 755 756 axgbe_printf(0, "VLAN Stripping Disabled\n"); 757 758 return (0); 759 } 760 761 static int 762 xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 763 { 764 /* Enable VLAN filtering */ 765 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); 766 767 /* Enable VLAN Hash Table filtering */ 768 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); 769 770 /* Disable VLAN tag inverse matching */ 771 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); 772 773 /* Only filter on the lower 12-bits of the VLAN tag */ 774 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); 775 776 /* In order for the VLAN Hash Table filtering to be effective, 777 * the VLAN tag identifier in the VLAN Tag Register must not 778 * be zero. Set the VLAN tag identifier to "1" to enable the 779 * VLAN Hash Table filtering. This implies that a VLAN tag of 780 * 1 will always pass filtering. 781 */ 782 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); 783 784 axgbe_printf(0, "VLAN filtering Enabled\n"); 785 786 return (0); 787 } 788 789 static int 790 xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 791 { 792 /* Disable VLAN filtering */ 793 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); 794 795 axgbe_printf(0, "VLAN filtering Disabled\n"); 796 797 return (0); 798 } 799 800 static uint32_t 801 xgbe_vid_crc32_le(__le16 vid_le) 802 { 803 uint32_t crc = ~0; 804 uint32_t temp = 0; 805 unsigned char *data = (unsigned char *)&vid_le; 806 unsigned char data_byte = 0; 807 int i, bits; 808 809 bits = get_bitmask_order(VLAN_VID_MASK); 810 for (i = 0; i < bits; i++) { 811 if ((i % 8) == 0) 812 data_byte = data[i / 8]; 813 814 temp = ((crc & 1) ^ data_byte) & 1; 815 crc >>= 1; 816 data_byte >>= 1; 817 818 if (temp) 819 crc ^= CRC32_POLY_LE; 820 } 821 822 return (crc); 823 } 824 825 static int 826 xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) 827 { 828 uint32_t crc; 829 uint16_t vid; 830 uint16_t vlan_hash_table = 0; 831 __le16 vid_le = 0; 832 833 axgbe_printf(1, "%s: Before updating VLANHTR 0x%x\n", __func__, 834 XGMAC_IOREAD(pdata, MAC_VLANHTR)); 835 836 /* Generate the VLAN Hash Table value */ 837 for_each_set_bit(vid, pdata->active_vlans, VLAN_NVID) { 838 839 /* Get the CRC32 value of the VLAN ID */ 840 vid_le = cpu_to_le16(vid); 841 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28; 842 843 vlan_hash_table |= (1 << crc); 844 axgbe_printf(1, "%s: vid 0x%x vid_le 0x%x crc 0x%x " 845 "vlan_hash_table 0x%x\n", __func__, vid, vid_le, crc, 846 vlan_hash_table); 847 } 848 849 /* Set the VLAN Hash Table filtering register */ 850 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); 851 852 axgbe_printf(1, "%s: After updating VLANHTR 0x%x\n", __func__, 853 XGMAC_IOREAD(pdata, MAC_VLANHTR)); 854 855 return (0); 856 } 857 858 static int 859 xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, unsigned int enable) 860 { 861 unsigned int val = enable ? 1 : 0; 862 863 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) 864 return (0); 865 866 axgbe_printf(1, "%s promiscous mode\n", enable? "entering" : "leaving"); 867 868 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); 869 870 /* Hardware will still perform VLAN filtering in promiscuous mode */ 871 if (enable) { 872 axgbe_printf(1, "Disabling rx vlan filtering\n"); 873 xgbe_disable_rx_vlan_filtering(pdata); 874 } else { 875 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) { 876 axgbe_printf(1, "Enabling rx vlan filtering\n"); 877 xgbe_enable_rx_vlan_filtering(pdata); 878 } 879 } 880 881 return (0); 882 } 883 884 static int 885 xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, unsigned int enable) 886 { 887 unsigned int val = enable ? 1 : 0; 888 889 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) 890 return (0); 891 892 axgbe_printf(1,"%s allmulti mode\n", enable ? "entering" : "leaving"); 893 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); 894 895 return (0); 896 } 897 898 static void 899 xgbe_set_mac_reg(struct xgbe_prv_data *pdata, char *addr, unsigned int *mac_reg) 900 { 901 unsigned int mac_addr_hi, mac_addr_lo; 902 uint8_t *mac_addr; 903 904 mac_addr_lo = 0; 905 mac_addr_hi = 0; 906 907 if (addr) { 908 mac_addr = (uint8_t *)&mac_addr_lo; 909 mac_addr[0] = addr[0]; 910 mac_addr[1] = addr[1]; 911 mac_addr[2] = addr[2]; 912 mac_addr[3] = addr[3]; 913 mac_addr = (uint8_t *)&mac_addr_hi; 914 mac_addr[0] = addr[4]; 915 mac_addr[1] = addr[5]; 916 917 axgbe_printf(1, "adding mac address %pM at %#x\n", addr, *mac_reg); 918 919 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); 920 } 921 922 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); 923 *mac_reg += MAC_MACA_INC; 924 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); 925 *mac_reg += MAC_MACA_INC; 926 } 927 928 static void 929 xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) 930 { 931 unsigned int mac_reg; 932 unsigned int addn_macs; 933 934 mac_reg = MAC_MACA1HR; 935 addn_macs = pdata->hw_feat.addn_mac; 936 937 xgbe_set_mac_reg(pdata, pdata->mac_addr, &mac_reg); 938 addn_macs--; 939 940 /* Clear remaining additional MAC address entries */ 941 while (addn_macs--) 942 xgbe_set_mac_reg(pdata, NULL, &mac_reg); 943 } 944 945 static int 946 xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) 947 { 948 /* TODO - add support to set mac hash table */ 949 xgbe_set_mac_addn_addrs(pdata); 950 951 return (0); 952 } 953 954 static int 955 xgbe_set_mac_address(struct xgbe_prv_data *pdata, uint8_t *addr) 956 { 957 unsigned int mac_addr_hi, mac_addr_lo; 958 959 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); 960 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | 961 (addr[1] << 8) | (addr[0] << 0); 962 963 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); 964 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); 965 966 return (0); 967 } 968 969 static int 970 xgbe_config_rx_mode(struct xgbe_prv_data *pdata) 971 { 972 unsigned int pr_mode, am_mode; 973 974 pr_mode = ((if_getflags(pdata->netdev) & IFF_PPROMISC) != 0); 975 am_mode = ((if_getflags(pdata->netdev) & IFF_ALLMULTI) != 0); 976 977 xgbe_set_promiscuous_mode(pdata, pr_mode); 978 xgbe_set_all_multicast_mode(pdata, am_mode); 979 980 xgbe_add_mac_addresses(pdata); 981 982 return (0); 983 } 984 985 static int 986 xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 987 { 988 unsigned int reg; 989 990 if (gpio > 15) 991 return (-EINVAL); 992 993 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 994 995 reg &= ~(1 << (gpio + 16)); 996 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 997 998 return (0); 999 } 1000 1001 static int 1002 xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 1003 { 1004 unsigned int reg; 1005 1006 if (gpio > 15) 1007 return (-EINVAL); 1008 1009 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 1010 1011 reg |= (1 << (gpio + 16)); 1012 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 1013 1014 return (0); 1015 } 1016 1017 static int 1018 xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) 1019 { 1020 unsigned long flags; 1021 unsigned int mmd_address, index, offset; 1022 int mmd_data; 1023 1024 if (mmd_reg & MII_ADDR_C45) 1025 mmd_address = mmd_reg & ~MII_ADDR_C45; 1026 else 1027 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1028 1029 /* The PCS registers are accessed using mmio. The underlying 1030 * management interface uses indirect addressing to access the MMD 1031 * register sets. This requires accessing of the PCS register in two 1032 * phases, an address phase and a data phase. 1033 * 1034 * The mmio interface is based on 16-bit offsets and values. All 1035 * register offsets must therefore be adjusted by left shifting the 1036 * offset 1 bit and reading 16 bits of data. 1037 */ 1038 mmd_address <<= 1; 1039 index = mmd_address & ~pdata->xpcs_window_mask; 1040 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 1041 1042 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1043 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); 1044 mmd_data = XPCS16_IOREAD(pdata, offset); 1045 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1046 1047 return (mmd_data); 1048 } 1049 1050 static void 1051 xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, 1052 int mmd_data) 1053 { 1054 unsigned long flags; 1055 unsigned int mmd_address, index, offset; 1056 1057 if (mmd_reg & MII_ADDR_C45) 1058 mmd_address = mmd_reg & ~MII_ADDR_C45; 1059 else 1060 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1061 1062 /* The PCS registers are accessed using mmio. The underlying 1063 * management interface uses indirect addressing to access the MMD 1064 * register sets. This requires accessing of the PCS register in two 1065 * phases, an address phase and a data phase. 1066 * 1067 * The mmio interface is based on 16-bit offsets and values. All 1068 * register offsets must therefore be adjusted by left shifting the 1069 * offset 1 bit and writing 16 bits of data. 1070 */ 1071 mmd_address <<= 1; 1072 index = mmd_address & ~pdata->xpcs_window_mask; 1073 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 1074 1075 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1076 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); 1077 XPCS16_IOWRITE(pdata, offset, mmd_data); 1078 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1079 } 1080 1081 static int 1082 xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) 1083 { 1084 unsigned long flags; 1085 unsigned int mmd_address; 1086 int mmd_data; 1087 1088 if (mmd_reg & MII_ADDR_C45) 1089 mmd_address = mmd_reg & ~MII_ADDR_C45; 1090 else 1091 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1092 1093 /* The PCS registers are accessed using mmio. The underlying APB3 1094 * management interface uses indirect addressing to access the MMD 1095 * register sets. This requires accessing of the PCS register in two 1096 * phases, an address phase and a data phase. 1097 * 1098 * The mmio interface is based on 32-bit offsets and values. All 1099 * register offsets must therefore be adjusted by left shifting the 1100 * offset 2 bits and reading 32 bits of data. 1101 */ 1102 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1103 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 1104 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2); 1105 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1106 1107 return (mmd_data); 1108 } 1109 1110 static void 1111 xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, 1112 int mmd_data) 1113 { 1114 unsigned int mmd_address; 1115 unsigned long flags; 1116 1117 if (mmd_reg & MII_ADDR_C45) 1118 mmd_address = mmd_reg & ~MII_ADDR_C45; 1119 else 1120 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1121 1122 /* The PCS registers are accessed using mmio. The underlying APB3 1123 * management interface uses indirect addressing to access the MMD 1124 * register sets. This requires accessing of the PCS register in two 1125 * phases, an address phase and a data phase. 1126 * 1127 * The mmio interface is based on 32-bit offsets and values. All 1128 * register offsets must therefore be adjusted by left shifting the 1129 * offset 2 bits and writing 32 bits of data. 1130 */ 1131 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1132 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 1133 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); 1134 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1135 } 1136 1137 static int 1138 xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) 1139 { 1140 switch (pdata->vdata->xpcs_access) { 1141 case XGBE_XPCS_ACCESS_V1: 1142 return (xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg)); 1143 1144 case XGBE_XPCS_ACCESS_V2: 1145 default: 1146 return (xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg)); 1147 } 1148 } 1149 1150 static void 1151 xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, 1152 int mmd_data) 1153 { 1154 switch (pdata->vdata->xpcs_access) { 1155 case XGBE_XPCS_ACCESS_V1: 1156 return (xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data)); 1157 1158 case XGBE_XPCS_ACCESS_V2: 1159 default: 1160 return (xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data)); 1161 } 1162 } 1163 1164 static unsigned int 1165 xgbe_create_mdio_sca(int port, int reg) 1166 { 1167 unsigned int mdio_sca, da; 1168 1169 da = (reg & MII_ADDR_C45) ? reg >> 16 : 0; 1170 1171 mdio_sca = 0; 1172 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg); 1173 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port); 1174 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, da); 1175 1176 return (mdio_sca); 1177 } 1178 1179 static int 1180 xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg, 1181 uint16_t val) 1182 { 1183 unsigned int mdio_sca, mdio_sccd; 1184 1185 mtx_lock_spin(&pdata->mdio_mutex); 1186 1187 mdio_sca = xgbe_create_mdio_sca(addr, reg); 1188 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 1189 1190 mdio_sccd = 0; 1191 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val); 1192 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1); 1193 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 1194 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 1195 1196 if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) == 1197 EWOULDBLOCK) { 1198 axgbe_error("%s: MDIO write error\n", __func__); 1199 mtx_unlock_spin(&pdata->mdio_mutex); 1200 return (-ETIMEDOUT); 1201 } 1202 1203 mtx_unlock_spin(&pdata->mdio_mutex); 1204 return (0); 1205 } 1206 1207 static int 1208 xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg) 1209 { 1210 unsigned int mdio_sca, mdio_sccd; 1211 1212 mtx_lock_spin(&pdata->mdio_mutex); 1213 1214 mdio_sca = xgbe_create_mdio_sca(addr, reg); 1215 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 1216 1217 mdio_sccd = 0; 1218 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3); 1219 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 1220 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 1221 1222 if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) == 1223 EWOULDBLOCK) { 1224 axgbe_error("%s: MDIO read error\n", __func__); 1225 mtx_unlock_spin(&pdata->mdio_mutex); 1226 return (-ETIMEDOUT); 1227 } 1228 1229 mtx_unlock_spin(&pdata->mdio_mutex); 1230 1231 return (XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA)); 1232 } 1233 1234 static int 1235 xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port, 1236 enum xgbe_mdio_mode mode) 1237 { 1238 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); 1239 1240 switch (mode) { 1241 case XGBE_MDIO_MODE_CL22: 1242 if (port > XGMAC_MAX_C22_PORT) 1243 return (-EINVAL); 1244 reg_val |= (1 << port); 1245 break; 1246 case XGBE_MDIO_MODE_CL45: 1247 break; 1248 default: 1249 return (-EINVAL); 1250 } 1251 1252 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); 1253 1254 return (0); 1255 } 1256 1257 static int 1258 xgbe_tx_complete(struct xgbe_ring_desc *rdesc) 1259 { 1260 return (!XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN)); 1261 } 1262 1263 static int 1264 xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) 1265 { 1266 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); 1267 1268 axgbe_printf(0, "Receive checksum offload Disabled\n"); 1269 return (0); 1270 } 1271 1272 static int 1273 xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) 1274 { 1275 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); 1276 1277 axgbe_printf(0, "Receive checksum offload Enabled\n"); 1278 return (0); 1279 } 1280 1281 static void 1282 xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) 1283 { 1284 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1285 1286 /* Reset the Tx descriptor 1287 * Set buffer 1 (lo) address to zero 1288 * Set buffer 1 (hi) address to zero 1289 * Reset all other control bits (IC, TTSE, B2L & B1L) 1290 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) 1291 */ 1292 rdesc->desc0 = 0; 1293 rdesc->desc1 = 0; 1294 rdesc->desc2 = 0; 1295 rdesc->desc3 = 0; 1296 1297 wmb(); 1298 } 1299 1300 static void 1301 xgbe_tx_desc_init(struct xgbe_channel *channel) 1302 { 1303 struct xgbe_ring *ring = channel->tx_ring; 1304 struct xgbe_ring_data *rdata; 1305 int i; 1306 int start_index = ring->cur; 1307 1308 /* Initialze all descriptors */ 1309 for (i = 0; i < ring->rdesc_count; i++) { 1310 rdata = XGBE_GET_DESC_DATA(ring, i); 1311 1312 /* Initialize Tx descriptor */ 1313 xgbe_tx_desc_reset(rdata); 1314 } 1315 1316 /* Update the total number of Tx descriptors */ 1317 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); 1318 1319 /* Update the starting address of descriptor ring */ 1320 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1321 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, 1322 upper_32_bits(rdata->rdata_paddr)); 1323 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, 1324 lower_32_bits(rdata->rdata_paddr)); 1325 } 1326 1327 static void 1328 xgbe_rx_desc_init(struct xgbe_channel *channel) 1329 { 1330 struct xgbe_ring *ring = channel->rx_ring; 1331 struct xgbe_ring_data *rdata; 1332 unsigned int start_index = ring->cur; 1333 1334 /* 1335 * Just set desc_count and the starting address of the desc list 1336 * here. Rest will be done as part of the txrx path. 1337 */ 1338 1339 /* Update the total number of Rx descriptors */ 1340 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); 1341 1342 /* Update the starting address of descriptor ring */ 1343 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1344 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, 1345 upper_32_bits(rdata->rdata_paddr)); 1346 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, 1347 lower_32_bits(rdata->rdata_paddr)); 1348 } 1349 1350 static int 1351 xgbe_dev_read(struct xgbe_channel *channel) 1352 { 1353 struct xgbe_prv_data *pdata = channel->pdata; 1354 struct xgbe_ring *ring = channel->rx_ring; 1355 struct xgbe_ring_data *rdata; 1356 struct xgbe_ring_desc *rdesc; 1357 struct xgbe_packet_data *packet = &ring->packet_data; 1358 unsigned int err, etlt, l34t = 0; 1359 1360 axgbe_printf(1, "-->xgbe_dev_read: cur = %d\n", ring->cur); 1361 1362 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1363 rdesc = rdata->rdesc; 1364 1365 /* Check for data availability */ 1366 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) 1367 return (1); 1368 1369 rmb(); 1370 1371 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { 1372 /* TODO - Timestamp Context Descriptor */ 1373 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1374 CONTEXT, 1); 1375 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1376 CONTEXT_NEXT, 0); 1377 return (0); 1378 } 1379 1380 /* Normal Descriptor, be sure Context Descriptor bit is off */ 1381 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); 1382 1383 /* Indicate if a Context Descriptor is next */ 1384 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) 1385 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1386 CONTEXT_NEXT, 1); 1387 1388 /* Get the header length */ 1389 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { 1390 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1391 FIRST, 1); 1392 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, 1393 RX_NORMAL_DESC2, HL); 1394 if (rdata->rx.hdr_len) 1395 pdata->ext_stats.rx_split_header_packets++; 1396 } else 1397 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1398 FIRST, 0); 1399 1400 /* Get the RSS hash */ 1401 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { 1402 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1403 RSS_HASH, 1); 1404 1405 packet->rss_hash = le32_to_cpu(rdesc->desc1); 1406 1407 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); 1408 switch (l34t) { 1409 case RX_DESC3_L34T_IPV4_TCP: 1410 packet->rss_hash_type = M_HASHTYPE_RSS_TCP_IPV4; 1411 break; 1412 case RX_DESC3_L34T_IPV4_UDP: 1413 packet->rss_hash_type = M_HASHTYPE_RSS_UDP_IPV4; 1414 break; 1415 case RX_DESC3_L34T_IPV6_TCP: 1416 packet->rss_hash_type = M_HASHTYPE_RSS_TCP_IPV6; 1417 break; 1418 case RX_DESC3_L34T_IPV6_UDP: 1419 packet->rss_hash_type = M_HASHTYPE_RSS_UDP_IPV6; 1420 break; 1421 default: 1422 packet->rss_hash_type = M_HASHTYPE_OPAQUE; 1423 break; 1424 } 1425 } 1426 1427 /* Not all the data has been transferred for this packet */ 1428 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) { 1429 /* This is not the last of the data for this packet */ 1430 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1431 LAST, 0); 1432 return (0); 1433 } 1434 1435 /* This is the last of the data for this packet */ 1436 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1437 LAST, 1); 1438 1439 /* Get the packet length */ 1440 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); 1441 1442 /* Set checksum done indicator as appropriate */ 1443 /* TODO - add tunneling support */ 1444 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1445 CSUM_DONE, 1); 1446 1447 /* Check for errors (only valid in last descriptor) */ 1448 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); 1449 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); 1450 axgbe_printf(1, "%s: err=%u, etlt=%#x\n", __func__, err, etlt); 1451 1452 if (!err || !etlt) { 1453 /* No error if err is 0 or etlt is 0 */ 1454 if (etlt == 0x09 && 1455 (if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) { 1456 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1457 VLAN_CTAG, 1); 1458 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, 1459 RX_NORMAL_DESC0, OVT); 1460 axgbe_printf(1, "vlan-ctag=%#06x\n", packet->vlan_ctag); 1461 } 1462 } else { 1463 unsigned int tnp = XGMAC_GET_BITS(packet->attributes, 1464 RX_PACKET_ATTRIBUTES, TNP); 1465 1466 if ((etlt == 0x05) || (etlt == 0x06)) { 1467 axgbe_printf(1, "%s: err1 l34t %d err 0x%x etlt 0x%x\n", 1468 __func__, l34t, err, etlt); 1469 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1470 CSUM_DONE, 0); 1471 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1472 TNPCSUM_DONE, 0); 1473 pdata->ext_stats.rx_csum_errors++; 1474 } else if (tnp && ((etlt == 0x09) || (etlt == 0x0a))) { 1475 axgbe_printf(1, "%s: err2 l34t %d err 0x%x etlt 0x%x\n", 1476 __func__, l34t, err, etlt); 1477 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1478 CSUM_DONE, 0); 1479 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1480 TNPCSUM_DONE, 0); 1481 pdata->ext_stats.rx_vxlan_csum_errors++; 1482 } else { 1483 axgbe_printf(1, "%s: tnp %d l34t %d err 0x%x etlt 0x%x\n", 1484 __func__, tnp, l34t, err, etlt); 1485 axgbe_printf(1, "%s: Channel: %d SR 0x%x DSR 0x%x \n", 1486 __func__, channel->queue_index, 1487 XGMAC_DMA_IOREAD(channel, DMA_CH_SR), 1488 XGMAC_DMA_IOREAD(channel, DMA_CH_DSR)); 1489 axgbe_printf(1, "%s: ring cur %d dirty %d\n", 1490 __func__, ring->cur, ring->dirty); 1491 axgbe_printf(1, "%s: Desc 0x%08x-0x%08x-0x%08x-0x%08x\n", 1492 __func__, rdesc->desc0, rdesc->desc1, rdesc->desc2, 1493 rdesc->desc3); 1494 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, 1495 FRAME, 1); 1496 } 1497 } 1498 1499 axgbe_printf(1, "<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", 1500 channel->name, ring->cur & (ring->rdesc_count - 1), ring->cur); 1501 1502 return (0); 1503 } 1504 1505 static int 1506 xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) 1507 { 1508 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ 1509 return (XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT)); 1510 } 1511 1512 static int 1513 xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) 1514 { 1515 /* Rx and Tx share LD bit, so check TDES3.LD bit */ 1516 return (XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD)); 1517 } 1518 1519 static int 1520 xgbe_enable_int(struct xgbe_channel *channel, enum xgbe_int int_id) 1521 { 1522 struct xgbe_prv_data *pdata = channel->pdata; 1523 1524 axgbe_printf(1, "enable_int: DMA_CH_IER read - 0x%x\n", 1525 channel->curr_ier); 1526 1527 switch (int_id) { 1528 case XGMAC_INT_DMA_CH_SR_TI: 1529 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); 1530 break; 1531 case XGMAC_INT_DMA_CH_SR_TPS: 1532 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1); 1533 break; 1534 case XGMAC_INT_DMA_CH_SR_TBU: 1535 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1); 1536 break; 1537 case XGMAC_INT_DMA_CH_SR_RI: 1538 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); 1539 break; 1540 case XGMAC_INT_DMA_CH_SR_RBU: 1541 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); 1542 break; 1543 case XGMAC_INT_DMA_CH_SR_RPS: 1544 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1); 1545 break; 1546 case XGMAC_INT_DMA_CH_SR_TI_RI: 1547 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); 1548 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); 1549 break; 1550 case XGMAC_INT_DMA_CH_SR_FBE: 1551 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); 1552 break; 1553 case XGMAC_INT_DMA_ALL: 1554 channel->curr_ier |= channel->saved_ier; 1555 break; 1556 default: 1557 return (-1); 1558 } 1559 1560 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 1561 1562 axgbe_printf(1, "enable_int: DMA_CH_IER write - 0x%x\n", 1563 channel->curr_ier); 1564 1565 return (0); 1566 } 1567 1568 static int 1569 xgbe_disable_int(struct xgbe_channel *channel, enum xgbe_int int_id) 1570 { 1571 struct xgbe_prv_data *pdata = channel->pdata; 1572 1573 axgbe_printf(1, "disable_int: DMA_CH_IER read - 0x%x\n", 1574 channel->curr_ier); 1575 1576 switch (int_id) { 1577 case XGMAC_INT_DMA_CH_SR_TI: 1578 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); 1579 break; 1580 case XGMAC_INT_DMA_CH_SR_TPS: 1581 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0); 1582 break; 1583 case XGMAC_INT_DMA_CH_SR_TBU: 1584 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0); 1585 break; 1586 case XGMAC_INT_DMA_CH_SR_RI: 1587 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); 1588 break; 1589 case XGMAC_INT_DMA_CH_SR_RBU: 1590 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0); 1591 break; 1592 case XGMAC_INT_DMA_CH_SR_RPS: 1593 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0); 1594 break; 1595 case XGMAC_INT_DMA_CH_SR_TI_RI: 1596 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); 1597 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); 1598 break; 1599 case XGMAC_INT_DMA_CH_SR_FBE: 1600 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0); 1601 break; 1602 case XGMAC_INT_DMA_ALL: 1603 channel->saved_ier = channel->curr_ier; 1604 channel->curr_ier = 0; 1605 break; 1606 default: 1607 return (-1); 1608 } 1609 1610 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 1611 1612 axgbe_printf(1, "disable_int: DMA_CH_IER write - 0x%x\n", 1613 channel->curr_ier); 1614 1615 return (0); 1616 } 1617 1618 static int 1619 __xgbe_exit(struct xgbe_prv_data *pdata) 1620 { 1621 unsigned int count = 2000; 1622 1623 /* Issue a software reset */ 1624 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); 1625 DELAY(10); 1626 1627 /* Poll Until Poll Condition */ 1628 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) 1629 DELAY(500); 1630 1631 if (!count) 1632 return (-EBUSY); 1633 1634 return (0); 1635 } 1636 1637 static int 1638 xgbe_exit(struct xgbe_prv_data *pdata) 1639 { 1640 int ret; 1641 1642 /* To guard against possible incorrectly generated interrupts, 1643 * issue the software reset twice. 1644 */ 1645 ret = __xgbe_exit(pdata); 1646 if (ret) { 1647 axgbe_error("%s: exit error %d\n", __func__, ret); 1648 return (ret); 1649 } 1650 1651 return (__xgbe_exit(pdata)); 1652 } 1653 1654 static int 1655 xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) 1656 { 1657 unsigned int i, count; 1658 1659 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) 1660 return (0); 1661 1662 for (i = 0; i < pdata->tx_q_count; i++) 1663 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); 1664 1665 /* Poll Until Poll Condition */ 1666 for (i = 0; i < pdata->tx_q_count; i++) { 1667 count = 2000; 1668 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, 1669 MTL_Q_TQOMR, FTQ)) 1670 DELAY(500); 1671 1672 if (!count) 1673 return (-EBUSY); 1674 } 1675 1676 return (0); 1677 } 1678 1679 static void 1680 xgbe_config_dma_bus(struct xgbe_prv_data *pdata) 1681 { 1682 unsigned int sbmr; 1683 1684 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR); 1685 1686 /* Set enhanced addressing mode */ 1687 XGMAC_SET_BITS(sbmr, DMA_SBMR, EAME, 1); 1688 1689 /* Set the System Bus mode */ 1690 XGMAC_SET_BITS(sbmr, DMA_SBMR, UNDEF, 1); 1691 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); 1692 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); 1693 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); 1694 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); 1695 1696 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr); 1697 1698 /* Set descriptor fetching threshold */ 1699 if (pdata->vdata->tx_desc_prefetch) 1700 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS, 1701 pdata->vdata->tx_desc_prefetch); 1702 1703 if (pdata->vdata->rx_desc_prefetch) 1704 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS, 1705 pdata->vdata->rx_desc_prefetch); 1706 } 1707 1708 static void 1709 xgbe_config_dma_cache(struct xgbe_prv_data *pdata) 1710 { 1711 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); 1712 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); 1713 if (pdata->awarcr) 1714 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); 1715 } 1716 1717 static void 1718 xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) 1719 { 1720 unsigned int i; 1721 1722 /* Set Tx to weighted round robin scheduling algorithm */ 1723 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); 1724 1725 /* Set Tx traffic classes to use WRR algorithm with equal weights */ 1726 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 1727 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 1728 MTL_TSA_ETS); 1729 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); 1730 } 1731 1732 /* Set Rx to strict priority algorithm */ 1733 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); 1734 } 1735 1736 static void 1737 xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata, 1738 unsigned int queue, unsigned int q_fifo_size) 1739 { 1740 unsigned int frame_fifo_size; 1741 unsigned int rfa, rfd; 1742 1743 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata)); 1744 axgbe_printf(1, "%s: queue %d q_fifo_size %d frame_fifo_size 0x%x\n", 1745 __func__, queue, q_fifo_size, frame_fifo_size); 1746 1747 /* TODO - add pfc/ets related support */ 1748 1749 /* This path deals with just maximum frame sizes which are 1750 * limited to a jumbo frame of 9,000 (plus headers, etc.) 1751 * so we can never exceed the maximum allowable RFA/RFD 1752 * values. 1753 */ 1754 if (q_fifo_size <= 2048) { 1755 /* rx_rfd to zero to signal no flow control */ 1756 pdata->rx_rfa[queue] = 0; 1757 pdata->rx_rfd[queue] = 0; 1758 return; 1759 } 1760 1761 if (q_fifo_size <= 4096) { 1762 /* Between 2048 and 4096 */ 1763 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ 1764 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ 1765 return; 1766 } 1767 1768 if (q_fifo_size <= frame_fifo_size) { 1769 /* Between 4096 and max-frame */ 1770 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ 1771 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ 1772 return; 1773 } 1774 1775 if (q_fifo_size <= (frame_fifo_size * 3)) { 1776 /* Between max-frame and 3 max-frames, 1777 * trigger if we get just over a frame of data and 1778 * resume when we have just under half a frame left. 1779 */ 1780 rfa = q_fifo_size - frame_fifo_size; 1781 rfd = rfa + (frame_fifo_size / 2); 1782 } else { 1783 /* Above 3 max-frames - trigger when just over 1784 * 2 frames of space available 1785 */ 1786 rfa = frame_fifo_size * 2; 1787 rfa += XGMAC_FLOW_CONTROL_UNIT; 1788 rfd = rfa + frame_fifo_size; 1789 } 1790 1791 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); 1792 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); 1793 axgbe_printf(1, "%s: forced queue %d rfa 0x%x rfd 0x%x\n", __func__, 1794 queue, pdata->rx_rfa[queue], pdata->rx_rfd[queue]); 1795 } 1796 1797 static void 1798 xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata, 1799 unsigned int *fifo) 1800 { 1801 unsigned int q_fifo_size; 1802 unsigned int i; 1803 1804 for (i = 0; i < pdata->rx_q_count; i++) { 1805 q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT; 1806 1807 axgbe_printf(1, "%s: fifo[%d] - 0x%x q_fifo_size 0x%x\n", 1808 __func__, i, fifo[i], q_fifo_size); 1809 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); 1810 } 1811 } 1812 1813 static void 1814 xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) 1815 { 1816 unsigned int i; 1817 1818 for (i = 0; i < pdata->rx_q_count; i++) { 1819 axgbe_printf(1, "%s: queue %d rfa %d rfd %d\n", __func__, i, 1820 pdata->rx_rfa[i], pdata->rx_rfd[i]); 1821 1822 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 1823 pdata->rx_rfa[i]); 1824 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 1825 pdata->rx_rfd[i]); 1826 1827 axgbe_printf(1, "%s: MTL_Q_RQFCR 0x%x\n", __func__, 1828 XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR)); 1829 } 1830 } 1831 1832 static unsigned int 1833 xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata) 1834 { 1835 /* The configured value may not be the actual amount of fifo RAM */ 1836 return (min_t(unsigned int, pdata->tx_max_fifo_size, 1837 pdata->hw_feat.tx_fifo_size)); 1838 } 1839 1840 static unsigned int 1841 xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata) 1842 { 1843 /* The configured value may not be the actual amount of fifo RAM */ 1844 return (min_t(unsigned int, pdata->rx_max_fifo_size, 1845 pdata->hw_feat.rx_fifo_size)); 1846 } 1847 1848 static void 1849 xgbe_calculate_equal_fifo(unsigned int fifo_size, unsigned int queue_count, 1850 unsigned int *fifo) 1851 { 1852 unsigned int q_fifo_size; 1853 unsigned int p_fifo; 1854 unsigned int i; 1855 1856 q_fifo_size = fifo_size / queue_count; 1857 1858 /* Calculate the fifo setting by dividing the queue's fifo size 1859 * by the fifo allocation increment (with 0 representing the 1860 * base allocation increment so decrement the result by 1). 1861 */ 1862 p_fifo = q_fifo_size / XGMAC_FIFO_UNIT; 1863 if (p_fifo) 1864 p_fifo--; 1865 1866 /* Distribute the fifo equally amongst the queues */ 1867 for (i = 0; i < queue_count; i++) 1868 fifo[i] = p_fifo; 1869 } 1870 1871 static unsigned int 1872 xgbe_set_nonprio_fifos(unsigned int fifo_size, unsigned int queue_count, 1873 unsigned int *fifo) 1874 { 1875 unsigned int i; 1876 1877 MPASS(powerof2(XGMAC_FIFO_MIN_ALLOC)); 1878 1879 if (queue_count <= IEEE_8021QAZ_MAX_TCS) 1880 return (fifo_size); 1881 1882 /* Rx queues 9 and up are for specialized packets, 1883 * such as PTP or DCB control packets, etc. and 1884 * don't require a large fifo 1885 */ 1886 for (i = IEEE_8021QAZ_MAX_TCS; i < queue_count; i++) { 1887 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1; 1888 fifo_size -= XGMAC_FIFO_MIN_ALLOC; 1889 } 1890 1891 return (fifo_size); 1892 } 1893 1894 static void 1895 xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) 1896 { 1897 unsigned int fifo_size; 1898 unsigned int fifo[XGBE_MAX_QUEUES]; 1899 unsigned int i; 1900 1901 fifo_size = xgbe_get_tx_fifo_size(pdata); 1902 axgbe_printf(1, "%s: fifo_size 0x%x\n", __func__, fifo_size); 1903 1904 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); 1905 1906 for (i = 0; i < pdata->tx_q_count; i++) { 1907 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); 1908 axgbe_printf(1, "Tx q %d FIFO Size 0x%x\n", i, 1909 XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR)); 1910 } 1911 1912 axgbe_printf(1, "%d Tx hardware queues, %d byte fifo per queue\n", 1913 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 1914 } 1915 1916 static void 1917 xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) 1918 { 1919 unsigned int fifo_size; 1920 unsigned int fifo[XGBE_MAX_QUEUES]; 1921 unsigned int prio_queues; 1922 unsigned int i; 1923 1924 /* TODO - add pfc/ets related support */ 1925 1926 /* Clear any DCB related fifo/queue information */ 1927 fifo_size = xgbe_get_rx_fifo_size(pdata); 1928 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 1929 axgbe_printf(1, "%s: fifo_size 0x%x rx_q_cnt %d prio %d\n", __func__, 1930 fifo_size, pdata->rx_q_count, prio_queues); 1931 1932 /* Assign a minimum fifo to the non-VLAN priority queues */ 1933 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); 1934 1935 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo); 1936 1937 for (i = 0; i < pdata->rx_q_count; i++) { 1938 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); 1939 axgbe_printf(1, "Rx q %d FIFO Size 0x%x\n", i, 1940 XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR)); 1941 } 1942 1943 xgbe_calculate_flow_control_threshold(pdata, fifo); 1944 xgbe_config_flow_control_threshold(pdata); 1945 1946 axgbe_printf(1, "%u Rx hardware queues, %u byte fifo/queue\n", 1947 pdata->rx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 1948 } 1949 1950 static void 1951 xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) 1952 { 1953 unsigned int qptc, qptc_extra, queue; 1954 unsigned int prio_queues; 1955 unsigned int ppq, ppq_extra, prio; 1956 unsigned int mask; 1957 unsigned int i, j, reg, reg_val; 1958 1959 /* Map the MTL Tx Queues to Traffic Classes 1960 * Note: Tx Queues >= Traffic Classes 1961 */ 1962 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; 1963 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; 1964 1965 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { 1966 for (j = 0; j < qptc; j++) { 1967 axgbe_printf(1, "TXq%u mapped to TC%u\n", queue, i); 1968 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 1969 Q2TCMAP, i); 1970 pdata->q2tc_map[queue++] = i; 1971 } 1972 1973 if (i < qptc_extra) { 1974 axgbe_printf(1, "TXq%u mapped to TC%u\n", queue, i); 1975 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 1976 Q2TCMAP, i); 1977 pdata->q2tc_map[queue++] = i; 1978 } 1979 } 1980 1981 /* Map the 8 VLAN priority values to available MTL Rx queues */ 1982 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 1983 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; 1984 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; 1985 1986 reg = MAC_RQC2R; 1987 reg_val = 0; 1988 for (i = 0, prio = 0; i < prio_queues;) { 1989 mask = 0; 1990 for (j = 0; j < ppq; j++) { 1991 axgbe_printf(1, "PRIO%u mapped to RXq%u\n", prio, i); 1992 mask |= (1 << prio); 1993 pdata->prio2q_map[prio++] = i; 1994 } 1995 1996 if (i < ppq_extra) { 1997 axgbe_printf(1, "PRIO%u mapped to RXq%u\n", prio, i); 1998 mask |= (1 << prio); 1999 pdata->prio2q_map[prio++] = i; 2000 } 2001 2002 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); 2003 2004 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) 2005 continue; 2006 2007 XGMAC_IOWRITE(pdata, reg, reg_val); 2008 reg += MAC_RQC2_INC; 2009 reg_val = 0; 2010 } 2011 2012 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ 2013 reg = MTL_RQDCM0R; 2014 reg_val = 0; 2015 for (i = 0; i < pdata->rx_q_count;) { 2016 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); 2017 2018 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) 2019 continue; 2020 2021 XGMAC_IOWRITE(pdata, reg, reg_val); 2022 2023 reg += MTL_RQDCM_INC; 2024 reg_val = 0; 2025 } 2026 } 2027 2028 static void 2029 xgbe_config_mac_address(struct xgbe_prv_data *pdata) 2030 { 2031 xgbe_set_mac_address(pdata, if_getlladdr(pdata->netdev)); 2032 2033 /* 2034 * Promisc mode does not work as intended. Multicast traffic 2035 * is triggering the filter, so enable Receive All. 2036 */ 2037 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, RA, 1); 2038 2039 /* Filtering is done using perfect filtering and hash filtering */ 2040 if (pdata->hw_feat.hash_table_size) { 2041 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 2042 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 2043 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); 2044 } 2045 } 2046 2047 static void 2048 xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) 2049 { 2050 unsigned int val; 2051 2052 val = (if_getmtu(pdata->netdev) > XGMAC_STD_PACKET_MTU) ? 1 : 0; 2053 2054 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 2055 } 2056 2057 static void 2058 xgbe_config_mac_speed(struct xgbe_prv_data *pdata) 2059 { 2060 xgbe_set_speed(pdata, pdata->phy_speed); 2061 } 2062 2063 static void 2064 xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) 2065 { 2066 if ((if_getcapenable(pdata->netdev) & IFCAP_RXCSUM)) 2067 xgbe_enable_rx_csum(pdata); 2068 else 2069 xgbe_disable_rx_csum(pdata); 2070 } 2071 2072 static void 2073 xgbe_config_vlan_support(struct xgbe_prv_data *pdata) 2074 { 2075 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 2076 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 2077 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 2078 2079 /* Set the current VLAN Hash Table register value */ 2080 xgbe_update_vlan_hash_table(pdata); 2081 2082 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) { 2083 axgbe_printf(1, "Enabling rx vlan filtering\n"); 2084 xgbe_enable_rx_vlan_filtering(pdata); 2085 } else { 2086 axgbe_printf(1, "Disabling rx vlan filtering\n"); 2087 xgbe_disable_rx_vlan_filtering(pdata); 2088 } 2089 2090 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) { 2091 axgbe_printf(1, "Enabling rx vlan stripping\n"); 2092 xgbe_enable_rx_vlan_stripping(pdata); 2093 } else { 2094 axgbe_printf(1, "Disabling rx vlan stripping\n"); 2095 xgbe_disable_rx_vlan_stripping(pdata); 2096 } 2097 } 2098 2099 static uint64_t 2100 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) 2101 { 2102 bool read_hi; 2103 uint64_t val; 2104 2105 if (pdata->vdata->mmc_64bit) { 2106 switch (reg_lo) { 2107 /* These registers are always 32 bit */ 2108 case MMC_RXRUNTERROR: 2109 case MMC_RXJABBERERROR: 2110 case MMC_RXUNDERSIZE_G: 2111 case MMC_RXOVERSIZE_G: 2112 case MMC_RXWATCHDOGERROR: 2113 read_hi = false; 2114 break; 2115 2116 default: 2117 read_hi = true; 2118 } 2119 } else { 2120 switch (reg_lo) { 2121 /* These registers are always 64 bit */ 2122 case MMC_TXOCTETCOUNT_GB_LO: 2123 case MMC_TXOCTETCOUNT_G_LO: 2124 case MMC_RXOCTETCOUNT_GB_LO: 2125 case MMC_RXOCTETCOUNT_G_LO: 2126 read_hi = true; 2127 break; 2128 2129 default: 2130 read_hi = false; 2131 } 2132 } 2133 2134 val = XGMAC_IOREAD(pdata, reg_lo); 2135 2136 if (read_hi) 2137 val |= ((uint64_t)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); 2138 2139 return (val); 2140 } 2141 2142 static void 2143 xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) 2144 { 2145 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2146 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); 2147 2148 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) 2149 stats->txoctetcount_gb += 2150 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 2151 2152 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) 2153 stats->txframecount_gb += 2154 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 2155 2156 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) 2157 stats->txbroadcastframes_g += 2158 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 2159 2160 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) 2161 stats->txmulticastframes_g += 2162 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 2163 2164 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) 2165 stats->tx64octets_gb += 2166 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 2167 2168 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) 2169 stats->tx65to127octets_gb += 2170 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 2171 2172 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) 2173 stats->tx128to255octets_gb += 2174 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 2175 2176 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) 2177 stats->tx256to511octets_gb += 2178 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 2179 2180 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) 2181 stats->tx512to1023octets_gb += 2182 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 2183 2184 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) 2185 stats->tx1024tomaxoctets_gb += 2186 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 2187 2188 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) 2189 stats->txunicastframes_gb += 2190 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 2191 2192 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) 2193 stats->txmulticastframes_gb += 2194 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 2195 2196 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) 2197 stats->txbroadcastframes_g += 2198 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 2199 2200 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) 2201 stats->txunderflowerror += 2202 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 2203 2204 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) 2205 stats->txoctetcount_g += 2206 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 2207 2208 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) 2209 stats->txframecount_g += 2210 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 2211 2212 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) 2213 stats->txpauseframes += 2214 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 2215 2216 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) 2217 stats->txvlanframes_g += 2218 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 2219 } 2220 2221 static void 2222 xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) 2223 { 2224 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2225 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); 2226 2227 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) 2228 stats->rxframecount_gb += 2229 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 2230 2231 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) 2232 stats->rxoctetcount_gb += 2233 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 2234 2235 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) 2236 stats->rxoctetcount_g += 2237 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 2238 2239 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) 2240 stats->rxbroadcastframes_g += 2241 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 2242 2243 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) 2244 stats->rxmulticastframes_g += 2245 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 2246 2247 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) 2248 stats->rxcrcerror += 2249 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 2250 2251 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) 2252 stats->rxrunterror += 2253 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 2254 2255 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) 2256 stats->rxjabbererror += 2257 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 2258 2259 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) 2260 stats->rxundersize_g += 2261 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 2262 2263 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) 2264 stats->rxoversize_g += 2265 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 2266 2267 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) 2268 stats->rx64octets_gb += 2269 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 2270 2271 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) 2272 stats->rx65to127octets_gb += 2273 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 2274 2275 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) 2276 stats->rx128to255octets_gb += 2277 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 2278 2279 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) 2280 stats->rx256to511octets_gb += 2281 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 2282 2283 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) 2284 stats->rx512to1023octets_gb += 2285 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 2286 2287 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) 2288 stats->rx1024tomaxoctets_gb += 2289 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 2290 2291 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) 2292 stats->rxunicastframes_g += 2293 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 2294 2295 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) 2296 stats->rxlengtherror += 2297 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 2298 2299 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) 2300 stats->rxoutofrangetype += 2301 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 2302 2303 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) 2304 stats->rxpauseframes += 2305 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 2306 2307 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) 2308 stats->rxfifooverflow += 2309 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 2310 2311 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) 2312 stats->rxvlanframes_gb += 2313 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 2314 2315 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) 2316 stats->rxwatchdogerror += 2317 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 2318 } 2319 2320 static void 2321 xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) 2322 { 2323 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2324 2325 /* Freeze counters */ 2326 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 2327 2328 stats->txoctetcount_gb += 2329 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 2330 2331 stats->txframecount_gb += 2332 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 2333 2334 stats->txbroadcastframes_g += 2335 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 2336 2337 stats->txmulticastframes_g += 2338 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 2339 2340 stats->tx64octets_gb += 2341 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 2342 2343 stats->tx65to127octets_gb += 2344 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 2345 2346 stats->tx128to255octets_gb += 2347 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 2348 2349 stats->tx256to511octets_gb += 2350 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 2351 2352 stats->tx512to1023octets_gb += 2353 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 2354 2355 stats->tx1024tomaxoctets_gb += 2356 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 2357 2358 stats->txunicastframes_gb += 2359 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 2360 2361 stats->txmulticastframes_gb += 2362 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 2363 2364 stats->txbroadcastframes_gb += 2365 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 2366 2367 stats->txunderflowerror += 2368 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 2369 2370 stats->txoctetcount_g += 2371 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 2372 2373 stats->txframecount_g += 2374 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 2375 2376 stats->txpauseframes += 2377 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 2378 2379 stats->txvlanframes_g += 2380 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 2381 2382 stats->rxframecount_gb += 2383 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 2384 2385 stats->rxoctetcount_gb += 2386 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 2387 2388 stats->rxoctetcount_g += 2389 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 2390 2391 stats->rxbroadcastframes_g += 2392 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 2393 2394 stats->rxmulticastframes_g += 2395 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 2396 2397 stats->rxcrcerror += 2398 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 2399 2400 stats->rxrunterror += 2401 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 2402 2403 stats->rxjabbererror += 2404 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 2405 2406 stats->rxundersize_g += 2407 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 2408 2409 stats->rxoversize_g += 2410 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 2411 2412 stats->rx64octets_gb += 2413 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 2414 2415 stats->rx65to127octets_gb += 2416 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 2417 2418 stats->rx128to255octets_gb += 2419 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 2420 2421 stats->rx256to511octets_gb += 2422 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 2423 2424 stats->rx512to1023octets_gb += 2425 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 2426 2427 stats->rx1024tomaxoctets_gb += 2428 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 2429 2430 stats->rxunicastframes_g += 2431 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 2432 2433 stats->rxlengtherror += 2434 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 2435 2436 stats->rxoutofrangetype += 2437 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 2438 2439 stats->rxpauseframes += 2440 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 2441 2442 stats->rxfifooverflow += 2443 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 2444 2445 stats->rxvlanframes_gb += 2446 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 2447 2448 stats->rxwatchdogerror += 2449 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 2450 2451 /* Un-freeze counters */ 2452 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 2453 } 2454 2455 static void 2456 xgbe_config_mmc(struct xgbe_prv_data *pdata) 2457 { 2458 /* Set counters to reset on read */ 2459 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); 2460 2461 /* Reset the counters */ 2462 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); 2463 } 2464 2465 static void 2466 xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, unsigned int queue) 2467 { 2468 unsigned int tx_status; 2469 unsigned long tx_timeout; 2470 2471 /* The Tx engine cannot be stopped if it is actively processing 2472 * packets. Wait for the Tx queue to empty the Tx fifo. Don't 2473 * wait forever though... 2474 */ 2475 tx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz); 2476 while (ticks < tx_timeout) { 2477 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); 2478 if ((XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) && 2479 (XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0)) 2480 break; 2481 2482 DELAY(500); 2483 } 2484 2485 if (ticks >= tx_timeout) 2486 axgbe_printf(1, "timed out waiting for Tx queue %u to empty\n", 2487 queue); 2488 } 2489 2490 static void 2491 xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, unsigned int queue) 2492 { 2493 unsigned int tx_dsr, tx_pos, tx_qidx; 2494 unsigned int tx_status; 2495 unsigned long tx_timeout; 2496 2497 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) 2498 return (xgbe_txq_prepare_tx_stop(pdata, queue)); 2499 2500 /* Calculate the status register to read and the position within */ 2501 if (queue < DMA_DSRX_FIRST_QUEUE) { 2502 tx_dsr = DMA_DSR0; 2503 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START; 2504 } else { 2505 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; 2506 2507 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); 2508 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + 2509 DMA_DSRX_TPS_START; 2510 } 2511 2512 /* The Tx engine cannot be stopped if it is actively processing 2513 * descriptors. Wait for the Tx engine to enter the stopped or 2514 * suspended state. Don't wait forever though... 2515 */ 2516 tx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz); 2517 while (ticks < tx_timeout) { 2518 tx_status = XGMAC_IOREAD(pdata, tx_dsr); 2519 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); 2520 if ((tx_status == DMA_TPS_STOPPED) || 2521 (tx_status == DMA_TPS_SUSPENDED)) 2522 break; 2523 2524 DELAY(500); 2525 } 2526 2527 if (ticks >= tx_timeout) 2528 axgbe_printf(1, "timed out waiting for Tx DMA channel %u to stop\n", 2529 queue); 2530 } 2531 2532 static void 2533 xgbe_enable_tx(struct xgbe_prv_data *pdata) 2534 { 2535 unsigned int i; 2536 2537 /* Enable each Tx DMA channel */ 2538 for (i = 0; i < pdata->channel_count; i++) { 2539 if (!pdata->channel[i]->tx_ring) 2540 break; 2541 2542 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); 2543 } 2544 2545 /* Enable each Tx queue */ 2546 for (i = 0; i < pdata->tx_q_count; i++) 2547 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 2548 MTL_Q_ENABLED); 2549 2550 /* Enable MAC Tx */ 2551 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 2552 } 2553 2554 static void 2555 xgbe_disable_tx(struct xgbe_prv_data *pdata) 2556 { 2557 unsigned int i; 2558 2559 /* Prepare for Tx DMA channel stop */ 2560 for (i = 0; i < pdata->tx_q_count; i++) 2561 xgbe_prepare_tx_stop(pdata, i); 2562 2563 /* Disable MAC Tx */ 2564 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 2565 2566 /* Disable each Tx queue */ 2567 for (i = 0; i < pdata->tx_q_count; i++) 2568 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); 2569 2570 /* Disable each Tx DMA channel */ 2571 for (i = 0; i < pdata->channel_count; i++) { 2572 if (!pdata->channel[i]->tx_ring) 2573 break; 2574 2575 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); 2576 } 2577 } 2578 2579 static void 2580 xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, unsigned int queue) 2581 { 2582 unsigned int rx_status; 2583 unsigned long rx_timeout; 2584 2585 /* The Rx engine cannot be stopped if it is actively processing 2586 * packets. Wait for the Rx queue to empty the Rx fifo. Don't 2587 * wait forever though... 2588 */ 2589 rx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz); 2590 while (ticks < rx_timeout) { 2591 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); 2592 if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) && 2593 (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0)) 2594 break; 2595 2596 DELAY(500); 2597 } 2598 2599 if (ticks >= rx_timeout) 2600 axgbe_printf(1, "timed out waiting for Rx queue %d to empty\n", 2601 queue); 2602 } 2603 2604 static void 2605 xgbe_enable_rx(struct xgbe_prv_data *pdata) 2606 { 2607 unsigned int reg_val, i; 2608 2609 /* Enable each Rx DMA channel */ 2610 for (i = 0; i < pdata->channel_count; i++) { 2611 if (!pdata->channel[i]->rx_ring) 2612 break; 2613 2614 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); 2615 } 2616 2617 /* Enable each Rx queue */ 2618 reg_val = 0; 2619 for (i = 0; i < pdata->rx_q_count; i++) 2620 reg_val |= (0x02 << (i << 1)); 2621 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 2622 2623 /* Enable MAC Rx */ 2624 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 2625 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 2626 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 2627 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 2628 } 2629 2630 static void 2631 xgbe_disable_rx(struct xgbe_prv_data *pdata) 2632 { 2633 unsigned int i; 2634 2635 /* Disable MAC Rx */ 2636 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 2637 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 2638 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 2639 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 2640 2641 /* Prepare for Rx DMA channel stop */ 2642 for (i = 0; i < pdata->rx_q_count; i++) 2643 xgbe_prepare_rx_stop(pdata, i); 2644 2645 /* Disable each Rx queue */ 2646 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 2647 2648 /* Disable each Rx DMA channel */ 2649 for (i = 0; i < pdata->channel_count; i++) { 2650 if (!pdata->channel[i]->rx_ring) 2651 break; 2652 2653 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); 2654 } 2655 } 2656 2657 static void 2658 xgbe_powerup_tx(struct xgbe_prv_data *pdata) 2659 { 2660 unsigned int i; 2661 2662 /* Enable each Tx DMA channel */ 2663 for (i = 0; i < pdata->channel_count; i++) { 2664 if (!pdata->channel[i]->tx_ring) 2665 break; 2666 2667 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); 2668 } 2669 2670 /* Enable MAC Tx */ 2671 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 2672 } 2673 2674 static void 2675 xgbe_powerdown_tx(struct xgbe_prv_data *pdata) 2676 { 2677 unsigned int i; 2678 2679 /* Prepare for Tx DMA channel stop */ 2680 for (i = 0; i < pdata->tx_q_count; i++) 2681 xgbe_prepare_tx_stop(pdata, i); 2682 2683 /* Disable MAC Tx */ 2684 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 2685 2686 /* Disable each Tx DMA channel */ 2687 for (i = 0; i < pdata->channel_count; i++) { 2688 if (!pdata->channel[i]->tx_ring) 2689 break; 2690 2691 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); 2692 } 2693 } 2694 2695 static void 2696 xgbe_powerup_rx(struct xgbe_prv_data *pdata) 2697 { 2698 unsigned int i; 2699 2700 /* Enable each Rx DMA channel */ 2701 for (i = 0; i < pdata->channel_count; i++) { 2702 if (!pdata->channel[i]->rx_ring) 2703 break; 2704 2705 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); 2706 } 2707 } 2708 2709 static void 2710 xgbe_powerdown_rx(struct xgbe_prv_data *pdata) 2711 { 2712 unsigned int i; 2713 2714 /* Disable each Rx DMA channel */ 2715 for (i = 0; i < pdata->channel_count; i++) { 2716 if (!pdata->channel[i]->rx_ring) 2717 break; 2718 2719 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); 2720 } 2721 } 2722 2723 static int 2724 xgbe_init(struct xgbe_prv_data *pdata) 2725 { 2726 struct xgbe_desc_if *desc_if = &pdata->desc_if; 2727 int ret; 2728 2729 /* Flush Tx queues */ 2730 ret = xgbe_flush_tx_queues(pdata); 2731 if (ret) { 2732 axgbe_error("error flushing TX queues\n"); 2733 return (ret); 2734 } 2735 2736 /* 2737 * Initialize DMA related features 2738 */ 2739 xgbe_config_dma_bus(pdata); 2740 xgbe_config_dma_cache(pdata); 2741 xgbe_config_osp_mode(pdata); 2742 xgbe_config_pbl_val(pdata); 2743 xgbe_config_rx_coalesce(pdata); 2744 xgbe_config_tx_coalesce(pdata); 2745 xgbe_config_rx_buffer_size(pdata); 2746 xgbe_config_tso_mode(pdata); 2747 xgbe_config_sph_mode(pdata); 2748 xgbe_config_rss(pdata); 2749 desc_if->wrapper_tx_desc_init(pdata); 2750 desc_if->wrapper_rx_desc_init(pdata); 2751 xgbe_enable_dma_interrupts(pdata); 2752 2753 /* 2754 * Initialize MTL related features 2755 */ 2756 xgbe_config_mtl_mode(pdata); 2757 xgbe_config_queue_mapping(pdata); 2758 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); 2759 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); 2760 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); 2761 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); 2762 xgbe_config_tx_fifo_size(pdata); 2763 xgbe_config_rx_fifo_size(pdata); 2764 /*TODO: Error Packet and undersized good Packet forwarding enable 2765 (FEP and FUP) 2766 */ 2767 xgbe_enable_mtl_interrupts(pdata); 2768 2769 /* 2770 * Initialize MAC related features 2771 */ 2772 xgbe_config_mac_address(pdata); 2773 xgbe_config_rx_mode(pdata); 2774 xgbe_config_jumbo_enable(pdata); 2775 xgbe_config_flow_control(pdata); 2776 xgbe_config_mac_speed(pdata); 2777 xgbe_config_checksum_offload(pdata); 2778 xgbe_config_vlan_support(pdata); 2779 xgbe_config_mmc(pdata); 2780 xgbe_enable_mac_interrupts(pdata); 2781 2782 return (0); 2783 } 2784 2785 void 2786 xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) 2787 { 2788 2789 hw_if->tx_complete = xgbe_tx_complete; 2790 2791 hw_if->set_mac_address = xgbe_set_mac_address; 2792 hw_if->config_rx_mode = xgbe_config_rx_mode; 2793 2794 hw_if->enable_rx_csum = xgbe_enable_rx_csum; 2795 hw_if->disable_rx_csum = xgbe_disable_rx_csum; 2796 2797 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; 2798 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; 2799 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; 2800 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; 2801 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; 2802 2803 hw_if->read_mmd_regs = xgbe_read_mmd_regs; 2804 hw_if->write_mmd_regs = xgbe_write_mmd_regs; 2805 2806 hw_if->set_speed = xgbe_set_speed; 2807 2808 hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode; 2809 hw_if->read_ext_mii_regs = xgbe_read_ext_mii_regs; 2810 hw_if->write_ext_mii_regs = xgbe_write_ext_mii_regs; 2811 2812 hw_if->set_gpio = xgbe_set_gpio; 2813 hw_if->clr_gpio = xgbe_clr_gpio; 2814 2815 hw_if->enable_tx = xgbe_enable_tx; 2816 hw_if->disable_tx = xgbe_disable_tx; 2817 hw_if->enable_rx = xgbe_enable_rx; 2818 hw_if->disable_rx = xgbe_disable_rx; 2819 2820 hw_if->powerup_tx = xgbe_powerup_tx; 2821 hw_if->powerdown_tx = xgbe_powerdown_tx; 2822 hw_if->powerup_rx = xgbe_powerup_rx; 2823 hw_if->powerdown_rx = xgbe_powerdown_rx; 2824 2825 hw_if->dev_read = xgbe_dev_read; 2826 hw_if->enable_int = xgbe_enable_int; 2827 hw_if->disable_int = xgbe_disable_int; 2828 hw_if->init = xgbe_init; 2829 hw_if->exit = xgbe_exit; 2830 2831 /* Descriptor related Sequences have to be initialized here */ 2832 hw_if->tx_desc_init = xgbe_tx_desc_init; 2833 hw_if->rx_desc_init = xgbe_rx_desc_init; 2834 hw_if->tx_desc_reset = xgbe_tx_desc_reset; 2835 hw_if->is_last_desc = xgbe_is_last_desc; 2836 hw_if->is_context_desc = xgbe_is_context_desc; 2837 2838 /* For FLOW ctrl */ 2839 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; 2840 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; 2841 2842 /* For RX coalescing */ 2843 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; 2844 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; 2845 hw_if->usec_to_riwt = xgbe_usec_to_riwt; 2846 hw_if->riwt_to_usec = xgbe_riwt_to_usec; 2847 2848 /* For RX and TX threshold config */ 2849 hw_if->config_rx_threshold = xgbe_config_rx_threshold; 2850 hw_if->config_tx_threshold = xgbe_config_tx_threshold; 2851 2852 /* For RX and TX Store and Forward Mode config */ 2853 hw_if->config_rsf_mode = xgbe_config_rsf_mode; 2854 hw_if->config_tsf_mode = xgbe_config_tsf_mode; 2855 2856 /* For TX DMA Operating on Second Frame config */ 2857 hw_if->config_osp_mode = xgbe_config_osp_mode; 2858 2859 /* For MMC statistics support */ 2860 hw_if->tx_mmc_int = xgbe_tx_mmc_int; 2861 hw_if->rx_mmc_int = xgbe_rx_mmc_int; 2862 hw_if->read_mmc_stats = xgbe_read_mmc_stats; 2863 2864 /* For Receive Side Scaling */ 2865 hw_if->enable_rss = xgbe_enable_rss; 2866 hw_if->disable_rss = xgbe_disable_rss; 2867 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; 2868 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; 2869 } 2870