1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 #include "opt_wlan.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/sysctl.h> 47 #include <sys/mbuf.h> 48 #include <sys/malloc.h> 49 #include <sys/lock.h> 50 #include <sys/mutex.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/errno.h> 55 #include <sys/callout.h> 56 #include <sys/bus.h> 57 #include <sys/endian.h> 58 #include <sys/kthread.h> 59 #include <sys/taskqueue.h> 60 #include <sys/priv.h> 61 62 #include <machine/bus.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 #include <net/if_arp.h> 69 #include <net/ethernet.h> 70 #include <net/if_llc.h> 71 72 #include <net80211/ieee80211_var.h> 73 #include <net80211/ieee80211_regdomain.h> 74 #ifdef IEEE80211_SUPPORT_SUPERG 75 #include <net80211/ieee80211_superg.h> 76 #endif 77 #ifdef IEEE80211_SUPPORT_TDMA 78 #include <net80211/ieee80211_tdma.h> 79 #endif 80 81 #include <net/bpf.h> 82 83 #ifdef INET 84 #include <netinet/in.h> 85 #include <netinet/if_ether.h> 86 #endif 87 88 #include <dev/ath/if_athvar.h> 89 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 90 #include <dev/ath/ath_hal/ah_diagcodes.h> 91 92 #include <dev/ath/if_ath_debug.h> 93 #include <dev/ath/if_ath_misc.h> 94 #include <dev/ath/if_ath_tx.h> 95 #include <dev/ath/if_ath_sysctl.h> 96 97 #ifdef ATH_TX99_DIAG 98 #include <dev/ath/ath_tx99/ath_tx99.h> 99 #endif 100 101 /* 102 * ATH_BCBUF determines the number of vap's that can transmit 103 * beacons and also (currently) the number of vap's that can 104 * have unique mac addresses/bssid. When staggering beacons 105 * 4 is probably a good max as otherwise the beacons become 106 * very closely spaced and there is limited time for cab q traffic 107 * to go out. You can burst beacons instead but that is not good 108 * for stations in power save and at some point you really want 109 * another radio (and channel). 110 * 111 * The limit on the number of mac addresses is tied to our use of 112 * the U/L bit and tracking addresses in a byte; it would be 113 * worthwhile to allow more for applications like proxy sta. 114 */ 115 CTASSERT(ATH_BCBUF <= 8); 116 117 static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 118 const char name[IFNAMSIZ], int unit, int opmode, 119 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 120 const uint8_t mac[IEEE80211_ADDR_LEN]); 121 static void ath_vap_delete(struct ieee80211vap *); 122 static void ath_init(void *); 123 static void ath_stop_locked(struct ifnet *); 124 static void ath_stop(struct ifnet *); 125 static void ath_start(struct ifnet *); 126 static int ath_reset_vap(struct ieee80211vap *, u_long); 127 static int ath_media_change(struct ifnet *); 128 static void ath_watchdog(void *); 129 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 130 static void ath_fatal_proc(void *, int); 131 static void ath_bmiss_vap(struct ieee80211vap *); 132 static void ath_bmiss_proc(void *, int); 133 static int ath_keyset(struct ath_softc *, const struct ieee80211_key *, 134 struct ieee80211_node *); 135 static int ath_key_alloc(struct ieee80211vap *, 136 struct ieee80211_key *, 137 ieee80211_keyix *, ieee80211_keyix *); 138 static int ath_key_delete(struct ieee80211vap *, 139 const struct ieee80211_key *); 140 static int ath_key_set(struct ieee80211vap *, const struct ieee80211_key *, 141 const u_int8_t mac[IEEE80211_ADDR_LEN]); 142 static void ath_key_update_begin(struct ieee80211vap *); 143 static void ath_key_update_end(struct ieee80211vap *); 144 static void ath_update_mcast(struct ifnet *); 145 static void ath_update_promisc(struct ifnet *); 146 static void ath_mode_init(struct ath_softc *); 147 static void ath_setslottime(struct ath_softc *); 148 static void ath_updateslot(struct ifnet *); 149 static int ath_beaconq_setup(struct ath_hal *); 150 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 151 static void ath_beacon_update(struct ieee80211vap *, int item); 152 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 153 static void ath_beacon_proc(void *, int); 154 static struct ath_buf *ath_beacon_generate(struct ath_softc *, 155 struct ieee80211vap *); 156 static void ath_bstuck_proc(void *, int); 157 static void ath_beacon_return(struct ath_softc *, struct ath_buf *); 158 static void ath_beacon_free(struct ath_softc *); 159 static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *); 160 static void ath_descdma_cleanup(struct ath_softc *sc, 161 struct ath_descdma *, ath_bufhead *); 162 static int ath_desc_alloc(struct ath_softc *); 163 static void ath_desc_free(struct ath_softc *); 164 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 165 const uint8_t [IEEE80211_ADDR_LEN]); 166 static void ath_node_free(struct ieee80211_node *); 167 static void ath_node_getsignal(const struct ieee80211_node *, 168 int8_t *, int8_t *); 169 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 170 static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 171 int subtype, int rssi, int nf); 172 static void ath_setdefantenna(struct ath_softc *, u_int); 173 static void ath_rx_proc(void *, int); 174 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 175 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 176 static int ath_tx_setup(struct ath_softc *, int, int); 177 static int ath_wme_update(struct ieee80211com *); 178 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 179 static void ath_tx_cleanup(struct ath_softc *); 180 static void ath_tx_proc_q0(void *, int); 181 static void ath_tx_proc_q0123(void *, int); 182 static void ath_tx_proc(void *, int); 183 static void ath_tx_draintxq(struct ath_softc *, struct ath_txq *); 184 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 185 static void ath_draintxq(struct ath_softc *); 186 static void ath_stoprecv(struct ath_softc *); 187 static int ath_startrecv(struct ath_softc *); 188 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 189 static void ath_scan_start(struct ieee80211com *); 190 static void ath_scan_end(struct ieee80211com *); 191 static void ath_set_channel(struct ieee80211com *); 192 static void ath_calibrate(void *); 193 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 194 static void ath_setup_stationkey(struct ieee80211_node *); 195 static void ath_newassoc(struct ieee80211_node *, int); 196 static int ath_setregdomain(struct ieee80211com *, 197 struct ieee80211_regdomain *, int, 198 struct ieee80211_channel []); 199 static void ath_getradiocaps(struct ieee80211com *, int, int *, 200 struct ieee80211_channel []); 201 static int ath_getchannels(struct ath_softc *); 202 static void ath_led_event(struct ath_softc *, int); 203 204 static int ath_rate_setup(struct ath_softc *, u_int mode); 205 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 206 207 static void ath_announce(struct ath_softc *); 208 209 #ifdef IEEE80211_SUPPORT_TDMA 210 static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, 211 u_int32_t bintval); 212 static void ath_tdma_bintvalsetup(struct ath_softc *sc, 213 const struct ieee80211_tdma_state *tdma); 214 static void ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap); 215 static void ath_tdma_update(struct ieee80211_node *ni, 216 const struct ieee80211_tdma_param *tdma, int); 217 static void ath_tdma_beacon_send(struct ath_softc *sc, 218 struct ieee80211vap *vap); 219 220 static __inline void 221 ath_hal_setcca(struct ath_hal *ah, int ena) 222 { 223 /* 224 * NB: fill me in; this is not provided by default because disabling 225 * CCA in most locales violates regulatory. 226 */ 227 } 228 229 static __inline int 230 ath_hal_getcca(struct ath_hal *ah) 231 { 232 u_int32_t diag; 233 if (ath_hal_getcapability(ah, HAL_CAP_DIAG, 0, &diag) != HAL_OK) 234 return 1; 235 return ((diag & 0x500000) == 0); 236 } 237 238 #define TDMA_EP_MULTIPLIER (1<<10) /* pow2 to optimize out * and / */ 239 #define TDMA_LPF_LEN 6 240 #define TDMA_DUMMY_MARKER 0x127 241 #define TDMA_EP_MUL(x, mul) ((x) * (mul)) 242 #define TDMA_IN(x) (TDMA_EP_MUL((x), TDMA_EP_MULTIPLIER)) 243 #define TDMA_LPF(x, y, len) \ 244 ((x != TDMA_DUMMY_MARKER) ? (((x) * ((len)-1) + (y)) / (len)) : (y)) 245 #define TDMA_SAMPLE(x, y) do { \ 246 x = TDMA_LPF((x), TDMA_IN(y), TDMA_LPF_LEN); \ 247 } while (0) 248 #define TDMA_EP_RND(x,mul) \ 249 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 250 #define TDMA_AVG(x) TDMA_EP_RND(x, TDMA_EP_MULTIPLIER) 251 #endif /* IEEE80211_SUPPORT_TDMA */ 252 253 SYSCTL_DECL(_hw_ath); 254 255 /* XXX validate sysctl values */ 256 static int ath_longcalinterval = 30; /* long cals every 30 secs */ 257 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 258 0, "long chip calibration interval (secs)"); 259 static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 260 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 261 0, "short chip calibration interval (msecs)"); 262 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 263 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 264 0, "reset chip calibration results (secs)"); 265 static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */ 266 SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval, 267 0, "ANI calibration (msecs)"); 268 269 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 270 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 271 0, "rx buffers allocated"); 272 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 273 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 274 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 275 0, "tx buffers allocated"); 276 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 277 278 static int ath_bstuck_threshold = 4; /* max missed beacons */ 279 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 280 0, "max missed beacon xmits before chip reset"); 281 282 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 283 284 #define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20) 285 #define HAL_MODE_HT40 \ 286 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \ 287 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS) 288 int 289 ath_attach(u_int16_t devid, struct ath_softc *sc) 290 { 291 struct ifnet *ifp; 292 struct ieee80211com *ic; 293 struct ath_hal *ah = NULL; 294 HAL_STATUS status; 295 int error = 0, i; 296 u_int wmodes; 297 uint8_t macaddr[IEEE80211_ADDR_LEN]; 298 299 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 300 301 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 302 if (ifp == NULL) { 303 device_printf(sc->sc_dev, "can not if_alloc()\n"); 304 error = ENOSPC; 305 goto bad; 306 } 307 ic = ifp->if_l2com; 308 309 /* set these up early for if_printf use */ 310 if_initname(ifp, device_get_name(sc->sc_dev), 311 device_get_unit(sc->sc_dev)); 312 313 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, sc->sc_eepromdata, &status); 314 if (ah == NULL) { 315 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 316 status); 317 error = ENXIO; 318 goto bad; 319 } 320 sc->sc_ah = ah; 321 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 322 #ifdef ATH_DEBUG 323 sc->sc_debug = ath_debug; 324 #endif 325 326 /* 327 * Check if the MAC has multi-rate retry support. 328 * We do this by trying to setup a fake extended 329 * descriptor. MAC's that don't have support will 330 * return false w/o doing anything. MAC's that do 331 * support it will return true w/o doing anything. 332 */ 333 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 334 335 /* 336 * Check if the device has hardware counters for PHY 337 * errors. If so we need to enable the MIB interrupt 338 * so we can act on stat triggers. 339 */ 340 if (ath_hal_hwphycounters(ah)) 341 sc->sc_needmib = 1; 342 343 /* 344 * Get the hardware key cache size. 345 */ 346 sc->sc_keymax = ath_hal_keycachesize(ah); 347 if (sc->sc_keymax > ATH_KEYMAX) { 348 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 349 ATH_KEYMAX, sc->sc_keymax); 350 sc->sc_keymax = ATH_KEYMAX; 351 } 352 /* 353 * Reset the key cache since some parts do not 354 * reset the contents on initial power up. 355 */ 356 for (i = 0; i < sc->sc_keymax; i++) 357 ath_hal_keyreset(ah, i); 358 359 /* 360 * Collect the default channel list. 361 */ 362 error = ath_getchannels(sc); 363 if (error != 0) 364 goto bad; 365 366 /* 367 * Setup rate tables for all potential media types. 368 */ 369 ath_rate_setup(sc, IEEE80211_MODE_11A); 370 ath_rate_setup(sc, IEEE80211_MODE_11B); 371 ath_rate_setup(sc, IEEE80211_MODE_11G); 372 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 373 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 374 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 375 ath_rate_setup(sc, IEEE80211_MODE_11NA); 376 ath_rate_setup(sc, IEEE80211_MODE_11NG); 377 ath_rate_setup(sc, IEEE80211_MODE_HALF); 378 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 379 380 /* NB: setup here so ath_rate_update is happy */ 381 ath_setcurmode(sc, IEEE80211_MODE_11A); 382 383 /* 384 * Allocate tx+rx descriptors and populate the lists. 385 */ 386 error = ath_desc_alloc(sc); 387 if (error != 0) { 388 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 389 goto bad; 390 } 391 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0); 392 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0); 393 394 ATH_TXBUF_LOCK_INIT(sc); 395 396 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 397 taskqueue_thread_enqueue, &sc->sc_tq); 398 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 399 "%s taskq", ifp->if_xname); 400 401 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 402 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 403 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 404 405 /* 406 * Allocate hardware transmit queues: one queue for 407 * beacon frames and one data queue for each QoS 408 * priority. Note that the hal handles resetting 409 * these queues at the needed time. 410 * 411 * XXX PS-Poll 412 */ 413 sc->sc_bhalq = ath_beaconq_setup(ah); 414 if (sc->sc_bhalq == (u_int) -1) { 415 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 416 error = EIO; 417 goto bad2; 418 } 419 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 420 if (sc->sc_cabq == NULL) { 421 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 422 error = EIO; 423 goto bad2; 424 } 425 /* NB: insure BK queue is the lowest priority h/w queue */ 426 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 427 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 428 ieee80211_wme_acnames[WME_AC_BK]); 429 error = EIO; 430 goto bad2; 431 } 432 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 433 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 434 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 435 /* 436 * Not enough hardware tx queues to properly do WME; 437 * just punt and assign them all to the same h/w queue. 438 * We could do a better job of this if, for example, 439 * we allocate queues when we switch from station to 440 * AP mode. 441 */ 442 if (sc->sc_ac2q[WME_AC_VI] != NULL) 443 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 444 if (sc->sc_ac2q[WME_AC_BE] != NULL) 445 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 446 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 447 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 448 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 449 } 450 451 /* 452 * Special case certain configurations. Note the 453 * CAB queue is handled by these specially so don't 454 * include them when checking the txq setup mask. 455 */ 456 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 457 case 0x01: 458 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 459 break; 460 case 0x0f: 461 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 462 break; 463 default: 464 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 465 break; 466 } 467 468 /* 469 * Setup rate control. Some rate control modules 470 * call back to change the anntena state so expose 471 * the necessary entry points. 472 * XXX maybe belongs in struct ath_ratectrl? 473 */ 474 sc->sc_setdefantenna = ath_setdefantenna; 475 sc->sc_rc = ath_rate_attach(sc); 476 if (sc->sc_rc == NULL) { 477 error = EIO; 478 goto bad2; 479 } 480 481 sc->sc_blinking = 0; 482 sc->sc_ledstate = 1; 483 sc->sc_ledon = 0; /* low true */ 484 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 485 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 486 /* 487 * Auto-enable soft led processing for IBM cards and for 488 * 5211 minipci cards. Users can also manually enable/disable 489 * support with a sysctl. 490 */ 491 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 492 if (sc->sc_softled) { 493 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 494 HAL_GPIO_MUX_MAC_NETWORK_LED); 495 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 496 } 497 498 ifp->if_softc = sc; 499 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 500 ifp->if_start = ath_start; 501 ifp->if_ioctl = ath_ioctl; 502 ifp->if_init = ath_init; 503 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 504 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 505 IFQ_SET_READY(&ifp->if_snd); 506 507 ic->ic_ifp = ifp; 508 /* XXX not right but it's not used anywhere important */ 509 ic->ic_phytype = IEEE80211_T_OFDM; 510 ic->ic_opmode = IEEE80211_M_STA; 511 ic->ic_caps = 512 IEEE80211_C_STA /* station mode */ 513 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 514 | IEEE80211_C_HOSTAP /* hostap mode */ 515 | IEEE80211_C_MONITOR /* monitor mode */ 516 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 517 | IEEE80211_C_WDS /* 4-address traffic works */ 518 | IEEE80211_C_MBSS /* mesh point link mode */ 519 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 520 | IEEE80211_C_SHSLOT /* short slot time supported */ 521 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 522 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 523 | IEEE80211_C_TXFRAG /* handle tx frags */ 524 ; 525 /* 526 * Query the hal to figure out h/w crypto support. 527 */ 528 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 529 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 530 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 531 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 532 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 533 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 534 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 535 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 536 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 537 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 538 /* 539 * Check if h/w does the MIC and/or whether the 540 * separate key cache entries are required to 541 * handle both tx+rx MIC keys. 542 */ 543 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 544 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 545 /* 546 * If the h/w supports storing tx+rx MIC keys 547 * in one cache slot automatically enable use. 548 */ 549 if (ath_hal_hastkipsplit(ah) || 550 !ath_hal_settkipsplit(ah, AH_FALSE)) 551 sc->sc_splitmic = 1; 552 /* 553 * If the h/w can do TKIP MIC together with WME then 554 * we use it; otherwise we force the MIC to be done 555 * in software by the net80211 layer. 556 */ 557 if (ath_hal_haswmetkipmic(ah)) 558 sc->sc_wmetkipmic = 1; 559 } 560 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 561 /* 562 * Check for multicast key search support. 563 */ 564 if (ath_hal_hasmcastkeysearch(sc->sc_ah) && 565 !ath_hal_getmcastkeysearch(sc->sc_ah)) { 566 ath_hal_setmcastkeysearch(sc->sc_ah, 1); 567 } 568 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 569 /* 570 * Mark key cache slots associated with global keys 571 * as in use. If we knew TKIP was not to be used we 572 * could leave the +32, +64, and +32+64 slots free. 573 */ 574 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 575 setbit(sc->sc_keymap, i); 576 setbit(sc->sc_keymap, i+64); 577 if (sc->sc_splitmic) { 578 setbit(sc->sc_keymap, i+32); 579 setbit(sc->sc_keymap, i+32+64); 580 } 581 } 582 /* 583 * TPC support can be done either with a global cap or 584 * per-packet support. The latter is not available on 585 * all parts. We're a bit pedantic here as all parts 586 * support a global cap. 587 */ 588 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 589 ic->ic_caps |= IEEE80211_C_TXPMGT; 590 591 /* 592 * Mark WME capability only if we have sufficient 593 * hardware queues to do proper priority scheduling. 594 */ 595 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 596 ic->ic_caps |= IEEE80211_C_WME; 597 /* 598 * Check for misc other capabilities. 599 */ 600 if (ath_hal_hasbursting(ah)) 601 ic->ic_caps |= IEEE80211_C_BURST; 602 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 603 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah); 604 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 605 if (ath_hal_hasfastframes(ah)) 606 ic->ic_caps |= IEEE80211_C_FF; 607 wmodes = ath_hal_getwirelessmodes(ah); 608 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 609 ic->ic_caps |= IEEE80211_C_TURBOP; 610 #ifdef IEEE80211_SUPPORT_TDMA 611 if (ath_hal_macversion(ah) > 0x78) { 612 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 613 ic->ic_tdma_update = ath_tdma_update; 614 } 615 #endif 616 617 /* 618 * The if_ath 11n support is completely not ready for normal use. 619 * Enabling this option will likely break everything and everything. 620 * Don't think of doing that unless you know what you're doing. 621 */ 622 623 #ifdef DO_ATH_11N 624 /* 625 * Query HT capabilities 626 */ 627 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK && 628 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) { 629 int rxs, txs; 630 631 device_printf(sc->sc_dev, "[HT] enabling HT modes\n"); 632 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */ 633 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */ 634 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */ 635 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 636 /* At the present time, the hardware doesn't support short-GI in 20mhz mode */ 637 #if 0 638 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 639 #endif 640 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */ 641 ; 642 643 if (wmodes & HAL_MODE_HT40) 644 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40 645 | IEEE80211_HTCAP_SHORTGI40; 646 647 /* 648 * rx/tx stream is not currently used anywhere; it needs to be taken 649 * into account when negotiating which MCS rates it'll receive and 650 * what MCS rates are available for TX. 651 */ 652 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &rxs); 653 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &txs); 654 655 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask); 656 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask); 657 658 ic->ic_txstream = txs; 659 ic->ic_rxstream = rxs; 660 661 device_printf(sc->sc_dev, "[HT] %d RX streams; %d TX streams\n", rxs, txs); 662 } 663 #endif 664 665 /* 666 * Indicate we need the 802.11 header padded to a 667 * 32-bit boundary for 4-address and QoS frames. 668 */ 669 ic->ic_flags |= IEEE80211_F_DATAPAD; 670 671 /* 672 * Query the hal about antenna support. 673 */ 674 sc->sc_defant = ath_hal_getdefantenna(ah); 675 676 /* 677 * Not all chips have the VEOL support we want to 678 * use with IBSS beacons; check here for it. 679 */ 680 sc->sc_hasveol = ath_hal_hasveol(ah); 681 682 /* get mac address from hardware */ 683 ath_hal_getmac(ah, macaddr); 684 if (sc->sc_hasbmask) 685 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 686 687 /* NB: used to size node table key mapping array */ 688 ic->ic_max_keyix = sc->sc_keymax; 689 /* call MI attach routine. */ 690 ieee80211_ifattach(ic, macaddr); 691 ic->ic_setregdomain = ath_setregdomain; 692 ic->ic_getradiocaps = ath_getradiocaps; 693 sc->sc_opmode = HAL_M_STA; 694 695 /* override default methods */ 696 ic->ic_newassoc = ath_newassoc; 697 ic->ic_updateslot = ath_updateslot; 698 ic->ic_wme.wme_update = ath_wme_update; 699 ic->ic_vap_create = ath_vap_create; 700 ic->ic_vap_delete = ath_vap_delete; 701 ic->ic_raw_xmit = ath_raw_xmit; 702 ic->ic_update_mcast = ath_update_mcast; 703 ic->ic_update_promisc = ath_update_promisc; 704 ic->ic_node_alloc = ath_node_alloc; 705 sc->sc_node_free = ic->ic_node_free; 706 ic->ic_node_free = ath_node_free; 707 ic->ic_node_getsignal = ath_node_getsignal; 708 ic->ic_scan_start = ath_scan_start; 709 ic->ic_scan_end = ath_scan_end; 710 ic->ic_set_channel = ath_set_channel; 711 712 ieee80211_radiotap_attach(ic, 713 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 714 ATH_TX_RADIOTAP_PRESENT, 715 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 716 ATH_RX_RADIOTAP_PRESENT); 717 718 /* 719 * Setup dynamic sysctl's now that country code and 720 * regdomain are available from the hal. 721 */ 722 ath_sysctlattach(sc); 723 ath_sysctl_stats_attach(sc); 724 725 if (bootverbose) 726 ieee80211_announce(ic); 727 ath_announce(sc); 728 return 0; 729 bad2: 730 ath_tx_cleanup(sc); 731 ath_desc_free(sc); 732 bad: 733 if (ah) 734 ath_hal_detach(ah); 735 if (ifp != NULL) 736 if_free(ifp); 737 sc->sc_invalid = 1; 738 return error; 739 } 740 741 int 742 ath_detach(struct ath_softc *sc) 743 { 744 struct ifnet *ifp = sc->sc_ifp; 745 746 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 747 __func__, ifp->if_flags); 748 749 /* 750 * NB: the order of these is important: 751 * o stop the chip so no more interrupts will fire 752 * o call the 802.11 layer before detaching the hal to 753 * insure callbacks into the driver to delete global 754 * key cache entries can be handled 755 * o free the taskqueue which drains any pending tasks 756 * o reclaim the tx queue data structures after calling 757 * the 802.11 layer as we'll get called back to reclaim 758 * node state and potentially want to use them 759 * o to cleanup the tx queues the hal is called, so detach 760 * it last 761 * Other than that, it's straightforward... 762 */ 763 ath_stop(ifp); 764 ieee80211_ifdetach(ifp->if_l2com); 765 taskqueue_free(sc->sc_tq); 766 #ifdef ATH_TX99_DIAG 767 if (sc->sc_tx99 != NULL) 768 sc->sc_tx99->detach(sc->sc_tx99); 769 #endif 770 ath_rate_detach(sc->sc_rc); 771 ath_desc_free(sc); 772 ath_tx_cleanup(sc); 773 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 774 if_free(ifp); 775 776 return 0; 777 } 778 779 /* 780 * MAC address handling for multiple BSS on the same radio. 781 * The first vap uses the MAC address from the EEPROM. For 782 * subsequent vap's we set the U/L bit (bit 1) in the MAC 783 * address and use the next six bits as an index. 784 */ 785 static void 786 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 787 { 788 int i; 789 790 if (clone && sc->sc_hasbmask) { 791 /* NB: we only do this if h/w supports multiple bssid */ 792 for (i = 0; i < 8; i++) 793 if ((sc->sc_bssidmask & (1<<i)) == 0) 794 break; 795 if (i != 0) 796 mac[0] |= (i << 2)|0x2; 797 } else 798 i = 0; 799 sc->sc_bssidmask |= 1<<i; 800 sc->sc_hwbssidmask[0] &= ~mac[0]; 801 if (i == 0) 802 sc->sc_nbssid0++; 803 } 804 805 static void 806 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 807 { 808 int i = mac[0] >> 2; 809 uint8_t mask; 810 811 if (i != 0 || --sc->sc_nbssid0 == 0) { 812 sc->sc_bssidmask &= ~(1<<i); 813 /* recalculate bssid mask from remaining addresses */ 814 mask = 0xff; 815 for (i = 1; i < 8; i++) 816 if (sc->sc_bssidmask & (1<<i)) 817 mask &= ~((i<<2)|0x2); 818 sc->sc_hwbssidmask[0] |= mask; 819 } 820 } 821 822 /* 823 * Assign a beacon xmit slot. We try to space out 824 * assignments so when beacons are staggered the 825 * traffic coming out of the cab q has maximal time 826 * to go out before the next beacon is scheduled. 827 */ 828 static int 829 assign_bslot(struct ath_softc *sc) 830 { 831 u_int slot, free; 832 833 free = 0; 834 for (slot = 0; slot < ATH_BCBUF; slot++) 835 if (sc->sc_bslot[slot] == NULL) { 836 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 837 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 838 return slot; 839 free = slot; 840 /* NB: keep looking for a double slot */ 841 } 842 return free; 843 } 844 845 static struct ieee80211vap * 846 ath_vap_create(struct ieee80211com *ic, 847 const char name[IFNAMSIZ], int unit, int opmode, int flags, 848 const uint8_t bssid[IEEE80211_ADDR_LEN], 849 const uint8_t mac0[IEEE80211_ADDR_LEN]) 850 { 851 struct ath_softc *sc = ic->ic_ifp->if_softc; 852 struct ath_vap *avp; 853 struct ieee80211vap *vap; 854 uint8_t mac[IEEE80211_ADDR_LEN]; 855 int ic_opmode, needbeacon, error; 856 857 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap), 858 M_80211_VAP, M_WAITOK | M_ZERO); 859 needbeacon = 0; 860 IEEE80211_ADDR_COPY(mac, mac0); 861 862 ATH_LOCK(sc); 863 ic_opmode = opmode; /* default to opmode of new vap */ 864 switch (opmode) { 865 case IEEE80211_M_STA: 866 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */ 867 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 868 goto bad; 869 } 870 if (sc->sc_nvaps) { 871 /* 872 * With multiple vaps we must fall back 873 * to s/w beacon miss handling. 874 */ 875 flags |= IEEE80211_CLONE_NOBEACONS; 876 } 877 if (flags & IEEE80211_CLONE_NOBEACONS) { 878 /* 879 * Station mode w/o beacons are implemented w/ AP mode. 880 */ 881 ic_opmode = IEEE80211_M_HOSTAP; 882 } 883 break; 884 case IEEE80211_M_IBSS: 885 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 886 device_printf(sc->sc_dev, 887 "only 1 ibss vap supported\n"); 888 goto bad; 889 } 890 needbeacon = 1; 891 break; 892 case IEEE80211_M_AHDEMO: 893 #ifdef IEEE80211_SUPPORT_TDMA 894 if (flags & IEEE80211_CLONE_TDMA) { 895 if (sc->sc_nvaps != 0) { 896 device_printf(sc->sc_dev, 897 "only 1 tdma vap supported\n"); 898 goto bad; 899 } 900 needbeacon = 1; 901 flags |= IEEE80211_CLONE_NOBEACONS; 902 } 903 /* fall thru... */ 904 #endif 905 case IEEE80211_M_MONITOR: 906 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 907 /* 908 * Adopt existing mode. Adding a monitor or ahdemo 909 * vap to an existing configuration is of dubious 910 * value but should be ok. 911 */ 912 /* XXX not right for monitor mode */ 913 ic_opmode = ic->ic_opmode; 914 } 915 break; 916 case IEEE80211_M_HOSTAP: 917 case IEEE80211_M_MBSS: 918 needbeacon = 1; 919 break; 920 case IEEE80211_M_WDS: 921 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) { 922 device_printf(sc->sc_dev, 923 "wds not supported in sta mode\n"); 924 goto bad; 925 } 926 /* 927 * Silently remove any request for a unique 928 * bssid; WDS vap's always share the local 929 * mac address. 930 */ 931 flags &= ~IEEE80211_CLONE_BSSID; 932 if (sc->sc_nvaps == 0) 933 ic_opmode = IEEE80211_M_HOSTAP; 934 else 935 ic_opmode = ic->ic_opmode; 936 break; 937 default: 938 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 939 goto bad; 940 } 941 /* 942 * Check that a beacon buffer is available; the code below assumes it. 943 */ 944 if (needbeacon & STAILQ_EMPTY(&sc->sc_bbuf)) { 945 device_printf(sc->sc_dev, "no beacon buffer available\n"); 946 goto bad; 947 } 948 949 /* STA, AHDEMO? */ 950 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) { 951 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 952 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 953 } 954 955 vap = &avp->av_vap; 956 /* XXX can't hold mutex across if_alloc */ 957 ATH_UNLOCK(sc); 958 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, 959 bssid, mac); 960 ATH_LOCK(sc); 961 if (error != 0) { 962 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 963 __func__, error); 964 goto bad2; 965 } 966 967 /* h/w crypto support */ 968 vap->iv_key_alloc = ath_key_alloc; 969 vap->iv_key_delete = ath_key_delete; 970 vap->iv_key_set = ath_key_set; 971 vap->iv_key_update_begin = ath_key_update_begin; 972 vap->iv_key_update_end = ath_key_update_end; 973 974 /* override various methods */ 975 avp->av_recv_mgmt = vap->iv_recv_mgmt; 976 vap->iv_recv_mgmt = ath_recv_mgmt; 977 vap->iv_reset = ath_reset_vap; 978 vap->iv_update_beacon = ath_beacon_update; 979 avp->av_newstate = vap->iv_newstate; 980 vap->iv_newstate = ath_newstate; 981 avp->av_bmiss = vap->iv_bmiss; 982 vap->iv_bmiss = ath_bmiss_vap; 983 984 avp->av_bslot = -1; 985 if (needbeacon) { 986 /* 987 * Allocate beacon state and setup the q for buffered 988 * multicast frames. We know a beacon buffer is 989 * available because we checked above. 990 */ 991 avp->av_bcbuf = STAILQ_FIRST(&sc->sc_bbuf); 992 STAILQ_REMOVE_HEAD(&sc->sc_bbuf, bf_list); 993 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 994 /* 995 * Assign the vap to a beacon xmit slot. As above 996 * this cannot fail to find a free one. 997 */ 998 avp->av_bslot = assign_bslot(sc); 999 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 1000 ("beacon slot %u not empty", avp->av_bslot)); 1001 sc->sc_bslot[avp->av_bslot] = vap; 1002 sc->sc_nbcnvaps++; 1003 } 1004 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1005 /* 1006 * Multple vaps are to transmit beacons and we 1007 * have h/w support for TSF adjusting; enable 1008 * use of staggered beacons. 1009 */ 1010 sc->sc_stagbeacons = 1; 1011 } 1012 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1013 } 1014 1015 ic->ic_opmode = ic_opmode; 1016 if (opmode != IEEE80211_M_WDS) { 1017 sc->sc_nvaps++; 1018 if (opmode == IEEE80211_M_STA) 1019 sc->sc_nstavaps++; 1020 if (opmode == IEEE80211_M_MBSS) 1021 sc->sc_nmeshvaps++; 1022 } 1023 switch (ic_opmode) { 1024 case IEEE80211_M_IBSS: 1025 sc->sc_opmode = HAL_M_IBSS; 1026 break; 1027 case IEEE80211_M_STA: 1028 sc->sc_opmode = HAL_M_STA; 1029 break; 1030 case IEEE80211_M_AHDEMO: 1031 #ifdef IEEE80211_SUPPORT_TDMA 1032 if (vap->iv_caps & IEEE80211_C_TDMA) { 1033 sc->sc_tdma = 1; 1034 /* NB: disable tsf adjust */ 1035 sc->sc_stagbeacons = 0; 1036 } 1037 /* 1038 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1039 * just ap mode. 1040 */ 1041 /* fall thru... */ 1042 #endif 1043 case IEEE80211_M_HOSTAP: 1044 case IEEE80211_M_MBSS: 1045 sc->sc_opmode = HAL_M_HOSTAP; 1046 break; 1047 case IEEE80211_M_MONITOR: 1048 sc->sc_opmode = HAL_M_MONITOR; 1049 break; 1050 default: 1051 /* XXX should not happen */ 1052 break; 1053 } 1054 if (sc->sc_hastsfadd) { 1055 /* 1056 * Configure whether or not TSF adjust should be done. 1057 */ 1058 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1059 } 1060 if (flags & IEEE80211_CLONE_NOBEACONS) { 1061 /* 1062 * Enable s/w beacon miss handling. 1063 */ 1064 sc->sc_swbmiss = 1; 1065 } 1066 ATH_UNLOCK(sc); 1067 1068 /* complete setup */ 1069 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status); 1070 return vap; 1071 bad2: 1072 reclaim_address(sc, mac); 1073 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1074 bad: 1075 free(avp, M_80211_VAP); 1076 ATH_UNLOCK(sc); 1077 return NULL; 1078 } 1079 1080 static void 1081 ath_vap_delete(struct ieee80211vap *vap) 1082 { 1083 struct ieee80211com *ic = vap->iv_ic; 1084 struct ifnet *ifp = ic->ic_ifp; 1085 struct ath_softc *sc = ifp->if_softc; 1086 struct ath_hal *ah = sc->sc_ah; 1087 struct ath_vap *avp = ATH_VAP(vap); 1088 1089 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1090 /* 1091 * Quiesce the hardware while we remove the vap. In 1092 * particular we need to reclaim all references to 1093 * the vap state by any frames pending on the tx queues. 1094 */ 1095 ath_hal_intrset(ah, 0); /* disable interrupts */ 1096 ath_draintxq(sc); /* stop xmit side */ 1097 ath_stoprecv(sc); /* stop recv side */ 1098 } 1099 1100 ieee80211_vap_detach(vap); 1101 ATH_LOCK(sc); 1102 /* 1103 * Reclaim beacon state. Note this must be done before 1104 * the vap instance is reclaimed as we may have a reference 1105 * to it in the buffer for the beacon frame. 1106 */ 1107 if (avp->av_bcbuf != NULL) { 1108 if (avp->av_bslot != -1) { 1109 sc->sc_bslot[avp->av_bslot] = NULL; 1110 sc->sc_nbcnvaps--; 1111 } 1112 ath_beacon_return(sc, avp->av_bcbuf); 1113 avp->av_bcbuf = NULL; 1114 if (sc->sc_nbcnvaps == 0) { 1115 sc->sc_stagbeacons = 0; 1116 if (sc->sc_hastsfadd) 1117 ath_hal_settsfadjust(sc->sc_ah, 0); 1118 } 1119 /* 1120 * Reclaim any pending mcast frames for the vap. 1121 */ 1122 ath_tx_draintxq(sc, &avp->av_mcastq); 1123 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq); 1124 } 1125 /* 1126 * Update bookkeeping. 1127 */ 1128 if (vap->iv_opmode == IEEE80211_M_STA) { 1129 sc->sc_nstavaps--; 1130 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1131 sc->sc_swbmiss = 0; 1132 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1133 vap->iv_opmode == IEEE80211_M_MBSS) { 1134 reclaim_address(sc, vap->iv_myaddr); 1135 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1136 if (vap->iv_opmode == IEEE80211_M_MBSS) 1137 sc->sc_nmeshvaps--; 1138 } 1139 if (vap->iv_opmode != IEEE80211_M_WDS) 1140 sc->sc_nvaps--; 1141 #ifdef IEEE80211_SUPPORT_TDMA 1142 /* TDMA operation ceases when the last vap is destroyed */ 1143 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1144 sc->sc_tdma = 0; 1145 sc->sc_swbmiss = 0; 1146 } 1147 #endif 1148 ATH_UNLOCK(sc); 1149 free(avp, M_80211_VAP); 1150 1151 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1152 /* 1153 * Restart rx+tx machines if still running (RUNNING will 1154 * be reset if we just destroyed the last vap). 1155 */ 1156 if (ath_startrecv(sc) != 0) 1157 if_printf(ifp, "%s: unable to restart recv logic\n", 1158 __func__); 1159 if (sc->sc_beacons) { /* restart beacons */ 1160 #ifdef IEEE80211_SUPPORT_TDMA 1161 if (sc->sc_tdma) 1162 ath_tdma_config(sc, NULL); 1163 else 1164 #endif 1165 ath_beacon_config(sc, NULL); 1166 } 1167 ath_hal_intrset(ah, sc->sc_imask); 1168 } 1169 } 1170 1171 void 1172 ath_suspend(struct ath_softc *sc) 1173 { 1174 struct ifnet *ifp = sc->sc_ifp; 1175 struct ieee80211com *ic = ifp->if_l2com; 1176 1177 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1178 __func__, ifp->if_flags); 1179 1180 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0; 1181 if (ic->ic_opmode == IEEE80211_M_STA) 1182 ath_stop(ifp); 1183 else 1184 ieee80211_suspend_all(ic); 1185 /* 1186 * NB: don't worry about putting the chip in low power 1187 * mode; pci will power off our socket on suspend and 1188 * CardBus detaches the device. 1189 */ 1190 } 1191 1192 /* 1193 * Reset the key cache since some parts do not reset the 1194 * contents on resume. First we clear all entries, then 1195 * re-load keys that the 802.11 layer assumes are setup 1196 * in h/w. 1197 */ 1198 static void 1199 ath_reset_keycache(struct ath_softc *sc) 1200 { 1201 struct ifnet *ifp = sc->sc_ifp; 1202 struct ieee80211com *ic = ifp->if_l2com; 1203 struct ath_hal *ah = sc->sc_ah; 1204 int i; 1205 1206 for (i = 0; i < sc->sc_keymax; i++) 1207 ath_hal_keyreset(ah, i); 1208 ieee80211_crypto_reload_keys(ic); 1209 } 1210 1211 void 1212 ath_resume(struct ath_softc *sc) 1213 { 1214 struct ifnet *ifp = sc->sc_ifp; 1215 struct ieee80211com *ic = ifp->if_l2com; 1216 struct ath_hal *ah = sc->sc_ah; 1217 HAL_STATUS status; 1218 1219 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1220 __func__, ifp->if_flags); 1221 1222 /* 1223 * Must reset the chip before we reload the 1224 * keycache as we were powered down on suspend. 1225 */ 1226 ath_hal_reset(ah, sc->sc_opmode, 1227 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 1228 AH_FALSE, &status); 1229 ath_reset_keycache(sc); 1230 if (sc->sc_resume_up) { 1231 if (ic->ic_opmode == IEEE80211_M_STA) { 1232 ath_init(sc); 1233 /* 1234 * Program the beacon registers using the last rx'd 1235 * beacon frame and enable sync on the next beacon 1236 * we see. This should handle the case where we 1237 * wakeup and find the same AP and also the case where 1238 * we wakeup and need to roam. For the latter we 1239 * should get bmiss events that trigger a roam. 1240 */ 1241 ath_beacon_config(sc, NULL); 1242 sc->sc_syncbeacon = 1; 1243 } else 1244 ieee80211_resume_all(ic); 1245 } 1246 if (sc->sc_softled) { 1247 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 1248 HAL_GPIO_MUX_MAC_NETWORK_LED); 1249 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 1250 } 1251 } 1252 1253 void 1254 ath_shutdown(struct ath_softc *sc) 1255 { 1256 struct ifnet *ifp = sc->sc_ifp; 1257 1258 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1259 __func__, ifp->if_flags); 1260 1261 ath_stop(ifp); 1262 /* NB: no point powering down chip as we're about to reboot */ 1263 } 1264 1265 /* 1266 * Interrupt handler. Most of the actual processing is deferred. 1267 */ 1268 void 1269 ath_intr(void *arg) 1270 { 1271 struct ath_softc *sc = arg; 1272 struct ifnet *ifp = sc->sc_ifp; 1273 struct ath_hal *ah = sc->sc_ah; 1274 HAL_INT status; 1275 1276 if (sc->sc_invalid) { 1277 /* 1278 * The hardware is not ready/present, don't touch anything. 1279 * Note this can happen early on if the IRQ is shared. 1280 */ 1281 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 1282 return; 1283 } 1284 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 1285 return; 1286 if ((ifp->if_flags & IFF_UP) == 0 || 1287 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1288 HAL_INT status; 1289 1290 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1291 __func__, ifp->if_flags); 1292 ath_hal_getisr(ah, &status); /* clear ISR */ 1293 ath_hal_intrset(ah, 0); /* disable further intr's */ 1294 return; 1295 } 1296 /* 1297 * Figure out the reason(s) for the interrupt. Note 1298 * that the hal returns a pseudo-ISR that may include 1299 * bits we haven't explicitly enabled so we mask the 1300 * value to insure we only process bits we requested. 1301 */ 1302 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 1303 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 1304 status &= sc->sc_imask; /* discard unasked for bits */ 1305 if (status & HAL_INT_FATAL) { 1306 sc->sc_stats.ast_hardware++; 1307 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1308 ath_fatal_proc(sc, 0); 1309 } else { 1310 if (status & HAL_INT_SWBA) { 1311 /* 1312 * Software beacon alert--time to send a beacon. 1313 * Handle beacon transmission directly; deferring 1314 * this is too slow to meet timing constraints 1315 * under load. 1316 */ 1317 #ifdef IEEE80211_SUPPORT_TDMA 1318 if (sc->sc_tdma) { 1319 if (sc->sc_tdmaswba == 0) { 1320 struct ieee80211com *ic = ifp->if_l2com; 1321 struct ieee80211vap *vap = 1322 TAILQ_FIRST(&ic->ic_vaps); 1323 ath_tdma_beacon_send(sc, vap); 1324 sc->sc_tdmaswba = 1325 vap->iv_tdma->tdma_bintval; 1326 } else 1327 sc->sc_tdmaswba--; 1328 } else 1329 #endif 1330 { 1331 ath_beacon_proc(sc, 0); 1332 #ifdef IEEE80211_SUPPORT_SUPERG 1333 /* 1334 * Schedule the rx taskq in case there's no 1335 * traffic so any frames held on the staging 1336 * queue are aged and potentially flushed. 1337 */ 1338 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1339 #endif 1340 } 1341 } 1342 if (status & HAL_INT_RXEOL) { 1343 /* 1344 * NB: the hardware should re-read the link when 1345 * RXE bit is written, but it doesn't work at 1346 * least on older hardware revs. 1347 */ 1348 sc->sc_stats.ast_rxeol++; 1349 sc->sc_rxlink = NULL; 1350 } 1351 if (status & HAL_INT_TXURN) { 1352 sc->sc_stats.ast_txurn++; 1353 /* bump tx trigger level */ 1354 ath_hal_updatetxtriglevel(ah, AH_TRUE); 1355 } 1356 if (status & HAL_INT_RX) 1357 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1358 if (status & HAL_INT_TX) 1359 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 1360 if (status & HAL_INT_BMISS) { 1361 sc->sc_stats.ast_bmiss++; 1362 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 1363 } 1364 if (status & HAL_INT_MIB) { 1365 sc->sc_stats.ast_mib++; 1366 /* 1367 * Disable interrupts until we service the MIB 1368 * interrupt; otherwise it will continue to fire. 1369 */ 1370 ath_hal_intrset(ah, 0); 1371 /* 1372 * Let the hal handle the event. We assume it will 1373 * clear whatever condition caused the interrupt. 1374 */ 1375 ath_hal_mibevent(ah, &sc->sc_halstats); 1376 ath_hal_intrset(ah, sc->sc_imask); 1377 } 1378 if (status & HAL_INT_RXORN) { 1379 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 1380 sc->sc_stats.ast_rxorn++; 1381 } 1382 } 1383 } 1384 1385 static void 1386 ath_fatal_proc(void *arg, int pending) 1387 { 1388 struct ath_softc *sc = arg; 1389 struct ifnet *ifp = sc->sc_ifp; 1390 u_int32_t *state; 1391 u_int32_t len; 1392 void *sp; 1393 1394 if_printf(ifp, "hardware error; resetting\n"); 1395 /* 1396 * Fatal errors are unrecoverable. Typically these 1397 * are caused by DMA errors. Collect h/w state from 1398 * the hal so we can diagnose what's going on. 1399 */ 1400 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 1401 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 1402 state = sp; 1403 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 1404 state[0], state[1] , state[2], state[3], 1405 state[4], state[5]); 1406 } 1407 ath_reset(ifp); 1408 } 1409 1410 static void 1411 ath_bmiss_vap(struct ieee80211vap *vap) 1412 { 1413 /* 1414 * Workaround phantom bmiss interrupts by sanity-checking 1415 * the time of our last rx'd frame. If it is within the 1416 * beacon miss interval then ignore the interrupt. If it's 1417 * truly a bmiss we'll get another interrupt soon and that'll 1418 * be dispatched up for processing. Note this applies only 1419 * for h/w beacon miss events. 1420 */ 1421 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 1422 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1423 struct ath_softc *sc = ifp->if_softc; 1424 u_int64_t lastrx = sc->sc_lastrx; 1425 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 1426 u_int bmisstimeout = 1427 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 1428 1429 DPRINTF(sc, ATH_DEBUG_BEACON, 1430 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 1431 __func__, (unsigned long long) tsf, 1432 (unsigned long long)(tsf - lastrx), 1433 (unsigned long long) lastrx, bmisstimeout); 1434 1435 if (tsf - lastrx <= bmisstimeout) { 1436 sc->sc_stats.ast_bmiss_phantom++; 1437 return; 1438 } 1439 } 1440 ATH_VAP(vap)->av_bmiss(vap); 1441 } 1442 1443 static int 1444 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 1445 { 1446 uint32_t rsize; 1447 void *sp; 1448 1449 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize)) 1450 return 0; 1451 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 1452 *hangs = *(uint32_t *)sp; 1453 return 1; 1454 } 1455 1456 static void 1457 ath_bmiss_proc(void *arg, int pending) 1458 { 1459 struct ath_softc *sc = arg; 1460 struct ifnet *ifp = sc->sc_ifp; 1461 uint32_t hangs; 1462 1463 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 1464 1465 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 1466 if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs); 1467 ath_reset(ifp); 1468 } else 1469 ieee80211_beacon_miss(ifp->if_l2com); 1470 } 1471 1472 /* 1473 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 1474 * calcs together with WME. If necessary disable the crypto 1475 * hardware and mark the 802.11 state so keys will be setup 1476 * with the MIC work done in software. 1477 */ 1478 static void 1479 ath_settkipmic(struct ath_softc *sc) 1480 { 1481 struct ifnet *ifp = sc->sc_ifp; 1482 struct ieee80211com *ic = ifp->if_l2com; 1483 1484 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 1485 if (ic->ic_flags & IEEE80211_F_WME) { 1486 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 1487 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 1488 } else { 1489 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 1490 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 1491 } 1492 } 1493 } 1494 1495 static void 1496 ath_init(void *arg) 1497 { 1498 struct ath_softc *sc = (struct ath_softc *) arg; 1499 struct ifnet *ifp = sc->sc_ifp; 1500 struct ieee80211com *ic = ifp->if_l2com; 1501 struct ath_hal *ah = sc->sc_ah; 1502 HAL_STATUS status; 1503 1504 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1505 __func__, ifp->if_flags); 1506 1507 ATH_LOCK(sc); 1508 /* 1509 * Stop anything previously setup. This is safe 1510 * whether this is the first time through or not. 1511 */ 1512 ath_stop_locked(ifp); 1513 1514 /* 1515 * The basic interface to setting the hardware in a good 1516 * state is ``reset''. On return the hardware is known to 1517 * be powered up and with interrupts disabled. This must 1518 * be followed by initialization of the appropriate bits 1519 * and then setup of the interrupt mask. 1520 */ 1521 ath_settkipmic(sc); 1522 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) { 1523 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1524 status); 1525 ATH_UNLOCK(sc); 1526 return; 1527 } 1528 ath_chan_change(sc, ic->ic_curchan); 1529 1530 /* 1531 * Likewise this is set during reset so update 1532 * state cached in the driver. 1533 */ 1534 sc->sc_diversity = ath_hal_getdiversity(ah); 1535 sc->sc_lastlongcal = 0; 1536 sc->sc_resetcal = 1; 1537 sc->sc_lastcalreset = 0; 1538 sc->sc_lastani = 0; 1539 sc->sc_lastshortcal = 0; 1540 sc->sc_doresetcal = AH_FALSE; 1541 1542 /* 1543 * Setup the hardware after reset: the key cache 1544 * is filled as needed and the receive engine is 1545 * set going. Frame transmit is handled entirely 1546 * in the frame output path; there's nothing to do 1547 * here except setup the interrupt mask. 1548 */ 1549 if (ath_startrecv(sc) != 0) { 1550 if_printf(ifp, "unable to start recv logic\n"); 1551 ATH_UNLOCK(sc); 1552 return; 1553 } 1554 1555 /* 1556 * Enable interrupts. 1557 */ 1558 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1559 | HAL_INT_RXEOL | HAL_INT_RXORN 1560 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1561 /* 1562 * Enable MIB interrupts when there are hardware phy counters. 1563 * Note we only do this (at the moment) for station mode. 1564 */ 1565 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1566 sc->sc_imask |= HAL_INT_MIB; 1567 1568 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1569 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc); 1570 ath_hal_intrset(ah, sc->sc_imask); 1571 1572 ATH_UNLOCK(sc); 1573 1574 #ifdef ATH_TX99_DIAG 1575 if (sc->sc_tx99 != NULL) 1576 sc->sc_tx99->start(sc->sc_tx99); 1577 else 1578 #endif 1579 ieee80211_start_all(ic); /* start all vap's */ 1580 } 1581 1582 static void 1583 ath_stop_locked(struct ifnet *ifp) 1584 { 1585 struct ath_softc *sc = ifp->if_softc; 1586 struct ath_hal *ah = sc->sc_ah; 1587 1588 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1589 __func__, sc->sc_invalid, ifp->if_flags); 1590 1591 ATH_LOCK_ASSERT(sc); 1592 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1593 /* 1594 * Shutdown the hardware and driver: 1595 * reset 802.11 state machine 1596 * turn off timers 1597 * disable interrupts 1598 * turn off the radio 1599 * clear transmit machinery 1600 * clear receive machinery 1601 * drain and release tx queues 1602 * reclaim beacon resources 1603 * power down hardware 1604 * 1605 * Note that some of this work is not possible if the 1606 * hardware is gone (invalid). 1607 */ 1608 #ifdef ATH_TX99_DIAG 1609 if (sc->sc_tx99 != NULL) 1610 sc->sc_tx99->stop(sc->sc_tx99); 1611 #endif 1612 callout_stop(&sc->sc_wd_ch); 1613 sc->sc_wd_timer = 0; 1614 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1615 if (!sc->sc_invalid) { 1616 if (sc->sc_softled) { 1617 callout_stop(&sc->sc_ledtimer); 1618 ath_hal_gpioset(ah, sc->sc_ledpin, 1619 !sc->sc_ledon); 1620 sc->sc_blinking = 0; 1621 } 1622 ath_hal_intrset(ah, 0); 1623 } 1624 ath_draintxq(sc); 1625 if (!sc->sc_invalid) { 1626 ath_stoprecv(sc); 1627 ath_hal_phydisable(ah); 1628 } else 1629 sc->sc_rxlink = NULL; 1630 ath_beacon_free(sc); /* XXX not needed */ 1631 } 1632 } 1633 1634 static void 1635 ath_stop(struct ifnet *ifp) 1636 { 1637 struct ath_softc *sc = ifp->if_softc; 1638 1639 ATH_LOCK(sc); 1640 ath_stop_locked(ifp); 1641 ATH_UNLOCK(sc); 1642 } 1643 1644 /* 1645 * Reset the hardware w/o losing operational state. This is 1646 * basically a more efficient way of doing ath_stop, ath_init, 1647 * followed by state transitions to the current 802.11 1648 * operational state. Used to recover from various errors and 1649 * to reset or reload hardware state. 1650 */ 1651 int 1652 ath_reset(struct ifnet *ifp) 1653 { 1654 struct ath_softc *sc = ifp->if_softc; 1655 struct ieee80211com *ic = ifp->if_l2com; 1656 struct ath_hal *ah = sc->sc_ah; 1657 HAL_STATUS status; 1658 1659 ath_hal_intrset(ah, 0); /* disable interrupts */ 1660 ath_draintxq(sc); /* stop xmit side */ 1661 ath_stoprecv(sc); /* stop recv side */ 1662 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1663 /* NB: indicate channel change so we do a full reset */ 1664 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status)) 1665 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1666 __func__, status); 1667 sc->sc_diversity = ath_hal_getdiversity(ah); 1668 if (ath_startrecv(sc) != 0) /* restart recv */ 1669 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1670 /* 1671 * We may be doing a reset in response to an ioctl 1672 * that changes the channel so update any state that 1673 * might change as a result. 1674 */ 1675 ath_chan_change(sc, ic->ic_curchan); 1676 if (sc->sc_beacons) { /* restart beacons */ 1677 #ifdef IEEE80211_SUPPORT_TDMA 1678 if (sc->sc_tdma) 1679 ath_tdma_config(sc, NULL); 1680 else 1681 #endif 1682 ath_beacon_config(sc, NULL); 1683 } 1684 ath_hal_intrset(ah, sc->sc_imask); 1685 1686 ath_start(ifp); /* restart xmit */ 1687 return 0; 1688 } 1689 1690 static int 1691 ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 1692 { 1693 struct ieee80211com *ic = vap->iv_ic; 1694 struct ifnet *ifp = ic->ic_ifp; 1695 struct ath_softc *sc = ifp->if_softc; 1696 struct ath_hal *ah = sc->sc_ah; 1697 1698 switch (cmd) { 1699 case IEEE80211_IOC_TXPOWER: 1700 /* 1701 * If per-packet TPC is enabled, then we have nothing 1702 * to do; otherwise we need to force the global limit. 1703 * All this can happen directly; no need to reset. 1704 */ 1705 if (!ath_hal_gettpc(ah)) 1706 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 1707 return 0; 1708 } 1709 return ath_reset(ifp); 1710 } 1711 1712 struct ath_buf * 1713 _ath_getbuf_locked(struct ath_softc *sc) 1714 { 1715 struct ath_buf *bf; 1716 1717 ATH_TXBUF_LOCK_ASSERT(sc); 1718 1719 bf = STAILQ_FIRST(&sc->sc_txbuf); 1720 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) 1721 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1722 else 1723 bf = NULL; 1724 if (bf == NULL) { 1725 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 1726 STAILQ_FIRST(&sc->sc_txbuf) == NULL ? 1727 "out of xmit buffers" : "xmit buffer busy"); 1728 } 1729 return bf; 1730 } 1731 1732 struct ath_buf * 1733 ath_getbuf(struct ath_softc *sc) 1734 { 1735 struct ath_buf *bf; 1736 1737 ATH_TXBUF_LOCK(sc); 1738 bf = _ath_getbuf_locked(sc); 1739 if (bf == NULL) { 1740 struct ifnet *ifp = sc->sc_ifp; 1741 1742 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 1743 sc->sc_stats.ast_tx_qstop++; 1744 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1745 } 1746 ATH_TXBUF_UNLOCK(sc); 1747 return bf; 1748 } 1749 1750 static void 1751 ath_start(struct ifnet *ifp) 1752 { 1753 struct ath_softc *sc = ifp->if_softc; 1754 struct ieee80211_node *ni; 1755 struct ath_buf *bf; 1756 struct mbuf *m, *next; 1757 ath_bufhead frags; 1758 1759 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 1760 return; 1761 for (;;) { 1762 /* 1763 * Grab a TX buffer and associated resources. 1764 */ 1765 bf = ath_getbuf(sc); 1766 if (bf == NULL) 1767 break; 1768 1769 IFQ_DEQUEUE(&ifp->if_snd, m); 1770 if (m == NULL) { 1771 ATH_TXBUF_LOCK(sc); 1772 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1773 ATH_TXBUF_UNLOCK(sc); 1774 break; 1775 } 1776 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1777 /* 1778 * Check for fragmentation. If this frame 1779 * has been broken up verify we have enough 1780 * buffers to send all the fragments so all 1781 * go out or none... 1782 */ 1783 STAILQ_INIT(&frags); 1784 if ((m->m_flags & M_FRAG) && 1785 !ath_txfrag_setup(sc, &frags, m, ni)) { 1786 DPRINTF(sc, ATH_DEBUG_XMIT, 1787 "%s: out of txfrag buffers\n", __func__); 1788 sc->sc_stats.ast_tx_nofrag++; 1789 ifp->if_oerrors++; 1790 ath_freetx(m); 1791 goto bad; 1792 } 1793 ifp->if_opackets++; 1794 nextfrag: 1795 /* 1796 * Pass the frame to the h/w for transmission. 1797 * Fragmented frames have each frag chained together 1798 * with m_nextpkt. We know there are sufficient ath_buf's 1799 * to send all the frags because of work done by 1800 * ath_txfrag_setup. We leave m_nextpkt set while 1801 * calling ath_tx_start so it can use it to extend the 1802 * the tx duration to cover the subsequent frag and 1803 * so it can reclaim all the mbufs in case of an error; 1804 * ath_tx_start clears m_nextpkt once it commits to 1805 * handing the frame to the hardware. 1806 */ 1807 next = m->m_nextpkt; 1808 if (ath_tx_start(sc, ni, bf, m)) { 1809 bad: 1810 ifp->if_oerrors++; 1811 reclaim: 1812 bf->bf_m = NULL; 1813 bf->bf_node = NULL; 1814 ATH_TXBUF_LOCK(sc); 1815 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1816 ath_txfrag_cleanup(sc, &frags, ni); 1817 ATH_TXBUF_UNLOCK(sc); 1818 if (ni != NULL) 1819 ieee80211_free_node(ni); 1820 continue; 1821 } 1822 if (next != NULL) { 1823 /* 1824 * Beware of state changing between frags. 1825 * XXX check sta power-save state? 1826 */ 1827 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 1828 DPRINTF(sc, ATH_DEBUG_XMIT, 1829 "%s: flush fragmented packet, state %s\n", 1830 __func__, 1831 ieee80211_state_name[ni->ni_vap->iv_state]); 1832 ath_freetx(next); 1833 goto reclaim; 1834 } 1835 m = next; 1836 bf = STAILQ_FIRST(&frags); 1837 KASSERT(bf != NULL, ("no buf for txfrag")); 1838 STAILQ_REMOVE_HEAD(&frags, bf_list); 1839 goto nextfrag; 1840 } 1841 1842 sc->sc_wd_timer = 5; 1843 } 1844 } 1845 1846 static int 1847 ath_media_change(struct ifnet *ifp) 1848 { 1849 int error = ieee80211_media_change(ifp); 1850 /* NB: only the fixed rate can change and that doesn't need a reset */ 1851 return (error == ENETRESET ? 0 : error); 1852 } 1853 1854 #ifdef ATH_DEBUG 1855 static void 1856 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix, 1857 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1858 { 1859 static const char *ciphers[] = { 1860 "WEP", 1861 "AES-OCB", 1862 "AES-CCM", 1863 "CKIP", 1864 "TKIP", 1865 "CLR", 1866 }; 1867 int i, n; 1868 1869 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1870 for (i = 0, n = hk->kv_len; i < n; i++) 1871 printf("%02x", hk->kv_val[i]); 1872 printf(" mac %s", ether_sprintf(mac)); 1873 if (hk->kv_type == HAL_CIPHER_TKIP) { 1874 printf(" %s ", sc->sc_splitmic ? "mic" : "rxmic"); 1875 for (i = 0; i < sizeof(hk->kv_mic); i++) 1876 printf("%02x", hk->kv_mic[i]); 1877 if (!sc->sc_splitmic) { 1878 printf(" txmic "); 1879 for (i = 0; i < sizeof(hk->kv_txmic); i++) 1880 printf("%02x", hk->kv_txmic[i]); 1881 } 1882 } 1883 printf("\n"); 1884 } 1885 #endif 1886 1887 /* 1888 * Set a TKIP key into the hardware. This handles the 1889 * potential distribution of key state to multiple key 1890 * cache slots for TKIP. 1891 */ 1892 static int 1893 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1894 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1895 { 1896 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1897 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1898 struct ath_hal *ah = sc->sc_ah; 1899 1900 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1901 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1902 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1903 if (sc->sc_splitmic) { 1904 /* 1905 * TX key goes at first index, RX key at the rx index. 1906 * The hal handles the MIC keys at index+64. 1907 */ 1908 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1909 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1910 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1911 return 0; 1912 1913 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1914 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1915 /* XXX delete tx key on failure? */ 1916 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1917 } else { 1918 /* 1919 * Room for both TX+RX MIC keys in one key cache 1920 * slot, just set key at the first index; the hal 1921 * will handle the rest. 1922 */ 1923 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1924 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1925 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1926 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1927 } 1928 } else if (k->wk_flags & IEEE80211_KEY_XMIT) { 1929 if (sc->sc_splitmic) { 1930 /* 1931 * NB: must pass MIC key in expected location when 1932 * the keycache only holds one MIC key per entry. 1933 */ 1934 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic)); 1935 } else 1936 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1937 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1938 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1939 } else if (k->wk_flags & IEEE80211_KEY_RECV) { 1940 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1941 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1942 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1943 } 1944 return 0; 1945 #undef IEEE80211_KEY_XR 1946 } 1947 1948 /* 1949 * Set a net80211 key into the hardware. This handles the 1950 * potential distribution of key state to multiple key 1951 * cache slots for TKIP with hardware MIC support. 1952 */ 1953 static int 1954 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1955 struct ieee80211_node *bss) 1956 { 1957 #define N(a) (sizeof(a)/sizeof(a[0])) 1958 static const u_int8_t ciphermap[] = { 1959 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1960 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1961 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1962 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1963 (u_int8_t) -1, /* 4 is not allocated */ 1964 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1965 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1966 }; 1967 struct ath_hal *ah = sc->sc_ah; 1968 const struct ieee80211_cipher *cip = k->wk_cipher; 1969 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1970 const u_int8_t *mac; 1971 HAL_KEYVAL hk; 1972 1973 memset(&hk, 0, sizeof(hk)); 1974 /* 1975 * Software crypto uses a "clear key" so non-crypto 1976 * state kept in the key cache are maintained and 1977 * so that rx frames have an entry to match. 1978 */ 1979 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1980 KASSERT(cip->ic_cipher < N(ciphermap), 1981 ("invalid cipher type %u", cip->ic_cipher)); 1982 hk.kv_type = ciphermap[cip->ic_cipher]; 1983 hk.kv_len = k->wk_keylen; 1984 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1985 } else 1986 hk.kv_type = HAL_CIPHER_CLR; 1987 1988 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1989 /* 1990 * Group keys on hardware that supports multicast frame 1991 * key search use a MAC that is the sender's address with 1992 * the multicast bit set instead of the app-specified address. 1993 */ 1994 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1995 gmac[0] |= 0x01; 1996 mac = gmac; 1997 } else 1998 mac = k->wk_macaddr; 1999 2000 if (hk.kv_type == HAL_CIPHER_TKIP && 2001 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2002 return ath_keyset_tkip(sc, k, &hk, mac); 2003 } else { 2004 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 2005 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 2006 } 2007 #undef N 2008 } 2009 2010 /* 2011 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2012 * each key, one for decrypt/encrypt and the other for the MIC. 2013 */ 2014 static u_int16_t 2015 key_alloc_2pair(struct ath_softc *sc, 2016 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2017 { 2018 #define N(a) (sizeof(a)/sizeof(a[0])) 2019 u_int i, keyix; 2020 2021 KASSERT(sc->sc_splitmic, ("key cache !split")); 2022 /* XXX could optimize */ 2023 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2024 u_int8_t b = sc->sc_keymap[i]; 2025 if (b != 0xff) { 2026 /* 2027 * One or more slots in this byte are free. 2028 */ 2029 keyix = i*NBBY; 2030 while (b & 1) { 2031 again: 2032 keyix++; 2033 b >>= 1; 2034 } 2035 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 2036 if (isset(sc->sc_keymap, keyix+32) || 2037 isset(sc->sc_keymap, keyix+64) || 2038 isset(sc->sc_keymap, keyix+32+64)) { 2039 /* full pair unavailable */ 2040 /* XXX statistic */ 2041 if (keyix == (i+1)*NBBY) { 2042 /* no slots were appropriate, advance */ 2043 continue; 2044 } 2045 goto again; 2046 } 2047 setbit(sc->sc_keymap, keyix); 2048 setbit(sc->sc_keymap, keyix+64); 2049 setbit(sc->sc_keymap, keyix+32); 2050 setbit(sc->sc_keymap, keyix+32+64); 2051 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2052 "%s: key pair %u,%u %u,%u\n", 2053 __func__, keyix, keyix+64, 2054 keyix+32, keyix+32+64); 2055 *txkeyix = keyix; 2056 *rxkeyix = keyix+32; 2057 return 1; 2058 } 2059 } 2060 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2061 return 0; 2062 #undef N 2063 } 2064 2065 /* 2066 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2067 * each key, one for decrypt/encrypt and the other for the MIC. 2068 */ 2069 static u_int16_t 2070 key_alloc_pair(struct ath_softc *sc, 2071 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2072 { 2073 #define N(a) (sizeof(a)/sizeof(a[0])) 2074 u_int i, keyix; 2075 2076 KASSERT(!sc->sc_splitmic, ("key cache split")); 2077 /* XXX could optimize */ 2078 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2079 u_int8_t b = sc->sc_keymap[i]; 2080 if (b != 0xff) { 2081 /* 2082 * One or more slots in this byte are free. 2083 */ 2084 keyix = i*NBBY; 2085 while (b & 1) { 2086 again: 2087 keyix++; 2088 b >>= 1; 2089 } 2090 if (isset(sc->sc_keymap, keyix+64)) { 2091 /* full pair unavailable */ 2092 /* XXX statistic */ 2093 if (keyix == (i+1)*NBBY) { 2094 /* no slots were appropriate, advance */ 2095 continue; 2096 } 2097 goto again; 2098 } 2099 setbit(sc->sc_keymap, keyix); 2100 setbit(sc->sc_keymap, keyix+64); 2101 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2102 "%s: key pair %u,%u\n", 2103 __func__, keyix, keyix+64); 2104 *txkeyix = *rxkeyix = keyix; 2105 return 1; 2106 } 2107 } 2108 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2109 return 0; 2110 #undef N 2111 } 2112 2113 /* 2114 * Allocate a single key cache slot. 2115 */ 2116 static int 2117 key_alloc_single(struct ath_softc *sc, 2118 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2119 { 2120 #define N(a) (sizeof(a)/sizeof(a[0])) 2121 u_int i, keyix; 2122 2123 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 2124 for (i = 0; i < N(sc->sc_keymap); i++) { 2125 u_int8_t b = sc->sc_keymap[i]; 2126 if (b != 0xff) { 2127 /* 2128 * One or more slots are free. 2129 */ 2130 keyix = i*NBBY; 2131 while (b & 1) 2132 keyix++, b >>= 1; 2133 setbit(sc->sc_keymap, keyix); 2134 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 2135 __func__, keyix); 2136 *txkeyix = *rxkeyix = keyix; 2137 return 1; 2138 } 2139 } 2140 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 2141 return 0; 2142 #undef N 2143 } 2144 2145 /* 2146 * Allocate one or more key cache slots for a uniacst key. The 2147 * key itself is needed only to identify the cipher. For hardware 2148 * TKIP with split cipher+MIC keys we allocate two key cache slot 2149 * pairs so that we can setup separate TX and RX MIC keys. Note 2150 * that the MIC key for a TKIP key at slot i is assumed by the 2151 * hardware to be at slot i+64. This limits TKIP keys to the first 2152 * 64 entries. 2153 */ 2154 static int 2155 ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2156 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2157 { 2158 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2159 2160 /* 2161 * Group key allocation must be handled specially for 2162 * parts that do not support multicast key cache search 2163 * functionality. For those parts the key id must match 2164 * the h/w key index so lookups find the right key. On 2165 * parts w/ the key search facility we install the sender's 2166 * mac address (with the high bit set) and let the hardware 2167 * find the key w/o using the key id. This is preferred as 2168 * it permits us to support multiple users for adhoc and/or 2169 * multi-station operation. 2170 */ 2171 if (k->wk_keyix != IEEE80211_KEYIX_NONE) { 2172 /* 2173 * Only global keys should have key index assigned. 2174 */ 2175 if (!(&vap->iv_nw_keys[0] <= k && 2176 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2177 /* should not happen */ 2178 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2179 "%s: bogus group key\n", __func__); 2180 return 0; 2181 } 2182 if (vap->iv_opmode != IEEE80211_M_HOSTAP || 2183 !(k->wk_flags & IEEE80211_KEY_GROUP) || 2184 !sc->sc_mcastkey) { 2185 /* 2186 * XXX we pre-allocate the global keys so 2187 * have no way to check if they've already 2188 * been allocated. 2189 */ 2190 *keyix = *rxkeyix = k - vap->iv_nw_keys; 2191 return 1; 2192 } 2193 /* 2194 * Group key and device supports multicast key search. 2195 */ 2196 k->wk_keyix = IEEE80211_KEYIX_NONE; 2197 } 2198 2199 /* 2200 * We allocate two pair for TKIP when using the h/w to do 2201 * the MIC. For everything else, including software crypto, 2202 * we allocate a single entry. Note that s/w crypto requires 2203 * a pass-through slot on the 5211 and 5212. The 5210 does 2204 * not support pass-through cache entries and we map all 2205 * those requests to slot 0. 2206 */ 2207 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2208 return key_alloc_single(sc, keyix, rxkeyix); 2209 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 2210 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2211 if (sc->sc_splitmic) 2212 return key_alloc_2pair(sc, keyix, rxkeyix); 2213 else 2214 return key_alloc_pair(sc, keyix, rxkeyix); 2215 } else { 2216 return key_alloc_single(sc, keyix, rxkeyix); 2217 } 2218 } 2219 2220 /* 2221 * Delete an entry in the key cache allocated by ath_key_alloc. 2222 */ 2223 static int 2224 ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2225 { 2226 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2227 struct ath_hal *ah = sc->sc_ah; 2228 const struct ieee80211_cipher *cip = k->wk_cipher; 2229 u_int keyix = k->wk_keyix; 2230 2231 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 2232 2233 ath_hal_keyreset(ah, keyix); 2234 /* 2235 * Handle split tx/rx keying required for TKIP with h/w MIC. 2236 */ 2237 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2238 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 2239 ath_hal_keyreset(ah, keyix+32); /* RX key */ 2240 if (keyix >= IEEE80211_WEP_NKID) { 2241 /* 2242 * Don't touch keymap entries for global keys so 2243 * they are never considered for dynamic allocation. 2244 */ 2245 clrbit(sc->sc_keymap, keyix); 2246 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2247 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2248 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 2249 if (sc->sc_splitmic) { 2250 /* +32 for RX key, +32+64 for RX key MIC */ 2251 clrbit(sc->sc_keymap, keyix+32); 2252 clrbit(sc->sc_keymap, keyix+32+64); 2253 } 2254 } 2255 } 2256 return 1; 2257 } 2258 2259 /* 2260 * Set the key cache contents for the specified key. Key cache 2261 * slot(s) must already have been allocated by ath_key_alloc. 2262 */ 2263 static int 2264 ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k, 2265 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2266 { 2267 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2268 2269 return ath_keyset(sc, k, vap->iv_bss); 2270 } 2271 2272 /* 2273 * Block/unblock tx+rx processing while a key change is done. 2274 * We assume the caller serializes key management operations 2275 * so we only need to worry about synchronization with other 2276 * uses that originate in the driver. 2277 */ 2278 static void 2279 ath_key_update_begin(struct ieee80211vap *vap) 2280 { 2281 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2282 struct ath_softc *sc = ifp->if_softc; 2283 2284 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2285 taskqueue_block(sc->sc_tq); 2286 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 2287 } 2288 2289 static void 2290 ath_key_update_end(struct ieee80211vap *vap) 2291 { 2292 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2293 struct ath_softc *sc = ifp->if_softc; 2294 2295 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2296 IF_UNLOCK(&ifp->if_snd); 2297 taskqueue_unblock(sc->sc_tq); 2298 } 2299 2300 /* 2301 * Calculate the receive filter according to the 2302 * operating mode and state: 2303 * 2304 * o always accept unicast, broadcast, and multicast traffic 2305 * o accept PHY error frames when hardware doesn't have MIB support 2306 * to count and we need them for ANI (sta mode only until recently) 2307 * and we are not scanning (ANI is disabled) 2308 * NB: older hal's add rx filter bits out of sight and we need to 2309 * blindly preserve them 2310 * o probe request frames are accepted only when operating in 2311 * hostap, adhoc, mesh, or monitor modes 2312 * o enable promiscuous mode 2313 * - when in monitor mode 2314 * - if interface marked PROMISC (assumes bridge setting is filtered) 2315 * o accept beacons: 2316 * - when operating in station mode for collecting rssi data when 2317 * the station is otherwise quiet, or 2318 * - when operating in adhoc mode so the 802.11 layer creates 2319 * node table entries for peers, 2320 * - when scanning 2321 * - when doing s/w beacon miss (e.g. for ap+sta) 2322 * - when operating in ap mode in 11g to detect overlapping bss that 2323 * require protection 2324 * - when operating in mesh mode to detect neighbors 2325 * o accept control frames: 2326 * - when in monitor mode 2327 * XXX HT protection for 11n 2328 */ 2329 static u_int32_t 2330 ath_calcrxfilter(struct ath_softc *sc) 2331 { 2332 struct ifnet *ifp = sc->sc_ifp; 2333 struct ieee80211com *ic = ifp->if_l2com; 2334 u_int32_t rfilt; 2335 2336 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2337 if (!sc->sc_needmib && !sc->sc_scanning) 2338 rfilt |= HAL_RX_FILTER_PHYERR; 2339 if (ic->ic_opmode != IEEE80211_M_STA) 2340 rfilt |= HAL_RX_FILTER_PROBEREQ; 2341 /* XXX ic->ic_monvaps != 0? */ 2342 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 2343 rfilt |= HAL_RX_FILTER_PROM; 2344 if (ic->ic_opmode == IEEE80211_M_STA || 2345 ic->ic_opmode == IEEE80211_M_IBSS || 2346 sc->sc_swbmiss || sc->sc_scanning) 2347 rfilt |= HAL_RX_FILTER_BEACON; 2348 /* 2349 * NB: We don't recalculate the rx filter when 2350 * ic_protmode changes; otherwise we could do 2351 * this only when ic_protmode != NONE. 2352 */ 2353 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 2354 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 2355 rfilt |= HAL_RX_FILTER_BEACON; 2356 if (sc->sc_nmeshvaps) { 2357 rfilt |= HAL_RX_FILTER_BEACON; 2358 if (sc->sc_hasbmatch) 2359 rfilt |= HAL_RX_FILTER_BSSID; 2360 else 2361 rfilt |= HAL_RX_FILTER_PROM; 2362 } 2363 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2364 rfilt |= HAL_RX_FILTER_CONTROL; 2365 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 2366 rfilt |= HAL_RX_FILTER_COMPBAR; 2367 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 2368 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 2369 return rfilt; 2370 } 2371 2372 static void 2373 ath_update_promisc(struct ifnet *ifp) 2374 { 2375 struct ath_softc *sc = ifp->if_softc; 2376 u_int32_t rfilt; 2377 2378 /* configure rx filter */ 2379 rfilt = ath_calcrxfilter(sc); 2380 ath_hal_setrxfilter(sc->sc_ah, rfilt); 2381 2382 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 2383 } 2384 2385 static void 2386 ath_update_mcast(struct ifnet *ifp) 2387 { 2388 struct ath_softc *sc = ifp->if_softc; 2389 u_int32_t mfilt[2]; 2390 2391 /* calculate and install multicast filter */ 2392 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2393 struct ifmultiaddr *ifma; 2394 /* 2395 * Merge multicast addresses to form the hardware filter. 2396 */ 2397 mfilt[0] = mfilt[1] = 0; 2398 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */ 2399 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2400 caddr_t dl; 2401 u_int32_t val; 2402 u_int8_t pos; 2403 2404 /* calculate XOR of eight 6bit values */ 2405 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2406 val = LE_READ_4(dl + 0); 2407 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2408 val = LE_READ_4(dl + 3); 2409 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2410 pos &= 0x3f; 2411 mfilt[pos / 32] |= (1 << (pos % 32)); 2412 } 2413 if_maddr_runlock(ifp); 2414 } else 2415 mfilt[0] = mfilt[1] = ~0; 2416 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 2417 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 2418 __func__, mfilt[0], mfilt[1]); 2419 } 2420 2421 static void 2422 ath_mode_init(struct ath_softc *sc) 2423 { 2424 struct ifnet *ifp = sc->sc_ifp; 2425 struct ath_hal *ah = sc->sc_ah; 2426 u_int32_t rfilt; 2427 2428 /* configure rx filter */ 2429 rfilt = ath_calcrxfilter(sc); 2430 ath_hal_setrxfilter(ah, rfilt); 2431 2432 /* configure operational mode */ 2433 ath_hal_setopmode(ah); 2434 2435 /* handle any link-level address change */ 2436 ath_hal_setmac(ah, IF_LLADDR(ifp)); 2437 2438 /* calculate and install multicast filter */ 2439 ath_update_mcast(ifp); 2440 } 2441 2442 /* 2443 * Set the slot time based on the current setting. 2444 */ 2445 static void 2446 ath_setslottime(struct ath_softc *sc) 2447 { 2448 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2449 struct ath_hal *ah = sc->sc_ah; 2450 u_int usec; 2451 2452 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2453 usec = 13; 2454 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2455 usec = 21; 2456 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2457 /* honor short/long slot time only in 11g */ 2458 /* XXX shouldn't honor on pure g or turbo g channel */ 2459 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2460 usec = HAL_SLOT_TIME_9; 2461 else 2462 usec = HAL_SLOT_TIME_20; 2463 } else 2464 usec = HAL_SLOT_TIME_9; 2465 2466 DPRINTF(sc, ATH_DEBUG_RESET, 2467 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2468 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2469 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2470 2471 ath_hal_setslottime(ah, usec); 2472 sc->sc_updateslot = OK; 2473 } 2474 2475 /* 2476 * Callback from the 802.11 layer to update the 2477 * slot time based on the current setting. 2478 */ 2479 static void 2480 ath_updateslot(struct ifnet *ifp) 2481 { 2482 struct ath_softc *sc = ifp->if_softc; 2483 struct ieee80211com *ic = ifp->if_l2com; 2484 2485 /* 2486 * When not coordinating the BSS, change the hardware 2487 * immediately. For other operation we defer the change 2488 * until beacon updates have propagated to the stations. 2489 */ 2490 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2491 ic->ic_opmode == IEEE80211_M_MBSS) 2492 sc->sc_updateslot = UPDATE; 2493 else 2494 ath_setslottime(sc); 2495 } 2496 2497 /* 2498 * Setup a h/w transmit queue for beacons. 2499 */ 2500 static int 2501 ath_beaconq_setup(struct ath_hal *ah) 2502 { 2503 HAL_TXQ_INFO qi; 2504 2505 memset(&qi, 0, sizeof(qi)); 2506 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2507 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2508 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2509 /* NB: for dynamic turbo, don't enable any other interrupts */ 2510 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2511 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2512 } 2513 2514 /* 2515 * Setup the transmit queue parameters for the beacon queue. 2516 */ 2517 static int 2518 ath_beaconq_config(struct ath_softc *sc) 2519 { 2520 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2521 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2522 struct ath_hal *ah = sc->sc_ah; 2523 HAL_TXQ_INFO qi; 2524 2525 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2526 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2527 ic->ic_opmode == IEEE80211_M_MBSS) { 2528 /* 2529 * Always burst out beacon and CAB traffic. 2530 */ 2531 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2532 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2533 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2534 } else { 2535 struct wmeParams *wmep = 2536 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2537 /* 2538 * Adhoc mode; important thing is to use 2x cwmin. 2539 */ 2540 qi.tqi_aifs = wmep->wmep_aifsn; 2541 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2542 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2543 } 2544 2545 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2546 device_printf(sc->sc_dev, "unable to update parameters for " 2547 "beacon hardware queue!\n"); 2548 return 0; 2549 } else { 2550 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2551 return 1; 2552 } 2553 #undef ATH_EXPONENT_TO_VALUE 2554 } 2555 2556 /* 2557 * Allocate and setup an initial beacon frame. 2558 */ 2559 static int 2560 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2561 { 2562 struct ieee80211vap *vap = ni->ni_vap; 2563 struct ath_vap *avp = ATH_VAP(vap); 2564 struct ath_buf *bf; 2565 struct mbuf *m; 2566 int error; 2567 2568 bf = avp->av_bcbuf; 2569 if (bf->bf_m != NULL) { 2570 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2571 m_freem(bf->bf_m); 2572 bf->bf_m = NULL; 2573 } 2574 if (bf->bf_node != NULL) { 2575 ieee80211_free_node(bf->bf_node); 2576 bf->bf_node = NULL; 2577 } 2578 2579 /* 2580 * NB: the beacon data buffer must be 32-bit aligned; 2581 * we assume the mbuf routines will return us something 2582 * with this alignment (perhaps should assert). 2583 */ 2584 m = ieee80211_beacon_alloc(ni, &avp->av_boff); 2585 if (m == NULL) { 2586 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 2587 sc->sc_stats.ast_be_nombuf++; 2588 return ENOMEM; 2589 } 2590 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2591 bf->bf_segs, &bf->bf_nseg, 2592 BUS_DMA_NOWAIT); 2593 if (error != 0) { 2594 device_printf(sc->sc_dev, 2595 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 2596 __func__, error); 2597 m_freem(m); 2598 return error; 2599 } 2600 2601 /* 2602 * Calculate a TSF adjustment factor required for staggered 2603 * beacons. Note that we assume the format of the beacon 2604 * frame leaves the tstamp field immediately following the 2605 * header. 2606 */ 2607 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 2608 uint64_t tsfadjust; 2609 struct ieee80211_frame *wh; 2610 2611 /* 2612 * The beacon interval is in TU's; the TSF is in usecs. 2613 * We figure out how many TU's to add to align the timestamp 2614 * then convert to TSF units and handle byte swapping before 2615 * inserting it in the frame. The hardware will then add this 2616 * each time a beacon frame is sent. Note that we align vap's 2617 * 1..N and leave vap 0 untouched. This means vap 0 has a 2618 * timestamp in one beacon interval while the others get a 2619 * timstamp aligned to the next interval. 2620 */ 2621 tsfadjust = ni->ni_intval * 2622 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 2623 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 2624 2625 DPRINTF(sc, ATH_DEBUG_BEACON, 2626 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 2627 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 2628 avp->av_bslot, ni->ni_intval, 2629 (long long unsigned) le64toh(tsfadjust)); 2630 2631 wh = mtod(m, struct ieee80211_frame *); 2632 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 2633 } 2634 bf->bf_m = m; 2635 bf->bf_node = ieee80211_ref_node(ni); 2636 2637 return 0; 2638 } 2639 2640 /* 2641 * Setup the beacon frame for transmit. 2642 */ 2643 static void 2644 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2645 { 2646 #define USE_SHPREAMBLE(_ic) \ 2647 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2648 == IEEE80211_F_SHPREAMBLE) 2649 struct ieee80211_node *ni = bf->bf_node; 2650 struct ieee80211com *ic = ni->ni_ic; 2651 struct mbuf *m = bf->bf_m; 2652 struct ath_hal *ah = sc->sc_ah; 2653 struct ath_desc *ds; 2654 int flags, antenna; 2655 const HAL_RATE_TABLE *rt; 2656 u_int8_t rix, rate; 2657 2658 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 2659 __func__, m, m->m_len); 2660 2661 /* setup descriptors */ 2662 ds = bf->bf_desc; 2663 2664 flags = HAL_TXDESC_NOACK; 2665 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2666 ds->ds_link = bf->bf_daddr; /* self-linked */ 2667 flags |= HAL_TXDESC_VEOL; 2668 /* 2669 * Let hardware handle antenna switching. 2670 */ 2671 antenna = sc->sc_txantenna; 2672 } else { 2673 ds->ds_link = 0; 2674 /* 2675 * Switch antenna every 4 beacons. 2676 * XXX assumes two antenna 2677 */ 2678 if (sc->sc_txantenna != 0) 2679 antenna = sc->sc_txantenna; 2680 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 2681 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 2682 else 2683 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2684 } 2685 2686 KASSERT(bf->bf_nseg == 1, 2687 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2688 ds->ds_data = bf->bf_segs[0].ds_addr; 2689 /* 2690 * Calculate rate code. 2691 * XXX everything at min xmit rate 2692 */ 2693 rix = 0; 2694 rt = sc->sc_currates; 2695 rate = rt->info[rix].rateCode; 2696 if (USE_SHPREAMBLE(ic)) 2697 rate |= rt->info[rix].shortPreamble; 2698 ath_hal_setuptxdesc(ah, ds 2699 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2700 , sizeof(struct ieee80211_frame)/* header length */ 2701 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2702 , ni->ni_txpower /* txpower XXX */ 2703 , rate, 1 /* series 0 rate/tries */ 2704 , HAL_TXKEYIX_INVALID /* no encryption */ 2705 , antenna /* antenna mode */ 2706 , flags /* no ack, veol for beacons */ 2707 , 0 /* rts/cts rate */ 2708 , 0 /* rts/cts duration */ 2709 ); 2710 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2711 ath_hal_filltxdesc(ah, ds 2712 , roundup(m->m_len, 4) /* buffer length */ 2713 , AH_TRUE /* first segment */ 2714 , AH_TRUE /* last segment */ 2715 , ds /* first descriptor */ 2716 ); 2717 #if 0 2718 ath_desc_swap(ds); 2719 #endif 2720 #undef USE_SHPREAMBLE 2721 } 2722 2723 static void 2724 ath_beacon_update(struct ieee80211vap *vap, int item) 2725 { 2726 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 2727 2728 setbit(bo->bo_flags, item); 2729 } 2730 2731 /* 2732 * Append the contents of src to dst; both queues 2733 * are assumed to be locked. 2734 */ 2735 static void 2736 ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 2737 { 2738 STAILQ_CONCAT(&dst->axq_q, &src->axq_q); 2739 dst->axq_link = src->axq_link; 2740 src->axq_link = NULL; 2741 dst->axq_depth += src->axq_depth; 2742 src->axq_depth = 0; 2743 } 2744 2745 /* 2746 * Transmit a beacon frame at SWBA. Dynamic updates to the 2747 * frame contents are done as needed and the slot time is 2748 * also adjusted based on current state. 2749 */ 2750 static void 2751 ath_beacon_proc(void *arg, int pending) 2752 { 2753 struct ath_softc *sc = arg; 2754 struct ath_hal *ah = sc->sc_ah; 2755 struct ieee80211vap *vap; 2756 struct ath_buf *bf; 2757 int slot, otherant; 2758 uint32_t bfaddr; 2759 2760 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2761 __func__, pending); 2762 /* 2763 * Check if the previous beacon has gone out. If 2764 * not don't try to post another, skip this period 2765 * and wait for the next. Missed beacons indicate 2766 * a problem and should not occur. If we miss too 2767 * many consecutive beacons reset the device. 2768 */ 2769 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2770 sc->sc_bmisscount++; 2771 sc->sc_stats.ast_be_missed++; 2772 DPRINTF(sc, ATH_DEBUG_BEACON, 2773 "%s: missed %u consecutive beacons\n", 2774 __func__, sc->sc_bmisscount); 2775 if (sc->sc_bmisscount >= ath_bstuck_threshold) 2776 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 2777 return; 2778 } 2779 if (sc->sc_bmisscount != 0) { 2780 DPRINTF(sc, ATH_DEBUG_BEACON, 2781 "%s: resume beacon xmit after %u misses\n", 2782 __func__, sc->sc_bmisscount); 2783 sc->sc_bmisscount = 0; 2784 } 2785 2786 if (sc->sc_stagbeacons) { /* staggered beacons */ 2787 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2788 uint32_t tsftu; 2789 2790 tsftu = ath_hal_gettsf32(ah) >> 10; 2791 /* XXX lintval */ 2792 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 2793 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 2794 bfaddr = 0; 2795 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 2796 bf = ath_beacon_generate(sc, vap); 2797 if (bf != NULL) 2798 bfaddr = bf->bf_daddr; 2799 } 2800 } else { /* burst'd beacons */ 2801 uint32_t *bflink = &bfaddr; 2802 2803 for (slot = 0; slot < ATH_BCBUF; slot++) { 2804 vap = sc->sc_bslot[slot]; 2805 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 2806 bf = ath_beacon_generate(sc, vap); 2807 if (bf != NULL) { 2808 *bflink = bf->bf_daddr; 2809 bflink = &bf->bf_desc->ds_link; 2810 } 2811 } 2812 } 2813 *bflink = 0; /* terminate list */ 2814 } 2815 2816 /* 2817 * Handle slot time change when a non-ERP station joins/leaves 2818 * an 11g network. The 802.11 layer notifies us via callback, 2819 * we mark updateslot, then wait one beacon before effecting 2820 * the change. This gives associated stations at least one 2821 * beacon interval to note the state change. 2822 */ 2823 /* XXX locking */ 2824 if (sc->sc_updateslot == UPDATE) { 2825 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2826 sc->sc_slotupdate = slot; 2827 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 2828 ath_setslottime(sc); /* commit change to h/w */ 2829 2830 /* 2831 * Check recent per-antenna transmit statistics and flip 2832 * the default antenna if noticeably more frames went out 2833 * on the non-default antenna. 2834 * XXX assumes 2 anntenae 2835 */ 2836 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 2837 otherant = sc->sc_defant & 1 ? 2 : 1; 2838 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2839 ath_setdefantenna(sc, otherant); 2840 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2841 } 2842 2843 if (bfaddr != 0) { 2844 /* 2845 * Stop any current dma and put the new frame on the queue. 2846 * This should never fail since we check above that no frames 2847 * are still pending on the queue. 2848 */ 2849 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2850 DPRINTF(sc, ATH_DEBUG_ANY, 2851 "%s: beacon queue %u did not stop?\n", 2852 __func__, sc->sc_bhalq); 2853 } 2854 /* NB: cabq traffic should already be queued and primed */ 2855 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 2856 ath_hal_txstart(ah, sc->sc_bhalq); 2857 2858 sc->sc_stats.ast_be_xmit++; 2859 } 2860 } 2861 2862 static struct ath_buf * 2863 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 2864 { 2865 struct ath_vap *avp = ATH_VAP(vap); 2866 struct ath_txq *cabq = sc->sc_cabq; 2867 struct ath_buf *bf; 2868 struct mbuf *m; 2869 int nmcastq, error; 2870 2871 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 2872 ("not running, state %d", vap->iv_state)); 2873 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 2874 2875 /* 2876 * Update dynamic beacon contents. If this returns 2877 * non-zero then we need to remap the memory because 2878 * the beacon frame changed size (probably because 2879 * of the TIM bitmap). 2880 */ 2881 bf = avp->av_bcbuf; 2882 m = bf->bf_m; 2883 nmcastq = avp->av_mcastq.axq_depth; 2884 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 2885 /* XXX too conservative? */ 2886 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2887 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2888 bf->bf_segs, &bf->bf_nseg, 2889 BUS_DMA_NOWAIT); 2890 if (error != 0) { 2891 if_printf(vap->iv_ifp, 2892 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 2893 __func__, error); 2894 return NULL; 2895 } 2896 } 2897 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 2898 DPRINTF(sc, ATH_DEBUG_BEACON, 2899 "%s: cabq did not drain, mcastq %u cabq %u\n", 2900 __func__, nmcastq, cabq->axq_depth); 2901 sc->sc_stats.ast_cabq_busy++; 2902 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 2903 /* 2904 * CABQ traffic from a previous vap is still pending. 2905 * We must drain the q before this beacon frame goes 2906 * out as otherwise this vap's stations will get cab 2907 * frames from a different vap. 2908 * XXX could be slow causing us to miss DBA 2909 */ 2910 ath_tx_draintxq(sc, cabq); 2911 } 2912 } 2913 ath_beacon_setup(sc, bf); 2914 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 2915 2916 /* 2917 * Enable the CAB queue before the beacon queue to 2918 * insure cab frames are triggered by this beacon. 2919 */ 2920 if (avp->av_boff.bo_tim[4] & 1) { 2921 struct ath_hal *ah = sc->sc_ah; 2922 2923 /* NB: only at DTIM */ 2924 ATH_TXQ_LOCK(cabq); 2925 ATH_TXQ_LOCK(&avp->av_mcastq); 2926 if (nmcastq) { 2927 struct ath_buf *bfm; 2928 2929 /* 2930 * Move frames from the s/w mcast q to the h/w cab q. 2931 * XXX MORE_DATA bit 2932 */ 2933 bfm = STAILQ_FIRST(&avp->av_mcastq.axq_q); 2934 if (cabq->axq_link != NULL) { 2935 *cabq->axq_link = bfm->bf_daddr; 2936 } else 2937 ath_hal_puttxbuf(ah, cabq->axq_qnum, 2938 bfm->bf_daddr); 2939 ath_txqmove(cabq, &avp->av_mcastq); 2940 2941 sc->sc_stats.ast_cabq_xmit += nmcastq; 2942 } 2943 /* NB: gated by beacon so safe to start here */ 2944 ath_hal_txstart(ah, cabq->axq_qnum); 2945 ATH_TXQ_UNLOCK(cabq); 2946 ATH_TXQ_UNLOCK(&avp->av_mcastq); 2947 } 2948 return bf; 2949 } 2950 2951 static void 2952 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 2953 { 2954 struct ath_vap *avp = ATH_VAP(vap); 2955 struct ath_hal *ah = sc->sc_ah; 2956 struct ath_buf *bf; 2957 struct mbuf *m; 2958 int error; 2959 2960 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 2961 2962 /* 2963 * Update dynamic beacon contents. If this returns 2964 * non-zero then we need to remap the memory because 2965 * the beacon frame changed size (probably because 2966 * of the TIM bitmap). 2967 */ 2968 bf = avp->av_bcbuf; 2969 m = bf->bf_m; 2970 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 2971 /* XXX too conservative? */ 2972 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2973 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2974 bf->bf_segs, &bf->bf_nseg, 2975 BUS_DMA_NOWAIT); 2976 if (error != 0) { 2977 if_printf(vap->iv_ifp, 2978 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 2979 __func__, error); 2980 return; 2981 } 2982 } 2983 ath_beacon_setup(sc, bf); 2984 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 2985 2986 /* NB: caller is known to have already stopped tx dma */ 2987 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2988 ath_hal_txstart(ah, sc->sc_bhalq); 2989 } 2990 2991 /* 2992 * Reset the hardware after detecting beacons have stopped. 2993 */ 2994 static void 2995 ath_bstuck_proc(void *arg, int pending) 2996 { 2997 struct ath_softc *sc = arg; 2998 struct ifnet *ifp = sc->sc_ifp; 2999 3000 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 3001 sc->sc_bmisscount); 3002 sc->sc_stats.ast_bstuck++; 3003 ath_reset(ifp); 3004 } 3005 3006 /* 3007 * Reclaim beacon resources and return buffer to the pool. 3008 */ 3009 static void 3010 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 3011 { 3012 3013 if (bf->bf_m != NULL) { 3014 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3015 m_freem(bf->bf_m); 3016 bf->bf_m = NULL; 3017 } 3018 if (bf->bf_node != NULL) { 3019 ieee80211_free_node(bf->bf_node); 3020 bf->bf_node = NULL; 3021 } 3022 STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 3023 } 3024 3025 /* 3026 * Reclaim beacon resources. 3027 */ 3028 static void 3029 ath_beacon_free(struct ath_softc *sc) 3030 { 3031 struct ath_buf *bf; 3032 3033 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 3034 if (bf->bf_m != NULL) { 3035 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3036 m_freem(bf->bf_m); 3037 bf->bf_m = NULL; 3038 } 3039 if (bf->bf_node != NULL) { 3040 ieee80211_free_node(bf->bf_node); 3041 bf->bf_node = NULL; 3042 } 3043 } 3044 } 3045 3046 /* 3047 * Configure the beacon and sleep timers. 3048 * 3049 * When operating as an AP this resets the TSF and sets 3050 * up the hardware to notify us when we need to issue beacons. 3051 * 3052 * When operating in station mode this sets up the beacon 3053 * timers according to the timestamp of the last received 3054 * beacon and the current TSF, configures PCF and DTIM 3055 * handling, programs the sleep registers so the hardware 3056 * will wakeup in time to receive beacons, and configures 3057 * the beacon miss handling so we'll receive a BMISS 3058 * interrupt when we stop seeing beacons from the AP 3059 * we've associated with. 3060 */ 3061 static void 3062 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 3063 { 3064 #define TSF_TO_TU(_h,_l) \ 3065 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 3066 #define FUDGE 2 3067 struct ath_hal *ah = sc->sc_ah; 3068 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3069 struct ieee80211_node *ni; 3070 u_int32_t nexttbtt, intval, tsftu; 3071 u_int64_t tsf; 3072 3073 if (vap == NULL) 3074 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 3075 ni = vap->iv_bss; 3076 3077 /* extract tstamp from last beacon and convert to TU */ 3078 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 3079 LE_READ_4(ni->ni_tstamp.data)); 3080 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3081 ic->ic_opmode == IEEE80211_M_MBSS) { 3082 /* 3083 * For multi-bss ap/mesh support beacons are either staggered 3084 * evenly over N slots or burst together. For the former 3085 * arrange for the SWBA to be delivered for each slot. 3086 * Slots that are not occupied will generate nothing. 3087 */ 3088 /* NB: the beacon interval is kept internally in TU's */ 3089 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3090 if (sc->sc_stagbeacons) 3091 intval /= ATH_BCBUF; 3092 } else { 3093 /* NB: the beacon interval is kept internally in TU's */ 3094 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3095 } 3096 if (nexttbtt == 0) /* e.g. for ap mode */ 3097 nexttbtt = intval; 3098 else if (intval) /* NB: can be 0 for monitor mode */ 3099 nexttbtt = roundup(nexttbtt, intval); 3100 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 3101 __func__, nexttbtt, intval, ni->ni_intval); 3102 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 3103 HAL_BEACON_STATE bs; 3104 int dtimperiod, dtimcount; 3105 int cfpperiod, cfpcount; 3106 3107 /* 3108 * Setup dtim and cfp parameters according to 3109 * last beacon we received (which may be none). 3110 */ 3111 dtimperiod = ni->ni_dtim_period; 3112 if (dtimperiod <= 0) /* NB: 0 if not known */ 3113 dtimperiod = 1; 3114 dtimcount = ni->ni_dtim_count; 3115 if (dtimcount >= dtimperiod) /* NB: sanity check */ 3116 dtimcount = 0; /* XXX? */ 3117 cfpperiod = 1; /* NB: no PCF support yet */ 3118 cfpcount = 0; 3119 /* 3120 * Pull nexttbtt forward to reflect the current 3121 * TSF and calculate dtim+cfp state for the result. 3122 */ 3123 tsf = ath_hal_gettsf64(ah); 3124 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3125 do { 3126 nexttbtt += intval; 3127 if (--dtimcount < 0) { 3128 dtimcount = dtimperiod - 1; 3129 if (--cfpcount < 0) 3130 cfpcount = cfpperiod - 1; 3131 } 3132 } while (nexttbtt < tsftu); 3133 memset(&bs, 0, sizeof(bs)); 3134 bs.bs_intval = intval; 3135 bs.bs_nexttbtt = nexttbtt; 3136 bs.bs_dtimperiod = dtimperiod*intval; 3137 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 3138 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 3139 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 3140 bs.bs_cfpmaxduration = 0; 3141 #if 0 3142 /* 3143 * The 802.11 layer records the offset to the DTIM 3144 * bitmap while receiving beacons; use it here to 3145 * enable h/w detection of our AID being marked in 3146 * the bitmap vector (to indicate frames for us are 3147 * pending at the AP). 3148 * XXX do DTIM handling in s/w to WAR old h/w bugs 3149 * XXX enable based on h/w rev for newer chips 3150 */ 3151 bs.bs_timoffset = ni->ni_timoff; 3152 #endif 3153 /* 3154 * Calculate the number of consecutive beacons to miss 3155 * before taking a BMISS interrupt. 3156 * Note that we clamp the result to at most 10 beacons. 3157 */ 3158 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 3159 if (bs.bs_bmissthreshold > 10) 3160 bs.bs_bmissthreshold = 10; 3161 else if (bs.bs_bmissthreshold <= 0) 3162 bs.bs_bmissthreshold = 1; 3163 3164 /* 3165 * Calculate sleep duration. The configuration is 3166 * given in ms. We insure a multiple of the beacon 3167 * period is used. Also, if the sleep duration is 3168 * greater than the DTIM period then it makes senses 3169 * to make it a multiple of that. 3170 * 3171 * XXX fixed at 100ms 3172 */ 3173 bs.bs_sleepduration = 3174 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 3175 if (bs.bs_sleepduration > bs.bs_dtimperiod) 3176 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 3177 3178 DPRINTF(sc, ATH_DEBUG_BEACON, 3179 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 3180 , __func__ 3181 , tsf, tsftu 3182 , bs.bs_intval 3183 , bs.bs_nexttbtt 3184 , bs.bs_dtimperiod 3185 , bs.bs_nextdtim 3186 , bs.bs_bmissthreshold 3187 , bs.bs_sleepduration 3188 , bs.bs_cfpperiod 3189 , bs.bs_cfpmaxduration 3190 , bs.bs_cfpnext 3191 , bs.bs_timoffset 3192 ); 3193 ath_hal_intrset(ah, 0); 3194 ath_hal_beacontimers(ah, &bs); 3195 sc->sc_imask |= HAL_INT_BMISS; 3196 ath_hal_intrset(ah, sc->sc_imask); 3197 } else { 3198 ath_hal_intrset(ah, 0); 3199 if (nexttbtt == intval) 3200 intval |= HAL_BEACON_RESET_TSF; 3201 if (ic->ic_opmode == IEEE80211_M_IBSS) { 3202 /* 3203 * In IBSS mode enable the beacon timers but only 3204 * enable SWBA interrupts if we need to manually 3205 * prepare beacon frames. Otherwise we use a 3206 * self-linked tx descriptor and let the hardware 3207 * deal with things. 3208 */ 3209 intval |= HAL_BEACON_ENA; 3210 if (!sc->sc_hasveol) 3211 sc->sc_imask |= HAL_INT_SWBA; 3212 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 3213 /* 3214 * Pull nexttbtt forward to reflect 3215 * the current TSF. 3216 */ 3217 tsf = ath_hal_gettsf64(ah); 3218 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3219 do { 3220 nexttbtt += intval; 3221 } while (nexttbtt < tsftu); 3222 } 3223 ath_beaconq_config(sc); 3224 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3225 ic->ic_opmode == IEEE80211_M_MBSS) { 3226 /* 3227 * In AP/mesh mode we enable the beacon timers 3228 * and SWBA interrupts to prepare beacon frames. 3229 */ 3230 intval |= HAL_BEACON_ENA; 3231 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 3232 ath_beaconq_config(sc); 3233 } 3234 ath_hal_beaconinit(ah, nexttbtt, intval); 3235 sc->sc_bmisscount = 0; 3236 ath_hal_intrset(ah, sc->sc_imask); 3237 /* 3238 * When using a self-linked beacon descriptor in 3239 * ibss mode load it once here. 3240 */ 3241 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 3242 ath_beacon_start_adhoc(sc, vap); 3243 } 3244 sc->sc_syncbeacon = 0; 3245 #undef FUDGE 3246 #undef TSF_TO_TU 3247 } 3248 3249 static void 3250 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3251 { 3252 bus_addr_t *paddr = (bus_addr_t*) arg; 3253 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 3254 *paddr = segs->ds_addr; 3255 } 3256 3257 static int 3258 ath_descdma_setup(struct ath_softc *sc, 3259 struct ath_descdma *dd, ath_bufhead *head, 3260 const char *name, int nbuf, int ndesc) 3261 { 3262 #define DS2PHYS(_dd, _ds) \ 3263 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 3264 struct ifnet *ifp = sc->sc_ifp; 3265 struct ath_desc *ds; 3266 struct ath_buf *bf; 3267 int i, bsize, error; 3268 3269 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 3270 __func__, name, nbuf, ndesc); 3271 3272 dd->dd_name = name; 3273 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 3274 3275 /* 3276 * Setup DMA descriptor area. 3277 */ 3278 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 3279 PAGE_SIZE, 0, /* alignment, bounds */ 3280 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3281 BUS_SPACE_MAXADDR, /* highaddr */ 3282 NULL, NULL, /* filter, filterarg */ 3283 dd->dd_desc_len, /* maxsize */ 3284 1, /* nsegments */ 3285 dd->dd_desc_len, /* maxsegsize */ 3286 BUS_DMA_ALLOCNOW, /* flags */ 3287 NULL, /* lockfunc */ 3288 NULL, /* lockarg */ 3289 &dd->dd_dmat); 3290 if (error != 0) { 3291 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 3292 return error; 3293 } 3294 3295 /* allocate descriptors */ 3296 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 3297 if (error != 0) { 3298 if_printf(ifp, "unable to create dmamap for %s descriptors, " 3299 "error %u\n", dd->dd_name, error); 3300 goto fail0; 3301 } 3302 3303 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 3304 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 3305 &dd->dd_dmamap); 3306 if (error != 0) { 3307 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 3308 "error %u\n", nbuf * ndesc, dd->dd_name, error); 3309 goto fail1; 3310 } 3311 3312 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 3313 dd->dd_desc, dd->dd_desc_len, 3314 ath_load_cb, &dd->dd_desc_paddr, 3315 BUS_DMA_NOWAIT); 3316 if (error != 0) { 3317 if_printf(ifp, "unable to map %s descriptors, error %u\n", 3318 dd->dd_name, error); 3319 goto fail2; 3320 } 3321 3322 ds = dd->dd_desc; 3323 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 3324 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 3325 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 3326 3327 /* allocate rx buffers */ 3328 bsize = sizeof(struct ath_buf) * nbuf; 3329 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 3330 if (bf == NULL) { 3331 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 3332 dd->dd_name, bsize); 3333 goto fail3; 3334 } 3335 dd->dd_bufptr = bf; 3336 3337 STAILQ_INIT(head); 3338 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 3339 bf->bf_desc = ds; 3340 bf->bf_daddr = DS2PHYS(dd, ds); 3341 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3342 &bf->bf_dmamap); 3343 if (error != 0) { 3344 if_printf(ifp, "unable to create dmamap for %s " 3345 "buffer %u, error %u\n", dd->dd_name, i, error); 3346 ath_descdma_cleanup(sc, dd, head); 3347 return error; 3348 } 3349 STAILQ_INSERT_TAIL(head, bf, bf_list); 3350 } 3351 return 0; 3352 fail3: 3353 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3354 fail2: 3355 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3356 fail1: 3357 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3358 fail0: 3359 bus_dma_tag_destroy(dd->dd_dmat); 3360 memset(dd, 0, sizeof(*dd)); 3361 return error; 3362 #undef DS2PHYS 3363 } 3364 3365 static void 3366 ath_descdma_cleanup(struct ath_softc *sc, 3367 struct ath_descdma *dd, ath_bufhead *head) 3368 { 3369 struct ath_buf *bf; 3370 struct ieee80211_node *ni; 3371 3372 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3373 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3374 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3375 bus_dma_tag_destroy(dd->dd_dmat); 3376 3377 STAILQ_FOREACH(bf, head, bf_list) { 3378 if (bf->bf_m) { 3379 m_freem(bf->bf_m); 3380 bf->bf_m = NULL; 3381 } 3382 if (bf->bf_dmamap != NULL) { 3383 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 3384 bf->bf_dmamap = NULL; 3385 } 3386 ni = bf->bf_node; 3387 bf->bf_node = NULL; 3388 if (ni != NULL) { 3389 /* 3390 * Reclaim node reference. 3391 */ 3392 ieee80211_free_node(ni); 3393 } 3394 } 3395 3396 STAILQ_INIT(head); 3397 free(dd->dd_bufptr, M_ATHDEV); 3398 memset(dd, 0, sizeof(*dd)); 3399 } 3400 3401 static int 3402 ath_desc_alloc(struct ath_softc *sc) 3403 { 3404 int error; 3405 3406 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 3407 "rx", ath_rxbuf, 1); 3408 if (error != 0) 3409 return error; 3410 3411 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3412 "tx", ath_txbuf, ATH_TXDESC); 3413 if (error != 0) { 3414 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3415 return error; 3416 } 3417 3418 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3419 "beacon", ATH_BCBUF, 1); 3420 if (error != 0) { 3421 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3422 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3423 return error; 3424 } 3425 return 0; 3426 } 3427 3428 static void 3429 ath_desc_free(struct ath_softc *sc) 3430 { 3431 3432 if (sc->sc_bdma.dd_desc_len != 0) 3433 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3434 if (sc->sc_txdma.dd_desc_len != 0) 3435 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3436 if (sc->sc_rxdma.dd_desc_len != 0) 3437 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3438 } 3439 3440 static struct ieee80211_node * 3441 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3442 { 3443 struct ieee80211com *ic = vap->iv_ic; 3444 struct ath_softc *sc = ic->ic_ifp->if_softc; 3445 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3446 struct ath_node *an; 3447 3448 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 3449 if (an == NULL) { 3450 /* XXX stat+msg */ 3451 return NULL; 3452 } 3453 ath_rate_node_init(sc, an); 3454 3455 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 3456 return &an->an_node; 3457 } 3458 3459 static void 3460 ath_node_free(struct ieee80211_node *ni) 3461 { 3462 struct ieee80211com *ic = ni->ni_ic; 3463 struct ath_softc *sc = ic->ic_ifp->if_softc; 3464 3465 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 3466 3467 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3468 sc->sc_node_free(ni); 3469 } 3470 3471 static void 3472 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3473 { 3474 struct ieee80211com *ic = ni->ni_ic; 3475 struct ath_softc *sc = ic->ic_ifp->if_softc; 3476 struct ath_hal *ah = sc->sc_ah; 3477 3478 *rssi = ic->ic_node_getrssi(ni); 3479 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 3480 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 3481 else 3482 *noise = -95; /* nominally correct */ 3483 } 3484 3485 static int 3486 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 3487 { 3488 struct ath_hal *ah = sc->sc_ah; 3489 int error; 3490 struct mbuf *m; 3491 struct ath_desc *ds; 3492 3493 m = bf->bf_m; 3494 if (m == NULL) { 3495 /* 3496 * NB: by assigning a page to the rx dma buffer we 3497 * implicitly satisfy the Atheros requirement that 3498 * this buffer be cache-line-aligned and sized to be 3499 * multiple of the cache line size. Not doing this 3500 * causes weird stuff to happen (for the 5210 at least). 3501 */ 3502 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3503 if (m == NULL) { 3504 DPRINTF(sc, ATH_DEBUG_ANY, 3505 "%s: no mbuf/cluster\n", __func__); 3506 sc->sc_stats.ast_rx_nombuf++; 3507 return ENOMEM; 3508 } 3509 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 3510 3511 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 3512 bf->bf_dmamap, m, 3513 bf->bf_segs, &bf->bf_nseg, 3514 BUS_DMA_NOWAIT); 3515 if (error != 0) { 3516 DPRINTF(sc, ATH_DEBUG_ANY, 3517 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 3518 __func__, error); 3519 sc->sc_stats.ast_rx_busdma++; 3520 m_freem(m); 3521 return error; 3522 } 3523 KASSERT(bf->bf_nseg == 1, 3524 ("multi-segment packet; nseg %u", bf->bf_nseg)); 3525 bf->bf_m = m; 3526 } 3527 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 3528 3529 /* 3530 * Setup descriptors. For receive we always terminate 3531 * the descriptor list with a self-linked entry so we'll 3532 * not get overrun under high load (as can happen with a 3533 * 5212 when ANI processing enables PHY error frames). 3534 * 3535 * To insure the last descriptor is self-linked we create 3536 * each descriptor as self-linked and add it to the end. As 3537 * each additional descriptor is added the previous self-linked 3538 * entry is ``fixed'' naturally. This should be safe even 3539 * if DMA is happening. When processing RX interrupts we 3540 * never remove/process the last, self-linked, entry on the 3541 * descriptor list. This insures the hardware always has 3542 * someplace to write a new frame. 3543 */ 3544 ds = bf->bf_desc; 3545 ds->ds_link = bf->bf_daddr; /* link to self */ 3546 ds->ds_data = bf->bf_segs[0].ds_addr; 3547 ath_hal_setuprxdesc(ah, ds 3548 , m->m_len /* buffer size */ 3549 , 0 3550 ); 3551 3552 if (sc->sc_rxlink != NULL) 3553 *sc->sc_rxlink = bf->bf_daddr; 3554 sc->sc_rxlink = &ds->ds_link; 3555 return 0; 3556 } 3557 3558 /* 3559 * Extend 15-bit time stamp from rx descriptor to 3560 * a full 64-bit TSF using the specified TSF. 3561 */ 3562 static __inline u_int64_t 3563 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 3564 { 3565 if ((tsf & 0x7fff) < rstamp) 3566 tsf -= 0x8000; 3567 return ((tsf &~ 0x7fff) | rstamp); 3568 } 3569 3570 /* 3571 * Intercept management frames to collect beacon rssi data 3572 * and to do ibss merges. 3573 */ 3574 static void 3575 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 3576 int subtype, int rssi, int nf) 3577 { 3578 struct ieee80211vap *vap = ni->ni_vap; 3579 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 3580 3581 /* 3582 * Call up first so subsequent work can use information 3583 * potentially stored in the node (e.g. for ibss merge). 3584 */ 3585 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 3586 switch (subtype) { 3587 case IEEE80211_FC0_SUBTYPE_BEACON: 3588 /* update rssi statistics for use by the hal */ 3589 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 3590 if (sc->sc_syncbeacon && 3591 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 3592 /* 3593 * Resync beacon timers using the tsf of the beacon 3594 * frame we just received. 3595 */ 3596 ath_beacon_config(sc, vap); 3597 } 3598 /* fall thru... */ 3599 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3600 if (vap->iv_opmode == IEEE80211_M_IBSS && 3601 vap->iv_state == IEEE80211_S_RUN) { 3602 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 3603 uint64_t tsf = ath_extend_tsf(rstamp, 3604 ath_hal_gettsf64(sc->sc_ah)); 3605 /* 3606 * Handle ibss merge as needed; check the tsf on the 3607 * frame before attempting the merge. The 802.11 spec 3608 * says the station should change it's bssid to match 3609 * the oldest station with the same ssid, where oldest 3610 * is determined by the tsf. Note that hardware 3611 * reconfiguration happens through callback to 3612 * ath_newstate as the state machine will go from 3613 * RUN -> RUN when this happens. 3614 */ 3615 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 3616 DPRINTF(sc, ATH_DEBUG_STATE, 3617 "ibss merge, rstamp %u tsf %ju " 3618 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 3619 (uintmax_t)ni->ni_tstamp.tsf); 3620 (void) ieee80211_ibss_merge(ni); 3621 } 3622 } 3623 break; 3624 } 3625 } 3626 3627 /* 3628 * Set the default antenna. 3629 */ 3630 static void 3631 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3632 { 3633 struct ath_hal *ah = sc->sc_ah; 3634 3635 /* XXX block beacon interrupts */ 3636 ath_hal_setdefantenna(ah, antenna); 3637 if (sc->sc_defant != antenna) 3638 sc->sc_stats.ast_ant_defswitch++; 3639 sc->sc_defant = antenna; 3640 sc->sc_rxotherant = 0; 3641 } 3642 3643 static void 3644 ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 3645 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 3646 { 3647 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 3648 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 3649 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 3650 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 3651 struct ath_softc *sc = ifp->if_softc; 3652 const HAL_RATE_TABLE *rt; 3653 uint8_t rix; 3654 3655 rt = sc->sc_currates; 3656 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3657 rix = rt->rateCodeToIndex[rs->rs_rate]; 3658 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3659 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3660 #ifdef AH_SUPPORT_AR5416 3661 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 3662 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 3663 struct ieee80211com *ic = ifp->if_l2com; 3664 3665 if ((rs->rs_flags & HAL_RX_2040) == 0) 3666 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 3667 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 3668 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 3669 else 3670 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 3671 if ((rs->rs_flags & HAL_RX_GI) == 0) 3672 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 3673 } 3674 #endif 3675 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf)); 3676 if (rs->rs_status & HAL_RXERR_CRC) 3677 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3678 /* XXX propagate other error flags from descriptor */ 3679 sc->sc_rx_th.wr_antnoise = nf; 3680 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 3681 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 3682 #undef CHAN_HT 3683 #undef CHAN_HT20 3684 #undef CHAN_HT40U 3685 #undef CHAN_HT40D 3686 } 3687 3688 static void 3689 ath_handle_micerror(struct ieee80211com *ic, 3690 struct ieee80211_frame *wh, int keyix) 3691 { 3692 struct ieee80211_node *ni; 3693 3694 /* XXX recheck MIC to deal w/ chips that lie */ 3695 /* XXX discard MIC errors on !data frames */ 3696 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 3697 if (ni != NULL) { 3698 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 3699 ieee80211_free_node(ni); 3700 } 3701 } 3702 3703 static void 3704 ath_rx_proc(void *arg, int npending) 3705 { 3706 #define PA2DESC(_sc, _pa) \ 3707 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3708 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3709 struct ath_softc *sc = arg; 3710 struct ath_buf *bf; 3711 struct ifnet *ifp = sc->sc_ifp; 3712 struct ieee80211com *ic = ifp->if_l2com; 3713 struct ath_hal *ah = sc->sc_ah; 3714 struct ath_desc *ds; 3715 struct ath_rx_status *rs; 3716 struct mbuf *m; 3717 struct ieee80211_node *ni; 3718 int len, type, ngood; 3719 HAL_STATUS status; 3720 int16_t nf; 3721 u_int64_t tsf; 3722 3723 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3724 ngood = 0; 3725 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 3726 sc->sc_stats.ast_rx_noise = nf; 3727 tsf = ath_hal_gettsf64(ah); 3728 do { 3729 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3730 if (bf == NULL) { /* NB: shouldn't happen */ 3731 if_printf(ifp, "%s: no buffer!\n", __func__); 3732 break; 3733 } 3734 m = bf->bf_m; 3735 if (m == NULL) { /* NB: shouldn't happen */ 3736 /* 3737 * If mbuf allocation failed previously there 3738 * will be no mbuf; try again to re-populate it. 3739 */ 3740 /* XXX make debug msg */ 3741 if_printf(ifp, "%s: no mbuf!\n", __func__); 3742 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3743 goto rx_next; 3744 } 3745 ds = bf->bf_desc; 3746 if (ds->ds_link == bf->bf_daddr) { 3747 /* NB: never process the self-linked entry at the end */ 3748 break; 3749 } 3750 /* XXX sync descriptor memory */ 3751 /* 3752 * Must provide the virtual address of the current 3753 * descriptor, the physical address, and the virtual 3754 * address of the next descriptor in the h/w chain. 3755 * This allows the HAL to look ahead to see if the 3756 * hardware is done with a descriptor by checking the 3757 * done bit in the following descriptor and the address 3758 * of the current descriptor the DMA engine is working 3759 * on. All this is necessary because of our use of 3760 * a self-linked list to avoid rx overruns. 3761 */ 3762 rs = &bf->bf_status.ds_rxstat; 3763 status = ath_hal_rxprocdesc(ah, ds, 3764 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 3765 #ifdef ATH_DEBUG 3766 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3767 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 3768 #endif 3769 if (status == HAL_EINPROGRESS) 3770 break; 3771 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3772 3773 /* These aren't specifically errors */ 3774 if (rs->rs_flags & HAL_RX_GI) 3775 sc->sc_stats.ast_rx_halfgi++; 3776 if (rs->rs_flags & HAL_RX_2040) 3777 sc->sc_stats.ast_rx_2040++; 3778 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 3779 sc->sc_stats.ast_rx_pre_crc_err++; 3780 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 3781 sc->sc_stats.ast_rx_post_crc_err++; 3782 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 3783 sc->sc_stats.ast_rx_decrypt_busy_err++; 3784 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 3785 sc->sc_stats.ast_rx_hi_rx_chain++; 3786 3787 if (rs->rs_status != 0) { 3788 if (rs->rs_status & HAL_RXERR_CRC) 3789 sc->sc_stats.ast_rx_crcerr++; 3790 if (rs->rs_status & HAL_RXERR_FIFO) 3791 sc->sc_stats.ast_rx_fifoerr++; 3792 if (rs->rs_status & HAL_RXERR_PHY) { 3793 sc->sc_stats.ast_rx_phyerr++; 3794 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 3795 if (rs->rs_phyerr < 64) 3796 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 3797 goto rx_error; /* NB: don't count in ierrors */ 3798 } 3799 if (rs->rs_status & HAL_RXERR_DECRYPT) { 3800 /* 3801 * Decrypt error. If the error occurred 3802 * because there was no hardware key, then 3803 * let the frame through so the upper layers 3804 * can process it. This is necessary for 5210 3805 * parts which have no way to setup a ``clear'' 3806 * key cache entry. 3807 * 3808 * XXX do key cache faulting 3809 */ 3810 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 3811 goto rx_accept; 3812 sc->sc_stats.ast_rx_badcrypt++; 3813 } 3814 if (rs->rs_status & HAL_RXERR_MIC) { 3815 sc->sc_stats.ast_rx_badmic++; 3816 /* 3817 * Do minimal work required to hand off 3818 * the 802.11 header for notification. 3819 */ 3820 /* XXX frag's and qos frames */ 3821 len = rs->rs_datalen; 3822 if (len >= sizeof (struct ieee80211_frame)) { 3823 bus_dmamap_sync(sc->sc_dmat, 3824 bf->bf_dmamap, 3825 BUS_DMASYNC_POSTREAD); 3826 ath_handle_micerror(ic, 3827 mtod(m, struct ieee80211_frame *), 3828 sc->sc_splitmic ? 3829 rs->rs_keyix-32 : rs->rs_keyix); 3830 } 3831 } 3832 ifp->if_ierrors++; 3833 rx_error: 3834 /* 3835 * Cleanup any pending partial frame. 3836 */ 3837 if (sc->sc_rxpending != NULL) { 3838 m_freem(sc->sc_rxpending); 3839 sc->sc_rxpending = NULL; 3840 } 3841 /* 3842 * When a tap is present pass error frames 3843 * that have been requested. By default we 3844 * pass decrypt+mic errors but others may be 3845 * interesting (e.g. crc). 3846 */ 3847 if (ieee80211_radiotap_active(ic) && 3848 (rs->rs_status & sc->sc_monpass)) { 3849 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3850 BUS_DMASYNC_POSTREAD); 3851 /* NB: bpf needs the mbuf length setup */ 3852 len = rs->rs_datalen; 3853 m->m_pkthdr.len = m->m_len = len; 3854 ath_rx_tap(ifp, m, rs, tsf, nf); 3855 ieee80211_radiotap_rx_all(ic, m); 3856 } 3857 /* XXX pass MIC errors up for s/w reclaculation */ 3858 goto rx_next; 3859 } 3860 rx_accept: 3861 /* 3862 * Sync and unmap the frame. At this point we're 3863 * committed to passing the mbuf somewhere so clear 3864 * bf_m; this means a new mbuf must be allocated 3865 * when the rx descriptor is setup again to receive 3866 * another frame. 3867 */ 3868 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3869 BUS_DMASYNC_POSTREAD); 3870 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3871 bf->bf_m = NULL; 3872 3873 len = rs->rs_datalen; 3874 m->m_len = len; 3875 3876 if (rs->rs_more) { 3877 /* 3878 * Frame spans multiple descriptors; save 3879 * it for the next completed descriptor, it 3880 * will be used to construct a jumbogram. 3881 */ 3882 if (sc->sc_rxpending != NULL) { 3883 /* NB: max frame size is currently 2 clusters */ 3884 sc->sc_stats.ast_rx_toobig++; 3885 m_freem(sc->sc_rxpending); 3886 } 3887 m->m_pkthdr.rcvif = ifp; 3888 m->m_pkthdr.len = len; 3889 sc->sc_rxpending = m; 3890 goto rx_next; 3891 } else if (sc->sc_rxpending != NULL) { 3892 /* 3893 * This is the second part of a jumbogram, 3894 * chain it to the first mbuf, adjust the 3895 * frame length, and clear the rxpending state. 3896 */ 3897 sc->sc_rxpending->m_next = m; 3898 sc->sc_rxpending->m_pkthdr.len += len; 3899 m = sc->sc_rxpending; 3900 sc->sc_rxpending = NULL; 3901 } else { 3902 /* 3903 * Normal single-descriptor receive; setup 3904 * the rcvif and packet length. 3905 */ 3906 m->m_pkthdr.rcvif = ifp; 3907 m->m_pkthdr.len = len; 3908 } 3909 3910 ifp->if_ipackets++; 3911 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 3912 3913 /* 3914 * Populate the rx status block. When there are bpf 3915 * listeners we do the additional work to provide 3916 * complete status. Otherwise we fill in only the 3917 * material required by ieee80211_input. Note that 3918 * noise setting is filled in above. 3919 */ 3920 if (ieee80211_radiotap_active(ic)) 3921 ath_rx_tap(ifp, m, rs, tsf, nf); 3922 3923 /* 3924 * From this point on we assume the frame is at least 3925 * as large as ieee80211_frame_min; verify that. 3926 */ 3927 if (len < IEEE80211_MIN_LEN) { 3928 if (!ieee80211_radiotap_active(ic)) { 3929 DPRINTF(sc, ATH_DEBUG_RECV, 3930 "%s: short packet %d\n", __func__, len); 3931 sc->sc_stats.ast_rx_tooshort++; 3932 } else { 3933 /* NB: in particular this captures ack's */ 3934 ieee80211_radiotap_rx_all(ic, m); 3935 } 3936 m_freem(m); 3937 goto rx_next; 3938 } 3939 3940 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3941 const HAL_RATE_TABLE *rt = sc->sc_currates; 3942 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 3943 3944 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 3945 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 3946 } 3947 3948 m_adj(m, -IEEE80211_CRC_LEN); 3949 3950 /* 3951 * Locate the node for sender, track state, and then 3952 * pass the (referenced) node up to the 802.11 layer 3953 * for its use. 3954 */ 3955 ni = ieee80211_find_rxnode_withkey(ic, 3956 mtod(m, const struct ieee80211_frame_min *), 3957 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 3958 IEEE80211_KEYIX_NONE : rs->rs_keyix); 3959 sc->sc_lastrs = rs; 3960 /* tag AMPDU aggregates for reorder processing */ 3961 #if 0 3962 /* 3963 * Just make sure all frames are tagged for AMPDU reorder checking. 3964 * As there seems to be some situations where single frames aren't 3965 * matching a node but bump the seqno. This needs to be investigated. 3966 */ 3967 m->m_flags |= M_AMPDU; 3968 #endif 3969 3970 /* Keep statistics on the number of aggregate packets received */ 3971 if (rs->rs_isaggr) 3972 sc->sc_stats.ast_rx_agg++; 3973 3974 if (ni != NULL) { 3975 /* 3976 * Only punt packets for ampdu reorder processing for 11n nodes; 3977 * net80211 enforces that M_AMPDU is only set for 11n nodes. 3978 */ 3979 if (ni->ni_flags & IEEE80211_NODE_HT) 3980 m->m_flags |= M_AMPDU; 3981 3982 /* 3983 * Sending station is known, dispatch directly. 3984 */ 3985 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 3986 ieee80211_free_node(ni); 3987 /* 3988 * Arrange to update the last rx timestamp only for 3989 * frames from our ap when operating in station mode. 3990 * This assumes the rx key is always setup when 3991 * associated. 3992 */ 3993 if (ic->ic_opmode == IEEE80211_M_STA && 3994 rs->rs_keyix != HAL_RXKEYIX_INVALID) 3995 ngood++; 3996 } else { 3997 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 3998 } 3999 /* 4000 * Track rx rssi and do any rx antenna management. 4001 */ 4002 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 4003 if (sc->sc_diversity) { 4004 /* 4005 * When using fast diversity, change the default rx 4006 * antenna if diversity chooses the other antenna 3 4007 * times in a row. 4008 */ 4009 if (sc->sc_defant != rs->rs_antenna) { 4010 if (++sc->sc_rxotherant >= 3) 4011 ath_setdefantenna(sc, rs->rs_antenna); 4012 } else 4013 sc->sc_rxotherant = 0; 4014 } 4015 if (sc->sc_softled) { 4016 /* 4017 * Blink for any data frame. Otherwise do a 4018 * heartbeat-style blink when idle. The latter 4019 * is mainly for station mode where we depend on 4020 * periodic beacon frames to trigger the poll event. 4021 */ 4022 if (type == IEEE80211_FC0_TYPE_DATA) { 4023 const HAL_RATE_TABLE *rt = sc->sc_currates; 4024 ath_led_event(sc, 4025 rt->rateCodeToIndex[rs->rs_rate]); 4026 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 4027 ath_led_event(sc, 0); 4028 } 4029 rx_next: 4030 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 4031 } while (ath_rxbuf_init(sc, bf) == 0); 4032 4033 /* rx signal state monitoring */ 4034 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 4035 if (ngood) 4036 sc->sc_lastrx = tsf; 4037 4038 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 4039 #ifdef IEEE80211_SUPPORT_SUPERG 4040 ieee80211_ff_age_all(ic, 100); 4041 #endif 4042 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4043 ath_start(ifp); 4044 } 4045 #undef PA2DESC 4046 } 4047 4048 static void 4049 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 4050 { 4051 txq->axq_qnum = qnum; 4052 txq->axq_ac = 0; 4053 txq->axq_depth = 0; 4054 txq->axq_intrcnt = 0; 4055 txq->axq_link = NULL; 4056 STAILQ_INIT(&txq->axq_q); 4057 ATH_TXQ_LOCK_INIT(sc, txq); 4058 } 4059 4060 /* 4061 * Setup a h/w transmit queue. 4062 */ 4063 static struct ath_txq * 4064 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 4065 { 4066 #define N(a) (sizeof(a)/sizeof(a[0])) 4067 struct ath_hal *ah = sc->sc_ah; 4068 HAL_TXQ_INFO qi; 4069 int qnum; 4070 4071 memset(&qi, 0, sizeof(qi)); 4072 qi.tqi_subtype = subtype; 4073 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 4074 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 4075 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 4076 /* 4077 * Enable interrupts only for EOL and DESC conditions. 4078 * We mark tx descriptors to receive a DESC interrupt 4079 * when a tx queue gets deep; otherwise waiting for the 4080 * EOL to reap descriptors. Note that this is done to 4081 * reduce interrupt load and this only defers reaping 4082 * descriptors, never transmitting frames. Aside from 4083 * reducing interrupts this also permits more concurrency. 4084 * The only potential downside is if the tx queue backs 4085 * up in which case the top half of the kernel may backup 4086 * due to a lack of tx descriptors. 4087 */ 4088 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 4089 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 4090 if (qnum == -1) { 4091 /* 4092 * NB: don't print a message, this happens 4093 * normally on parts with too few tx queues 4094 */ 4095 return NULL; 4096 } 4097 if (qnum >= N(sc->sc_txq)) { 4098 device_printf(sc->sc_dev, 4099 "hal qnum %u out of range, max %zu!\n", 4100 qnum, N(sc->sc_txq)); 4101 ath_hal_releasetxqueue(ah, qnum); 4102 return NULL; 4103 } 4104 if (!ATH_TXQ_SETUP(sc, qnum)) { 4105 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 4106 sc->sc_txqsetup |= 1<<qnum; 4107 } 4108 return &sc->sc_txq[qnum]; 4109 #undef N 4110 } 4111 4112 /* 4113 * Setup a hardware data transmit queue for the specified 4114 * access control. The hal may not support all requested 4115 * queues in which case it will return a reference to a 4116 * previously setup queue. We record the mapping from ac's 4117 * to h/w queues for use by ath_tx_start and also track 4118 * the set of h/w queues being used to optimize work in the 4119 * transmit interrupt handler and related routines. 4120 */ 4121 static int 4122 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 4123 { 4124 #define N(a) (sizeof(a)/sizeof(a[0])) 4125 struct ath_txq *txq; 4126 4127 if (ac >= N(sc->sc_ac2q)) { 4128 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 4129 ac, N(sc->sc_ac2q)); 4130 return 0; 4131 } 4132 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 4133 if (txq != NULL) { 4134 txq->axq_ac = ac; 4135 sc->sc_ac2q[ac] = txq; 4136 return 1; 4137 } else 4138 return 0; 4139 #undef N 4140 } 4141 4142 /* 4143 * Update WME parameters for a transmit queue. 4144 */ 4145 static int 4146 ath_txq_update(struct ath_softc *sc, int ac) 4147 { 4148 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 4149 #define ATH_TXOP_TO_US(v) (v<<5) 4150 struct ifnet *ifp = sc->sc_ifp; 4151 struct ieee80211com *ic = ifp->if_l2com; 4152 struct ath_txq *txq = sc->sc_ac2q[ac]; 4153 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4154 struct ath_hal *ah = sc->sc_ah; 4155 HAL_TXQ_INFO qi; 4156 4157 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 4158 #ifdef IEEE80211_SUPPORT_TDMA 4159 if (sc->sc_tdma) { 4160 /* 4161 * AIFS is zero so there's no pre-transmit wait. The 4162 * burst time defines the slot duration and is configured 4163 * through net80211. The QCU is setup to not do post-xmit 4164 * back off, lockout all lower-priority QCU's, and fire 4165 * off the DMA beacon alert timer which is setup based 4166 * on the slot configuration. 4167 */ 4168 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4169 | HAL_TXQ_TXERRINT_ENABLE 4170 | HAL_TXQ_TXURNINT_ENABLE 4171 | HAL_TXQ_TXEOLINT_ENABLE 4172 | HAL_TXQ_DBA_GATED 4173 | HAL_TXQ_BACKOFF_DISABLE 4174 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 4175 ; 4176 qi.tqi_aifs = 0; 4177 /* XXX +dbaprep? */ 4178 qi.tqi_readyTime = sc->sc_tdmaslotlen; 4179 qi.tqi_burstTime = qi.tqi_readyTime; 4180 } else { 4181 #endif 4182 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4183 | HAL_TXQ_TXERRINT_ENABLE 4184 | HAL_TXQ_TXDESCINT_ENABLE 4185 | HAL_TXQ_TXURNINT_ENABLE 4186 ; 4187 qi.tqi_aifs = wmep->wmep_aifsn; 4188 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 4189 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 4190 qi.tqi_readyTime = 0; 4191 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 4192 #ifdef IEEE80211_SUPPORT_TDMA 4193 } 4194 #endif 4195 4196 DPRINTF(sc, ATH_DEBUG_RESET, 4197 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 4198 __func__, txq->axq_qnum, qi.tqi_qflags, 4199 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 4200 4201 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 4202 if_printf(ifp, "unable to update hardware queue " 4203 "parameters for %s traffic!\n", 4204 ieee80211_wme_acnames[ac]); 4205 return 0; 4206 } else { 4207 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 4208 return 1; 4209 } 4210 #undef ATH_TXOP_TO_US 4211 #undef ATH_EXPONENT_TO_VALUE 4212 } 4213 4214 /* 4215 * Callback from the 802.11 layer to update WME parameters. 4216 */ 4217 static int 4218 ath_wme_update(struct ieee80211com *ic) 4219 { 4220 struct ath_softc *sc = ic->ic_ifp->if_softc; 4221 4222 return !ath_txq_update(sc, WME_AC_BE) || 4223 !ath_txq_update(sc, WME_AC_BK) || 4224 !ath_txq_update(sc, WME_AC_VI) || 4225 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 4226 } 4227 4228 /* 4229 * Reclaim resources for a setup queue. 4230 */ 4231 static void 4232 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 4233 { 4234 4235 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 4236 ATH_TXQ_LOCK_DESTROY(txq); 4237 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 4238 } 4239 4240 /* 4241 * Reclaim all tx queue resources. 4242 */ 4243 static void 4244 ath_tx_cleanup(struct ath_softc *sc) 4245 { 4246 int i; 4247 4248 ATH_TXBUF_LOCK_DESTROY(sc); 4249 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4250 if (ATH_TXQ_SETUP(sc, i)) 4251 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 4252 } 4253 4254 /* 4255 * Return h/w rate index for an IEEE rate (w/o basic rate bit) 4256 * using the current rates in sc_rixmap. 4257 */ 4258 int 4259 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate) 4260 { 4261 int rix = sc->sc_rixmap[rate]; 4262 /* NB: return lowest rix for invalid rate */ 4263 return (rix == 0xff ? 0 : rix); 4264 } 4265 4266 /* 4267 * Process completed xmit descriptors from the specified queue. 4268 */ 4269 static int 4270 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4271 { 4272 struct ath_hal *ah = sc->sc_ah; 4273 struct ifnet *ifp = sc->sc_ifp; 4274 struct ieee80211com *ic = ifp->if_l2com; 4275 struct ath_buf *bf, *last; 4276 struct ath_desc *ds, *ds0; 4277 struct ath_tx_status *ts; 4278 struct ieee80211_node *ni; 4279 struct ath_node *an; 4280 int sr, lr, pri, nacked; 4281 HAL_STATUS status; 4282 4283 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4284 __func__, txq->axq_qnum, 4285 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4286 txq->axq_link); 4287 nacked = 0; 4288 for (;;) { 4289 ATH_TXQ_LOCK(txq); 4290 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4291 bf = STAILQ_FIRST(&txq->axq_q); 4292 if (bf == NULL) { 4293 ATH_TXQ_UNLOCK(txq); 4294 break; 4295 } 4296 ds0 = &bf->bf_desc[0]; 4297 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4298 ts = &bf->bf_status.ds_txstat; 4299 status = ath_hal_txprocdesc(ah, ds, ts); 4300 #ifdef ATH_DEBUG 4301 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4302 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 4303 status == HAL_OK); 4304 #endif 4305 if (status == HAL_EINPROGRESS) { 4306 ATH_TXQ_UNLOCK(txq); 4307 break; 4308 } 4309 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4310 #ifdef IEEE80211_SUPPORT_TDMA 4311 if (txq->axq_depth > 0) { 4312 /* 4313 * More frames follow. Mark the buffer busy 4314 * so it's not re-used while the hardware may 4315 * still re-read the link field in the descriptor. 4316 */ 4317 bf->bf_flags |= ATH_BUF_BUSY; 4318 } else 4319 #else 4320 if (txq->axq_depth == 0) 4321 #endif 4322 txq->axq_link = NULL; 4323 ATH_TXQ_UNLOCK(txq); 4324 4325 ni = bf->bf_node; 4326 if (ni != NULL) { 4327 an = ATH_NODE(ni); 4328 if (ts->ts_status == 0) { 4329 u_int8_t txant = ts->ts_antenna; 4330 sc->sc_stats.ast_ant_tx[txant]++; 4331 sc->sc_ant_tx[txant]++; 4332 if (ts->ts_finaltsi != 0) 4333 sc->sc_stats.ast_tx_altrate++; 4334 pri = M_WME_GETAC(bf->bf_m); 4335 if (pri >= WME_AC_VO) 4336 ic->ic_wme.wme_hipri_traffic++; 4337 if ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0) 4338 ni->ni_inact = ni->ni_inact_reload; 4339 } else { 4340 if (ts->ts_status & HAL_TXERR_XRETRY) 4341 sc->sc_stats.ast_tx_xretries++; 4342 if (ts->ts_status & HAL_TXERR_FIFO) 4343 sc->sc_stats.ast_tx_fifoerr++; 4344 if (ts->ts_status & HAL_TXERR_FILT) 4345 sc->sc_stats.ast_tx_filtered++; 4346 if (bf->bf_m->m_flags & M_FF) 4347 sc->sc_stats.ast_ff_txerr++; 4348 } 4349 sr = ts->ts_shortretry; 4350 lr = ts->ts_longretry; 4351 sc->sc_stats.ast_tx_shortretry += sr; 4352 sc->sc_stats.ast_tx_longretry += lr; 4353 /* 4354 * Hand the descriptor to the rate control algorithm. 4355 */ 4356 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 4357 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0) { 4358 /* 4359 * If frame was ack'd update statistics, 4360 * including the last rx time used to 4361 * workaround phantom bmiss interrupts. 4362 */ 4363 if (ts->ts_status == 0) { 4364 nacked++; 4365 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 4366 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4367 ts->ts_rssi); 4368 } 4369 ath_rate_tx_complete(sc, an, bf); 4370 } 4371 /* 4372 * Do any tx complete callback. Note this must 4373 * be done before releasing the node reference. 4374 */ 4375 if (bf->bf_m->m_flags & M_TXCB) 4376 ieee80211_process_callback(ni, bf->bf_m, 4377 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0 ? 4378 ts->ts_status : HAL_TXERR_XRETRY); 4379 ieee80211_free_node(ni); 4380 } 4381 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4382 BUS_DMASYNC_POSTWRITE); 4383 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4384 4385 m_freem(bf->bf_m); 4386 bf->bf_m = NULL; 4387 bf->bf_node = NULL; 4388 4389 ATH_TXBUF_LOCK(sc); 4390 last = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list); 4391 if (last != NULL) 4392 last->bf_flags &= ~ATH_BUF_BUSY; 4393 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4394 ATH_TXBUF_UNLOCK(sc); 4395 } 4396 #ifdef IEEE80211_SUPPORT_SUPERG 4397 /* 4398 * Flush fast-frame staging queue when traffic slows. 4399 */ 4400 if (txq->axq_depth <= 1) 4401 ieee80211_ff_flush(ic, txq->axq_ac); 4402 #endif 4403 return nacked; 4404 } 4405 4406 static __inline int 4407 txqactive(struct ath_hal *ah, int qnum) 4408 { 4409 u_int32_t txqs = 1<<qnum; 4410 ath_hal_gettxintrtxqs(ah, &txqs); 4411 return (txqs & (1<<qnum)); 4412 } 4413 4414 /* 4415 * Deferred processing of transmit interrupt; special-cased 4416 * for a single hardware transmit queue (e.g. 5210 and 5211). 4417 */ 4418 static void 4419 ath_tx_proc_q0(void *arg, int npending) 4420 { 4421 struct ath_softc *sc = arg; 4422 struct ifnet *ifp = sc->sc_ifp; 4423 4424 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 4425 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4426 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4427 ath_tx_processq(sc, sc->sc_cabq); 4428 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4429 sc->sc_wd_timer = 0; 4430 4431 if (sc->sc_softled) 4432 ath_led_event(sc, sc->sc_txrix); 4433 4434 ath_start(ifp); 4435 } 4436 4437 /* 4438 * Deferred processing of transmit interrupt; special-cased 4439 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4440 */ 4441 static void 4442 ath_tx_proc_q0123(void *arg, int npending) 4443 { 4444 struct ath_softc *sc = arg; 4445 struct ifnet *ifp = sc->sc_ifp; 4446 int nacked; 4447 4448 /* 4449 * Process each active queue. 4450 */ 4451 nacked = 0; 4452 if (txqactive(sc->sc_ah, 0)) 4453 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4454 if (txqactive(sc->sc_ah, 1)) 4455 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4456 if (txqactive(sc->sc_ah, 2)) 4457 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4458 if (txqactive(sc->sc_ah, 3)) 4459 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4460 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4461 ath_tx_processq(sc, sc->sc_cabq); 4462 if (nacked) 4463 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4464 4465 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4466 sc->sc_wd_timer = 0; 4467 4468 if (sc->sc_softled) 4469 ath_led_event(sc, sc->sc_txrix); 4470 4471 ath_start(ifp); 4472 } 4473 4474 /* 4475 * Deferred processing of transmit interrupt. 4476 */ 4477 static void 4478 ath_tx_proc(void *arg, int npending) 4479 { 4480 struct ath_softc *sc = arg; 4481 struct ifnet *ifp = sc->sc_ifp; 4482 int i, nacked; 4483 4484 /* 4485 * Process each active queue. 4486 */ 4487 nacked = 0; 4488 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4489 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4490 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4491 if (nacked) 4492 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4493 4494 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4495 sc->sc_wd_timer = 0; 4496 4497 if (sc->sc_softled) 4498 ath_led_event(sc, sc->sc_txrix); 4499 4500 ath_start(ifp); 4501 } 4502 4503 static void 4504 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4505 { 4506 #ifdef ATH_DEBUG 4507 struct ath_hal *ah = sc->sc_ah; 4508 #endif 4509 struct ieee80211_node *ni; 4510 struct ath_buf *bf; 4511 u_int ix; 4512 4513 /* 4514 * NB: this assumes output has been stopped and 4515 * we do not need to block ath_tx_proc 4516 */ 4517 ATH_TXBUF_LOCK(sc); 4518 bf = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list); 4519 if (bf != NULL) 4520 bf->bf_flags &= ~ATH_BUF_BUSY; 4521 ATH_TXBUF_UNLOCK(sc); 4522 for (ix = 0;; ix++) { 4523 ATH_TXQ_LOCK(txq); 4524 bf = STAILQ_FIRST(&txq->axq_q); 4525 if (bf == NULL) { 4526 txq->axq_link = NULL; 4527 ATH_TXQ_UNLOCK(txq); 4528 break; 4529 } 4530 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4531 ATH_TXQ_UNLOCK(txq); 4532 #ifdef ATH_DEBUG 4533 if (sc->sc_debug & ATH_DEBUG_RESET) { 4534 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 4535 4536 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, 4537 ath_hal_txprocdesc(ah, bf->bf_desc, 4538 &bf->bf_status.ds_txstat) == HAL_OK); 4539 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *), 4540 bf->bf_m->m_len, 0, -1); 4541 } 4542 #endif /* ATH_DEBUG */ 4543 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4544 ni = bf->bf_node; 4545 bf->bf_node = NULL; 4546 if (ni != NULL) { 4547 /* 4548 * Do any callback and reclaim the node reference. 4549 */ 4550 if (bf->bf_m->m_flags & M_TXCB) 4551 ieee80211_process_callback(ni, bf->bf_m, -1); 4552 ieee80211_free_node(ni); 4553 } 4554 m_freem(bf->bf_m); 4555 bf->bf_m = NULL; 4556 bf->bf_flags &= ~ATH_BUF_BUSY; 4557 4558 ATH_TXBUF_LOCK(sc); 4559 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4560 ATH_TXBUF_UNLOCK(sc); 4561 } 4562 } 4563 4564 static void 4565 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4566 { 4567 struct ath_hal *ah = sc->sc_ah; 4568 4569 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4570 __func__, txq->axq_qnum, 4571 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4572 txq->axq_link); 4573 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4574 } 4575 4576 /* 4577 * Drain the transmit queues and reclaim resources. 4578 */ 4579 static void 4580 ath_draintxq(struct ath_softc *sc) 4581 { 4582 struct ath_hal *ah = sc->sc_ah; 4583 struct ifnet *ifp = sc->sc_ifp; 4584 int i; 4585 4586 /* XXX return value */ 4587 if (!sc->sc_invalid) { 4588 /* don't touch the hardware if marked invalid */ 4589 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4590 __func__, sc->sc_bhalq, 4591 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 4592 NULL); 4593 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4594 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4595 if (ATH_TXQ_SETUP(sc, i)) 4596 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4597 } 4598 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4599 if (ATH_TXQ_SETUP(sc, i)) 4600 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4601 #ifdef ATH_DEBUG 4602 if (sc->sc_debug & ATH_DEBUG_RESET) { 4603 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 4604 if (bf != NULL && bf->bf_m != NULL) { 4605 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 4606 ath_hal_txprocdesc(ah, bf->bf_desc, 4607 &bf->bf_status.ds_txstat) == HAL_OK); 4608 ieee80211_dump_pkt(ifp->if_l2com, 4609 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len, 4610 0, -1); 4611 } 4612 } 4613 #endif /* ATH_DEBUG */ 4614 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4615 sc->sc_wd_timer = 0; 4616 } 4617 4618 /* 4619 * Disable the receive h/w in preparation for a reset. 4620 */ 4621 static void 4622 ath_stoprecv(struct ath_softc *sc) 4623 { 4624 #define PA2DESC(_sc, _pa) \ 4625 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 4626 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4627 struct ath_hal *ah = sc->sc_ah; 4628 4629 ath_hal_stoppcurecv(ah); /* disable PCU */ 4630 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4631 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4632 DELAY(3000); /* 3ms is long enough for 1 frame */ 4633 #ifdef ATH_DEBUG 4634 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4635 struct ath_buf *bf; 4636 u_int ix; 4637 4638 printf("%s: rx queue %p, link %p\n", __func__, 4639 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4640 ix = 0; 4641 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4642 struct ath_desc *ds = bf->bf_desc; 4643 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 4644 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4645 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 4646 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4647 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 4648 ix++; 4649 } 4650 } 4651 #endif 4652 if (sc->sc_rxpending != NULL) { 4653 m_freem(sc->sc_rxpending); 4654 sc->sc_rxpending = NULL; 4655 } 4656 sc->sc_rxlink = NULL; /* just in case */ 4657 #undef PA2DESC 4658 } 4659 4660 /* 4661 * Enable the receive h/w following a reset. 4662 */ 4663 static int 4664 ath_startrecv(struct ath_softc *sc) 4665 { 4666 struct ath_hal *ah = sc->sc_ah; 4667 struct ath_buf *bf; 4668 4669 sc->sc_rxlink = NULL; 4670 sc->sc_rxpending = NULL; 4671 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4672 int error = ath_rxbuf_init(sc, bf); 4673 if (error != 0) { 4674 DPRINTF(sc, ATH_DEBUG_RECV, 4675 "%s: ath_rxbuf_init failed %d\n", 4676 __func__, error); 4677 return error; 4678 } 4679 } 4680 4681 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4682 ath_hal_putrxbuf(ah, bf->bf_daddr); 4683 ath_hal_rxena(ah); /* enable recv descriptors */ 4684 ath_mode_init(sc); /* set filters, etc. */ 4685 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4686 return 0; 4687 } 4688 4689 /* 4690 * Update internal state after a channel change. 4691 */ 4692 static void 4693 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4694 { 4695 enum ieee80211_phymode mode; 4696 4697 /* 4698 * Change channels and update the h/w rate map 4699 * if we're switching; e.g. 11a to 11b/g. 4700 */ 4701 mode = ieee80211_chan2mode(chan); 4702 if (mode != sc->sc_curmode) 4703 ath_setcurmode(sc, mode); 4704 sc->sc_curchan = chan; 4705 } 4706 4707 /* 4708 * Set/change channels. If the channel is really being changed, 4709 * it's done by resetting the chip. To accomplish this we must 4710 * first cleanup any pending DMA, then restart stuff after a la 4711 * ath_init. 4712 */ 4713 static int 4714 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4715 { 4716 struct ifnet *ifp = sc->sc_ifp; 4717 struct ieee80211com *ic = ifp->if_l2com; 4718 struct ath_hal *ah = sc->sc_ah; 4719 4720 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 4721 __func__, ieee80211_chan2ieee(ic, chan), 4722 chan->ic_freq, chan->ic_flags); 4723 if (chan != sc->sc_curchan) { 4724 HAL_STATUS status; 4725 /* 4726 * To switch channels clear any pending DMA operations; 4727 * wait long enough for the RX fifo to drain, reset the 4728 * hardware at the new frequency, and then re-enable 4729 * the relevant bits of the h/w. 4730 */ 4731 ath_hal_intrset(ah, 0); /* disable interrupts */ 4732 ath_draintxq(sc); /* clear pending tx frames */ 4733 ath_stoprecv(sc); /* turn off frame recv */ 4734 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) { 4735 if_printf(ifp, "%s: unable to reset " 4736 "channel %u (%u MHz, flags 0x%x), hal status %u\n", 4737 __func__, ieee80211_chan2ieee(ic, chan), 4738 chan->ic_freq, chan->ic_flags, status); 4739 return EIO; 4740 } 4741 sc->sc_diversity = ath_hal_getdiversity(ah); 4742 4743 /* 4744 * Re-enable rx framework. 4745 */ 4746 if (ath_startrecv(sc) != 0) { 4747 if_printf(ifp, "%s: unable to restart recv logic\n", 4748 __func__); 4749 return EIO; 4750 } 4751 4752 /* 4753 * Change channels and update the h/w rate map 4754 * if we're switching; e.g. 11a to 11b/g. 4755 */ 4756 ath_chan_change(sc, chan); 4757 4758 /* 4759 * Re-enable interrupts. 4760 */ 4761 ath_hal_intrset(ah, sc->sc_imask); 4762 } 4763 return 0; 4764 } 4765 4766 /* 4767 * Periodically recalibrate the PHY to account 4768 * for temperature/environment changes. 4769 */ 4770 static void 4771 ath_calibrate(void *arg) 4772 { 4773 struct ath_softc *sc = arg; 4774 struct ath_hal *ah = sc->sc_ah; 4775 struct ifnet *ifp = sc->sc_ifp; 4776 struct ieee80211com *ic = ifp->if_l2com; 4777 HAL_BOOL longCal, isCalDone; 4778 HAL_BOOL aniCal, shortCal = AH_FALSE; 4779 int nextcal; 4780 4781 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 4782 goto restart; 4783 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 4784 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000); 4785 if (sc->sc_doresetcal) 4786 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000); 4787 4788 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal); 4789 if (aniCal) { 4790 sc->sc_stats.ast_ani_cal++; 4791 sc->sc_lastani = ticks; 4792 ath_hal_ani_poll(ah, sc->sc_curchan); 4793 } 4794 4795 if (longCal) { 4796 sc->sc_stats.ast_per_cal++; 4797 sc->sc_lastlongcal = ticks; 4798 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4799 /* 4800 * Rfgain is out of bounds, reset the chip 4801 * to load new gain values. 4802 */ 4803 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4804 "%s: rfgain change\n", __func__); 4805 sc->sc_stats.ast_per_rfgain++; 4806 ath_reset(ifp); 4807 } 4808 /* 4809 * If this long cal is after an idle period, then 4810 * reset the data collection state so we start fresh. 4811 */ 4812 if (sc->sc_resetcal) { 4813 (void) ath_hal_calreset(ah, sc->sc_curchan); 4814 sc->sc_lastcalreset = ticks; 4815 sc->sc_lastshortcal = ticks; 4816 sc->sc_resetcal = 0; 4817 sc->sc_doresetcal = AH_TRUE; 4818 } 4819 } 4820 4821 /* Only call if we're doing a short/long cal, not for ANI calibration */ 4822 if (shortCal || longCal) { 4823 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 4824 if (longCal) { 4825 /* 4826 * Calibrate noise floor data again in case of change. 4827 */ 4828 ath_hal_process_noisefloor(ah); 4829 } 4830 } else { 4831 DPRINTF(sc, ATH_DEBUG_ANY, 4832 "%s: calibration of channel %u failed\n", 4833 __func__, sc->sc_curchan->ic_freq); 4834 sc->sc_stats.ast_per_calfail++; 4835 } 4836 if (shortCal) 4837 sc->sc_lastshortcal = ticks; 4838 } 4839 if (!isCalDone) { 4840 restart: 4841 /* 4842 * Use a shorter interval to potentially collect multiple 4843 * data samples required to complete calibration. Once 4844 * we're told the work is done we drop back to a longer 4845 * interval between requests. We're more aggressive doing 4846 * work when operating as an AP to improve operation right 4847 * after startup. 4848 */ 4849 sc->sc_lastshortcal = ticks; 4850 nextcal = ath_shortcalinterval*hz/1000; 4851 if (sc->sc_opmode != HAL_M_HOSTAP) 4852 nextcal *= 10; 4853 sc->sc_doresetcal = AH_TRUE; 4854 } else { 4855 /* nextcal should be the shortest time for next event */ 4856 nextcal = ath_longcalinterval*hz; 4857 if (sc->sc_lastcalreset == 0) 4858 sc->sc_lastcalreset = sc->sc_lastlongcal; 4859 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 4860 sc->sc_resetcal = 1; /* setup reset next trip */ 4861 sc->sc_doresetcal = AH_FALSE; 4862 } 4863 /* ANI calibration may occur more often than short/long/resetcal */ 4864 if (ath_anicalinterval > 0) 4865 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000); 4866 4867 if (nextcal != 0) { 4868 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 4869 __func__, nextcal, isCalDone ? "" : "!"); 4870 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc); 4871 } else { 4872 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 4873 __func__); 4874 /* NB: don't rearm timer */ 4875 } 4876 } 4877 4878 static void 4879 ath_scan_start(struct ieee80211com *ic) 4880 { 4881 struct ifnet *ifp = ic->ic_ifp; 4882 struct ath_softc *sc = ifp->if_softc; 4883 struct ath_hal *ah = sc->sc_ah; 4884 u_int32_t rfilt; 4885 4886 /* XXX calibration timer? */ 4887 4888 sc->sc_scanning = 1; 4889 sc->sc_syncbeacon = 0; 4890 rfilt = ath_calcrxfilter(sc); 4891 ath_hal_setrxfilter(ah, rfilt); 4892 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 4893 4894 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 4895 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr)); 4896 } 4897 4898 static void 4899 ath_scan_end(struct ieee80211com *ic) 4900 { 4901 struct ifnet *ifp = ic->ic_ifp; 4902 struct ath_softc *sc = ifp->if_softc; 4903 struct ath_hal *ah = sc->sc_ah; 4904 u_int32_t rfilt; 4905 4906 sc->sc_scanning = 0; 4907 rfilt = ath_calcrxfilter(sc); 4908 ath_hal_setrxfilter(ah, rfilt); 4909 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 4910 4911 ath_hal_process_noisefloor(ah); 4912 4913 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 4914 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 4915 sc->sc_curaid); 4916 } 4917 4918 static void 4919 ath_set_channel(struct ieee80211com *ic) 4920 { 4921 struct ifnet *ifp = ic->ic_ifp; 4922 struct ath_softc *sc = ifp->if_softc; 4923 4924 (void) ath_chan_set(sc, ic->ic_curchan); 4925 /* 4926 * If we are returning to our bss channel then mark state 4927 * so the next recv'd beacon's tsf will be used to sync the 4928 * beacon timers. Note that since we only hear beacons in 4929 * sta/ibss mode this has no effect in other operating modes. 4930 */ 4931 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 4932 sc->sc_syncbeacon = 1; 4933 } 4934 4935 /* 4936 * Walk the vap list and check if there any vap's in RUN state. 4937 */ 4938 static int 4939 ath_isanyrunningvaps(struct ieee80211vap *this) 4940 { 4941 struct ieee80211com *ic = this->iv_ic; 4942 struct ieee80211vap *vap; 4943 4944 IEEE80211_LOCK_ASSERT(ic); 4945 4946 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 4947 if (vap != this && vap->iv_state >= IEEE80211_S_RUN) 4948 return 1; 4949 } 4950 return 0; 4951 } 4952 4953 static int 4954 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 4955 { 4956 struct ieee80211com *ic = vap->iv_ic; 4957 struct ath_softc *sc = ic->ic_ifp->if_softc; 4958 struct ath_vap *avp = ATH_VAP(vap); 4959 struct ath_hal *ah = sc->sc_ah; 4960 struct ieee80211_node *ni = NULL; 4961 int i, error, stamode; 4962 u_int32_t rfilt; 4963 static const HAL_LED_STATE leds[] = { 4964 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4965 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4966 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4967 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4968 HAL_LED_RUN, /* IEEE80211_S_CAC */ 4969 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4970 HAL_LED_RUN, /* IEEE80211_S_CSA */ 4971 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 4972 }; 4973 4974 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4975 ieee80211_state_name[vap->iv_state], 4976 ieee80211_state_name[nstate]); 4977 4978 callout_drain(&sc->sc_cal_ch); 4979 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4980 4981 if (nstate == IEEE80211_S_SCAN) { 4982 /* 4983 * Scanning: turn off beacon miss and don't beacon. 4984 * Mark beacon state so when we reach RUN state we'll 4985 * [re]setup beacons. Unblock the task q thread so 4986 * deferred interrupt processing is done. 4987 */ 4988 ath_hal_intrset(ah, 4989 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4990 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4991 sc->sc_beacons = 0; 4992 taskqueue_unblock(sc->sc_tq); 4993 } 4994 4995 ni = vap->iv_bss; 4996 rfilt = ath_calcrxfilter(sc); 4997 stamode = (vap->iv_opmode == IEEE80211_M_STA || 4998 vap->iv_opmode == IEEE80211_M_AHDEMO || 4999 vap->iv_opmode == IEEE80211_M_IBSS); 5000 if (stamode && nstate == IEEE80211_S_RUN) { 5001 sc->sc_curaid = ni->ni_associd; 5002 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5003 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5004 } 5005 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5006 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid); 5007 ath_hal_setrxfilter(ah, rfilt); 5008 5009 /* XXX is this to restore keycache on resume? */ 5010 if (vap->iv_opmode != IEEE80211_M_STA && 5011 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5012 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5013 if (ath_hal_keyisvalid(ah, i)) 5014 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5015 } 5016 5017 /* 5018 * Invoke the parent method to do net80211 work. 5019 */ 5020 error = avp->av_newstate(vap, nstate, arg); 5021 if (error != 0) 5022 goto bad; 5023 5024 if (nstate == IEEE80211_S_RUN) { 5025 /* NB: collect bss node again, it may have changed */ 5026 ni = vap->iv_bss; 5027 5028 DPRINTF(sc, ATH_DEBUG_STATE, 5029 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 5030 "capinfo 0x%04x chan %d\n", __func__, 5031 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid), 5032 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5033 5034 switch (vap->iv_opmode) { 5035 #ifdef IEEE80211_SUPPORT_TDMA 5036 case IEEE80211_M_AHDEMO: 5037 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 5038 break; 5039 /* fall thru... */ 5040 #endif 5041 case IEEE80211_M_HOSTAP: 5042 case IEEE80211_M_IBSS: 5043 case IEEE80211_M_MBSS: 5044 /* 5045 * Allocate and setup the beacon frame. 5046 * 5047 * Stop any previous beacon DMA. This may be 5048 * necessary, for example, when an ibss merge 5049 * causes reconfiguration; there will be a state 5050 * transition from RUN->RUN that means we may 5051 * be called with beacon transmission active. 5052 */ 5053 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5054 5055 error = ath_beacon_alloc(sc, ni); 5056 if (error != 0) 5057 goto bad; 5058 /* 5059 * If joining an adhoc network defer beacon timer 5060 * configuration to the next beacon frame so we 5061 * have a current TSF to use. Otherwise we're 5062 * starting an ibss/bss so there's no need to delay; 5063 * if this is the first vap moving to RUN state, then 5064 * beacon state needs to be [re]configured. 5065 */ 5066 if (vap->iv_opmode == IEEE80211_M_IBSS && 5067 ni->ni_tstamp.tsf != 0) { 5068 sc->sc_syncbeacon = 1; 5069 } else if (!sc->sc_beacons) { 5070 #ifdef IEEE80211_SUPPORT_TDMA 5071 if (vap->iv_caps & IEEE80211_C_TDMA) 5072 ath_tdma_config(sc, vap); 5073 else 5074 #endif 5075 ath_beacon_config(sc, vap); 5076 sc->sc_beacons = 1; 5077 } 5078 break; 5079 case IEEE80211_M_STA: 5080 /* 5081 * Defer beacon timer configuration to the next 5082 * beacon frame so we have a current TSF to use 5083 * (any TSF collected when scanning is likely old). 5084 */ 5085 sc->sc_syncbeacon = 1; 5086 break; 5087 case IEEE80211_M_MONITOR: 5088 /* 5089 * Monitor mode vaps have only INIT->RUN and RUN->RUN 5090 * transitions so we must re-enable interrupts here to 5091 * handle the case of a single monitor mode vap. 5092 */ 5093 ath_hal_intrset(ah, sc->sc_imask); 5094 break; 5095 case IEEE80211_M_WDS: 5096 break; 5097 default: 5098 break; 5099 } 5100 /* 5101 * Let the hal process statistics collected during a 5102 * scan so it can provide calibrated noise floor data. 5103 */ 5104 ath_hal_process_noisefloor(ah); 5105 /* 5106 * Reset rssi stats; maybe not the best place... 5107 */ 5108 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 5109 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 5110 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 5111 /* 5112 * Finally, start any timers and the task q thread 5113 * (in case we didn't go through SCAN state). 5114 */ 5115 if (ath_longcalinterval != 0) { 5116 /* start periodic recalibration timer */ 5117 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 5118 } else { 5119 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5120 "%s: calibration disabled\n", __func__); 5121 } 5122 taskqueue_unblock(sc->sc_tq); 5123 } else if (nstate == IEEE80211_S_INIT) { 5124 /* 5125 * If there are no vaps left in RUN state then 5126 * shutdown host/driver operation: 5127 * o disable interrupts 5128 * o disable the task queue thread 5129 * o mark beacon processing as stopped 5130 */ 5131 if (!ath_isanyrunningvaps(vap)) { 5132 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5133 /* disable interrupts */ 5134 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 5135 taskqueue_block(sc->sc_tq); 5136 sc->sc_beacons = 0; 5137 } 5138 #ifdef IEEE80211_SUPPORT_TDMA 5139 ath_hal_setcca(ah, AH_TRUE); 5140 #endif 5141 } 5142 bad: 5143 return error; 5144 } 5145 5146 /* 5147 * Allocate a key cache slot to the station so we can 5148 * setup a mapping from key index to node. The key cache 5149 * slot is needed for managing antenna state and for 5150 * compression when stations do not use crypto. We do 5151 * it uniliaterally here; if crypto is employed this slot 5152 * will be reassigned. 5153 */ 5154 static void 5155 ath_setup_stationkey(struct ieee80211_node *ni) 5156 { 5157 struct ieee80211vap *vap = ni->ni_vap; 5158 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5159 ieee80211_keyix keyix, rxkeyix; 5160 5161 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 5162 /* 5163 * Key cache is full; we'll fall back to doing 5164 * the more expensive lookup in software. Note 5165 * this also means no h/w compression. 5166 */ 5167 /* XXX msg+statistic */ 5168 } else { 5169 /* XXX locking? */ 5170 ni->ni_ucastkey.wk_keyix = keyix; 5171 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 5172 /* NB: must mark device key to get called back on delete */ 5173 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 5174 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 5175 /* NB: this will create a pass-thru key entry */ 5176 ath_keyset(sc, &ni->ni_ucastkey, vap->iv_bss); 5177 } 5178 } 5179 5180 /* 5181 * Setup driver-specific state for a newly associated node. 5182 * Note that we're called also on a re-associate, the isnew 5183 * param tells us if this is the first time or not. 5184 */ 5185 static void 5186 ath_newassoc(struct ieee80211_node *ni, int isnew) 5187 { 5188 struct ath_node *an = ATH_NODE(ni); 5189 struct ieee80211vap *vap = ni->ni_vap; 5190 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5191 const struct ieee80211_txparam *tp = ni->ni_txparms; 5192 5193 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); 5194 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate); 5195 5196 ath_rate_newassoc(sc, an, isnew); 5197 if (isnew && 5198 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 5199 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 5200 ath_setup_stationkey(ni); 5201 } 5202 5203 static int 5204 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 5205 int nchans, struct ieee80211_channel chans[]) 5206 { 5207 struct ath_softc *sc = ic->ic_ifp->if_softc; 5208 struct ath_hal *ah = sc->sc_ah; 5209 HAL_STATUS status; 5210 5211 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5212 "%s: rd %u cc %u location %c%s\n", 5213 __func__, reg->regdomain, reg->country, reg->location, 5214 reg->ecm ? " ecm" : ""); 5215 5216 status = ath_hal_set_channels(ah, chans, nchans, 5217 reg->country, reg->regdomain); 5218 if (status != HAL_OK) { 5219 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 5220 __func__, status); 5221 return EINVAL; /* XXX */ 5222 } 5223 return 0; 5224 } 5225 5226 static void 5227 ath_getradiocaps(struct ieee80211com *ic, 5228 int maxchans, int *nchans, struct ieee80211_channel chans[]) 5229 { 5230 struct ath_softc *sc = ic->ic_ifp->if_softc; 5231 struct ath_hal *ah = sc->sc_ah; 5232 5233 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 5234 __func__, SKU_DEBUG, CTRY_DEFAULT); 5235 5236 /* XXX check return */ 5237 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 5238 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 5239 5240 } 5241 5242 static int 5243 ath_getchannels(struct ath_softc *sc) 5244 { 5245 struct ifnet *ifp = sc->sc_ifp; 5246 struct ieee80211com *ic = ifp->if_l2com; 5247 struct ath_hal *ah = sc->sc_ah; 5248 HAL_STATUS status; 5249 5250 /* 5251 * Collect channel set based on EEPROM contents. 5252 */ 5253 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 5254 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 5255 if (status != HAL_OK) { 5256 if_printf(ifp, "%s: unable to collect channel list from hal, " 5257 "status %d\n", __func__, status); 5258 return EINVAL; 5259 } 5260 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 5261 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 5262 /* XXX map Atheros sku's to net80211 SKU's */ 5263 /* XXX net80211 types too small */ 5264 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 5265 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 5266 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 5267 ic->ic_regdomain.isocc[1] = ' '; 5268 5269 ic->ic_regdomain.ecm = 1; 5270 ic->ic_regdomain.location = 'I'; 5271 5272 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5273 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 5274 __func__, sc->sc_eerd, sc->sc_eecc, 5275 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 5276 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 5277 return 0; 5278 } 5279 5280 static void 5281 ath_led_done(void *arg) 5282 { 5283 struct ath_softc *sc = arg; 5284 5285 sc->sc_blinking = 0; 5286 } 5287 5288 /* 5289 * Turn the LED off: flip the pin and then set a timer so no 5290 * update will happen for the specified duration. 5291 */ 5292 static void 5293 ath_led_off(void *arg) 5294 { 5295 struct ath_softc *sc = arg; 5296 5297 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 5298 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 5299 } 5300 5301 /* 5302 * Blink the LED according to the specified on/off times. 5303 */ 5304 static void 5305 ath_led_blink(struct ath_softc *sc, int on, int off) 5306 { 5307 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 5308 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 5309 sc->sc_blinking = 1; 5310 sc->sc_ledoff = off; 5311 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 5312 } 5313 5314 static void 5315 ath_led_event(struct ath_softc *sc, int rix) 5316 { 5317 sc->sc_ledevent = ticks; /* time of last event */ 5318 if (sc->sc_blinking) /* don't interrupt active blink */ 5319 return; 5320 ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff); 5321 } 5322 5323 static int 5324 ath_rate_setup(struct ath_softc *sc, u_int mode) 5325 { 5326 struct ath_hal *ah = sc->sc_ah; 5327 const HAL_RATE_TABLE *rt; 5328 5329 switch (mode) { 5330 case IEEE80211_MODE_11A: 5331 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5332 break; 5333 case IEEE80211_MODE_HALF: 5334 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 5335 break; 5336 case IEEE80211_MODE_QUARTER: 5337 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 5338 break; 5339 case IEEE80211_MODE_11B: 5340 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5341 break; 5342 case IEEE80211_MODE_11G: 5343 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5344 break; 5345 case IEEE80211_MODE_TURBO_A: 5346 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 5347 break; 5348 case IEEE80211_MODE_TURBO_G: 5349 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5350 break; 5351 case IEEE80211_MODE_STURBO_A: 5352 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5353 break; 5354 case IEEE80211_MODE_11NA: 5355 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 5356 break; 5357 case IEEE80211_MODE_11NG: 5358 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 5359 break; 5360 default: 5361 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5362 __func__, mode); 5363 return 0; 5364 } 5365 sc->sc_rates[mode] = rt; 5366 return (rt != NULL); 5367 } 5368 5369 static void 5370 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5371 { 5372 #define N(a) (sizeof(a)/sizeof(a[0])) 5373 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5374 static const struct { 5375 u_int rate; /* tx/rx 802.11 rate */ 5376 u_int16_t timeOn; /* LED on time (ms) */ 5377 u_int16_t timeOff; /* LED off time (ms) */ 5378 } blinkrates[] = { 5379 { 108, 40, 10 }, 5380 { 96, 44, 11 }, 5381 { 72, 50, 13 }, 5382 { 48, 57, 14 }, 5383 { 36, 67, 16 }, 5384 { 24, 80, 20 }, 5385 { 22, 100, 25 }, 5386 { 18, 133, 34 }, 5387 { 12, 160, 40 }, 5388 { 10, 200, 50 }, 5389 { 6, 240, 58 }, 5390 { 4, 267, 66 }, 5391 { 2, 400, 100 }, 5392 { 0, 500, 130 }, 5393 /* XXX half/quarter rates */ 5394 }; 5395 const HAL_RATE_TABLE *rt; 5396 int i, j; 5397 5398 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5399 rt = sc->sc_rates[mode]; 5400 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5401 for (i = 0; i < rt->rateCount; i++) { 5402 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 5403 if (rt->info[i].phy != IEEE80211_T_HT) 5404 sc->sc_rixmap[ieeerate] = i; 5405 else 5406 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 5407 } 5408 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5409 for (i = 0; i < N(sc->sc_hwmap); i++) { 5410 if (i >= rt->rateCount) { 5411 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5412 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5413 continue; 5414 } 5415 sc->sc_hwmap[i].ieeerate = 5416 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 5417 if (rt->info[i].phy == IEEE80211_T_HT) 5418 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 5419 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5420 if (rt->info[i].shortPreamble || 5421 rt->info[i].phy == IEEE80211_T_OFDM) 5422 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5423 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags; 5424 for (j = 0; j < N(blinkrates)-1; j++) 5425 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5426 break; 5427 /* NB: this uses the last entry if the rate isn't found */ 5428 /* XXX beware of overlow */ 5429 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5430 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5431 } 5432 sc->sc_currates = rt; 5433 sc->sc_curmode = mode; 5434 /* 5435 * All protection frames are transmited at 2Mb/s for 5436 * 11g, otherwise at 1Mb/s. 5437 */ 5438 if (mode == IEEE80211_MODE_11G) 5439 sc->sc_protrix = ath_tx_findrix(sc, 2*2); 5440 else 5441 sc->sc_protrix = ath_tx_findrix(sc, 2*1); 5442 /* NB: caller is responsible for resetting rate control state */ 5443 #undef N 5444 } 5445 5446 static void 5447 ath_watchdog(void *arg) 5448 { 5449 struct ath_softc *sc = arg; 5450 5451 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 5452 struct ifnet *ifp = sc->sc_ifp; 5453 uint32_t hangs; 5454 5455 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 5456 hangs != 0) { 5457 if_printf(ifp, "%s hang detected (0x%x)\n", 5458 hangs & 0xff ? "bb" : "mac", hangs); 5459 } else 5460 if_printf(ifp, "device timeout\n"); 5461 ath_reset(ifp); 5462 ifp->if_oerrors++; 5463 sc->sc_stats.ast_watchdog++; 5464 } 5465 callout_schedule(&sc->sc_wd_ch, hz); 5466 } 5467 5468 #ifdef ATH_DIAGAPI 5469 /* 5470 * Diagnostic interface to the HAL. This is used by various 5471 * tools to do things like retrieve register contents for 5472 * debugging. The mechanism is intentionally opaque so that 5473 * it can change frequently w/o concern for compatiblity. 5474 */ 5475 static int 5476 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5477 { 5478 struct ath_hal *ah = sc->sc_ah; 5479 u_int id = ad->ad_id & ATH_DIAG_ID; 5480 void *indata = NULL; 5481 void *outdata = NULL; 5482 u_int32_t insize = ad->ad_in_size; 5483 u_int32_t outsize = ad->ad_out_size; 5484 int error = 0; 5485 5486 if (ad->ad_id & ATH_DIAG_IN) { 5487 /* 5488 * Copy in data. 5489 */ 5490 indata = malloc(insize, M_TEMP, M_NOWAIT); 5491 if (indata == NULL) { 5492 error = ENOMEM; 5493 goto bad; 5494 } 5495 error = copyin(ad->ad_in_data, indata, insize); 5496 if (error) 5497 goto bad; 5498 } 5499 if (ad->ad_id & ATH_DIAG_DYN) { 5500 /* 5501 * Allocate a buffer for the results (otherwise the HAL 5502 * returns a pointer to a buffer where we can read the 5503 * results). Note that we depend on the HAL leaving this 5504 * pointer for us to use below in reclaiming the buffer; 5505 * may want to be more defensive. 5506 */ 5507 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5508 if (outdata == NULL) { 5509 error = ENOMEM; 5510 goto bad; 5511 } 5512 } 5513 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5514 if (outsize < ad->ad_out_size) 5515 ad->ad_out_size = outsize; 5516 if (outdata != NULL) 5517 error = copyout(outdata, ad->ad_out_data, 5518 ad->ad_out_size); 5519 } else { 5520 error = EINVAL; 5521 } 5522 bad: 5523 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5524 free(indata, M_TEMP); 5525 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5526 free(outdata, M_TEMP); 5527 return error; 5528 } 5529 #endif /* ATH_DIAGAPI */ 5530 5531 static int 5532 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 5533 { 5534 #define IS_RUNNING(ifp) \ 5535 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 5536 struct ath_softc *sc = ifp->if_softc; 5537 struct ieee80211com *ic = ifp->if_l2com; 5538 struct ifreq *ifr = (struct ifreq *)data; 5539 const HAL_RATE_TABLE *rt; 5540 int error = 0; 5541 5542 switch (cmd) { 5543 case SIOCSIFFLAGS: 5544 ATH_LOCK(sc); 5545 if (IS_RUNNING(ifp)) { 5546 /* 5547 * To avoid rescanning another access point, 5548 * do not call ath_init() here. Instead, 5549 * only reflect promisc mode settings. 5550 */ 5551 ath_mode_init(sc); 5552 } else if (ifp->if_flags & IFF_UP) { 5553 /* 5554 * Beware of being called during attach/detach 5555 * to reset promiscuous mode. In that case we 5556 * will still be marked UP but not RUNNING. 5557 * However trying to re-init the interface 5558 * is the wrong thing to do as we've already 5559 * torn down much of our state. There's 5560 * probably a better way to deal with this. 5561 */ 5562 if (!sc->sc_invalid) 5563 ath_init(sc); /* XXX lose error */ 5564 } else { 5565 ath_stop_locked(ifp); 5566 #ifdef notyet 5567 /* XXX must wakeup in places like ath_vap_delete */ 5568 if (!sc->sc_invalid) 5569 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 5570 #endif 5571 } 5572 ATH_UNLOCK(sc); 5573 break; 5574 case SIOCGIFMEDIA: 5575 case SIOCSIFMEDIA: 5576 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 5577 break; 5578 case SIOCGATHSTATS: 5579 /* NB: embed these numbers to get a consistent view */ 5580 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5581 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5582 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi); 5583 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi); 5584 #ifdef IEEE80211_SUPPORT_TDMA 5585 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap); 5586 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam); 5587 #endif 5588 rt = sc->sc_currates; 5589 /* XXX HT rates */ 5590 sc->sc_stats.ast_tx_rate = 5591 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC; 5592 return copyout(&sc->sc_stats, 5593 ifr->ifr_data, sizeof (sc->sc_stats)); 5594 case SIOCZATHSTATS: 5595 error = priv_check(curthread, PRIV_DRIVER); 5596 if (error == 0) 5597 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 5598 break; 5599 #ifdef ATH_DIAGAPI 5600 case SIOCGATHDIAG: 5601 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5602 break; 5603 #endif 5604 case SIOCGIFADDR: 5605 error = ether_ioctl(ifp, cmd, data); 5606 break; 5607 default: 5608 error = EINVAL; 5609 break; 5610 } 5611 return error; 5612 #undef IS_RUNNING 5613 } 5614 5615 /* 5616 * Announce various information on device/driver attach. 5617 */ 5618 static void 5619 ath_announce(struct ath_softc *sc) 5620 { 5621 struct ifnet *ifp = sc->sc_ifp; 5622 struct ath_hal *ah = sc->sc_ah; 5623 5624 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n", 5625 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 5626 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5627 if (bootverbose) { 5628 int i; 5629 for (i = 0; i <= WME_AC_VO; i++) { 5630 struct ath_txq *txq = sc->sc_ac2q[i]; 5631 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5632 txq->axq_qnum, ieee80211_wme_acnames[i]); 5633 } 5634 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5635 sc->sc_cabq->axq_qnum); 5636 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5637 } 5638 if (ath_rxbuf != ATH_RXBUF) 5639 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5640 if (ath_txbuf != ATH_TXBUF) 5641 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5642 if (sc->sc_mcastkey && bootverbose) 5643 if_printf(ifp, "using multicast key search\n"); 5644 } 5645 5646 #ifdef IEEE80211_SUPPORT_TDMA 5647 static __inline uint32_t 5648 ath_hal_getnexttbtt(struct ath_hal *ah) 5649 { 5650 #define AR_TIMER0 0x8028 5651 return OS_REG_READ(ah, AR_TIMER0); 5652 } 5653 5654 static __inline void 5655 ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta) 5656 { 5657 /* XXX handle wrap/overflow */ 5658 OS_REG_WRITE(ah, AR_TSF_L32, OS_REG_READ(ah, AR_TSF_L32) + tsfdelta); 5659 } 5660 5661 static void 5662 ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval) 5663 { 5664 struct ath_hal *ah = sc->sc_ah; 5665 HAL_BEACON_TIMERS bt; 5666 5667 bt.bt_intval = bintval | HAL_BEACON_ENA; 5668 bt.bt_nexttbtt = nexttbtt; 5669 bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep; 5670 bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep; 5671 bt.bt_nextatim = nexttbtt+1; 5672 ath_hal_beaconsettimers(ah, &bt); 5673 } 5674 5675 /* 5676 * Calculate the beacon interval. This is periodic in the 5677 * superframe for the bss. We assume each station is configured 5678 * identically wrt transmit rate so the guard time we calculate 5679 * above will be the same on all stations. Note we need to 5680 * factor in the xmit time because the hardware will schedule 5681 * a frame for transmit if the start of the frame is within 5682 * the burst time. When we get hardware that properly kills 5683 * frames in the PCU we can reduce/eliminate the guard time. 5684 * 5685 * Roundup to 1024 is so we have 1 TU buffer in the guard time 5686 * to deal with the granularity of the nexttbtt timer. 11n MAC's 5687 * with 1us timer granularity should allow us to reduce/eliminate 5688 * this. 5689 */ 5690 static void 5691 ath_tdma_bintvalsetup(struct ath_softc *sc, 5692 const struct ieee80211_tdma_state *tdma) 5693 { 5694 /* copy from vap state (XXX check all vaps have same value?) */ 5695 sc->sc_tdmaslotlen = tdma->tdma_slotlen; 5696 5697 sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) * 5698 tdma->tdma_slotcnt, 1024); 5699 sc->sc_tdmabintval >>= 10; /* TSF -> TU */ 5700 if (sc->sc_tdmabintval & 1) 5701 sc->sc_tdmabintval++; 5702 5703 if (tdma->tdma_slot == 0) { 5704 /* 5705 * Only slot 0 beacons; other slots respond. 5706 */ 5707 sc->sc_imask |= HAL_INT_SWBA; 5708 sc->sc_tdmaswba = 0; /* beacon immediately */ 5709 } else { 5710 /* XXX all vaps must be slot 0 or slot !0 */ 5711 sc->sc_imask &= ~HAL_INT_SWBA; 5712 } 5713 } 5714 5715 /* 5716 * Max 802.11 overhead. This assumes no 4-address frames and 5717 * the encapsulation done by ieee80211_encap (llc). We also 5718 * include potential crypto overhead. 5719 */ 5720 #define IEEE80211_MAXOVERHEAD \ 5721 (sizeof(struct ieee80211_qosframe) \ 5722 + sizeof(struct llc) \ 5723 + IEEE80211_ADDR_LEN \ 5724 + IEEE80211_WEP_IVLEN \ 5725 + IEEE80211_WEP_KIDLEN \ 5726 + IEEE80211_WEP_CRCLEN \ 5727 + IEEE80211_WEP_MICLEN \ 5728 + IEEE80211_CRC_LEN) 5729 5730 /* 5731 * Setup initially for tdma operation. Start the beacon 5732 * timers and enable SWBA if we are slot 0. Otherwise 5733 * we wait for slot 0 to arrive so we can sync up before 5734 * starting to transmit. 5735 */ 5736 static void 5737 ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap) 5738 { 5739 struct ath_hal *ah = sc->sc_ah; 5740 struct ifnet *ifp = sc->sc_ifp; 5741 struct ieee80211com *ic = ifp->if_l2com; 5742 const struct ieee80211_txparam *tp; 5743 const struct ieee80211_tdma_state *tdma = NULL; 5744 int rix; 5745 5746 if (vap == NULL) { 5747 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 5748 if (vap == NULL) { 5749 if_printf(ifp, "%s: no vaps?\n", __func__); 5750 return; 5751 } 5752 } 5753 tp = vap->iv_bss->ni_txparms; 5754 /* 5755 * Calculate the guard time for each slot. This is the 5756 * time to send a maximal-size frame according to the 5757 * fixed/lowest transmit rate. Note that the interface 5758 * mtu does not include the 802.11 overhead so we must 5759 * tack that on (ath_hal_computetxtime includes the 5760 * preamble and plcp in it's calculation). 5761 */ 5762 tdma = vap->iv_tdma; 5763 if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 5764 rix = ath_tx_findrix(sc, tp->ucastrate); 5765 else 5766 rix = ath_tx_findrix(sc, tp->mcastrate); 5767 /* XXX short preamble assumed */ 5768 sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates, 5769 ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE); 5770 5771 ath_hal_intrset(ah, 0); 5772 5773 ath_beaconq_config(sc); /* setup h/w beacon q */ 5774 if (sc->sc_setcca) 5775 ath_hal_setcca(ah, AH_FALSE); /* disable CCA */ 5776 ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */ 5777 ath_tdma_settimers(sc, sc->sc_tdmabintval, 5778 sc->sc_tdmabintval | HAL_BEACON_RESET_TSF); 5779 sc->sc_syncbeacon = 0; 5780 5781 sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER; 5782 sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER; 5783 5784 ath_hal_intrset(ah, sc->sc_imask); 5785 5786 DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u " 5787 "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__, 5788 tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt, 5789 tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval, 5790 sc->sc_tdmadbaprep); 5791 } 5792 5793 /* 5794 * Update tdma operation. Called from the 802.11 layer 5795 * when a beacon is received from the TDMA station operating 5796 * in the slot immediately preceding us in the bss. Use 5797 * the rx timestamp for the beacon frame to update our 5798 * beacon timers so we follow their schedule. Note that 5799 * by using the rx timestamp we implicitly include the 5800 * propagation delay in our schedule. 5801 */ 5802 static void 5803 ath_tdma_update(struct ieee80211_node *ni, 5804 const struct ieee80211_tdma_param *tdma, int changed) 5805 { 5806 #define TSF_TO_TU(_h,_l) \ 5807 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 5808 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 5809 struct ieee80211vap *vap = ni->ni_vap; 5810 struct ieee80211com *ic = ni->ni_ic; 5811 struct ath_softc *sc = ic->ic_ifp->if_softc; 5812 struct ath_hal *ah = sc->sc_ah; 5813 const HAL_RATE_TABLE *rt = sc->sc_currates; 5814 u_int64_t tsf, rstamp, nextslot; 5815 u_int32_t txtime, nextslottu, timer0; 5816 int32_t tudelta, tsfdelta; 5817 const struct ath_rx_status *rs; 5818 int rix; 5819 5820 sc->sc_stats.ast_tdma_update++; 5821 5822 /* 5823 * Check for and adopt configuration changes. 5824 */ 5825 if (changed != 0) { 5826 const struct ieee80211_tdma_state *ts = vap->iv_tdma; 5827 5828 ath_tdma_bintvalsetup(sc, ts); 5829 if (changed & TDMA_UPDATE_SLOTLEN) 5830 ath_wme_update(ic); 5831 5832 DPRINTF(sc, ATH_DEBUG_TDMA, 5833 "%s: adopt slot %u slotcnt %u slotlen %u us " 5834 "bintval %u TU\n", __func__, 5835 ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen, 5836 sc->sc_tdmabintval); 5837 5838 /* XXX right? */ 5839 ath_hal_intrset(ah, sc->sc_imask); 5840 /* NB: beacon timers programmed below */ 5841 } 5842 5843 /* extend rx timestamp to 64 bits */ 5844 rs = sc->sc_lastrs; 5845 tsf = ath_hal_gettsf64(ah); 5846 rstamp = ath_extend_tsf(rs->rs_tstamp, tsf); 5847 /* 5848 * The rx timestamp is set by the hardware on completing 5849 * reception (at the point where the rx descriptor is DMA'd 5850 * to the host). To find the start of our next slot we 5851 * must adjust this time by the time required to send 5852 * the packet just received. 5853 */ 5854 rix = rt->rateCodeToIndex[rs->rs_rate]; 5855 txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix, 5856 rt->info[rix].shortPreamble); 5857 /* NB: << 9 is to cvt to TU and /2 */ 5858 nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9); 5859 nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD; 5860 5861 /* 5862 * TIMER0 is the h/w's idea of NextTBTT (in TU's). Convert 5863 * to usecs and calculate the difference between what the 5864 * other station thinks and what we have programmed. This 5865 * lets us figure how to adjust our timers to match. The 5866 * adjustments are done by pulling the TSF forward and possibly 5867 * rewriting the beacon timers. 5868 */ 5869 timer0 = ath_hal_getnexttbtt(ah); 5870 tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD+1)) - TU_TO_TSF(timer0)); 5871 5872 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 5873 "tsfdelta %d avg +%d/-%d\n", tsfdelta, 5874 TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam)); 5875 5876 if (tsfdelta < 0) { 5877 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 5878 TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta); 5879 tsfdelta = -tsfdelta % 1024; 5880 nextslottu++; 5881 } else if (tsfdelta > 0) { 5882 TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta); 5883 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 5884 tsfdelta = 1024 - (tsfdelta % 1024); 5885 nextslottu++; 5886 } else { 5887 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 5888 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 5889 } 5890 tudelta = nextslottu - timer0; 5891 5892 /* 5893 * Copy sender's timetstamp into tdma ie so they can 5894 * calculate roundtrip time. We submit a beacon frame 5895 * below after any timer adjustment. The frame goes out 5896 * at the next TBTT so the sender can calculate the 5897 * roundtrip by inspecting the tdma ie in our beacon frame. 5898 * 5899 * NB: This tstamp is subtlely preserved when 5900 * IEEE80211_BEACON_TDMA is marked (e.g. when the 5901 * slot position changes) because ieee80211_add_tdma 5902 * skips over the data. 5903 */ 5904 memcpy(ATH_VAP(vap)->av_boff.bo_tdma + 5905 __offsetof(struct ieee80211_tdma_param, tdma_tstamp), 5906 &ni->ni_tstamp.data, 8); 5907 #if 0 5908 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 5909 "tsf %llu nextslot %llu (%d, %d) nextslottu %u timer0 %u (%d)\n", 5910 (unsigned long long) tsf, (unsigned long long) nextslot, 5911 (int)(nextslot - tsf), tsfdelta, 5912 nextslottu, timer0, tudelta); 5913 #endif 5914 /* 5915 * Adjust the beacon timers only when pulling them forward 5916 * or when going back by less than the beacon interval. 5917 * Negative jumps larger than the beacon interval seem to 5918 * cause the timers to stop and generally cause instability. 5919 * This basically filters out jumps due to missed beacons. 5920 */ 5921 if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) { 5922 ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval); 5923 sc->sc_stats.ast_tdma_timers++; 5924 } 5925 if (tsfdelta > 0) { 5926 ath_hal_adjusttsf(ah, tsfdelta); 5927 sc->sc_stats.ast_tdma_tsf++; 5928 } 5929 ath_tdma_beacon_send(sc, vap); /* prepare response */ 5930 #undef TU_TO_TSF 5931 #undef TSF_TO_TU 5932 } 5933 5934 /* 5935 * Transmit a beacon frame at SWBA. Dynamic updates 5936 * to the frame contents are done as needed. 5937 */ 5938 static void 5939 ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap) 5940 { 5941 struct ath_hal *ah = sc->sc_ah; 5942 struct ath_buf *bf; 5943 int otherant; 5944 5945 /* 5946 * Check if the previous beacon has gone out. If 5947 * not don't try to post another, skip this period 5948 * and wait for the next. Missed beacons indicate 5949 * a problem and should not occur. If we miss too 5950 * many consecutive beacons reset the device. 5951 */ 5952 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 5953 sc->sc_bmisscount++; 5954 DPRINTF(sc, ATH_DEBUG_BEACON, 5955 "%s: missed %u consecutive beacons\n", 5956 __func__, sc->sc_bmisscount); 5957 if (sc->sc_bmisscount >= ath_bstuck_threshold) 5958 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 5959 return; 5960 } 5961 if (sc->sc_bmisscount != 0) { 5962 DPRINTF(sc, ATH_DEBUG_BEACON, 5963 "%s: resume beacon xmit after %u misses\n", 5964 __func__, sc->sc_bmisscount); 5965 sc->sc_bmisscount = 0; 5966 } 5967 5968 /* 5969 * Check recent per-antenna transmit statistics and flip 5970 * the default antenna if noticeably more frames went out 5971 * on the non-default antenna. 5972 * XXX assumes 2 anntenae 5973 */ 5974 if (!sc->sc_diversity) { 5975 otherant = sc->sc_defant & 1 ? 2 : 1; 5976 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 5977 ath_setdefantenna(sc, otherant); 5978 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 5979 } 5980 5981 bf = ath_beacon_generate(sc, vap); 5982 if (bf != NULL) { 5983 /* 5984 * Stop any current dma and put the new frame on the queue. 5985 * This should never fail since we check above that no frames 5986 * are still pending on the queue. 5987 */ 5988 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 5989 DPRINTF(sc, ATH_DEBUG_ANY, 5990 "%s: beacon queue %u did not stop?\n", 5991 __func__, sc->sc_bhalq); 5992 /* NB: the HAL still stops DMA, so proceed */ 5993 } 5994 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 5995 ath_hal_txstart(ah, sc->sc_bhalq); 5996 5997 sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */ 5998 5999 /* 6000 * Record local TSF for our last send for use 6001 * in arbitrating slot collisions. 6002 */ 6003 vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah); 6004 } 6005 } 6006 #endif /* IEEE80211_SUPPORT_TDMA */ 6007 6008