1 /* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 27 #include "ar9002/ar9280.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 31 #include "ar9002/ar9280v1.ini" 32 #include "ar9002/ar9280v2.ini" 33 34 static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 35 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 36 .calNumSamples = MIN_CAL_SAMPLES, 37 .calCountMax = PER_MAX_LOG_COUNT, 38 .calCollect = ar5416IQCalCollect, 39 .calPostProc = ar5416IQCalibration 40 }; 41 static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 42 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 43 .calNumSamples = MIN_CAL_SAMPLES, 44 .calCountMax = PER_MIN_LOG_COUNT, 45 .calCollect = ar5416AdcGainCalCollect, 46 .calPostProc = ar5416AdcGainCalibration 47 }; 48 static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 49 .calName = "ADC DC", .calType = ADC_DC_CAL, 50 .calNumSamples = MIN_CAL_SAMPLES, 51 .calCountMax = PER_MIN_LOG_COUNT, 52 .calCollect = ar5416AdcDcCalCollect, 53 .calPostProc = ar5416AdcDcCalibration 54 }; 55 static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 56 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 57 .calNumSamples = MIN_CAL_SAMPLES, 58 .calCountMax = INIT_LOG_COUNT, 59 .calCollect = ar5416AdcDcCalCollect, 60 .calPostProc = ar5416AdcDcCalibration 61 }; 62 63 static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 64 static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 65 static void ar9280WriteIni(struct ath_hal *ah, 66 const struct ieee80211_channel *chan); 67 68 static void 69 ar9280AniSetup(struct ath_hal *ah) 70 { 71 /* 72 * These are the parameters from the AR5416 ANI code; 73 * they likely need quite a bit of adjustment for the 74 * AR9280. 75 */ 76 static const struct ar5212AniParams aniparams = { 77 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 78 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 79 .coarseHigh = { -14, -14, -14, -14, -12 }, 80 .coarseLow = { -64, -64, -64, -64, -70 }, 81 .firpwr = { -78, -78, -78, -78, -80 }, 82 .maxSpurImmunityLevel = 2, 83 .cycPwrThr1 = { 2, 4, 6 }, 84 .maxFirstepLevel = 2, /* levels 0..2 */ 85 .firstep = { 0, 4, 8 }, 86 .ofdmTrigHigh = 500, 87 .ofdmTrigLow = 200, 88 .cckTrigHigh = 200, 89 .cckTrigLow = 100, 90 .rssiThrHigh = 40, 91 .rssiThrLow = 7, 92 .period = 100, 93 }; 94 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 95 AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL; 96 97 /* NB: ANI is not enabled yet */ 98 ar5416AniAttach(ah, &aniparams, &aniparams, AH_FALSE); 99 } 100 101 /* 102 * Attach for an AR9280 part. 103 */ 104 static struct ath_hal * 105 ar9280Attach(uint16_t devid, HAL_SOFTC sc, 106 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 107 HAL_STATUS *status) 108 { 109 struct ath_hal_9280 *ahp9280; 110 struct ath_hal_5212 *ahp; 111 struct ath_hal *ah; 112 uint32_t val; 113 HAL_STATUS ecode; 114 HAL_BOOL rfStatus; 115 116 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 117 __func__, sc, (void*) st, (void*) sh); 118 119 /* NB: memory is returned zero'd */ 120 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 121 if (ahp9280 == AH_NULL) { 122 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 123 "%s: cannot allocate memory for state block\n", __func__); 124 *status = HAL_ENOMEM; 125 return AH_NULL; 126 } 127 ahp = AH5212(ahp9280); 128 ah = &ahp->ah_priv.h; 129 130 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 131 132 /* XXX override with 9280 specific state */ 133 /* override 5416 methods for our needs */ 134 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 135 ah->ah_configPCIE = ar9280ConfigPCIE; 136 137 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 138 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 139 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 140 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 141 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 142 143 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 144 AH5416(ah)->ah_writeIni = ar9280WriteIni; 145 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 146 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 147 148 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 149 /* reset chip */ 150 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 151 __func__); 152 ecode = HAL_EIO; 153 goto bad; 154 } 155 156 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 157 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 158 __func__); 159 ecode = HAL_EIO; 160 goto bad; 161 } 162 /* Read Revisions from Chips before taking out of reset */ 163 val = OS_REG_READ(ah, AR_SREV); 164 HALDEBUG(ah, HAL_DEBUG_ATTACH, 165 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 166 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 167 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 168 /* NB: include chip type to differentiate from pre-Sowl versions */ 169 AH_PRIVATE(ah)->ah_macVersion = 170 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 171 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 172 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 173 174 /* setup common ini data; rf backends handle remainder */ 175 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 176 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 177 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 178 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 179 ar9280PciePhy_clkreq_always_on_L1_v2, 2); 180 HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 181 ar9280Modes_fast_clock_v2, 3); 182 } else { 183 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 184 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 185 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 186 ar9280PciePhy_v1, 2); 187 } 188 ar5416AttachPCIE(ah); 189 190 ecode = ath_hal_v14EepromAttach(ah); 191 if (ecode != HAL_OK) 192 goto bad; 193 194 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 195 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 196 ecode = HAL_EIO; 197 goto bad; 198 } 199 200 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 201 202 if (!ar5212ChipTest(ah)) { 203 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 204 __func__); 205 ecode = HAL_ESELFTEST; 206 goto bad; 207 } 208 209 /* 210 * Set correct Baseband to analog shift 211 * setting to access analog chips. 212 */ 213 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 214 215 /* Read Radio Chip Rev Extract */ 216 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 217 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 218 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 219 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 220 break; 221 default: 222 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 223 AH_PRIVATE(ah)->ah_analog5GhzRev = 224 AR_RAD5133_SREV_MAJOR; 225 break; 226 } 227 #ifdef AH_DEBUG 228 HALDEBUG(ah, HAL_DEBUG_ANY, 229 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 230 "this driver\n", __func__, 231 AH_PRIVATE(ah)->ah_analog5GhzRev); 232 ecode = HAL_ENOTSUPP; 233 goto bad; 234 #endif 235 } 236 rfStatus = ar9280RfAttach(ah, &ecode); 237 if (!rfStatus) { 238 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 239 __func__, ecode); 240 goto bad; 241 } 242 243 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 244 /* setup rxgain table */ 245 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 246 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 247 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 248 ar9280Modes_backoff_13db_rxgain_v2, 6); 249 break; 250 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 251 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 252 ar9280Modes_backoff_23db_rxgain_v2, 6); 253 break; 254 case AR5416_EEP_RXGAIN_ORIG: 255 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 256 ar9280Modes_original_rxgain_v2, 6); 257 break; 258 default: 259 HALASSERT(AH_FALSE); 260 goto bad; /* XXX ? try to continue */ 261 } 262 } 263 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 264 /* setp txgain table */ 265 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 266 case AR5416_EEP_TXGAIN_HIGH_POWER: 267 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 268 ar9280Modes_high_power_tx_gain_v2, 6); 269 break; 270 case AR5416_EEP_TXGAIN_ORIG: 271 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 272 ar9280Modes_original_tx_gain_v2, 6); 273 break; 274 default: 275 HALASSERT(AH_FALSE); 276 goto bad; /* XXX ? try to continue */ 277 } 278 } 279 280 /* 281 * Got everything we need now to setup the capabilities. 282 */ 283 if (!ar9280FillCapabilityInfo(ah)) { 284 ecode = HAL_EEREAD; 285 goto bad; 286 } 287 288 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 289 if (ecode != HAL_OK) { 290 HALDEBUG(ah, HAL_DEBUG_ANY, 291 "%s: error getting mac address from EEPROM\n", __func__); 292 goto bad; 293 } 294 /* XXX How about the serial number ? */ 295 /* Read Reg Domain */ 296 AH_PRIVATE(ah)->ah_currentRD = 297 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 298 299 /* 300 * ah_miscMode is populated by ar5416FillCapabilityInfo() 301 * starting from griffin. Set here to make sure that 302 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 303 * placed into hardware. 304 */ 305 if (ahp->ah_miscMode != 0) 306 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 307 308 ar9280AniSetup(ah); /* Anti Noise Immunity */ 309 310 /* Setup noise floor min/max/nominal values */ 311 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 312 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 313 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 314 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 315 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 316 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 317 318 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 319 320 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 321 322 return ah; 323 bad: 324 if (ah != AH_NULL) 325 ah->ah_detach(ah); 326 if (status) 327 *status = ecode; 328 return AH_NULL; 329 } 330 331 static void 332 ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 333 { 334 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 335 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 336 OS_DELAY(1000); 337 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 338 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 339 } 340 } 341 342 static void 343 ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 344 { 345 u_int modesIndex, freqIndex; 346 int regWrites = 0; 347 348 /* Setup the indices for the next set of register array writes */ 349 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 350 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 351 freqIndex = 2; 352 if (IEEE80211_IS_CHAN_HT40(chan)) 353 modesIndex = 3; 354 else if (IEEE80211_IS_CHAN_108G(chan)) 355 modesIndex = 5; 356 else 357 modesIndex = 4; 358 } else { 359 freqIndex = 1; 360 if (IEEE80211_IS_CHAN_HT40(chan) || 361 IEEE80211_IS_CHAN_TURBO(chan)) 362 modesIndex = 2; 363 else 364 modesIndex = 1; 365 } 366 367 /* Set correct Baseband to analog shift setting to access analog chips. */ 368 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 369 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 370 371 /* XXX Merlin ini fixups */ 372 /* XXX Merlin 100us delay for shift registers */ 373 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 374 modesIndex, regWrites); 375 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 376 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 377 modesIndex, regWrites); 378 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 379 modesIndex, regWrites); 380 } 381 /* XXX Merlin 100us delay for shift registers */ 382 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 383 1, regWrites); 384 385 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 386 /* 5GHz channels w/ Fast Clock use different modal values */ 387 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 388 modesIndex, regWrites); 389 } 390 } 391 392 #define AR_BASE_FREQ_2GHZ 2300 393 #define AR_BASE_FREQ_5GHZ 4900 394 #define AR_SPUR_FEEQ_BOUND_HT40 19 395 #define AR_SPUR_FEEQ_BOUND_HT20 10 396 397 void 398 ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 399 { 400 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 401 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 402 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 403 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 404 static int inc[4] = { 0, 100, 0, 0 }; 405 406 int bb_spur = AR_NO_SPUR; 407 int freq; 408 int bin, cur_bin; 409 int bb_spur_off, spur_subchannel_sd; 410 int spur_freq_sd; 411 int spur_delta_phase; 412 int denominator; 413 int upper, lower, cur_vit_mask; 414 int tmp, newVal; 415 int i; 416 CHAN_CENTERS centers; 417 418 int8_t mask_m[123]; 419 int8_t mask_p[123]; 420 int8_t mask_amt; 421 int tmp_mask; 422 int cur_bb_spur; 423 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 424 425 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 426 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 427 428 ar5416GetChannelCenters(ah, chan, ¢ers); 429 freq = centers.synth_center; 430 431 /* 432 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 433 * otherwise spur is out-of-band and can be ignored. 434 */ 435 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 436 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 437 /* Get actual spur freq in MHz from EEPROM read value */ 438 if (is2GHz) { 439 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 440 } else { 441 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 442 } 443 444 if (AR_NO_SPUR == cur_bb_spur) 445 break; 446 cur_bb_spur = cur_bb_spur - freq; 447 448 if (IEEE80211_IS_CHAN_HT40(chan)) { 449 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 450 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 451 bb_spur = cur_bb_spur; 452 break; 453 } 454 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 455 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 456 bb_spur = cur_bb_spur; 457 break; 458 } 459 } 460 461 if (AR_NO_SPUR == bb_spur) { 462 #if 1 463 /* 464 * MRC CCK can interfere with beacon detection and cause deaf/mute. 465 * Disable MRC CCK for now. 466 */ 467 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 468 #else 469 /* Enable MRC CCK if no spur is found in this channel. */ 470 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 471 #endif 472 return; 473 } else { 474 /* 475 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 476 * is found in this channel. 477 */ 478 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 479 } 480 481 bin = bb_spur * 320; 482 483 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 484 485 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 486 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 487 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 488 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 489 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 490 491 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 492 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 493 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 494 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 495 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 496 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 497 498 /* Pick control or extn channel to cancel the spur */ 499 if (IEEE80211_IS_CHAN_HT40(chan)) { 500 if (bb_spur < 0) { 501 spur_subchannel_sd = 1; 502 bb_spur_off = bb_spur + 10; 503 } else { 504 spur_subchannel_sd = 0; 505 bb_spur_off = bb_spur - 10; 506 } 507 } else { 508 spur_subchannel_sd = 0; 509 bb_spur_off = bb_spur; 510 } 511 512 /* 513 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 514 * /80 for dyn2040. 515 */ 516 if (IEEE80211_IS_CHAN_HT40(chan)) 517 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 518 else 519 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 520 521 /* 522 * in 11A mode the denominator of spur_freq_sd should be 40 and 523 * it should be 44 in 11G 524 */ 525 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 526 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 527 528 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 529 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 530 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 531 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 532 533 /* Choose to cancel between control and extension channels */ 534 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 535 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 536 537 /* 538 * ============================================ 539 * Set Pilot and Channel Masks 540 * 541 * pilot mask 1 [31:0] = +6..-26, no 0 bin 542 * pilot mask 2 [19:0] = +26..+7 543 * 544 * channel mask 1 [31:0] = +6..-26, no 0 bin 545 * channel mask 2 [19:0] = +26..+7 546 */ 547 cur_bin = -6000; 548 upper = bin + 100; 549 lower = bin - 100; 550 551 for (i = 0; i < 4; i++) { 552 int pilot_mask = 0; 553 int chan_mask = 0; 554 int bp = 0; 555 for (bp = 0; bp < 30; bp++) { 556 if ((cur_bin > lower) && (cur_bin < upper)) { 557 pilot_mask = pilot_mask | 0x1 << bp; 558 chan_mask = chan_mask | 0x1 << bp; 559 } 560 cur_bin += 100; 561 } 562 cur_bin += inc[i]; 563 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 564 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 565 } 566 567 /* ================================================= 568 * viterbi mask 1 based on channel magnitude 569 * four levels 0-3 570 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 571 * [1 2 2 1] for -9.6 or [1 2 1] for +16 572 * - enable_mask_ppm, all bins move with freq 573 * 574 * - mask_select, 8 bits for rates (reg 67,0x990c) 575 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 576 * choose which mask to use mask or mask2 577 */ 578 579 /* 580 * viterbi mask 2 2nd set for per data rate puncturing 581 * four levels 0-3 582 * - mask_select, 8 bits for rates (reg 67) 583 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 584 * [1 2 2 1] for -9.6 or [1 2 1] for +16 585 */ 586 cur_vit_mask = 6100; 587 upper = bin + 120; 588 lower = bin - 120; 589 590 for (i = 0; i < 123; i++) { 591 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 592 if ((abs(cur_vit_mask - bin)) < 75) { 593 mask_amt = 1; 594 } else { 595 mask_amt = 0; 596 } 597 if (cur_vit_mask < 0) { 598 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 599 } else { 600 mask_p[cur_vit_mask / 100] = mask_amt; 601 } 602 } 603 cur_vit_mask -= 100; 604 } 605 606 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 607 | (mask_m[48] << 26) | (mask_m[49] << 24) 608 | (mask_m[50] << 22) | (mask_m[51] << 20) 609 | (mask_m[52] << 18) | (mask_m[53] << 16) 610 | (mask_m[54] << 14) | (mask_m[55] << 12) 611 | (mask_m[56] << 10) | (mask_m[57] << 8) 612 | (mask_m[58] << 6) | (mask_m[59] << 4) 613 | (mask_m[60] << 2) | (mask_m[61] << 0); 614 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 615 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 616 617 tmp_mask = (mask_m[31] << 28) 618 | (mask_m[32] << 26) | (mask_m[33] << 24) 619 | (mask_m[34] << 22) | (mask_m[35] << 20) 620 | (mask_m[36] << 18) | (mask_m[37] << 16) 621 | (mask_m[48] << 14) | (mask_m[39] << 12) 622 | (mask_m[40] << 10) | (mask_m[41] << 8) 623 | (mask_m[42] << 6) | (mask_m[43] << 4) 624 | (mask_m[44] << 2) | (mask_m[45] << 0); 625 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 626 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 627 628 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 629 | (mask_m[18] << 26) | (mask_m[18] << 24) 630 | (mask_m[20] << 22) | (mask_m[20] << 20) 631 | (mask_m[22] << 18) | (mask_m[22] << 16) 632 | (mask_m[24] << 14) | (mask_m[24] << 12) 633 | (mask_m[25] << 10) | (mask_m[26] << 8) 634 | (mask_m[27] << 6) | (mask_m[28] << 4) 635 | (mask_m[29] << 2) | (mask_m[30] << 0); 636 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 637 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 638 639 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 640 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 641 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 642 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 643 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 644 | (mask_m[10] << 10) | (mask_m[11] << 8) 645 | (mask_m[12] << 6) | (mask_m[13] << 4) 646 | (mask_m[14] << 2) | (mask_m[15] << 0); 647 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 648 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 649 650 tmp_mask = (mask_p[15] << 28) 651 | (mask_p[14] << 26) | (mask_p[13] << 24) 652 | (mask_p[12] << 22) | (mask_p[11] << 20) 653 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 654 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 655 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 656 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 657 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 658 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 659 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 660 661 tmp_mask = (mask_p[30] << 28) 662 | (mask_p[29] << 26) | (mask_p[28] << 24) 663 | (mask_p[27] << 22) | (mask_p[26] << 20) 664 | (mask_p[25] << 18) | (mask_p[24] << 16) 665 | (mask_p[23] << 14) | (mask_p[22] << 12) 666 | (mask_p[21] << 10) | (mask_p[20] << 8) 667 | (mask_p[19] << 6) | (mask_p[18] << 4) 668 | (mask_p[17] << 2) | (mask_p[16] << 0); 669 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 670 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 671 672 tmp_mask = (mask_p[45] << 28) 673 | (mask_p[44] << 26) | (mask_p[43] << 24) 674 | (mask_p[42] << 22) | (mask_p[41] << 20) 675 | (mask_p[40] << 18) | (mask_p[39] << 16) 676 | (mask_p[38] << 14) | (mask_p[37] << 12) 677 | (mask_p[36] << 10) | (mask_p[35] << 8) 678 | (mask_p[34] << 6) | (mask_p[33] << 4) 679 | (mask_p[32] << 2) | (mask_p[31] << 0); 680 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 681 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 682 683 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 684 | (mask_p[59] << 26) | (mask_p[58] << 24) 685 | (mask_p[57] << 22) | (mask_p[56] << 20) 686 | (mask_p[55] << 18) | (mask_p[54] << 16) 687 | (mask_p[53] << 14) | (mask_p[52] << 12) 688 | (mask_p[51] << 10) | (mask_p[50] << 8) 689 | (mask_p[49] << 6) | (mask_p[48] << 4) 690 | (mask_p[47] << 2) | (mask_p[46] << 0); 691 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 692 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 693 } 694 695 /* 696 * Fill all software cached or static hardware state information. 697 * Return failure if capabilities are to come from EEPROM and 698 * cannot be read. 699 */ 700 static HAL_BOOL 701 ar9280FillCapabilityInfo(struct ath_hal *ah) 702 { 703 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 704 705 if (!ar5416FillCapabilityInfo(ah)) 706 return AH_FALSE; 707 pCap->halNumGpioPins = 10; 708 pCap->halWowSupport = AH_TRUE; 709 pCap->halWowMatchPatternExact = AH_TRUE; 710 #if 0 711 pCap->halWowMatchPatternDword = AH_TRUE; 712 #endif 713 /* AR9280 is a 2x2 stream device */ 714 pCap->halTxStreams = 2; 715 pCap->halRxStreams = 2; 716 717 pCap->halCSTSupport = AH_TRUE; 718 pCap->halRifsRxSupport = AH_TRUE; 719 pCap->halRifsTxSupport = AH_TRUE; 720 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 721 pCap->halExtChanDfsSupport = AH_TRUE; 722 #if 0 723 /* XXX bluetooth */ 724 pCap->halBtCoexSupport = AH_TRUE; 725 #endif 726 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 727 pCap->hal4kbSplitTransSupport = AH_FALSE; 728 pCap->halRxStbcSupport = 1; 729 pCap->halTxStbcSupport = 1; 730 731 return AH_TRUE; 732 } 733 734 /* 735 * This has been disabled - having the HAL flip chainmasks on/off 736 * when attempting to implement 11n disrupts things. For now, just 737 * leave this flipped off and worry about implementing TX diversity 738 * for legacy and MCS0-7 when 11n is fully functioning. 739 */ 740 HAL_BOOL 741 ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 742 { 743 #define ANTENNA0_CHAINMASK 0x1 744 #define ANTENNA1_CHAINMASK 0x2 745 #if 0 746 struct ath_hal_5416 *ahp = AH5416(ah); 747 748 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 749 switch (settings) { 750 case HAL_ANT_FIXED_A: 751 /* Enable first antenna only */ 752 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 753 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 754 break; 755 case HAL_ANT_FIXED_B: 756 /* Enable second antenna only, after checking capability */ 757 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 758 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 759 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 760 break; 761 case HAL_ANT_VARIABLE: 762 /* Restore original chainmask settings */ 763 /* XXX */ 764 ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 765 ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 766 break; 767 } 768 769 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 770 __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 771 772 #endif 773 return AH_TRUE; 774 #undef ANTENNA0_CHAINMASK 775 #undef ANTENNA1_CHAINMASK 776 } 777 778 static const char* 779 ar9280Probe(uint16_t vendorid, uint16_t devid) 780 { 781 if (vendorid == ATHEROS_VENDOR_ID && 782 (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)) 783 return "Atheros 9280"; 784 return AH_NULL; 785 } 786 AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 787