1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" 26 27 #include "ar5416/ar5416.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 31 /* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 32 #define EEP_MINOR(_ah) \ 33 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 34 #define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 35 #define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 36 37 /* Additional Time delay to wait after activiting the Base band */ 38 #define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 39 #define PLL_SETTLE_DELAY 300 /* 300 usec */ 40 #define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 41 42 static void ar5416InitDMA(struct ath_hal *ah); 43 static void ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *); 44 static void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode); 45 static void ar5416InitQoS(struct ath_hal *ah); 46 static void ar5416InitUserSettings(struct ath_hal *ah); 47 static void ar5416UpdateChainMasks(struct ath_hal *ah, HAL_BOOL is_ht); 48 49 #if 0 50 static HAL_BOOL ar5416ChannelChange(struct ath_hal *, const struct ieee80211_channel *); 51 #endif 52 static void ar5416SetDeltaSlope(struct ath_hal *, const struct ieee80211_channel *); 53 54 static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah); 55 static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type); 56 static void ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan); 57 static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah, 58 struct ar5416eeprom *pEepData, 59 const struct ieee80211_channel *chan, int16_t *ratesArray, 60 uint16_t cfgCtl, uint16_t AntennaReduction, 61 uint16_t twiceMaxRegulatoryPower, 62 uint16_t powerLimit); 63 static HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah, 64 struct ar5416eeprom *pEepData, 65 const struct ieee80211_channel *chan, 66 int16_t *pTxPowerIndexOffset); 67 static uint16_t ar5416GetMaxEdgePower(uint16_t freq, 68 CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz); 69 70 static int16_t interpolate(uint16_t target, uint16_t srcLeft, 71 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 72 static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan); 73 static void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, 74 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ *pRawDataSet, 75 uint8_t * bChans, uint16_t availPiers, 76 uint16_t tPdGainOverlap, int16_t *pMinCalPower, 77 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, 78 uint16_t numXpdGains); 79 static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList, 80 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 81 static HAL_BOOL ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 82 uint8_t *pPwrList, uint8_t *pVpdList, 83 uint16_t numIntercepts, uint8_t *pRetVpdList); 84 85 /* 86 * Places the device in and out of reset and then places sane 87 * values in the registers based on EEPROM config, initialization 88 * vectors (as determined by the mode), and station configuration 89 * 90 * bChannelChange is used to preserve DMA/PCU registers across 91 * a HW Reset during channel change. 92 */ 93 HAL_BOOL 94 ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode, 95 struct ieee80211_channel *chan, 96 HAL_BOOL bChannelChange, HAL_STATUS *status) 97 { 98 #define N(a) (sizeof (a) / sizeof (a[0])) 99 #define FAIL(_code) do { ecode = _code; goto bad; } while (0) 100 struct ath_hal_5212 *ahp = AH5212(ah); 101 HAL_CHANNEL_INTERNAL *ichan; 102 uint32_t saveDefAntenna, saveLedState; 103 uint32_t macStaId1; 104 uint16_t rfXpdGain[2]; 105 HAL_STATUS ecode; 106 uint32_t powerVal, rssiThrReg; 107 uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow; 108 int i; 109 110 OS_MARK(ah, AH_MARK_RESET, bChannelChange); 111 112 /* Bring out of sleep mode */ 113 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 114 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n", 115 __func__); 116 FAIL(HAL_EIO); 117 } 118 119 /* 120 * Map public channel to private. 121 */ 122 ichan = ath_hal_checkchannel(ah, chan); 123 if (ichan == AH_NULL) 124 FAIL(HAL_EINVAL); 125 switch (opmode) { 126 case HAL_M_STA: 127 case HAL_M_IBSS: 128 case HAL_M_HOSTAP: 129 case HAL_M_MONITOR: 130 break; 131 default: 132 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 133 __func__, opmode); 134 FAIL(HAL_EINVAL); 135 break; 136 } 137 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 138 139 /* XXX Turn on fast channel change for 5416 */ 140 /* 141 * Preserve the bmiss rssi threshold and count threshold 142 * across resets 143 */ 144 rssiThrReg = OS_REG_READ(ah, AR_RSSI_THR); 145 /* If reg is zero, first time thru set to default val */ 146 if (rssiThrReg == 0) 147 rssiThrReg = INIT_RSSI_THR; 148 149 /* 150 * Preserve the antenna on a channel change 151 */ 152 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 153 if (saveDefAntenna == 0) /* XXX magic constants */ 154 saveDefAntenna = 1; 155 156 /* Save hardware flag before chip reset clears the register */ 157 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 158 (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT); 159 160 /* Save led state from pci config register */ 161 saveLedState = OS_REG_READ(ah, AR_MAC_LED) & 162 (AR_MAC_LED_ASSOC | AR_MAC_LED_MODE | 163 AR_MAC_LED_BLINK_THRESH_SEL | AR_MAC_LED_BLINK_SLOW); 164 165 if (!ar5416ChipReset(ah, chan)) { 166 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 167 FAIL(HAL_EIO); 168 } 169 170 /* Restore bmiss rssi & count thresholds */ 171 OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg); 172 173 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 174 if (AR_SREV_MERLIN_10_OR_LATER(ah)) 175 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 176 177 if (AR_SREV_KITE(ah)) { 178 uint32_t val; 179 val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 180 val &= ~AR_PHY_RIFS_INIT_DELAY; 181 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 182 } 183 184 AH5416(ah)->ah_writeIni(ah, chan); 185 186 /* Setup 11n MAC/Phy mode registers */ 187 ar5416Set11nRegs(ah, chan); 188 189 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 190 191 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_DAG_CTRLCCK=0x%x\n", 192 __func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK)); 193 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_ADC_CTL=0x%x\n", 194 __func__, OS_REG_READ(ah,AR_PHY_ADC_CTL)); 195 196 /* Set the mute mask to the correct default */ 197 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) 198 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); 199 200 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) { 201 /* Clear reg to alllow RX_CLEAR line debug */ 202 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); 203 } 204 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) { 205 #ifdef notyet 206 /* Enable burst prefetch for the data queues */ 207 OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... ); 208 /* Enable double-buffering */ 209 OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS); 210 #endif 211 } 212 213 /* 214 * Setup ah_tx_chainmask / ah_rx_chainmask before we fiddle 215 * with enabling the TX/RX radio chains. 216 */ 217 ar5416UpdateChainMasks(ah, IEEE80211_IS_CHAN_HT(chan)); 218 /* 219 * This routine swaps the analog chains - it should be done 220 * before any radio register twiddling is done. 221 */ 222 ar5416InitChainMasks(ah); 223 224 /* Setup the transmit power values. */ 225 if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) { 226 HALDEBUG(ah, HAL_DEBUG_ANY, 227 "%s: error init'ing transmit power\n", __func__); 228 FAIL(HAL_EIO); 229 } 230 231 /* Write the analog registers */ 232 if (!ahp->ah_rfHal->setRfRegs(ah, chan, 233 IEEE80211_IS_CHAN_2GHZ(chan) ? 2: 1, rfXpdGain)) { 234 HALDEBUG(ah, HAL_DEBUG_ANY, 235 "%s: ar5212SetRfRegs failed\n", __func__); 236 FAIL(HAL_EIO); 237 } 238 239 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 240 if (IEEE80211_IS_CHAN_OFDM(chan)|| IEEE80211_IS_CHAN_HT(chan)) 241 ar5416SetDeltaSlope(ah, chan); 242 243 AH5416(ah)->ah_spurMitigate(ah, chan); 244 245 /* Setup board specific options for EEPROM version 3 */ 246 if (!ah->ah_setBoardValues(ah, chan)) { 247 HALDEBUG(ah, HAL_DEBUG_ANY, 248 "%s: error setting board options\n", __func__); 249 FAIL(HAL_EIO); 250 } 251 252 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 253 254 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 255 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 256 | macStaId1 257 | AR_STA_ID1_RTS_USE_DEF 258 | ahp->ah_staId1Defaults 259 ); 260 ar5212SetOperatingMode(ah, opmode); 261 262 /* Set Venice BSSID mask according to current state */ 263 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); 264 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); 265 266 /* Restore previous led state */ 267 OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | saveLedState); 268 269 /* Restore previous antenna */ 270 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 271 272 /* then our BSSID */ 273 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 274 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); 275 276 /* Restore bmiss rssi & count thresholds */ 277 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 278 279 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 280 281 if (!ar5212SetChannel(ah, chan)) 282 FAIL(HAL_EIO); 283 284 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 285 286 /* Set 1:1 QCU to DCU mapping for all queues */ 287 for (i = 0; i < AR_NUM_DCU; i++) 288 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 289 290 ahp->ah_intrTxqs = 0; 291 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) 292 ar5212ResetTxQueue(ah, i); 293 294 ar5416InitIMR(ah, opmode); 295 ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 296 ar5416InitQoS(ah); 297 ar5416InitUserSettings(ah); 298 299 /* 300 * disable seq number generation in hw 301 */ 302 OS_REG_WRITE(ah, AR_STA_ID1, 303 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 304 305 ar5416InitDMA(ah); 306 307 /* 308 * program OBS bus to see MAC interrupts 309 */ 310 OS_REG_WRITE(ah, AR_OBS, 8); 311 312 #ifdef AR5416_INT_MITIGATION 313 OS_REG_WRITE(ah, AR_MIRT, 0); 314 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 315 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 316 #endif 317 318 ar5416InitBB(ah, chan); 319 320 /* Setup compression registers */ 321 ar5212SetCompRegs(ah); /* XXX not needed? */ 322 323 /* 324 * 5416 baseband will check the per rate power table 325 * and select the lower of the two 326 */ 327 ackTpcPow = 63; 328 ctsTpcPow = 63; 329 chirpTpcPow = 63; 330 powerVal = SM(ackTpcPow, AR_TPC_ACK) | 331 SM(ctsTpcPow, AR_TPC_CTS) | 332 SM(chirpTpcPow, AR_TPC_CHIRP); 333 OS_REG_WRITE(ah, AR_TPC, powerVal); 334 335 if (!ar5416InitCal(ah, chan)) 336 FAIL(HAL_ESELFTEST); 337 338 ar5416RestoreChainMask(ah); 339 340 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 341 342 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 343 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 344 345 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 346 347 OS_MARK(ah, AH_MARK_RESET_DONE, 0); 348 349 return AH_TRUE; 350 bad: 351 OS_MARK(ah, AH_MARK_RESET_DONE, ecode); 352 if (status != AH_NULL) 353 *status = ecode; 354 return AH_FALSE; 355 #undef FAIL 356 #undef N 357 } 358 359 #if 0 360 /* 361 * This channel change evaluates whether the selected hardware can 362 * perform a synthesizer-only channel change (no reset). If the 363 * TX is not stopped, or the RFBus cannot be granted in the given 364 * time, the function returns false as a reset is necessary 365 */ 366 HAL_BOOL 367 ar5416ChannelChange(struct ath_hal *ah, const structu ieee80211_channel *chan) 368 { 369 uint32_t ulCount; 370 uint32_t data, synthDelay, qnum; 371 uint16_t rfXpdGain[4]; 372 struct ath_hal_5212 *ahp = AH5212(ah); 373 HAL_CHANNEL_INTERNAL *ichan; 374 375 /* 376 * Map public channel to private. 377 */ 378 ichan = ath_hal_checkchannel(ah, chan); 379 380 /* TX must be stopped or RF Bus grant will not work */ 381 for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) { 382 if (ar5212NumTxPending(ah, qnum)) { 383 HALDEBUG(ah, HAL_DEBUG_ANY, 384 "%s: frames pending on queue %d\n", __func__, qnum); 385 return AH_FALSE; 386 } 387 } 388 389 /* 390 * Kill last Baseband Rx Frame - Request analog bus grant 391 */ 392 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); 393 if (!ath_hal_wait(ah, AR_PHY_RFBUS_GNT, AR_PHY_RFBUS_GRANT_EN, AR_PHY_RFBUS_GRANT_EN)) { 394 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: could not kill baseband rx\n", 395 __func__); 396 return AH_FALSE; 397 } 398 399 ar5416Set11nRegs(ah, chan); /* NB: setup 5416-specific regs */ 400 401 /* Change the synth */ 402 if (!ar5212SetChannel(ah, chan)) 403 return AH_FALSE; 404 405 /* Setup the transmit power values. */ 406 if (!ar5416SetTransmitPower(ah, chan, rfXpdGain)) { 407 HALDEBUG(ah, HAL_DEBUG_ANY, 408 "%s: error init'ing transmit power\n", __func__); 409 return AH_FALSE; 410 } 411 412 /* 413 * Wait for the frequency synth to settle (synth goes on 414 * via PHY_ACTIVE_EN). Read the phy active delay register. 415 * Value is in 100ns increments. 416 */ 417 data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 418 if (IS_CHAN_CCK(ichan)) { 419 synthDelay = (4 * data) / 22; 420 } else { 421 synthDelay = data / 10; 422 } 423 424 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 425 426 /* Release the RFBus Grant */ 427 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 428 429 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 430 if (IEEE80211_IS_CHAN_OFDM(ichan)|| IEEE80211_IS_CHAN_HT(chan)) { 431 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3); 432 ar5212SetSpurMitigation(ah, chan); 433 ar5416SetDeltaSlope(ah, chan); 434 } 435 436 /* XXX spur mitigation for Melin */ 437 438 if (!IEEE80211_IS_CHAN_DFS(chan)) 439 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 440 441 ichan->channel_time = 0; 442 ichan->tsf_last = ar5212GetTsf64(ah); 443 ar5212TxEnable(ah, AH_TRUE); 444 return AH_TRUE; 445 } 446 #endif 447 448 static void 449 ar5416InitDMA(struct ath_hal *ah) 450 { 451 struct ath_hal_5212 *ahp = AH5212(ah); 452 453 /* 454 * set AHB_MODE not to do cacheline prefetches 455 */ 456 OS_REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 457 458 /* 459 * let mac dma reads be in 128 byte chunks 460 */ 461 OS_REG_WRITE(ah, AR_TXCFG, 462 (OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK) | AR_TXCFG_DMASZ_128B); 463 464 /* 465 * let mac dma writes be in 128 byte chunks 466 */ 467 OS_REG_WRITE(ah, AR_RXCFG, 468 (OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B); 469 470 /* restore TX trigger level */ 471 OS_REG_WRITE(ah, AR_TXCFG, 472 (OS_REG_READ(ah, AR_TXCFG) &~ AR_FTRIG) | 473 SM(ahp->ah_txTrigLev, AR_FTRIG)); 474 475 /* 476 * Setup receive FIFO threshold to hold off TX activities 477 */ 478 OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 479 480 /* 481 * reduce the number of usable entries in PCU TXBUF to avoid 482 * wrap around. 483 */ 484 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE); 485 } 486 487 static void 488 ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan) 489 { 490 uint32_t synthDelay; 491 492 /* 493 * Wait for the frequency synth to settle (synth goes on 494 * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 495 * Value is in 100ns increments. 496 */ 497 synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 498 if (IEEE80211_IS_CHAN_CCK(chan)) { 499 synthDelay = (4 * synthDelay) / 22; 500 } else { 501 synthDelay /= 10; 502 } 503 504 /* Turn on PLL on 5416 */ 505 HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n", 506 __func__, IEEE80211_IS_CHAN_5GHZ(chan) ? "5GHz" : "2GHz"); 507 ar5416InitPLL(ah, chan); 508 509 /* Activate the PHY (includes baseband activate and synthesizer on) */ 510 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 511 512 /* 513 * If the AP starts the calibration before the base band timeout 514 * completes we could get rx_clear false triggering. Add an 515 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 516 * does not happen. 517 */ 518 if (IEEE80211_IS_CHAN_HALF(chan)) { 519 OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY); 520 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 521 OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY); 522 } else { 523 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 524 } 525 } 526 527 static void 528 ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode) 529 { 530 struct ath_hal_5212 *ahp = AH5212(ah); 531 532 /* 533 * Setup interrupt handling. Note that ar5212ResetTxQueue 534 * manipulates the secondary IMR's as queues are enabled 535 * and disabled. This is done with RMW ops to insure the 536 * settings we make here are preserved. 537 */ 538 ahp->ah_maskReg = AR_IMR_TXERR | AR_IMR_TXURN 539 | AR_IMR_RXERR | AR_IMR_RXORN 540 | AR_IMR_BCNMISC; 541 542 #ifdef AR5416_INT_MITIGATION 543 ahp->ah_maskReg |= AR_IMR_TXINTM | AR_IMR_RXINTM 544 | AR_IMR_TXMINTR | AR_IMR_RXMINTR; 545 #else 546 ahp->ah_maskReg |= AR_IMR_TXOK | AR_IMR_RXOK; 547 #endif 548 if (opmode == HAL_M_HOSTAP) 549 ahp->ah_maskReg |= AR_IMR_MIB; 550 OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 551 /* Enable bus errors that are OR'd to set the HIUERR bit */ 552 #if 0 553 OS_REG_WRITE(ah, AR_IMR_S2, 554 OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST); 555 #endif 556 } 557 558 static void 559 ar5416InitQoS(struct ath_hal *ah) 560 { 561 /* QoS support */ 562 OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ 563 OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ 564 565 /* Turn on NOACK Support for QoS packets */ 566 OS_REG_WRITE(ah, AR_NOACK, 567 SM(2, AR_NOACK_2BIT_VALUE) | 568 SM(5, AR_NOACK_BIT_OFFSET) | 569 SM(0, AR_NOACK_BYTE_OFFSET)); 570 571 /* 572 * initialize TXOP for all TIDs 573 */ 574 OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 575 OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 576 OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 577 OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 578 OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 579 } 580 581 static void 582 ar5416InitUserSettings(struct ath_hal *ah) 583 { 584 struct ath_hal_5212 *ahp = AH5212(ah); 585 586 /* Restore user-specified settings */ 587 if (ahp->ah_miscMode != 0) 588 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 589 if (ahp->ah_sifstime != (u_int) -1) 590 ar5212SetSifsTime(ah, ahp->ah_sifstime); 591 if (ahp->ah_slottime != (u_int) -1) 592 ar5212SetSlotTime(ah, ahp->ah_slottime); 593 if (ahp->ah_acktimeout != (u_int) -1) 594 ar5212SetAckTimeout(ah, ahp->ah_acktimeout); 595 if (ahp->ah_ctstimeout != (u_int) -1) 596 ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); 597 if (AH_PRIVATE(ah)->ah_diagreg != 0) 598 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 599 #if 0 /* XXX Todo */ 600 if (ahp->ah_globaltxtimeout != (u_int) -1) 601 ar5416SetGlobalTxTimeout(ah, ahp->ah_globaltxtimeout); 602 #endif 603 } 604 605 /* 606 * Places the hardware into reset and then pulls it out of reset 607 */ 608 HAL_BOOL 609 ar5416ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan) 610 { 611 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); 612 /* 613 * Warm reset is optimistic. 614 */ 615 if (AR_SREV_MERLIN_20_OR_LATER(ah) && 616 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 617 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) 618 return AH_FALSE; 619 } else { 620 if (!ar5416SetResetReg(ah, HAL_RESET_WARM)) 621 return AH_FALSE; 622 } 623 624 /* Bring out of sleep mode (AGAIN) */ 625 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 626 return AH_FALSE; 627 628 ar5416InitPLL(ah, chan); 629 630 /* 631 * Perform warm reset before the mode/PLL/turbo registers 632 * are changed in order to deactivate the radio. Mode changes 633 * with an active radio can result in corrupted shifts to the 634 * radio device. 635 */ 636 if (chan != AH_NULL) { 637 uint32_t rfMode; 638 639 /* treat channel B as channel G , no B mode suport in owl */ 640 rfMode = IEEE80211_IS_CHAN_CCK(chan) ? 641 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 642 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 643 /* phy mode bits for 5GHz channels require Fast Clock */ 644 rfMode |= AR_PHY_MODE_DYNAMIC 645 | AR_PHY_MODE_DYN_CCK_DISABLE; 646 } else if (!AR_SREV_MERLIN_10_OR_LATER(ah)) { 647 rfMode |= IEEE80211_IS_CHAN_5GHZ(chan) ? 648 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 649 } 650 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 651 } 652 return AH_TRUE; 653 } 654 655 /* 656 * Delta slope coefficient computation. 657 * Required for OFDM operation. 658 */ 659 static void 660 ar5416GetDeltaSlopeValues(struct ath_hal *ah, uint32_t coef_scaled, 661 uint32_t *coef_mantissa, uint32_t *coef_exponent) 662 { 663 #define COEF_SCALE_S 24 664 uint32_t coef_exp, coef_man; 665 /* 666 * ALGO -> coef_exp = 14-floor(log2(coef)); 667 * floor(log2(x)) is the highest set bit position 668 */ 669 for (coef_exp = 31; coef_exp > 0; coef_exp--) 670 if ((coef_scaled >> coef_exp) & 0x1) 671 break; 672 /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ 673 HALASSERT(coef_exp); 674 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 675 676 /* 677 * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); 678 * The coefficient is already shifted up for scaling 679 */ 680 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 681 682 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 683 *coef_exponent = coef_exp - 16; 684 685 #undef COEF_SCALE_S 686 } 687 688 void 689 ar5416SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan) 690 { 691 #define INIT_CLOCKMHZSCALED 0x64000000 692 uint32_t coef_scaled, ds_coef_exp, ds_coef_man; 693 uint32_t clockMhzScaled; 694 695 CHAN_CENTERS centers; 696 697 /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */ 698 /* scale for selected channel bandwidth */ 699 clockMhzScaled = INIT_CLOCKMHZSCALED; 700 if (IEEE80211_IS_CHAN_TURBO(chan)) 701 clockMhzScaled <<= 1; 702 else if (IEEE80211_IS_CHAN_HALF(chan)) 703 clockMhzScaled >>= 1; 704 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 705 clockMhzScaled >>= 2; 706 707 /* 708 * ALGO -> coef = 1e8/fcarrier*fclock/40; 709 * scaled coef to provide precision for this floating calculation 710 */ 711 ar5416GetChannelCenters(ah, chan, ¢ers); 712 coef_scaled = clockMhzScaled / centers.synth_center; 713 714 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); 715 716 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 717 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 718 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 719 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 720 721 /* 722 * For Short GI, 723 * scaled coeff is 9/10 that of normal coeff 724 */ 725 coef_scaled = (9 * coef_scaled)/10; 726 727 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); 728 729 /* for short gi */ 730 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, 731 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 732 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, 733 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 734 #undef INIT_CLOCKMHZSCALED 735 } 736 737 /* 738 * Set a limit on the overall output power. Used for dynamic 739 * transmit power control and the like. 740 * 741 * NB: limit is in units of 0.5 dbM. 742 */ 743 HAL_BOOL 744 ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 745 { 746 uint16_t dummyXpdGains[2]; 747 748 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 749 return ar5416SetTransmitPower(ah, AH_PRIVATE(ah)->ah_curchan, 750 dummyXpdGains); 751 } 752 753 HAL_BOOL 754 ar5416GetChipPowerLimits(struct ath_hal *ah, 755 struct ieee80211_channel *chan) 756 { 757 struct ath_hal_5212 *ahp = AH5212(ah); 758 int16_t minPower, maxPower; 759 760 /* 761 * Get Pier table max and min powers. 762 */ 763 if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { 764 /* NB: rf code returns 1/4 dBm units, convert */ 765 chan->ic_maxpower = maxPower / 2; 766 chan->ic_minpower = minPower / 2; 767 } else { 768 HALDEBUG(ah, HAL_DEBUG_ANY, 769 "%s: no min/max power for %u/0x%x\n", 770 __func__, chan->ic_freq, chan->ic_flags); 771 chan->ic_maxpower = AR5416_MAX_RATE_POWER; 772 chan->ic_minpower = 0; 773 } 774 HALDEBUG(ah, HAL_DEBUG_RESET, 775 "Chan %d: MaxPow = %d MinPow = %d\n", 776 chan->ic_freq, chan->ic_maxpower, chan->ic_minpower); 777 return AH_TRUE; 778 } 779 780 /* XXX gag, this is sick */ 781 typedef enum Ar5416_Rates { 782 rate6mb, rate9mb, rate12mb, rate18mb, 783 rate24mb, rate36mb, rate48mb, rate54mb, 784 rate1l, rate2l, rate2s, rate5_5l, 785 rate5_5s, rate11l, rate11s, rateXr, 786 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 787 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 788 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 789 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 790 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 791 Ar5416RateSize 792 } AR5416_RATES; 793 794 /************************************************************** 795 * ar5416SetTransmitPower 796 * 797 * Set the transmit power in the baseband for the given 798 * operating channel and mode. 799 */ 800 HAL_BOOL 801 ar5416SetTransmitPower(struct ath_hal *ah, 802 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 803 { 804 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 805 #define N(a) (sizeof (a) / sizeof (a[0])) 806 807 MODAL_EEP_HEADER *pModal; 808 struct ath_hal_5212 *ahp = AH5212(ah); 809 int16_t ratesArray[Ar5416RateSize]; 810 int16_t txPowerIndexOffset = 0; 811 uint8_t ht40PowerIncForPdadc = 2; 812 int i; 813 814 uint16_t cfgCtl; 815 uint16_t powerLimit; 816 uint16_t twiceAntennaReduction; 817 uint16_t twiceMaxRegulatoryPower; 818 int16_t maxPower; 819 HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 820 struct ar5416eeprom *pEepData = &ee->ee_base; 821 822 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 823 824 /* Setup info for the actual eeprom */ 825 OS_MEMZERO(ratesArray, sizeof(ratesArray)); 826 cfgCtl = ath_hal_getctl(ah, chan); 827 powerLimit = chan->ic_maxregpower * 2; 828 twiceAntennaReduction = chan->ic_maxantgain; 829 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 830 pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]; 831 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 832 __func__,chan->ic_freq, cfgCtl ); 833 834 if (IS_EEP_MINOR_V2(ah)) { 835 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 836 } 837 838 if (!ar5416SetPowerPerRateTable(ah, pEepData, chan, 839 &ratesArray[0],cfgCtl, 840 twiceAntennaReduction, 841 twiceMaxRegulatoryPower, powerLimit)) { 842 HALDEBUG(ah, HAL_DEBUG_ANY, 843 "%s: unable to set tx power per rate table\n", __func__); 844 return AH_FALSE; 845 } 846 847 if (!ar5416SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 848 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 849 __func__); 850 return AH_FALSE; 851 } 852 853 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); 854 855 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 856 maxPower = AH_MAX(maxPower, ratesArray[rate1l]); 857 } 858 859 if (IEEE80211_IS_CHAN_HT40(chan)) { 860 maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); 861 } 862 863 ahp->ah_tx6PowerInHalfDbm = maxPower; 864 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 865 ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 866 867 /* 868 * txPowerIndexOffset is set by the SetPowerTable() call - 869 * adjust the rate table (0 offset if rates EEPROM not loaded) 870 */ 871 for (i = 0; i < N(ratesArray); i++) { 872 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 873 if (ratesArray[i] > AR5416_MAX_RATE_POWER) 874 ratesArray[i] = AR5416_MAX_RATE_POWER; 875 } 876 877 #ifdef AH_EEPROM_DUMP 878 ar5416PrintPowerPerRate(ah, ratesArray); 879 #endif 880 881 /* Write the OFDM power per rate set */ 882 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 883 POW_SM(ratesArray[rate18mb], 24) 884 | POW_SM(ratesArray[rate12mb], 16) 885 | POW_SM(ratesArray[rate9mb], 8) 886 | POW_SM(ratesArray[rate6mb], 0) 887 ); 888 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 889 POW_SM(ratesArray[rate54mb], 24) 890 | POW_SM(ratesArray[rate48mb], 16) 891 | POW_SM(ratesArray[rate36mb], 8) 892 | POW_SM(ratesArray[rate24mb], 0) 893 ); 894 895 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 896 /* Write the CCK power per rate set */ 897 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 898 POW_SM(ratesArray[rate2s], 24) 899 | POW_SM(ratesArray[rate2l], 16) 900 | POW_SM(ratesArray[rateXr], 8) /* XR target power */ 901 | POW_SM(ratesArray[rate1l], 0) 902 ); 903 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 904 POW_SM(ratesArray[rate11s], 24) 905 | POW_SM(ratesArray[rate11l], 16) 906 | POW_SM(ratesArray[rate5_5s], 8) 907 | POW_SM(ratesArray[rate5_5l], 0) 908 ); 909 HALDEBUG(ah, HAL_DEBUG_RESET, 910 "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n", 911 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), 912 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 913 } 914 915 /* Write the HT20 power per rate set */ 916 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 917 POW_SM(ratesArray[rateHt20_3], 24) 918 | POW_SM(ratesArray[rateHt20_2], 16) 919 | POW_SM(ratesArray[rateHt20_1], 8) 920 | POW_SM(ratesArray[rateHt20_0], 0) 921 ); 922 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 923 POW_SM(ratesArray[rateHt20_7], 24) 924 | POW_SM(ratesArray[rateHt20_6], 16) 925 | POW_SM(ratesArray[rateHt20_5], 8) 926 | POW_SM(ratesArray[rateHt20_4], 0) 927 ); 928 929 if (IEEE80211_IS_CHAN_HT40(chan)) { 930 /* Write the HT40 power per rate set */ 931 /* Correct PAR difference between HT40 and HT20/LEGACY */ 932 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 933 POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24) 934 | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16) 935 | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8) 936 | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0) 937 ); 938 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 939 POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24) 940 | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16) 941 | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8) 942 | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0) 943 ); 944 /* Write the Dup/Ext 40 power per rate set */ 945 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 946 POW_SM(ratesArray[rateExtOfdm], 24) 947 | POW_SM(ratesArray[rateExtCck], 16) 948 | POW_SM(ratesArray[rateDupOfdm], 8) 949 | POW_SM(ratesArray[rateDupCck], 0) 950 ); 951 } 952 953 /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */ 954 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 955 POW_SM(pModal->pwrDecreaseFor3Chain, 6) 956 | POW_SM(pModal->pwrDecreaseFor2Chain, 0) 957 ); 958 return AH_TRUE; 959 #undef POW_SM 960 #undef N 961 } 962 963 /* 964 * Exported call to check for a recent gain reading and return 965 * the current state of the thermal calibration gain engine. 966 */ 967 HAL_RFGAIN 968 ar5416GetRfgain(struct ath_hal *ah) 969 { 970 return HAL_RFGAIN_INACTIVE; 971 } 972 973 /* 974 * Places all of hardware into reset 975 */ 976 HAL_BOOL 977 ar5416Disable(struct ath_hal *ah) 978 { 979 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 980 return AH_FALSE; 981 return ar5416SetResetReg(ah, HAL_RESET_COLD); 982 } 983 984 /* 985 * Places the PHY and Radio chips into reset. A full reset 986 * must be called to leave this state. The PCI/MAC/PCU are 987 * not placed into reset as we must receive interrupt to 988 * re-enable the hardware. 989 */ 990 HAL_BOOL 991 ar5416PhyDisable(struct ath_hal *ah) 992 { 993 return ar5416SetResetReg(ah, HAL_RESET_WARM); 994 } 995 996 /* 997 * Write the given reset bit mask into the reset register 998 */ 999 HAL_BOOL 1000 ar5416SetResetReg(struct ath_hal *ah, uint32_t type) 1001 { 1002 switch (type) { 1003 case HAL_RESET_POWER_ON: 1004 return ar5416SetResetPowerOn(ah); 1005 case HAL_RESET_WARM: 1006 case HAL_RESET_COLD: 1007 return ar5416SetReset(ah, type); 1008 default: 1009 HALASSERT(AH_FALSE); 1010 return AH_FALSE; 1011 } 1012 } 1013 1014 static HAL_BOOL 1015 ar5416SetResetPowerOn(struct ath_hal *ah) 1016 { 1017 /* Power On Reset (Hard Reset) */ 1018 1019 /* 1020 * Set force wake 1021 * 1022 * If the MAC was running, previously calling 1023 * reset will wake up the MAC but it may go back to sleep 1024 * before we can start polling. 1025 * Set force wake stops that 1026 * This must be called before initiating a hard reset. 1027 */ 1028 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1029 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1030 1031 /* 1032 * RTC reset and clear 1033 */ 1034 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); 1035 OS_REG_WRITE(ah, AR_RTC_RESET, 0); 1036 OS_DELAY(20); 1037 OS_REG_WRITE(ah, AR_RC, 0); 1038 1039 OS_REG_WRITE(ah, AR_RTC_RESET, 1); 1040 1041 /* 1042 * Poll till RTC is ON 1043 */ 1044 if (!ath_hal_wait(ah, AR_RTC_STATUS, AR_RTC_PM_STATUS_M, AR_RTC_STATUS_ON)) { 1045 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC not waking up\n", __func__); 1046 return AH_FALSE; 1047 } 1048 1049 return ar5416SetReset(ah, HAL_RESET_COLD); 1050 } 1051 1052 static HAL_BOOL 1053 ar5416SetReset(struct ath_hal *ah, int type) 1054 { 1055 uint32_t tmpReg, mask; 1056 1057 /* 1058 * Force wake 1059 */ 1060 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1061 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1062 1063 /* 1064 * Reset AHB 1065 */ 1066 tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 1067 if (tmpReg & (AR_INTR_SYNC_LOCAL_TIMEOUT|AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1068 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1069 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF); 1070 } else { 1071 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); 1072 } 1073 1074 /* 1075 * Set Mac(BB,Phy) Warm Reset 1076 */ 1077 switch (type) { 1078 case HAL_RESET_WARM: 1079 OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM); 1080 break; 1081 case HAL_RESET_COLD: 1082 OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM|AR_RTC_RC_MAC_COLD); 1083 break; 1084 default: 1085 HALASSERT(AH_FALSE); 1086 break; 1087 } 1088 1089 /* 1090 * Clear resets and force wakeup 1091 */ 1092 OS_REG_WRITE(ah, AR_RTC_RC, 0); 1093 if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) { 1094 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC stuck in MAC reset\n", __func__); 1095 return AH_FALSE; 1096 } 1097 1098 /* Clear AHB reset */ 1099 OS_REG_WRITE(ah, AR_RC, 0); 1100 1101 if (type == HAL_RESET_COLD) { 1102 if (isBigEndian()) { 1103 /* 1104 * Set CFG, little-endian for register 1105 * and descriptor accesses. 1106 */ 1107 mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG; 1108 #ifndef AH_NEED_DESC_SWAP 1109 mask |= AR_CFG_SWTD; 1110 #endif 1111 HALDEBUG(ah, HAL_DEBUG_RESET, 1112 "%s Applying descriptor swap\n", __func__); 1113 OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); 1114 } else 1115 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 1116 } 1117 1118 ar5416InitPLL(ah, AH_NULL); 1119 1120 return AH_TRUE; 1121 } 1122 1123 void 1124 ar5416InitChainMasks(struct ath_hal *ah) 1125 { 1126 if (AH5416(ah)->ah_rx_chainmask == 0x5 || 1127 AH5416(ah)->ah_tx_chainmask == 0x5) 1128 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 1129 /* Setup Chain Masks */ 1130 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask); 1131 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask); 1132 OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask); 1133 } 1134 1135 void 1136 ar5416RestoreChainMask(struct ath_hal *ah) 1137 { 1138 int rx_chainmask = AH5416(ah)->ah_rx_chainmask; 1139 1140 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 1141 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 1142 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 1143 } 1144 } 1145 1146 /* 1147 * Update the chainmask based on the current channel configuration. 1148 * 1149 * XXX ath9k checks bluetooth co-existence here 1150 * XXX ath9k checks whether the current state is "off-channel". 1151 * XXX ath9k sticks the hardware into 1x1 mode for legacy; 1152 * we're going to leave multi-RX on for multi-path cancellation. 1153 */ 1154 static void 1155 ar5416UpdateChainMasks(struct ath_hal *ah, HAL_BOOL is_ht) 1156 { 1157 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 1158 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 1159 1160 if (is_ht) { 1161 AH5416(ah)->ah_tx_chainmask = pCap->halTxChainMask; 1162 } else { 1163 AH5416(ah)->ah_tx_chainmask = 1; 1164 } 1165 AH5416(ah)->ah_rx_chainmask = pCap->halRxChainMask; 1166 HALDEBUG(ah, HAL_DEBUG_ANY, "TX chainmask: 0x%x; RX chainmask: 0x%x\n", 1167 AH5416(ah)->ah_tx_chainmask, 1168 AH5416(ah)->ah_rx_chainmask); 1169 } 1170 1171 #ifndef IS_5GHZ_FAST_CLOCK_EN 1172 #define IS_5GHZ_FAST_CLOCK_EN(ah, chan) AH_FALSE 1173 #endif 1174 1175 static void 1176 ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 1177 { 1178 uint32_t pll; 1179 1180 if (AR_SREV_MERLIN_20(ah) && 1181 chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) { 1182 /* 1183 * PLL WAR for Merlin 2.0/2.1 1184 * When doing fast clock, set PLL to 0x142c 1185 * Else, set PLL to 0x2850 to prevent reset-to-reset variation 1186 */ 1187 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; 1188 } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1189 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 1190 if (chan != AH_NULL) { 1191 if (IEEE80211_IS_CHAN_HALF(chan)) 1192 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 1193 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 1194 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 1195 else if (IEEE80211_IS_CHAN_5GHZ(chan)) 1196 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); 1197 else 1198 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 1199 } else 1200 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 1201 } else if (AR_SREV_SOWL_10_OR_LATER(ah)) { 1202 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 1203 if (chan != AH_NULL) { 1204 if (IEEE80211_IS_CHAN_HALF(chan)) 1205 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 1206 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 1207 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 1208 else if (IEEE80211_IS_CHAN_5GHZ(chan)) 1209 pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV); 1210 else 1211 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); 1212 } else 1213 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); 1214 } else { 1215 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 1216 if (chan != AH_NULL) { 1217 if (IEEE80211_IS_CHAN_HALF(chan)) 1218 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 1219 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 1220 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 1221 else if (IEEE80211_IS_CHAN_5GHZ(chan)) 1222 pll |= SM(0xa, AR_RTC_PLL_DIV); 1223 else 1224 pll |= SM(0xb, AR_RTC_PLL_DIV); 1225 } else 1226 pll |= SM(0xb, AR_RTC_PLL_DIV); 1227 } 1228 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 1229 1230 /* TODO: 1231 * For multi-band owl, switch between bands by reiniting the PLL. 1232 */ 1233 1234 OS_DELAY(RTC_PLL_SETTLE_DELAY); 1235 1236 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 1237 } 1238 1239 static void 1240 ar5416SetDefGainValues(struct ath_hal *ah, 1241 const MODAL_EEP_HEADER *pModal, 1242 const struct ar5416eeprom *eep, 1243 uint8_t txRxAttenLocal, int regChainOffset, int i) 1244 { 1245 if (IS_EEP_MINOR_V3(ah)) { 1246 txRxAttenLocal = pModal->txRxAttenCh[i]; 1247 1248 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 1249 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1250 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 1251 pModal->bswMargin[i]); 1252 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1253 AR_PHY_GAIN_2GHZ_XATTEN1_DB, 1254 pModal->bswAtten[i]); 1255 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1256 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 1257 pModal->xatten2Margin[i]); 1258 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1259 AR_PHY_GAIN_2GHZ_XATTEN2_DB, 1260 pModal->xatten2Db[i]); 1261 } else { 1262 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1263 (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & 1264 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) 1265 | SM(pModal-> bswMargin[i], 1266 AR_PHY_GAIN_2GHZ_BSW_MARGIN)); 1267 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1268 (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & 1269 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) 1270 | SM(pModal->bswAtten[i], 1271 AR_PHY_GAIN_2GHZ_BSW_ATTEN)); 1272 } 1273 } 1274 1275 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 1276 OS_REG_RMW_FIELD(ah, 1277 AR_PHY_RXGAIN + regChainOffset, 1278 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 1279 OS_REG_RMW_FIELD(ah, 1280 AR_PHY_RXGAIN + regChainOffset, 1281 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]); 1282 } else { 1283 OS_REG_WRITE(ah, 1284 AR_PHY_RXGAIN + regChainOffset, 1285 (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & 1286 ~AR_PHY_RXGAIN_TXRX_ATTEN) 1287 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN)); 1288 OS_REG_WRITE(ah, 1289 AR_PHY_GAIN_2GHZ + regChainOffset, 1290 (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & 1291 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | 1292 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); 1293 } 1294 } 1295 1296 1297 1298 /* 1299 * Read EEPROM header info and program the device for correct operation 1300 * given the channel value. 1301 */ 1302 HAL_BOOL 1303 ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 1304 { 1305 const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 1306 const struct ar5416eeprom *eep = &ee->ee_base; 1307 const MODAL_EEP_HEADER *pModal; 1308 int i, regChainOffset; 1309 uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */ 1310 1311 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 1312 pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]; 1313 1314 /* NB: workaround for eeprom versions <= 14.2 */ 1315 txRxAttenLocal = IEEE80211_IS_CHAN_2GHZ(chan) ? 23 : 44; 1316 1317 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 1318 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 1319 if (AR_SREV_MERLIN(ah)) { 1320 if (i >= 2) break; 1321 } 1322 if (AR_SREV_OWL_20_OR_LATER(ah) && 1323 (AH5416(ah)->ah_rx_chainmask == 0x5 || 1324 AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) { 1325 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 1326 * only chains 0 and 2 populated 1327 */ 1328 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1329 } else { 1330 regChainOffset = i * 0x1000; 1331 } 1332 1333 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]); 1334 1335 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset, 1336 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) & 1337 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 1338 SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 1339 SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 1340 1341 /* 1342 * Large signal upgrade. 1343 * XXX update 1344 */ 1345 1346 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) 1347 ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i); 1348 1349 } 1350 1351 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 1352 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1353 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_OB, pModal->ob); 1354 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_DB, pModal->db); 1355 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_OB, pModal->ob_ch1); 1356 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_DB, pModal->db_ch1); 1357 } else { 1358 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_OB5, pModal->ob); 1359 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_DB5, pModal->db); 1360 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_OB5, pModal->ob_ch1); 1361 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_DB5, pModal->db_ch1); 1362 } 1363 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_XPABIAS_LVL, pModal->xpaBiasLvl); 1364 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_LOCALBIAS, pModal->flagBits & AR5416_EEP_FLAG_LOCALBIAS); 1365 OS_A_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, pModal->flagBits & AR5416_EEP_FLAG_FORCEXPAON); 1366 } 1367 1368 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling); 1369 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); 1370 1371 if (! AR_SREV_MERLIN_20_OR_LATER(ah)) 1372 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize); 1373 1374 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 1375 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) 1376 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) 1377 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) 1378 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 1379 1380 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn); 1381 1382 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1383 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1384 pModal->thresh62); 1385 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 1386 pModal->thresh62); 1387 } else { 1388 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, 1389 pModal->thresh62); 1390 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA_THRESH62, 1391 pModal->thresh62); 1392 } 1393 1394 /* Minor Version Specific application */ 1395 if (IS_EEP_MINOR_V2(ah)) { 1396 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart); 1397 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn); 1398 } 1399 1400 if (IS_EEP_MINOR_V3(ah) && IEEE80211_IS_CHAN_HT40(chan)) 1401 /* Overwrite switch settling with HT40 value */ 1402 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); 1403 1404 if (AR_SREV_MERLIN_20_OR_LATER(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_19) 1405 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, pModal->miscBits); 1406 1407 if (AR_SREV_MERLIN_20(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_20) { 1408 if (IEEE80211_IS_CHAN_2GHZ(chan)) 1409 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, eep->baseEepHeader.dacLpMode); 1410 else if (eep->baseEepHeader.dacHiPwrMode_5G) 1411 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0); 1412 else 1413 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, eep->baseEepHeader.dacLpMode); 1414 1415 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, pModal->miscBits >> 2); 1416 OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_DESIRED_SCALE_CCK, eep->baseEepHeader.desiredScaleCCK); 1417 } 1418 1419 return AH_TRUE; 1420 } 1421 1422 /* 1423 * Helper functions common for AP/CB/XB 1424 */ 1425 1426 /* 1427 * ar5416SetPowerPerRateTable 1428 * 1429 * Sets the transmit power in the baseband for the given 1430 * operating channel and mode. 1431 */ 1432 static HAL_BOOL 1433 ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, 1434 const struct ieee80211_channel *chan, 1435 int16_t *ratesArray, uint16_t cfgCtl, 1436 uint16_t AntennaReduction, 1437 uint16_t twiceMaxRegulatoryPower, 1438 uint16_t powerLimit) 1439 { 1440 #define N(a) (sizeof(a)/sizeof(a[0])) 1441 /* Local defines to distinguish between extension and control CTL's */ 1442 #define EXT_ADDITIVE (0x8000) 1443 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 1444 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 1445 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 1446 1447 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1448 int i; 1449 int16_t twiceLargestAntenna; 1450 CAL_CTL_DATA *rep; 1451 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 1452 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 1453 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 1454 int16_t scaledPower, minCtlPower; 1455 1456 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ 1457 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 1458 static const uint16_t ctlModesFor11a[] = { 1459 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 1460 }; 1461 static const uint16_t ctlModesFor11g[] = { 1462 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 1463 }; 1464 const uint16_t *pCtlMode; 1465 uint16_t numCtlModes, ctlMode, freq; 1466 CHAN_CENTERS centers; 1467 1468 ar5416GetChannelCenters(ah, chan, ¢ers); 1469 1470 /* Compute TxPower reduction due to Antenna Gain */ 1471 1472 twiceLargestAntenna = AH_MAX(AH_MAX( 1473 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0], 1474 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]), 1475 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 1476 #if 0 1477 /* Turn it back on if we need to calculate per chain antenna gain reduction */ 1478 /* Use only if the expected gain > 6dbi */ 1479 /* Chain 0 is always used */ 1480 twiceLargestAntenna = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0]; 1481 1482 /* Look at antenna gains of Chains 1 and 2 if the TX mask is set */ 1483 if (ahp->ah_tx_chainmask & 0x2) 1484 twiceLargestAntenna = AH_MAX(twiceLargestAntenna, 1485 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]); 1486 1487 if (ahp->ah_tx_chainmask & 0x4) 1488 twiceLargestAntenna = AH_MAX(twiceLargestAntenna, 1489 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 1490 #endif 1491 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 1492 1493 /* XXX setup for 5212 use (really used?) */ 1494 ath_hal_eepromSet(ah, 1495 IEEE80211_IS_CHAN_2GHZ(chan) ? AR_EEP_ANTGAINMAX_2 : AR_EEP_ANTGAINMAX_5, 1496 twiceLargestAntenna); 1497 1498 /* 1499 * scaledPower is the minimum of the user input power level and 1500 * the regulatory allowed power level 1501 */ 1502 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 1503 1504 /* Reduce scaled Power by number of chains active to get to per chain tx power level */ 1505 /* TODO: better value than these? */ 1506 switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) { 1507 case 1: 1508 break; 1509 case 2: 1510 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain; 1511 break; 1512 case 3: 1513 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain; 1514 break; 1515 default: 1516 return AH_FALSE; /* Unsupported number of chains */ 1517 } 1518 1519 scaledPower = AH_MAX(0, scaledPower); 1520 1521 /* Get target powers from EEPROM - our baseline for TX Power */ 1522 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1523 /* Setup for CTL modes */ 1524 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 1525 pCtlMode = ctlModesFor11g; 1526 1527 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 1528 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 1529 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 1530 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 1531 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 1532 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 1533 1534 if (IEEE80211_IS_CHAN_HT40(chan)) { 1535 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 1536 1537 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 1538 AR5416_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 1539 /* Get target powers for extension channels */ 1540 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 1541 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 1542 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 1543 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 1544 } 1545 } else { 1546 /* Setup for CTL modes */ 1547 numCtlModes = N(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */ 1548 pCtlMode = ctlModesFor11a; 1549 1550 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, 1551 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 1552 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20, 1553 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 1554 1555 if (IEEE80211_IS_CHAN_HT40(chan)) { 1556 numCtlModes = N(ctlModesFor11a); /* All 5G CTL's */ 1557 1558 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40, 1559 AR5416_NUM_5G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 1560 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, 1561 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 1562 } 1563 } 1564 1565 /* 1566 * For MIMO, need to apply regulatory caps individually across dynamically 1567 * running modes: CCK, OFDM, HT20, HT40 1568 * 1569 * The outer loop walks through each possible applicable runtime mode. 1570 * The inner loop walks through each ctlIndex entry in EEPROM. 1571 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 1572 * 1573 */ 1574 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 1575 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 1576 (pCtlMode[ctlMode] == CTL_2GHT40); 1577 if (isHt40CtlMode) { 1578 freq = centers.ctl_center; 1579 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 1580 freq = centers.ext_center; 1581 } else { 1582 freq = centers.ctl_center; 1583 } 1584 1585 /* walk through each CTL index stored in EEPROM */ 1586 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 1587 uint16_t twiceMinEdgePower; 1588 1589 /* compare test group from regulatory channel list with test mode from pCtlMode list */ 1590 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 1591 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 1592 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 1593 rep = &(pEepData->ctlData[i]); 1594 twiceMinEdgePower = ar5416GetMaxEdgePower(freq, 1595 rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], 1596 IEEE80211_IS_CHAN_2GHZ(chan)); 1597 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 1598 /* Find the minimum of all CTL edge powers that apply to this channel */ 1599 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 1600 } else { 1601 /* specific */ 1602 twiceMaxEdgePower = twiceMinEdgePower; 1603 break; 1604 } 1605 } 1606 } 1607 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 1608 /* Apply ctl mode to correct target power set */ 1609 switch(pCtlMode[ctlMode]) { 1610 case CTL_11B: 1611 for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 1612 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 1613 } 1614 break; 1615 case CTL_11A: 1616 case CTL_11G: 1617 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 1618 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 1619 } 1620 break; 1621 case CTL_5GHT20: 1622 case CTL_2GHT20: 1623 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 1624 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 1625 } 1626 break; 1627 case CTL_11B_EXT: 1628 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 1629 break; 1630 case CTL_11A_EXT: 1631 case CTL_11G_EXT: 1632 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 1633 break; 1634 case CTL_5GHT40: 1635 case CTL_2GHT40: 1636 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 1637 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 1638 } 1639 break; 1640 default: 1641 return AH_FALSE; 1642 break; 1643 } 1644 } /* end ctl mode checking */ 1645 1646 /* Set rates Array from collected data */ 1647 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; 1648 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 1649 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 1650 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 1651 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 1652 1653 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 1654 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 1655 } 1656 1657 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1658 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 1659 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 1660 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 1661 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 1662 } 1663 if (IEEE80211_IS_CHAN_HT40(chan)) { 1664 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 1665 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; 1666 } 1667 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 1668 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 1669 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 1670 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1671 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 1672 } 1673 } 1674 return AH_TRUE; 1675 #undef EXT_ADDITIVE 1676 #undef CTL_11A_EXT 1677 #undef CTL_11G_EXT 1678 #undef CTL_11B_EXT 1679 #undef SUB_NUM_CTL_MODES_AT_5G_40 1680 #undef SUB_NUM_CTL_MODES_AT_2G_40 1681 #undef N 1682 } 1683 1684 /************************************************************************** 1685 * fbin2freq 1686 * 1687 * Get channel value from binary representation held in eeprom 1688 * RETURNS: the frequency in MHz 1689 */ 1690 static uint16_t 1691 fbin2freq(uint8_t fbin, HAL_BOOL is2GHz) 1692 { 1693 /* 1694 * Reserved value 0xFF provides an empty definition both as 1695 * an fbin and as a frequency - do not convert 1696 */ 1697 if (fbin == AR5416_BCHAN_UNUSED) { 1698 return fbin; 1699 } 1700 1701 return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); 1702 } 1703 1704 /* 1705 * ar5416GetMaxEdgePower 1706 * 1707 * Find the maximum conformance test limit for the given channel and CTL info 1708 */ 1709 static uint16_t 1710 ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz) 1711 { 1712 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1713 int i; 1714 1715 /* Get the edge power */ 1716 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) { 1717 /* 1718 * If there's an exact channel match or an inband flag set 1719 * on the lower channel use the given rdEdgePower 1720 */ 1721 if (freq == fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { 1722 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER); 1723 break; 1724 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel, is2GHz))) { 1725 if (fbin2freq(pRdEdgesPower[i - 1].bChannel, is2GHz) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) { 1726 twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER); 1727 } 1728 /* Leave loop - no more affecting edges possible in this monotonic increasing list */ 1729 break; 1730 } 1731 } 1732 HALASSERT(twiceMaxEdgePower > 0); 1733 return twiceMaxEdgePower; 1734 } 1735 1736 /************************************************************** 1737 * ar5416GetTargetPowers 1738 * 1739 * Return the rates of target power for the given target power table 1740 * channel, and number of channels 1741 */ 1742 void 1743 ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, 1744 CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels, 1745 CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates, 1746 HAL_BOOL isHt40Target) 1747 { 1748 uint16_t clo, chi; 1749 int i; 1750 int matchIndex = -1, lowIndex = -1; 1751 uint16_t freq; 1752 CHAN_CENTERS centers; 1753 1754 ar5416GetChannelCenters(ah, chan, ¢ers); 1755 freq = isHt40Target ? centers.synth_center : centers.ctl_center; 1756 1757 /* Copy the target powers into the temp channel list */ 1758 if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 1759 matchIndex = 0; 1760 } else { 1761 for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 1762 if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 1763 matchIndex = i; 1764 break; 1765 } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) && 1766 (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)))) 1767 { 1768 lowIndex = i - 1; 1769 break; 1770 } 1771 } 1772 if ((matchIndex == -1) && (lowIndex == -1)) { 1773 HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))); 1774 matchIndex = i - 1; 1775 } 1776 } 1777 1778 if (matchIndex != -1) { 1779 OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower)); 1780 } else { 1781 HALASSERT(lowIndex != -1); 1782 /* 1783 * Get the lower and upper channels, target powers, 1784 * and interpolate between them. 1785 */ 1786 clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 1787 chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 1788 1789 for (i = 0; i < numRates; i++) { 1790 pNewPower->tPow2x[i] = (uint8_t)interpolate(freq, clo, chi, 1791 powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]); 1792 } 1793 } 1794 } 1795 /************************************************************** 1796 * ar5416GetTargetPowersLeg 1797 * 1798 * Return the four rates of target power for the given target power table 1799 * channel, and number of channels 1800 */ 1801 void 1802 ar5416GetTargetPowersLeg(struct ath_hal *ah, 1803 const struct ieee80211_channel *chan, 1804 CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels, 1805 CAL_TARGET_POWER_LEG *pNewPower, uint16_t numRates, 1806 HAL_BOOL isExtTarget) 1807 { 1808 uint16_t clo, chi; 1809 int i; 1810 int matchIndex = -1, lowIndex = -1; 1811 uint16_t freq; 1812 CHAN_CENTERS centers; 1813 1814 ar5416GetChannelCenters(ah, chan, ¢ers); 1815 freq = (isExtTarget) ? centers.ext_center :centers.ctl_center; 1816 1817 /* Copy the target powers into the temp channel list */ 1818 if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 1819 matchIndex = 0; 1820 } else { 1821 for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 1822 if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 1823 matchIndex = i; 1824 break; 1825 } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) && 1826 (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)))) 1827 { 1828 lowIndex = i - 1; 1829 break; 1830 } 1831 } 1832 if ((matchIndex == -1) && (lowIndex == -1)) { 1833 HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))); 1834 matchIndex = i - 1; 1835 } 1836 } 1837 1838 if (matchIndex != -1) { 1839 OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower)); 1840 } else { 1841 HALASSERT(lowIndex != -1); 1842 /* 1843 * Get the lower and upper channels, target powers, 1844 * and interpolate between them. 1845 */ 1846 clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 1847 chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 1848 1849 for (i = 0; i < numRates; i++) { 1850 pNewPower->tPow2x[i] = (uint8_t)interpolate(freq, clo, chi, 1851 powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]); 1852 } 1853 } 1854 } 1855 1856 /************************************************************** 1857 * ar5416SetPowerCalTable 1858 * 1859 * Pull the PDADC piers from cal data and interpolate them across the given 1860 * points as well as from the nearest pier(s) to get a power detector 1861 * linear voltage to power level table. 1862 */ 1863 static HAL_BOOL 1864 ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, 1865 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 1866 { 1867 CAL_DATA_PER_FREQ *pRawDataset; 1868 uint8_t *pCalBChans = AH_NULL; 1869 uint16_t pdGainOverlap_t2; 1870 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 1871 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 1872 uint16_t numPiers, i, j; 1873 int16_t tMinCalPower; 1874 uint16_t numXpdGain, xpdMask; 1875 uint16_t xpdGainValues[AR5416_NUM_PD_GAINS]; 1876 uint32_t reg32, regOffset, regChainOffset; 1877 1878 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 1879 1880 xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain; 1881 1882 if (IS_EEP_MINOR_V2(ah)) { 1883 pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap; 1884 } else { 1885 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 1886 } 1887 1888 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1889 pCalBChans = pEepData->calFreqPier2G; 1890 numPiers = AR5416_NUM_2G_CAL_PIERS; 1891 } else { 1892 pCalBChans = pEepData->calFreqPier5G; 1893 numPiers = AR5416_NUM_5G_CAL_PIERS; 1894 } 1895 1896 numXpdGain = 0; 1897 /* Calculate the value of xpdgains from the xpdGain Mask */ 1898 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 1899 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 1900 if (numXpdGain >= AR5416_NUM_PD_GAINS) { 1901 HALASSERT(0); 1902 break; 1903 } 1904 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 1905 numXpdGain++; 1906 } 1907 } 1908 1909 /* Write the detector gain biases and their number */ 1910 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) & 1911 ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) | 1912 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) | 1913 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3)); 1914 1915 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 1916 1917 if (AR_SREV_OWL_20_OR_LATER(ah) && 1918 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) { 1919 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 1920 * only chains 0 and 2 populated 1921 */ 1922 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1923 } else { 1924 regChainOffset = i * 0x1000; 1925 } 1926 1927 if (pEepData->baseEepHeader.txMask & (1 << i)) { 1928 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1929 pRawDataset = pEepData->calPierData2G[i]; 1930 } else { 1931 pRawDataset = pEepData->calPierData5G[i]; 1932 } 1933 1934 ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 1935 pCalBChans, numPiers, 1936 pdGainOverlap_t2, 1937 &tMinCalPower, gainBoundaries, 1938 pdadcValues, numXpdGain); 1939 1940 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { 1941 /* 1942 * Note the pdadc table may not start at 0 dBm power, could be 1943 * negative or greater than 0. Need to offset the power 1944 * values by the amount of minPower for griffin 1945 */ 1946 1947 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, 1948 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 1949 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | 1950 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | 1951 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | 1952 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); 1953 } 1954 1955 /* Write the power values into the baseband power table */ 1956 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 1957 1958 for (j = 0; j < 32; j++) { 1959 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) | 1960 ((pdadcValues[4*j + 1] & 0xFF) << 8) | 1961 ((pdadcValues[4*j + 2] & 0xFF) << 16) | 1962 ((pdadcValues[4*j + 3] & 0xFF) << 24) ; 1963 OS_REG_WRITE(ah, regOffset, reg32); 1964 1965 #ifdef PDADC_DUMP 1966 ath_hal_printf(ah, "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n", 1967 i, 1968 4*j, pdadcValues[4*j], 1969 4*j+1, pdadcValues[4*j + 1], 1970 4*j+2, pdadcValues[4*j + 2], 1971 4*j+3, pdadcValues[4*j + 3]); 1972 #endif 1973 regOffset += 4; 1974 } 1975 } 1976 } 1977 *pTxPowerIndexOffset = 0; 1978 1979 return AH_TRUE; 1980 } 1981 1982 /************************************************************** 1983 * ar5416GetGainBoundariesAndPdadcs 1984 * 1985 * Uses the data points read from EEPROM to reconstruct the pdadc power table 1986 * Called by ar5416SetPowerCalTable only. 1987 */ 1988 static void 1989 ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, 1990 const struct ieee80211_channel *chan, 1991 CAL_DATA_PER_FREQ *pRawDataSet, 1992 uint8_t * bChans, uint16_t availPiers, 1993 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 1994 uint8_t * pPDADCValues, uint16_t numXpdGains) 1995 { 1996 1997 int i, j, k; 1998 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 1999 uint16_t idxL, idxR, numPiers; /* Pier indexes */ 2000 2001 /* filled out Vpd table for all pdGains (chanL) */ 2002 static uint8_t vpdTableL[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 2003 2004 /* filled out Vpd table for all pdGains (chanR) */ 2005 static uint8_t vpdTableR[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 2006 2007 /* filled out Vpd table for all pdGains (interpolated) */ 2008 static uint8_t vpdTableI[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 2009 2010 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 2011 uint8_t minPwrT4[AR5416_NUM_PD_GAINS]; 2012 uint8_t maxPwrT4[AR5416_NUM_PD_GAINS]; 2013 int16_t vpdStep; 2014 int16_t tmpVal; 2015 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 2016 HAL_BOOL match; 2017 int16_t minDelta = 0; 2018 CHAN_CENTERS centers; 2019 2020 ar5416GetChannelCenters(ah, chan, ¢ers); 2021 2022 /* Trim numPiers for the number of populated channel Piers */ 2023 for (numPiers = 0; numPiers < availPiers; numPiers++) { 2024 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 2025 break; 2026 } 2027 } 2028 2029 /* Find pier indexes around the current channel */ 2030 match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)), 2031 bChans, numPiers, &idxL, &idxR); 2032 2033 if (match) { 2034 /* Directly fill both vpd tables from the matching index */ 2035 for (i = 0; i < numXpdGains; i++) { 2036 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 2037 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 2038 ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i], 2039 pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 2040 } 2041 } else { 2042 for (i = 0; i < numXpdGains; i++) { 2043 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 2044 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 2045 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 2046 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 2047 2048 /* Start Vpd interpolation from the max of the minimum powers */ 2049 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 2050 2051 /* End Vpd interpolation from the min of the max powers */ 2052 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 2053 HALASSERT(maxPwrT4[i] > minPwrT4[i]); 2054 2055 /* Fill pier Vpds */ 2056 ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 2057 ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 2058 2059 /* Interpolate the final vpd */ 2060 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 2061 vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)), 2062 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 2063 } 2064 } 2065 } 2066 *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 2067 2068 k = 0; /* index for the final table */ 2069 for (i = 0; i < numXpdGains; i++) { 2070 if (i == (numXpdGains - 1)) { 2071 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 2072 } else { 2073 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 2074 } 2075 2076 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 2077 2078 /* NB: only applies to owl 1.0 */ 2079 if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) { 2080 /* 2081 * fix the gain delta, but get a delta that can be applied to min to 2082 * keep the upper power values accurate, don't think max needs to 2083 * be adjusted because should not be at that area of the table? 2084 */ 2085 minDelta = pPdGainBoundaries[0] - 23; 2086 pPdGainBoundaries[0] = 23; 2087 } 2088 else { 2089 minDelta = 0; 2090 } 2091 2092 /* Find starting index for this pdGain */ 2093 if (i == 0) { 2094 ss = 0; /* for the first pdGain, start from index 0 */ 2095 } else { 2096 /* need overlap entries extrapolated below. */ 2097 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 2098 } 2099 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 2100 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 2101 /* 2102 *-ve ss indicates need to extrapolate data below for this pdGain 2103 */ 2104 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2105 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 2106 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 2107 ss++; 2108 } 2109 2110 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 2111 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 2112 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 2113 2114 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2115 pPDADCValues[k++] = vpdTableI[i][ss++]; 2116 } 2117 2118 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 2119 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 2120 /* 2121 * for last gain, pdGainBoundary == Pmax_t2, so will 2122 * have to extrapolate 2123 */ 2124 if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 2125 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2126 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 2127 (ss - maxIndex +1) * vpdStep)); 2128 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 2129 ss++; 2130 } 2131 } /* extrapolated above */ 2132 } /* for all pdGainUsed */ 2133 2134 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 2135 while (i < AR5416_PD_GAINS_IN_MASK) { 2136 pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; 2137 i++; 2138 } 2139 2140 while (k < AR5416_NUM_PDADC_VALUES) { 2141 pPDADCValues[k] = pPDADCValues[k-1]; 2142 k++; 2143 } 2144 return; 2145 } 2146 2147 /************************************************************** 2148 * getLowerUppderIndex 2149 * 2150 * Return indices surrounding the value in sorted integer lists. 2151 * Requirement: the input list must be monotonically increasing 2152 * and populated up to the list size 2153 * Returns: match is set if an index in the array matches exactly 2154 * or a the target is before or after the range of the array. 2155 */ 2156 HAL_BOOL 2157 getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize, 2158 uint16_t *indexL, uint16_t *indexR) 2159 { 2160 uint16_t i; 2161 2162 /* 2163 * Check first and last elements for beyond ordered array cases. 2164 */ 2165 if (target <= pList[0]) { 2166 *indexL = *indexR = 0; 2167 return AH_TRUE; 2168 } 2169 if (target >= pList[listSize-1]) { 2170 *indexL = *indexR = (uint16_t)(listSize - 1); 2171 return AH_TRUE; 2172 } 2173 2174 /* look for value being near or between 2 values in list */ 2175 for (i = 0; i < listSize - 1; i++) { 2176 /* 2177 * If value is close to the current value of the list 2178 * then target is not between values, it is one of the values 2179 */ 2180 if (pList[i] == target) { 2181 *indexL = *indexR = i; 2182 return AH_TRUE; 2183 } 2184 /* 2185 * Look for value being between current value and next value 2186 * if so return these 2 values 2187 */ 2188 if (target < pList[i + 1]) { 2189 *indexL = i; 2190 *indexR = (uint16_t)(i + 1); 2191 return AH_FALSE; 2192 } 2193 } 2194 HALASSERT(0); 2195 *indexL = *indexR = 0; 2196 return AH_FALSE; 2197 } 2198 2199 /************************************************************** 2200 * ar5416FillVpdTable 2201 * 2202 * Fill the Vpdlist for indices Pmax-Pmin 2203 * Note: pwrMin, pwrMax and Vpdlist are all in dBm * 4 2204 */ 2205 static HAL_BOOL 2206 ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList, 2207 uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList) 2208 { 2209 uint16_t i, k; 2210 uint8_t currPwr = pwrMin; 2211 uint16_t idxL, idxR; 2212 2213 HALASSERT(pwrMax > pwrMin); 2214 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { 2215 getLowerUpperIndex(currPwr, pPwrList, numIntercepts, 2216 &(idxL), &(idxR)); 2217 if (idxR < 1) 2218 idxR = 1; /* extrapolate below */ 2219 if (idxL == numIntercepts - 1) 2220 idxL = (uint16_t)(numIntercepts - 2); /* extrapolate above */ 2221 if (pPwrList[idxL] == pPwrList[idxR]) 2222 k = pVpdList[idxL]; 2223 else 2224 k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / 2225 (pPwrList[idxR] - pPwrList[idxL]) ); 2226 HALASSERT(k < 256); 2227 pRetVpdList[i] = (uint8_t)k; 2228 currPwr += 2; /* half dB steps */ 2229 } 2230 2231 return AH_TRUE; 2232 } 2233 2234 /************************************************************************** 2235 * interpolate 2236 * 2237 * Returns signed interpolated or the scaled up interpolated value 2238 */ 2239 static int16_t 2240 interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, 2241 int16_t targetLeft, int16_t targetRight) 2242 { 2243 int16_t rv; 2244 2245 if (srcRight == srcLeft) { 2246 rv = targetLeft; 2247 } else { 2248 rv = (int16_t)( ((target - srcLeft) * targetRight + 2249 (srcRight - target) * targetLeft) / (srcRight - srcLeft) ); 2250 } 2251 return rv; 2252 } 2253 2254 /* 2255 * The linux ath9k driver and (from what I've been told) the reference 2256 * Atheros driver enables the 11n PHY by default whether or not it's 2257 * configured. 2258 */ 2259 static void 2260 ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan) 2261 { 2262 uint32_t phymode; 2263 uint32_t enableDacFifo = 0; 2264 HAL_HT_MACMODE macmode; /* MAC - 20/40 mode */ 2265 2266 if (AR_SREV_KITE_10_OR_LATER(ah)) 2267 enableDacFifo = (OS_REG_READ(ah, AR_PHY_TURBO) & AR_PHY_FC_ENABLE_DAC_FIFO); 2268 2269 /* Enable 11n HT, 20 MHz */ 2270 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 2271 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 2272 2273 /* Configure baseband for dynamic 20/40 operation */ 2274 if (IEEE80211_IS_CHAN_HT40(chan)) { 2275 phymode |= AR_PHY_FC_DYN2040_EN; 2276 2277 /* Configure control (primary) channel at +-10MHz */ 2278 if (IEEE80211_IS_CHAN_HT40U(chan)) 2279 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 2280 #if 0 2281 /* Configure 20/25 spacing */ 2282 if (ht->ht_extprotspacing == HAL_HT_EXTPROTSPACING_25) 2283 phymode |= AR_PHY_FC_DYN2040_EXT_CH; 2284 #endif 2285 macmode = HAL_HT_MACMODE_2040; 2286 } else 2287 macmode = HAL_HT_MACMODE_20; 2288 OS_REG_WRITE(ah, AR_PHY_TURBO, phymode); 2289 2290 /* Configure MAC for 20/40 operation */ 2291 ar5416Set11nMac2040(ah, macmode); 2292 2293 /* global transmit timeout (25 TUs default)*/ 2294 /* XXX - put this elsewhere??? */ 2295 OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S) ; 2296 2297 /* carrier sense timeout */ 2298 OS_REG_SET_BIT(ah, AR_GTTM, AR_GTTM_CST_USEC); 2299 OS_REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 2300 } 2301 2302 void 2303 ar5416GetChannelCenters(struct ath_hal *ah, 2304 const struct ieee80211_channel *chan, CHAN_CENTERS *centers) 2305 { 2306 uint16_t freq = ath_hal_gethwchannel(ah, chan); 2307 2308 centers->ctl_center = freq; 2309 centers->synth_center = freq; 2310 /* 2311 * In 20/40 phy mode, the center frequency is 2312 * "between" the control and extension channels. 2313 */ 2314 if (IEEE80211_IS_CHAN_HT40U(chan)) { 2315 centers->synth_center += HT40_CHANNEL_CENTER_SHIFT; 2316 centers->ext_center = 2317 centers->synth_center + HT40_CHANNEL_CENTER_SHIFT; 2318 } else if (IEEE80211_IS_CHAN_HT40D(chan)) { 2319 centers->synth_center -= HT40_CHANNEL_CENTER_SHIFT; 2320 centers->ext_center = 2321 centers->synth_center - HT40_CHANNEL_CENTER_SHIFT; 2322 } else { 2323 centers->ext_center = freq; 2324 } 2325 } 2326