1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #ifndef _ATH_AH_DECODE_H_ 22 #define _ATH_AH_DECODE_H_ 23 /* 24 * Register tracing support. 25 * 26 * Setting hw.ath.hal.alq=1 enables tracing of all register reads and 27 * writes to the file /tmp/ath_hal.log. The file format is a simple 28 * fixed-size array of records. When done logging set hw.ath.hal.alq=0 29 * and then decode the file with the arcode program (that is part of the 30 * HAL). If you start+stop tracing the data will be appended to an 31 * existing file. 32 */ 33 struct athregrec { 34 uint32_t threadid; 35 uint32_t op : 8, 36 reg : 24; 37 uint32_t val; 38 }; 39 40 enum { 41 OP_READ = 0, /* register read */ 42 OP_WRITE = 1, /* register write */ 43 OP_DEVICE = 2, /* device identification */ 44 OP_MARK = 3, /* application marker */ 45 }; 46 47 enum { 48 AH_MARK_RESET, /* ar*Reset entry, bChannelChange */ 49 AH_MARK_RESET_LINE, /* ar*_reset.c, line %d */ 50 AH_MARK_RESET_DONE, /* ar*Reset exit, error code */ 51 AH_MARK_CHIPRESET, /* ar*ChipReset, channel num */ 52 AH_MARK_PERCAL, /* ar*PerCalibration, channel num */ 53 AH_MARK_SETCHANNEL, /* ar*SetChannel, channel num */ 54 AH_MARK_ANI_RESET, /* ar*AniReset, opmode */ 55 AH_MARK_ANI_POLL, /* ar*AniReset, listen time */ 56 AH_MARK_ANI_CONTROL, /* ar*AniReset, cmd */ 57 AH_MARK_RX_CTL, /* RX DMA control */ 58 AH_MARK_CHIP_POWER, /* chip power control, mode */ 59 AH_MARK_CHIP_POWER_DONE, /* chip power control done, status */ 60 }; 61 62 enum { 63 AH_MARK_RX_CTL_PCU_START, 64 AH_MARK_RX_CTL_PCU_STOP, 65 AH_MARK_RX_CTL_DMA_START, 66 AH_MARK_RX_CTL_DMA_STOP, 67 AH_MARK_RX_CTL_DMA_STOP_ERR, 68 AH_MARK_RX_CTL_DMA_STOP_OK, 69 }; 70 71 #endif /* _ATH_AH_DECODE_H_ */ 72