1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/module.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/ata.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/malloc.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/stdarg.h> 43 #include <machine/resource.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/ata/ata-all.h> 49 #include <dev/ata/ata-pci.h> 50 #include <ata_if.h> 51 52 /* local prototypes */ 53 static int ata_serverworks_chipinit(device_t dev); 54 static int ata_serverworks_ch_attach(device_t dev); 55 static int ata_serverworks_ch_detach(device_t dev); 56 static void ata_serverworks_tf_read(struct ata_request *request); 57 static void ata_serverworks_tf_write(struct ata_request *request); 58 static int ata_serverworks_setmode(device_t dev, int target, int mode); 59 static void ata_serverworks_sata_reset(device_t dev); 60 static int ata_serverworks_status(device_t dev); 61 62 /* misc defines */ 63 #define SWKS_33 0 64 #define SWKS_66 1 65 #define SWKS_100 2 66 #define SWKS_MIO 3 67 68 /* 69 * ServerWorks chipset support functions 70 */ 71 static int 72 ata_serverworks_probe(device_t dev) 73 { 74 struct ata_pci_controller *ctlr = device_get_softc(dev); 75 static const struct ata_chip_id ids[] = 76 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_WDMA2, "ROSB4" }, 77 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" }, 78 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" }, 79 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" }, 80 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" }, 81 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" }, 82 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 83 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 84 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" }, 85 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" }, 86 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" }, 87 { 0, 0, 0, 0, 0, 0}}; 88 89 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID) 90 return ENXIO; 91 92 if (!(ctlr->chip = ata_match_chip(dev, ids))) 93 return ENXIO; 94 95 ata_set_desc(dev); 96 ctlr->chipinit = ata_serverworks_chipinit; 97 return (BUS_PROBE_LOW_PRIORITY); 98 } 99 100 static int 101 ata_serverworks_status(device_t dev) 102 { 103 struct ata_channel *ch = device_get_softc(dev); 104 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 105 106 /* 107 * Check if this interrupt belongs to our channel. 108 */ 109 if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit))) 110 return (0); 111 112 /* 113 * We need to do a 4-byte read on the status reg before the values 114 * will report correctly 115 */ 116 117 ATA_IDX_INL(ch,ATA_STATUS); 118 119 return ata_pci_status(dev); 120 } 121 122 static int 123 ata_serverworks_chipinit(device_t dev) 124 { 125 struct ata_pci_controller *ctlr = device_get_softc(dev); 126 127 if (ata_setup_interrupt(dev, ata_generic_intr)) 128 return ENXIO; 129 130 if (ctlr->chip->cfg1 == SWKS_MIO) { 131 ctlr->r_type2 = SYS_RES_MEMORY; 132 ctlr->r_rid2 = PCIR_BAR(5); 133 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 134 &ctlr->r_rid2, RF_ACTIVE))) 135 return ENXIO; 136 137 ctlr->channels = ctlr->chip->cfg2; 138 ctlr->ch_attach = ata_serverworks_ch_attach; 139 ctlr->ch_detach = ata_serverworks_ch_detach; 140 ctlr->setmode = ata_sata_setmode; 141 ctlr->getrev = ata_sata_getrev; 142 ctlr->reset = ata_serverworks_sata_reset; 143 return 0; 144 } 145 else if (ctlr->chip->cfg1 == SWKS_33) { 146 device_t *children; 147 int nchildren, i; 148 149 /* locate the ISA part in the southbridge and enable UDMA33 */ 150 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 151 for (i = 0; i < nchildren; i++) { 152 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 153 pci_write_config(children[i], 0x64, 154 (pci_read_config(children[i], 0x64, 4) & 155 ~0x00002000) | 0x00004000, 4); 156 break; 157 } 158 } 159 free(children, M_TEMP); 160 } 161 } 162 else { 163 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x40) | 164 ((ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02), 1); 165 } 166 ctlr->setmode = ata_serverworks_setmode; 167 return 0; 168 } 169 170 static int 171 ata_serverworks_ch_attach(device_t dev) 172 { 173 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 174 struct ata_channel *ch = device_get_softc(dev); 175 int ch_offset; 176 int i; 177 178 ch_offset = ch->unit * 0x100; 179 180 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 181 ch->r_io[i].res = ctlr->r_res2; 182 183 /* setup ATA registers */ 184 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 185 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 186 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 187 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 188 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 189 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 190 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 191 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 192 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 193 ata_default_registers(dev); 194 195 /* setup DMA registers */ 196 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 197 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 198 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 199 200 /* setup SATA registers */ 201 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 202 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 203 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 204 205 ch->flags |= ATA_NO_SLAVE | ATA_SATA | ATA_KNOWN_PRESENCE; 206 ata_pci_hw(dev); 207 ch->hw.tf_read = ata_serverworks_tf_read; 208 ch->hw.tf_write = ata_serverworks_tf_write; 209 210 if (ctlr->chip->chipid == ATA_K2) { 211 /* 212 * Set SICR registers to turn off waiting for a status message 213 * before sending FIS. Values obtained from the Darwin driver. 214 */ 215 216 ATA_OUTL(ctlr->r_res2, ch_offset + 0x80, 217 ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000); 218 ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0); 219 220 /* 221 * Some controllers have a bug where they will send the command 222 * to the drive before seeing a DMA start, and then can begin 223 * receiving data before the DMA start arrives. The controller 224 * will then become confused and either corrupt the data or crash. 225 * Remedy this by starting DMA before sending the drive command. 226 */ 227 228 ch->flags |= ATA_DMA_BEFORE_CMD; 229 230 /* 231 * The status register must be read as a long to fill the other 232 * registers. 233 */ 234 235 ch->hw.status = ata_serverworks_status; 236 ch->flags |= ATA_STATUS_IS_LONG; 237 } 238 239 /* chip does not reliably do 64K DMA transfers */ 240 ch->dma.max_iosize = 64 * DEV_BSIZE; 241 242 ata_pci_dmainit(dev); 243 244 return 0; 245 } 246 247 static int 248 ata_serverworks_ch_detach(device_t dev) 249 { 250 251 ata_pci_dmafini(dev); 252 return (0); 253 } 254 255 static void 256 ata_serverworks_tf_read(struct ata_request *request) 257 { 258 struct ata_channel *ch = device_get_softc(request->parent); 259 260 if (request->flags & ATA_R_48BIT) { 261 u_int16_t temp; 262 263 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT); 264 temp = ATA_IDX_INW(ch, ATA_SECTOR); 265 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) | 266 ((u_int64_t)(temp & 0xff00) << 24); 267 temp = ATA_IDX_INW(ch, ATA_CYL_LSB); 268 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) | 269 ((u_int64_t)(temp & 0xff00) << 32); 270 temp = ATA_IDX_INW(ch, ATA_CYL_MSB); 271 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) | 272 ((u_int64_t)(temp & 0xff00) << 40); 273 } 274 else { 275 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff; 276 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) | 277 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) | 278 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) | 279 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24); 280 } 281 } 282 283 static void 284 ata_serverworks_tf_write(struct ata_request *request) 285 { 286 struct ata_channel *ch = device_get_softc(request->parent); 287 288 if (request->flags & ATA_R_48BIT) { 289 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 290 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 291 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 292 (request->u.ata.lba & 0x00ff)); 293 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 294 ((request->u.ata.lba >> 8) & 0x00ff)); 295 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 296 ((request->u.ata.lba >> 16) & 0x00ff)); 297 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 298 } 299 else { 300 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 301 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 302 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba); 303 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 304 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 305 ATA_IDX_OUTW(ch, ATA_DRIVE, 306 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 307 ((request->u.ata.lba >> 24) & 0x0f)); 308 } 309 } 310 311 static int 312 ata_serverworks_setmode(device_t dev, int target, int mode) 313 { 314 device_t parent = device_get_parent(dev); 315 struct ata_pci_controller *ctlr = device_get_softc(parent); 316 struct ata_channel *ch = device_get_softc(dev); 317 int devno = (ch->unit << 1) + target; 318 int offset = (devno ^ 0x01) << 3; 319 int piomode; 320 static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 321 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 322 323 mode = min(mode, ctlr->chip->max_dma); 324 if (mode >= ATA_UDMA0) { 325 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */ 326 pci_write_config(parent, 0x56, 327 (pci_read_config(parent, 0x56, 2) & 328 ~(0xf << (devno << 2))) | 329 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 330 pci_write_config(parent, 0x54, 331 pci_read_config(parent, 0x54, 1) | 332 (0x01 << devno), 1); 333 pci_write_config(parent, 0x44, 334 (pci_read_config(parent, 0x44, 4) & 335 ~(0xff << offset)) | 336 (dmatimings[2] << offset), 4); 337 piomode = ATA_PIO4; 338 } else if (mode >= ATA_WDMA0) { 339 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */ 340 pci_write_config(parent, 0x54, 341 pci_read_config(parent, 0x54, 1) & 342 ~(0x01 << devno), 1); 343 pci_write_config(parent, 0x44, 344 (pci_read_config(parent, 0x44, 4) & 345 ~(0xff << offset)) | 346 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 347 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 348 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 349 } else { 350 /* Disable UDMA, set requested PIO. */ 351 pci_write_config(parent, 0x54, 352 pci_read_config(parent, 0x54, 1) & 353 ~(0x01 << devno), 1); 354 piomode = mode; 355 } 356 /* Set PIO mode and timings, calculated above. */ 357 if (ctlr->chip->cfg1 != SWKS_33) { 358 pci_write_config(parent, 0x4a, 359 (pci_read_config(parent, 0x4a, 2) & 360 ~(0xf << (devno << 2))) | 361 ((piomode - ATA_PIO0) << (devno<<2)),2); 362 } 363 pci_write_config(parent, 0x40, 364 (pci_read_config(parent, 0x40, 4) & 365 ~(0xff << offset)) | 366 (piotimings[ata_mode2idx(piomode)] << offset), 4); 367 return (mode); 368 } 369 370 static void 371 ata_serverworks_sata_reset(device_t dev) 372 { 373 struct ata_channel *ch = device_get_softc(dev); 374 375 if (ata_sata_phy_reset(dev, -1, 0)) 376 ata_generic_reset(dev); 377 else 378 ch->devices = 0; 379 } 380 381 ATA_DECLARE_DRIVER(ata_serverworks); 382