1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_nvidia_chipinit(device_t dev); 56 static int ata_nvidia_ch_attach(device_t dev); 57 static int ata_nvidia_status(device_t dev); 58 static void ata_nvidia_reset(device_t dev); 59 static void ata_nvidia_setmode(device_t dev, int mode); 60 61 /* misc defines */ 62 #define NV4 0x01 63 #define NVQ 0x02 64 #define NVAHCI 0x04 65 66 67 /* 68 * nVidia chipset support functions 69 */ 70 static int 71 ata_nvidia_probe(device_t dev) 72 { 73 struct ata_pci_controller *ctlr = device_get_softc(dev); 74 static struct ata_chip_id ids[] = 75 {{ ATA_NFORCE1, 0, 0, 0, ATA_UDMA5, "nForce" }, 76 { ATA_NFORCE2, 0, 0, 0, ATA_UDMA6, "nForce2" }, 77 { ATA_NFORCE2_PRO, 0, 0, 0, ATA_UDMA6, "nForce2 Pro" }, 78 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 79 { ATA_NFORCE3, 0, 0, 0, ATA_UDMA6, "nForce3" }, 80 { ATA_NFORCE3_PRO, 0, 0, 0, ATA_UDMA6, "nForce3 Pro" }, 81 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 82 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 83 { ATA_NFORCE_MCP04, 0, 0, 0, ATA_UDMA6, "nForce MCP" }, 84 { ATA_NFORCE_MCP04_S1, 0, NV4, 0, ATA_SA150, "nForce MCP" }, 85 { ATA_NFORCE_MCP04_S2, 0, NV4, 0, ATA_SA150, "nForce MCP" }, 86 { ATA_NFORCE_CK804, 0, 0, 0, ATA_UDMA6, "nForce CK804" }, 87 { ATA_NFORCE_CK804_S1, 0, NV4, 0, ATA_SA300, "nForce CK804" }, 88 { ATA_NFORCE_CK804_S2, 0, NV4, 0, ATA_SA300, "nForce CK804" }, 89 { ATA_NFORCE_MCP51, 0, 0, 0, ATA_UDMA6, "nForce MCP51" }, 90 { ATA_NFORCE_MCP51_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" }, 91 { ATA_NFORCE_MCP51_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" }, 92 { ATA_NFORCE_MCP55, 0, 0, 0, ATA_UDMA6, "nForce MCP55" }, 93 { ATA_NFORCE_MCP55_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" }, 94 { ATA_NFORCE_MCP55_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" }, 95 { ATA_NFORCE_MCP61, 0, 0, 0, ATA_UDMA6, "nForce MCP61" }, 96 { ATA_NFORCE_MCP61_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 97 { ATA_NFORCE_MCP61_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 98 { ATA_NFORCE_MCP61_S3, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 99 { ATA_NFORCE_MCP65, 0, 0, 0, ATA_UDMA6, "nForce MCP65" }, 100 { ATA_NFORCE_MCP65_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 101 { ATA_NFORCE_MCP65_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 102 { ATA_NFORCE_MCP65_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 103 { ATA_NFORCE_MCP65_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 104 { ATA_NFORCE_MCP65_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 105 { ATA_NFORCE_MCP65_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 106 { ATA_NFORCE_MCP65_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 107 { ATA_NFORCE_MCP65_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 108 { ATA_NFORCE_MCP67, 0, 0, 0, ATA_UDMA6, "nForce MCP67" }, 109 { ATA_NFORCE_MCP67_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 110 { ATA_NFORCE_MCP67_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 111 { ATA_NFORCE_MCP67_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 112 { ATA_NFORCE_MCP67_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 113 { ATA_NFORCE_MCP67_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 114 { ATA_NFORCE_MCP67_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 115 { ATA_NFORCE_MCP67_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 116 { ATA_NFORCE_MCP67_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 117 { ATA_NFORCE_MCP67_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 118 { ATA_NFORCE_MCP67_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 119 { ATA_NFORCE_MCP67_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 120 { ATA_NFORCE_MCP67_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 121 { ATA_NFORCE_MCP67_AC, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 122 { ATA_NFORCE_MCP73, 0, 0, 0, ATA_UDMA6, "nForce MCP73" }, 123 { ATA_NFORCE_MCP73_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 124 { ATA_NFORCE_MCP73_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 125 { ATA_NFORCE_MCP73_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 126 { ATA_NFORCE_MCP73_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 127 { ATA_NFORCE_MCP73_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 128 { ATA_NFORCE_MCP73_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 129 { ATA_NFORCE_MCP73_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 130 { ATA_NFORCE_MCP73_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 131 { ATA_NFORCE_MCP73_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 132 { ATA_NFORCE_MCP73_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 133 { ATA_NFORCE_MCP73_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 134 { ATA_NFORCE_MCP73_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 135 { ATA_NFORCE_MCP77, 0, 0, 0, ATA_UDMA6, "nForce MCP77" }, 136 { ATA_NFORCE_MCP77_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 137 { ATA_NFORCE_MCP77_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 138 { ATA_NFORCE_MCP77_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 139 { ATA_NFORCE_MCP77_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 140 { ATA_NFORCE_MCP77_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 141 { ATA_NFORCE_MCP77_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 142 { ATA_NFORCE_MCP77_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 143 { ATA_NFORCE_MCP77_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 144 { ATA_NFORCE_MCP77_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 145 { ATA_NFORCE_MCP77_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 146 { ATA_NFORCE_MCP77_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 147 { ATA_NFORCE_MCP77_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 148 { ATA_NFORCE_MCP79_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 149 { ATA_NFORCE_MCP79_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 150 { ATA_NFORCE_MCP79_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 151 { ATA_NFORCE_MCP79_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 152 { ATA_NFORCE_MCP79_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 153 { ATA_NFORCE_MCP79_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 154 { ATA_NFORCE_MCP79_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 155 { ATA_NFORCE_MCP79_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 156 { ATA_NFORCE_MCP79_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 157 { ATA_NFORCE_MCP79_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 158 { ATA_NFORCE_MCP79_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 159 { ATA_NFORCE_MCP79_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 160 { ATA_NFORCE_MCP89_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 161 { ATA_NFORCE_MCP89_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 162 { ATA_NFORCE_MCP89_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 163 { ATA_NFORCE_MCP89_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 164 { ATA_NFORCE_MCP89_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 165 { ATA_NFORCE_MCP89_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 166 { ATA_NFORCE_MCP89_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 167 { ATA_NFORCE_MCP89_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 168 { ATA_NFORCE_MCP89_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 169 { ATA_NFORCE_MCP89_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 170 { ATA_NFORCE_MCP89_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 171 { ATA_NFORCE_MCP89_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 172 { 0, 0, 0, 0, 0, 0}} ; 173 174 if (pci_get_vendor(dev) != ATA_NVIDIA_ID) 175 return ENXIO; 176 177 if (!(ctlr->chip = ata_match_chip(dev, ids))) 178 return ENXIO; 179 180 ata_set_desc(dev); 181 if (ctlr->chip->cfg1 & NVAHCI) 182 ctlr->chipinit = ata_ahci_chipinit; 183 else 184 ctlr->chipinit = ata_nvidia_chipinit; 185 return (BUS_PROBE_DEFAULT); 186 } 187 188 static int 189 ata_nvidia_chipinit(device_t dev) 190 { 191 struct ata_pci_controller *ctlr = device_get_softc(dev); 192 193 if (ata_setup_interrupt(dev, ata_generic_intr)) 194 return ENXIO; 195 196 if (ctlr->chip->max_dma >= ATA_SA150) { 197 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 198 ctlr->r_type2 = SYS_RES_IOPORT; 199 else 200 ctlr->r_type2 = SYS_RES_MEMORY; 201 ctlr->r_rid2 = PCIR_BAR(5); 202 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 203 &ctlr->r_rid2, RF_ACTIVE))) { 204 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; 205 206 ctlr->ch_attach = ata_nvidia_ch_attach; 207 ctlr->ch_detach = ata_pci_ch_detach; 208 ctlr->reset = ata_nvidia_reset; 209 210 /* enable control access */ 211 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 212 /* MCP55 seems to need some time to allow r_res2 read. */ 213 DELAY(10); 214 if (ctlr->chip->cfg1 & NVQ) { 215 /* clear interrupt status */ 216 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 217 218 /* enable device and PHY state change interrupts */ 219 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 220 221 /* disable NCQ support */ 222 ATA_OUTL(ctlr->r_res2, 0x0400, 223 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 224 } 225 else { 226 /* clear interrupt status */ 227 ATA_OUTB(ctlr->r_res2, offset, 0xff); 228 229 /* enable device and PHY state change interrupts */ 230 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 231 } 232 } 233 ctlr->setmode = ata_sata_setmode; 234 } 235 else { 236 /* disable prefetch, postwrite */ 237 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 238 ctlr->setmode = ata_nvidia_setmode; 239 } 240 return 0; 241 } 242 243 static int 244 ata_nvidia_ch_attach(device_t dev) 245 { 246 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 247 struct ata_channel *ch = device_get_softc(dev); 248 249 /* setup the usual register normal pci style */ 250 if (ata_pci_ch_attach(dev)) 251 return ENXIO; 252 253 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 254 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 255 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 256 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 257 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 258 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 259 260 ch->hw.status = ata_nvidia_status; 261 ch->flags |= ATA_NO_SLAVE; 262 263 return 0; 264 } 265 266 static int 267 ata_nvidia_status(device_t dev) 268 { 269 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 270 struct ata_channel *ch = device_get_softc(dev); 271 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; 272 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); 273 u_int32_t istatus; 274 275 /* get interrupt status */ 276 if (ctlr->chip->cfg1 & NVQ) 277 istatus = ATA_INL(ctlr->r_res2, offset); 278 else 279 istatus = ATA_INB(ctlr->r_res2, offset); 280 281 /* do we have any PHY events ? */ 282 if (istatus & (0x0c << shift)) 283 ata_sata_phy_check_events(dev); 284 285 /* clear interrupt(s) */ 286 if (ctlr->chip->cfg1 & NVQ) 287 ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0); 288 else 289 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift)); 290 291 /* do we have any device action ? */ 292 return (istatus & (0x01 << shift)); 293 } 294 295 static void 296 ata_nvidia_reset(device_t dev) 297 { 298 if (ata_sata_phy_reset(dev, -1, 1)) 299 ata_generic_reset(dev); 300 } 301 302 static void 303 ata_nvidia_setmode(device_t dev, int mode) 304 { 305 device_t gparent = GRANDPARENT(dev); 306 struct ata_pci_controller *ctlr = device_get_softc(gparent); 307 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 308 struct ata_device *atadev = device_get_softc(dev); 309 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20, 310 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 311 int modes[7] = { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }; 312 int devno = (ch->unit << 1) + atadev->unit; 313 int reg = 0x63 - devno; 314 int error; 315 316 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 317 mode = ata_check_80pin(dev, mode); 318 319 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 320 if (bootverbose) 321 device_printf(dev, "%ssetting %s on %s chip\n", 322 (error) ? "FAILURE " : "", ata_mode2str(mode), 323 ctlr->chip->text); 324 if (!error) { 325 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1); 326 if (mode >= ATA_UDMA0) 327 pci_write_config(gparent, reg, modes[mode & ATA_MODE_MASK], 1); 328 else 329 pci_write_config(gparent, reg, 0x8b, 1); 330 atadev->mode = mode; 331 } 332 } 333 334 ATA_DECLARE_DRIVER(ata_nvidia); 335 MODULE_DEPEND(ata_nvidia, ata_ahci, 1, 1, 1); 336