1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_marvell_chipinit(device_t dev); 56 static int ata_marvell_ch_attach(device_t dev); 57 static void ata_marvell_setmode(device_t dev, int mode); 58 static int ata_marvell_edma_ch_attach(device_t dev); 59 static int ata_marvell_edma_ch_detach(device_t dev); 60 static int ata_marvell_edma_status(device_t dev); 61 static int ata_marvell_edma_begin_transaction(struct ata_request *request); 62 static int ata_marvell_edma_end_transaction(struct ata_request *request); 63 static void ata_marvell_edma_reset(device_t dev); 64 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 65 static void ata_marvell_edma_dmainit(device_t dev); 66 67 /* misc defines */ 68 #define MV_50XX 50 69 #define MV_60XX 60 70 #define MV_6042 62 71 #define MV_7042 72 72 #define MV_61XX 61 73 74 75 /* 76 * Marvell chipset support functions 77 */ 78 #define ATA_MV_HOST_BASE(ch) \ 79 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000) 80 #define ATA_MV_EDMA_BASE(ch) \ 81 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000) 82 83 struct ata_marvell_response { 84 u_int16_t tag; 85 u_int8_t edma_status; 86 u_int8_t dev_status; 87 u_int32_t timestamp; 88 }; 89 90 struct ata_marvell_dma_prdentry { 91 u_int32_t addrlo; 92 u_int32_t count; 93 u_int32_t addrhi; 94 u_int32_t reserved; 95 }; 96 97 static int 98 ata_marvell_probe(device_t dev) 99 { 100 struct ata_pci_controller *ctlr = device_get_softc(dev); 101 static struct ata_chip_id ids[] = 102 {{ ATA_M88SX5040, 0, 4, MV_50XX, ATA_SA150, "88SX5040" }, 103 { ATA_M88SX5041, 0, 4, MV_50XX, ATA_SA150, "88SX5041" }, 104 { ATA_M88SX5080, 0, 8, MV_50XX, ATA_SA150, "88SX5080" }, 105 { ATA_M88SX5081, 0, 8, MV_50XX, ATA_SA150, "88SX5081" }, 106 { ATA_M88SX6041, 0, 4, MV_60XX, ATA_SA300, "88SX6041" }, 107 { ATA_M88SX6042, 0, 4, MV_6042, ATA_SA300, "88SX6042" }, 108 { ATA_M88SX6081, 0, 8, MV_60XX, ATA_SA300, "88SX6081" }, 109 { ATA_M88SX7042, 0, 4, MV_7042, ATA_SA300, "88SX7042" }, 110 { ATA_M88SX6101, 0, 0, MV_61XX, ATA_UDMA6, "88SX6101" }, 111 { ATA_M88SX6102, 0, 0, MV_61XX, ATA_UDMA6, "88SX6102" }, 112 { ATA_M88SX6111, 0, 1, MV_61XX, ATA_UDMA6, "88SX6111" }, 113 { ATA_M88SX6121, 0, 2, MV_61XX, ATA_UDMA6, "88SX6121" }, 114 { ATA_M88SX6141, 0, 4, MV_61XX, ATA_UDMA6, "88SX6141" }, 115 { ATA_M88SX6145, 0, 4, MV_61XX, ATA_UDMA6, "88SX6145" }, 116 { 0, 0, 0, 0, 0, 0}}; 117 118 if (pci_get_vendor(dev) != ATA_MARVELL_ID) 119 return ENXIO; 120 121 if (!(ctlr->chip = ata_match_chip(dev, ids))) 122 return ENXIO; 123 124 ata_set_desc(dev); 125 126 switch (ctlr->chip->cfg2) { 127 case MV_50XX: 128 case MV_60XX: 129 case MV_6042: 130 case MV_7042: 131 ctlr->chipinit = ata_marvell_edma_chipinit; 132 break; 133 case MV_61XX: 134 ctlr->chipinit = ata_marvell_chipinit; 135 break; 136 } 137 return (BUS_PROBE_DEFAULT); 138 } 139 140 static int 141 ata_marvell_chipinit(device_t dev) 142 { 143 struct ata_pci_controller *ctlr = device_get_softc(dev); 144 device_t child; 145 146 if (ata_setup_interrupt(dev, ata_generic_intr)) 147 return ENXIO; 148 /* Create AHCI subdevice if AHCI part present. */ 149 if (ctlr->chip->cfg1) { 150 child = device_add_child(dev, NULL, -1); 151 if (child != NULL) { 152 device_set_ivars(child, (void *)(intptr_t)-1); 153 bus_generic_attach(dev); 154 } 155 } 156 ctlr->ch_attach = ata_marvell_ch_attach; 157 ctlr->ch_detach = ata_pci_ch_detach; 158 ctlr->reset = ata_generic_reset; 159 ctlr->setmode = ata_marvell_setmode; 160 ctlr->channels = 1; 161 return (0); 162 } 163 164 static int 165 ata_marvell_ch_attach(device_t dev) 166 { 167 struct ata_channel *ch = device_get_softc(dev); 168 int error; 169 170 error = ata_pci_ch_attach(dev); 171 /* dont use 32 bit PIO transfers */ 172 ch->flags |= ATA_USE_16BIT; 173 return (error); 174 } 175 176 static void 177 ata_marvell_setmode(device_t dev, int mode) 178 { 179 device_t gparent = GRANDPARENT(dev); 180 struct ata_pci_controller *ctlr = device_get_softc(gparent); 181 struct ata_device *atadev = device_get_softc(dev); 182 183 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 184 mode = ata_check_80pin(dev, mode); 185 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 186 atadev->mode = mode; 187 } 188 189 int 190 ata_marvell_edma_chipinit(device_t dev) 191 { 192 struct ata_pci_controller *ctlr = device_get_softc(dev); 193 194 if (ata_setup_interrupt(dev, ata_generic_intr)) 195 return ENXIO; 196 197 ctlr->r_type1 = SYS_RES_MEMORY; 198 ctlr->r_rid1 = PCIR_BAR(0); 199 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 200 &ctlr->r_rid1, RF_ACTIVE))) 201 return ENXIO; 202 203 /* mask all host controller interrupts */ 204 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); 205 206 /* mask all PCI interrupts */ 207 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); 208 209 ctlr->ch_attach = ata_marvell_edma_ch_attach; 210 ctlr->ch_detach = ata_marvell_edma_ch_detach; 211 ctlr->reset = ata_marvell_edma_reset; 212 ctlr->setmode = ata_sata_setmode; 213 ctlr->channels = ctlr->chip->cfg1; 214 215 /* clear host controller interrupts */ 216 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); 217 if (ctlr->chip->cfg1 > 4) 218 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); 219 220 /* clear PCI interrupts */ 221 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); 222 223 /* unmask PCI interrupts we want */ 224 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); 225 226 /* unmask host controller interrupts we want */ 227 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | 228 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); 229 230 return 0; 231 } 232 233 static int 234 ata_marvell_edma_ch_attach(device_t dev) 235 { 236 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 237 struct ata_channel *ch = device_get_softc(dev); 238 u_int64_t work; 239 int i; 240 241 ata_marvell_edma_dmainit(dev); 242 work = ch->dma.work_bus; 243 /* clear work area */ 244 bzero(ch->dma.work, 1024+256); 245 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 246 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 247 248 /* set legacy ATA resources */ 249 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 250 ch->r_io[i].res = ctlr->r_res1; 251 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); 252 } 253 ch->r_io[ATA_CONTROL].res = ctlr->r_res1; 254 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); 255 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; 256 ata_default_registers(dev); 257 258 /* set SATA resources */ 259 switch (ctlr->chip->cfg2) { 260 case MV_50XX: 261 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 262 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); 263 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 264 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); 265 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 266 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); 267 break; 268 case MV_60XX: 269 case MV_6042: 270 case MV_7042: 271 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 272 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); 273 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 274 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); 275 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 276 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); 277 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; 278 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); 279 break; 280 } 281 282 ch->flags |= ATA_NO_SLAVE; 283 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ 284 ata_generic_hw(dev); 285 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction; 286 ch->hw.end_transaction = ata_marvell_edma_end_transaction; 287 ch->hw.status = ata_marvell_edma_status; 288 289 /* disable the EDMA machinery */ 290 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 291 DELAY(100000); /* SOS should poll for disabled */ 292 293 /* set configuration to non-queued 128b read transfers stop on error */ 294 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); 295 296 /* request queue base high */ 297 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32); 298 299 /* request queue in ptr */ 300 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 301 302 /* request queue out ptr */ 303 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); 304 305 /* response queue base high */ 306 work += 1024; 307 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32); 308 309 /* response queue in ptr */ 310 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); 311 312 /* response queue out ptr */ 313 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 314 315 /* clear SATA error register */ 316 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 317 318 /* clear any outstanding error interrupts */ 319 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 320 321 /* unmask all error interrupts */ 322 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 323 324 /* enable EDMA machinery */ 325 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 326 return 0; 327 } 328 329 static int 330 ata_marvell_edma_ch_detach(device_t dev) 331 { 332 struct ata_channel *ch = device_get_softc(dev); 333 334 if (ch->dma.work_tag && ch->dma.work_map) 335 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 336 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 337 ata_dmafini(dev); 338 return (0); 339 } 340 341 static int 342 ata_marvell_edma_status(device_t dev) 343 { 344 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 345 struct ata_channel *ch = device_get_softc(dev); 346 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60); 347 int shift = (ch->unit << 1) + (ch->unit > 3); 348 349 if (cause & (1 << shift)) { 350 351 /* clear interrupt(s) */ 352 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 353 354 /* do we have any PHY events ? */ 355 ata_sata_phy_check_events(dev); 356 } 357 358 /* do we have any device action ? */ 359 return (cause & (2 << shift)); 360 } 361 362 /* must be called with ATA channel locked and state_mtx held */ 363 static int 364 ata_marvell_edma_begin_transaction(struct ata_request *request) 365 { 366 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 367 struct ata_channel *ch = device_get_softc(request->parent); 368 u_int32_t req_in; 369 u_int8_t *bytep; 370 int i; 371 int error, slot; 372 373 /* only DMA R/W goes through the EMDA machine */ 374 if (request->u.ata.command != ATA_READ_DMA && 375 request->u.ata.command != ATA_WRITE_DMA && 376 request->u.ata.command != ATA_READ_DMA48 && 377 request->u.ata.command != ATA_WRITE_DMA48) { 378 379 /* disable the EDMA machinery */ 380 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001) 381 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 382 return ata_begin_transaction(request); 383 } 384 385 /* check sanity, setup SG list and DMA engine */ 386 if ((error = ch->dma.load(request, NULL, NULL))) { 387 device_printf(request->parent, "setting up DMA failed\n"); 388 request->result = error; 389 return ATA_OP_FINISHED; 390 } 391 392 /* get next free request queue slot */ 393 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch)); 394 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; 395 bytep = (u_int8_t *)(ch->dma.work); 396 bytep += (slot << 5); 397 398 /* fill in this request */ 399 le32enc(bytep + 0 * sizeof(u_int32_t), 400 request->dma->sg_bus & 0xffffffff); 401 le32enc(bytep + 1 * sizeof(u_int32_t), 402 (u_int64_t)request->dma->sg_bus >> 32); 403 if (ctlr->chip->cfg2 != MV_6042 && ctlr->chip->cfg2 != MV_7042) { 404 le16enc(bytep + 4 * sizeof(u_int16_t), 405 (request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag << 1)); 406 407 i = 10; 408 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 409 bytep[i++] = 0x10 | ATA_COUNT; 410 bytep[i++] = request->u.ata.count & 0xff; 411 bytep[i++] = 0x10 | ATA_COUNT; 412 413 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 414 bytep[i++] = 0x10 | ATA_SECTOR; 415 bytep[i++] = request->u.ata.lba & 0xff; 416 bytep[i++] = 0x10 | ATA_SECTOR; 417 418 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 419 bytep[i++] = 0x10 | ATA_CYL_LSB; 420 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 421 bytep[i++] = 0x10 | ATA_CYL_LSB; 422 423 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 424 bytep[i++] = 0x10 | ATA_CYL_MSB; 425 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 426 bytep[i++] = 0x10 | ATA_CYL_MSB; 427 428 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf); 429 bytep[i++] = 0x10 | ATA_DRIVE; 430 431 bytep[i++] = request->u.ata.command; 432 bytep[i++] = 0x90 | ATA_COMMAND; 433 } else { 434 le32enc(bytep + 2 * sizeof(u_int32_t), 435 (request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag << 1)); 436 437 i = 16; 438 bytep[i++] = 0; 439 bytep[i++] = 0; 440 bytep[i++] = request->u.ata.command; 441 bytep[i++] = request->u.ata.feature & 0xff; 442 443 bytep[i++] = request->u.ata.lba & 0xff; 444 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 445 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 446 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0x0f); 447 448 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 449 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 450 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 451 bytep[i++] = (request->u.ata.feature >> 8) & 0xff; 452 453 bytep[i++] = request->u.ata.count & 0xff; 454 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 455 bytep[i++] = 0; 456 bytep[i++] = 0; 457 } 458 459 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 460 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 461 462 /* enable EDMA machinery if needed */ 463 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { 464 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 465 while (!(ATA_INL(ctlr->r_res1, 466 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 467 DELAY(10); 468 } 469 470 /* tell EDMA it has a new request */ 471 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f; 472 req_in &= 0xfffffc00; 473 req_in += (slot << 5); 474 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in); 475 476 return ATA_OP_CONTINUES; 477 } 478 479 /* must be called with ATA channel locked and state_mtx held */ 480 static int 481 ata_marvell_edma_end_transaction(struct ata_request *request) 482 { 483 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 484 struct ata_channel *ch = device_get_softc(request->parent); 485 int offset = (ch->unit > 3 ? 0x30014 : 0x20014); 486 u_int32_t icr = ATA_INL(ctlr->r_res1, offset); 487 int res; 488 489 /* EDMA interrupt */ 490 if ((icr & (0x0001 << (ch->unit & 3)))) { 491 struct ata_marvell_response *response; 492 u_int32_t rsp_in, rsp_out; 493 int slot; 494 495 /* stop timeout */ 496 callout_stop(&request->callout); 497 498 /* get response ptr's */ 499 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch)); 500 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch)); 501 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; 502 rsp_out &= 0xffffff00; 503 rsp_out += (slot << 3); 504 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 505 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 506 response = (struct ata_marvell_response *) 507 (ch->dma.work + 1024 + (slot << 3)); 508 509 /* record status for this request */ 510 request->status = response->dev_status; 511 request->error = 0; 512 513 /* ack response */ 514 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out); 515 516 /* update progress */ 517 if (!(request->status & ATA_S_ERROR) && 518 !(request->flags & ATA_R_TIMEOUT)) 519 request->donecount = request->bytecount; 520 521 /* unload SG list */ 522 ch->dma.unload(request); 523 524 res = ATA_OP_FINISHED; 525 } 526 527 /* legacy ATA interrupt */ 528 else { 529 res = ata_end_transaction(request); 530 } 531 532 /* ack interrupt */ 533 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3)))); 534 return res; 535 } 536 537 static void 538 ata_marvell_edma_reset(device_t dev) 539 { 540 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 541 struct ata_channel *ch = device_get_softc(dev); 542 543 /* disable the EDMA machinery */ 544 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 545 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 546 DELAY(10); 547 548 /* clear SATA error register */ 549 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 550 551 /* clear any outstanding error interrupts */ 552 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 553 554 /* unmask all error interrupts */ 555 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 556 557 /* enable channel and test for devices */ 558 if (ata_sata_phy_reset(dev, -1, 1)) 559 ata_generic_reset(dev); 560 561 /* enable EDMA machinery */ 562 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 563 } 564 565 static void 566 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, 567 int error) 568 { 569 struct ata_dmasetprd_args *args = xsc; 570 struct ata_marvell_dma_prdentry *prd = args->dmatab; 571 int i; 572 573 if ((args->error = error)) 574 return; 575 576 for (i = 0; i < nsegs; i++) { 577 prd[i].addrlo = htole32(segs[i].ds_addr); 578 prd[i].count = htole32(segs[i].ds_len); 579 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32); 580 prd[i].reserved = 0; 581 } 582 prd[i - 1].count |= htole32(ATA_DMA_EOT); 583 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 584 args->nsegs = nsegs; 585 } 586 587 static void 588 ata_marvell_edma_dmainit(device_t dev) 589 { 590 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 591 struct ata_channel *ch = device_get_softc(dev); 592 593 ata_dmainit(dev); 594 /* note start and stop are not used here */ 595 ch->dma.setprd = ata_marvell_edma_dmasetprd; 596 597 /* if 64bit support present adjust max address used */ 598 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004) 599 ch->dma.max_address = BUS_SPACE_MAXADDR; 600 601 /* chip does not reliably do 64K DMA transfers */ 602 if (ctlr->chip->cfg2 == MV_50XX || ctlr->chip->cfg2 == MV_60XX) 603 ch->dma.max_iosize = 64 * DEV_BSIZE; 604 else 605 ch->dma.max_iosize = (ATA_DMA_ENTRIES - 1) * PAGE_SIZE; 606 } 607 608 ATA_DECLARE_DRIVER(ata_marvell); 609