1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/module.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/ata.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/malloc.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/stdarg.h> 43 #include <machine/resource.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/ata/ata-all.h> 49 #include <dev/ata/ata-pci.h> 50 #include <ata_if.h> 51 52 /* local prototypes */ 53 static int ata_intel_chipinit(device_t dev); 54 static int ata_intel_chipdeinit(device_t dev); 55 static int ata_intel_ch_attach(device_t dev); 56 static void ata_intel_reset(device_t dev); 57 static int ata_intel_old_setmode(device_t dev, int target, int mode); 58 static int ata_intel_new_setmode(device_t dev, int target, int mode); 59 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 60 static int ata_intel_sata_getrev(device_t dev, int target); 61 static int ata_intel_sata_status(device_t dev); 62 static int ata_intel_sata_ahci_read(device_t dev, int port, 63 int reg, u_int32_t *result); 64 static int ata_intel_sata_cscr_read(device_t dev, int port, 65 int reg, u_int32_t *result); 66 static int ata_intel_sata_sidpr_read(device_t dev, int port, 67 int reg, u_int32_t *result); 68 static int ata_intel_sata_ahci_write(device_t dev, int port, 69 int reg, u_int32_t result); 70 static int ata_intel_sata_cscr_write(device_t dev, int port, 71 int reg, u_int32_t result); 72 static int ata_intel_sata_sidpr_write(device_t dev, int port, 73 int reg, u_int32_t result); 74 static int ata_intel_sata_sidpr_test(device_t dev); 75 static int ata_intel_31244_ch_attach(device_t dev); 76 static int ata_intel_31244_ch_detach(device_t dev); 77 static int ata_intel_31244_status(device_t dev); 78 static void ata_intel_31244_tf_write(struct ata_request *request); 79 static void ata_intel_31244_reset(device_t dev); 80 81 /* misc defines */ 82 #define INTEL_ICH5 2 83 #define INTEL_6CH 4 84 #define INTEL_6CH2 8 85 #define INTEL_ICH7 16 86 87 struct ata_intel_data { 88 struct mtx lock; 89 u_char smap[4]; 90 }; 91 92 #define ATA_INTEL_SMAP(ctlr, ch) \ 93 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2] 94 #define ATA_INTEL_LOCK(ctlr) \ 95 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 96 #define ATA_INTEL_UNLOCK(ctlr) \ 97 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 98 99 /* 100 * Intel chipset support functions 101 */ 102 static int 103 ata_intel_probe(device_t dev) 104 { 105 struct ata_pci_controller *ctlr = device_get_softc(dev); 106 static const struct ata_chip_id ids[] = 107 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 108 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 109 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 110 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 111 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 112 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 113 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 114 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 115 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 116 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 117 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 118 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 119 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 120 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 121 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 122 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 123 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 124 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 125 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 126 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 127 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 128 { ATA_I82801FB_S1, 0, 0, 0, ATA_SA150, "ICH6" }, 129 { ATA_I82801FB_R1, 0, 0, 0, ATA_SA150, "ICH6" }, 130 { ATA_I82801FBM, 0, 0, 0, ATA_SA150, "ICH6M" }, 131 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 132 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 133 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 134 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 135 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 136 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 137 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 138 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 139 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 140 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 141 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 142 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 143 { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 144 { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 145 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 146 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 147 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 148 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 149 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 150 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 151 { ATA_IBP_S1, 0, INTEL_6CH, 0, ATA_SA300, "Ibex Peak" }, 152 { ATA_IBP_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Ibex Peak" }, 153 { ATA_IBP_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Ibex Peak" }, 154 { ATA_IBP_S4, 0, INTEL_6CH, 0, ATA_SA300, "Ibex Peak-M" }, 155 { ATA_IBP_S5, 0, INTEL_6CH2, 0, ATA_SA300, "Ibex Peak-M" }, 156 { ATA_IBP_S6, 0, INTEL_6CH, 0, ATA_SA300, "Ibex Peak-M" }, 157 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Cougar Point" }, 158 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Cougar Point" }, 159 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 160 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 161 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA600, "Patsburg" }, 162 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 163 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Panther Point" }, 164 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Panther Point" }, 165 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 166 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 167 { ATA_AVOTON_S1, 0, INTEL_6CH, 0, ATA_SA600, "Avoton" }, 168 { ATA_AVOTON_S2, 0, INTEL_6CH, 0, ATA_SA600, "Avoton" }, 169 { ATA_AVOTON_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, 170 { ATA_AVOTON_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, 171 { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point" }, 172 { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point" }, 173 { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA600, "Lynx Point" }, 174 { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Lynx Point" }, 175 { ATA_WCPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Wildcat Point" }, 176 { ATA_WCPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Wildcat Point" }, 177 { ATA_WCPT_S3, 0, INTEL_6CH2, 0, ATA_SA600, "Wildcat Point" }, 178 { ATA_WCPT_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Wildcat Point" }, 179 { ATA_WELLS_S1, 0, INTEL_6CH, 0, ATA_SA600, "Wellsburg" }, 180 { ATA_WELLS_S2, 0, INTEL_6CH2, 0, ATA_SA600, "Wellsburg" }, 181 { ATA_WELLS_S3, 0, INTEL_6CH, 0, ATA_SA600, "Wellsburg" }, 182 { ATA_WELLS_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Wellsburg" }, 183 { ATA_LPTLP_S1, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point-LP" }, 184 { ATA_LPTLP_S2, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point-LP" }, 185 { ATA_LPTLP_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, 186 { ATA_LPTLP_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, 187 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 188 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 189 { ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 190 { ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 191 { ATA_IBT_S1, 0, 0, 0, ATA_SA300, "BayTrail" }, 192 { ATA_IBT_S2, 0, 0, 0, ATA_SA300, "BayTrail" }, 193 { 0, 0, 0, 0, 0, 0}}; 194 195 if (pci_get_vendor(dev) != ATA_INTEL_ID) 196 return ENXIO; 197 198 if (!(ctlr->chip = ata_match_chip(dev, ids))) 199 return ENXIO; 200 201 ata_set_desc(dev); 202 ctlr->chipinit = ata_intel_chipinit; 203 ctlr->chipdeinit = ata_intel_chipdeinit; 204 return (BUS_PROBE_LOW_PRIORITY); 205 } 206 207 static int 208 ata_intel_chipinit(device_t dev) 209 { 210 struct ata_pci_controller *ctlr = device_get_softc(dev); 211 struct ata_intel_data *data; 212 213 if (ata_setup_interrupt(dev, ata_generic_intr)) 214 return ENXIO; 215 216 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO); 217 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF); 218 ctlr->chipset_data = (void *)data; 219 220 /* good old PIIX needs special treatment (not implemented) */ 221 if (ctlr->chip->chipid == ATA_I82371FB) { 222 ctlr->setmode = ata_intel_old_setmode; 223 } 224 225 /* the intel 31244 needs special care if in DPA mode */ 226 else if (ctlr->chip->chipid == ATA_I31244) { 227 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 228 ctlr->r_type2 = SYS_RES_MEMORY; 229 ctlr->r_rid2 = PCIR_BAR(0); 230 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 231 &ctlr->r_rid2, 232 RF_ACTIVE))) 233 return ENXIO; 234 ctlr->channels = 4; 235 ctlr->ch_attach = ata_intel_31244_ch_attach; 236 ctlr->ch_detach = ata_intel_31244_ch_detach; 237 ctlr->reset = ata_intel_31244_reset; 238 } 239 ctlr->setmode = ata_sata_setmode; 240 ctlr->getrev = ata_sata_getrev; 241 } 242 /* SCH */ 243 else if (ctlr->chip->chipid == ATA_ISCH) { 244 ctlr->channels = 1; 245 ctlr->ch_attach = ata_intel_ch_attach; 246 ctlr->ch_detach = ata_pci_ch_detach; 247 ctlr->setmode = ata_intel_sch_setmode; 248 } 249 /* non SATA intel chips goes here */ 250 else if (ctlr->chip->max_dma < ATA_SA150) { 251 ctlr->channels = ctlr->chip->cfg2; 252 ctlr->ch_attach = ata_intel_ch_attach; 253 ctlr->ch_detach = ata_pci_ch_detach; 254 ctlr->setmode = ata_intel_new_setmode; 255 } 256 257 /* SATA parts can be either compat or AHCI */ 258 else { 259 /* force all ports active "the legacy way" */ 260 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 261 262 ctlr->ch_attach = ata_intel_ch_attach; 263 ctlr->ch_detach = ata_pci_ch_detach; 264 ctlr->reset = ata_intel_reset; 265 266 /* BAR(5) may point to SATA interface registers */ 267 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 268 ctlr->r_type2 = SYS_RES_MEMORY; 269 ctlr->r_rid2 = PCIR_BAR(5); 270 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 271 &ctlr->r_rid2, RF_ACTIVE); 272 if (ctlr->r_res2 != NULL) { 273 /* Set SCRAE bit to enable registers access. */ 274 pci_write_config(dev, 0x94, 275 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 276 /* Set Ports Implemented register bits. */ 277 ATA_OUTL(ctlr->r_res2, 0x0C, 278 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 279 } 280 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */ 281 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 || 282 pci_get_subvendor(dev) != 0x106b) { 283 ctlr->r_type2 = SYS_RES_IOPORT; 284 ctlr->r_rid2 = PCIR_BAR(5); 285 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 286 &ctlr->r_rid2, RF_ACTIVE); 287 } 288 if (ctlr->r_res2 != NULL || 289 (ctlr->chip->cfg1 & INTEL_ICH5)) 290 ctlr->getrev = ata_intel_sata_getrev; 291 ctlr->setmode = ata_sata_setmode; 292 } 293 return 0; 294 } 295 296 static int 297 ata_intel_chipdeinit(device_t dev) 298 { 299 struct ata_pci_controller *ctlr = device_get_softc(dev); 300 struct ata_intel_data *data; 301 302 data = ctlr->chipset_data; 303 mtx_destroy(&data->lock); 304 free(data, M_ATAPCI); 305 ctlr->chipset_data = NULL; 306 return (0); 307 } 308 309 static int 310 ata_intel_ch_attach(device_t dev) 311 { 312 struct ata_pci_controller *ctlr; 313 struct ata_channel *ch; 314 u_char *smap; 315 u_int map; 316 317 /* setup the usual register normal pci style */ 318 if (ata_pci_ch_attach(dev)) 319 return (ENXIO); 320 321 ctlr = device_get_softc(device_get_parent(dev)); 322 ch = device_get_softc(dev); 323 324 /* if r_res2 is valid it points to SATA interface registers */ 325 if (ctlr->r_res2) { 326 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 327 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 328 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 329 ch->r_io[ATA_IDX_DATA].offset = 0x04; 330 } 331 332 ch->flags |= ATA_ALWAYS_DMASTAT; 333 if (ctlr->chip->max_dma >= ATA_SA150) { 334 smap = ATA_INTEL_SMAP(ctlr, ch); 335 map = pci_read_config(device_get_parent(dev), 0x90, 1); 336 if (ctlr->chip->cfg1 & INTEL_ICH5) { 337 map &= 0x07; 338 if ((map & 0x04) == 0) { 339 ch->flags |= ATA_SATA; 340 ch->flags |= ATA_NO_SLAVE; 341 smap[0] = (map & 0x01) ^ ch->unit; 342 smap[1] = 0; 343 } else if ((map & 0x02) == 0 && ch->unit == 0) { 344 ch->flags |= ATA_SATA; 345 smap[0] = (map & 0x01) ? 1 : 0; 346 smap[1] = (map & 0x01) ? 0 : 1; 347 } else if ((map & 0x02) != 0 && ch->unit == 1) { 348 ch->flags |= ATA_SATA; 349 smap[0] = (map & 0x01) ? 1 : 0; 350 smap[1] = (map & 0x01) ? 0 : 1; 351 } 352 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 353 ch->flags |= ATA_SATA; 354 ch->flags |= ATA_NO_SLAVE; 355 smap[0] = (ch->unit == 0) ? 0 : 1; 356 smap[1] = 0; 357 } else { 358 map &= 0x03; 359 if (map == 0x00) { 360 ch->flags |= ATA_SATA; 361 smap[0] = (ch->unit == 0) ? 0 : 1; 362 smap[1] = (ch->unit == 0) ? 2 : 3; 363 } else if (map == 0x02 && ch->unit == 0) { 364 ch->flags |= ATA_SATA; 365 smap[0] = 0; 366 smap[1] = 2; 367 } else if (map == 0x01 && ch->unit == 1) { 368 ch->flags |= ATA_SATA; 369 smap[0] = 1; 370 smap[1] = 3; 371 } 372 } 373 if (ch->flags & ATA_SATA) { 374 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 375 ch->hw.pm_read = ata_intel_sata_cscr_read; 376 ch->hw.pm_write = ata_intel_sata_cscr_write; 377 } else if (ctlr->r_res2) { 378 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 379 ch->hw.pm_read = ata_intel_sata_ahci_read; 380 ch->hw.pm_write = ata_intel_sata_ahci_write; 381 } else if (ata_intel_sata_sidpr_test(dev)) { 382 ch->hw.pm_read = ata_intel_sata_sidpr_read; 383 ch->hw.pm_write = ata_intel_sata_sidpr_write; 384 } 385 } 386 if (ch->hw.pm_write != NULL) { 387 ch->flags |= ATA_PERIODIC_POLL; 388 ch->hw.status = ata_intel_sata_status; 389 ata_sata_scr_write(ch, 0, 390 ATA_SERROR, 0xffffffff); 391 if ((ch->flags & ATA_NO_SLAVE) == 0) { 392 ata_sata_scr_write(ch, 1, 393 ATA_SERROR, 0xffffffff); 394 } 395 } 396 } else 397 ctlr->setmode = ata_intel_new_setmode; 398 if (ctlr->chip->max_dma >= ATA_SA600) 399 ch->flags |= ATA_USE_16BIT; 400 } else if (ctlr->chip->chipid != ATA_ISCH) 401 ch->flags |= ATA_CHECKS_CABLE; 402 return (0); 403 } 404 405 static void 406 ata_intel_reset(device_t dev) 407 { 408 device_t parent = device_get_parent(dev); 409 struct ata_pci_controller *ctlr = device_get_softc(parent); 410 struct ata_channel *ch = device_get_softc(dev); 411 int mask, pshift, timeout, devs; 412 u_char *smap; 413 uint16_t pcs; 414 415 /* In combined mode, skip SATA stuff for PATA channel. */ 416 if ((ch->flags & ATA_SATA) == 0) 417 return (ata_generic_reset(dev)); 418 419 /* Do hard-reset on respective SATA ports. */ 420 smap = ATA_INTEL_SMAP(ctlr, ch); 421 mask = 1 << smap[0]; 422 if ((ch->flags & ATA_NO_SLAVE) == 0) 423 mask |= (1 << smap[1]); 424 pci_write_config(parent, 0x92, 425 pci_read_config(parent, 0x92, 2) & ~mask, 2); 426 DELAY(100); 427 pci_write_config(parent, 0x92, 428 pci_read_config(parent, 0x92, 2) | mask, 2); 429 430 /* Wait up to 1 sec for "connect well". */ 431 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 432 pshift = 8; 433 else 434 pshift = 4; 435 for (timeout = 0; timeout < 100 ; timeout++) { 436 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask; 437 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 438 break; 439 ata_udelay(10000); 440 } 441 442 if (bootverbose) 443 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs); 444 /* If any device found, do soft-reset. */ 445 if (ch->hw.pm_read != NULL) { 446 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0; 447 if ((ch->flags & ATA_NO_SLAVE) == 0) 448 devs |= ata_sata_phy_reset(dev, 1, 2) ? 449 ATA_ATA_SLAVE : 0; 450 } else { 451 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0; 452 if ((ch->flags & ATA_NO_SLAVE) == 0) 453 devs |= (pcs & (1 << smap[1])) ? 454 ATA_ATA_SLAVE : 0; 455 } 456 if (devs) { 457 ata_generic_reset(dev); 458 /* Reset may give fake slave when only ATAPI master present. */ 459 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER)); 460 } else 461 ch->devices = 0; 462 } 463 464 static int 465 ata_intel_old_setmode(device_t dev, int target, int mode) 466 { 467 device_t parent = device_get_parent(dev); 468 struct ata_pci_controller *ctlr = device_get_softc(parent); 469 470 mode = min(mode, ctlr->chip->max_dma); 471 return (mode); 472 } 473 474 static int 475 ata_intel_new_setmode(device_t dev, int target, int mode) 476 { 477 device_t parent = device_get_parent(dev); 478 struct ata_pci_controller *ctlr = device_get_softc(parent); 479 struct ata_channel *ch = device_get_softc(dev); 480 int devno = (ch->unit << 1) + target; 481 int piomode; 482 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 483 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 484 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 485 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 486 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 487 u_int32_t mask40 = 0, new40 = 0; 488 u_int8_t mask44 = 0, new44 = 0; 489 static const uint8_t timings[] = 490 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 491 static const uint8_t utimings[] = 492 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 493 494 /* In combined mode, skip PATA stuff for SATA channel. */ 495 if (ch->flags & ATA_SATA) 496 return (ata_sata_setmode(dev, target, mode)); 497 498 mode = min(mode, ctlr->chip->max_dma); 499 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 500 !(reg54 & (0x10 << devno))) { 501 ata_print_cable(dev, "controller"); 502 mode = ATA_UDMA2; 503 } 504 /* Enable/disable UDMA and set timings. */ 505 if (mode >= ATA_UDMA0) { 506 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 507 pci_write_config(parent, 0x4a, 508 (reg4a & ~(0x3 << (devno << 2))) | 509 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 510 piomode = ATA_PIO4; 511 } else { 512 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 513 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 514 piomode = mode; 515 } 516 reg54 |= 0x0400; 517 /* Set UDMA reference clock (33/66/133MHz). */ 518 reg54 &= ~(0x1001 << devno); 519 if (mode >= ATA_UDMA5) 520 reg54 |= (0x1000 << devno); 521 else if (mode >= ATA_UDMA3) 522 reg54 |= (0x1 << devno); 523 pci_write_config(parent, 0x54, reg54, 2); 524 /* Allow PIO/WDMA timing controls. */ 525 reg40 &= ~0x00ff00ff; 526 reg40 |= 0x40774077; 527 /* Set PIO/WDMA timings. */ 528 if (target == 0) { 529 mask40 = 0x3300; 530 new40 = timings[ata_mode2idx(piomode)] << 8; 531 } else { 532 mask44 = 0x0f; 533 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 534 (timings[ata_mode2idx(piomode)] & 0x03); 535 } 536 if (ch->unit) { 537 mask40 <<= 16; 538 new40 <<= 16; 539 mask44 <<= 4; 540 new44 <<= 4; 541 } 542 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 543 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 544 return (mode); 545 } 546 547 static int 548 ata_intel_sch_setmode(device_t dev, int target, int mode) 549 { 550 device_t parent = device_get_parent(dev); 551 struct ata_pci_controller *ctlr = device_get_softc(parent); 552 u_int8_t dtim = 0x80 + (target << 2); 553 u_int32_t tim = pci_read_config(parent, dtim, 4); 554 int piomode; 555 556 mode = min(mode, ctlr->chip->max_dma); 557 if (mode >= ATA_UDMA0) { 558 tim |= (0x1 << 31); 559 tim &= ~(0x7 << 16); 560 tim |= ((mode & ATA_MODE_MASK) << 16); 561 piomode = ATA_PIO4; 562 } else if (mode >= ATA_WDMA0) { 563 tim &= ~(0x1 << 31); 564 tim &= ~(0x3 << 8); 565 tim |= ((mode & ATA_MODE_MASK) << 8); 566 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 567 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 568 } else 569 piomode = mode; 570 tim &= ~(0x7); 571 tim |= (piomode & 0x7); 572 pci_write_config(parent, dtim, tim, 4); 573 return (mode); 574 } 575 576 static int 577 ata_intel_sata_getrev(device_t dev, int target) 578 { 579 struct ata_channel *ch = device_get_softc(dev); 580 uint32_t status; 581 582 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 583 return ((status & 0x0f0) >> 4); 584 return (0xff); 585 } 586 587 static int 588 ata_intel_sata_status(device_t dev) 589 { 590 struct ata_channel *ch = device_get_softc(dev); 591 592 ata_sata_phy_check_events(dev, 0); 593 if ((ch->flags & ATA_NO_SLAVE) == 0) 594 ata_sata_phy_check_events(dev, 1); 595 596 return ata_pci_status(dev); 597 } 598 599 static int 600 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 601 { 602 struct ata_pci_controller *ctlr; 603 struct ata_channel *ch; 604 device_t parent; 605 u_char *smap; 606 int offset; 607 608 parent = device_get_parent(dev); 609 ctlr = device_get_softc(parent); 610 ch = device_get_softc(dev); 611 port = (port == 1) ? 1 : 0; 612 smap = ATA_INTEL_SMAP(ctlr, ch); 613 offset = 0x100 + smap[port] * 0x80; 614 switch (reg) { 615 case ATA_SSTATUS: 616 reg = 0x28; 617 break; 618 case ATA_SCONTROL: 619 reg = 0x2c; 620 break; 621 case ATA_SERROR: 622 reg = 0x30; 623 break; 624 default: 625 return (EINVAL); 626 } 627 *result = ATA_INL(ctlr->r_res2, offset + reg); 628 return (0); 629 } 630 631 static int 632 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 633 { 634 struct ata_pci_controller *ctlr; 635 struct ata_channel *ch; 636 device_t parent; 637 u_char *smap; 638 639 parent = device_get_parent(dev); 640 ctlr = device_get_softc(parent); 641 ch = device_get_softc(dev); 642 smap = ATA_INTEL_SMAP(ctlr, ch); 643 port = (port == 1) ? 1 : 0; 644 switch (reg) { 645 case ATA_SSTATUS: 646 reg = 0; 647 break; 648 case ATA_SERROR: 649 reg = 1; 650 break; 651 case ATA_SCONTROL: 652 reg = 2; 653 break; 654 default: 655 return (EINVAL); 656 } 657 ATA_INTEL_LOCK(ctlr); 658 pci_write_config(parent, 0xa0, 659 0x50 + smap[port] * 0x10 + reg * 4, 4); 660 *result = pci_read_config(parent, 0xa4, 4); 661 ATA_INTEL_UNLOCK(ctlr); 662 return (0); 663 } 664 665 static int 666 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 667 { 668 struct ata_pci_controller *ctlr; 669 struct ata_channel *ch; 670 device_t parent; 671 672 parent = device_get_parent(dev); 673 ctlr = device_get_softc(parent); 674 ch = device_get_softc(dev); 675 port = (port == 1) ? 1 : 0; 676 switch (reg) { 677 case ATA_SSTATUS: 678 reg = 0; 679 break; 680 case ATA_SCONTROL: 681 reg = 1; 682 break; 683 case ATA_SERROR: 684 reg = 2; 685 break; 686 default: 687 return (EINVAL); 688 } 689 ATA_INTEL_LOCK(ctlr); 690 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 691 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 692 ATA_INTEL_UNLOCK(ctlr); 693 return (0); 694 } 695 696 static int 697 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 698 { 699 struct ata_pci_controller *ctlr; 700 struct ata_channel *ch; 701 device_t parent; 702 u_char *smap; 703 int offset; 704 705 parent = device_get_parent(dev); 706 ctlr = device_get_softc(parent); 707 ch = device_get_softc(dev); 708 port = (port == 1) ? 1 : 0; 709 smap = ATA_INTEL_SMAP(ctlr, ch); 710 offset = 0x100 + smap[port] * 0x80; 711 switch (reg) { 712 case ATA_SSTATUS: 713 reg = 0x28; 714 break; 715 case ATA_SCONTROL: 716 reg = 0x2c; 717 break; 718 case ATA_SERROR: 719 reg = 0x30; 720 break; 721 default: 722 return (EINVAL); 723 } 724 ATA_OUTL(ctlr->r_res2, offset + reg, value); 725 return (0); 726 } 727 728 static int 729 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 730 { 731 struct ata_pci_controller *ctlr; 732 struct ata_channel *ch; 733 device_t parent; 734 u_char *smap; 735 736 parent = device_get_parent(dev); 737 ctlr = device_get_softc(parent); 738 ch = device_get_softc(dev); 739 smap = ATA_INTEL_SMAP(ctlr, ch); 740 port = (port == 1) ? 1 : 0; 741 switch (reg) { 742 case ATA_SSTATUS: 743 reg = 0; 744 break; 745 case ATA_SERROR: 746 reg = 1; 747 break; 748 case ATA_SCONTROL: 749 reg = 2; 750 break; 751 default: 752 return (EINVAL); 753 } 754 ATA_INTEL_LOCK(ctlr); 755 pci_write_config(parent, 0xa0, 756 0x50 + smap[port] * 0x10 + reg * 4, 4); 757 pci_write_config(parent, 0xa4, value, 4); 758 ATA_INTEL_UNLOCK(ctlr); 759 return (0); 760 } 761 762 static int 763 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 764 { 765 struct ata_pci_controller *ctlr; 766 struct ata_channel *ch; 767 device_t parent; 768 769 parent = device_get_parent(dev); 770 ctlr = device_get_softc(parent); 771 ch = device_get_softc(dev); 772 port = (port == 1) ? 1 : 0; 773 switch (reg) { 774 case ATA_SSTATUS: 775 reg = 0; 776 break; 777 case ATA_SCONTROL: 778 reg = 1; 779 break; 780 case ATA_SERROR: 781 reg = 2; 782 break; 783 default: 784 return (EINVAL); 785 } 786 ATA_INTEL_LOCK(ctlr); 787 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 788 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 789 ATA_INTEL_UNLOCK(ctlr); 790 return (0); 791 } 792 793 static int 794 ata_intel_sata_sidpr_test(device_t dev) 795 { 796 struct ata_channel *ch = device_get_softc(dev); 797 int port; 798 uint32_t val; 799 800 port = (ch->flags & ATA_NO_SLAVE) ? 0 : 1; 801 for (; port >= 0; port--) { 802 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 803 if ((val & ATA_SC_IPM_MASK) == 804 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 805 return (1); 806 val |= ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER; 807 ata_intel_sata_sidpr_write(dev, port, ATA_SCONTROL, val); 808 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 809 if ((val & ATA_SC_IPM_MASK) == 810 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 811 return (1); 812 } 813 if (bootverbose) 814 device_printf(dev, 815 "SControl registers are not functional: %08x\n", val); 816 return (0); 817 } 818 819 static int 820 ata_intel_31244_ch_attach(device_t dev) 821 { 822 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 823 struct ata_channel *ch = device_get_softc(dev); 824 int i; 825 int ch_offset; 826 827 ata_pci_dmainit(dev); 828 829 ch_offset = 0x200 + ch->unit * 0x200; 830 831 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 832 ch->r_io[i].res = ctlr->r_res2; 833 834 /* setup ATA registers */ 835 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 836 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 837 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 838 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 839 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 840 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 841 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 842 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 843 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 844 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 845 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 846 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 847 848 /* setup DMA registers */ 849 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 850 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 851 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 852 853 /* setup SATA registers */ 854 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 855 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 856 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 857 858 ch->flags |= ATA_NO_SLAVE; 859 ch->flags |= ATA_SATA; 860 ata_pci_hw(dev); 861 ch->hw.status = ata_intel_31244_status; 862 ch->hw.tf_write = ata_intel_31244_tf_write; 863 864 /* enable PHY state change interrupt */ 865 ATA_OUTL(ctlr->r_res2, 0x4, 866 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 867 return 0; 868 } 869 870 static int 871 ata_intel_31244_ch_detach(device_t dev) 872 { 873 874 ata_pci_dmafini(dev); 875 return (0); 876 } 877 878 static int 879 ata_intel_31244_status(device_t dev) 880 { 881 /* do we have any PHY events ? */ 882 ata_sata_phy_check_events(dev, -1); 883 884 /* any drive action to take care of ? */ 885 return ata_pci_status(dev); 886 } 887 888 static void 889 ata_intel_31244_tf_write(struct ata_request *request) 890 { 891 struct ata_channel *ch = device_get_softc(request->parent); 892 893 if (request->flags & ATA_R_48BIT) { 894 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 895 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 896 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 897 (request->u.ata.lba & 0x00ff)); 898 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 899 ((request->u.ata.lba >> 8) & 0x00ff)); 900 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 901 ((request->u.ata.lba >> 16) & 0x00ff)); 902 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 903 } 904 else { 905 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 906 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 907 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 908 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 909 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 910 ATA_IDX_OUTB(ch, ATA_DRIVE, 911 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 912 ((request->u.ata.lba >> 24) & 0x0f)); 913 } 914 } 915 916 static void 917 ata_intel_31244_reset(device_t dev) 918 { 919 struct ata_channel *ch = device_get_softc(dev); 920 921 if (ata_sata_phy_reset(dev, -1, 1)) 922 ata_generic_reset(dev); 923 else 924 ch->devices = 0; 925 } 926 927 ATA_DECLARE_DRIVER(ata_intel); 928