1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/ata/ata-all.h> 48 #include <ata_if.h> 49 50 void 51 ata_sata_phy_check_events(device_t dev) 52 { 53 struct ata_channel *ch = device_get_softc(dev); 54 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR); 55 56 /* clear error bits/interrupt */ 57 ATA_IDX_OUTL(ch, ATA_SERROR, error); 58 59 /* if we have a connection event deal with it */ 60 if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 61 if (bootverbose) { 62 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS); 63 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) || 64 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) { 65 device_printf(dev, "CONNECT requested\n"); 66 } else 67 device_printf(dev, "DISCONNECT requested\n"); 68 } 69 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 70 } 71 } 72 73 int 74 ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val) 75 { 76 int r; 77 78 if (port < 0) { 79 *val = ATA_IDX_INL(ch, reg); 80 return (0); 81 } else { 82 switch (reg) { 83 case ATA_SSTATUS: 84 r = 0; 85 break; 86 case ATA_SERROR: 87 r = 1; 88 break; 89 case ATA_SCONTROL: 90 r = 2; 91 break; 92 default: 93 return (EINVAL); 94 } 95 return (ch->hw.pm_read(ch->dev, port, r, val)); 96 } 97 } 98 99 int 100 ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val) 101 { 102 int r; 103 104 if (port < 0) { 105 ATA_IDX_OUTL(ch, reg, val); 106 return (0); 107 } else { 108 switch (reg) { 109 case ATA_SERROR: 110 r = 1; 111 break; 112 case ATA_SCONTROL: 113 r = 2; 114 break; 115 default: 116 return (EINVAL); 117 } 118 return (ch->hw.pm_write(ch->dev, port, r, val)); 119 } 120 } 121 122 static int 123 ata_sata_connect(struct ata_channel *ch, int port) 124 { 125 u_int32_t status; 126 int timeout; 127 128 /* wait up to 1 second for "connect well" */ 129 for (timeout = 0; timeout < 100 ; timeout++) { 130 if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status)) 131 return (0); 132 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 || 133 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) 134 break; 135 ata_udelay(10000); 136 } 137 if (timeout >= 100) { 138 if (bootverbose) { 139 if (port < 0) { 140 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 141 status); 142 } else { 143 device_printf(ch->dev, "p%d: SATA connect timeout status=%08x\n", 144 port, status); 145 } 146 } 147 return 0; 148 } 149 if (bootverbose) { 150 if (port < 0) { 151 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 152 timeout * 10, status); 153 } else { 154 device_printf(ch->dev, "p%d: SATA connect time=%dms status=%08x\n", 155 port, timeout * 10, status); 156 } 157 } 158 159 /* clear SATA error register */ 160 ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff); 161 162 return 1; 163 } 164 165 int 166 ata_sata_phy_reset(device_t dev, int port, int quick) 167 { 168 struct ata_channel *ch = device_get_softc(dev); 169 int loop, retry; 170 uint32_t val; 171 172 if (quick) { 173 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 174 return (0); 175 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 176 return ata_sata_connect(ch, port); 177 } 178 179 if (bootverbose) { 180 if (port < 0) { 181 device_printf(dev, "hardware reset ...\n"); 182 } else { 183 device_printf(dev, "p%d: hardware reset ...\n", port); 184 } 185 } 186 for (retry = 0; retry < 10; retry++) { 187 for (loop = 0; loop < 10; loop++) { 188 if (ata_sata_scr_write(ch, port, ATA_SCONTROL, ATA_SC_DET_RESET)) 189 return (0); 190 ata_udelay(100); 191 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 192 return (0); 193 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 194 break; 195 } 196 ata_udelay(5000); 197 for (loop = 0; loop < 10; loop++) { 198 if (ata_sata_scr_write(ch, port, ATA_SCONTROL, 199 ATA_SC_DET_IDLE | ((ch->pm_level > 0) ? 0 : 200 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))) 201 return (0); 202 ata_udelay(100); 203 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 204 return (0); 205 if ((val & ATA_SC_DET_MASK) == 0) 206 return ata_sata_connect(ch, port); 207 } 208 } 209 return 0; 210 } 211 212 void 213 ata_sata_setmode(device_t dev, int mode) 214 { 215 struct ata_device *atadev = device_get_softc(dev); 216 217 /* 218 * if we detect that the device isn't a real SATA device we limit 219 * the transfer mode to UDMA5/ATA100. 220 * this works around the problems some devices has with the 221 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133. 222 */ 223 if (atadev->param.satacapabilities != 0x0000 && 224 atadev->param.satacapabilities != 0xffff) { 225 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 226 227 /* on some drives we need to set the transfer mode */ 228 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 229 ata_limit_mode(dev, mode, ATA_UDMA6)); 230 231 /* query SATA STATUS for the speed */ 232 if (ch->r_io[ATA_SSTATUS].res && 233 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) == 234 ATA_SS_CONWELL_GEN2)) 235 atadev->mode = ATA_SA300; 236 else 237 atadev->mode = ATA_SA150; 238 } 239 else { 240 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 241 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 242 atadev->mode = mode; 243 } 244 } 245 246 int 247 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 248 { 249 250 if (request->flags & ATA_R_ATAPI) { 251 fis[0] = 0x27; /* host to device */ 252 fis[1] = 0x80 | (request->unit & 0x0f); 253 fis[2] = ATA_PACKET_CMD; 254 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) 255 fis[3] = ATA_F_DMA; 256 else { 257 fis[5] = request->transfersize; 258 fis[6] = request->transfersize >> 8; 259 } 260 fis[7] = ATA_D_LBA; 261 fis[15] = ATA_A_4BIT; 262 return 20; 263 } 264 else { 265 fis[0] = 0x27; /* host to device */ 266 fis[1] = 0x80 | (request->unit & 0x0f); 267 fis[2] = request->u.ata.command; 268 fis[3] = request->u.ata.feature; 269 fis[4] = request->u.ata.lba; 270 fis[5] = request->u.ata.lba >> 8; 271 fis[6] = request->u.ata.lba >> 16; 272 fis[7] = ATA_D_LBA; 273 if (!(request->flags & ATA_R_48BIT)) 274 fis[7] |= (ATA_D_IBM | (request->u.ata.lba >> 24 & 0x0f)); 275 fis[8] = request->u.ata.lba >> 24; 276 fis[9] = request->u.ata.lba >> 32; 277 fis[10] = request->u.ata.lba >> 40; 278 fis[11] = request->u.ata.feature >> 8; 279 fis[12] = request->u.ata.count; 280 fis[13] = request->u.ata.count >> 8; 281 fis[15] = ATA_A_4BIT; 282 return 20; 283 } 284 return 0; 285 } 286 287 void 288 ata_pm_identify(device_t dev) 289 { 290 struct ata_channel *ch = device_get_softc(dev); 291 u_int32_t pm_chipid, pm_revision, pm_ports; 292 int port; 293 294 /* get PM vendor & product data */ 295 if (ch->hw.pm_read(dev, ATA_PM, 0, &pm_chipid)) { 296 device_printf(dev, "error getting PM vendor data\n"); 297 return; 298 } 299 300 /* get PM revision data */ 301 if (ch->hw.pm_read(dev, ATA_PM, 1, &pm_revision)) { 302 device_printf(dev, "error getting PM revison data\n"); 303 return; 304 } 305 306 /* get number of HW ports on the PM */ 307 if (ch->hw.pm_read(dev, ATA_PM, 2, &pm_ports)) { 308 device_printf(dev, "error getting PM port info\n"); 309 return; 310 } 311 pm_ports &= 0x0000000f; 312 313 /* chip specific quirks */ 314 switch (pm_chipid) { 315 case 0x37261095: 316 /* This PM declares 6 ports, while only 5 of them are real. 317 * Port 5 is enclosure management bridge port, which has implementation 318 * problems, causing probe faults. Hide it for now. */ 319 device_printf(dev, "SiI 3726 (rev=%x) Port Multiplier with %d (5) ports\n", 320 pm_revision, pm_ports); 321 pm_ports = 5; 322 break; 323 324 case 0x47261095: 325 /* This PM declares 7 ports, while only 5 of them are real. 326 * Port 5 is some fake "Config Disk" with 640 sectors size, 327 * port 6 is enclosure management bridge port. 328 * Both fake ports has implementation problems, causing 329 * probe faults. Hide them for now. */ 330 device_printf(dev, "SiI 4726 (rev=%x) Port Multiplier with %d (5) ports\n", 331 pm_revision, pm_ports); 332 pm_ports = 5; 333 break; 334 335 default: 336 device_printf(dev, "Port Multiplier (id=%08x rev=%x) with %d ports\n", 337 pm_chipid, pm_revision, pm_ports); 338 } 339 340 /* reset all ports and register if anything connected */ 341 for (port=0; port < pm_ports; port++) { 342 u_int32_t signature; 343 344 if (!ata_sata_phy_reset(dev, port, 1)) 345 continue; 346 347 /* 348 * XXX: I have no idea how to properly wait for PMP port hardreset 349 * completion. Without this delay soft reset does not completes 350 * successfully. 351 */ 352 DELAY(1000000); 353 354 signature = ch->hw.softreset(dev, port); 355 356 if (bootverbose) 357 device_printf(dev, "p%d: SIGNATURE=%08x\n", port, signature); 358 359 /* figure out whats there */ 360 switch (signature >> 16) { 361 case 0x0000: 362 ch->devices |= (ATA_ATA_MASTER << port); 363 continue; 364 case 0xeb14: 365 ch->devices |= (ATA_ATAPI_MASTER << port); 366 continue; 367 } 368 } 369 } 370