1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/endian.h> 35 #include <sys/ata.h> 36 #include <sys/conf.h> 37 #include <sys/ctype.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 #include <dev/ata/ata-pci.h> 46 #include <ata_if.h> 47 48 /* prototypes */ 49 static int ata_generic_status(device_t dev); 50 static int ata_wait(struct ata_channel *ch, int unit, u_int8_t); 51 static void ata_pio_read(struct ata_request *, int); 52 static void ata_pio_write(struct ata_request *, int); 53 static void ata_tf_read(struct ata_request *); 54 static void ata_tf_write(struct ata_request *); 55 56 /* 57 * low level ATA functions 58 */ 59 void 60 ata_generic_hw(device_t dev) 61 { 62 struct ata_channel *ch = device_get_softc(dev); 63 64 ch->hw.begin_transaction = ata_begin_transaction; 65 ch->hw.end_transaction = ata_end_transaction; 66 ch->hw.status = ata_generic_status; 67 ch->hw.softreset = NULL; 68 ch->hw.command = ata_generic_command; 69 ch->hw.tf_read = ata_tf_read; 70 ch->hw.tf_write = ata_tf_write; 71 ch->hw.pm_read = NULL; 72 ch->hw.pm_write = NULL; 73 } 74 75 /* must be called with ATA channel locked and state_mtx held */ 76 int 77 ata_begin_transaction(struct ata_request *request) 78 { 79 struct ata_channel *ch = device_get_softc(request->parent); 80 int dummy, error; 81 82 ATA_DEBUG_RQ(request, "begin transaction"); 83 84 /* disable ATAPI DMA writes if HW doesn't support it */ 85 if ((ch->flags & ATA_NO_ATAPI_DMA) && 86 (request->flags & ATA_R_ATAPI) == ATA_R_ATAPI) 87 request->flags &= ~ATA_R_DMA; 88 if ((ch->flags & ATA_ATAPI_DMA_RO) && 89 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 90 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 91 request->flags &= ~ATA_R_DMA; 92 93 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 94 95 /* ATA PIO data transfer and control commands */ 96 default: 97 { 98 /* record command direction here as our request might be gone later */ 99 int write = (request->flags & ATA_R_WRITE); 100 101 /* issue command */ 102 if (ch->hw.command(request)) { 103 device_printf(request->parent, "error issuing %s command\n", 104 ata_cmd2str(request)); 105 request->result = EIO; 106 goto begin_finished; 107 } 108 109 /* device reset doesn't interrupt */ 110 if (request->u.ata.command == ATA_DEVICE_RESET) { 111 112 int timeout = 1000000; 113 do { 114 DELAY(10); 115 request->status = ATA_IDX_INB(ch, ATA_STATUS); 116 } while (request->status & ATA_S_BUSY && timeout--); 117 if (request->status & ATA_S_ERROR) 118 request->error = ATA_IDX_INB(ch, ATA_ERROR); 119 goto begin_finished; 120 } 121 122 /* if write command output the data */ 123 if (write) { 124 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 125 device_printf(request->parent, 126 "timeout waiting for write DRQ\n"); 127 request->result = EIO; 128 goto begin_finished; 129 } 130 ata_pio_write(request, request->transfersize); 131 } 132 } 133 goto begin_continue; 134 135 /* ATA DMA data transfer commands */ 136 case ATA_R_DMA: 137 /* check sanity, setup SG list and DMA engine */ 138 if ((error = ch->dma.load(request, NULL, &dummy))) { 139 device_printf(request->parent, "setting up DMA failed\n"); 140 request->result = error; 141 goto begin_finished; 142 } 143 144 /* issue command */ 145 if (ch->hw.command(request)) { 146 device_printf(request->parent, "error issuing %s command\n", 147 ata_cmd2str(request)); 148 request->result = EIO; 149 goto begin_finished; 150 } 151 152 /* start DMA engine */ 153 if (ch->dma.start && ch->dma.start(request)) { 154 device_printf(request->parent, "error starting DMA\n"); 155 request->result = EIO; 156 goto begin_finished; 157 } 158 goto begin_continue; 159 160 /* ATAPI PIO commands */ 161 case ATA_R_ATAPI: 162 /* is this just a POLL DSC command ? */ 163 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 164 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 165 DELAY(10); 166 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 167 request->result = EBUSY; 168 goto begin_finished; 169 } 170 171 /* start ATAPI operation */ 172 if (ch->hw.command(request)) { 173 device_printf(request->parent, "error issuing ATA PACKET command\n"); 174 request->result = EIO; 175 goto begin_finished; 176 } 177 goto begin_continue; 178 179 /* ATAPI DMA commands */ 180 case ATA_R_ATAPI|ATA_R_DMA: 181 /* is this just a POLL DSC command ? */ 182 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 183 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 184 DELAY(10); 185 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 186 request->result = EBUSY; 187 goto begin_finished; 188 } 189 190 /* check sanity, setup SG list and DMA engine */ 191 if ((error = ch->dma.load(request, NULL, &dummy))) { 192 device_printf(request->parent, "setting up DMA failed\n"); 193 request->result = error; 194 goto begin_finished; 195 } 196 197 /* start ATAPI operation */ 198 if (ch->hw.command(request)) { 199 device_printf(request->parent, "error issuing ATA PACKET command\n"); 200 request->result = EIO; 201 goto begin_finished; 202 } 203 204 /* start DMA engine */ 205 if (ch->dma.start && ch->dma.start(request)) { 206 request->result = EIO; 207 goto begin_finished; 208 } 209 goto begin_continue; 210 } 211 /* NOT REACHED */ 212 printf("ata_begin_transaction OOPS!!!\n"); 213 214 begin_finished: 215 if (ch->dma.unload) { 216 ch->dma.unload(request); 217 } 218 return ATA_OP_FINISHED; 219 220 begin_continue: 221 callout_reset(&request->callout, request->timeout * hz, 222 (timeout_t*)ata_timeout, request); 223 return ATA_OP_CONTINUES; 224 } 225 226 /* must be called with ATA channel locked and state_mtx held */ 227 int 228 ata_end_transaction(struct ata_request *request) 229 { 230 struct ata_channel *ch = device_get_softc(request->parent); 231 int length; 232 233 ATA_DEBUG_RQ(request, "end transaction"); 234 235 /* clear interrupt and get status */ 236 request->status = ATA_IDX_INB(ch, ATA_STATUS); 237 238 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 239 240 /* ATA PIO data transfer and control commands */ 241 default: 242 243 /* on timeouts we have no data or anything so just return */ 244 if (request->flags & ATA_R_TIMEOUT) 245 goto end_finished; 246 247 /* on control commands read back registers to the request struct */ 248 if (request->flags & ATA_R_CONTROL) { 249 ch->hw.tf_read(request); 250 } 251 252 /* if we got an error we are done with the HW */ 253 if (request->status & ATA_S_ERROR) { 254 request->error = ATA_IDX_INB(ch, ATA_ERROR); 255 goto end_finished; 256 } 257 258 /* are we moving data ? */ 259 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 260 261 /* if read data get it */ 262 if (request->flags & ATA_R_READ) { 263 int flags = ATA_S_DRQ; 264 265 if (request->u.ata.command != ATA_ATAPI_IDENTIFY) 266 flags |= ATA_S_READY; 267 if (ata_wait(ch, request->unit, flags) < 0) { 268 device_printf(request->parent, 269 "timeout waiting for read DRQ\n"); 270 request->result = EIO; 271 goto end_finished; 272 } 273 ata_pio_read(request, request->transfersize); 274 } 275 276 /* update how far we've gotten */ 277 request->donecount += request->transfersize; 278 279 /* do we need a scoop more ? */ 280 if (request->bytecount > request->donecount) { 281 282 /* set this transfer size according to HW capabilities */ 283 request->transfersize = 284 min((request->bytecount - request->donecount), 285 request->transfersize); 286 287 /* if data write command, output the data */ 288 if (request->flags & ATA_R_WRITE) { 289 290 /* if we get an error here we are done with the HW */ 291 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 292 device_printf(request->parent, 293 "timeout waiting for write DRQ\n"); 294 request->status = ATA_IDX_INB(ch, ATA_STATUS); 295 goto end_finished; 296 } 297 298 /* output data and return waiting for new interrupt */ 299 ata_pio_write(request, request->transfersize); 300 goto end_continue; 301 } 302 303 /* if data read command, return & wait for interrupt */ 304 if (request->flags & ATA_R_READ) 305 goto end_continue; 306 } 307 } 308 /* done with HW */ 309 goto end_finished; 310 311 /* ATA DMA data transfer commands */ 312 case ATA_R_DMA: 313 314 /* stop DMA engine and get status */ 315 if (ch->dma.stop) 316 request->dma->status = ch->dma.stop(request); 317 318 /* did we get error or data */ 319 if (request->status & ATA_S_ERROR) 320 request->error = ATA_IDX_INB(ch, ATA_ERROR); 321 else if (request->dma->status & ATA_BMSTAT_ERROR) 322 request->status |= ATA_S_ERROR; 323 else if (!(request->flags & ATA_R_TIMEOUT)) 324 request->donecount = request->bytecount; 325 326 /* release SG list etc */ 327 ch->dma.unload(request); 328 329 /* done with HW */ 330 goto end_finished; 331 332 /* ATAPI PIO commands */ 333 case ATA_R_ATAPI: 334 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 335 336 /* on timeouts we have no data or anything so just return */ 337 if (request->flags & ATA_R_TIMEOUT) 338 goto end_finished; 339 340 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 341 (request->status & ATA_S_DRQ)) { 342 343 case ATAPI_P_CMDOUT: 344 /* this seems to be needed for some (slow) devices */ 345 DELAY(10); 346 347 if (!(request->status & ATA_S_DRQ)) { 348 device_printf(request->parent, "command interrupt without DRQ\n"); 349 request->status = ATA_S_ERROR; 350 goto end_finished; 351 } 352 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 353 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 354 /* return wait for interrupt */ 355 goto end_continue; 356 357 case ATAPI_P_WRITE: 358 if (request->flags & ATA_R_READ) { 359 request->status = ATA_S_ERROR; 360 device_printf(request->parent, 361 "%s trying to write on read buffer\n", 362 ata_cmd2str(request)); 363 goto end_finished; 364 break; 365 } 366 ata_pio_write(request, length); 367 request->donecount += length; 368 369 /* set next transfer size according to HW capabilities */ 370 request->transfersize = min((request->bytecount-request->donecount), 371 request->transfersize); 372 /* return wait for interrupt */ 373 goto end_continue; 374 375 case ATAPI_P_READ: 376 if (request->flags & ATA_R_WRITE) { 377 request->status = ATA_S_ERROR; 378 device_printf(request->parent, 379 "%s trying to read on write buffer\n", 380 ata_cmd2str(request)); 381 goto end_finished; 382 } 383 ata_pio_read(request, length); 384 request->donecount += length; 385 386 /* set next transfer size according to HW capabilities */ 387 request->transfersize = min((request->bytecount-request->donecount), 388 request->transfersize); 389 /* return wait for interrupt */ 390 goto end_continue; 391 392 case ATAPI_P_DONEDRQ: 393 device_printf(request->parent, 394 "WARNING - %s DONEDRQ non conformant device\n", 395 ata_cmd2str(request)); 396 if (request->flags & ATA_R_READ) { 397 ata_pio_read(request, length); 398 request->donecount += length; 399 } 400 else if (request->flags & ATA_R_WRITE) { 401 ata_pio_write(request, length); 402 request->donecount += length; 403 } 404 else 405 request->status = ATA_S_ERROR; 406 /* FALLTHROUGH */ 407 408 case ATAPI_P_ABORT: 409 case ATAPI_P_DONE: 410 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 411 request->error = ATA_IDX_INB(ch, ATA_ERROR); 412 goto end_finished; 413 414 default: 415 device_printf(request->parent, "unknown transfer phase\n"); 416 request->status = ATA_S_ERROR; 417 } 418 419 /* done with HW */ 420 goto end_finished; 421 422 /* ATAPI DMA commands */ 423 case ATA_R_ATAPI|ATA_R_DMA: 424 425 /* stop DMA engine and get status */ 426 if (ch->dma.stop) 427 request->dma->status = ch->dma.stop(request); 428 429 /* did we get error or data */ 430 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 431 request->error = ATA_IDX_INB(ch, ATA_ERROR); 432 else if (request->dma->status & ATA_BMSTAT_ERROR) 433 request->status |= ATA_S_ERROR; 434 else if (!(request->flags & ATA_R_TIMEOUT)) 435 request->donecount = request->bytecount; 436 437 /* release SG list etc */ 438 ch->dma.unload(request); 439 440 /* done with HW */ 441 goto end_finished; 442 } 443 /* NOT REACHED */ 444 printf("ata_end_transaction OOPS!!\n"); 445 446 end_finished: 447 callout_stop(&request->callout); 448 return ATA_OP_FINISHED; 449 450 end_continue: 451 return ATA_OP_CONTINUES; 452 } 453 454 /* must be called with ATA channel locked and state_mtx held */ 455 void 456 ata_generic_reset(device_t dev) 457 { 458 struct ata_channel *ch = device_get_softc(dev); 459 460 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 461 u_int8_t err = 0, lsb = 0, msb = 0; 462 int mask = 0, timeout; 463 464 /* do we have any signs of ATA/ATAPI HW being present ? */ 465 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 466 DELAY(10); 467 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 468 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 469 stat0 = ATA_S_BUSY; 470 mask |= 0x01; 471 } 472 473 /* in some setups we dont want to test for a slave */ 474 if (!(ch->flags & ATA_NO_SLAVE)) { 475 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE)); 476 DELAY(10); 477 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 478 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 479 stat1 = ATA_S_BUSY; 480 mask |= 0x02; 481 } 482 } 483 484 if (bootverbose) 485 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 486 mask, ostat0, ostat1); 487 488 /* if nothing showed up there is no need to get any further */ 489 /* XXX SOS is that too strong?, we just might loose devices here */ 490 ch->devices = 0; 491 if (!mask) 492 return; 493 494 /* reset (both) devices on this channel */ 495 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 496 DELAY(10); 497 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 498 ata_udelay(10000); 499 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 500 ata_udelay(100000); 501 ATA_IDX_INB(ch, ATA_ERROR); 502 503 /* wait for BUSY to go inactive */ 504 for (timeout = 0; timeout < 310; timeout++) { 505 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 506 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER)); 507 DELAY(10); 508 err = ATA_IDX_INB(ch, ATA_ERROR); 509 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 510 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 511 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 512 if (bootverbose) 513 device_printf(dev, 514 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 515 stat0, err, lsb, msb); 516 if (stat0 == err && lsb == err && msb == err && 517 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 518 mask &= ~0x01; 519 if (!(stat0 & ATA_S_BUSY)) { 520 if ((err & 0x7f) == ATA_E_ILI) { 521 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 522 ch->devices |= ATA_ATAPI_MASTER; 523 } 524 else if (stat0 & ATA_S_READY) { 525 ch->devices |= ATA_ATA_MASTER; 526 } 527 } 528 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 529 stat0 |= ATA_S_BUSY; 530 } 531 } 532 } 533 534 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 535 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 536 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE)); 537 DELAY(10); 538 err = ATA_IDX_INB(ch, ATA_ERROR); 539 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 540 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 541 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 542 if (bootverbose) 543 device_printf(dev, 544 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 545 stat1, err, lsb, msb); 546 if (stat1 == err && lsb == err && msb == err && 547 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 548 mask &= ~0x02; 549 if (!(stat1 & ATA_S_BUSY)) { 550 if ((err & 0x7f) == ATA_E_ILI) { 551 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 552 ch->devices |= ATA_ATAPI_SLAVE; 553 } 554 else if (stat1 & ATA_S_READY) { 555 ch->devices |= ATA_ATA_SLAVE; 556 } 557 } 558 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 559 stat1 |= ATA_S_BUSY; 560 } 561 } 562 } 563 564 if (mask == 0x00) /* nothing to wait for */ 565 break; 566 if (mask == 0x01) /* wait for master only */ 567 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10)) 568 break; 569 if (mask == 0x02) /* wait for slave only */ 570 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10)) 571 break; 572 if (mask == 0x03) { /* wait for both master & slave */ 573 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 574 break; 575 if ((stat0 == 0xff) && (timeout > 20)) 576 mask &= ~0x01; 577 if ((stat1 == 0xff) && (timeout > 20)) 578 mask &= ~0x02; 579 } 580 ata_udelay(100000); 581 } 582 583 if (bootverbose) 584 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n", 585 stat0, stat1, ch->devices); 586 } 587 588 /* must be called with ATA channel locked and state_mtx held */ 589 int 590 ata_generic_status(device_t dev) 591 { 592 struct ata_channel *ch = device_get_softc(dev); 593 594 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 595 DELAY(100); 596 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 597 return 0; 598 } 599 return 1; 600 } 601 602 static int 603 ata_wait(struct ata_channel *ch, int unit, u_int8_t mask) 604 { 605 u_int8_t status; 606 int timeout = 0; 607 608 DELAY(1); 609 610 /* wait at max 1 second for device to get !BUSY */ 611 while (timeout < 1000000) { 612 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 613 614 /* if drive fails status, reselect the drive and try again */ 615 if (status == 0xff) { 616 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(unit)); 617 timeout += 1000; 618 DELAY(1000); 619 continue; 620 } 621 622 /* are we done ? */ 623 if (!(status & ATA_S_BUSY)) 624 break; 625 626 if (timeout > 1000) { 627 timeout += 1000; 628 DELAY(1000); 629 } 630 else { 631 timeout += 10; 632 DELAY(10); 633 } 634 } 635 if (timeout >= 1000000) 636 return -2; 637 if (!mask) 638 return (status & ATA_S_ERROR); 639 640 DELAY(1); 641 642 /* wait 50 msec for bits wanted */ 643 timeout = 5000; 644 while (timeout--) { 645 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 646 if ((status & mask) == mask) 647 return (status & ATA_S_ERROR); 648 DELAY(10); 649 } 650 return -3; 651 } 652 653 int 654 ata_generic_command(struct ata_request *request) 655 { 656 struct ata_channel *ch = device_get_softc(request->parent); 657 658 /* select device */ 659 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit)); 660 661 /* ready to issue command ? */ 662 if (ata_wait(ch, request->unit, 0) < 0) { 663 device_printf(request->parent, "timeout waiting to issue command\n"); 664 return -1; 665 } 666 667 /* enable interrupt */ 668 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 669 670 if (request->flags & ATA_R_ATAPI) { 671 int timeout = 5000; 672 int res; 673 674 /* issue packet command to controller */ 675 if (request->flags & ATA_R_DMA) { 676 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 677 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 678 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 679 } 680 else { 681 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 682 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 683 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 684 } 685 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 686 687 /* command interrupt device ? just return and wait for interrupt */ 688 if (request->flags & ATA_R_ATAPI_INTR) 689 return 0; 690 691 /* command processed ? */ 692 res = ata_wait(ch, request->unit, 0); 693 if (res != 0) { 694 if (res < 0) 695 device_printf(request->parent, "timeout waiting for PACKET command\n"); 696 return (-1); 697 } 698 /* wait for ready to write ATAPI command block */ 699 while (timeout--) { 700 int reason = ATA_IDX_INB(ch, ATA_IREASON); 701 int status = ATA_IDX_INB(ch, ATA_STATUS); 702 703 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 704 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 705 break; 706 DELAY(20); 707 } 708 if (timeout <= 0) { 709 device_printf(request->parent, "timeout waiting for ATAPI ready\n"); 710 request->result = EIO; 711 return -1; 712 } 713 714 /* this seems to be needed for some (slow) devices */ 715 DELAY(10); 716 717 /* output command block */ 718 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 719 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 720 } 721 else { 722 ch->hw.tf_write(request); 723 724 /* issue command to controller */ 725 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 726 } 727 return 0; 728 } 729 730 static void 731 ata_tf_read(struct ata_request *request) 732 { 733 struct ata_channel *ch = device_get_softc(request->parent); 734 735 if (request->flags & ATA_R_48BIT) { 736 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 737 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 738 request->u.ata.lba = 739 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 740 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 741 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 742 743 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 744 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 745 request->u.ata.lba |= 746 (ATA_IDX_INB(ch, ATA_SECTOR) | 747 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 748 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 749 } 750 else { 751 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 752 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 753 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 754 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 755 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 756 } 757 } 758 759 static void 760 ata_tf_write(struct ata_request *request) 761 { 762 struct ata_channel *ch = device_get_softc(request->parent); 763 #ifndef ATA_CAM 764 struct ata_device *atadev = device_get_softc(request->dev); 765 #endif 766 767 if (request->flags & ATA_R_48BIT) { 768 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 769 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 770 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 771 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 772 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 773 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 774 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 775 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 776 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 777 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 778 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 779 } 780 else { 781 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 782 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 783 #ifndef ATA_CAM 784 if (atadev->flags & ATA_D_USE_CHS) { 785 int heads, sectors; 786 787 if (atadev->param.atavalid & ATA_FLAG_54_58) { 788 heads = atadev->param.current_heads; 789 sectors = atadev->param.current_sectors; 790 } 791 else { 792 heads = atadev->param.heads; 793 sectors = atadev->param.sectors; 794 } 795 796 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 797 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 798 (request->u.ata.lba / (sectors * heads))); 799 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 800 (request->u.ata.lba / (sectors * heads)) >> 8); 801 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 802 (((request->u.ata.lba% (sectors * heads)) / 803 sectors) & 0xf)); 804 } 805 else { 806 #endif 807 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 808 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 809 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 810 ATA_IDX_OUTB(ch, ATA_DRIVE, 811 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 812 ((request->u.ata.lba >> 24) & 0x0f)); 813 #ifndef ATA_CAM 814 } 815 #endif 816 } 817 } 818 819 static void 820 ata_pio_read(struct ata_request *request, int length) 821 { 822 struct ata_channel *ch = device_get_softc(request->parent); 823 int size = min(request->transfersize, length); 824 int resid; 825 826 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 827 ATA_IDX_INSW_STRM(ch, ATA_DATA, 828 (void*)((uintptr_t)request->data+request->donecount), 829 size / sizeof(int16_t)); 830 else 831 ATA_IDX_INSL_STRM(ch, ATA_DATA, 832 (void*)((uintptr_t)request->data+request->donecount), 833 size / sizeof(int32_t)); 834 835 if (request->transfersize < length) { 836 device_printf(request->parent, "WARNING - %s read data overrun %d>%d\n", 837 ata_cmd2str(request), length, request->transfersize); 838 for (resid = request->transfersize; resid < length; 839 resid += sizeof(int16_t)) 840 ATA_IDX_INW(ch, ATA_DATA); 841 } 842 } 843 844 static void 845 ata_pio_write(struct ata_request *request, int length) 846 { 847 struct ata_channel *ch = device_get_softc(request->parent); 848 int size = min(request->transfersize, length); 849 int resid; 850 851 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 852 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 853 (void*)((uintptr_t)request->data+request->donecount), 854 size / sizeof(int16_t)); 855 else 856 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 857 (void*)((uintptr_t)request->data+request->donecount), 858 size / sizeof(int32_t)); 859 860 if (request->transfersize < length) { 861 device_printf(request->parent, "WARNING - %s write data underrun %d>%d\n", 862 ata_cmd2str(request), length, request->transfersize); 863 for (resid = request->transfersize; resid < length; 864 resid += sizeof(int16_t)) 865 ATA_IDX_OUTW(ch, ATA_DATA, 0); 866 } 867 } 868