1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #define ASMC_MAXFANS 6 31 #define ASMC_MAXVAL 32 /* Maximum SMC value size */ 32 #define ASMC_KEYLEN 4 /* SMC key name length */ 33 #define ASMC_TYPELEN 4 /* SMC type string length */ 34 35 struct asmc_softc { 36 device_t sc_dev; 37 struct mtx sc_mtx; 38 int sc_nfan; 39 int sc_nkeys; 40 int16_t sms_rest_x; 41 int16_t sms_rest_y; 42 int16_t sms_rest_z; 43 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1]; 44 struct sysctl_oid *sc_temp_tree; 45 struct sysctl_oid *sc_sms_tree; 46 struct sysctl_oid *sc_light_tree; 47 const struct asmc_model *sc_model; 48 int sc_rid_port; 49 int sc_rid_irq; 50 struct resource *sc_ioport; 51 struct resource *sc_irq; 52 void *sc_cookie; 53 int sc_sms_intrtype; 54 struct taskqueue *sc_sms_tq; 55 struct task sc_sms_task; 56 uint8_t sc_sms_intr_works; 57 struct cdev *sc_kbd_bkl; 58 uint32_t sc_kbd_bkl_level; 59 #ifdef ASMC_DEBUG 60 /* Raw key access */ 61 struct sysctl_oid *sc_raw_tree; 62 char sc_rawkey[ASMC_KEYLEN + 1]; 63 uint8_t sc_rawval[ASMC_MAXVAL]; 64 uint8_t sc_rawlen; 65 char sc_rawtype[ASMC_TYPELEN + 1]; 66 #endif 67 }; 68 69 /* 70 * Data port. 71 */ 72 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00) 73 #define ASMC_DATAPORT_WRITE(sc, val) \ 74 bus_write_1(sc->sc_ioport, 0x00, val) 75 #define ASMC_STATUS_MASK 0x0f 76 77 /* 78 * Command port. 79 */ 80 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04) 81 #define ASMC_CMDPORT_WRITE(sc, val) \ 82 bus_write_1(sc->sc_ioport, 0x04, val) 83 #define ASMC_CMDREAD 0x10 84 #define ASMC_CMDWRITE 0x11 85 #define ASMC_CMDGETBYINDEX 0x12 86 #define ASMC_CMDGETINFO 0x13 87 88 #define ASMC_STATUS_AWAIT_DATA 0x04 89 #define ASMC_STATUS_DATA_READY 0x05 90 91 #define ASMC_KEYINFO_RESPLEN 6 /* getinfo: 1 len + 4 type + 1 attr */ 92 #define ASMC_MAXRETRIES 10 93 94 /* 95 * Interrupt port. 96 */ 97 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f) 98 99 /* Number of keys */ 100 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */ 101 102 /* Query the ASMC revision */ 103 #define ASMC_KEY_REV "REV " /* RO: 6 bytes */ 104 105 /* 106 * Fan control via SMC. 107 */ 108 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */ 109 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */ 110 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */ 111 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */ 112 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RW; 2 bytes */ 113 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */ 114 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */ 115 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */ 116 117 /* 118 * Sudden Motion Sensor (SMS). 119 */ 120 #define ASMC_SMS_INIT1 0xe0 121 #define ASMC_SMS_INIT2 0xf8 122 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */ 123 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */ 124 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */ 125 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */ 126 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */ 127 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */ 128 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */ 129 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */ 130 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */ 131 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */ 132 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */ 133 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */ 134 135 /* 136 * Light Sensor. 137 */ 138 #define ASMC_ALSL_INT2A 0x2a /* Ambient Light related Interrupt */ 139 140 /* 141 * Keyboard backlight. 142 */ 143 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */ 144 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */ 145 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */ 146 147 /* 148 * Clamshell. 149 */ 150 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */ 151 152 /* 153 * Auto power on / Wake-on-LAN. 154 */ 155 #define ASMC_KEY_AUPO "AUPO" /* RW; 1 byte */ 156 157 /* 158 * Interrupt keys. 159 */ 160 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */ 161 162 /* 163 * Temperatures. 164 * 165 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini, 166 * fourth the Mac Pro 8-core and finally the MacBook Air. 167 * 168 */ 169 /* maximum array size for temperatures including the last NULL */ 170 #define ASMC_TEMP_MAX 80 171 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \ 172 "TM0P", NULL } 173 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \ 174 "northbridge2", "heatsink1", \ 175 "heatsink2", "memory", } 176 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \ 177 "Northbridge Point 1", \ 178 "Northbridge Point 2", "Heatsink 1", \ 179 "Heatsink 2", "Memory Bank A", } 180 181 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \ 182 "TM0P", NULL } 183 184 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \ 185 "heatsink1", "heatsink2", \ 186 "memory", } 187 188 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \ 189 "Northbridge Point 1", \ 190 "Heatsink 1","Heatsink 2" \ 191 "Memory Bank A", } 192 193 #define ASMC_MB71_TEMPS { "TB0T", "TB1T", "TB2T", "TC0D", "TC0P", \ 194 "TH0P", "TN0D", "TN0P", "TN0S", "TN1D", \ 195 "TN1E", "TN1F", "TN1G", "TN1S", "Th1H", \ 196 "Ts0P", "Ts0S", NULL } 197 198 #define ASMC_MB71_TEMPNAMES { "enclosure_bottom0", "battery_1", "battery_2", "cpu_package", "cpu_proximity", \ 199 "hdd_bay", "northbridge0_diode", "northbridge0_proximity", "TN0S", "mpc_die2", \ 200 "TN1E", "TN1F", "TN1G", "TN1S", "heatsink1", \ 201 "palm_rest", "memory_proximity", } 202 203 #define ASMC_MB71_TEMPDESCS { "Enclosure Bottom 0", "Battery 1", "Battery 2", "CPU Package", "CPU Proximity", \ 204 "HDD Bay", "Northbridge Diode", "Northbridge Proximity", "TN0S", "MPC Die 2", \ 205 "TN1E", "TN1F", "TN1G", "TN1S", "Heatsink 1", \ 206 "Palm Rest", "Memory Proximity", } 207 208 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \ 209 "TG0H", "TG0P", "TG0T", NULL } 210 211 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \ 212 "heatsink2", "memory", "graphics", \ 213 "graphicssink", "unknown", } 214 215 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \ 216 "Heatsink 1", "Heatsink 2", \ 217 "Memory Controller", \ 218 "Graphics Chip", "Graphics Heatsink", \ 219 "Unknown", } 220 221 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \ 222 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \ 223 "TTF0", "TW0P", NULL } 224 225 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \ 226 "heatsink3", "memory", "graphicssink", \ 227 "graphics", "cpu", "cpu2", "unknown1", \ 228 "unknown2", "wireless", } 229 230 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \ 231 "Main Heatsink 1", "Main Heatsink 2", \ 232 "Main Heatsink 3", \ 233 "Memory Controller", \ 234 "Graphics Chip Heatsink", \ 235 "Graphics Chip Diode", \ 236 "CPU Temperature Diode", "CPU Point 2", \ 237 "Unknown", "Unknown", \ 238 "Wireless Module", } 239 240 #define ASMC_MBP51_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \ 241 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \ 242 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \ 243 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \ 244 NULL } 245 246 #define ASMC_MBP51_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 247 "enclosure_bottom_2", "enclosure_bottom_3", \ 248 "cpu_diode", "cpu", \ 249 "cpu_pin", "gpu_diode", \ 250 "gpu", "gpu_heatsink", \ 251 "gpu_pin", "gpu_transistor", \ 252 "gpu_2_heatsink", "northbridge_diode", \ 253 "northbridge_pin", "unknown", \ 254 "heatsink_2", "memory_controller", \ 255 "pci_express_slot_pin", "pci_express_slot_unk" } 256 257 #define ASMC_MBP51_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 258 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 259 "CPU Diode", "CPU ???", \ 260 "CPU Pin", "GPU Diode", \ 261 "GPU ???", "GPU Heatsink", \ 262 "GPU Pin", "GPU Transistor", \ 263 "GPU 2 Heatsink", "Northbridge Diode", \ 264 "Northbridge Pin", "Unknown", \ 265 "Heatsink 2", "Memory Controller", \ 266 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 267 268 #define ASMC_MBP62_TEMPS { "TB0T", "TB1T", "TB2T", \ 269 "TC0C", "TC0D", "TC0P", \ 270 "TC1C", "TG0D", "TG0P", \ 271 "TG0T", "TMCD", "TP0P", \ 272 "TPCD", "Th1H", "Th2H", \ 273 "Tm0P", "Ts0P", "Ts0S" } 274 275 #define ASMC_MBP62_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 276 "enclosure_bottom_2", "cpu0", \ 277 "cpu_diode", "cpu_proximity", \ 278 "cpu1", "gpu_diode", \ 279 "gpu_pin", "gpu_transistor", \ 280 "TMCD", "pch_controller_proximity", \ 281 "pch_die", "heatsink1", \ 282 "heatsink2", "memory-controller", \ 283 "palmrest", "memoryproximity" } 284 285 #define ASMC_MBP62_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 286 "Enclosure Bottom 2", "CPU 0", \ 287 "CPU Diode", "CPU Proximity", \ 288 "CPU 1", "GPU Diode", \ 289 "GPU Pin", "GPU Transistor", \ 290 "TMCD", "PCH Controller Proximity", \ 291 "PCH Die", "Heat Sink 1", \ 292 "Heat Sink 2", "Memory Controller", \ 293 "Palm Rest", "Memory Proximity" } 294 295 #define ASMC_MBP55_TEMPS { "TB0T", "TB1T", \ 296 "TB2T", "TB3T", \ 297 "TC0D", "TC0P", \ 298 "TN0D", "TN0P", \ 299 "TTF0", \ 300 "Th0H", "Th1H", "ThFH", \ 301 "Ts0P", "Ts0S", \ 302 NULL } 303 304 #define ASMC_MBP55_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 305 "enclosure_bottom_2", "enclosure_bottom_3", \ 306 "cpu_diode", "cpu_pin", \ 307 "northbridge_diode", "northbridge_pin", \ 308 "unknown", \ 309 "heatsink_0", "heatsink_1", "heatsink_2", \ 310 "pci_express_slot_pin", "pci_express_slot_unk" } 311 312 #define ASMC_MBP55_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 313 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 314 "CPU Diode", "CPU Pin", \ 315 "Northbridge Diode", "Northbridge Pin", \ 316 "Unknown", \ 317 "Heatsink 0", "Heatsink 1", "Heatsink 2", \ 318 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 319 320 #define ASMC_MBP81_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 321 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 322 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 323 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 324 "Ts0S", NULL } 325 326 #define ASMC_MBP81_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 327 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 328 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 329 "TP0P", "TPCD", "wireless", "Th1H", "Ts0P", \ 330 "Ts0S" } 331 332 #define ASMC_MBP81_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 333 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 334 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 335 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 336 "Ts0S" } 337 338 #define ASMC_MBP82_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 339 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 340 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 341 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 342 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 343 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL } 344 345 #define ASMC_MBP82_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 346 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 347 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 348 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \ 349 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \ 350 "Th2H", "memory", "Ts0P", "Ts0S" } 351 352 #define ASMC_MBP82_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 353 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 354 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 355 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 356 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 357 "Th2H", "Tm0P", "Ts0P", "Ts0S" } 358 359 #define ASMC_MBP83_TEMPS { "ALSL", "F0Ac", "F1Ac", "IB0R", "IC0R", \ 360 "ID0R", "IG0R", "IO0R", "PCPC", "PCPG", \ 361 "PCPT", "PD0R", "TB1T", "TB2T", "TC0C", \ 362 "TC0D", "TC0P", "TC1C", "TC2C", "TC3C", \ 363 "TC4C", "TG0D", "TG0P", "THSP", "TP0P", \ 364 "TPCD", "Th1H", "Th2H", "Tm0P", "Ts0P", \ 365 "VC0C", "VD0R", "VG0C", "VN0C", "VP0R", NULL } 366 367 #define ASMC_MBP83_TEMPNAMES { "ambient_light", "fan_leftside", "fan_rightside", \ 368 "battery_current", "cpu_vcorevtt", "dc_current", \ 369 "gpu_voltage", "other", "cpu_package_core", \ 370 "cpu_package_gpu", "cpu_package_total", "dc_in", \ 371 "battery_1", "battery_2", "cpu_die_digital", \ 372 "cpu_die_analog", "cpu_proximity", "cpu_core_1", \ 373 "cpu_core_2", "cpu_core_3", "cpu_core_4", "gpu_die_analog", \ 374 "gpu_proximity", "thunderbolt", "platform_controller", \ 375 "pch_die_digital", "right_fin_stack", "left_fin_stack", \ 376 "dc_in_air_flow", "palm_rest", "cpu_vcore", "dc_in_voltage", \ 377 "gpu_vcore", "intel_gpu_vcore", "pbus_voltage" } 378 379 #define ASMC_MBP83_TEMPDESCS { "Ambient Light", "Fan Leftside", "Fan Rightside", \ 380 "Battery BMON Current", "CPU VcoreVTT", "DC In AMON Current", \ 381 "GPU Voltage", "Other 5V 3V", "CPU Package Core", \ 382 "CPU Package GPU", "CPU Package Total", "DC In", \ 383 "Battery Sensor 1", "Battery Sensor 2", "CPU Die Digital", \ 384 "CPU Die Analog", "CPU Proximity", "CPU Core 1 DTS", \ 385 "CPU Core 2 DTS", "CPU Core 3 DTS", "CPU Core 4 DTS", \ 386 "GPU Die Analog", "GPU Proximity", "Thunderbolt Proximity", \ 387 "Platform Controller Hub", "PCH Die Digital", \ 388 "Right Fin Stack Proximity", "Left Fin Stack Proximity", \ 389 "DC In Proximity Air Flow", "Palm Rest", "CPU VCore", \ 390 "DC In Voltage", "GPU VCore", "Intel GPU VCore", "PBus Voltage" } 391 392 #define ASMC_MBP91_TEMPS { "TA0P", "TB0T", "TB1T", "TB2T", "TC0E", \ 393 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 394 "TC4C", "TCGC", "TCSA", "TCXC", "TG0D", \ 395 "TG0P", "TG1D", "TG1F", "TG1d", "TGTC", \ 396 "TGTD", "TM0P", "TM0S", "TP0P", "TPCD", \ 397 "Th1H", "Th2H", "Ts0P", "Ts0S", "Tsqf", NULL } 398 399 #define ASMC_MBP91_TEMPNAMES { "ambient", "enclosure_bottom_1", "enclosure_bottom_2", \ 400 "enclosure_bottom_3", "cpu_die_peci_0", "cpu_die_peci_1", \ 401 "cpu_proximity", "cpu_core_1", "cpu_core_2", "cpu_core_3", \ 402 "cpu_core_4", "intel_gpu", "cpu_sys_agent", \ 403 "cpu_core_peci", "gpu_analog", \ 404 "gpu_proximity", "geforce_gpu_digital", "tg1f", \ 405 "gpu_2_die", "tgtc", "tgtd", "memory_proximity", \ 406 "mem_bank_a1", "platform_ctrl_hub", "pch_digital", \ 407 "main_heatsink_r", "main_heatsink_l", "palm_rest", \ 408 "bottom_skin", "tsqf" } 409 410 #define ASMC_MBP91_TEMPDESCS { "Ambient", "Enclosure Bottom 1", "Enclosure Bottom 2", \ 411 "Enclosure Bottom 3", "CPU Die PECI 0", "CPU Die PECI 1", \ 412 "CPU Proximity", "CPU Core 1", "CPU Core 2", \ 413 "CPU Core 3", "CPU Core 4", "Intel GPU", \ 414 "CPU System Agent Core", "CPU Core - PECI", \ 415 "GPU Die - Analog", "GPU Proximity", \ 416 "GeForce GPU Die - Digital", "TG1F", "GPU 2 Die" \ 417 "TGTC", "TGTD", "Memory Proximity", \ 418 "Memory Bank A1", "Platform Controller Hub", "PCH Die - Digital", \ 419 "Main Heatsink Right", "Main Heatsink Left", "Palm Rest", \ 420 "Bottom Skin", "Tsqf" } 421 422 #define ASMC_MBP92_TEMPS { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 423 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 424 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 425 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 426 "TPCD", NULL } 427 428 #define ASMC_MBP92_TEMPNAMES { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 429 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 430 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 431 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 432 "TPCD" } 433 434 #define ASMC_MBP92_TEMPDESCS { "Palm Rest", "Memory Proximity", "Airflow 1", \ 435 "Battery 1", "Battery 2", "Battery TS_MAX", \ 436 "CPU Core 1", "CPU Core 2", "CPU1", "CPU1", \ 437 "TC0J", "CPU 1 Proximity", "TCFC", \ 438 "PECI GPU", "PECI SA", "TCTD", "PECI CPU", \ 439 "GPU Die", "Memory Bank A1", "Memory Module A1", \ 440 "PCH Die" } 441 442 #define ASMC_MBP112_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 443 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 444 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 445 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 446 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 447 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 448 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 449 "Ts1S", NULL } 450 451 #define ASMC_MBP112_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 452 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 453 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 454 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 455 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 456 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 457 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 458 "Ts1S" } 459 460 #define ASMC_MBP112_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 461 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 462 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 463 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 464 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 465 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 466 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 467 "Ts1S" } 468 469 #define ASMC_MBP113_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 470 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 471 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 472 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 473 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 474 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 475 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 476 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 477 "Ts1S", NULL } 478 479 #define ASMC_MBP113_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 480 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 481 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 482 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 483 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 484 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 485 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 486 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 487 "Ts1S" } 488 489 #define ASMC_MBP113_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 490 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 491 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 492 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 493 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 494 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 495 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 496 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 497 "Ts1S" } 498 499 #define ASMC_MBP114_TEMPS { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 500 "IO3R", "IO5R", "IM0C", "IC1C", "IC2C", \ 501 "IC3C", "ILDC", "IBLC", "IAPC", "IHSC", \ 502 "ICMC", "TC0P", "TP0P", "TM0P", \ 503 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 504 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 505 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 506 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 507 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 508 "PCPG", "PCPT", "PSTR", "PDTR", NULL } 509 510 #define ASMC_MBP114_TEMPNAMES { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 511 "IO3R", "IO5R", "IM0C", "IC1C", "IC2C", \ 512 "IC3C", "ILDC", "IBLC", "IAPC", "IHSC", \ 513 "ICMC", "TC0P", "TP0P", "TM0P", \ 514 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 515 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 516 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 517 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 518 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 519 "PCPG", "PCPT", "PSTR", "PDTR" } 520 521 #define ASMC_MBP114_TEMPDESCS { "CPU High (CPU, I/O)", "DC In", "SSD", "Charger (BMON)", "CPU", \ 522 "Other 3.3V", "Other 5V", "Memory", "Platform Controller Hub Core", "CPU Load Current Monitor", \ 523 "CPU DDR", "LCD Panel", "LCD Backlight", "Airport", "Thunderbolt", \ 524 "S2", "CPU Proximity", "Platform Controller Hub", "Memory Proximity", "Air Flow Proximity", \ 525 "Left Fin Stack", "Right Fin Stack", "Airport Proximity", "Palm Rest", "Palm Rest Actuator", \ 526 "Battery Max", "Battery Sensor 1", "Battery Sensor 2", "SSD A", "SSD B", \ 527 "CPU Core 1", "CPU Core 2", "CPU Core 3", "CPU Core 4", "CPU PECI Die", \ 528 "Intel GPU", "Platform Controller Hub PECI", "CPU System Agent Core", "CPU VCore", "DC In", \ 529 "Pbus", "Ambient Light", "Leftside", "Rightside", "CPU Package Core", \ 530 "CPU Package GPU", "CPU Package Total", "System Total", "DC In" } 531 532 /* MacBookPro11,5 - same as 11,4 but without IBLC, ICMC, and IC2C keys */ 533 #define ASMC_MBP115_TEMPS { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 534 "IO3R", "IO5R", "IM0C", "IC1C", \ 535 "IC3C", "ILDC", "IAPC", "IHSC", \ 536 "TC0P", "TP0P", "TM0P", \ 537 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 538 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 539 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 540 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 541 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 542 "PCPG", "PCPT", "PSTR", "PDTR", NULL } 543 544 545 #define ASMC_MBP115_TEMPNAMES { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 546 "IO3R", "IO5R", "IM0C", "IC1C", \ 547 "IC3C", "ILDC", "IAPC", "IHSC", \ 548 "TC0P", "TP0P", "TM0P", \ 549 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 550 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 551 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 552 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 553 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 554 "PCPG", "PCPT", "PSTR", "PDTR" } 555 556 #define ASMC_MBP115_TEMPDESCS { "CPU High (CPU, I/O)", "DC In", "SSD", "Charger (BMON)", "CPU", \ 557 "Other 3.3V", "Other 5V", "Memory", "Platform Controller Hub Core", \ 558 "CPU DDR", "LCD Panel", "Airport", "Thunderbolt", \ 559 "CPU Proximity", "Platform Controller Hub", "Memory Proximity", "Air Flow Proximity", \ 560 "Left Fin Stack", "Right Fin Stack", "Airport Proximity", "Palm Rest", "Palm Rest Actuator", \ 561 "Battery Max", "Battery Sensor 1", "Battery Sensor 2", "SSD A", "SSD B", \ 562 "CPU Core 1", "CPU Core 2", "CPU Core 3", "CPU Core 4", "CPU PECI Die", \ 563 "Intel GPU", "Platform Controller Hub PECI", "CPU System Agent Core", "CPU VCore", "DC In", \ 564 "Pbus", "Ambient Light", "Leftside", "Rightside", "CPU Package Core", \ 565 "CPU Package GPU", "CPU Package Total", "System Total", "DC In" } 566 567 #define ASMC_MBP131_TEMPS { "TB0T", "TB1T", "TB2T", "TC0F", \ 568 "TC0P", "TC1C", "TC2C", "TCGC", \ 569 "TCSA", "TCXC", "Th1H", "TM0P", \ 570 "TPCD", "Ts0P", "Ts0S", "TaLC", \ 571 "Ts1P", NULL } 572 573 #define ASMC_MBP131_TEMPNAMES { "battery", "battery_1", "battery_2", "cpu_die_peci", \ 574 "cpu_proximity", "cpu_core_1", "cpu_core_2", "intel_gpu", \ 575 "cpu_sys_agent", "cpu_core_peci", "right_fin_stack", "memory_proximity", \ 576 "platform_ctrl_hub", "trackpad", "bottom_skin", "air_flow", \ 577 "trackpad_act" } 578 579 #define ASMC_MBP131_TEMPDESCS { "Battery", "Battery Sensor 1", "Battery Sensor 2", "CPU Die (PECI)", \ 580 "CPU Proximity", "CPU Core 1", "CPU Core 2", "Intel GPU", \ 581 "CPU System Agent Core (PECI)", "CPU Core (PECI)", "Right Fin Stack", "DDR3 Proximity", \ 582 "Platform Controller Hub Die", "Trackpad", "Bottom Skin", "Air Flow", \ 583 "Trackpad Actuator" } 584 585 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL } 586 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" } 587 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \ 588 "Northbridge Point 2" } 589 590 #define ASMC_MM21_TEMPS { "TA0P", "TC0D", \ 591 "TC0H", "TC0P", \ 592 "TC1P", "TN0P", \ 593 "TN1P", NULL } 594 595 #define ASMC_MM21_TEMPNAMES { "ambient_air", "cpu_die", \ 596 "cpu_heatsink", "cpu_proximity1", \ 597 "cpu_proximity2", "northbridge_proximity1", \ 598 "northbridge_proximity2", } 599 600 #define ASMC_MM21_TEMPDESCS { "Ambient Air Temperature" \ 601 "CPU Die Core Temperature", \ 602 "CPU Heatsink Temperature", \ 603 "CPU Proximity 1 Temperature", \ 604 "CPU Proximity 2 Temperature", \ 605 "Northbridge Proximity 1 Temperature", \ 606 "Northbridge Proximity 2 Temperature", } 607 608 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \ 609 "TC0P", "TH0P", \ 610 "TN0D", "TN0P", \ 611 "TW0P", NULL } 612 613 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \ 614 "cpu0_proximity", "hdd_bay", \ 615 "northbridge_die", \ 616 "northbridge_proximity", \ 617 "wireless_proximity", } 618 619 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \ 620 "CPU0 Heatsink Temperature", \ 621 "CPU0 Proximity Temperature", \ 622 "HDD Bay Temperature", \ 623 "Northbridge Die Core Temperature", \ 624 "Northbridge Proximity Temperature", \ 625 "Wireless Module Proximity Temperature", } 626 627 #define ASMC_MM41_TEMPS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 628 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 629 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 630 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 631 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 632 "TW0P", "Tm0P", "Tp0C", NULL } 633 634 #define ASMC_MM41_TEMPNAMES { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 635 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 636 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 637 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 638 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 639 "TW0P", "Tm0P", "Tp0C", NULL } 640 641 #define ASMC_MM41_TEMPDESCS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 642 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 643 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 644 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 645 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 646 "TW0P", "Tm0P", "Tp0C", NULL } 647 648 #define ASMC_MM52_TEMPS { "TA0P", "TA1P", \ 649 "TC0D", "TC0P", \ 650 "TG0D", "TG1D", \ 651 "TG0P", "TG0M", \ 652 "TI0P", \ 653 "TM0S", "TMBS", \ 654 "TM0P", "TP0P", \ 655 "TPCD", "Tp0C", \ 656 "TW0P", NULL } 657 658 #define ASMC_MM52_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 659 "cpu_die", "cpu_proximity", \ 660 "gpu_diode1", "gpu_diode2", \ 661 "gpu_proximity", "gpu_integrated_switcher", \ 662 "thunderbolt_proximity", \ 663 "memory_slot1", "memory_slot2", \ 664 "memory_proximity", "pch_controller_proximity", \ 665 "pch_controller_die", "pwr_supply", \ 666 "wireless_proximity", } 667 668 #define ASMC_MM52_TEMPDESCS { "Ambient Air Proximity Temperature", \ 669 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 670 "CPU Die Temperature", "CPU Proximity Temperature", \ 671 "GPU Diode 1 Temperature" , "GPU Diode 2 Temperature", \ 672 "GPU Proximity Temperature", \ 673 "Integrated Graphics/GPU Switcher Temperature", \ 674 "Thunderbolt Proximity Temperature", \ 675 "Memory Slot 1 Temperature", \ 676 "Memory Slot 2 Temperature", \ 677 "Memory Slots Proximity Temperature", \ 678 "Platform Controller Hub Proximity Temperature", \ 679 "Platform Controller Hub Die Temperature", \ 680 "Power Supply Temperature", \ 681 "Wireless Module Proximity Temperature", } 682 683 #define ASMC_MM61_TEMPS { "TA0P", "TA1P", \ 684 "TC0D", "TC0G", "TC0P", "TCPG", \ 685 "TI0P", \ 686 "TM0S", "TMBS", "TM0P", \ 687 "TP0P", "TPCD", \ 688 "Tp0C", \ 689 "TW0P", NULL } 690 691 #define ASMC_MM61_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 692 "cpu_die", "TC0G", "cpu_proximity", "TCPG", \ 693 "thunderbolt_proximity", \ 694 "memory_slot1", "memory_slot2", "memory_proximity", \ 695 "pch_controller_proximity", "pch_controller_die", \ 696 "pwr_supply", \ 697 "wireless_proximity", NULL } 698 699 #define ASMC_MM61_TEMPDESCS { "Ambient Air Proximity Temperature", \ 700 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 701 "CPU Die Temperature", \ 702 NULL, \ 703 "CPU Proximity Temperature", \ 704 NULL, \ 705 "Thunderbolt Proximity Temperature", \ 706 "Memory Slot 1 Temperature", \ 707 "Memory Slot 2 Temperature", \ 708 "Memory Slots Proximity Temperature", \ 709 "Platform Controller Hub Proximity Temperature", \ 710 "Platform Controller Hub Die Temperature", \ 711 "Power Supply Temperature", \ 712 "Wireless Module Proximity Temperature", NULL } 713 714 #define ASMC_MM62_TEMPS { "TA0P", "TA1P", \ 715 "TC0D", "TC0G", "TC0P", "TCPG", \ 716 "TI0P", \ 717 "TM0S", "TMBS", "TM0P", \ 718 "TP0P", "TPCD", \ 719 "Tp0C", \ 720 "TW0P", NULL } 721 722 #define ASMC_MM62_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 723 "cpu_die", "TC0G", "cpu_proximity", "TCPG", \ 724 "thunderbolt_proximity", \ 725 "memory_slot1", "memory_slot2", "memory_proximity", \ 726 "pch_controller_proximity", "pch_controller_die", \ 727 "pwr_supply", \ 728 "wireless_proximity", NULL } 729 730 #define ASMC_MM62_TEMPDESCS { "Ambient Air Proximity Temperature", \ 731 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 732 "CPU Die Temperature", \ 733 NULL, \ 734 "CPU Proximity Temperature", \ 735 NULL, \ 736 "Thunderbolt Proximity Temperature", \ 737 "Memory Slot 1 Temperature", \ 738 "Memory Slot 2 Temperature", \ 739 "Memory Slots Proximity Temperature", \ 740 "Platform Controller Hub Proximity Temperature", \ 741 "Platform Controller Hub Die Temperature", \ 742 "Power Supply Temperature", \ 743 "Wireless Module Proximity Temperature", NULL } 744 745 #define ASMC_MM71_TEMPS { "TA0p", "TA1p", \ 746 "TA2p", "TC0c", \ 747 "TC0p", "TC1c", \ 748 "TCGc", "TCSc", \ 749 "TCXC", "TCXR", \ 750 "TM0p", "TPCd", \ 751 "TW0p", "Te0T", \ 752 "Tm0P", NULL } 753 754 #define ASMC_MM71_TEMPNAMES { "ambient_air1", "ambient_air2", \ 755 "ambient_air3", "cpu_core1_peci", \ 756 "cpu_proximity", "cpu_core2_peci", \ 757 "intel_gpu", "cpu_sa_core_peci", \ 758 "cpu_core", "cpu_peci_dts", \ 759 "memory_proximity", "pch_controller_die", \ 760 "wireless_proximity", "thunderbolt_diode", \ 761 "logic_board", } 762 763 #define ASMC_MM71_TEMPDESCS { "Ambient Air Temperature 1", \ 764 "Ambient Air Temperature 2", \ 765 "Ambient Air Temperature 3", \ 766 "CPU Core 1 PECI Temperature", "CPU Proximity Temperature", \ 767 "CPU Core 2 PECI Temperature", "Intel GPU Temperature", \ 768 "CPU System Agent Core PECI Temperature", \ 769 "CPU Core Temperature", "CPU PECI DTS Temperature", \ 770 "Memory Proximity Temperature", \ 771 "Platform Controller Hub Die Temperature", \ 772 "Wireless Module Proximity Temperature", \ 773 "Thunderbolt Diode Temperature", \ 774 "Logic Board temperature", } 775 776 #define ASMC_MP1_TEMPS { "TA0P", \ 777 "TCAH", "TCBH", \ 778 "TC0P", "TC0C", "TC1C", \ 779 "TC2C", "TC3C", "THTG", \ 780 "TH0P", "TH1P", \ 781 "TH2P", "TH3P", \ 782 "TM0P", "TM1P", "TM2P", \ 783 "TM8P", "TM9P", "TMAP", \ 784 "TM0S", "TM1S", "TM2P", "TM3S", \ 785 "TM8S", "TM9S", "TMAS", "TMBS", \ 786 "TN0H", "TS0C", \ 787 "Tp0C", "Tp1C", "Tv0S", "Tv1S", NULL } 788 789 #define ASMC_MP1_TEMPNAMES { "ambient", \ 790 "cpu_a_heatsink", "cpu_b_heatsink", \ 791 "cpu_a_proximity", "cpu_core0", "cpu_core1", \ 792 "cpu_core2", "cpu_core3", "THTG", \ 793 "hdd_bay0", "hdd_bay1", \ 794 "hdd_bay2", "hdd_bay3", \ 795 "memory_card_a_proximity0", \ 796 "memory_card_a_proximity1", \ 797 "memory_card_a_proximity2", \ 798 "memory_card_b_proximity0", \ 799 "memory_card_b_proximity1", \ 800 "memory_card_b_proximity2", \ 801 "memory_card_a_slot0", \ 802 "memory_card_a_slot1", \ 803 "memory_card_a_slot2", \ 804 "memory_card_a_slot3", \ 805 "memory_card_b_slot0", \ 806 "memory_card_b_slot1", \ 807 "memory_card_b_slot2", \ 808 "memory_card_b_slot3", \ 809 "mch_heatsink", "expansion_slots", \ 810 "power_supply_loc0", "power_supply_loc1", \ 811 "Tv0S", "Tv1S", } 812 813 #define ASMC_MP1_TEMPDESCS { "Ambient Air", \ 814 "CPU A Heatsink", "CPU B Heatsink", \ 815 "CPU A Proximity", \ 816 "CPU Core 1", "CPU Core 2", \ 817 "CPU Core 3", "CPU Core 4", "THTG", \ 818 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 819 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 820 "Memory Riser A, Proximity 1", \ 821 "Memory Riser A, Proximity 2", \ 822 "Memory Riser A, Proximity 3", \ 823 "Memory Riser B, Proximity 1", \ 824 "Memory Riser B, Proximity 2", \ 825 "Memory Riser B, Proximity 3", \ 826 "Memory Riser A, Slot 1", \ 827 "Memory Riser A, Slot 2", \ 828 "Memory Riser A, Slot 3", \ 829 "Memory Riser A, Slot 4", \ 830 "Memory Riser B, Slot 1", \ 831 "Memory Riser B, Slot 2", \ 832 "Memory Riser B, Slot 3", \ 833 "Memory Riser B, Slot 4", \ 834 "MCH Heatsink", "Expansion Slots", \ 835 "Power Supply, Location 1", \ 836 "Power Supply, Location 2", \ 837 "Tv0S", "Tv1S", } 838 839 #define ASMC_MP31_TEMPS { "TA0P", \ 840 "TC0C", "TC0D", "TC0P", \ 841 "TC1C", "TC1D", \ 842 "TC2C", "TC2D", \ 843 "TC3C", "TC3D", \ 844 "TCAG", "TCAH", "TCBG", "TCBH", \ 845 "TH0P", "TH1P", "TH2P", "TH3P", \ 846 "TM0P", "TM0S", "TM1P", "TM1S", \ 847 "TM2P", "TM2S", "TM3S", \ 848 "TM8P", "TM8S", "TM9P", "TM9S", \ 849 "TMAP", "TMAS", "TMBS", \ 850 "TN0C", "TN0D", "TN0H", \ 851 "TS0C", \ 852 "Tp0C", "Tp1C", \ 853 "Tv0S", "Tv1S", NULL } 854 855 #define ASMC_MP31_TEMPNAMES { "ambient", \ 856 "cpu_core0", "cpu_diode0", "cpu_a_proximity", \ 857 "cpu_core1", "cpu_diode1", \ 858 "cpu_core2", "cpu_diode2", \ 859 "cpu_core3", "cpu_diode3", \ 860 "cpu_a_pkg", "cpu_a_heatsink", \ 861 "cpu_b_pkg", "cpu_b_heatsink", \ 862 "hdd_bay0", "hdd_bay1", \ 863 "hdd_bay2", "hdd_bay3", \ 864 "mem_riser_a_prox0", "mem_riser_a_slot0", \ 865 "mem_riser_a_prox1", "mem_riser_a_slot1", \ 866 "mem_riser_a_prox2", "mem_riser_a_slot2", \ 867 "mem_riser_a_slot3", \ 868 "mem_riser_b_prox0", "mem_riser_b_slot0", \ 869 "mem_riser_b_prox1", "mem_riser_b_slot1", \ 870 "mem_riser_b_prox2", "mem_riser_b_slot2", \ 871 "mem_riser_b_slot3", \ 872 "northbridge_core", "northbridge_diode", \ 873 "northbridge_heatsink", \ 874 "expansion_slots", \ 875 "power_supply0", "power_supply1", \ 876 "vrm0", "vrm1", } 877 878 #define ASMC_MP31_TEMPDESCS { "Ambient Air", \ 879 "CPU Core 1", "CPU Diode 1", \ 880 "CPU A Proximity", \ 881 "CPU Core 2", "CPU Diode 2", \ 882 "CPU Core 3", "CPU Diode 3", \ 883 "CPU Core 4", "CPU Diode 4", \ 884 "CPU A Package", "CPU A Heatsink", \ 885 "CPU B Package", "CPU B Heatsink", \ 886 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 887 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 888 "Memory Riser A, Proximity 1", \ 889 "Memory Riser A, Slot 1", \ 890 "Memory Riser A, Proximity 2", \ 891 "Memory Riser A, Slot 2", \ 892 "Memory Riser A, Proximity 3", \ 893 "Memory Riser A, Slot 3", \ 894 "Memory Riser A, Slot 4", \ 895 "Memory Riser B, Proximity 1", \ 896 "Memory Riser B, Slot 1", \ 897 "Memory Riser B, Proximity 2", \ 898 "Memory Riser B, Slot 2", \ 899 "Memory Riser B, Proximity 3", \ 900 "Memory Riser B, Slot 3", \ 901 "Memory Riser B, Slot 4", \ 902 "Northbridge Core", "Northbridge Diode", \ 903 "Northbridge Heatsink", \ 904 "Expansion Slots", \ 905 "Power Supply 1", "Power Supply 2", \ 906 "VRM 1", "VRM 2", } 907 908 #define ASMC_MP2_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 909 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 910 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 911 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 912 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 913 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 914 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \ 915 NULL } 916 917 #define ASMC_MP2_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 918 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 919 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 920 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 921 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 922 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 923 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 924 925 #define ASMC_MP2_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 926 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 927 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 928 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 929 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 930 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 931 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 932 933 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 934 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 935 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 936 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 937 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 938 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 939 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 940 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 941 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 942 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 943 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 944 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 945 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 946 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 947 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \ 948 NULL } 949 950 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \ 951 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 952 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 953 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 954 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 955 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 956 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 957 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \ 958 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \ 959 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \ 960 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 961 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 962 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 963 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 964 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 965 966 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 967 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 968 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 969 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 970 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 971 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 972 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 973 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 974 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 975 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 976 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 977 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 978 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 979 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 980 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 981 982 #define ASMC_MP6_TEMPS { "TA0P", "TA1P", "TC0P", "TG0D", "TG0P", \ 983 "TG1D", "TG1P", "TM0P", "TM1P", NULL } 984 985 #define ASMC_MP6_TEMPNAMES { "ambient_air_1", "ambient_air_2", \ 986 "cpu_proximity", "gpu_diode_1", \ 987 "gpu_proximity_1", "gpu_diode_2", \ 988 "gpu_proximity_2", "mem_proximity_1", \ 989 "mem_proximity_2" } 990 991 #define ASMC_MP6_TEMPDESCS { "Ambient Air 1", "Ambient Air 2", \ 992 "CPU Proximity", "GPU Diode 1", \ 993 "GPU Proximity 1", "GPU Diode 2", \ 994 "GPU Proximity 2", "Memory Bank A", \ 995 "Memory Bank B" } 996 997 #define ASMC_MBA_TEMPS { "TB0T", NULL } 998 #define ASMC_MBA_TEMPNAMES { "enclosure" } 999 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" } 1000 1001 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \ 1002 "TC0D", "TC0E", "TC0P", NULL } 1003 1004 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \ 1005 "TC0D", "TC0E", "TC0P" } 1006 1007 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \ 1008 "TC0D", "TC0E", "TC0P" } 1009 1010 #define ASMC_MBA4_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 1011 "TC0D", "TC0E", "TC0F", "TC0P", \ 1012 "TC1C", "TC2C", "TCGC", "TCSA", \ 1013 "TH0F", "TH0J", "TH0O", "TH0o", \ 1014 "TM0P", "TPCD", "Ta0P", "Th1H", \ 1015 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 1016 NULL } 1017 1018 #define ASMC_MBA4_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TC0C", \ 1019 "TC0D", "TC0E", "TC0F", "TC0P", \ 1020 "TC1C", "TC2C", "TCGC", "TCSA", \ 1021 "TH0F", "TH0J", "TH0O", "TH0o", \ 1022 "TM0P", "TPCD", "Ta0P", "Th1H", \ 1023 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 1024 NULL } 1025 1026 #define ASMC_MBA4_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TC0C", \ 1027 "TC0D", "TC0E", "TC0F", "TC0P", \ 1028 "TC1C", "TC2C", "TCGC", "TCSA", \ 1029 "TH0F", "TH0J", "TH0O", "TH0o", \ 1030 "TM0P", "TPCD", "Ta0P", "Th1H", \ 1031 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 1032 NULL } 1033 1034 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 1035 "TC0D", "TC0E", "TC0F", "TC0P", \ 1036 "TC1C", "TC2C", "TCGC", "TCSA", \ 1037 "TCXC", "THSP", "TM0P", "TPCD", \ 1038 "Ta0P", "Th1H", "Tm0P", "Tm1P", \ 1039 "Ts0P", "Ts0S", NULL } 1040 1041 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \ 1042 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \ 1043 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 1044 "TCXC", "THSP", "memorybank", "pchdie", \ 1045 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \ 1046 "palmrest", "memoryproximity" } 1047 1048 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\ 1049 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1050 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 1051 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 1052 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \ 1053 "Palm Rest", "Memory Proximity" } 1054 1055 /* 1056 * TODO: validate the temp zones for MBA 6.x ! 1057 */ 1058 #define ASMC_MBA6_TEMPS { "TB0T", "TB1T", "TB2T", \ 1059 "TC0E", "TC0F", "TC0P", \ 1060 "TC1C", "TC2C", "TCGC", "TCSA", \ 1061 "TCXC", "THSP", "TM0P", "TPCD", \ 1062 "Ta0P", "Th1H", "Tm0P", \ 1063 "Ts0P", "Ts0S", NULL } 1064 1065 #define ASMC_MBA6_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 1066 "cputemp1", "cputemp2", "cpuproximity", \ 1067 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 1068 "TCXC", "THSP", "memorybank", "pchdie", \ 1069 "Ta0P", "heatpipe", "mainboardproximity1", \ 1070 "palmrest", "memoryproximity" } 1071 1072 #define ASMC_MBA6_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 1073 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1074 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 1075 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 1076 "Ta0P", "Heatpipe", "Mainboard Proximity 1", \ 1077 "Palm Rest", "Memory Proximity" } 1078 1079 1080 #define ASMC_MBA7_TEMPS { "TB0T", "TB1T", "TB2T", \ 1081 "TC0E", "TC0F", "TC0P", \ 1082 "TC1C", "TC2C", \ 1083 "TCGC", "TCSA", "TCXC", \ 1084 "THSP", "TM0P", "TPCD", \ 1085 "TW0P" "Ta0P", "Th1H", \ 1086 "Tm0P", "Ts0P", "Ts0S", NULL } 1087 1088 #define ASMC_MBA7_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 1089 "cputemp1", "cputemp2", "cpuproximity", \ 1090 "cpucore1", "cpucore2", \ 1091 "pecigpu", "pecisa", "pecicpu", \ 1092 "thunderboltproximity", "memorybank", "pchdie", \ 1093 "wirelessproximity", "airflowproximity", "heatpipe", \ 1094 "mainboardproximity", "palmrest", "memoryproximity" } 1095 1096 #define ASMC_MBA7_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 1097 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1098 "CPU Core 1", "CPU Core 2", \ 1099 "PECI GPU", "PECI SA", "PECI CPU", \ 1100 "Thunderbolt Proximity", "Memory Bank A", "PCH Die", \ 1101 "Wireless Proximity", "Airflow Proxmity", "Heatpipe", \ 1102 "Mainboard Proximity", "Palm Rest", "Memory Proximity" } 1103