1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 14 ** 15 ** Redistribution and use in source and binary forms,with or without 16 ** modification,are permitted provided that the following conditions 17 ** are met: 18 ** 1. Redistributions of source code must retain the above copyright 19 ** notice,this list of conditions and the following disclaimer. 20 ** 2. Redistributions in binary form must reproduce the above copyright 21 ** notice,this list of conditions and the following disclaimer in the 22 ** documentation and/or other materials provided with the distribution. 23 ** 3. The name of the author may not be used to endorse or promote products 24 ** derived from this software without specific prior written permission. 25 ** 26 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 28 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 30 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 31 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 33 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 34 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 35 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 ************************************************************************** 37 * $FreeBSD$ 38 */ 39 #define ARCMSR_SCSI_INITIATOR_ID 255 40 #define ARCMSR_DEV_SECTOR_SIZE 512 41 #define ARCMSR_MAX_XFER_SECTORS 4096 42 #define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 43 #define ARCMSR_MAX_TARGETLUN 8 /*8*/ 44 #define ARCMSR_MAX_CHIPTYPE_NUM 4 45 #define ARCMSR_MAX_OUTSTANDING_CMD 256 46 #define ARCMSR_MAX_START_JOB 256 47 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 48 #define ARCMSR_MAX_FREESRB_NUM 384 49 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 50 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 51 #define ARCMSR_MAX_ADAPTER 4 52 #define ARCMSR_RELEASE_SIMQ_LEVEL 230 53 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ 54 #define ARCMSR_MAX_HBD_POSTQUEUE 256 55 #define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ 56 #define ARCMSR_NUM_MSIX_VECTORS 4 57 /* 58 ********************************************************************* 59 */ 60 #ifndef TRUE 61 #define TRUE 1 62 #endif 63 #ifndef FALSE 64 #define FALSE 0 65 #endif 66 #ifndef INTR_ENTROPY 67 # define INTR_ENTROPY 0 68 #endif 69 70 #ifndef offsetof 71 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 72 #endif 73 74 #if __FreeBSD_version >= 500005 75 #define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF) 76 #define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l) 77 #define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l) 78 #define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l) 79 #define ARCMSR_LOCK_TRY(l) mtx_trylock(l) 80 #define arcmsr_htole32(x) htole32(x) 81 typedef struct mtx arcmsr_lock_t; 82 #else 83 #define ARCMSR_LOCK_INIT(l, s) simple_lock_init(l) 84 #define ARCMSR_LOCK_DESTROY(l) 85 #define ARCMSR_LOCK_ACQUIRE(l) simple_lock(l) 86 #define ARCMSR_LOCK_RELEASE(l) simple_unlock(l) 87 #define ARCMSR_LOCK_TRY(l) simple_lock_try(l) 88 #define arcmsr_htole32(x) (x) 89 typedef struct simplelock arcmsr_lock_t; 90 #endif 91 92 /* 93 ********************************************************************************** 94 ** 95 ********************************************************************************** 96 */ 97 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 98 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 99 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 100 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 101 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 102 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 103 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ 104 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 105 #define PCI_DEVICE_ID_ARECA_1203 0x1203 /* Device ID */ 106 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 107 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 108 #define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */ 109 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 110 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 111 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 112 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 113 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 114 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 115 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 116 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 117 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 118 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 119 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 120 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 121 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 122 #define PCI_DEVICE_ID_ARECA_1884 0x1884 /* Device ID */ 123 124 #define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */ 125 #define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */ 126 #define ARECA_SUB_DEV_ID_1883 0x1883 /* Subsystem Device ID */ 127 #define ARECA_SUB_DEV_ID_1884 0x1884 /* Subsystem Device ID */ 128 #define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */ 129 #define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */ 130 #define ARECA_SUB_DEV_ID_1216 0x1216 /* Subsystem Device ID */ 131 #define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */ 132 #define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */ 133 #define ARECA_SUB_DEV_ID_1226 0x1226 /* Subsystem Device ID */ 134 135 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 136 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 137 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 138 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 139 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 140 #define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 141 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 142 #define PCIDevVenIDARC1203 0x120317D3 /* Vendor Device ID */ 143 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 144 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 145 #define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ 146 #define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */ 147 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 148 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 149 #define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ 150 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 151 #define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 152 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 153 #define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 154 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 155 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 156 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 157 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 158 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 159 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 160 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ 161 #define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */ 162 #define PCIDevVenIDARC1884 0x188417D3 /* Vendor Device ID */ 163 164 #ifndef PCIR_BARS 165 #define PCIR_BARS 0x10 166 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 167 #endif 168 169 #define PCI_BASE_ADDR0 0x10 170 #define PCI_BASE_ADDR1 0x14 171 #define PCI_BASE_ADDR2 0x18 172 #define PCI_BASE_ADDR3 0x1C 173 #define PCI_BASE_ADDR4 0x20 174 #define PCI_BASE_ADDR5 0x24 175 /* 176 ********************************************************************************** 177 ** 178 ********************************************************************************** 179 */ 180 #define ARCMSR_SCSICMD_IOCTL 0x77 181 #define ARCMSR_CDEVSW_IOCTL 0x88 182 #define ARCMSR_MESSAGE_FAIL 0x0001 183 #define ARCMSR_MESSAGE_SUCCESS 0x0000 184 /* 185 ********************************************************************************** 186 ** 187 ********************************************************************************** 188 */ 189 #define arcmsr_ccbsrb_ptr spriv_ptr0 190 #define arcmsr_ccbacb_ptr spriv_ptr1 191 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 192 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 193 #define get_min(x,y) ((x) < (y) ? (x) : (y)) 194 #define get_max(x,y) ((x) < (y) ? (y) : (x)) 195 /* 196 ************************************************************************** 197 ************************************************************************** 198 */ 199 #define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r)) 200 #define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d) 201 #define READ_CHIP_REG32(b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], r) 202 #define WRITE_CHIP_REG32(b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], r, d) 203 /* 204 ********************************************************************************** 205 ** IOCTL CONTROL Mail Box 206 ********************************************************************************** 207 */ 208 struct CMD_MESSAGE { 209 u_int32_t HeaderLength; 210 u_int8_t Signature[8]; 211 u_int32_t Timeout; 212 u_int32_t ControlCode; 213 u_int32_t ReturnCode; 214 u_int32_t Length; 215 }; 216 217 struct CMD_MESSAGE_FIELD { 218 struct CMD_MESSAGE cmdmessage; /* ioctl header */ 219 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 220 }; 221 222 /************************************************************************/ 223 /************************************************************************/ 224 225 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 226 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 227 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 228 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 229 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 230 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 231 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 232 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 233 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 234 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 235 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 236 237 /*DeviceType*/ 238 #define ARECA_SATA_RAID 0x90000000 239 240 /*FunctionCode*/ 241 #define FUNCTION_READ_RQBUFFER 0x0801 242 #define FUNCTION_WRITE_WQBUFFER 0x0802 243 #define FUNCTION_CLEAR_RQBUFFER 0x0803 244 #define FUNCTION_CLEAR_WQBUFFER 0x0804 245 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 246 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 247 #define FUNCTION_SAY_HELLO 0x0807 248 #define FUNCTION_SAY_GOODBYE 0x0808 249 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 250 /* 251 ************************************************************************ 252 ** IOCTL CONTROL CODE 253 ************************************************************************ 254 */ 255 /* ARECA IO CONTROL CODE*/ 256 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 257 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 258 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 259 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 260 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 261 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 262 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 263 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 264 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 265 266 /* ARECA IOCTL ReturnCode */ 267 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 268 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 269 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 270 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 271 /* 272 ************************************************************************ 273 ** SPEC. for Areca HBA adapter 274 ************************************************************************ 275 */ 276 /* signature of set and get firmware config */ 277 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 278 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 279 /* message code of inbound message register */ 280 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 281 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 282 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 283 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 284 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 285 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 286 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 287 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 288 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 289 /* doorbell interrupt generator */ 290 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 291 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 292 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 293 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 294 /* srb areca cdb flag */ 295 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 296 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 297 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 298 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 299 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 300 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 301 /* outbound firmware ok */ 302 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 303 304 #define ARCMSR_ARC1680_BUS_RESET 0x00000003 305 /* 306 ************************************************************************ 307 ** SPEC. for Areca HBB adapter 308 ************************************************************************ 309 */ 310 /* ARECA HBB COMMAND for its FIRMWARE */ 311 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 312 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 313 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 314 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 315 316 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870 /* window of "instruction flags" from iop to driver */ 317 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874 318 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878 /* window of "instruction flags" from driver to iop */ 319 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C 320 321 /* ARECA FLAG LANGUAGE */ 322 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 323 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */ 324 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 325 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 326 327 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 328 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 329 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 330 331 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 332 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 333 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 334 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 335 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 336 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 337 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 338 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 339 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 340 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 341 342 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 343 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */ 344 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 345 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 346 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */ 347 348 /* data tunnel buffer between user space program and its firmware */ 349 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */ 350 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */ 351 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */ 352 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010 353 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018 354 #define ARCMSR_HBB_BASE0_LEN 0x00021000 355 #define ARCMSR_HBB_BASE1_LEN 0x00010000 356 /* 357 ************************************************************************ 358 ** SPEC. for Areca HBC adapter 359 ************************************************************************ 360 */ 361 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 362 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 363 /* Host Interrupt Mask */ 364 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 365 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 366 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 367 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 368 /* Host Interrupt Status */ 369 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 370 /* 371 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 372 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 373 */ 374 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 375 /* 376 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 377 ** value. This bit clears only when Outbound Doorbell bits 378 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 379 ** Clear register clears bits in the Outbound Doorbell register. 380 */ 381 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 382 /* 383 ** Set whenever the Outbound Post List Producer/Consumer 384 ** Register (FIFO) is not empty. It clears when the Outbound 385 ** Post List FIFO is empty. 386 */ 387 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 388 /* 389 ** This bit indicates a SAS interrupt from a source external to 390 ** the PCIe core. This bit is not maskable. 391 */ 392 /* DoorBell*/ 393 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/ 394 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/ 395 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/ 396 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 397 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 398 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 399 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 400 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 401 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 402 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 403 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ 404 #define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024 405 #define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080 406 407 /* 408 ************************************************************************ 409 ** SPEC. for Areca HBD adapter 410 ************************************************************************ 411 */ 412 #define ARCMSR_HBDMU_CHIP_ID 0x00004 413 #define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008 414 #define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034 415 #define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200 416 #define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C 417 #define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400 418 #define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404 419 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420 420 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424 421 #define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460 422 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480 423 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484 424 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000 425 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004 426 #define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018 427 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060 428 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064 429 #define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C 430 #define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070 431 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088 432 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C 433 434 #define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000 435 #define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100 436 #define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200 437 438 #define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16 439 #define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20 440 441 /* Host Interrupt Mask */ 442 #define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */ 443 #define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */ 444 445 /* Host Interrupt Status */ 446 #define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010 447 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000 448 #define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010 449 450 /* DoorBell*/ 451 #define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001 452 #define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002 453 454 #define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001 455 #define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002 456 457 /*outbound message 0 ready*/ 458 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 459 460 #define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003 461 462 /*outbound message cmd isr door bell clear*/ 463 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000 464 465 /*outbound list */ 466 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001 467 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 468 469 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 470 #define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000 471 /* 472 ******************************************************************************* 473 ** SPEC. for Areca HBE adapter 474 ******************************************************************************* 475 */ 476 #define ARCMSR_SIGNATURE_1884 0x188417D3 477 #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001 478 #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 479 #define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 /* disable all ISR */ 480 481 #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002 482 #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004 483 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 /* inbound message 0 ready */ 484 #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002 485 #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004 486 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 /* outbound message 0 ready */ 487 #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK */ 488 /* ARC-1884 doorbell sync */ 489 #define ARCMSR_HBEMU_DOORBELL_SYNC 0x100 490 #define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004 491 /* 492 ********************************************************************* 493 ** Message Unit structure 494 ********************************************************************* 495 */ 496 struct HBA_MessageUnit 497 { 498 u_int32_t resrved0[4]; /*0000 000F*/ 499 u_int32_t inbound_msgaddr0; /*0010 0013*/ 500 u_int32_t inbound_msgaddr1; /*0014 0017*/ 501 u_int32_t outbound_msgaddr0; /*0018 001B*/ 502 u_int32_t outbound_msgaddr1; /*001C 001F*/ 503 u_int32_t inbound_doorbell; /*0020 0023*/ 504 u_int32_t inbound_intstatus; /*0024 0027*/ 505 u_int32_t inbound_intmask; /*0028 002B*/ 506 u_int32_t outbound_doorbell; /*002C 002F*/ 507 u_int32_t outbound_intstatus; /*0030 0033*/ 508 u_int32_t outbound_intmask; /*0034 0037*/ 509 u_int32_t reserved1[2]; /*0038 003F*/ 510 u_int32_t inbound_queueport; /*0040 0043*/ 511 u_int32_t outbound_queueport; /*0044 0047*/ 512 u_int32_t reserved2[2]; /*0048 004F*/ 513 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 514 u_int32_t reserved4[128]; /*0800 09FF 128*/ 515 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 516 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 517 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 518 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 519 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 520 }; 521 /* 522 ********************************************************************* 523 ** 524 ********************************************************************* 525 */ 526 struct HBB_DOORBELL_1203 527 { 528 u_int8_t doorbell_reserved[ARCMSR_IOP2DRV_DOORBELL_1203]; /*reserved */ 529 u_int32_t iop2drv_doorbell; /*offset 0x00021870:00,01,02,03: window of "instruction flags" from iop to driver */ 530 u_int32_t iop2drv_doorbell_mask; /* 04,05,06,07: doorbell mask */ 531 u_int32_t drv2iop_doorbell; /* 08,09,10,11: window of "instruction flags" from driver to iop */ 532 u_int32_t drv2iop_doorbell_mask; /* 12,13,14,15: doorbell mask */ 533 }; 534 struct HBB_DOORBELL 535 { 536 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ 537 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 538 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 539 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 540 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 541 }; 542 /* 543 ********************************************************************* 544 ** 545 ********************************************************************* 546 */ 547 struct HBB_RWBUFFER 548 { 549 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ 550 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 551 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 552 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 553 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 554 }; 555 /* 556 ********************************************************************* 557 ** 558 ********************************************************************* 559 */ 560 struct HBB_MessageUnit 561 { 562 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 563 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 564 int32_t postq_index; /* post queue index */ 565 int32_t doneq_index; /* done queue index */ 566 struct HBB_DOORBELL *hbb_doorbell; 567 struct HBB_RWBUFFER *hbb_rwbuffer; 568 bus_size_t drv2iop_doorbell; /* window of "instruction flags" from driver to iop */ 569 bus_size_t drv2iop_doorbell_mask; /* doorbell mask */ 570 bus_size_t iop2drv_doorbell; /* window of "instruction flags" from iop to driver */ 571 bus_size_t iop2drv_doorbell_mask; /* doorbell mask */ 572 }; 573 574 /* 575 ********************************************************************* 576 ** 577 ********************************************************************* 578 */ 579 struct HBC_MessageUnit { 580 u_int32_t message_unit_status; /*0000 0003*/ 581 u_int32_t slave_error_attribute; /*0004 0007*/ 582 u_int32_t slave_error_address; /*0008 000B*/ 583 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 584 u_int32_t master_error_attribute; /*0010 0013*/ 585 u_int32_t master_error_address_low; /*0014 0017*/ 586 u_int32_t master_error_address_high; /*0018 001B*/ 587 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 588 u_int32_t inbound_doorbell; /*0020 0023*/ 589 u_int32_t diagnostic_rw_data; /*0024 0027*/ 590 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 591 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 592 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 593 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 594 u_int32_t dcr_data; /*0038 003B*/ 595 u_int32_t dcr_address; /*003C 003F*/ 596 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 597 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 598 u_int32_t hcb_pci_address_low; /*0048 004B*/ 599 u_int32_t hcb_pci_address_high; /*004C 004F*/ 600 u_int32_t iop_int_status; /*0050 0053*/ 601 u_int32_t iop_int_mask; /*0054 0057*/ 602 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 603 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 604 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 605 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 606 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 607 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 608 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 609 u_int32_t i2o_message_unit_control; /*0074 0077*/ 610 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 611 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 612 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 613 u_int32_t message_dest_address_index; /*0090 0093*/ 614 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 615 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 616 u_int32_t outbound_doorbell; /*009C 009F*/ 617 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 618 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 619 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 620 u_int32_t reserved0; /*00AC 00AF*/ 621 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 622 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 623 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 624 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 625 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 626 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 627 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 628 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 629 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 630 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 631 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 632 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 633 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 634 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 635 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 636 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 637 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 638 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 639 u_int32_t host_diagnostic; /*00F8 00FB*/ 640 u_int32_t write_sequence; /*00FC 00FF*/ 641 u_int32_t reserved1[34]; /*0100 0187*/ 642 u_int32_t reserved2[1950]; /*0188 1FFF*/ 643 u_int32_t message_wbuffer[32]; /*2000 207F*/ 644 u_int32_t reserved3[32]; /*2080 20FF*/ 645 u_int32_t message_rbuffer[32]; /*2100 217F*/ 646 u_int32_t reserved4[32]; /*2180 21FF*/ 647 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 648 }; 649 /* 650 ********************************************************************* 651 ** 652 ********************************************************************* 653 */ 654 struct InBound_SRB { 655 uint32_t addressLow; //pointer to SRB block 656 uint32_t addressHigh; 657 uint32_t length; // in DWORDs 658 uint32_t reserved0; 659 }; 660 661 struct OutBound_SRB { 662 uint32_t addressLow; //pointer to SRB block 663 uint32_t addressHigh; 664 }; 665 666 struct HBD_MessageUnit { 667 uint32_t reserved0; 668 uint32_t chip_id; //0x0004 669 uint32_t cpu_mem_config; //0x0008 670 uint32_t reserved1[10]; //0x000C 671 uint32_t i2o_host_interrupt_mask; //0x0034 672 uint32_t reserved2[114]; //0x0038 673 uint32_t host_int_status; //0x0200 674 uint32_t host_int_enable; //0x0204 675 uint32_t reserved3[1]; //0x0208 676 uint32_t pcief0_int_enable; //0x020C 677 uint32_t reserved4[124]; //0x0210 678 uint32_t inbound_msgaddr0; //0x0400 679 uint32_t inbound_msgaddr1; //0x0404 680 uint32_t reserved5[6]; //0x0408 681 uint32_t outbound_msgaddr0; //0x0420 682 uint32_t outbound_msgaddr1; //0x0424 683 uint32_t reserved6[14]; //0x0428 684 uint32_t inbound_doorbell; //0x0460 685 uint32_t reserved7[7]; //0x0464 686 uint32_t outbound_doorbell; //0x0480 687 uint32_t outbound_doorbell_enable; //0x0484 688 uint32_t reserved8[734]; //0x0488 689 uint32_t inboundlist_base_low; //0x1000 690 uint32_t inboundlist_base_high; //0x1004 691 uint32_t reserved9[4]; //0x1008 692 uint32_t inboundlist_write_pointer; //0x1018 693 uint32_t inboundlist_read_pointer; //0x101C 694 uint32_t reserved10[16]; //0x1020 695 uint32_t outboundlist_base_low; //0x1060 696 uint32_t outboundlist_base_high; //0x1064 697 uint32_t reserved11; //0x1068 698 uint32_t outboundlist_copy_pointer; //0x106C 699 uint32_t outboundlist_read_pointer; //0x1070 0x1072 700 uint32_t reserved12[5]; //0x1074 701 uint32_t outboundlist_interrupt_cause; //0x1088 702 uint32_t outboundlist_interrupt_enable; //0x108C 703 uint32_t reserved13[988]; //0x1090 704 uint32_t message_wbuffer[32]; //0x2000 705 uint32_t reserved14[32]; //0x2080 706 uint32_t message_rbuffer[32]; //0x2100 707 uint32_t reserved15[32]; //0x2180 708 uint32_t msgcode_rwbuffer[256]; //0x2200 709 }; 710 711 struct HBD_MessageUnit0 { 712 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE]; 713 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1]; 714 uint16_t postq_index; 715 uint16_t doneq_index; 716 struct HBD_MessageUnit *phbdmu; 717 }; 718 /* 719 ********************************************************************* 720 ** 721 ********************************************************************* 722 */ 723 struct HBE_MessageUnit { 724 u_int32_t iobound_doorbell; /*0000 0003*/ 725 u_int32_t write_sequence_3xxx; /*0004 0007*/ 726 u_int32_t host_diagnostic_3xxx; /*0008 000B*/ 727 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 728 u_int32_t master_error_attribute; /*0010 0013*/ 729 u_int32_t master_error_address_low; /*0014 0017*/ 730 u_int32_t master_error_address_high; /*0018 001B*/ 731 u_int32_t hcb_size; /*001C 001F*/ 732 u_int32_t inbound_doorbell; /*0020 0023*/ 733 u_int32_t diagnostic_rw_data; /*0024 0027*/ 734 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 735 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 736 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 737 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 738 u_int32_t dcr_data; /*0038 003B*/ 739 u_int32_t dcr_address; /*003C 003F*/ 740 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 741 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 742 u_int32_t hcb_pci_address_low; /*0048 004B*/ 743 u_int32_t hcb_pci_address_high; /*004C 004F*/ 744 u_int32_t iop_int_status; /*0050 0053*/ 745 u_int32_t iop_int_mask; /*0054 0057*/ 746 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 747 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 748 u_int32_t inbound_free_list_index; /*0060 0063*/ 749 u_int32_t inbound_post_list_index; /*0064 0067*/ 750 u_int32_t outbound_free_list_index; /*0068 006B*/ 751 u_int32_t outbound_post_list_index; /*006C 006F*/ 752 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 753 u_int32_t i2o_message_unit_control; /*0074 0077*/ 754 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 755 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 756 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 757 u_int32_t message_dest_address_index; /*0090 0093*/ 758 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 759 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 760 u_int32_t outbound_doorbell; /*009C 009F*/ 761 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 762 u_int32_t message_source_address_index; /*00A4 00A7*/ 763 u_int32_t message_done_queue_index; /*00A8 00AB*/ 764 u_int32_t reserved0; /*00AC 00AF*/ 765 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 766 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 767 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 768 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 769 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 770 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 771 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 772 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 773 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 774 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 775 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 776 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 777 u_int32_t message_dest_queue_port_low; /*00E0 00E3*/ 778 u_int32_t message_dest_queue_port_high; /*00E4 00E7*/ 779 u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/ 780 u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/ 781 u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/ 782 u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/ 783 u_int32_t host_diagnostic; /*00F8 00FB*/ 784 u_int32_t write_sequence; /*00FC 00FF*/ 785 u_int32_t reserved1[46]; /*0100 01B7*/ 786 u_int32_t reply_post_producer_index; /*01B8 01BB*/ 787 u_int32_t reply_post_consumer_index; /*01BC 01BF*/ 788 u_int32_t reserved2[1936]; /*01C0 1FFF*/ 789 u_int32_t message_wbuffer[32]; /*2000 207F*/ 790 u_int32_t reserved3[32]; /*2080 20FF*/ 791 u_int32_t message_rbuffer[32]; /*2100 217F*/ 792 u_int32_t reserved4[32]; /*2180 21FF*/ 793 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 794 }; 795 796 typedef struct deliver_completeQ { 797 u_int16_t cmdFlag; 798 u_int16_t cmdSMID; 799 u_int16_t cmdLMID; // reserved (0) 800 u_int16_t cmdFlag2; // reserved (0) 801 } DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q; 802 803 #define COMPLETION_Q_POOL_SIZE (sizeof(struct deliver_completeQ) * 512 + 128) 804 805 /* 806 ********************************************************************* 807 ** 808 ********************************************************************* 809 */ 810 struct MessageUnit_UNION 811 { 812 union { 813 struct HBA_MessageUnit hbamu; 814 struct HBB_MessageUnit hbbmu; 815 struct HBC_MessageUnit hbcmu; 816 struct HBD_MessageUnit0 hbdmu; 817 struct HBE_MessageUnit hbemu; 818 } muu; 819 }; 820 /* 821 ************************************************************* 822 ** structure for holding DMA address data 823 ************************************************************* 824 */ 825 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 826 /* 827 ************************************************************************************************ 828 ** ARECA FIRMWARE SPEC 829 ************************************************************************************************ 830 ** Usage of IOP331 adapter 831 ** (All In/Out is in IOP331's view) 832 ** 1. Message 0 --> InitThread message and retrun code 833 ** 2. Doorbell is used for RS-232 emulation 834 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 835 ** bit1 -- data out has been read (DRIVER DATA READ OK) 836 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 837 ** bit1 -- data in has been read (IOP331 DATA READ OK) 838 ** 3. Index Memory Usage 839 ** offset 0xf00 : for RS232 out (request buffer) 840 ** offset 0xe00 : for RS232 in (scratch buffer) 841 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 842 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver) 843 ** 4. RS-232 emulation 844 ** Currently 128 byte buffer is used 845 ** 1st u_int32_t : Data length (1--124) 846 ** Byte 4--127 : Max 124 bytes of data 847 ** 5. PostQ 848 ** All SCSI Command must be sent through postQ: 849 ** (inbound queue port) Request frame must be 32 bytes aligned 850 ** # bit27--bit31 => flag for post ccb 851 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 852 ** bit31 : 0 : 256 bytes frame 853 ** 1 : 512 bytes frame 854 ** bit30 : 0 : normal request 855 ** 1 : BIOS request 856 ** bit29 : reserved 857 ** bit28 : reserved 858 ** bit27 : reserved 859 ** ------------------------------------------------------------------------------- 860 ** (outbount queue port) Request reply 861 ** # bit27--bit31 => flag for reply 862 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 863 ** bit31 : must be 0 (for this type of reply) 864 ** bit30 : reserved for BIOS handshake 865 ** bit29 : reserved 866 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 867 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData 868 ** bit27 : reserved 869 ** 6. BIOS request 870 ** All BIOS request is the same with request from PostQ 871 ** Except : 872 ** Request frame is sent from configuration space 873 ** offset: 0x78 : Request Frame (bit30 == 1) 874 ** offset: 0x18 : writeonly to generate IRQ to IOP331 875 ** Completion of request: 876 ** (bit30 == 0, bit28==err flag) 877 ** 7. Definition of SGL entry (structure) 878 ** 8. Message1 Out - Diag Status Code (????) 879 ** 9. Message0 message code : 880 ** 0x00 : NOP 881 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver) 882 ** Signature 0x87974060(4) 883 ** Request len 0x00000200(4) 884 ** numbers of queue 0x00000100(4) 885 ** SDRAM Size 0x00000100(4)-->256 MB 886 ** IDE Channels 0x00000008(4) 887 ** vendor 40 bytes char 888 ** model 8 bytes char 889 ** FirmVer 16 bytes char 890 ** Device Map 16 bytes char 891 ** 892 ** FirmwareVersion DWORD <== Added for checking of new firmware capability 893 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 894 ** Signature 0x87974063(4) 895 ** UPPER32 of Request Frame (4)-->Driver Only 896 ** 0x03 : Reset (Abort all queued Command) 897 ** 0x04 : Stop Background Activity 898 ** 0x05 : Flush Cache 899 ** 0x06 : Start Background Activity (re-start if background is halted) 900 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 901 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331) 902 ** byte 0 : 0xaa <-- signature 903 ** byte 1 : 0x55 <-- signature 904 ** byte 2 : year (04) 905 ** byte 3 : month (1..12) 906 ** byte 4 : date (1..31) 907 ** byte 5 : hour (0..23) 908 ** byte 6 : minute (0..59) 909 ** byte 7 : second (0..59) 910 ** ********************************************************************************* 911 ** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter 912 ** ==> Difference from IOP348 913 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code 914 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP) 915 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 916 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 917 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver) 918 ** <A> use doorbell to generate interrupt 919 ** 920 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop) 921 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver) 922 ** 923 ** a. Message1: Out - Diag Status Code (????) 924 ** 925 ** b. Message0: message code 926 ** 0x00 : NOP 927 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver) 928 ** Signature 0x87974060(4) 929 ** Request len 0x00000200(4) 930 ** numbers of queue 0x00000100(4) 931 ** SDRAM Size 0x00000100(4)-->256 MB 932 ** IDE Channels 0x00000008(4) 933 ** vendor 40 bytes char 934 ** model 8 bytes char 935 ** FirmVer 16 bytes char 936 ** Device Map 16 bytes char 937 ** cfgVersion ULONG <== Added for checking of new firmware capability 938 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP) 939 ** Signature 0x87974063(4) 940 ** UPPER32 of Request Frame (4)-->Driver Only 941 ** 0x03 : Reset (Abort all queued Command) 942 ** 0x04 : Stop Background Activity 943 ** 0x05 : Flush Cache 944 ** 0x06 : Start Background Activity (re-start if background is halted) 945 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 946 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP) 947 ** byte 0 : 0xaa <-- signature 948 ** byte 1 : 0x55 <-- signature 949 ** byte 2 : year (04) 950 ** byte 3 : month (1..12) 951 ** byte 4 : date (1..31) 952 ** byte 5 : hour (0..23) 953 ** byte 6 : minute (0..59) 954 ** byte 7 : second (0..59) 955 ** 956 ** <2> Doorbell Register is used for RS-232 emulation 957 ** <A> different clear register 958 ** <B> different bit0 definition (bit0 is reserved) 959 ** 960 ** inbound doorbell : at offset 0x20 961 ** inbound doorbell clear : at offset 0x70 962 ** 963 ** inbound doorbell : bit0 -- reserved 964 ** bit1 -- data in ready (DRIVER DATA WRITE OK) 965 ** bit2 -- data out has been read (DRIVER DATA READ OK) 966 ** bit3 -- inbound message 0 ready 967 ** bit4 -- more than 12 request completed in a time 968 ** 969 ** outbound doorbell : at offset 0x9C 970 ** outbound doorbell clear : at offset 0xA0 971 ** 972 ** outbound doorbell : bit0 -- reserved 973 ** bit1 -- data out ready (IOP DATA WRITE OK) 974 ** bit2 -- data in has been read (IOP DATA READ OK) 975 ** bit3 -- outbound message 0 ready 976 ** 977 ** <3> Index Memory Usage (Buffer Area) 978 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer) 979 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer) 980 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver) 981 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP) 982 ** 983 ** <4> PostQ (Command Post Address) 984 ** All SCSI Command must be sent through postQ: 985 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43 986 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper) 987 ** outbound queue port32 at offset 0x44 988 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper) 989 ** <A> For 32bit queue, access low part is enough to send/receive request 990 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the 991 ** same for outbound queue port 992 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction 993 ** to post inbound request in a single instruction, and use 64bit instruction 994 ** to retrieve outbound request in a single instruction. 995 ** If in 32bit environment, when sending inbound queue, write high part first 996 ** then write low part. For receiving outbound request, read high part first 997 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF. 998 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the 999 ** consistency of the FIFO. Another way to check empty is to check status flag 1000 ** at 0x30 bit3. 1001 ** <C> Post Address IS NOT shifted (must be 16 bytes aligned) 1002 ** For BIOS, 16bytes aligned is OK 1003 ** For Driver, 32bytes alignment is recommended. 1004 ** POST Command bit0 to bit3 is defined differently 1005 ** ---------------------------- 1006 ** bit0:1 for PULL mode (must be 1) 1007 ** ---------------------------- 1008 ** bit3/2/1: for arcmsr cdb size (arccdbsize) 1009 ** 000: <= 0x0080 (128) 1010 ** 001: <= 0x0100 (256) 1011 ** 010: <= 0x0180 (384) 1012 ** 011: <= 0x0200 (512) 1013 ** 100: <= 0x0280 (640) 1014 ** 101: <= 0x0300 (768) 1015 ** 110: <= 0x0300 (reserved) 1016 ** 111: <= 0x0300 (reserved) 1017 ** ----------------------------- 1018 ** if len > 0x300 the len always set as 0x300 1019 ** ----------------------------- 1020 ** post addr = addr | ((len-1) >> 6) | 1 1021 ** ----------------------------- 1022 ** page length in command buffer still required, 1023 ** 1024 ** if page length > 3, 1025 ** firmware will assume more request data need to be retrieved 1026 ** 1027 ** <D> Outbound Posting 1028 ** bit0:0 , no error, 1 with error, refer to status buffer 1029 ** bit1:0 , reserved (will be 0) 1030 ** bit2:0 , reserved (will be 0) 1031 ** bit3:0 , reserved (will be 0) 1032 ** bit63-4: Completed command address 1033 ** 1034 ** <E> BIOS support, no special support is required. 1035 ** LSI2108 support I/O register 1036 ** All driver functionality is supported through I/O address 1037 ** 1038 ************************************************************************************************ 1039 */ 1040 /* 1041 ********************************** 1042 ** 1043 ********************************** 1044 */ 1045 /* size 8 bytes */ 1046 /* 32bit Scatter-Gather list */ 1047 struct SG32ENTRY { /* length bit 24 == 0 */ 1048 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 1049 u_int32_t address; 1050 }; 1051 /* size 12 bytes */ 1052 /* 64bit Scatter-Gather list */ 1053 struct SG64ENTRY { /* length bit 24 == 1 */ 1054 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 1055 u_int32_t address; 1056 u_int32_t addresshigh; 1057 }; 1058 struct SGENTRY_UNION { 1059 union { 1060 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 1061 struct SG64ENTRY sg64entry; /* 30h */ 1062 }u; 1063 }; 1064 /* 1065 ********************************** 1066 ** 1067 ********************************** 1068 */ 1069 struct QBUFFER { 1070 u_int32_t data_len; 1071 u_int8_t data[124]; 1072 }; 1073 /* 1074 ********************************** 1075 */ 1076 typedef struct PHYS_ADDR64 { 1077 u_int32_t phyadd_low; 1078 u_int32_t phyadd_high; 1079 }PHYSADDR64; 1080 /* 1081 ************************************************************************************************ 1082 ** FIRMWARE INFO 1083 ************************************************************************************************ 1084 */ 1085 #define ARCMSR_FW_MODEL_OFFSET 15 1086 #define ARCMSR_FW_VERS_OFFSET 17 1087 #define ARCMSR_FW_DEVMAP_OFFSET 21 1088 #define ARCMSR_FW_CFGVER_OFFSET 25 1089 1090 struct FIRMWARE_INFO { 1091 u_int32_t signature; /*0,00-03*/ 1092 u_int32_t request_len; /*1,04-07*/ 1093 u_int32_t numbers_queue; /*2,08-11*/ 1094 u_int32_t sdram_size; /*3,12-15*/ 1095 u_int32_t ide_channels; /*4,16-19*/ 1096 char vendor[40]; /*5,20-59*/ 1097 char model[8]; /*15,60-67*/ 1098 char firmware_ver[16]; /*17,68-83*/ 1099 char device_map[16]; /*21,84-99*/ 1100 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 1101 char cfgSerial[16]; /*26,104-119*/ 1102 u_int32_t cfgPicStatus; /*30,120-123*/ 1103 }; 1104 /* (A) For cfgVersion in FIRMWARE_INFO 1105 ** if low BYTE (byte#0) >= 3 (version 3) 1106 ** then byte#1 report the capability of the firmware can xfer in a single request 1107 ** 1108 ** byte#1 1109 ** 0 256K 1110 ** 1 512K 1111 ** 2 1M 1112 ** 3 2M 1113 ** 4 4M 1114 ** 5 8M 1115 ** 6 16M 1116 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages 1117 ** Driver support new xfer method need to set this field to indicate 1118 ** large CDB block in 0x100 unit (we use 0x100 byte as one page) 1119 ** e.g. If the length of CDB including MSG header and SGL is 0x1508 1120 ** driver need to set the msgPages to 0x16 1121 ** (C) REQ_LEN_512BYTE must be used also to indicate SRB length 1122 ** e.g. CDB len msgPages REQ_LEN_512BYTE flag 1123 ** <= 0x100 1 0 1124 ** <= 0x200 2 1 1125 ** <= 0x300 3 1 1126 ** <= 0x400 4 1 1127 ** . 1128 ** . 1129 */ 1130 1131 /* 1132 ************************************************************************************************ 1133 ** size 0x1F8 (504) 1134 ************************************************************************************************ 1135 */ 1136 struct ARCMSR_CDB { 1137 u_int8_t Bus; /* 00h should be 0 */ 1138 u_int8_t TargetID; /* 01h should be 0--15 */ 1139 u_int8_t LUN; /* 02h should be 0--7 */ 1140 u_int8_t Function; /* 03h should be 1 */ 1141 1142 u_int8_t CdbLength; /* 04h not used now */ 1143 u_int8_t sgcount; /* 05h */ 1144 u_int8_t Flags; /* 06h */ 1145 u_int8_t msgPages; /* 07h */ 1146 1147 u_int32_t Context; /* 08h Address of this request */ 1148 u_int32_t DataLength; /* 0ch not used now */ 1149 1150 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 1151 /* 1152 ******************************************************** 1153 ** Device Status : the same from SCSI bus if error occur 1154 ** SCSI bus status codes. 1155 ******************************************************** 1156 */ 1157 u_int8_t DeviceStatus; /* 20h if error */ 1158 1159 u_int8_t SenseData[15]; /* 21h output */ 1160 1161 union { 1162 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 1163 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 1164 } u; 1165 }; 1166 /* CDB flag */ 1167 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 1168 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 1169 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 1170 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 1171 #define ARCMSR_CDB_FLAG_HEADQ 0x08 1172 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 1173 /* scsi status */ 1174 #define SCSISTAT_GOOD 0x00 1175 #define SCSISTAT_CHECK_CONDITION 0x02 1176 #define SCSISTAT_CONDITION_MET 0x04 1177 #define SCSISTAT_BUSY 0x08 1178 #define SCSISTAT_INTERMEDIATE 0x10 1179 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 1180 #define SCSISTAT_RESERVATION_CONFLICT 0x18 1181 #define SCSISTAT_COMMAND_TERMINATED 0x22 1182 #define SCSISTAT_QUEUE_FULL 0x28 1183 /* DeviceStatus */ 1184 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 1185 #define ARCMSR_DEV_ABORTED 0xF1 1186 #define ARCMSR_DEV_INIT_FAIL 0xF2 1187 /* 1188 ********************************************************************* 1189 ** Command Control Block (SrbExtension) 1190 ** SRB must be not cross page boundary,and the order from offset 0 1191 ** structure describing an ATA disk request 1192 ** this SRB length must be 32 bytes boundary 1193 ********************************************************************* 1194 */ 1195 struct CommandControlBlock { 1196 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 1197 u_int32_t cdb_phyaddr_low; /* 504-507 */ 1198 u_int32_t arc_cdb_size; /* 508-511 */ 1199 /* ======================512+32 bytes============================ */ 1200 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 1201 struct AdapterControlBlock *acb; /* 520-523 524-527 */ 1202 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 1203 u_int16_t srb_flags; /* 536-537 */ 1204 u_int16_t srb_state; /* 538-539 */ 1205 u_int32_t cdb_phyaddr_high; /* 540-543 */ 1206 struct callout ccb_callout; 1207 u_int32_t smid; 1208 /* ========================================================== */ 1209 }; 1210 /* srb_flags */ 1211 #define SRB_FLAG_READ 0x0000 1212 #define SRB_FLAG_WRITE 0x0001 1213 #define SRB_FLAG_ERROR 0x0002 1214 #define SRB_FLAG_FLUSHCACHE 0x0004 1215 #define SRB_FLAG_MASTER_ABORTED 0x0008 1216 #define SRB_FLAG_DMAVALID 0x0010 1217 #define SRB_FLAG_DMACONSISTENT 0x0020 1218 #define SRB_FLAG_DMAWRITE 0x0040 1219 #define SRB_FLAG_PKTBIND 0x0080 1220 #define SRB_FLAG_TIMER_START 0x0080 1221 /* srb_state */ 1222 #define ARCMSR_SRB_DONE 0x0000 1223 #define ARCMSR_SRB_UNBUILD 0x0000 1224 #define ARCMSR_SRB_TIMEOUT 0x1111 1225 #define ARCMSR_SRB_RETRY 0x2222 1226 #define ARCMSR_SRB_START 0x55AA 1227 #define ARCMSR_SRB_PENDING 0xAA55 1228 #define ARCMSR_SRB_RESET 0xA5A5 1229 #define ARCMSR_SRB_ABORTED 0x5A5A 1230 #define ARCMSR_SRB_ILLEGAL 0xFFFF 1231 1232 #define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0) 1233 #define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM) 1234 1235 /* 1236 ********************************************************************* 1237 ** Adapter Control Block 1238 ********************************************************************* 1239 */ 1240 #define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */ 1241 #define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */ 1242 #define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */ 1243 #define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */ 1244 #define ACB_ADAPTER_TYPE_E 0x00000004 /* hbd L IOP */ 1245 1246 struct AdapterControlBlock { 1247 u_int32_t adapter_type; /* adapter A,B..... */ 1248 1249 bus_space_tag_t btag[2]; 1250 bus_space_handle_t bhandle[2]; 1251 bus_dma_tag_t parent_dmat; 1252 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 1253 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 1254 bus_dmamap_t srb_dmamap; 1255 device_t pci_dev; 1256 #if __FreeBSD_version < 503000 1257 dev_t ioctl_dev; 1258 #else 1259 struct cdev *ioctl_dev; 1260 #endif 1261 int pci_unit; 1262 1263 struct resource *sys_res_arcmsr[2]; 1264 struct resource *irqres[ARCMSR_NUM_MSIX_VECTORS]; 1265 void *ih[ARCMSR_NUM_MSIX_VECTORS]; /* interrupt handle */ 1266 int irq_id[ARCMSR_NUM_MSIX_VECTORS]; 1267 1268 /* Hooks into the CAM XPT */ 1269 struct cam_sim *psim; 1270 struct cam_path *ppath; 1271 u_int8_t *uncacheptr; 1272 unsigned long vir2phy_offset; 1273 union { 1274 unsigned long phyaddr; 1275 struct { 1276 u_int32_t phyadd_low; 1277 u_int32_t phyadd_high; 1278 }B; 1279 }srb_phyaddr; 1280 // unsigned long srb_phyaddr; 1281 /* Offset is used in making arc cdb physical to virtual calculations */ 1282 u_int32_t outbound_int_enable; 1283 1284 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */ 1285 1286 u_int8_t adapter_index; 1287 u_int8_t irq; 1288 u_int16_t acb_flags; 1289 1290 struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 1291 struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 1292 int32_t workingsrb_doneindex; /* done srb array index */ 1293 int32_t workingsrb_startindex; /* start srb array index */ 1294 int32_t srboutstandingcount; 1295 1296 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 1297 u_int32_t rqbuf_firstindex; /* first of read buffer */ 1298 u_int32_t rqbuf_lastindex; /* last of read buffer */ 1299 1300 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 1301 u_int32_t wqbuf_firstindex; /* first of write buffer */ 1302 u_int32_t wqbuf_lastindex; /* last of write buffer */ 1303 1304 arcmsr_lock_t isr_lock; 1305 arcmsr_lock_t srb_lock; 1306 arcmsr_lock_t postDone_lock; 1307 arcmsr_lock_t qbuffer_lock; 1308 1309 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 1310 u_int32_t num_resets; 1311 u_int32_t num_aborts; 1312 u_int32_t firm_request_len; /*1,04-07*/ 1313 u_int32_t firm_numbers_queue; /*2,08-11*/ 1314 u_int32_t firm_sdram_size; /*3,12-15*/ 1315 u_int32_t firm_ide_channels; /*4,16-19*/ 1316 u_int32_t firm_cfg_version; 1317 char firm_model[12]; /*15,60-67*/ 1318 char firm_version[20]; /*17,68-83*/ 1319 char device_map[20]; /*21,84-99 */ 1320 struct callout devmap_callout; 1321 u_int32_t pktRequestCount; 1322 u_int32_t pktReturnCount; 1323 u_int32_t vendor_device_id; 1324 u_int32_t adapter_bus_speed; 1325 u_int32_t maxOutstanding; 1326 u_int16_t sub_device_id; 1327 u_int32_t doneq_index; 1328 u_int32_t in_doorbell; 1329 u_int32_t out_doorbell; 1330 u_int32_t completionQ_entry; 1331 pCompletion_Q pCompletionQ; 1332 int msix_vectors; 1333 int rid[2]; 1334 };/* HW_DEVICE_EXTENSION */ 1335 /* acb_flags */ 1336 #define ACB_F_SCSISTOPADAPTER 0x0001 1337 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 1338 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 1339 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 1340 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 1341 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 1342 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 1343 #define ACB_F_BUS_RESET 0x0080 1344 #define ACB_F_IOP_INITED 0x0100 /* iop init */ 1345 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 1346 #define ACB_F_CAM_DEV_QFRZN 0x0400 1347 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 1348 #define ACB_F_SRB_FUNCTION_POWER 0x1000 1349 #define ACB_F_MSIX_ENABLED 0x2000 1350 /* devstate */ 1351 #define ARECA_RAID_GONE 0x55 1352 #define ARECA_RAID_GOOD 0xaa 1353 /* adapter_bus_speed */ 1354 #define ACB_BUS_SPEED_3G 0 1355 #define ACB_BUS_SPEED_6G 1 1356 #define ACB_BUS_SPEED_12G 2 1357 /* 1358 ************************************************************* 1359 ************************************************************* 1360 */ 1361 struct SENSE_DATA { 1362 u_int8_t ErrorCode:7; 1363 u_int8_t Valid:1; 1364 u_int8_t SegmentNumber; 1365 u_int8_t SenseKey:4; 1366 u_int8_t Reserved:1; 1367 u_int8_t IncorrectLength:1; 1368 u_int8_t EndOfMedia:1; 1369 u_int8_t FileMark:1; 1370 u_int8_t Information[4]; 1371 u_int8_t AdditionalSenseLength; 1372 u_int8_t CommandSpecificInformation[4]; 1373 u_int8_t AdditionalSenseCode; 1374 u_int8_t AdditionalSenseCodeQualifier; 1375 u_int8_t FieldReplaceableUnitCode; 1376 u_int8_t SenseKeySpecific[3]; 1377 }; 1378 /* 1379 ********************************** 1380 ** Peripheral Device Type definitions 1381 ********************************** 1382 */ 1383 #define SCSI_DASD 0x00 /* Direct-access Device */ 1384 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 1385 #define SCSI_PRINTER 0x02 /* Printer device */ 1386 #define SCSI_PROCESSOR 0x03 /* Processor device */ 1387 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 1388 #define SCSI_CDROM 0x05 /* CD-ROM device */ 1389 #define SCSI_SCANNER 0x06 /* Scanner device */ 1390 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 1391 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 1392 #define SCSI_COMM 0x09 /* Communications device */ 1393 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 1394 /* 1395 ************************************************************************************************************ 1396 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1397 ** 80331 PCI-to-PCI Bridge 1398 ** PCI Configuration Space 1399 ** 1400 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1401 ** Programming Interface 1402 ** ======================== 1403 ** Configuration Register Address Space Groupings and Ranges 1404 ** ============================================================= 1405 ** Register Group Configuration Offset 1406 ** ------------------------------------------------------------- 1407 ** Standard PCI Configuration 00-3Fh 1408 ** ------------------------------------------------------------- 1409 ** Device Specific Registers 40-A7h 1410 ** ------------------------------------------------------------- 1411 ** Reserved A8-CBh 1412 ** ------------------------------------------------------------- 1413 ** Enhanced Capability List CC-FFh 1414 ** ========================================================================================================== 1415 ** Standard PCI [Type 1] Configuration Space Address Map 1416 ** ********************************************************************************************************** 1417 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1418 ** ---------------------------------------------------------------------------------------------------------- 1419 ** | Device ID | Vendor ID | 00h 1420 ** ---------------------------------------------------------------------------------------------------------- 1421 ** | Primary Status | Primary Command | 04h 1422 ** ---------------------------------------------------------------------------------------------------------- 1423 ** | Class Code | RevID | 08h 1424 ** ---------------------------------------------------------------------------------------------------------- 1425 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 1426 ** ---------------------------------------------------------------------------------------------------------- 1427 ** | Reserved | 10h 1428 ** ---------------------------------------------------------------------------------------------------------- 1429 ** | Reserved | 14h 1430 ** ---------------------------------------------------------------------------------------------------------- 1431 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 1432 ** ---------------------------------------------------------------------------------------------------------- 1433 ** | Secondary Status | I/O Limit | I/O Base | 1Ch 1434 ** ---------------------------------------------------------------------------------------------------------- 1435 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 1436 ** ---------------------------------------------------------------------------------------------------------- 1437 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 1438 ** ---------------------------------------------------------------------------------------------------------- 1439 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h 1440 ** ---------------------------------------------------------------------------------------------------------- 1441 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 1442 ** ---------------------------------------------------------------------------------------------------------- 1443 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 1444 ** ---------------------------------------------------------------------------------------------------------- 1445 ** | Reserved | Capabilities Pointer | 34h 1446 ** ---------------------------------------------------------------------------------------------------------- 1447 ** | Reserved | 38h 1448 ** ---------------------------------------------------------------------------------------------------------- 1449 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 1450 **============================================================================================================= 1451 */ 1452 /* 1453 **============================================================================================================= 1454 ** 0x03-0x00 : 1455 ** Bit Default Description 1456 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 1457 ** ID is unique per product speed as indicated. 1458 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 1459 **============================================================================================================= 1460 */ 1461 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 1462 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 1463 /* 1464 **============================================================================== 1465 ** 0x05-0x04 : command register 1466 ** Bit Default Description 1467 **15:11 00h Reserved 1468 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 1469 ** The bridge does not support interrupts. 1470 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 1471 ** transactions on the primary bus. 1472 ** The bridge does not generate fast back to back 1473 ** transactions on the primary bus. 1474 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 1475 ** 0=The bridge does not assert P_SERR#. 1476 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 1477 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 1478 ** that bridge does not perform address or data stepping, 1479 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 1480 ** 0=When a data parity error is detected bridge does not assert S_PERR#. 1481 ** Also bridge does not assert P_SERR# in response to 1482 ** a detected address or attribute parity error. 1483 ** 1=When a data parity error is detected bridge asserts S_PERR#. 1484 ** The bridge also asserts P_SERR# 1485 ** (when enabled globally via bit(8) of this register) 1486 ** in response to a detected address or attribute parity error. 1487 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 1488 ** VGA palette write transactions are I/O transactions 1489 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 1490 ** P_AD[15:10] are not decoded (i.e. aliases are claimed), 1491 ** or are fully decoding 1492 ** (i.e., must be all 0's depending upon the VGA 1493 ** aliasing bit in the Bridge Control Register, offset 3Eh. 1494 ** P_AD[31:16] equal to 0000h 1495 ** 0=The bridge ignores VGA palette write transactions, 1496 ** unless decoded by the standard I/O address range window. 1497 ** 1=The bridge responds to VGA palette write transactions 1498 ** with medium DEVSEL# timing and forwards them to the secondary bus. 1499 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 1500 ** MWI transactions targeting resources on the opposite side of the bridge, 1501 ** however, are forwarded as MWI transactions. 1502 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 1503 ** This bit is read only and always returns 0 when read 1504 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 1505 ** Initiation of configuration transactions is not affected by the state of this bit. 1506 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 1507 ** 1=The bridge is enabled to function as an initiator on the primary interface. 1508 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 1509 ** 0=The bridge target response to memory transactions on the primary interface is disabled. 1510 ** 1=The bridge target response to memory transactions on the primary interface is enabled. 1511 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 1512 ** 0=The bridge target response to I/O transactions on the primary interface is disabled. 1513 ** 1=The bridge target response to I/O transactions on the primary interface is enabled. 1514 **============================================================================== 1515 */ 1516 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 1517 #define PCI_DISABLE_INTERRUPT 0x0400 1518 /* 1519 **============================================================================== 1520 ** 0x07-0x06 : status register 1521 ** Bit Default Description 1522 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1523 ** attribute or data parity error. 1524 ** This bit is set regardless of the state of the PER bit in the command register. 1525 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 1526 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 1527 ** acting as the initiator on the primary bus, 1528 ** its transaction (with the exception of special cycles) 1529 ** has been terminated with a Master Abort. 1530 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 1531 ** acting as the initiator on the primary bus, 1532 ** its transaction has been terminated with a Target Abort. 1533 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 1534 ** as the target of a transaction, terminates it with a Target Abort. 1535 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1536 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 1537 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1538 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1539 ** The bridge is the current master on the primary bus 1540 ** S_PERR# is detected asserted or is asserted by bridge 1541 ** The Parity Error Response bit is set in the Command register 1542 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 1543 ** is able to respond to fast back to back transactions on its primary interface. 1544 ** 06 0 Reserved 1545 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 1546 ** 1 = 1547 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 1548 ** Offset 34h (Capability Pointer register) 1549 ** provides the offset for the first entry 1550 ** in the linked list of enhanced capabilities. 1551 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 1552 ** The bridge does not support interrupts. 1553 ** 02:00 000 Reserved 1554 **============================================================================== 1555 */ 1556 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 1557 #define ARCMSR_ADAP_66MHZ 0x20 1558 /* 1559 **============================================================================== 1560 ** 0x08 : revision ID 1561 ** Bit Default Description 1562 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 1563 **============================================================================== 1564 */ 1565 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 1566 /* 1567 **============================================================================== 1568 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 1569 ** Bit Default Description 1570 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 1571 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 1572 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 1573 **============================================================================== 1574 */ 1575 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 1576 /* 1577 **============================================================================== 1578 ** 0x0c : cache line size 1579 ** Bit Default Description 1580 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 1581 ** The contents of this register are factored into 1582 ** internal policy decisions associated with memory read prefetching, 1583 ** and the promotion of Memory Write transactions to MWI transactions. 1584 ** Valid cache line sizes are 8 and 16 dwords. 1585 ** When the cache line size is set to an invalid value, 1586 ** bridge behaves as though the cache line size was set to 00h. 1587 **============================================================================== 1588 */ 1589 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 1590 /* 1591 **============================================================================== 1592 ** 0x0d : latency timer (number of pci clock 00-ff ) 1593 ** Bit Default Description 1594 ** Primary Latency Timer (PTV): 1595 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 1596 ** referenced from the assertion of FRAME# to the expiration of the timer, 1597 ** when bridge may continue as master of the current transaction. All bits are writable, 1598 ** resulting in a granularity of 1 PCI clock cycle. 1599 ** When the timer expires (i.e., equals 00h) 1600 ** bridge relinquishes the bus after the first data transfer 1601 ** when its PCI bus grant has been deasserted. 1602 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 1603 ** Indicates the number of PCI clock cycles, 1604 ** referenced from the assertion of FRAME# to the expiration of the timer, 1605 ** when bridge may continue as master of the current transaction. 1606 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 1607 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1608 ** (Except in the case where MLT expires within 3 data phases 1609 ** of an ADB.In this case bridge continues on 1610 ** until it reaches the next ADB before relinquishing the bus.) 1611 **============================================================================== 1612 */ 1613 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 1614 /* 1615 **============================================================================== 1616 ** 0x0e : (header type,single function ) 1617 ** Bit Default Description 1618 ** 07 0 Multi-function device (MVD): 80331 is a single-function device. 1619 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 1620 ** Returns ��01h�� when read indicating 1621 ** that the register layout conforms to the standard PCI-to-PCI bridge layout. 1622 **============================================================================== 1623 */ 1624 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 1625 /* 1626 **============================================================================== 1627 ** 0x0f : 1628 **============================================================================== 1629 */ 1630 /* 1631 **============================================================================== 1632 ** 0x13-0x10 : 1633 ** PCI CFG Base Address #0 (0x10) 1634 **============================================================================== 1635 */ 1636 /* 1637 **============================================================================== 1638 ** 0x17-0x14 : 1639 ** PCI CFG Base Address #1 (0x14) 1640 **============================================================================== 1641 */ 1642 /* 1643 **============================================================================== 1644 ** 0x1b-0x18 : 1645 ** PCI CFG Base Address #2 (0x18) 1646 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR 1647 ** Bit Default Description 1648 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 1649 ** Any Type 1 configuration cycle 1650 ** on the primary bus whose bus number is greater than the secondary bus number, 1651 ** and less than or equal to the subordinate bus number 1652 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 1653 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 1654 ** Any Type 1 configuration cycle matching this bus number 1655 ** is translated to a Type 0 configuration cycle (or a Special Cycle) 1656 ** before being executed on bridge's secondary PCI bus. 1657 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 1658 ** Any Type 1 configuration cycle on the primary interface 1659 ** with a bus number that is less than the contents 1660 ** of this register field does not be claimed by bridge. 1661 **-----------------0x1B--Secondary Latency Timer Register - SLTR 1662 ** Bit Default Description 1663 ** Secondary Latency Timer (STV): 1664 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 1665 ** Indicates the number of PCI clock cycles, 1666 ** referenced from the assertion of FRAME# to the expiration of the timer, 1667 ** when bridge may continue as master of the current transaction. All bits are writable, 1668 ** resulting in a granularity of 1 PCI clock cycle. 1669 ** When the timer expires (i.e., equals 00h) 1670 ** bridge relinquishes the bus after the first data transfer 1671 ** when its PCI bus grant has been deasserted. 1672 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 1673 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 1674 ** to the expiration of the timer, 1675 ** when bridge may continue as master of the current transaction. All bits are writable, 1676 ** resulting in a granularity of 1 PCI clock cycle. 1677 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1678 ** (Except in the case where MLT expires within 3 data phases of an ADB. 1679 ** In this case bridge continues on until it reaches the next ADB 1680 ** before relinquishing the bus) 1681 **============================================================================== 1682 */ 1683 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 1684 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 1685 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 1686 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 1687 /* 1688 **============================================================================== 1689 ** 0x1f-0x1c : 1690 ** PCI CFG Base Address #3 (0x1C) 1691 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 1692 ** Bit Default Description 1693 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 1694 ** determine when to forward I/O transactions from one interface to the other. 1695 ** These bits correspond to address lines 15:12 for 4KB alignment. 1696 ** Bits 11:0 are assumed to be FFFh. 1697 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 1698 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 1699 ** an address range to determine when to forward I/O transactions 1700 ** from one interface to the other. 1701 ** These bits correspond to address lines 15:12 for 4KB alignment. 1702 ** Bits 11:0 are assumed to be 000h. 1703 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 1704 **-----------------0x1F,0x1E--Secondary Status Register - SSR 1705 ** Bit Default Description 1706 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1707 ** attribute or data parity error on its secondary interface. 1708 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 1709 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 1710 ** acting as the initiator on the secondary bus, 1711 ** it's transaction (with the exception of special cycles) 1712 ** has been terminated with a Master Abort. 1713 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 1714 ** acting as the initiator on the secondary bus, 1715 ** it's transaction has been terminated with a Target Abort. 1716 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 1717 ** as the target of a transaction, terminates it with a Target Abort. 1718 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1719 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 1720 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1721 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1722 ** The bridge is the current master on the secondary bus 1723 ** S_PERR# is detected asserted or is asserted by bridge 1724 ** The Parity Error Response bit is set in the Command register 1725 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 1726 ** 06 0b Reserved 1727 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 1728 ** 1 = 1729 ** 04:00 00h Reserved 1730 **============================================================================== 1731 */ 1732 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 1733 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 1734 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 1735 /* 1736 **============================================================================== 1737 ** 0x23-0x20 : 1738 ** PCI CFG Base Address #4 (0x20) 1739 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 1740 ** Bit Default Description 1741 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1742 ** the upper 1MB aligned value (exclusive) of the range. 1743 ** The incoming address must be less than or equal to this value. 1744 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1745 ** are assumed to be F FFFFh. 1746 ** 19:16 0h Reserved. 1747 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 1748 ** of the incoming address to determine the lower 1MB 1749 ** aligned value (inclusive) of the range. 1750 ** The incoming address must be greater than or equal to this value. 1751 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1752 ** are assumed to be 0 0000h. 1753 ** 03:00 0h Reserved. 1754 **============================================================================== 1755 */ 1756 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 1757 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 1758 /* 1759 **============================================================================== 1760 ** 0x27-0x24 : 1761 ** PCI CFG Base Address #5 (0x24) 1762 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 1763 ** Bit Default Description 1764 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1765 ** the upper 1MB aligned value (exclusive) of the range. 1766 ** The incoming address must be less than or equal to this value. 1767 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1768 ** are assumed to be F FFFFh. 1769 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1770 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 1771 ** of the incoming address to determine the lower 1MB aligned value (inclusive) 1772 ** of the range. 1773 ** The incoming address must be greater than or equal to this value. 1774 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1775 ** are assumed to be 0 0000h. 1776 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1777 **============================================================================== 1778 */ 1779 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 1780 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 1781 /* 1782 **============================================================================== 1783 ** 0x2b-0x28 : 1784 ** Bit Default Description 1785 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 1786 ** bridge supports full 64-bit addressing. 1787 **============================================================================== 1788 */ 1789 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 1790 /* 1791 **============================================================================== 1792 ** 0x2f-0x2c : 1793 ** Bit Default Description 1794 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 1795 ** bridge supports full 64-bit addressing. 1796 **============================================================================== 1797 */ 1798 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 1799 /* 1800 **============================================================================== 1801 ** 0x33-0x30 : 1802 ** Bit Default Description 1803 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 1804 ** space. (Power Management Capability Registers) 1805 **============================================================================== 1806 */ 1807 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 1808 /* 1809 **============================================================================== 1810 ** 0x3b-0x35 : reserved 1811 **============================================================================== 1812 */ 1813 /* 1814 **============================================================================== 1815 ** 0x3d-0x3c : 1816 ** 1817 ** Bit Default Description 1818 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1819 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1820 **============================================================================== 1821 */ 1822 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1823 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1824 /* 1825 **============================================================================== 1826 ** 0x3f-0x3e : 1827 ** Bit Default Description 1828 ** 15:12 0h Reserved 1829 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1830 ** to a timer discard on either the primary or secondary interface. 1831 ** 0b=SERR# is not asserted. 1832 ** 1b=SERR# is asserted. 1833 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1834 ** The delayed completion is then discarded. 1835 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1836 ** that bridge waits for an initiator on the secondary bus 1837 ** to repeat a delayed transaction request. 1838 ** The counter starts when the delayed transaction completion is ready 1839 ** to be returned to the initiator. 1840 ** When the initiator has not repeated the transaction 1841 ** at least once before the counter expires,bridge 1842 ** discards the delayed transaction from its queues. 1843 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1844 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1845 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1846 ** that bridge waits for an initiator on the primary bus 1847 ** to repeat a delayed transaction request. 1848 ** The counter starts when the delayed transaction completion 1849 ** is ready to be returned to the initiator. 1850 ** When the initiator has not repeated the transaction 1851 ** at least once before the counter expires, 1852 ** bridge discards the delayed transaction from its queues. 1853 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1854 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1855 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1856 ** 06 0b Secondary Bus Reset (SBR): 1857 ** When cleared to 0b: The bridge deasserts S_RST#, 1858 ** when it had been asserted by writing this bit to a 1b. 1859 ** When set to 1b: The bridge asserts S_RST#. 1860 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1861 ** when a master abort termination occurs in response to 1862 ** a delayed transaction initiated by bridge on the target bus. 1863 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1864 ** and returns FFFF FFFFh when a read. 1865 ** 1b=When the transaction had not yet been completed on the initiator bus 1866 ** (e.g.,delayed reads, or non-posted writes), 1867 ** then bridge returns a Target Abort in response to the original requester 1868 ** when it returns looking for its delayed completion on the initiator bus. 1869 ** When the transaction had completed on the initiator bus (e.g., a PMW), 1870 ** then bridge asserts P_SERR# (when enabled). 1871 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1872 ** while attempting to deliver a posted memory write on the destination bus. 1873 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1874 ** (also of this register), 1875 ** and the VGA Palette Snoop Enable bit (Command Register). 1876 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 1877 ** the VGA Aliasing bit for the corresponding enabled functionality,: 1878 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1879 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1880 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 1881 ** then this bit has no impact on bridge behavior. 1882 ** 03 0b VGA Enable: Setting this bit enables address decoding 1883 ** and transaction forwarding of the following VGA transactions from the primary bus 1884 ** to the secondary bus: 1885 ** frame buffer memory addresses 000A0000h:000BFFFFh, 1886 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares), 1887 ** or must be ��000000b�� 1888 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1889 ** I/O and Memory Enable bits must be set in the Command register 1890 ** to enable forwarding of VGA cycles. 1891 ** 02 0b ISA Enable: Setting this bit enables special handling 1892 ** for the forwarding of ISA I/O transactions that fall within the address range 1893 ** specified by the I/O Base and Limit registers, 1894 ** and are within the lowest 64Kbyte of the I/O address map 1895 ** (i.e., 0000 0000h - 0000 FFFFh). 1896 ** 0b=All I/O transactions that fall within the I/O Base 1897 ** and Limit registers' specified range are forwarded 1898 ** from primary to secondary unfiltered. 1899 ** 1b=Blocks the forwarding from primary to secondary 1900 ** of the top 768 bytes of each 1Kbyte alias. 1901 ** On the secondary the top 768 bytes of each 1K alias 1902 ** are inversely decoded and forwarded 1903 ** from secondary to primary. 1904 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1905 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 1906 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1907 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error 1908 ** that is detected on its secondary interface. 1909 ** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1910 ** Also bridge does not assert P_SERR# in response to a detected address 1911 ** or attribute parity error. 1912 ** 1b=When a data parity error is detected bridge asserts S_PERR#. 1913 ** The bridge also asserts P_SERR# (when enabled globally via bit(8) 1914 ** of the Command register) 1915 ** in response to a detected address or attribute parity error. 1916 **============================================================================== 1917 */ 1918 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 1919 /* 1920 ************************************************************************** 1921 ** Device Specific Registers 40-A7h 1922 ************************************************************************** 1923 ** ---------------------------------------------------------------------------------------------------------- 1924 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1925 ** ---------------------------------------------------------------------------------------------------------- 1926 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 1927 ** ---------------------------------------------------------------------------------------------------------- 1928 ** | Bridge Control 2 | Bridge Control 1 | 44h 1929 ** ---------------------------------------------------------------------------------------------------------- 1930 ** | Reserved | Bridge Status | 48h 1931 ** ---------------------------------------------------------------------------------------------------------- 1932 ** | Reserved | 4Ch 1933 ** ---------------------------------------------------------------------------------------------------------- 1934 ** | Prefetch Policy | Multi-Transaction Timer | 50h 1935 ** ---------------------------------------------------------------------------------------------------------- 1936 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 1937 ** ---------------------------------------------------------------------------------------------------------- 1938 ** | Reserved | Reserved | Secondary Decode Enable | 58h 1939 ** ---------------------------------------------------------------------------------------------------------- 1940 ** | Reserved | Secondary IDSEL | 5Ch 1941 ** ---------------------------------------------------------------------------------------------------------- 1942 ** | Reserved | 5Ch 1943 ** ---------------------------------------------------------------------------------------------------------- 1944 ** | Reserved | 68h:CBh 1945 ** ---------------------------------------------------------------------------------------------------------- 1946 ************************************************************************** 1947 **============================================================================== 1948 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 1949 ** Bit Default Description 1950 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 1951 ** (PCI=16 clocks,PCI-X=6 clocks). 1952 ** Note that this field is only meaningful when: 1953 ** # Bit[11] of this register is set to 1b, 1954 ** indicating that a Grant Time-out violation had occurred. 1955 ** # bridge internal arbiter is enabled. 1956 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 1957 ** 0000b REQ#/GNT#[0] 1958 ** 0001b REQ#/GNT#[1] 1959 ** 0010b REQ#/GNT#[2] 1960 ** 0011b REQ#/GNT#[3] 1961 ** 1111b Default Value (no violation detected) 1962 ** When bit[11] is cleared by software, this field reverts back to its default value. 1963 ** All other values are Reserved 1964 ** 11 0b Grant Time-out Occurred: When set to 1b, 1965 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 1966 ** Software clears this bit by writing a 1b to it. 1967 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 1968 ** 1=During bus idle, bridge parks the bus on itself. 1969 ** The bus grant is removed from the last master and internally asserted to bridge. 1970 ** 09:08 00b Reserved 1971 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 1972 ** Each bit of this field assigns its corresponding secondary 1973 ** bus master to either the high priority arbiter ring (1b) 1974 ** or to the low priority arbiter ring (0b). 1975 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 1976 ** Bit [6] corresponds to the bridge internal secondary bus request 1977 ** while Bit [7] corresponds to the SATU secondary bus request. 1978 ** Bits [5:4] are unused. 1979 ** 0b=Indicates that the master belongs to the low priority group. 1980 ** 1b=Indicates that the master belongs to the high priority group 1981 **================================================================================= 1982 ** 0x43: Bridge Control Register 0 - BCR0 1983 ** Bit Default Description 1984 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 1985 ** and the Posted Write data is limited to 4KB. 1986 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 1987 ** 14 Posted Memory Write transactions and 8KB of posted write data. 1988 ** 06:03 0H Reserved. 1989 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 1990 ** to perform upstream prefetch operations for Memory 1991 ** Read requests received on its secondary interface. 1992 ** This bit also controls the bridge's ability to generate advanced read commands 1993 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 1994 ** to a Conventional PCI bus. 1995 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 1996 ** The use of Memory Read Line and Memory Read 1997 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request 1998 ** to an upstream bus operating in Conventional PCI mode. 1999 ** 1b=bridge treats upstream PCI Memory Read requests as though 2000 ** they target non-prefetchable memory and forwards upstream PCI-X Memory 2001 ** Read Block commands as Memory Read 2002 ** when the primary bus is operating 2003 ** in Conventional PCI mode. 2004 ** NOTE: This bit does not affect bridge ability to perform read prefetching 2005 ** when the received command is Memory Read Line or Memory Read Multiple. 2006 **================================================================================= 2007 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 2008 ** Bit Default Description 2009 ** 15:08 0000000b Reserved 2010 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, 2011 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 2012 ** The three options for handling these alias commands are to either pass it as is, 2013 ** re-map to the actual block memory read/write command encoding, or ignore 2014 ** the transaction forcing a Master Abort to occur on the Origination Bus. 2015 ** Bit (7:6) Handling of command 2016 ** 0 0 Re-map to Memory Read/Write Block before forwarding 2017 ** 0 1 Enqueue and forward the alias command code unaltered 2018 ** 1 0 Ignore the transaction, forcing Master Abort 2019 ** 1 1 Reserved 2020 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 2021 ** The watchdog timers are used to detect prohibitively long latencies in the system. 2022 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 2023 ** or Split Requests (PCI-X mode) is not completed within 2 24 events 2024 ** (��events�� are defined as PCI Clocks when operating in PCI-X mode, 2025 ** and as the number of times being retried when operating in Conventional PCI mode) 2026 ** 0b=All 2 24 watchdog timers are enabled. 2027 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to 2028 ** the number of attempts bridge makes when initiating a PMW, 2029 ** transacting a Delayed Transaction, or how long it waits for 2030 ** a split completion corresponding to one of its requests. 2031 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 2032 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 2033 ** 0b=The Secondary bus arbiter times out an agent 2034 ** that does not assert FRAME# within 16/6 clocks of receiving its grant, 2035 ** once the bus has gone idle. 2036 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 2037 ** An infringing agent does not receive a subsequent GNT# 2038 ** until it de-asserts its REQ# for at least one clock cycle. 2039 ** 1b=GNT# time-out mechanism is disabled. 2040 ** 03 00b Reserved. 2041 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 2042 ** The time out mechanism is used to ensure that initiators 2043 ** of delayed transactions return for their delayed completion data/status 2044 ** within a reasonable amount of time after it is available from bridge. 2045 ** 0b=The secondary master time-out counter is enabled 2046 ** and uses the value specified by the Secondary Discard Timer bit 2047 ** (see Bridge Control Register). 2048 ** 1b=The secondary master time-out counter is disabled. 2049 ** The bridge waits indefinitely for a secondary bus master 2050 ** to repeat a delayed transaction. 2051 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 2052 ** The time out mechanism is used to ensure that initiators 2053 ** of delayed transactions return for their delayed completion data/status 2054 ** within a reasonable amount of time after it is available from bridge. 2055 ** 0b=The primary master time-out counter is enabled and uses the value specified 2056 ** by the Primary Discard Timer bit (see Bridge Control Register). 2057 ** 1b=The secondary master time-out counter is disabled. 2058 ** The bridge waits indefinitely for a secondary bus master 2059 ** to repeat a delayed transaction. 2060 ** 00 0b Reserved 2061 **================================================================================= 2062 ** 0x47-0x46: Bridge Control Register 2 - BCR2 2063 ** Bit Default Description 2064 ** 15:07 0000b Reserved. 2065 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 2066 ** This bit disables all of the secondary PCI clock outputs including 2067 ** the feedback clock S_CLKOUT. 2068 ** This means that the user is required to provide an S_CLKIN input source. 2069 ** 05:04 11 (66 MHz) Preserved. 2070 ** 01 (100 MHz) 2071 ** 00 (133 MHz) 2072 ** 03:00 Fh (100 MHz & 66 MHz) 2073 ** 7h (133 MHz) 2074 ** This 4 bit field provides individual enable/disable mask bits for each of bridge 2075 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 2076 ** default to being enabled following the rising edge of P_RST#, depending on the 2077 ** frequency of the secondary bus clock: 2078 ** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with 2079 ** all four S_CLKOs enabled by default. (SCLKO[3:0])�P 2080 ** �E Designs with 133 MHz Secondary PCI clock power up 2081 ** with the lower order 3 S_CLKOs enabled by default. 2082 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 2083 ** to downstream device clock inputs. 2084 **================================================================================= 2085 ** 0x49-0x48: Bridge Status Register - BSR 2086 ** Bit Default Description 2087 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 2088 ** is conditionally asserted when the secondary discard timer expires. 2089 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 2090 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2091 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 2092 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2093 ** when bridge discards an upstream split read request 2094 ** after waiting in excess of 2 24 clocks for the corresponding 2095 ** Split Completion to arrive. 2096 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 2097 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2098 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 2099 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 2100 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 2101 ** Split Completion to arrive. 2102 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 2103 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 2104 ** by bridge, to retire a PMW upstream. 2105 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 2106 ** is conditionally asserted when a Target Abort occurs as a result of an attempt, 2107 ** by bridge, to retire a PMW upstream. 2108 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 2109 ** is conditionally asserted when bridge discards an upstream PMW transaction 2110 ** after receiving 2 24 target retries from the primary bus target 2111 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 2112 ** is conditionally asserted when a data parity error is detected by bridge 2113 ** while attempting to retire a PMW upstream 2114 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 2115 ** is conditionally asserted when bridge detects an address parity error on 2116 ** the secondary bus. 2117 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 2118 ** is conditionally asserted when the primary bus discard timer expires. 2119 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 2120 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2121 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 2122 ** from the secondary bus target. 2123 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2124 ** when bridge discards a downstream split read request 2125 ** after waiting in excess of 2 24 clocks for the corresponding 2126 ** Split Completion to arrive. 2127 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 2128 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2129 ** when bridge discards a downstream delayed write transaction request 2130 ** after receiving 2 24 target retries from the secondary bus target. 2131 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 2132 ** is conditionally asserted when bridge discards a downstream 2133 ** split write request after waiting in excess of 2 24 clocks 2134 ** for the corresponding Split Completion to arrive. 2135 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 2136 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 2137 ** by bridge, to retire a PMW downstream. 2138 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 2139 ** when a Target Abort occurs as a result of an attempt, by bridge, 2140 ** to retire a PMW downstream. 2141 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 2142 ** is conditionally asserted when bridge discards a downstream PMW transaction 2143 ** after receiving 2 24 target retries from the secondary bus target 2144 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 2145 ** is conditionally asserted when a data parity error is detected by bridge 2146 ** while attempting to retire a PMW downstream. 2147 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 2148 ** when bridge detects an address parity error on the primary bus. 2149 **================================================================================== 2150 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 2151 ** Bit Default Description 2152 ** 15:13 000b Reserved 2153 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 2154 ** that a secondary bus master has its grant maintained in order to enable 2155 ** multiple transactions to execute within the same arbitration cycle. 2156 ** Bit[02:00] GNT# Extended Duration 2157 ** 000 MTT Disabled (Default=no GNT# extension) 2158 ** 001 16 clocks 2159 ** 010 32 clocks 2160 ** 011 64 clocks 2161 ** 100 128 clocks 2162 ** 101 256 clocks 2163 ** 110 Invalid (treated as 000) 2164 ** 111 Invalid (treated as 000) 2165 ** 09:08 00b Reserved 2166 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 2167 ** pair supported by bridge secondary arbiter. 2168 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 2169 ** bit(6) corresponds to bridge internal REQ#/GNT# pair, 2170 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 2171 ** When a given bit is set to 1b, its corresponding REQ#/GNT# 2172 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 2173 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 2174 **================================================================================== 2175 ** 0x53-0x52: Read Prefetch Policy Register - RPPR 2176 ** Bit Default Description 2177 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 2178 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 2179 ** using the FirstRead parameter. 2180 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2181 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 2182 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 2183 ** the number of bytes to prefetch from the secondary bus interface 2184 ** on the initial PreFetch operation. 2185 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2186 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2187 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2188 ** in calculating the number of bytes to prefetch from the primary 2189 ** bus interface on subsequent PreFetch operations given 2190 ** that the read demands were not satisfied using 2191 ** the FirstRead parameter. 2192 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 2193 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 2194 ** Memory Read Multiple 6 cache lines 2195 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2196 ** in calculating the number of bytes to prefetch from 2197 ** the primary bus interface on the initial PreFetch operation. 2198 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 2199 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2200 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 2201 ** algorithm for the secondary and the primary bus interfaces. 2202 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 2203 ** enable bits for REQ#/GNT#[2:0]. 2204 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 2205 ** 1b: enables the staged pre-fetch feature 2206 ** 0b: disables staged pre-fetch, 2207 ** and hardwires read pre-fetch policy to the following for 2208 ** Memory Read, 2209 ** Memory Read Line, 2210 ** and Memory Read Multiple commands: 2211 ** Command Type Hardwired Pre-Fetch Amount... 2212 ** Memory Read 4 DWORDs 2213 ** Memory Read Line 1 cache line 2214 ** Memory Read Multiple 2 cache lines 2215 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 2216 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read 2217 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 2218 **================================================================================== 2219 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 2220 ** Bit Default Description 2221 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 2222 ** in response to its discarding of a delayed transaction that was initiated from the primary bus. 2223 ** 0b=bridge asserts P_SERR#. 2224 ** 1b=bridge does not assert P_SERR# 2225 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2226 ** 0b=bridge asserts P_SERR#. 2227 ** 1b=bridge does not assert P_SERR# 2228 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2229 ** 0b=bridge asserts P_SERR#. 2230 ** 1b=bridge does not assert P_SERR# 2231 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 2232 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 2233 ** 0b=bridge asserts P_SERR#. 2234 ** 1b=bridge does not assert P_SERR# 2235 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 2236 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 2237 ** 0b=bridge asserts P_SERR#. 2238 ** 1b=bridge does not assert P_SERR# 2239 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 2240 ** it discards an upstream posted write transaction. 2241 ** 0b=bridge asserts P_SERR#. 2242 ** 1b=bridge does not assert P_SERR# 2243 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 2244 ** when a data parity error is detected while attempting to retire on of its PMWs upstream. 2245 ** 0b=bridge asserts P_SERR#. 2246 ** 1b=bridge does not assert P_SERR# 2247 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 2248 ** when it detects an address parity error on the secondary bus. 2249 ** 0b=bridge asserts P_SERR#. 2250 ** 1b=bridge does not assert P_SERR# 2251 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 2252 ** its discarding of a delayed transaction that was initiated on the secondary bus. 2253 ** 0b=bridge asserts P_SERR#. 2254 ** 1b=bridge does not assert P_SERR# 2255 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2256 ** 0b=bridge asserts P_SERR#. 2257 ** 1b=bridge does not assert P_SERR# 2258 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2259 ** 0b=bridge asserts P_SERR#. 2260 ** 1b=bridge does not assert P_SERR# 2261 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 2262 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 2263 ** 0b=bridge asserts P_SERR#. 2264 ** 1b=bridge does not assert P_SERR# 2265 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 2266 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 2267 ** 0b=bridge asserts P_SERR#. 2268 ** 1b=bridge does not assert P_SERR# 2269 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 2270 ** that it discards a downstream posted write transaction. 2271 ** 0b=bridge asserts P_SERR#. 2272 ** 1b=bridge does not assert P_SERR# 2273 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 2274 ** when a data parity error is detected while attempting to retire on of its PMWs downstream. 2275 ** 0b=bridge asserts P_SERR#. 2276 ** 1b=bridge does not assert P_SERR# 2277 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 2278 ** when it detects an address parity error on the primary bus. 2279 ** 0b=bridge asserts P_SERR#. 2280 ** 1b=bridge does not assert P_SERR# 2281 **=============================================================================== 2282 ** 0x56: Pre-Boot Status Register - PBSR 2283 ** Bit Default Description 2284 ** 07 1 Reserved 2285 ** 06 - Reserved - value indeterminate 2286 ** 05:02 0 Reserved 2287 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 2288 ** This bit reflect captured S_133EN strap, 2289 ** indicating the maximum secondary bus clock frequency when in PCI-X mode. 2290 ** Max Allowable Secondary Bus Frequency 2291 ** ** S_133EN PCI-X Mode 2292 ** ** 0 100 MHz 2293 ** ** 1 133 MH 2294 ** 00 0b Reserved 2295 **=============================================================================== 2296 ** 0x59-0x58: Secondary Decode Enable Register - SDER 2297 ** Bit Default Description 2298 ** 15:03 FFF1h Preserved. 2299 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 2300 ** bridge overrides its secondary inverse decode logic and not 2301 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 2302 ** This creates a private memory space on the Secondary PCI bus 2303 ** that allows peer-to-peer transactions. 2304 ** 01:00 10 2 Preserved. 2305 **=============================================================================== 2306 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 2307 ** Bit Default Description 2308 ** 15:10 000000 2 Reserved. 2309 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 2310 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 2311 ** When this bit is clear, 2312 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 2313 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 2314 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 2315 ** When this bit is clear, 2316 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 2317 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 2318 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 2319 ** When this bit is clear, 2320 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 2321 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 2322 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 2323 ** When this bit is clear, 2324 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 2325 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 2326 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 2327 ** When this bit is clear, 2328 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 2329 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 2330 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 2331 ** When this bit is clear, 2332 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 2333 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 2334 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 2335 ** When this bit is clear, 2336 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 2337 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 2338 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 2339 ** When this bit is clear, 2340 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 2341 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 2342 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 2343 ** When this bit is clear, 2344 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 2345 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 2346 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 2347 ** When this bit is clear, 2348 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 2349 ************************************************************************** 2350 */ 2351 /* 2352 ************************************************************************** 2353 ** Reserved A8-CBh 2354 ************************************************************************** 2355 */ 2356 /* 2357 ************************************************************************** 2358 ** PCI Extended Enhanced Capabilities List CC-FFh 2359 ************************************************************************** 2360 ** ---------------------------------------------------------------------------------------------------------- 2361 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2362 ** ---------------------------------------------------------------------------------------------------------- 2363 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 2364 ** ---------------------------------------------------------------------------------------------------------- 2365 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h 2366 ** ---------------------------------------------------------------------------------------------------------- 2367 ** | Reserved | Reserved | Reserved | E4h 2368 ** ---------------------------------------------------------------------------------------------------------- 2369 ** | Reserved | E8h 2370 ** ---------------------------------------------------------------------------------------------------------- 2371 ** | Reserved | Reserved | Reserved | Reserved | ECh 2372 ** ---------------------------------------------------------------------------------------------------------- 2373 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 2374 ** ---------------------------------------------------------------------------------------------------------- 2375 ** | PCI-X Bridge Status | F4h 2376 ** ---------------------------------------------------------------------------------------------------------- 2377 ** | PCI-X Upstream Split Transaction Control | F8h 2378 ** ---------------------------------------------------------------------------------------------------------- 2379 ** | PCI-X Downstream Split Transaction Control | FCh 2380 ** ---------------------------------------------------------------------------------------------------------- 2381 **=============================================================================== 2382 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID 2383 ** Bit Default Description 2384 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 2385 **=============================================================================== 2386 ** 0xDD: Next Item Pointer - PM_NXTP 2387 ** Bit Default Description 2388 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 2389 **=============================================================================== 2390 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR 2391 ** Bit Default Description 2392 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 2393 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 2394 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 2395 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 2396 ** This returns 000b as PME# wake-up for bridge is not implemented. 2397 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 2398 ** 04:03 00 Reserved 2399 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 2400 **=============================================================================== 2401 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 2402 ** Bit Default Description 2403 ** 15:09 00h Reserved 2404 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 2405 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 2406 ** 07:02 00h Reserved 2407 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 2408 ** a function and to set the Function into a new power state. 2409 ** 00 - D0 state 2410 ** 01 - D1 state 2411 ** 10 - D2 state 2412 ** 11 - D3 hot state 2413 **=============================================================================== 2414 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 2415 ** Bit Default Description 2416 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 2417 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 2418 ** is to occur as a direct result of programming the function to D3 hot. 2419 ** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 2420 ** 05:00 00h Reserved 2421 **=============================================================================== 2422 ** 0xE3: Power Management Data Register - PMDR 2423 ** Bit Default Description 2424 ** 07:00 00h Reserved 2425 **=============================================================================== 2426 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 2427 ** Bit Default Description 2428 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 2429 **=============================================================================== 2430 ** 0xF1: Next Item Pointer - PX_NXTP 2431 ** Bit Default Description 2432 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 2433 ** register is 00h indicating that this is the last entry in the linked list of capabilities. 2434 **=============================================================================== 2435 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 2436 ** Bit Default Description 2437 ** 15:09 00h Reserved 2438 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 2439 ** The values are: 2440 ** ** BitsMax FrequencyClock Period 2441 ** ** 000PCI ModeN/A 2442 ** ** 00166 15 2443 ** ** 01010010 2444 ** ** 0111337.5 2445 ** ** 1xxreservedreserved 2446 ** ** The default value for this register is the operating frequency of the secondary bus 2447 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 2448 ** secondary bus to the primary bus because there is not enough room within the limit 2449 ** specified in the Split Transaction Commitment Limit field in the Downstream Split 2450 ** Transaction Control register. The bridge does not set this bit. 2451 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 2452 ** The bridge does not set this bit. 2453 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 2454 ** equal to bridge secondary bus number, device number 00h, 2455 ** and function number 0 is received on the secondary interface. 2456 ** This bit is cleared by software writing a '1'. 2457 ** 02 0b Split Completion Discarded (SCD): This bit is set 2458 ** when bridge discards a split completion moving toward the secondary bus 2459 ** because the requester would not accept it. This bit cleared by software writing a '1'. 2460 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 2461 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 2462 **=============================================================================== 2463 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 2464 ** Bit Default Description 2465 ** 31:22 0 Reserved 2466 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 2467 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 2468 ** because bridge throttles traffic on the completion side. 2469 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 2470 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 2471 ** this bit by writing a 1b to it. 2472 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 2473 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 2474 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 2475 ** 0=The maximum operating frequency is 66 MHz. 2476 ** 1=The maximum operating frequency is 133 MHz. 2477 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 2478 ** 0=Primary Interface is connected as a 32-bit PCI bus. 2479 ** 1=Primary Interface is connected as a 64-bit PCI bus. 2480 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 2481 ** of the BNUM register at offset 18h. 2482 ** Apparently it was deemed necessary reflect it here for diagnostic purposes. 2483 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 2484 ** May be updated whenever a PCI-X 2485 ** configuration write cycle that targets bridge scores a hit. 2486 ** 02:00 0h Function Number (FNUM): The bridge Function # 2487 **=============================================================================== 2488 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 2489 ** Bit Default Description 2490 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2491 ** Software is permitted to program this register to any value greater than or equal to 2492 ** the contents of the Split Transaction Capacity register. A value less than the contents 2493 ** of the Split Transaction Capacity register causes unspecified results. 2494 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2495 ** size regardless of the amount of buffer space available. 2496 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2497 ** split completions. This register controls behavior of the bridge buffers for forwarding 2498 ** Split Transactions from a primary bus requester to a secondary bus completer. 2499 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 2500 **=============================================================================== 2501 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 2502 ** Bit Default Description 2503 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2504 ** Software is permitted to program this register to any value greater than or equal to 2505 ** the contents of the Split Transaction Capacity register. A value less than the contents 2506 ** of the Split Transaction Capacity register causes unspecified results. 2507 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2508 ** size regardless of the amount of buffer space available. 2509 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2510 ** split completions. This register controls behavior of the bridge buffers for forwarding 2511 ** Split Transactions from a primary bus requester to a secondary bus completer. 2512 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs 2513 ** (7936 bytes). 2514 ************************************************************************** 2515 */ 2516 2517 2518 2519 2520 /* 2521 ************************************************************************************************************************************* 2522 ** 80331 Address Translation Unit Register Definitions 2523 ** ATU Interface Configuration Header Format 2524 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 2525 ************************************************************************************************************************************* 2526 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 2527 **=================================================================================================================================== 2528 ** | ATU Device ID | Vendor ID | 00h 2529 ** ---------------------------------------------------------------------------------------------------------- 2530 ** | Status | Command | 04H 2531 ** ---------------------------------------------------------------------------------------------------------- 2532 ** | ATU Class Code | Revision ID | 08H 2533 ** ---------------------------------------------------------------------------------------------------------- 2534 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 2535 ** ---------------------------------------------------------------------------------------------------------- 2536 ** | Inbound ATU Base Address 0 | 10H 2537 ** ---------------------------------------------------------------------------------------------------------- 2538 ** | Inbound ATU Upper Base Address 0 | 14H 2539 ** ---------------------------------------------------------------------------------------------------------- 2540 ** | Inbound ATU Base Address 1 | 18H 2541 ** ---------------------------------------------------------------------------------------------------------- 2542 ** | Inbound ATU Upper Base Address 1 | 1CH 2543 ** ---------------------------------------------------------------------------------------------------------- 2544 ** | Inbound ATU Base Address 2 | 20H 2545 ** ---------------------------------------------------------------------------------------------------------- 2546 ** | Inbound ATU Upper Base Address 2 | 24H 2547 ** ---------------------------------------------------------------------------------------------------------- 2548 ** | Reserved | 28H 2549 ** ---------------------------------------------------------------------------------------------------------- 2550 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 2551 ** ---------------------------------------------------------------------------------------------------------- 2552 ** | Expansion ROM Base Address | 30H 2553 ** ---------------------------------------------------------------------------------------------------------- 2554 ** | Reserved Capabilities Pointer | 34H 2555 ** ---------------------------------------------------------------------------------------------------------- 2556 ** | Reserved | 38H 2557 ** ---------------------------------------------------------------------------------------------------------- 2558 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 2559 ** ---------------------------------------------------------------------------------------------------------- 2560 ********************************************************************************************************************* 2561 */ 2562 /* 2563 *********************************************************************************** 2564 ** ATU Vendor ID Register - ATUVID 2565 ** ----------------------------------------------------------------- 2566 ** Bit Default Description 2567 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 2568 ** This register, combined with the DID, uniquely identify the PCI device. 2569 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 2570 ** to simulate the interface of a standard mechanism currently used by existing application software. 2571 *********************************************************************************** 2572 */ 2573 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 2574 /* 2575 *********************************************************************************** 2576 ** ATU Device ID Register - ATUDID 2577 ** ----------------------------------------------------------------- 2578 ** Bit Default Description 2579 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 2580 ** This ID, combined with the VID, uniquely identify any PCI device. 2581 *********************************************************************************** 2582 */ 2583 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 2584 /* 2585 *********************************************************************************** 2586 ** ATU Command Register - ATUCMD 2587 ** ----------------------------------------------------------------- 2588 ** Bit Default Description 2589 ** 15:11 000000 2 Reserved 2590 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 2591 ** 0=enables the assertion of interrupt signal. 2592 ** 1=disables the assertion of its interrupt signal. 2593 ** 09 0 2 Fast Back to Back Enable - When cleared, 2594 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 2595 ** Ignored when operating in the PCI-X mode. 2596 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 2597 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 2598 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 2599 ** of address stepping for PCI-X mode. 2600 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 2601 ** is detected. When cleared, parity checking is disabled. 2602 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 2603 ** does not perform VGA palette snooping. 2604 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 2605 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 2606 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 2607 ** Not implemented and a reserved bit field. 2608 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 2609 ** When cleared, disables the device from generating PCI accesses. 2610 ** When set, allows the device to behave as a PCI bus master. 2611 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 2612 ** of the state of this bit. 2613 ** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. 2614 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 2615 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 2616 ** Not implemented and a reserved bit field. 2617 *********************************************************************************** 2618 */ 2619 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 2620 /* 2621 *********************************************************************************** 2622 ** ATU Status Register - ATUSR (Sheet 1 of 2) 2623 ** ----------------------------------------------------------------- 2624 ** Bit Default Description 2625 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 2626 ** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 2627 ** �E Write Data Parity Error when the ATU is a target (inbound write). 2628 ** �E Read Data Parity Error when the ATU is a requester (outbound read). 2629 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 2630 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 2631 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 2632 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 2633 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 2634 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 2635 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 2636 ** terminates the transaction on the PCI bus with a target abort. 2637 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 2638 ** timing for a target device in Conventional PCI Mode regardless of the operating mode 2639 ** (except configuration accesses). 2640 ** 00 2=Fast 2641 ** 01 2=Medium 2642 ** 10 2=Slow 2643 ** 11 2=Reserved 2644 ** The ATU interface uses Medium timing. 2645 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 2646 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2647 ** �E And the ATU acted as the requester 2648 ** for the operation in which the error occurred. 2649 ** �E And the ATUCMD register��s Parity Error Response bit is set 2650 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2651 ** �E And the ATUCMD register��s Parity Error Response bit is set 2652 ** 07 1 2 (Conventional mode) 2653 ** 0 2 (PCI-X mode) 2654 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 2655 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 2656 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 2657 ** 06 0 2 UDF Supported - User Definable Features are not supported 2658 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 2659 ** 04 1 2 Capabilities - When set, this function implements extended capabilities. 2660 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt 2661 ** when the Interrupt Disable bit in the command register is a 0. 2662 ** 0=ATU interrupt signal deasserted. 2663 ** 1=ATU interrupt signal asserted. 2664 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 2665 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 2666 ** interrupt signal. 2667 ** 02:00 00000 2 Reserved. 2668 *********************************************************************************** 2669 */ 2670 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 2671 /* 2672 *********************************************************************************** 2673 ** ATU Revision ID Register - ATURID 2674 ** ----------------------------------------------------------------- 2675 ** Bit Default Description 2676 ** 07:00 00H ATU Revision - identifies the 80331 revision number. 2677 *********************************************************************************** 2678 */ 2679 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 2680 /* 2681 *********************************************************************************** 2682 ** ATU Class Code Register - ATUCCR 2683 ** ----------------------------------------------------------------- 2684 ** Bit Default Description 2685 ** 23:16 05H Base Class - Memory Controller 2686 ** 15:08 80H Sub Class - Other Memory Controller 2687 ** 07:00 00H Programming Interface - None defined 2688 *********************************************************************************** 2689 */ 2690 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 2691 /* 2692 *********************************************************************************** 2693 ** ATU Cacheline Size Register - ATUCLSR 2694 ** ----------------------------------------------------------------- 2695 ** Bit Default Description 2696 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 2697 *********************************************************************************** 2698 */ 2699 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 2700 /* 2701 *********************************************************************************** 2702 ** ATU Latency Timer Register - ATULT 2703 ** ----------------------------------------------------------------- 2704 ** Bit Default Description 2705 ** 07:03 00000 2 (for Conventional mode) 2706 ** 01000 2 (for PCI-X mode) 2707 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 2708 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 2709 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 2710 *********************************************************************************** 2711 */ 2712 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 2713 /* 2714 *********************************************************************************** 2715 ** ATU Header Type Register - ATUHTR 2716 ** ----------------------------------------------------------------- 2717 ** Bit Default Description 2718 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 2719 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 2720 ** header conforms to PCI Local Bus Specification, Revision 2.3. 2721 *********************************************************************************** 2722 */ 2723 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 2724 /* 2725 *********************************************************************************** 2726 ** ATU BIST Register - ATUBISTR 2727 ** 2728 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 2729 ** initiated. This register is the interface between the host processor requesting BIST functions and 2730 ** the 80331 replying with the results from the software implementation of the BIST functionality. 2731 ** ----------------------------------------------------------------- 2732 ** Bit Default Description 2733 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 2734 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 2735 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 2736 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 2737 ** found in ATUBISTR register bits [3:0]. 2738 ** When the ATUCR BIST Interrupt Enable bit is clear: 2739 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 2740 ** The Intel XScale core does not clear this bit. 2741 ** 05:04 00 2 Reserved 2742 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 2743 ** The Intel XScale core places the results of the software BIST in these bits. 2744 ** A nonzero value indicates a device-specific error. 2745 *********************************************************************************** 2746 */ 2747 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 2748 2749 /* 2750 *************************************************************************************** 2751 ** ATU Base Registers and Associated Limit Registers 2752 *************************************************************************************** 2753 ** Base Address Register Limit Register Description 2754 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 2755 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 2756 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 2757 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 2758 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 2759 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 2760 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 2761 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 2762 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 2763 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 2764 **-------------------------------------------------------------------------------------- 2765 ** ATU Inbound Window 1 is not a translate window. 2766 ** The ATU does not claim any PCI accesses that fall within this range. 2767 ** This window is used to allocate host memory for use by Private Devices. 2768 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 2769 *********************************************************************************** 2770 */ 2771 2772 /* 2773 *********************************************************************************** 2774 ** Inbound ATU Base Address Register 0 - IABAR0 2775 ** 2776 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 2777 ** defines the block of memory addresses where the inbound translation window 0 begins. 2778 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2779 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 2780 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 2781 ** depending on the value located within the IALR0. 2782 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 2783 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 2784 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2785 ** Warning: 2786 ** When IALR0 is cleared prior to host configuration: 2787 ** the user should also clear the Prefetchable Indicator and the Type Indicator. 2788 ** Assuming IALR0 is not cleared: 2789 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2790 ** when the Prefetchable Indicator is cleared prior to host configuration, 2791 ** the user should also set the Type Indicator for 32 bit addressability. 2792 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 2793 ** when the Prefetchable Indicator is set prior to host configuration, the user 2794 ** should also set the Type Indicator for 64 bit addressability. 2795 ** This is the default for IABAR0. 2796 ** ----------------------------------------------------------------- 2797 ** Bit Default Description 2798 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location 2799 ** the translation function is to respond to when addressed from the PCI bus. 2800 ** 11:04 00H Reserved. 2801 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2802 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 2803 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2804 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2805 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2806 ** The ATU does not occupy I/O space, 2807 ** thus this bit must be zero. 2808 *********************************************************************************** 2809 */ 2810 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 2811 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 2812 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2813 /* 2814 *********************************************************************************** 2815 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2816 ** 2817 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2818 ** Together with the Translation Base Address this register defines the actual location the translation 2819 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2820 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2821 ** Note: 2822 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2823 ** the IAUBAR0 register attributes are read-only. 2824 ** ----------------------------------------------------------------- 2825 ** Bit Default Description 2826 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2827 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2828 *********************************************************************************** 2829 */ 2830 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2831 /* 2832 *********************************************************************************** 2833 ** Inbound ATU Base Address Register 1 - IABAR1 2834 ** 2835 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2836 ** defines the block of memory addresses where the inbound translation window 1 begins. 2837 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2838 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2839 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2840 ** Warning: 2841 ** When a non-zero value is not written to IALR1 prior to host configuration, 2842 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2843 ** This is the default for IABAR1. 2844 ** Assuming a non-zero value is written to IALR1, 2845 ** the user may set the Prefetchable Indicator 2846 ** or the Type Indicator: 2847 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2848 ** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2849 ** the user should also leave the Type Indicator set for 32 bit addressability. 2850 ** This is the default for IABAR1. 2851 ** b. when the Prefetchable Indicator is set prior to host configuration, 2852 ** the user should also set the Type Indicator for 64 bit addressability. 2853 ** ----------------------------------------------------------------- 2854 ** Bit Default Description 2855 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2856 ** 11:04 00H Reserved. 2857 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2858 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2859 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2860 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2861 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2862 ** The ATU does not occupy I/O space, 2863 ** thus this bit must be zero. 2864 *********************************************************************************** 2865 */ 2866 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2867 /* 2868 *********************************************************************************** 2869 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2870 ** 2871 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2872 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2873 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2874 ** The programmed value within the base address register must comply with the PCI programming 2875 ** requirements for address alignment. 2876 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2877 ** from the PCI bus. 2878 ** Note: 2879 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 2880 ** the IAUBAR1 register attributes are read-only. 2881 ** This is the default for IABAR1. 2882 ** ----------------------------------------------------------------- 2883 ** Bit Default Description 2884 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 2885 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 2886 *********************************************************************************** 2887 */ 2888 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 2889 /* 2890 *********************************************************************************** 2891 ** Inbound ATU Base Address Register 2 - IABAR2 2892 ** 2893 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 2894 ** defines the block of memory addresses where the inbound translation window 2 begins. 2895 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2896 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 2897 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 2898 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2899 ** Warning: 2900 ** When a non-zero value is not written to IALR2 prior to host configuration, 2901 ** the user should not set either the Prefetchable Indicator 2902 ** or the Type Indicator for 64 bit addressability. 2903 ** This is the default for IABAR2. 2904 ** Assuming a non-zero value is written to IALR2, 2905 ** the user may set the Prefetchable Indicator 2906 ** or the Type Indicator: 2907 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2908 ** when the Prefetchable Indicator is not set prior to host configuration, 2909 ** the user should also leave the Type Indicator set for 32 bit addressability. 2910 ** This is the default for IABAR2. 2911 ** b. when the Prefetchable Indicator is set prior to host configuration, 2912 ** the user should also set the Type Indicator for 64 bit addressability. 2913 ** ----------------------------------------------------------------- 2914 ** Bit Default Description 2915 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location 2916 ** the translation function is to respond to when addressed from the PCI bus. 2917 ** 11:04 00H Reserved. 2918 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2919 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2920 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2921 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2922 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2923 ** The ATU does not occupy I/O space, 2924 ** thus this bit must be zero. 2925 *********************************************************************************** 2926 */ 2927 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 2928 /* 2929 *********************************************************************************** 2930 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2 2931 ** 2932 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2933 ** Together with the Translation Base Address this register defines the actual location 2934 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2935 ** The programmed value within the base address register must comply with the PCI programming 2936 ** requirements for address alignment. 2937 ** Note: 2938 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 2939 ** the IAUBAR2 register attributes are read-only. 2940 ** This is the default for IABAR2. 2941 ** ----------------------------------------------------------------- 2942 ** Bit Default Description 2943 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 2944 ** these bits define the actual location the translation function is to respond to 2945 ** when addressed from the PCI bus for addresses > 4GBytes. 2946 *********************************************************************************** 2947 */ 2948 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 2949 /* 2950 *********************************************************************************** 2951 ** ATU Subsystem Vendor ID Register - ASVIR 2952 ** ----------------------------------------------------------------- 2953 ** Bit Default Description 2954 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 2955 *********************************************************************************** 2956 */ 2957 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 2958 /* 2959 *********************************************************************************** 2960 ** ATU Subsystem ID Register - ASIR 2961 ** ----------------------------------------------------------------- 2962 ** Bit Default Description 2963 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 2964 *********************************************************************************** 2965 */ 2966 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 2967 /* 2968 *********************************************************************************** 2969 ** Expansion ROM Base Address Register -ERBAR 2970 ** ----------------------------------------------------------------- 2971 ** Bit Default Description 2972 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 2973 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 2974 ** 11:01 000H Reserved 2975 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address 2976 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 2977 *********************************************************************************** 2978 */ 2979 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 2980 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 2981 /* 2982 *********************************************************************************** 2983 ** ATU Capabilities Pointer Register - ATU_CAP_PTR 2984 ** ----------------------------------------------------------------- 2985 ** Bit Default Description 2986 ** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space 2987 ** that points to the 80331 PCl Bus Power Management extended capability. 2988 *********************************************************************************** 2989 */ 2990 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 2991 /* 2992 *********************************************************************************** 2993 ** Determining Block Sizes for Base Address Registers 2994 ** The required address size and type can be determined by writing ones to a base address register and 2995 ** reading from the registers. By scanning the returned value from the least-significant bit of the base 2996 ** address registers upwards, the programmer can determine the required address space size. The 2997 ** binary-weighted value of the first non-zero bit found indicates the required amount of space. 2998 ** Table 105 describes the relationship between the values read back and the byte sizes the base 2999 ** address register requires. 3000 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 3001 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 3002 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 3003 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 3004 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 3005 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 3006 ** associated limit registers to enable which bits within the base address register are read/write and 3007 ** which bits are read only (0). This allows the programming of these registers in a manner similar to 3008 ** other PCI devices even though the limit is variable. 3009 ** Table 105. Memory Block Size Read Response 3010 ** Response After Writing all 1s 3011 ** to the Base Address Register 3012 ** Size 3013 ** (Bytes) 3014 ** Response After Writing all 1s 3015 ** to the Base Address Register 3016 ** Size 3017 ** (Bytes) 3018 ** FFFFFFF0H 16 FFF00000H 1 M 3019 ** FFFFFFE0H 32 FFE00000H 2 M 3020 ** FFFFFFC0H 64 FFC00000H 4 M 3021 ** FFFFFF80H 128 FF800000H 8 M 3022 ** FFFFFF00H 256 FF000000H 16 M 3023 ** FFFFFE00H 512 FE000000H 32 M 3024 ** FFFFFC00H 1K FC000000H 64 M 3025 ** FFFFF800H 2K F8000000H 128 M 3026 ** FFFFF000H 4K F0000000H 256 M 3027 ** FFFFE000H 8K E0000000H 512 M 3028 ** FFFFC000H 16K C0000000H 1 G 3029 ** FFFF8000H 32K 80000000H 2 G 3030 ** FFFF0000H 64K 3031 ** 00000000H 3032 ** Register not 3033 ** imple-mented, 3034 ** no 3035 ** address 3036 ** space 3037 ** required. 3038 ** FFFE0000H 128K 3039 ** FFFC0000H 256K 3040 ** FFF80000H 512K 3041 ** 3042 *************************************************************************************** 3043 */ 3044 3045 3046 3047 /* 3048 *********************************************************************************** 3049 ** ATU Interrupt Line Register - ATUILR 3050 ** ----------------------------------------------------------------- 3051 ** Bit Default Description 3052 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 3053 ** request line connects to the device's PCI interrupt request lines 3054 ** (as specified in the interrupt pin register). 3055 ** A value of FFH signifies ��no connection�� or ��unknown��. 3056 *********************************************************************************** 3057 */ 3058 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 3059 /* 3060 *********************************************************************************** 3061 ** ATU Interrupt Pin Register - ATUIPR 3062 ** ----------------------------------------------------------------- 3063 ** Bit Default Description 3064 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 3065 *********************************************************************************** 3066 */ 3067 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 3068 /* 3069 *********************************************************************************** 3070 ** ATU Minimum Grant Register - ATUMGNT 3071 ** ----------------------------------------------------------------- 3072 ** Bit Default Description 3073 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 3074 *********************************************************************************** 3075 */ 3076 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 3077 /* 3078 *********************************************************************************** 3079 ** ATU Maximum Latency Register - ATUMLAT 3080 ** ----------------------------------------------------------------- 3081 ** Bit Default Description 3082 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 3083 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 3084 *********************************************************************************** 3085 */ 3086 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 3087 /* 3088 *********************************************************************************** 3089 ** Inbound Address Translation 3090 ** 3091 ** The ATU allows external PCI bus initiators to directly access the internal bus. 3092 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 3093 ** The process of inbound address translation involves two steps: 3094 ** 1. Address Detection. 3095 ** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 3096 ** within the address windows defined for the inbound ATU. 3097 ** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 3098 ** mode and with Decode A DEVSEL# timing in the PCI-X mode. 3099 ** 2. Address Translation. 3100 ** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 3101 ** The ATU uses the following registers in inbound address window 0 translation: 3102 ** �E Inbound ATU Base Address Register 0 3103 ** �E Inbound ATU Limit Register 0 3104 ** �E Inbound ATU Translate Value Register 0 3105 ** The ATU uses the following registers in inbound address window 2 translation: 3106 ** �E Inbound ATU Base Address Register 2 3107 ** �E Inbound ATU Limit Register 2 3108 ** �E Inbound ATU Translate Value Register 2 3109 ** The ATU uses the following registers in inbound address window 3 translation: 3110 ** �E Inbound ATU Base Address Register 3 3111 ** �E Inbound ATU Limit Register 3 3112 ** �E Inbound ATU Translate Value Register 3 3113 ** Note: Inbound Address window 1 is not a translate window. 3114 ** Instead, window 1 may be used to allocate host memory for Private Devices. 3115 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 3116 ** thus the host BIOS does not configure window 3. 3117 ** Window 3 is intended to be used as a special window into local memory for private PCI 3118 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 3119 ** PCI-to-PCI Bridge in 80331 or 3120 ** Inbound address detection is determined from the 32-bit PCI address, 3121 ** (64-bit PCI address during DACs) the base address register and the limit register. 3122 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 3123 ** 3124 ** The algorithm for detection is: 3125 ** 3126 ** Equation 1. Inbound Address Detection 3127 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 3128 ** the PCI Address is claimed by the Inbound ATU. 3129 ** 3130 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 3131 ** with the associated inbound limit register. 3132 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 3133 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 3134 ** 3135 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 3136 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 3137 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 3138 ** lower 32-bits are used during address translation. 3139 ** The algorithm is: 3140 ** 3141 ** 3142 ** Equation 2. Inbound Translation 3143 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 3144 ** 3145 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 3146 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 3147 ** the result is the internal bus address. This translation mechanism is used for all inbound memory 3148 ** read and write commands excluding inbound configuration read and writes. 3149 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 3150 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 3151 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 3152 ** example: 3153 ** Register Values 3154 ** Base_Register=3A00 0000H 3155 ** Limit_Register=FF80 0000H (8 Mbyte limit value) 3156 ** Value_Register=B100 0000H 3157 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 3158 ** 3159 ** Address Detection (32-bit address) 3160 ** 3161 ** PCI_Address & Limit_Register == Base_Register 3162 ** 3A45 012CH & FF80 0000H == 3A00 0000H 3163 ** 3164 ** ANS: PCI_Address is in the Inbound Translation Window 3165 ** Address Translation (to get internal bus address) 3166 ** 3167 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 3168 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 3169 ** 3170 ** ANS:IB_Address=B145 012CH 3171 *********************************************************************************** 3172 */ 3173 3174 3175 3176 /* 3177 *********************************************************************************** 3178 ** Inbound ATU Limit Register 0 - IALR0 3179 ** 3180 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 3181 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3182 ** PCI addresses to internal bus addresses. 3183 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3184 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3185 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3186 ** Specification, Revision 2.3 for additional information on programming base address registers. 3187 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 3188 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 3189 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 3190 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 3191 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 3192 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 3193 ** ----------------------------------------------------------------- 3194 ** Bit Default Description 3195 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 3196 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 3197 ** 11:00 000H Reserved 3198 *********************************************************************************** 3199 */ 3200 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 3201 /* 3202 *********************************************************************************** 3203 ** Inbound ATU Translate Value Register 0 - IATVR0 3204 ** 3205 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 3206 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3207 ** inbound ATU address translation. 3208 ** ----------------------------------------------------------------- 3209 ** Bit Default Description 3210 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 3211 ** This value must be 64-bit aligned on the internal bus. 3212 ** The default address allows the ATU to access the internal 80331 memory-mapped registers. 3213 ** 11:00 000H Reserved 3214 *********************************************************************************** 3215 */ 3216 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 3217 /* 3218 *********************************************************************************** 3219 ** Expansion ROM Limit Register - ERLR 3220 ** 3221 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 3222 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 3223 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 3224 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 3225 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 3226 ** the corresponding bit within the ERBAR read/write from PCI. 3227 ** ----------------------------------------------------------------- 3228 ** Bit Default Description 3229 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 3230 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 3231 ** 11:00 000H Reserved. 3232 *********************************************************************************** 3233 */ 3234 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 3235 /* 3236 *********************************************************************************** 3237 ** Expansion ROM Translate Value Register - ERTVR 3238 ** 3239 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 3240 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 3241 ** Expansion ROM address translation. 3242 ** ----------------------------------------------------------------- 3243 ** Bit Default Description 3244 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 3245 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 3246 ** 11:00 000H Reserved 3247 *********************************************************************************** 3248 */ 3249 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 3250 /* 3251 *********************************************************************************** 3252 ** Inbound ATU Limit Register 1 - IALR1 3253 ** 3254 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 3255 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 3256 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 3257 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 3258 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 3259 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 3260 ** register. 3261 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 3262 ** not process any PCI bus transactions to this memory range. 3263 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 3264 ** IAUBAR1, and IALR1. 3265 ** ----------------------------------------------------------------- 3266 ** Bit Default Description 3267 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 3268 ** required for the ATUs memory window 1. 3269 ** 11:00 000H Reserved 3270 *********************************************************************************** 3271 */ 3272 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 3273 /* 3274 *********************************************************************************** 3275 ** Inbound ATU Limit Register 2 - IALR2 3276 ** 3277 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 3278 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3279 ** PCI addresses to internal bus addresses. 3280 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 3281 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3282 ** register provides the block size requirements for the base address register. The remaining registers 3283 ** used for performing address translation are discussed in Section 3.2.1.1. 3284 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3285 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3286 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3287 ** Specification, Revision 2.3 for additional information on programming base address registers. 3288 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 3289 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 3290 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 3291 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 3292 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 3293 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 3294 ** register. 3295 ** ----------------------------------------------------------------- 3296 ** Bit Default Description 3297 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 3298 ** required for the ATUs memory window 2. 3299 ** 11:00 000H Reserved 3300 *********************************************************************************** 3301 */ 3302 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 3303 /* 3304 *********************************************************************************** 3305 ** Inbound ATU Translate Value Register 2 - IATVR2 3306 ** 3307 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 3308 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3309 ** inbound ATU address translation. 3310 ** ----------------------------------------------------------------- 3311 ** Bit Default Description 3312 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 3313 ** This value must be 64-bit aligned on the internal bus. 3314 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 3315 ** 11:00 000H Reserved 3316 *********************************************************************************** 3317 */ 3318 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 3319 /* 3320 *********************************************************************************** 3321 ** Outbound I/O Window Translate Value Register - OIOWTVR 3322 ** 3323 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 3324 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 3325 ** result of the outbound ATU address translation. 3326 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 3327 ** length of 64 Kbytes. 3328 ** ----------------------------------------------------------------- 3329 ** Bit Default Description 3330 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 3331 ** 15:00 0000H Reserved 3332 *********************************************************************************** 3333 */ 3334 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 3335 /* 3336 *********************************************************************************** 3337 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0 3338 ** 3339 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 3340 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3341 ** driven on the PCI bus as a result of the outbound ATU address translation. 3342 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 3343 ** of 64 Mbytes. 3344 ** ----------------------------------------------------------------- 3345 ** Bit Default Description 3346 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3347 ** 25:02 00 0000H Reserved 3348 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3349 ** Only linear incrementing mode is supported. 3350 *********************************************************************************** 3351 */ 3352 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 3353 /* 3354 *********************************************************************************** 3355 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 3356 ** 3357 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 3358 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3359 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3360 ** a SAC is generated on the PCI bus. 3361 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 3362 ** length of 64 Mbytes. 3363 ** ----------------------------------------------------------------- 3364 ** Bit Default Description 3365 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3366 *********************************************************************************** 3367 */ 3368 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 3369 /* 3370 *********************************************************************************** 3371 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1 3372 ** 3373 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 3374 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3375 ** driven on the PCI bus as a result of the outbound ATU address translation. 3376 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3377 ** of 64 Mbytes. 3378 ** ----------------------------------------------------------------- 3379 ** Bit Default Description 3380 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3381 ** 25:02 00 0000H Reserved 3382 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3383 ** Only linear incrementing mode is supported. 3384 *********************************************************************************** 3385 */ 3386 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 3387 /* 3388 *********************************************************************************** 3389 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 3390 ** 3391 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 3392 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3393 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3394 ** a SAC is generated on the PCI bus. 3395 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3396 ** of 64 Mbytes. 3397 ** ----------------------------------------------------------------- 3398 ** Bit Default Description 3399 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3400 *********************************************************************************** 3401 */ 3402 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 3403 /* 3404 *********************************************************************************** 3405 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 3406 ** 3407 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 3408 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 3409 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 3410 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 3411 ** ----------------------------------------------------------------- 3412 ** Bit Default Description 3413 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3414 *********************************************************************************** 3415 */ 3416 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 3417 /* 3418 *********************************************************************************** 3419 ** ATU Configuration Register - ATUCR 3420 ** 3421 ** The ATU Configuration Register controls the outbound address translation for address translation 3422 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 3423 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 3424 ** interrupt enabling. 3425 ** ----------------------------------------------------------------- 3426 ** Bit Default Description 3427 ** 31:20 00H Reserved 3428 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 3429 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 3430 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 3431 ** applicable in the PCI-X mode. 3432 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 3433 ** with Direct Addressing enabled (bit 7 of the ATUCR set), 3434 ** the ATU forwards internal bus cycles with an address between 0000.0040H and 3435 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 3436 ** When clear, no translation occurs. 3437 ** 17 0 2 Reserved 3438 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 3439 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 3440 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 3441 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 3442 ** 14:10 00000 2 Reserved 3443 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 3444 ** when the ATU detects that SERR# was asserted. When clear, 3445 ** the Intel XScale core is not interrupted when SERR# is detected. 3446 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 3447 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 3448 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 3449 ** the ATUCR. 3450 ** 07:04 0000 2 Reserved 3451 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 3452 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 3453 ** in the ATUBISTR register. 3454 ** 02 0 2 Reserved 3455 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 3456 ** When cleared, disables the outbound ATU. 3457 ** 00 0 2 Reserved 3458 *********************************************************************************** 3459 */ 3460 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 3461 /* 3462 *********************************************************************************** 3463 ** PCI Configuration and Status Register - PCSR 3464 ** 3465 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring 3466 ** various features of the PCI bus interface. 3467 ** ----------------------------------------------------------------- 3468 ** Bit Default Description 3469 ** 31:19 0000H Reserved 3470 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 3471 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 3472 ** Response bit is cleared. Set under the following conditions: 3473 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 3474 ** 17:16 Varies with 3475 ** external state 3476 ** of DEVSEL#, 3477 ** STOP#, and 3478 ** TRDY#, 3479 ** during 3480 ** P_RST# 3481 ** PCI-X capability - These two bits define the mode of 3482 ** the PCI bus (conventional or PCI-X) as well as the 3483 ** operating frequency in the case of PCI-X mode. 3484 ** 00 - Conventional PCI mode 3485 ** 01 - PCI-X 66 3486 ** 10 - PCI-X 100 3487 ** 11 - PCI-X 133 3488 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 3489 ** Revision 1.0a, the operating 3490 ** mode is determined by an initialization pattern on the PCI bus during 3491 ** P_RST# assertion: 3492 ** DEVSEL# STOP# TRDY# Mode 3493 ** Deasserted Deasserted Deasserted Conventional 3494 ** Deasserted Deasserted Asserted PCI-X 66 3495 ** Deasserted Asserted Deasserted PCI-X 100 3496 ** Deasserted Asserted Asserted PCI-X 133 3497 ** All other patterns are reserved. 3498 ** 15 0 2 3499 ** Outbound Transaction Queue Busy: 3500 ** 0=Outbound Transaction Queue Empty 3501 ** 1=Outbound Transaction Queue Busy 3502 ** 14 0 2 3503 ** Inbound Transaction Queue Busy: 3504 ** 0=Inbound Transaction Queue Empty 3505 ** 1=Inbound Transaction Queue Busy 3506 ** 13 0 2 Reserved. 3507 ** 12 0 2 Discard Timer Value - This bit controls the time-out value 3508 ** for the four discard timers attached to the queues holding read data. 3509 ** A value of 0 indicates the time-out value is 2 15 clocks. 3510 ** A value of 1 indicates the time-out value is 2 10 clocks. 3511 ** 11 0 2 Reserved. 3512 ** 10 Varies with 3513 ** external state 3514 ** of M66EN 3515 ** during 3516 ** P_RST# 3517 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 3518 ** Conventional PCI mode by the assertion of M66EN during bus initialization. 3519 ** When clear, the interface 3520 ** has been initialized as a 33 MHz bus. 3521 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 3522 ** 09 0 2 Reserved 3523 ** 08 Varies with 3524 ** external state 3525 ** of REQ64# 3526 ** during 3527 ** P_RST# 3528 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 3529 ** configured as 64-bit capable by 3530 ** the assertion of REQ64# on the rising edge of P_RST#. When set, 3531 ** the PCI interface is configured as 3532 ** 32-bit only. 3533 ** 07:06 00 2 Reserved. 3534 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 3535 ** and all units on the internal 3536 ** bus. In addition to the internal bus initialization, 3537 ** this bit triggers the assertion of the M_RST# pin for 3538 ** initialization of registered DIMMs. When set: 3539 ** When operating in the conventional PCI mode: 3540 ** �E All current PCI transactions being mastered by the ATU completes, 3541 ** and the ATU master interfaces 3542 ** proceeds to an idle state. No additional transactions is mastered by these units 3543 ** until the internal bus reset is complete. 3544 ** �E All current transactions being slaved by the ATU on either the PCI bus 3545 ** or the internal bus 3546 ** completes, and the ATU target interfaces proceeds to an idle state. 3547 ** All future slave transactions master aborts, 3548 ** with the exception of the completion cycle for the transaction that set the Reset 3549 ** Internal Bus bit in the PCSR. 3550 ** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 3551 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 3552 ** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 3553 ** Internal Bus clocks. 3554 ** �E The 80331 hardware clears this bit after the reset operation completes. 3555 ** When operating in the PCI-X mode: 3556 ** The ATU hardware responds the same as in Conventional PCI-X mode. 3557 ** However, this may create a problem in PCI-X mode for split requests in 3558 ** that there may still be an outstanding split completion that the 3559 ** ATU is either waiting to receive (Outbound Request) or initiate 3560 ** (Inbound Read Request). For a cleaner 3561 ** internal bus reset, host software can take the following steps prior 3562 ** to asserting Reset Internal bus: 3563 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 3564 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 3565 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 3566 ** queue busy bits to be clear. 3567 ** 3. Set the Reset Internal Bus bit 3568 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 3569 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split 3570 ** completion transactions. 3571 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 3572 ** guaranteed that any prior configuration cycles have properly completed since there is only a one 3573 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 3574 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 3575 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the 3576 ** Bus Master Indicator signal P_BMI used 3577 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 3578 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 3579 ** 03 Varies with external state of PRIVDEV during 3580 ** P_RST# 3581 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 3582 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 3583 ** 0=Private Device control Disabled - SISR register bits default to zero 3584 ** 1=Private Device control Enabled - SISR register bits default to one 3585 ** 02 Varies with external state of RETRY during P_RST# 3586 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 3587 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 3588 ** configuration cycles. 3589 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 3590 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 3591 ** low, the bit is cleared. 3592 ** 01 Varies with external state of CORE_RST# during P_RST# 3593 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 3594 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 3595 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 3596 ** XScale core reset. 3597 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 3598 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 3599 ** high, the bit is clear. 3600 ** 00 Varies with external state of PRIVMEM during P_RST# 3601 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 3602 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 3603 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero 3604 ** 1=Private Memory control Enabled - SDER register bits 2 default to one 3605 *********************************************************************************** 3606 */ 3607 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 3608 /* 3609 *********************************************************************************** 3610 ** ATU Interrupt Status Register - ATUISR 3611 ** 3612 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 3613 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 3614 ** of the 80331. All bits in this register are Read/Clear. 3615 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 3616 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 3617 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 3618 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 3619 ** register. 3620 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 3621 ** ----------------------------------------------------------------- 3622 ** Bit Default Description 3623 ** 31:18 0000H Reserved 3624 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 3625 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 3626 ** this bit results in the assertion of the ATU Configure Register Write Interrupt. 3627 ** 16 0 2 Reserved 3628 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 3629 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 3630 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 3631 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 3632 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 3633 ** Configure Register Write Interrupt. 3634 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 3635 ** Message on the PCI Bus with the Split Completion Error attribute bit set. 3636 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3637 ** Message from the PCI Bus with the Split Completion Error attribute bit set. 3638 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 3639 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 3640 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 3641 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 3642 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 3643 ** register��s Parity Error Response bit is cleared. Set under the following conditions: 3644 ** �E Write Data Parity Error when the ATU is a target (inbound write). 3645 ** �E Read Data Parity Error when the ATU is an initiator (outbound read). 3646 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 3647 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 3648 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 3649 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 3650 ** register bits 3:0. 3651 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 3652 ** of the ATU Configure Register Write Interrupt. 3653 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 3654 ** 06:05 00 2 Reserved. 3655 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 3656 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 3657 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 3658 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 3659 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 3660 ** conditions: 3661 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 3662 ** �E And the ATU acted as the requester for the operation in which the error occurred. 3663 ** �E And the ATUCMD register��s Parity Error Response bit is set 3664 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 3665 ** �E And the ATUCMD register��s Parity Error Response bit is set 3666 *********************************************************************************** 3667 */ 3668 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 3669 /* 3670 *********************************************************************************** 3671 ** ATU Interrupt Mask Register - ATUIMR 3672 ** 3673 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 3674 ** generated by the ATU. 3675 ** ----------------------------------------------------------------- 3676 ** Bit Default Description 3677 ** 31:15 0 0000H Reserved 3678 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 3679 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 3680 ** 0=Not Masked 3681 ** 1=Masked 3682 ** 13 0 2 Reserved 3683 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 3684 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 3685 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 3686 ** 0=Not Masked 3687 ** 1=Masked 3688 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 3689 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 3690 ** IABAR1 register or the IAUBAR1 register. 3691 ** 0=Not Masked 3692 ** 1=Masked 3693 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 3694 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 3695 ** 0=Not Masked 3696 ** 1=Masked 3697 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 3698 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 3699 ** PCIXSR being set. 3700 ** 0=Not Masked 3701 ** 1=Masked 3702 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 3703 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 3704 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 3705 ** 0=Not Masked 3706 ** 1=Masked 3707 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 3708 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 3709 ** 0=Not Masked 3710 ** 1=Masked 3711 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 3712 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 3713 ** 0=Not Masked 3714 ** 1=Masked 3715 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 3716 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 3717 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 3718 ** 0=Not Masked 3719 ** 1=Masked 3720 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 3721 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 3722 ** 0=Not Masked 3723 ** 1=Masked 3724 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 3725 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 3726 ** 0=Not Masked 3727 ** 1=Masked 3728 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 3729 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 3730 ** 0=Not Masked 3731 ** 1=Masked 3732 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 3733 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 3734 ** inbound write transaction. 3735 ** 0=SERR# Not Asserted due to error 3736 ** 1=SERR# Asserted due to error 3737 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 3738 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 3739 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is 3740 ** actually requested from the inbound read queue. 3741 ** 0=Disconnect with data 3742 ** (the data being up to 64 bits of 1��s) 3743 ** 1=Target Abort 3744 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 3745 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 3746 ** independent of the setting of this bit. 3747 *********************************************************************************** 3748 */ 3749 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 3750 /* 3751 *********************************************************************************** 3752 ** Inbound ATU Base Address Register 3 - IABAR3 3753 ** 3754 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 3755 ** of memory addresses where the inbound translation window 3 begins. 3756 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 3757 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 3758 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 3759 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 3760 ** Note: 3761 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 3762 ** IABAR3 is not configured by the host during normal system initialization. 3763 ** Warning: 3764 ** When a non-zero value is not written to IALR3, 3765 ** the user should not set either the Prefetchable Indicator 3766 ** or the Type Indicator for 64 bit addressability. 3767 ** This is the default for IABAR3. 3768 ** Assuming a non-zero value is written to IALR3, 3769 ** the user may set the Prefetchable Indicator 3770 ** or the Type Indicator: 3771 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 3772 ** when the Prefetchable Indicator is not set, 3773 ** the user should also leave the Type Indicator set for 32 bit addressability. 3774 ** This is the default for IABAR3. 3775 ** b. when the Prefetchable Indicator is set, 3776 ** the user should also set the Type Indicator for 64 bit addressability. 3777 ** ----------------------------------------------------------------- 3778 ** Bit Default Description 3779 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location 3780 ** the translation function is to respond to when addressed from the PCI bus. 3781 ** 11:04 00H Reserved. 3782 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 3783 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 3784 ** 00 - Memory Window is locatable anywhere in 32 bit address space 3785 ** 10 - Memory Window is locatable anywhere in 64 bit address space 3786 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3787 ** The ATU does not occupy I/O space, 3788 ** thus this bit must be zero. 3789 *********************************************************************************** 3790 */ 3791 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 3792 /* 3793 *********************************************************************************** 3794 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3 3795 ** 3796 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3797 ** Together with the Translation Base Address this register defines the actual location 3798 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3799 ** The programmed value within the base address register must comply with the PCI programming 3800 ** requirements for address alignment. 3801 ** Note: 3802 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 3803 ** the IAUBAR3 register attributes are read-only. 3804 ** This is the default for IABAR3. 3805 ** ----------------------------------------------------------------- 3806 ** Bit Default Description 3807 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 3808 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 3809 *********************************************************************************** 3810 */ 3811 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 3812 /* 3813 *********************************************************************************** 3814 ** Inbound ATU Limit Register 3 - IALR3 3815 ** 3816 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3817 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3818 ** PCI addresses to internal bus addresses. 3819 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3820 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3821 ** register provides the block size requirements for the base address register. The remaining registers 3822 ** used for performing address translation are discussed in Section 3.2.1.1. 3823 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3824 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3825 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3826 ** Specification, Revision 2.3 for additional information on programming base address registers. 3827 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3828 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3829 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3830 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3831 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3832 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3833 ** register. 3834 ** ----------------------------------------------------------------- 3835 ** Bit Default Description 3836 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3837 ** for the ATUs memory window 3. 3838 ** 11:00 000H Reserved 3839 *********************************************************************************** 3840 */ 3841 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3842 /* 3843 *********************************************************************************** 3844 ** Inbound ATU Translate Value Register 3 - IATVR3 3845 ** 3846 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3847 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3848 ** inbound ATU address translation. 3849 ** ----------------------------------------------------------------- 3850 ** Bit Default Description 3851 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3852 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3853 ** access the internal 80331 memory-mapped registers. 3854 ** 11:00 000H Reserved 3855 *********************************************************************************** 3856 */ 3857 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3858 /* 3859 *********************************************************************************** 3860 ** Outbound Configuration Cycle Address Register - OCCAR 3861 ** 3862 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3863 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3864 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3865 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3866 ** PCI bus. 3867 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3868 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3869 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3870 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3871 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3872 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3873 ** ----------------------------------------------------------------- 3874 ** Bit Default Description 3875 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3876 ** configuration read or write cycle. 3877 *********************************************************************************** 3878 */ 3879 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3880 /* 3881 *********************************************************************************** 3882 ** Outbound Configuration Cycle Data Register - OCCDR 3883 ** 3884 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 3885 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 3886 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to 3887 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 3888 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 3889 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 3890 ** actually entered into the data register (which does not physically exist). 3891 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 3892 ** within the ATU configuration space. 3893 ** ----------------------------------------------------------------- 3894 ** Bit Default Description 3895 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 3896 ** or write cycle. 3897 *********************************************************************************** 3898 */ 3899 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 3900 /* 3901 *********************************************************************************** 3902 ** VPD Capability Identifier Register - VPD_CAPID 3903 ** 3904 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3905 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3906 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 3907 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 3908 ** ----------------------------------------------------------------- 3909 ** Bit Default Description 3910 ** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability 3911 ** Headers as being the VPD capability registers. 3912 *********************************************************************************** 3913 */ 3914 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 3915 /* 3916 *********************************************************************************** 3917 ** VPD Next Item Pointer Register - VPD_NXTP 3918 ** 3919 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3920 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3921 ** For the 80331, this the final capability list, and hence, this register is set to 00H. 3922 ** ----------------------------------------------------------------- 3923 ** Bit Default Description 3924 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3925 ** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 3926 ** extended capabilities in the 80331, the register is set to 00H. 3927 *********************************************************************************** 3928 */ 3929 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 3930 /* 3931 *********************************************************************************** 3932 ** VPD Address Register - VPD_AR 3933 ** 3934 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 3935 ** accessed. The register is read/write and the initial value at power-up is indeterminate. 3936 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 3937 ** the Flag setting to determine whether the configuration write was intended to initiate a read or 3938 ** write of the VPD through the VPD Data Register. 3939 ** ----------------------------------------------------------------- 3940 ** Bit Default Description 3941 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 3942 ** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 3943 ** how the 80331 handles the data transfer. 3944 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 3945 ** Vital Product Data from the VPD storage component. 3946 *********************************************************************************** 3947 */ 3948 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 3949 /* 3950 *********************************************************************************** 3951 ** VPD Data Register - VPD_DR 3952 ** 3953 ** This register is used to transfer data between the 80331 and the VPD storage component. 3954 ** ----------------------------------------------------------------- 3955 ** Bit Default Description 3956 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 3957 *********************************************************************************** 3958 */ 3959 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 3960 /* 3961 *********************************************************************************** 3962 ** Power Management Capability Identifier Register -PM_CAPID 3963 ** 3964 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3965 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3966 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 3967 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 3968 ** Interface Specification, Revision 1.1. 3969 ** ----------------------------------------------------------------- 3970 ** Bit Default Description 3971 ** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability 3972 ** Headers as being the PCI Power Management Registers. 3973 *********************************************************************************** 3974 */ 3975 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 3976 /* 3977 *********************************************************************************** 3978 ** Power Management Next Item Pointer Register - PM_NXTP 3979 ** 3980 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3981 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3982 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 3983 ** ----------------------------------------------------------------- 3984 ** Bit Default Description 3985 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3986 ** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 3987 *********************************************************************************** 3988 */ 3989 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 3990 /* 3991 *********************************************************************************** 3992 ** Power Management Capabilities Register - PM_CAP 3993 ** 3994 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 3995 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 3996 ** information on the capabilities of the ATU function related to power management. 3997 ** ----------------------------------------------------------------- 3998 ** Bit Default Description 3999 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 4000 ** is not supported by the 80331. 4001 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 4002 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 4003 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 4004 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 4005 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 4006 ** following the transition to the D0 uninitialized state. 4007 ** 4 0 2 Reserved. 4008 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 4009 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 4010 ** Interface Specification, Revision 1.1 4011 *********************************************************************************** 4012 */ 4013 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 4014 /* 4015 *********************************************************************************** 4016 ** Power Management Control/Status Register - PM_CSR 4017 ** 4018 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 4019 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 4020 ** interface for the power management extended capability. 4021 ** ----------------------------------------------------------------- 4022 ** Bit Default Description 4023 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 4024 ** supported by the 80331. 4025 ** 14:9 00H Reserved 4026 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 4027 ** generation from any power state. 4028 ** 7:2 000000 2 Reserved 4029 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 4030 ** of a function and to set the function into a new power state. The definition of the values is: 4031 ** 00 2 - D0 4032 ** 01 2 - D1 4033 ** 10 2 - D2 (Unsupported) 4034 ** 11 2 - D3 hot 4035 ** The 80331 supports only the D0 and D3 hot states. 4036 ** 4037 *********************************************************************************** 4038 */ 4039 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 4040 /* 4041 *********************************************************************************** 4042 ** PCI-X Capability Identifier Register - PX_CAPID 4043 ** 4044 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 4045 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 4046 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 4047 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 4048 ** ----------------------------------------------------------------- 4049 ** Bit Default Description 4050 ** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability 4051 ** Headers as being the PCI-X capability registers. 4052 *********************************************************************************** 4053 */ 4054 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 4055 /* 4056 *********************************************************************************** 4057 ** PCI-X Next Item Pointer Register - PX_NXTP 4058 ** 4059 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 4060 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 4061 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 4062 ** to 00H. 4063 ** However, this register may be written to B8H prior to host configuration to include the VPD 4064 ** capability located at off-set B8H. 4065 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 4066 ** produce unpredictable system behavior. 4067 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be 4068 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 4069 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 4070 ** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 4071 ** PCSR�� on page 253 for more details on the 80331 initialization modes. 4072 ** ----------------------------------------------------------------- 4073 ** Bit Default Description 4074 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 4075 ** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 4076 ** extended capabilities in the 80331, the register is set to 00H. 4077 ** However, this field may be written prior to host configuration with B8H to extend the list to include the 4078 ** VPD extended capabilities header. 4079 *********************************************************************************** 4080 */ 4081 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 4082 /* 4083 *********************************************************************************** 4084 ** PCI-X Command Register - PX_CMD 4085 ** 4086 ** This register controls various modes and features of ATU and Message Unit when operating in the 4087 ** PCI-X mode. 4088 ** ----------------------------------------------------------------- 4089 ** Bit Default Description 4090 ** 15:7 000000000 2 Reserved. 4091 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 4092 ** the device is permitted to have outstanding at one time. 4093 ** Register Maximum Outstanding 4094 ** 0 1 4095 ** 1 2 4096 ** 2 3 4097 ** 3 4 4098 ** 4 8 4099 ** 5 12 4100 ** 6 16 4101 ** 7 32 4102 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 4103 ** initiating a Sequence with one of the burst memory read commands. 4104 ** Register Maximum Byte Count 4105 ** 0 512 4106 ** 1 1024 4107 ** 2 2048 4108 ** 3 4096 4109 ** 1 0 2 4110 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 4111 ** of Transactions. 4112 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 4113 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 4114 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 4115 *********************************************************************************** 4116 */ 4117 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 4118 /* 4119 *********************************************************************************** 4120 ** PCI-X Status Register - PX_SR 4121 ** 4122 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 4123 ** Unit when operating in the PCI-X mode. 4124 ** ----------------------------------------------------------------- 4125 ** Bit Default Description 4126 ** 31:30 00 2 Reserved 4127 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 4128 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 4129 ** writes a 1 to this location. 4130 ** 0=no Split Completion error message received. 4131 ** 1=a Split Completion error message has been received. 4132 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 4133 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 4134 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 4135 ** 1 16 512 (Default) 4136 ** 2 32 1024 4137 ** 2 32 2048 4138 ** 2 32 4096 4139 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 4140 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 4141 ** to 1024 bytes. 4142 ** 20 1 2 80331 is a complex device. 4143 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 4144 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 4145 ** 0=no unexpected Split Completion has been received. 4146 ** 1=an unexpected Split Completion has been received. 4147 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 4148 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 4149 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 4150 ** location. 4151 ** 0=no Split Completion has been discarded. 4152 ** 1=a Split Completion has been discarded. 4153 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 4154 ** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 4155 ** 17 1 2 80331 is a 133 MHz capable device. 4156 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 4157 ** therefore this bit is always set. 4158 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 4159 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 4160 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled 4161 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 4162 ** 0=The bus is 32 bits wide. 4163 ** 1=The bus is 64 bits wide. 4164 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 4165 ** segment for the device containing this function. The function uses this number as part of its Requester 4166 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 4167 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 4168 ** of the attribute phase of the Configuration Write, regardless of which register in the function is 4169 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 4170 ** the following are true: 4171 ** 1. The transaction uses a Configuration Write command. 4172 ** 2. IDSEL is asserted during the address phase. 4173 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4174 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 4175 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 4176 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 4177 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection 4178 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 4179 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 4180 ** time the function is addressed by a Configuration Write transaction, the device must update this register 4181 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 4182 ** register in the function is addressed by the transaction. The function is addressed by a Configuration 4183 ** Write transaction when all of the following are true: 4184 ** 1. The transaction uses a Configuration Write command. 4185 ** 2. IDSEL is asserted during the address phase. 4186 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4187 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 4188 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 4189 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 4190 ** configuration transaction to which this function responds. The function uses this number as part of its 4191 ** Requester ID and Completer ID. 4192 ** 4193 ************************************************************************** 4194 */ 4195 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 4196 4197 /* 4198 ************************************************************************** 4199 ** Inbound Read Transaction 4200 ** ======================================================================== 4201 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 4202 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through 4203 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 4204 ** (IRQ). 4205 ** When operating in the conventional PCI mode, all inbound read transactions are processed as 4206 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 4207 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 4208 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 4209 ** an inbound read transaction on the PCI bus is summarized in the following statements: 4210 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 4211 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 4212 ** Address Register during DACs) and Inbound Limit Register. 4213 ** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 4214 ** information from a previous delayed read, the current transaction information is compared to 4215 ** the previous transaction information (based on the setting of the DRC Alias bit in 4216 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 4217 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 4218 ** match and the data is not available, a Retry is signaled with no other action taken. When there 4219 ** is not a match and when the ITQ has less than eight entries, capture the transaction 4220 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and 4221 ** when the ITQ is full, then signal a Retry with no other action taken. 4222 ** �X When an address parity error is detected, the address parity response defined in 4223 ** Section 3.7 is used. 4224 ** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 4225 ** the IRQ, it continues until one of the following is true: 4226 ** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 4227 ** data is flushed. 4228 ** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 4229 ** Target Abort is never entered into the IRQ, and therefore is never returned. 4230 ** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 4231 ** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 4232 ** the initiator on the last data word available. 4233 ** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 4234 ** command are latched into the available ITQ and a Split Response Termination is signalled to 4235 ** the initiator. 4236 ** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 4237 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target 4238 ** before returning read data by generating the split completion transaction on the PCI-X bus. 4239 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 4240 ** transfer by returning data in 1024 byte aligned chunks. 4241 ** �E When operating in the PCI-X mode, once a split completion transaction has started, it 4242 ** continues until one of the following is true: 4243 ** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 4244 ** ADB (when the requester is a bridge) 4245 ** �X The byte count is satisfied. 4246 ** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 4247 ** Message (message class=2h - completer error, and message index=81h - target abort) to 4248 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4249 ** Refer to Section 3.7.1. 4250 ** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 4251 ** Message (message class=2h - completer error, and message index=80h - Master abort) to 4252 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4253 ** Refer to Section 3.7.1 4254 ** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 4255 ** bus, the ATU PCI slave interface waits with no premature disconnects. 4256 ** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 4257 ** taken by the target interface. Refer to Section 3.7.2.5. 4258 ** �E When operating in the conventional PCI mode, when the read on the internal bus is 4259 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 4260 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 4261 ** target abort is used, when clear, a disconnect is used. 4262 ** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 4263 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 4264 ** a Split Completion Message (message class=2h - completer error, and message index=81h - 4265 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU 4266 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 4267 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 4268 ** transaction is flushed. Refer to Section 3.7.1. 4269 ** �E When operating in the conventional PCI mode, when the transaction on the internal bus 4270 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the 4271 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 4272 ** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 4273 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer 4274 ** error, and message index=80h - internal bus master abort) to inform the requester about the 4275 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 4276 ** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 4277 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 4278 ** prevents it from accepting the completion it requested. In this case, since the Split Request 4279 ** addresses a location that has no read side effects, the completer must discard the Split 4280 ** Completion and take no further action. 4281 ** The data flow for an inbound read transaction on the internal bus is summarized in the following 4282 ** statements: 4283 ** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 4284 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 4285 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 4286 ** always uses conventional PCI ordering rules. 4287 ** �E Once the internal bus is granted, the internal bus master interface drives the translated address 4288 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 4289 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded 4290 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 4291 ** master has been delivered the target abort). 4292 ** �E Once the translated address is on the bus and the transaction has been accepted, the internal 4293 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 4294 ** received by the IRQ until one of the following is true: 4295 ** �X The full byte count requested by the ATU read request is received. The ATU internal bus 4296 ** initiator interface performs a initiator completion in this case. 4297 ** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 4298 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 4299 ** informed. 4300 ** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 4301 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 4302 ** Completion Message (message class=2h - completer error, and message index=81h - 4303 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The 4304 ** ITQ for this transaction is flushed. 4305 ** �X When operating in the conventional PCI mode, a single data phase disconnection is 4306 ** received from the internal bus target. When the data has not been received up to the next 4307 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 4308 ** When not, the bus returns to idle. 4309 ** �X When operating in the PCI-X mode, a single data phase disconnection is received from 4310 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 4311 ** obtain remaining data. 4312 ** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 4313 ** from the internal bus target. The bus returns to idle. 4314 ** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 4315 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 4316 ** remaining data. 4317 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 4318 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 4319 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 4320 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 4321 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 4322 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 4323 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 4324 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 4325 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 4326 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 4327 ** commands did not match, only the address. 4328 ************************************************************************** 4329 */ 4330 /* 4331 ************************************************************************** 4332 ** Inbound Write Transaction 4333 **======================================================================== 4334 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 4335 ** memory or a 80331 memory-mapped register. 4336 ** Data flow for an inbound write transaction on the PCI bus is summarized as: 4337 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 4338 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 4339 ** Base Address Register during DACs) and Inbound Limit Register. 4340 ** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 4341 ** available, the address is captured and the first data phase is accepted. 4342 ** �E The PCI interface continues to accept write data until one of the following is true: 4343 ** �X The initiator performs a disconnect. 4344 ** �X The transaction crosses a buffer boundary. 4345 ** �E When an address parity error is detected during the address phase of the transaction, the 4346 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 4347 ** parity error response. 4348 ** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 4349 ** parity error mechanism described in Section 3.7.1 is used. 4350 ** �E When a data parity error is detected while accepting data, the slave interface sets the 4351 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 4352 ** for details of the inbound write data parity error response. 4353 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 4354 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 4355 ** interface becomes aware of the inbound write. When there are additional write transactions ahead 4356 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 4357 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 4358 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 4359 ** interface, when operating in the PCI mode. 4360 ** In the PCI-X mode memory writes are always executed as immediate transactions, while 4361 ** configuration write transactions are processed as split transactions. The ATU generates a Split 4362 ** Completion Message, (with Message class=0h - Write Completion Class and Message index = 4363 ** 00h - Write Completion Message) once a configuration write is successfully executed. 4364 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 4365 ** The ATU handles such transactions as independent transactions. 4366 ** Data flow for the inbound write transaction on the internal bus is summarized as: 4367 ** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 4368 ** with associated data in the IWQ. 4369 ** �E When the internal bus is granted, the internal bus master interface initiates the write 4370 ** transaction by driving the translated address onto the internal bus. For details on inbound 4371 ** address translation. 4372 ** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 4373 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 4374 ** interface. 4375 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 4376 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 4377 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 4378 ** from the IWQ to the internal bus when data is available and the internal bus interface retains 4379 ** internal bus ownership. 4380 ** �E The internal bus interface stops transferring data from the current transaction to the internal 4381 ** bus when one of the following conditions becomes true: 4382 ** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 4383 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 4384 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 4385 ** complete the delivery of remaining data using the same sequence ID but with the 4386 ** modified starting address and byte count. 4387 ** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 4388 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 4389 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 4390 ** complete the delivery of remaining data using the same sequence ID but with the 4391 ** modified starting address and byte count. 4392 ** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 4393 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 4394 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 4395 ** bus to complete the delivery of remaining data using the same sequence ID but with the 4396 ** modified starting address and byte count. 4397 ** �X The data from the current transaction has completed (satisfaction of byte count). An 4398 ** initiator termination is performed and the bus returns to idle. 4399 ** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 4400 ** Data is flushed from the IWQ. 4401 ***************************************************************** 4402 */ 4403 4404 4405 4406 /* 4407 ************************************************************************** 4408 ** Inbound Read Completions Data Parity Errors 4409 **======================================================================== 4410 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4411 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 4412 ** completion transaction, the ATU attempts to complete the transaction normally and no further 4413 ** action is taken. 4414 ************************************************************************** 4415 */ 4416 4417 /* 4418 ************************************************************************** 4419 ** Inbound Configuration Write Completion Message Data Parity Errors 4420 **======================================================================== 4421 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4422 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 4423 ** assertion during the split completion transaction, the ATU attempts to complete the transaction 4424 ** normally and no further action is taken. 4425 ************************************************************************** 4426 */ 4427 4428 /* 4429 ************************************************************************** 4430 ** Inbound Read Request Data Parity Errors 4431 **===================== Immediate Data Transfer ========================== 4432 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 4433 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 4434 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 4435 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 4436 ** required and no error bits are set. 4437 **=====================Split Response Termination========================= 4438 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4439 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may 4440 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 4441 ** action is required and no error bits are set. 4442 ************************************************************************** 4443 */ 4444 4445 /* 4446 ************************************************************************** 4447 ** Inbound Write Request Data Parity Errors 4448 **======================================================================== 4449 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4450 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on 4451 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 4452 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with 4453 ** the given constraints are taken by the ATU: 4454 ** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 4455 ** following the data phase in which the data parity error is detected on the bus. This is only 4456 ** done when the Parity Error Response bit in the ATUCMD is set. 4457 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4458 ** actions is taken: 4459 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4460 ** Detected Parity Error bit in the ATUISR. When set, no action. 4461 *************************************************************************** 4462 */ 4463 4464 4465 /* 4466 *************************************************************************** 4467 ** Inbound Configuration Write Request 4468 ** ===================================================================== 4469 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4470 ** =============================================== 4471 ** Conventional PCI Mode 4472 ** =============================================== 4473 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 4474 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 4475 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following 4476 ** parts of the transactions: 4477 ** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 4478 ** address/command and data for delayed delivery to the internal configuration register. 4479 ** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 4480 ** of the operation back to the original master. 4481 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 4482 ** inbound transactions during Delayed Write Request cycles with the given constraints: 4483 ** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 4484 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 4485 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 4486 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 4487 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 4488 ** forwarded to the internal bus. PERR# is not asserted. 4489 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4490 ** actions is taken: 4491 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4492 ** Detected Parity Error bit in the ATUISR. When set, no action. 4493 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI 4494 ** bus and the ATU returns the status from the internal bus, completing the transaction. 4495 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 4496 ** therefore does not agree with the status being returned from the internal bus (i.e. status being 4497 ** returned is normal completion) the ATU performs the following actions with the given constraints: 4498 ** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 4499 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 4500 ** the IDWQ remains since the data of retried command did not match the data within the queue. 4501 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4502 ** actions is taken: 4503 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4504 ** Detected Parity Error bit in the ATUISR. When set, no action. 4505 ** =================================================== 4506 ** PCI-X Mode 4507 ** =================================================== 4508 ** Data parity errors occurring during configuration write operations received by the ATU may cause 4509 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 4510 ** occurs, the ATU accepts the write data and complete with a Split Response Termination. 4511 ** Specifically, the following actions with the given constraints are then taken by the ATU: 4512 ** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 4513 ** cycles following the Split Response Termination in which the data parity error is detected on 4514 ** the bus. When the ATU asserts PERR#, additional actions is taken: 4515 ** �X A Split Write Data Parity Error message (with message class=2h - completer error and 4516 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 4517 ** that addresses the requester of the configuration write. 4518 ** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 4519 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 4520 ** action. 4521 ** �X The Split Write Request is not enqueued and forwarded to the internal bus. 4522 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4523 ** actions is taken: 4524 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4525 ** Detected Parity Error bit in the ATUISR. When set, no action. 4526 ** 4527 *************************************************************************** 4528 */ 4529 4530 /* 4531 *************************************************************************** 4532 ** Split Completion Messages 4533 ** ======================================================================= 4534 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4535 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 4536 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 4537 ** ATU accepts the data and complete normally. Specifically, the following actions with the given 4538 ** constraints are taken by the ATU: 4539 ** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 4540 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 4541 ** is set. When the ATU asserts PERR#, additional actions is taken: 4542 ** �X The Master Parity Error bit in the ATUSR is set. 4543 ** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 4544 ** PCI Master Parity Error bit in the ATUISR. When set, no action. 4545 ** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 4546 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 4547 ** When the ATU asserts SERR#, additional actions is taken: 4548 ** Set the SERR# Asserted bit in the ATUSR. 4549 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 4550 ** SERR# Asserted bit in the ATUISR. When set, no action. 4551 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 4552 ** SERR# Detected bit in the ATUISR. When clear, no action. 4553 ** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 4554 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 4555 ** When the ATU sets this bit, additional actions is taken: 4556 ** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 4557 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 4558 ** When set, no action. 4559 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4560 ** actions is taken: 4561 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4562 ** Detected Parity Error bit in the ATUISR. When set, no action. 4563 ** �E The transaction associated with the Split Completion Message is discarded. 4564 ** �E When the discarded transaction was a read, a completion error message (with message 4565 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 4566 ** the internal bus of the 80331. 4567 ***************************************************************************** 4568 */ 4569 4570 4571 /* 4572 ****************************************************************************************************** 4573 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 4574 ** ================================================================================================== 4575 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331 4576 ** notifies the respective system when new data arrives. 4577 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 4578 ** window defined by: 4579 ** 1.Inbound ATU Base Address Register 0 (IABAR0) 4580 ** 2.Inbound ATU Limit Register 0 (IALR0) 4581 ** All of the Messaging Unit errors are reported in the same manner as ATU errors. 4582 ** Error conditions and status can be found in : 4583 ** 1.ATUSR 4584 ** 2.ATUISR 4585 **==================================================================================================== 4586 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 4587 **---------------------------------------------------------------------------------------------------- 4588 ** Message Registers 2 Inbound Optional Optional 4589 ** 2 Outbound 4590 **---------------------------------------------------------------------------------------------------- 4591 ** Doorbell Registers 1 Inbound Optional Optional 4592 ** 1 Outbound 4593 **---------------------------------------------------------------------------------------------------- 4594 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 4595 **---------------------------------------------------------------------------------------------------- 4596 ** Index Registers 1004 32-bit Memory Locations No Optional 4597 **==================================================================================================== 4598 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 4599 **==================================================================================================== 4600 ** 0000H Reserved 4601 ** 0004H Reserved 4602 ** 0008H Reserved 4603 ** 000CH Reserved 4604 **------------------------------------------------------------------------ 4605 ** 0010H Inbound Message Register 0 ] 4606 ** 0014H Inbound Message Register 1 ] 4607 ** 0018H Outbound Message Register 0 ] 4608 ** 001CH Outbound Message Register 1 ] 4 Message Registers 4609 **------------------------------------------------------------------------ 4610 ** 0020H Inbound Doorbell Register ] 4611 ** 0024H Inbound Interrupt Status Register ] 4612 ** 0028H Inbound Interrupt Mask Register ] 4613 ** 002CH Outbound Doorbell Register ] 4614 ** 0030H Outbound Interrupt Status Register ] 4615 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 4616 **------------------------------------------------------------------------ 4617 ** 0038H Reserved 4618 ** 003CH Reserved 4619 **------------------------------------------------------------------------ 4620 ** 0040H Inbound Queue Port ] 4621 ** 0044H Outbound Queue Port ] 2 Queue Ports 4622 **------------------------------------------------------------------------ 4623 ** 0048H Reserved 4624 ** 004CH Reserved 4625 **------------------------------------------------------------------------ 4626 ** 0050H ] 4627 ** : ] 4628 ** : Intel Xscale Microarchitecture Local Memory ] 4629 ** : ] 4630 ** 0FFCH ] 1004 Index Registers 4631 ******************************************************************************* 4632 */ 4633 /* 4634 ***************************************************************************** 4635 ** Theory of MU Operation 4636 ***************************************************************************** 4637 **-------------------- 4638 ** inbound_msgaddr0: 4639 ** inbound_msgaddr1: 4640 ** outbound_msgaddr0: 4641 ** outbound_msgaddr1: 4642 ** . The MU has four independent messaging mechanisms. 4643 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 4644 ** Each holds a 32-bit value and generates an interrupt when written. 4645 **-------------------- 4646 ** inbound_doorbell: 4647 ** outbound_doorbell: 4648 ** . The two Doorbell Registers support software interrupts. 4649 ** When a bit is set in a Doorbell Register, an interrupt is generated. 4650 **-------------------- 4651 ** inbound_queueport: 4652 ** outbound_queueport: 4653 ** 4654 ** 4655 ** . The Circular Queues support a message passing scheme that uses 4 circular queues. 4656 ** The 4 circular queues are implemented in 80331 local memory. 4657 ** Two queues are used for inbound messages and two are used for outbound messages. 4658 ** Interrupts may be generated when the queue is written. 4659 **-------------------- 4660 ** local_buffer 0x0050 ....0x0FFF 4661 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 4662 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 4663 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 4664 ** Each interrupt generated by the Messaging Unit can be masked. 4665 **-------------------- 4666 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 4667 ** with the exception of Multi-DWORD reads to the index registers. 4668 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 4669 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 4670 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 4671 ** and the data is returned through split completion transaction(s). 4672 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 4673 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 4674 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 4675 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 4676 **-------------------- 4677 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 4678 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 4679 ** This PCI address window is used for PCI transactions that access the 80331 local memory. 4680 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 4681 **-------------------- 4682 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 4683 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 4684 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 4685 ** The Messaging Unit reports all PCI errors in the ATU Status Register. 4686 **-------------------- 4687 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 4688 ** The register interface, message registers, doorbell registers, 4689 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 4690 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 4691 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 4692 ************************************************************************** 4693 */ 4694 /* 4695 ************************************************************************** 4696 ** Message Registers 4697 ** ============================== 4698 ** . Messages can be sent and received by the 80331 through the use of the Message Registers. 4699 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 4700 ** . Inbound messages are sent by the host processor and received by the 80331. 4701 ** Outbound messages are sent by the 80331 and received by the host processor. 4702 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 4703 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 4704 ** 4705 ** Inbound Messages: 4706 ** ----------------- 4707 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 4708 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 4709 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 4710 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 4711 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 4712 ** The interrupt is cleared when the Intel XScale core writes a value of 4713 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 4714 ** ------------------------------------------------------------------------ 4715 ** Inbound Message Register - IMRx 4716 ** 4717 ** . There are two Inbound Message Registers: IMR0 and IMR1. 4718 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 4719 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 4720 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 4721 ** ----------------------------------------------------------------- 4722 ** Bit Default Description 4723 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 4724 ** When written, an interrupt to the Intel XScale core may be generated. 4725 ************************************************************************** 4726 */ 4727 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 4728 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 4729 /* 4730 ************************************************************************** 4731 ** Outbound Message Register - OMRx 4732 ** -------------------------------- 4733 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 4734 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 4735 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 4736 ** Interrupt Mask Register. 4737 ** 4738 ** Bit Default Description 4739 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 4740 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 4741 ************************************************************************** 4742 */ 4743 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 4744 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 4745 /* 4746 ************************************************************************** 4747 ** Doorbell Registers 4748 ** ============================== 4749 ** There are two Doorbell Registers: 4750 ** Inbound Doorbell Register 4751 ** Outbound Doorbell Register 4752 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 4753 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 4754 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 4755 ** 4756 ** Inbound Doorbells: 4757 ** ------------------ 4758 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 4759 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 4760 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 4761 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 4762 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4763 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 4764 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 4765 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 4766 ** and not the values written to the Inbound Doorbell Register. 4767 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 4768 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 4769 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 4770 ** ------------------------------------------------------------------------ 4771 ** Inbound Doorbell Register - IDR 4772 ** 4773 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 4774 ** . Bit 31 is reserved for generating an Error Doorbell interrupt. 4775 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 4776 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 4777 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 4778 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 4779 ** ------------------------------------------------------------------------ 4780 ** Bit Default Description 4781 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 4782 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 4783 ** When all bits are clear, do not generate a Normal Interrupt. 4784 ************************************************************************** 4785 */ 4786 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 4787 /* 4788 ************************************************************************** 4789 ** Inbound Interrupt Status Register - IISR 4790 ** 4791 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4792 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4793 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4794 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4795 ** these two are routed to the Messaging Unit Error interrupt input. 4796 ** The generation of interrupts recorded in the Inbound Interrupt Status Register 4797 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4798 ** Some of the bits in this register are Read Only. 4799 ** For those bits, the interrupt must be cleared through another register. 4800 ** 4801 ** Bit Default Description 4802 ** 31:07 0000000H 0 2 Reserved 4803 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4804 ** when an Index Register has been written after a PCI transaction. 4805 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4806 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4807 ** An Error interrupt is generated for this condition. 4808 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4809 ** Once cleared, an interrupt does NOT be generated 4810 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4811 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4812 ** software must retain the information that the Inbound Post queue status is not empty. 4813 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4814 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4815 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4816 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4817 ** Normal Interrupt bit in the Inbound Doorbell Register is set. 4818 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4819 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4820 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4821 ************************************************************************** 4822 */ 4823 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4824 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4825 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4826 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4827 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4828 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4829 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4830 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4831 /* 4832 ************************************************************************** 4833 ** Inbound Interrupt Mask Register - IIMR 4834 ** 4835 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4836 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4837 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4838 ** They only affect the generation of the Intel XScale core interrupt. 4839 ** ------------------------------------------------------------------------ 4840 ** Bit Default Description 4841 ** 31:07 000000H 0 2 Reserved 4842 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4843 ** when an Index Register has been written after a PCI transaction. 4844 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4845 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4846 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4847 ** by the MU hardware when the Inbound Post Queue has been written. 4848 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4849 ** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4850 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4851 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4852 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4853 ** Interrupt generated by a write to the Inbound Message 1 Register. 4854 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4855 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4856 ************************************************************************** 4857 */ 4858 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4859 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4860 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4861 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4862 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4863 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4864 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4865 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4866 /* 4867 ************************************************************************** 4868 ** Outbound Doorbell Register - ODR 4869 ** 4870 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4871 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4872 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4873 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4874 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4875 ** be cleared by an external PCI agent. 4876 ** ---------------------------------------------------------------------- 4877 ** Bit Default Description 4878 ** 31 0 2 Reserved 4879 ** 30 0 2 Reserved. 4880 ** 29 0 2 Reserved 4881 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4882 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4883 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4884 ** When this bit is cleared, the P_INTC# interrupt output 4885 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4886 ** signal is deasserted. 4887 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 4888 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4889 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 4890 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 4891 ** signal is deasserted. 4892 ************************************************************************** 4893 */ 4894 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 4895 /* 4896 ************************************************************************** 4897 ** Outbound Interrupt Status Register - OISR 4898 ** 4899 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 4900 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 4901 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 4902 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 4903 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 4904 ** register. 4905 ** ---------------------------------------------------------------------- 4906 ** Bit Default Description 4907 ** 31:05 000000H 000 2 Reserved 4908 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 4909 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 4910 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 4911 ** cleared when any prefetch data has been read from the Outbound Queue Port. 4912 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 4913 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 4914 ** Doorbell Register must all be clear. 4915 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 4916 ** written. Clearing this bit clears the interrupt. 4917 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 4918 ** written. Clearing this bit clears the interrupt. 4919 ************************************************************************** 4920 */ 4921 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 4922 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 4923 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 4924 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 4925 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 4926 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 4927 /* 4928 ************************************************************************** 4929 ** Outbound Interrupt Mask Register - OIMR 4930 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 4931 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 4932 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 4933 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 4934 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 4935 ** only affect the generation of the PCI interrupt. 4936 ** ---------------------------------------------------------------------- 4937 ** Bit Default Description 4938 ** 31:05 000000H Reserved 4939 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 4940 ** in the Outbound Doorbell Register is set. 4941 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 4942 ** the prefetch buffer is valid. 4943 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 4944 ** Doorbell Register. 4945 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 4946 ** generated by a write to the Outbound Message 1 Register. 4947 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 4948 ** generated by a write to the Outbound Message 0 Register. 4949 ************************************************************************** 4950 */ 4951 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 4952 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 4953 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 4954 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 4955 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 4956 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 4957 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 4958 /* 4959 ************************************************************************** 4960 ** 4961 ************************************************************************** 4962 */ 4963 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 4964 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 4965 /* 4966 ************************************************************************** 4967 ** Circular Queues 4968 ** ====================================================================== 4969 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 4970 ** this case, inbound and outbound refer to the direction of the flow of posted messages. 4971 ** Inbound messages are either: 4972 ** �E posted messages by other processors for the Intel XScale core to process or 4973 ** �E free (or empty) messages that can be reused by other processors. 4974 ** Outbound messages are either: 4975 ** �E posted messages by the Intel XScale core for other processors to process or 4976 ** �E free (or empty) messages that can be reused by the Intel XScale core. 4977 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 4978 ** The four Circular Queues are used to pass messages in the following manner. 4979 ** . The two inbound queues are used to handle inbound messages 4980 ** and the two outbound queues are used to handle outbound messages. 4981 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 4982 ** The other inbound queue is designated the Post queue and it contains inbound posted messages. 4983 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 4984 ** 4985 ** ============================================================================================================= 4986 ** Circular Queue Summary 4987 ** _____________________________________________________________________________________________________________ 4988 ** | Queue Name | Purpose | Action on PCI Interface| 4989 ** |______________________|____________________________________________________________|_________________________| 4990 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 4991 ** | | waiting to be processed by the 80331 | | 4992 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 4993 ** | | available for use by other processors | | 4994 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 4995 ** | | that are being posted to the other processors | | 4996 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 4997 ** | | available for use by the 80331 | | 4998 ** |______________________|____________________________________________________________|_________________________| 4999 ** 5000 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 5001 ** queue and to receive free messages returning from the 80331. 5002 ** The host processor posts inbound messages, 5003 ** the Intel XScale core receives the posted message and when it is finished with the message, 5004 ** places it back on the inbound free queue for reuse by the host processor. 5005 ** 5006 ** The circular queues are accessed by external PCI agents through two port locations in the PCI 5007 ** address space: 5008 ** Inbound Queue Port 5009 ** and Outbound Queue Port. 5010 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 5011 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 5012 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 5013 ** does not cause the MU hardware to increment the queue pointers. 5014 ** This is treated as when the PCI transaction did not occur. 5015 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 5016 ** ====================================================================================== 5017 ** Overview of Circular Queue Operation 5018 ** ====================================================================================== 5019 ** . The data storage for the circular queues must be provided by the 80331 local memory. 5020 ** . The base address of the circular queues is contained in the Queue Base Address Register. 5021 ** Each entry in the queue is a 32-bit data value. 5022 ** . Each read from or write to the queue may access only one queue entry. 5023 ** . Multi-DWORD accesses to the circular queues are not allowed. 5024 ** Sub-DWORD accesses are promoted to DWORD accesses. 5025 ** . Each circular queue has a head pointer and a tail pointer. 5026 ** The pointers are offsets from the Queue Base Address. 5027 ** . Writes to a queue occur at the head of the queue and reads occur from the tail. 5028 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 5029 ** Which unit maintains the pointer is determined by the writer of the queue. 5030 ** More details about the pointers are given in the queue descriptions below. 5031 ** The pointers are incremented after the queue access. 5032 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 5033 ** 5034 ** Messaging Unit... 5035 ** 5036 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 5037 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 5038 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 5039 ** . All four queues must be the same size and may be contiguous. 5040 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 5041 ** The Queue size is determined by the Queue Size field in the MU Configuration Register. 5042 ** . There is one base address for all four queues. 5043 ** It is stored in the Queue Base Address Register (QBAR). 5044 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 5045 ** here shows an example of how the circular queues should be set up based on the 5046 ** Intelligent I/O (I 2 O) Architecture Specification. 5047 ** Other ordering of the circular queues is possible. 5048 ** 5049 ** Queue Starting Address 5050 ** Inbound Free Queue QBAR 5051 ** Inbound Post Queue QBAR + Queue Size 5052 ** Outbound Post Queue QBAR + 2 * Queue Size 5053 ** Outbound Free Queue QBAR + 3 * Queue Size 5054 ** =================================================================================== 5055 ** Inbound Post Queue 5056 ** ------------------ 5057 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 5058 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 5059 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 5060 ** For a PCI write transaction that accesses the Inbound Queue Port, 5061 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 5062 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 5063 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 5064 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 5065 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 5066 ** The interrupt can be masked by the Inbound Interrupt Mask Register. 5067 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 5068 ** that the full condition is recognized by the core processor. 5069 ** In addition, to guarantee that the queue does not get overwritten, 5070 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 5071 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 5072 ** Only a new message posting the in the inbound queue generates a new interrupt. 5073 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 5074 ** software must retain the information that the Inbound Post queue status. 5075 ** From the time that the PCI write transaction is received until the data is written 5076 ** in local memory and the Inbound Post Head Pointer Register is incremented, 5077 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 5078 ** The Intel XScale core may read messages from the Inbound Post Queue 5079 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 5080 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 5081 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 5082 ** the hardware retries any PCI writes until a slot in the queue becomes available. 5083 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 5084 ** =================================================================================== 5085 ** Inbound Free Queue 5086 ** ------------------ 5087 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 5088 ** This queue is read from the queue tail by external PCI agents. 5089 ** It is written to the queue head by the Intel XScale core. 5090 ** The tail pointer is maintained by the MU hardware. 5091 ** The head pointer is maintained by the Intel XScale core. 5092 ** For a PCI read transaction that accesses the Inbound Queue Port, 5093 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 5094 ** When the queue is not empty (head and tail pointers are not equal) 5095 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 5096 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 5097 ** the value of -1 (FFFF.FFFFH) is returned. 5098 ** When the queue was not empty and the MU succeeded in returning the data at the tail, 5099 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 5100 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 5101 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 5102 ** When the PCI read access occurs, the data is read directly from the prefetch register. 5103 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 5104 ** when the head and tail pointers are equal and the queue is empty. 5105 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 5106 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 5107 ** and the Inbound Free Head Pointer Register is written. 5108 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 5109 ** A prefetch must appear atomic from the perspective of the external PCI agent. 5110 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 5111 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 5112 ** local memory location pointed to by the Inbound Free Head Pointer Register. 5113 ** The processor must then increment the Inbound Free Head Pointer Register. 5114 ** ================================================================================== 5115 ** Outbound Post Queue 5116 ** ------------------- 5117 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 5118 ** core for other processors to process. This queue is read from the queue tail by external PCI agents. 5119 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 5120 ** MU hardware. The head pointer is maintained by the Intel XScale core. 5121 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 5122 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 5123 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 5124 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail 5125 ** pointers are equal and the head pointer was last updated by hardware), the value of -1 5126 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 5127 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 5128 ** Register. 5129 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 5130 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 5131 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 5132 ** occurs, the data is read directly from the prefetch register. 5133 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 5134 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 5135 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 5136 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 5137 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 5138 ** Pointer Register when it adds messages to the queue. 5139 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 5140 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 5141 ** until the prefetch is completed. 5142 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 5143 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 5144 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 5145 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 5146 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 5147 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 5148 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then 5149 ** increment the Outbound Post Head Pointer Register. 5150 ** ================================================== 5151 ** Outbound Free Queue 5152 ** ----------------------- 5153 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel 5154 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 5155 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 5156 ** XScale core. The head pointer is maintained by the MU hardware. 5157 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 5158 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the 5159 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 5160 ** Head Pointer Register. 5161 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 5162 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 5163 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 5164 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 5165 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 5166 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 5167 ** core processor. 5168 ** From the time that a PCI write transaction is received until the data is written in local memory and 5169 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 5170 ** access the Outbound Free Queue Port is signalled a retry. 5171 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 5172 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 5173 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 5174 ** the hardware must retry any PCI writes until a slot in the queue becomes available. 5175 ** 5176 ** ================================================================================== 5177 ** Circular Queue Summary 5178 ** ---------------------- 5179 ** ________________________________________________________________________________________________________________________________________________ 5180 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 5181 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5182 ** |Inbound Post | Inbound Queue | | | | | 5183 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 5184 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5185 ** |Inbound Free | Inbound Queue | | | | | 5186 ** | Queue | Port | NO | NO | Intel XScale | MU hardware | 5187 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5188 ** ================================================================================== 5189 ** Circular Queue Status Summary 5190 ** ---------------------- 5191 ** ____________________________________________________________________________________________________ 5192 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 5193 ** |_____________________|________________|_____________________|_______________________________________| 5194 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 5195 ** |_____________________|________________|_____________________|_______________________________________| 5196 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 5197 ** |_____________________|________________|_____________________|_______________________________________| 5198 ************************************************************************** 5199 */ 5200 5201 /* 5202 ************************************************************************** 5203 ** Index Registers 5204 ** ======================== 5205 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 5206 ** These registers are for inbound messages only. 5207 ** The interrupt is recorded in the Inbound Interrupt Status Register. 5208 ** The storage for the Index Registers is allocated from the 80331 local memory. 5209 ** PCI write accesses to the Index Registers write the data to local memory. 5210 ** PCI read accesses to the Index Registers read the data from local memory. 5211 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 5212 ** to Inbound ATU Translate Value Register + FFFH. 5213 ** . The address of the first write access is stored in the Index Address Register. 5214 ** This register is written during the earliest write access and provides a means to determine which Index Register was written. 5215 ** Once updated by the MU, the Index Address Register is not updated until the Index Register 5216 ** Interrupt bit in the Inbound Interrupt Status Register is cleared. 5217 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 5218 ** Writes by the Intel XScale core to the local memory used by the Index Registers 5219 ** does not cause an interrupt and does not update the Index Address Register. 5220 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 5221 ************************************************************************** 5222 */ 5223 /* 5224 ************************************************************************** 5225 ** Messaging Unit Internal Bus Memory Map 5226 ** ======================================= 5227 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 5228 ** FFFF E300H reserved | 5229 ** .. .. | 5230 ** FFFF E30CH reserved | 5231 ** FFFF E310H Inbound Message Register 0 | Available through 5232 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 5233 ** FFFF E318H Outbound Message Register 0 | 5234 ** FFFF E31CH Outbound Message Register 1 | or 5235 ** FFFF E320H Inbound Doorbell Register | 5236 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 5237 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 5238 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 5239 ** FFFF E330H Outbound Interrupt Status Register | 5240 ** FFFF E334H Outbound Interrupt Mask Register | 5241 ** ______________________________________________________________________|________________________________________ 5242 ** FFFF E338H reserved | 5243 ** FFFF E33CH reserved | 5244 ** FFFF E340H reserved | 5245 ** FFFF E344H reserved | 5246 ** FFFF E348H reserved | 5247 ** FFFF E34CH reserved | 5248 ** FFFF E350H MU Configuration Register | 5249 ** FFFF E354H Queue Base Address Register | 5250 ** FFFF E358H reserved | 5251 ** FFFF E35CH reserved | must translate PCI address to 5252 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 5253 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 5254 ** FFFF E368H Inbound Post Head pointer Register | 5255 ** FFFF E36CH Inbound Post Tail Pointer Register | 5256 ** FFFF E370H Outbound Free Head Pointer Register | 5257 ** FFFF E374H Outbound Free Tail Pointer Register | 5258 ** FFFF E378H Outbound Post Head pointer Register | 5259 ** FFFF E37CH Outbound Post Tail Pointer Register | 5260 ** FFFF E380H Index Address Register | 5261 ** FFFF E384H reserved | 5262 ** .. .. | 5263 ** FFFF E3FCH reserved | 5264 ** ______________________________________________________________________|_______________________________________ 5265 ************************************************************************** 5266 */ 5267 /* 5268 ************************************************************************** 5269 ** MU Configuration Register - MUCR FFFF.E350H 5270 ** 5271 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 5272 ** . The Circular Queue Enable bit enables or disables the Circular Queues. 5273 ** The Circular Queues are disabled at reset to allow the software to initialize the head 5274 ** and tail pointer registers before any PCI accesses to the Queue Ports. 5275 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 5276 ** ------------------------------------------------------------------------ 5277 ** Bit Default Description 5278 ** 31:06 000000H 00 2 Reserved 5279 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 5280 ** All four queues are the same size. 5281 ** �E 00001 2 - 4K Entries (16 Kbytes) 5282 ** �E 00010 2 - 8K Entries (32 Kbytes) 5283 ** �E 00100 2 - 16K Entries (64 Kbytes) 5284 ** �E 01000 2 - 32K Entries (128 Kbytes) 5285 ** �E 10000 2 - 64K Entries (256 Kbytes) 5286 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 5287 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 5288 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 5289 ** disabled. When set, the Circular Queues are fully enabled. 5290 ************************************************************************** 5291 */ 5292 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 5293 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 5294 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 5295 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 5296 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 5297 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 5298 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 5299 /* 5300 ************************************************************************** 5301 ** Queue Base Address Register - QBAR 5302 ** 5303 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 5304 ** The base address is required to be located on a 1 Mbyte address boundary. 5305 ** . All Circular Queue head and tail pointers are based on the QBAR. 5306 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 5307 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 5308 ** Warning: 5309 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 5310 ** ------------------------------------------------------------------------ 5311 ** Bit Default Description 5312 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5313 ** 19:00 00000H Reserved 5314 ************************************************************************** 5315 */ 5316 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 5317 /* 5318 ************************************************************************** 5319 ** Inbound Free Head Pointer Register - IFHPR 5320 ** 5321 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 5322 ** the Queue Base Address of the head pointer for the Inbound Free Queue. 5323 ** The Head Pointer must be aligned on a DWORD address boundary. 5324 ** When read, the Queue Base Address is provided in the upper 12 bits of the register. 5325 ** Writes to the upper 12 bits of the register are ignored. 5326 ** This register is maintained by software. 5327 ** ------------------------------------------------------------------------ 5328 ** Bit Default Description 5329 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5330 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 5331 ** 01:00 00 2 Reserved 5332 ************************************************************************** 5333 */ 5334 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 5335 /* 5336 ************************************************************************** 5337 ** Inbound Free Tail Pointer Register - IFTPR 5338 ** 5339 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 5340 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 5341 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5342 ** of the register. Writes to the upper 12 bits of the register are ignored. 5343 ** ------------------------------------------------------------------------ 5344 ** Bit Default Description 5345 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5346 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 5347 ** 01:00 00 2 Reserved 5348 ************************************************************************** 5349 */ 5350 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 5351 /* 5352 ************************************************************************** 5353 ** Inbound Post Head Pointer Register - IPHPR 5354 ** 5355 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 5356 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 5357 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5358 ** of the register. Writes to the upper 12 bits of the register are ignored. 5359 ** ------------------------------------------------------------------------ 5360 ** Bit Default Description 5361 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5362 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 5363 ** 01:00 00 2 Reserved 5364 ************************************************************************** 5365 */ 5366 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 5367 /* 5368 ************************************************************************** 5369 ** Inbound Post Tail Pointer Register - IPTPR 5370 ** 5371 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 5372 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 5373 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5374 ** of the register. Writes to the upper 12 bits of the register are ignored. 5375 ** ------------------------------------------------------------------------ 5376 ** Bit Default Description 5377 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5378 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 5379 ** 01:00 00 2 Reserved 5380 ************************************************************************** 5381 */ 5382 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 5383 /* 5384 ************************************************************************** 5385 ** Index Address Register - IAR 5386 ** 5387 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 5388 ** It is written by the MU when the Index Registers are written by a PCI agent. 5389 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 5390 ** . The local memory address of the Index Register least recently accessed is computed 5391 ** by adding the Index Address Register to the Inbound ATU Translate Value Register. 5392 ** ------------------------------------------------------------------------ 5393 ** Bit Default Description 5394 ** 31:12 000000H Reserved 5395 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 5396 ** 01:00 00 2 Reserved 5397 ************************************************************************** 5398 */ 5399 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 5400 /* 5401 ********************************************************************************************************** 5402 ** RS-232 Interface for Areca Raid Controller 5403 ** The low level command interface is exclusive with VT100 terminal 5404 ** -------------------------------------------------------------------- 5405 ** 1. Sequence of command execution 5406 ** -------------------------------------------------------------------- 5407 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5408 ** (B) Command block : variable length of data including length, command code, data and checksum byte 5409 ** (C) Return data : variable length of data 5410 ** -------------------------------------------------------------------- 5411 ** 2. Command block 5412 ** -------------------------------------------------------------------- 5413 ** (A) 1st byte : command block length (low byte) 5414 ** (B) 2nd byte : command block length (high byte) 5415 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 5416 ** (C) 3rd byte : command code 5417 ** (D) 4th and following bytes : variable length data bytes depends on command code 5418 ** (E) last byte : checksum byte (sum of 1st byte until last data byte) 5419 ** -------------------------------------------------------------------- 5420 ** 3. Command code and associated data 5421 ** -------------------------------------------------------------------- 5422 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 5423 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 5424 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 5425 ** enum 5426 ** { 5427 ** GUI_SET_SERIAL=0x10, 5428 ** GUI_SET_VENDOR, 5429 ** GUI_SET_MODEL, 5430 ** GUI_IDENTIFY, 5431 ** GUI_CHECK_PASSWORD, 5432 ** GUI_LOGOUT, 5433 ** GUI_HTTP, 5434 ** GUI_SET_ETHERNET_ADDR, 5435 ** GUI_SET_LOGO, 5436 ** GUI_POLL_EVENT, 5437 ** GUI_GET_EVENT, 5438 ** GUI_GET_HW_MONITOR, 5439 ** 5440 ** // GUI_QUICK_CREATE=0x20, (function removed) 5441 ** GUI_GET_INFO_R=0x20, 5442 ** GUI_GET_INFO_V, 5443 ** GUI_GET_INFO_P, 5444 ** GUI_GET_INFO_S, 5445 ** GUI_CLEAR_EVENT, 5446 ** 5447 ** GUI_MUTE_BEEPER=0x30, 5448 ** GUI_BEEPER_SETTING, 5449 ** GUI_SET_PASSWORD, 5450 ** GUI_HOST_INTERFACE_MODE, 5451 ** GUI_REBUILD_PRIORITY, 5452 ** GUI_MAX_ATA_MODE, 5453 ** GUI_RESET_CONTROLLER, 5454 ** GUI_COM_PORT_SETTING, 5455 ** GUI_NO_OPERATION, 5456 ** GUI_DHCP_IP, 5457 ** 5458 ** GUI_CREATE_PASS_THROUGH=0x40, 5459 ** GUI_MODIFY_PASS_THROUGH, 5460 ** GUI_DELETE_PASS_THROUGH, 5461 ** GUI_IDENTIFY_DEVICE, 5462 ** 5463 ** GUI_CREATE_RAIDSET=0x50, 5464 ** GUI_DELETE_RAIDSET, 5465 ** GUI_EXPAND_RAIDSET, 5466 ** GUI_ACTIVATE_RAIDSET, 5467 ** GUI_CREATE_HOT_SPARE, 5468 ** GUI_DELETE_HOT_SPARE, 5469 ** 5470 ** GUI_CREATE_VOLUME=0x60, 5471 ** GUI_MODIFY_VOLUME, 5472 ** GUI_DELETE_VOLUME, 5473 ** GUI_START_CHECK_VOLUME, 5474 ** GUI_STOP_CHECK_VOLUME 5475 ** }; 5476 ** 5477 ** Command description : 5478 ** 5479 ** GUI_SET_SERIAL : Set the controller serial# 5480 ** byte 0,1 : length 5481 ** byte 2 : command code 0x10 5482 ** byte 3 : password length (should be 0x0f) 5483 ** byte 4-0x13 : should be "ArEcATecHnoLogY" 5484 ** byte 0x14--0x23 : Serial number string (must be 16 bytes) 5485 ** GUI_SET_VENDOR : Set vendor string for the controller 5486 ** byte 0,1 : length 5487 ** byte 2 : command code 0x11 5488 ** byte 3 : password length (should be 0x08) 5489 ** byte 4-0x13 : should be "ArEcAvAr" 5490 ** byte 0x14--0x3B : vendor string (must be 40 bytes) 5491 ** GUI_SET_MODEL : Set the model name of the controller 5492 ** byte 0,1 : length 5493 ** byte 2 : command code 0x12 5494 ** byte 3 : password length (should be 0x08) 5495 ** byte 4-0x13 : should be "ArEcAvAr" 5496 ** byte 0x14--0x1B : model string (must be 8 bytes) 5497 ** GUI_IDENTIFY : Identify device 5498 ** byte 0,1 : length 5499 ** byte 2 : command code 0x13 5500 ** return "Areca RAID Subsystem " 5501 ** GUI_CHECK_PASSWORD : Verify password 5502 ** byte 0,1 : length 5503 ** byte 2 : command code 0x14 5504 ** byte 3 : password length 5505 ** byte 4-0x?? : user password to be checked 5506 ** GUI_LOGOUT : Logout GUI (force password checking on next command) 5507 ** byte 0,1 : length 5508 ** byte 2 : command code 0x15 5509 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 5510 ** 5511 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 5512 ** byte 0,1 : length 5513 ** byte 2 : command code 0x17 5514 ** byte 3 : password length (should be 0x08) 5515 ** byte 4-0x13 : should be "ArEcAvAr" 5516 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 5517 ** GUI_SET_LOGO : Set logo in HTTP 5518 ** byte 0,1 : length 5519 ** byte 2 : command code 0x18 5520 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 5521 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 5522 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 5523 ** note .... page0 1st 2 byte must be actual length of the JPG file 5524 ** GUI_POLL_EVENT : Poll If Event Log Changed 5525 ** byte 0,1 : length 5526 ** byte 2 : command code 0x19 5527 ** GUI_GET_EVENT : Read Event 5528 ** byte 0,1 : length 5529 ** byte 2 : command code 0x1a 5530 ** byte 3 : Event Page (0:1st page/1/2/3:last page) 5531 ** GUI_GET_HW_MONITOR : Get HW monitor data 5532 ** byte 0,1 : length 5533 ** byte 2 : command code 0x1b 5534 ** byte 3 : # of FANs(example 2) 5535 ** byte 4 : # of Voltage sensor(example 3) 5536 ** byte 5 : # of temperature sensor(example 2) 5537 ** byte 6 : # of power 5538 ** byte 7/8 : Fan#0 (RPM) 5539 ** byte 9/10 : Fan#1 5540 ** byte 11/12 : Voltage#0 original value in *1000 5541 ** byte 13/14 : Voltage#0 value 5542 ** byte 15/16 : Voltage#1 org 5543 ** byte 17/18 : Voltage#1 5544 ** byte 19/20 : Voltage#2 org 5545 ** byte 21/22 : Voltage#2 5546 ** byte 23 : Temp#0 5547 ** byte 24 : Temp#1 5548 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 5549 ** byte 26 : UPS indicator 5550 ** GUI_QUICK_CREATE : Quick create raid/volume set 5551 ** byte 0,1 : length 5552 ** byte 2 : command code 0x20 5553 ** byte 3/4/5/6 : raw capacity 5554 ** byte 7 : raid level 5555 ** byte 8 : stripe size 5556 ** byte 9 : spare 5557 ** byte 10/11/12/13: device mask (the devices to create raid/volume) 5558 ** This function is removed, application like to implement quick create function 5559 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 5560 ** GUI_GET_INFO_R : Get Raid Set Information 5561 ** byte 0,1 : length 5562 ** byte 2 : command code 0x20 5563 ** byte 3 : raidset# 5564 ** 5565 ** typedef struct sGUI_RAIDSET 5566 ** { 5567 ** BYTE grsRaidSetName[16]; 5568 ** DWORD grsCapacity; 5569 ** DWORD grsCapacityX; 5570 ** DWORD grsFailMask; 5571 ** BYTE grsDevArray[32]; 5572 ** BYTE grsMemberDevices; 5573 ** BYTE grsNewMemberDevices; 5574 ** BYTE grsRaidState; 5575 ** BYTE grsVolumes; 5576 ** BYTE grsVolumeList[16]; 5577 ** BYTE grsRes1; 5578 ** BYTE grsRes2; 5579 ** BYTE grsRes3; 5580 ** BYTE grsFreeSegments; 5581 ** DWORD grsRawStripes[8]; 5582 ** DWORD grsRes4; 5583 ** DWORD grsRes5; // Total to 128 bytes 5584 ** DWORD grsRes6; // Total to 128 bytes 5585 ** } sGUI_RAIDSET, *pGUI_RAIDSET; 5586 ** GUI_GET_INFO_V : Get Volume Set Information 5587 ** byte 0,1 : length 5588 ** byte 2 : command code 0x21 5589 ** byte 3 : volumeset# 5590 ** 5591 ** typedef struct sGUI_VOLUMESET 5592 ** { 5593 ** BYTE gvsVolumeName[16]; // 16 5594 ** DWORD gvsCapacity; 5595 ** DWORD gvsCapacityX; 5596 ** DWORD gvsFailMask; 5597 ** DWORD gvsStripeSize; 5598 ** DWORD gvsNewFailMask; 5599 ** DWORD gvsNewStripeSize; 5600 ** DWORD gvsVolumeStatus; 5601 ** DWORD gvsProgress; // 32 5602 ** sSCSI_ATTR gvsScsi; 5603 ** BYTE gvsMemberDisks; 5604 ** BYTE gvsRaidLevel; // 8 5605 ** 5606 ** BYTE gvsNewMemberDisks; 5607 ** BYTE gvsNewRaidLevel; 5608 ** BYTE gvsRaidSetNumber; 5609 ** BYTE gvsRes0; // 4 5610 ** BYTE gvsRes1[4]; // 64 bytes 5611 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 5612 ** 5613 ** GUI_GET_INFO_P : Get Physical Drive Information 5614 ** byte 0,1 : length 5615 ** byte 2 : command code 0x22 5616 ** byte 3 : drive # (from 0 to max-channels - 1) 5617 ** 5618 ** typedef struct sGUI_PHY_DRV 5619 ** { 5620 ** BYTE gpdModelName[40]; 5621 ** BYTE gpdSerialNumber[20]; 5622 ** BYTE gpdFirmRev[8]; 5623 ** DWORD gpdCapacity; 5624 ** DWORD gpdCapacityX; // Reserved for expansion 5625 ** BYTE gpdDeviceState; 5626 ** BYTE gpdPioMode; 5627 ** BYTE gpdCurrentUdmaMode; 5628 ** BYTE gpdUdmaMode; 5629 ** BYTE gpdDriveSelect; 5630 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 5631 ** sSCSI_ATTR gpdScsi; 5632 ** BYTE gpdReserved[40]; // Total to 128 bytes 5633 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 5634 ** 5635 ** GUI_GET_INFO_S : Get System Information 5636 ** byte 0,1 : length 5637 ** byte 2 : command code 0x23 5638 ** 5639 ** typedef struct sCOM_ATTR 5640 ** { 5641 ** BYTE comBaudRate; 5642 ** BYTE comDataBits; 5643 ** BYTE comStopBits; 5644 ** BYTE comParity; 5645 ** BYTE comFlowControl; 5646 ** } sCOM_ATTR, *pCOM_ATTR; 5647 ** 5648 ** typedef struct sSYSTEM_INFO 5649 ** { 5650 ** BYTE gsiVendorName[40]; 5651 ** BYTE gsiSerialNumber[16]; 5652 ** BYTE gsiFirmVersion[16]; 5653 ** BYTE gsiBootVersion[16]; 5654 ** BYTE gsiMbVersion[16]; 5655 ** BYTE gsiModelName[8]; 5656 ** BYTE gsiLocalIp[4]; 5657 ** BYTE gsiCurrentIp[4]; 5658 ** DWORD gsiTimeTick; 5659 ** DWORD gsiCpuSpeed; 5660 ** DWORD gsiICache; 5661 ** DWORD gsiDCache; 5662 ** DWORD gsiScache; 5663 ** DWORD gsiMemorySize; 5664 ** DWORD gsiMemorySpeed; 5665 ** DWORD gsiEvents; 5666 ** BYTE gsiMacAddress[6]; 5667 ** BYTE gsiDhcp; 5668 ** BYTE gsiBeeper; 5669 ** BYTE gsiChannelUsage; 5670 ** BYTE gsiMaxAtaMode; 5671 ** BYTE gsiSdramEcc; // 1:if ECC enabled 5672 ** BYTE gsiRebuildPriority; 5673 ** sCOM_ATTR gsiComA; // 5 bytes 5674 ** sCOM_ATTR gsiComB; // 5 bytes 5675 ** BYTE gsiIdeChannels; 5676 ** BYTE gsiScsiHostChannels; 5677 ** BYTE gsiIdeHostChannels; 5678 ** BYTE gsiMaxVolumeSet; 5679 ** BYTE gsiMaxRaidSet; 5680 ** BYTE gsiEtherPort; // 1:if ether net port supported 5681 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 5682 ** BYTE gsiRes[75]; 5683 ** } sSYSTEM_INFO, *pSYSTEM_INFO; 5684 ** 5685 ** GUI_CLEAR_EVENT : Clear System Event 5686 ** byte 0,1 : length 5687 ** byte 2 : command code 0x24 5688 ** 5689 ** GUI_MUTE_BEEPER : Mute current beeper 5690 ** byte 0,1 : length 5691 ** byte 2 : command code 0x30 5692 ** 5693 ** GUI_BEEPER_SETTING : Disable beeper 5694 ** byte 0,1 : length 5695 ** byte 2 : command code 0x31 5696 ** byte 3 : 0->disable, 1->enable 5697 ** 5698 ** GUI_SET_PASSWORD : Change password 5699 ** byte 0,1 : length 5700 ** byte 2 : command code 0x32 5701 ** byte 3 : pass word length ( must <= 15 ) 5702 ** byte 4 : password (must be alpha-numerical) 5703 ** 5704 ** GUI_HOST_INTERFACE_MODE : Set host interface mode 5705 ** byte 0,1 : length 5706 ** byte 2 : command code 0x33 5707 ** byte 3 : 0->Independent, 1->cluster 5708 ** 5709 ** GUI_REBUILD_PRIORITY : Set rebuild priority 5710 ** byte 0,1 : length 5711 ** byte 2 : command code 0x34 5712 ** byte 3 : 0/1/2/3 (low->high) 5713 ** 5714 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 5715 ** byte 0,1 : length 5716 ** byte 2 : command code 0x35 5717 ** byte 3 : 0/1/2/3 (133/100/66/33) 5718 ** 5719 ** GUI_RESET_CONTROLLER : Reset Controller 5720 ** byte 0,1 : length 5721 ** byte 2 : command code 0x36 5722 ** *Response with VT100 screen (discard it) 5723 ** 5724 ** GUI_COM_PORT_SETTING : COM port setting 5725 ** byte 0,1 : length 5726 ** byte 2 : command code 0x37 5727 ** byte 3 : 0->COMA (term port), 1->COMB (debug port) 5728 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 5729 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 5730 ** byte 6 : stop bit (0:1, 1:2 stop bits) 5731 ** byte 7 : parity (0:none, 1:off, 2:even) 5732 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 5733 ** 5734 ** GUI_NO_OPERATION : No operation 5735 ** byte 0,1 : length 5736 ** byte 2 : command code 0x38 5737 ** 5738 ** GUI_DHCP_IP : Set DHCP option and local IP address 5739 ** byte 0,1 : length 5740 ** byte 2 : command code 0x39 5741 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled 5742 ** byte 4/5/6/7 : IP address 5743 ** 5744 ** GUI_CREATE_PASS_THROUGH : Create pass through disk 5745 ** byte 0,1 : length 5746 ** byte 2 : command code 0x40 5747 ** byte 3 : device # 5748 ** byte 4 : scsi channel (0/1) 5749 ** byte 5 : scsi id (0-->15) 5750 ** byte 6 : scsi lun (0-->7) 5751 ** byte 7 : tagged queue (1 : enabled) 5752 ** byte 8 : cache mode (1 : enabled) 5753 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5754 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5755 ** 5756 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 5757 ** byte 0,1 : length 5758 ** byte 2 : command code 0x41 5759 ** byte 3 : device # 5760 ** byte 4 : scsi channel (0/1) 5761 ** byte 5 : scsi id (0-->15) 5762 ** byte 6 : scsi lun (0-->7) 5763 ** byte 7 : tagged queue (1 : enabled) 5764 ** byte 8 : cache mode (1 : enabled) 5765 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5766 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5767 ** 5768 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk 5769 ** byte 0,1 : length 5770 ** byte 2 : command code 0x42 5771 ** byte 3 : device# to be deleted 5772 ** 5773 ** GUI_IDENTIFY_DEVICE : Identify Device 5774 ** byte 0,1 : length 5775 ** byte 2 : command code 0x43 5776 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 5777 ** byte 4/5/6/7 : IDE device mask to be flashed 5778 ** note .... no response data available 5779 ** 5780 ** GUI_CREATE_RAIDSET : Create Raid Set 5781 ** byte 0,1 : length 5782 ** byte 2 : command code 0x50 5783 ** byte 3/4/5/6 : device mask 5784 ** byte 7-22 : raidset name (if byte 7 == 0:use default) 5785 ** 5786 ** GUI_DELETE_RAIDSET : Delete Raid Set 5787 ** byte 0,1 : length 5788 ** byte 2 : command code 0x51 5789 ** byte 3 : raidset# 5790 ** 5791 ** GUI_EXPAND_RAIDSET : Expand Raid Set 5792 ** byte 0,1 : length 5793 ** byte 2 : command code 0x52 5794 ** byte 3 : raidset# 5795 ** byte 4/5/6/7 : device mask for expansion 5796 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5797 ** byte 11/12/13 : repeat for each volume in the raidset .... 5798 ** 5799 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5800 ** byte 0,1 : length 5801 ** byte 2 : command code 0x53 5802 ** byte 3 : raidset# 5803 ** 5804 ** GUI_CREATE_HOT_SPARE : Create hot spare disk 5805 ** byte 0,1 : length 5806 ** byte 2 : command code 0x54 5807 ** byte 3/4/5/6 : device mask for hot spare creation 5808 ** 5809 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5810 ** byte 0,1 : length 5811 ** byte 2 : command code 0x55 5812 ** byte 3/4/5/6 : device mask for hot spare deletion 5813 ** 5814 ** GUI_CREATE_VOLUME : Create volume set 5815 ** byte 0,1 : length 5816 ** byte 2 : command code 0x60 5817 ** byte 3 : raidset# 5818 ** byte 4-19 : volume set name (if byte4 == 0, use default) 5819 ** byte 20-27 : volume capacity (blocks) 5820 ** byte 28 : raid level 5821 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5822 ** byte 30 : channel 5823 ** byte 31 : ID 5824 ** byte 32 : LUN 5825 ** byte 33 : 1 enable tag 5826 ** byte 34 : 1 enable cache 5827 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5828 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5829 ** byte 36 : 1 to select quick init 5830 ** 5831 ** GUI_MODIFY_VOLUME : Modify volume Set 5832 ** byte 0,1 : length 5833 ** byte 2 : command code 0x61 5834 ** byte 3 : volumeset# 5835 ** byte 4-19 : new volume set name (if byte4 == 0, not change) 5836 ** byte 20-27 : new volume capacity (reserved) 5837 ** byte 28 : new raid level 5838 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5839 ** byte 30 : new channel 5840 ** byte 31 : new ID 5841 ** byte 32 : new LUN 5842 ** byte 33 : 1 enable tag 5843 ** byte 34 : 1 enable cache 5844 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5845 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5846 ** 5847 ** GUI_DELETE_VOLUME : Delete volume set 5848 ** byte 0,1 : length 5849 ** byte 2 : command code 0x62 5850 ** byte 3 : volumeset# 5851 ** 5852 ** GUI_START_CHECK_VOLUME : Start volume consistency check 5853 ** byte 0,1 : length 5854 ** byte 2 : command code 0x63 5855 ** byte 3 : volumeset# 5856 ** 5857 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5858 ** byte 0,1 : length 5859 ** byte 2 : command code 0x64 5860 ** --------------------------------------------------------------------- 5861 ** 4. Returned data 5862 ** --------------------------------------------------------------------- 5863 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5864 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5865 ** (C) status or data : 5866 ** <1> If length == 1 ==> 1 byte status code 5867 ** #define GUI_OK 0x41 5868 ** #define GUI_RAIDSET_NOT_NORMAL 0x42 5869 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5870 ** #define GUI_NO_RAIDSET 0x44 5871 ** #define GUI_NO_VOLUMESET 0x45 5872 ** #define GUI_NO_PHYSICAL_DRIVE 0x46 5873 ** #define GUI_PARAMETER_ERROR 0x47 5874 ** #define GUI_UNSUPPORTED_COMMAND 0x48 5875 ** #define GUI_DISK_CONFIG_CHANGED 0x49 5876 ** #define GUI_INVALID_PASSWORD 0x4a 5877 ** #define GUI_NO_DISK_SPACE 0x4b 5878 ** #define GUI_CHECKSUM_ERROR 0x4c 5879 ** #define GUI_PASSWORD_REQUIRED 0x4d 5880 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5881 ** (E) Checksum : checksum of length and status or data byte 5882 ************************************************************************** 5883 */ 5884