1 /* 2 *********************************************************************************************** 3 ** O.S : FreeBSD 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA SATA/SAS RAID HOST Adapter 8 ** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] 9 *********************************************************************************************** 10 ************************************************************************ 11 ** Copyright (C) 2002 - 2010, Areca Technology Corporation All rights reserved. 12 ** 13 ** Web site: www.areca.com.tw 14 ** E-mail: erich@areca.com.tw; ching2048@areca.com.tw 15 ** 16 ** Redistribution and use in source and binary forms,with or without 17 ** modification,are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice,this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice,this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 31 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 32 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ************************************************************************** 38 * $FreeBSD$ 39 */ 40 #define ARCMSR_SCSI_INITIATOR_ID 255 41 #define ARCMSR_DEV_SECTOR_SIZE 512 42 #define ARCMSR_MAX_XFER_SECTORS 4096 43 #define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 44 #define ARCMSR_MAX_TARGETLUN 8 /*8*/ 45 #define ARCMSR_MAX_CHIPTYPE_NUM 4 46 #define ARCMSR_MAX_OUTSTANDING_CMD 256 47 #define ARCMSR_MAX_START_JOB 257 48 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 49 #define ARCMSR_MAX_FREESRB_NUM 320 50 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 51 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 52 #define ARCMSR_MAX_ADAPTER 4 53 #define ARCMSR_RELEASE_SIMQ_LEVEL 230 54 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ 55 /* 56 ********************************************************************* 57 */ 58 #ifndef TRUE 59 #define TRUE 1 60 #endif 61 #ifndef FALSE 62 #define FALSE 0 63 #endif 64 #ifndef INTR_ENTROPY 65 # define INTR_ENTROPY 0 66 #endif 67 68 #ifndef offsetof 69 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 70 #endif 71 /* 72 ********************************************************************************** 73 ** 74 ********************************************************************************** 75 */ 76 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 77 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 78 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 79 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 80 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 81 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 82 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ 83 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 84 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 85 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 86 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 87 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 88 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 89 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 90 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 91 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 92 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 93 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 94 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 95 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 96 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 97 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 98 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 99 100 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 101 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 102 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 103 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 104 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 105 #define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 106 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 107 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 108 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 109 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 110 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 111 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 112 #define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 113 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 114 #define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 115 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 116 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 117 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 118 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 119 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 120 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 121 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ 122 123 #ifndef PCIR_BARS 124 #define PCIR_BARS 0x10 125 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 126 #endif 127 128 #define PCI_BASE_ADDR0 0x10 129 #define PCI_BASE_ADDR1 0x14 130 #define PCI_BASE_ADDR2 0x18 131 #define PCI_BASE_ADDR3 0x1C 132 #define PCI_BASE_ADDR4 0x20 133 #define PCI_BASE_ADDR5 0x24 134 /* 135 ********************************************************************************** 136 ** 137 ********************************************************************************** 138 */ 139 #define ARCMSR_SCSICMD_IOCTL 0x77 140 #define ARCMSR_CDEVSW_IOCTL 0x88 141 #define ARCMSR_MESSAGE_FAIL 0x0001 142 #define ARCMSR_MESSAGE_SUCCESS 0x0000 143 /* 144 ********************************************************************************** 145 ** 146 ********************************************************************************** 147 */ 148 #define arcmsr_ccbsrb_ptr spriv_ptr0 149 #define arcmsr_ccbacb_ptr spriv_ptr1 150 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 151 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 152 #define get_min(x,y) ((x) < (y) ? (x) : (y)) 153 #define get_max(x,y) ((x) < (y) ? (y) : (x)) 154 /* 155 ********************************************************************************** 156 ** 157 ********************************************************************************** 158 */ 159 struct CMD_MESSAGE { 160 u_int32_t HeaderLength; 161 u_int8_t Signature[8]; 162 u_int32_t Timeout; 163 u_int32_t ControlCode; 164 u_int32_t ReturnCode; 165 u_int32_t Length; 166 }; 167 168 struct CMD_MESSAGE_FIELD { 169 struct CMD_MESSAGE cmdmessage; /* ioctl header */ 170 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 171 }; 172 173 /************************************************************************/ 174 /************************************************************************/ 175 176 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 177 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 178 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 179 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 180 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 181 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 182 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 183 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 184 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 185 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 186 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 187 188 /*DeviceType*/ 189 #define ARECA_SATA_RAID 0x90000000 190 191 /*FunctionCode*/ 192 #define FUNCTION_READ_RQBUFFER 0x0801 193 #define FUNCTION_WRITE_WQBUFFER 0x0802 194 #define FUNCTION_CLEAR_RQBUFFER 0x0803 195 #define FUNCTION_CLEAR_WQBUFFER 0x0804 196 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 197 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 198 #define FUNCTION_SAY_HELLO 0x0807 199 #define FUNCTION_SAY_GOODBYE 0x0808 200 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 201 /* 202 ************************************************************************ 203 ** IOCTL CONTROL CODE 204 ************************************************************************ 205 */ 206 /* ARECA IO CONTROL CODE*/ 207 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 208 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 209 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 210 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 211 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 212 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 213 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 214 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 215 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 216 217 /* ARECA IOCTL ReturnCode */ 218 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 219 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 220 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 221 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 222 /* 223 ************************************************************************ 224 ** SPEC. for Areca HBB adapter 225 ************************************************************************ 226 */ 227 /* ARECA HBB COMMAND for its FIRMWARE */ 228 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 229 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 230 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 231 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 232 233 /* ARECA FLAG LANGUAGE */ 234 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 235 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */ 236 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 237 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 238 239 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 240 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 241 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 242 243 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 244 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 245 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 246 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 247 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 248 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 249 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 250 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 251 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 252 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 253 254 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 255 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */ 256 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 257 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 258 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */ 259 260 /* data tunnel buffer between user space program and its firmware */ 261 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */ 262 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */ 263 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */ 264 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010 265 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018 266 #define ARCMSR_HBB_BASE0_LEN 0x00021000 267 #define ARCMSR_HBB_BASE1_LEN 0x00010000 268 /* 269 ************************************************************************ 270 ** SPEC. for Areca HBC adapter 271 ************************************************************************ 272 */ 273 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 274 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 275 /* Host Interrupt Mask */ 276 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 277 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 278 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 279 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 280 /* Host Interrupt Status */ 281 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 282 /* 283 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 284 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 285 */ 286 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 287 /* 288 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 289 ** value. This bit clears only when Outbound Doorbell bits 290 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 291 ** Clear register clears bits in the Outbound Doorbell register. 292 */ 293 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 294 /* 295 ** Set whenever the Outbound Post List Producer/Consumer 296 ** Register (FIFO) is not empty. It clears when the Outbound 297 ** Post List FIFO is empty. 298 */ 299 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 300 /* 301 ** This bit indicates a SAS interrupt from a source external to 302 ** the PCIe core. This bit is not maskable. 303 */ 304 /* DoorBell*/ 305 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/ 306 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/ 307 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/ 308 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 309 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 310 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 311 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 312 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 313 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 314 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 315 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ 316 317 /* 318 ************************************************************* 319 ** structure for holding DMA address data 320 ************************************************************* 321 */ 322 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 323 /* 324 ************************************************************************************************ 325 ** ARECA FIRMWARE SPEC 326 ************************************************************************************************ 327 ** Usage of IOP331 adapter 328 ** (All In/Out is in IOP331's view) 329 ** 1. Message 0 --> InitThread message and retrun code 330 ** 2. Doorbell is used for RS-232 emulation 331 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 332 ** bit1 -- data out has been read (DRIVER DATA READ OK) 333 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 334 ** bit1 -- data in has been read (IOP331 DATA READ OK) 335 ** 3. Index Memory Usage 336 ** offset 0xf00 : for RS232 out (request buffer) 337 ** offset 0xe00 : for RS232 in (scratch buffer) 338 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 339 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver) 340 ** 4. RS-232 emulation 341 ** Currently 128 byte buffer is used 342 ** 1st u_int32_t : Data length (1--124) 343 ** Byte 4--127 : Max 124 bytes of data 344 ** 5. PostQ 345 ** All SCSI Command must be sent through postQ: 346 ** (inbound queue port) Request frame must be 32 bytes aligned 347 ** # bit27--bit31 => flag for post ccb 348 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 349 ** bit31 : 0 : 256 bytes frame 350 ** 1 : 512 bytes frame 351 ** bit30 : 0 : normal request 352 ** 1 : BIOS request 353 ** bit29 : reserved 354 ** bit28 : reserved 355 ** bit27 : reserved 356 ** ------------------------------------------------------------------------------- 357 ** (outbount queue port) Request reply 358 ** # bit27--bit31 => flag for reply 359 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 360 ** bit31 : must be 0 (for this type of reply) 361 ** bit30 : reserved for BIOS handshake 362 ** bit29 : reserved 363 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 364 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData 365 ** bit27 : reserved 366 ** 6. BIOS request 367 ** All BIOS request is the same with request from PostQ 368 ** Except : 369 ** Request frame is sent from configuration space 370 ** offset: 0x78 : Request Frame (bit30 == 1) 371 ** offset: 0x18 : writeonly to generate IRQ to IOP331 372 ** Completion of request: 373 ** (bit30 == 0, bit28==err flag) 374 ** 7. Definition of SGL entry (structure) 375 ** 8. Message1 Out - Diag Status Code (????) 376 ** 9. Message0 message code : 377 ** 0x00 : NOP 378 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver) 379 ** Signature 0x87974060(4) 380 ** Request len 0x00000200(4) 381 ** numbers of queue 0x00000100(4) 382 ** SDRAM Size 0x00000100(4)-->256 MB 383 ** IDE Channels 0x00000008(4) 384 ** vendor 40 bytes char 385 ** model 8 bytes char 386 ** FirmVer 16 bytes char 387 ** Device Map 16 bytes char 388 ** 389 ** FirmwareVersion DWORD <== Added for checking of new firmware capability 390 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 391 ** Signature 0x87974063(4) 392 ** UPPER32 of Request Frame (4)-->Driver Only 393 ** 0x03 : Reset (Abort all queued Command) 394 ** 0x04 : Stop Background Activity 395 ** 0x05 : Flush Cache 396 ** 0x06 : Start Background Activity (re-start if background is halted) 397 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 398 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331) 399 ** byte 0 : 0xaa <-- signature 400 ** byte 1 : 0x55 <-- signature 401 ** byte 2 : year (04) 402 ** byte 3 : month (1..12) 403 ** byte 4 : date (1..31) 404 ** byte 5 : hour (0..23) 405 ** byte 6 : minute (0..59) 406 ** byte 7 : second (0..59) 407 ** ********************************************************************************* 408 ** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter 409 ** ==> Difference from IOP348 410 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code 411 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP) 412 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 413 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 414 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver) 415 ** <A> use doorbell to generate interrupt 416 ** 417 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop) 418 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver) 419 ** 420 ** a. Message1: Out - Diag Status Code (????) 421 ** 422 ** b. Message0: message code 423 ** 0x00 : NOP 424 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver) 425 ** Signature 0x87974060(4) 426 ** Request len 0x00000200(4) 427 ** numbers of queue 0x00000100(4) 428 ** SDRAM Size 0x00000100(4)-->256 MB 429 ** IDE Channels 0x00000008(4) 430 ** vendor 40 bytes char 431 ** model 8 bytes char 432 ** FirmVer 16 bytes char 433 ** Device Map 16 bytes char 434 ** cfgVersion ULONG <== Added for checking of new firmware capability 435 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP) 436 ** Signature 0x87974063(4) 437 ** UPPER32 of Request Frame (4)-->Driver Only 438 ** 0x03 : Reset (Abort all queued Command) 439 ** 0x04 : Stop Background Activity 440 ** 0x05 : Flush Cache 441 ** 0x06 : Start Background Activity (re-start if background is halted) 442 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 443 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP) 444 ** byte 0 : 0xaa <-- signature 445 ** byte 1 : 0x55 <-- signature 446 ** byte 2 : year (04) 447 ** byte 3 : month (1..12) 448 ** byte 4 : date (1..31) 449 ** byte 5 : hour (0..23) 450 ** byte 6 : minute (0..59) 451 ** byte 7 : second (0..59) 452 ** 453 ** <2> Doorbell Register is used for RS-232 emulation 454 ** <A> different clear register 455 ** <B> different bit0 definition (bit0 is reserved) 456 ** 457 ** inbound doorbell : at offset 0x20 458 ** inbound doorbell clear : at offset 0x70 459 ** 460 ** inbound doorbell : bit0 -- reserved 461 ** bit1 -- data in ready (DRIVER DATA WRITE OK) 462 ** bit2 -- data out has been read (DRIVER DATA READ OK) 463 ** bit3 -- inbound message 0 ready 464 ** bit4 -- more than 12 request completed in a time 465 ** 466 ** outbound doorbell : at offset 0x9C 467 ** outbound doorbell clear : at offset 0xA0 468 ** 469 ** outbound doorbell : bit0 -- reserved 470 ** bit1 -- data out ready (IOP DATA WRITE OK) 471 ** bit2 -- data in has been read (IOP DATA READ OK) 472 ** bit3 -- outbound message 0 ready 473 ** 474 ** <3> Index Memory Usage (Buffer Area) 475 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer) 476 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer) 477 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver) 478 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP) 479 ** 480 ** <4> PostQ (Command Post Address) 481 ** All SCSI Command must be sent through postQ: 482 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43 483 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper) 484 ** outbound queue port32 at offset 0x44 485 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper) 486 ** <A> For 32bit queue, access low part is enough to send/receive request 487 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the 488 ** same for outbound queue port 489 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction 490 ** to post inbound request in a single instruction, and use 64bit instruction 491 ** to retrieve outbound request in a single instruction. 492 ** If in 32bit environment, when sending inbound queue, write high part first 493 ** then write low part. For receiving outbound request, read high part first 494 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF. 495 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the 496 ** consistency of the FIFO. Another way to check empty is to check status flag 497 ** at 0x30 bit3. 498 ** <C> Post Address IS NOT shifted (must be 16 bytes aligned) 499 ** For BIOS, 16bytes aligned is OK 500 ** For Driver, 32bytes alignment is recommended. 501 ** POST Command bit0 to bit3 is defined differently 502 ** ---------------------------- 503 ** bit0:1 for PULL mode (must be 1) 504 ** ---------------------------- 505 ** bit3/2/1: for arcmsr cdb size (arccdbsize) 506 ** 000: <= 0x0080 (128) 507 ** 001: <= 0x0100 (256) 508 ** 010: <= 0x0180 (384) 509 ** 011: <= 0x0200 (512) 510 ** 100: <= 0x0280 (640) 511 ** 101: <= 0x0300 (768) 512 ** 110: <= 0x0300 (reserved) 513 ** 111: <= 0x0300 (reserved) 514 ** ----------------------------- 515 ** if len > 0x300 the len always set as 0x300 516 ** ----------------------------- 517 ** post addr = addr | ((len-1) >> 6) | 1 518 ** ----------------------------- 519 ** page length in command buffer still required, 520 ** 521 ** if page length > 3, 522 ** firmware will assume more request data need to be retrieved 523 ** 524 ** <D> Outbound Posting 525 ** bit0:0 , no error, 1 with error, refer to status buffer 526 ** bit1:0 , reserved (will be 0) 527 ** bit2:0 , reserved (will be 0) 528 ** bit3:0 , reserved (will be 0) 529 ** bit63-4: Completed command address 530 ** 531 ** <E> BIOS support, no special support is required. 532 ** LSI2108 support I/O register 533 ** All driver functionality is supported through I/O address 534 ** 535 ** For further spec, refer to 536 ** \spec\lsi\2108 for Areca\2108\LSISAS2108_PG_NoEncryption.pdf : Chapter 8 (8-11/8-28) 537 ** \spec\lsi\2108 for Areca\2108\SAS2108_RM_20.pdf : for configuration space 538 ************************************************************************************************ 539 */ 540 /* signature of set and get firmware config */ 541 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 542 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 543 /* message code of inbound message register */ 544 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 545 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 546 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 547 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 548 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 549 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 550 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 551 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 552 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 553 /* doorbell interrupt generator */ 554 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 555 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 556 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 557 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 558 /* srb areca cdb flag */ 559 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 560 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 561 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 562 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 563 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 564 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 565 /* outbound firmware ok */ 566 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 567 /* 568 ********************************** 569 ** 570 ********************************** 571 */ 572 /* size 8 bytes */ 573 /* 32bit Scatter-Gather list */ 574 struct SG32ENTRY { /* length bit 24 == 0 */ 575 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 576 u_int32_t address; 577 }; 578 /* size 12 bytes */ 579 /* 64bit Scatter-Gather list */ 580 struct SG64ENTRY { /* length bit 24 == 1 */ 581 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 582 u_int32_t address; 583 u_int32_t addresshigh; 584 }; 585 struct SGENTRY_UNION { 586 union { 587 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 588 struct SG64ENTRY sg64entry; /* 30h */ 589 }u; 590 }; 591 /* 592 ********************************** 593 ** 594 ********************************** 595 */ 596 struct QBUFFER { 597 u_int32_t data_len; 598 u_int8_t data[124]; 599 }; 600 /* 601 ************************************************************************************************ 602 ** FIRMWARE INFO 603 ************************************************************************************************ 604 */ 605 #define ARCMSR_FW_MODEL_OFFSET 15 606 #define ARCMSR_FW_VERS_OFFSET 17 607 #define ARCMSR_FW_DEVMAP_OFFSET 21 608 #define ARCMSR_FW_CFGVER_OFFSET 25 609 610 struct FIRMWARE_INFO { 611 u_int32_t signature; /*0,00-03*/ 612 u_int32_t request_len; /*1,04-07*/ 613 u_int32_t numbers_queue; /*2,08-11*/ 614 u_int32_t sdram_size; /*3,12-15*/ 615 u_int32_t ide_channels; /*4,16-19*/ 616 char vendor[40]; /*5,20-59*/ 617 char model[8]; /*15,60-67*/ 618 char firmware_ver[16]; /*17,68-83*/ 619 char device_map[16]; /*21,84-99*/ 620 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 621 char cfgSerial[16]; /*26,104-119*/ 622 u_int32_t cfgPicStatus; /*30,120-123*/ 623 }; 624 /* (A) For cfgVersion in FIRMWARE_INFO 625 ** if low BYTE (byte#0) >= 3 (version 3) 626 ** then byte#1 report the capability of the firmware can xfer in a single request 627 ** 628 ** byte#1 629 ** 0 256K 630 ** 1 512K 631 ** 2 1M 632 ** 3 2M 633 ** 4 4M 634 ** 5 8M 635 ** 6 16M 636 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages 637 ** Driver support new xfer method need to set this field to indicate 638 ** large CDB block in 0x100 unit (we use 0x100 byte as one page) 639 ** e.g. If the length of CDB including MSG header and SGL is 0x1508 640 ** driver need to set the msgPages to 0x16 641 ** (C) REQ_LEN_512BYTE must be used also to indicate SRB length 642 ** e.g. CDB len msgPages REQ_LEN_512BYTE flag 643 ** <= 0x100 1 0 644 ** <= 0x200 2 1 645 ** <= 0x300 3 1 646 ** <= 0x400 4 1 647 ** . 648 ** . 649 */ 650 651 /* 652 ************************************************************************************************ 653 ** size 0x1F8 (504) 654 ************************************************************************************************ 655 */ 656 struct ARCMSR_CDB { 657 u_int8_t Bus; /* 00h should be 0 */ 658 u_int8_t TargetID; /* 01h should be 0--15 */ 659 u_int8_t LUN; /* 02h should be 0--7 */ 660 u_int8_t Function; /* 03h should be 1 */ 661 662 u_int8_t CdbLength; /* 04h not used now */ 663 u_int8_t sgcount; /* 05h */ 664 u_int8_t Flags; /* 06h */ 665 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 666 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 667 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 668 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 669 #define ARCMSR_CDB_FLAG_HEADQ 0x08 670 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 671 u_int8_t msgPages; /* 07h */ 672 673 u_int32_t Context; /* 08h Address of this request */ 674 u_int32_t DataLength; /* 0ch not used now */ 675 676 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 677 /* 678 ******************************************************** 679 **Device Status : the same from SCSI bus if error occur 680 ** SCSI bus status codes. 681 ******************************************************** 682 */ 683 u_int8_t DeviceStatus; /* 20h if error */ 684 #define SCSISTAT_GOOD 0x00 685 #define SCSISTAT_CHECK_CONDITION 0x02 686 #define SCSISTAT_CONDITION_MET 0x04 687 #define SCSISTAT_BUSY 0x08 688 #define SCSISTAT_INTERMEDIATE 0x10 689 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 690 #define SCSISTAT_RESERVATION_CONFLICT 0x18 691 #define SCSISTAT_COMMAND_TERMINATED 0x22 692 #define SCSISTAT_QUEUE_FULL 0x28 693 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 694 #define ARCMSR_DEV_ABORTED 0xF1 695 #define ARCMSR_DEV_INIT_FAIL 0xF2 696 697 u_int8_t SenseData[15]; /* 21h output */ 698 699 union { 700 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 701 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 702 } u; 703 }; 704 /* 705 ********************************************************************* 706 ** Command Control Block (SrbExtension) 707 ** SRB must be not cross page boundary,and the order from offset 0 708 ** structure describing an ATA disk request 709 ** this SRB length must be 32 bytes boundary 710 ********************************************************************* 711 */ 712 struct CommandControlBlock { 713 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 714 u_int32_t cdb_shifted_phyaddr; /* 504-507 */ 715 u_int32_t arc_cdb_size; /* 508-511 */ 716 /* ======================512+32 bytes============================ */ 717 #if defined(__x86_64__) || defined(__amd64__) || defined(__ia64__) || defined(__sparc64__) || defined(__powerpc__) 718 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 719 struct AdapterControlBlock *acb; /* 520-523 524-527 */ 720 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 721 u_int16_t srb_flags; /* 536-537 */ 722 u_int16_t startdone; /* 538-539 */ 723 u_int32_t reserved2; /* 540-543 */ 724 #else 725 union ccb *pccb; /* 512-515 pointer of freebsd scsi command */ 726 struct AdapterControlBlock *acb; /* 516-519 */ 727 bus_dmamap_t dm_segs_dmamap; /* 520-523 */ 728 u_int16_t srb_flags; /* 524-525 */ 729 u_int16_t startdone; /* 526-527 */ 730 u_int32_t reserved2[4]; /* 528-531 532-535 536-539 540-543 */ 731 #endif 732 /* ========================================================== */ 733 /* struct callout ccb_callout; */ 734 }; 735 /* srb_flags */ 736 #define SRB_FLAG_READ 0x0000 737 #define SRB_FLAG_WRITE 0x0001 738 #define SRB_FLAG_ERROR 0x0002 739 #define SRB_FLAG_FLUSHCACHE 0x0004 740 #define SRB_FLAG_MASTER_ABORTED 0x0008 741 #define SRB_FLAG_DMAVALID 0x0010 742 #define SRB_FLAG_DMACONSISTENT 0x0020 743 #define SRB_FLAG_DMAWRITE 0x0040 744 #define SRB_FLAG_PKTBIND 0x0080 745 /* startdone */ 746 #define ARCMSR_SRB_DONE 0x0000 747 #define ARCMSR_SRB_UNBUILD 0x0000 748 #define ARCMSR_SRB_TIMEOUT 0x1111 749 #define ARCMSR_SRB_RETRY 0x2222 750 #define ARCMSR_SRB_START 0x55AA 751 #define ARCMSR_SRB_PENDING 0xAA55 752 #define ARCMSR_SRB_RESET 0xA5A5 753 #define ARCMSR_SRB_ABORTED 0x5A5A 754 #define ARCMSR_SRB_ILLEGAL 0xFFFF 755 /* 756 ********************************************************************* 757 ** Adapter Control Block 758 ********************************************************************* 759 */ 760 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ 761 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ 762 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */ 763 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ 764 765 struct AdapterControlBlock { 766 u_int32_t adapter_type; /* adapter A,B..... */ 767 768 bus_space_tag_t btag[2]; 769 bus_space_handle_t bhandle[2]; 770 bus_dma_tag_t parent_dmat; 771 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 772 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 773 bus_dmamap_t srb_dmamap; 774 device_t pci_dev; 775 #if __FreeBSD_version < 503000 776 dev_t ioctl_dev; 777 #else 778 struct cdev * ioctl_dev; 779 #endif 780 int pci_unit; 781 782 struct resource * sys_res_arcmsr[2]; 783 struct resource * irqres; 784 void * ih; /* interrupt handle */ 785 786 /* Hooks into the CAM XPT */ 787 struct cam_sim *psim; 788 struct cam_path *ppath; 789 u_int8_t * uncacheptr; 790 unsigned long vir2phy_offset; 791 union { 792 unsigned long phyaddr; 793 struct { 794 u_int32_t phyadd_low; 795 u_int32_t phyadd_high; 796 }B; 797 } srb_phyaddr; 798 // unsigned long srb_phyaddr; 799 /* Offset is used in making arc cdb physical to virtual calculations */ 800 u_int32_t outbound_int_enable; 801 802 struct MessageUnit_UNION * pmu; /* message unit ATU inbound base address0 */ 803 804 u_int8_t adapter_index; /* */ 805 u_int8_t irq; 806 u_int16_t acb_flags; /* */ 807 808 struct CommandControlBlock * psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 809 struct CommandControlBlock * srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 810 int32_t workingsrb_doneindex; /* done srb array index */ 811 int32_t workingsrb_startindex; /* start srb array index */ 812 int32_t srboutstandingcount; 813 814 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 815 u_int32_t rqbuf_firstindex; /* first of read buffer */ 816 u_int32_t rqbuf_lastindex; /* last of read buffer */ 817 818 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 819 u_int32_t wqbuf_firstindex; /* first of write buffer */ 820 u_int32_t wqbuf_lastindex; /* last of write buffer */ 821 822 arcmsr_lock_t workingQ_done_lock; 823 arcmsr_lock_t workingQ_start_lock; 824 arcmsr_lock_t qbuffer_lock; 825 826 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 827 u_int32_t num_resets; 828 u_int32_t num_aborts; 829 u_int32_t firm_request_len; /*1,04-07*/ 830 u_int32_t firm_numbers_queue; /*2,08-11*/ 831 u_int32_t firm_sdram_size; /*3,12-15*/ 832 u_int32_t firm_ide_channels; /*4,16-19*/ 833 u_int32_t firm_cfg_version; 834 char firm_model[12]; /*15,60-67*/ 835 char firm_version[20]; /*17,68-83*/ 836 char device_map[20]; /*21,84-99 */ 837 struct callout devmap_callout; 838 };/* HW_DEVICE_EXTENSION */ 839 /* acb_flags */ 840 #define ACB_F_SCSISTOPADAPTER 0x0001 841 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 842 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 843 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 844 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 845 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 846 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 847 #define ACB_F_BUS_RESET 0x0080 848 #define ACB_F_IOP_INITED 0x0100 /* iop init */ 849 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 850 #define ACB_F_CAM_DEV_QFRZN 0x0400 851 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 852 #define ACB_F_SRB_FUNCTION_POWER 0x1000 853 /* devstate */ 854 #define ARECA_RAID_GONE 0x55 855 #define ARECA_RAID_GOOD 0xaa 856 /* 857 ********************************************************************* 858 ** Message Unit structure 859 ********************************************************************* 860 */ 861 struct HBA_MessageUnit 862 { 863 u_int32_t resrved0[4]; /*0000 000F*/ 864 u_int32_t inbound_msgaddr0; /*0010 0013*/ 865 u_int32_t inbound_msgaddr1; /*0014 0017*/ 866 u_int32_t outbound_msgaddr0; /*0018 001B*/ 867 u_int32_t outbound_msgaddr1; /*001C 001F*/ 868 u_int32_t inbound_doorbell; /*0020 0023*/ 869 u_int32_t inbound_intstatus; /*0024 0027*/ 870 u_int32_t inbound_intmask; /*0028 002B*/ 871 u_int32_t outbound_doorbell; /*002C 002F*/ 872 u_int32_t outbound_intstatus; /*0030 0033*/ 873 u_int32_t outbound_intmask; /*0034 0037*/ 874 u_int32_t reserved1[2]; /*0038 003F*/ 875 u_int32_t inbound_queueport; /*0040 0043*/ 876 u_int32_t outbound_queueport; /*0044 0047*/ 877 u_int32_t reserved2[2]; /*0048 004F*/ 878 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 879 u_int32_t reserved4[128]; /*0800 09FF 128*/ 880 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 881 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 882 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 883 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 884 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 885 }; 886 /* 887 ********************************************************************* 888 ** 889 ********************************************************************* 890 */ 891 struct HBB_DOORBELL 892 { 893 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ 894 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 895 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 896 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 897 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 898 }; 899 /* 900 ********************************************************************* 901 ** 902 ********************************************************************* 903 */ 904 struct HBB_RWBUFFER 905 { 906 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ 907 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 908 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 909 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 910 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 911 }; 912 /* 913 ********************************************************************* 914 ** 915 ********************************************************************* 916 */ 917 struct HBB_MessageUnit 918 { 919 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 920 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 921 int32_t postq_index; /* post queue index */ 922 int32_t doneq_index; /* done queue index */ 923 struct HBB_DOORBELL *hbb_doorbell; 924 struct HBB_RWBUFFER *hbb_rwbuffer; 925 }; 926 927 /* 928 ********************************************************************* 929 ** 930 ********************************************************************* 931 */ 932 struct HBC_MessageUnit { 933 u_int32_t message_unit_status; /*0000 0003*/ 934 u_int32_t slave_error_attribute; /*0004 0007*/ 935 u_int32_t slave_error_address; /*0008 000B*/ 936 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 937 u_int32_t master_error_attribute; /*0010 0013*/ 938 u_int32_t master_error_address_low; /*0014 0017*/ 939 u_int32_t master_error_address_high; /*0018 001B*/ 940 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 941 u_int32_t inbound_doorbell; /*0020 0023*/ 942 u_int32_t diagnostic_rw_data; /*0024 0027*/ 943 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 944 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 945 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 946 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 947 u_int32_t dcr_data; /*0038 003B*/ 948 u_int32_t dcr_address; /*003C 003F*/ 949 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 950 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 951 u_int32_t hcb_pci_address_low; /*0048 004B*/ 952 u_int32_t hcb_pci_address_high; /*004C 004F*/ 953 u_int32_t iop_int_status; /*0050 0053*/ 954 u_int32_t iop_int_mask; /*0054 0057*/ 955 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 956 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 957 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 958 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 959 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 960 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 961 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 962 u_int32_t i2o_message_unit_control; /*0074 0077*/ 963 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 964 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 965 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 966 u_int32_t message_dest_address_index; /*0090 0093*/ 967 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 968 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 969 u_int32_t outbound_doorbell; /*009C 009F*/ 970 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 971 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 972 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 973 u_int32_t reserved0; /*00AC 00AF*/ 974 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 975 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 976 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 977 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 978 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 979 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 980 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 981 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 982 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 983 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 984 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 985 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 986 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 987 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 988 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 989 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 990 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 991 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 992 u_int32_t host_diagnostic; /*00F8 00FB*/ 993 u_int32_t write_sequence; /*00FC 00FF*/ 994 u_int32_t reserved1[34]; /*0100 0187*/ 995 u_int32_t reserved2[1950]; /*0188 1FFF*/ 996 u_int32_t message_wbuffer[32]; /*2000 207F*/ 997 u_int32_t reserved3[32]; /*2080 20FF*/ 998 u_int32_t message_rbuffer[32]; /*2100 217F*/ 999 u_int32_t reserved4[32]; /*2180 21FF*/ 1000 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 1001 }; 1002 1003 /* 1004 ********************************************************************* 1005 ** 1006 ********************************************************************* 1007 */ 1008 struct MessageUnit_UNION 1009 { 1010 union { 1011 struct HBA_MessageUnit hbamu; 1012 struct HBB_MessageUnit hbbmu; 1013 struct HBC_MessageUnit hbcmu; 1014 } muu; 1015 }; 1016 1017 /* 1018 ************************************************************* 1019 ************************************************************* 1020 */ 1021 struct SENSE_DATA { 1022 u_int8_t ErrorCode:7; 1023 u_int8_t Valid:1; 1024 u_int8_t SegmentNumber; 1025 u_int8_t SenseKey:4; 1026 u_int8_t Reserved:1; 1027 u_int8_t IncorrectLength:1; 1028 u_int8_t EndOfMedia:1; 1029 u_int8_t FileMark:1; 1030 u_int8_t Information[4]; 1031 u_int8_t AdditionalSenseLength; 1032 u_int8_t CommandSpecificInformation[4]; 1033 u_int8_t AdditionalSenseCode; 1034 u_int8_t AdditionalSenseCodeQualifier; 1035 u_int8_t FieldReplaceableUnitCode; 1036 u_int8_t SenseKeySpecific[3]; 1037 }; 1038 /* 1039 ********************************** 1040 ** Peripheral Device Type definitions 1041 ********************************** 1042 */ 1043 #define SCSI_DASD 0x00 /* Direct-access Device */ 1044 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 1045 #define SCSI_PRINTER 0x02 /* Printer device */ 1046 #define SCSI_PROCESSOR 0x03 /* Processor device */ 1047 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 1048 #define SCSI_CDROM 0x05 /* CD-ROM device */ 1049 #define SCSI_SCANNER 0x06 /* Scanner device */ 1050 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 1051 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 1052 #define SCSI_COMM 0x09 /* Communications device */ 1053 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 1054 /* 1055 ************************************************************************************************************ 1056 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1057 ** 80331 PCI-to-PCI Bridge 1058 ** PCI Configuration Space 1059 ** 1060 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1061 ** Programming Interface 1062 ** ======================== 1063 ** Configuration Register Address Space Groupings and Ranges 1064 ** ============================================================= 1065 ** Register Group Configuration Offset 1066 ** ------------------------------------------------------------- 1067 ** Standard PCI Configuration 00-3Fh 1068 ** ------------------------------------------------------------- 1069 ** Device Specific Registers 40-A7h 1070 ** ------------------------------------------------------------- 1071 ** Reserved A8-CBh 1072 ** ------------------------------------------------------------- 1073 ** Enhanced Capability List CC-FFh 1074 ** ========================================================================================================== 1075 ** Standard PCI [Type 1] Configuration Space Address Map 1076 ** ********************************************************************************************************** 1077 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1078 ** ---------------------------------------------------------------------------------------------------------- 1079 ** | Device ID | Vendor ID | 00h 1080 ** ---------------------------------------------------------------------------------------------------------- 1081 ** | Primary Status | Primary Command | 04h 1082 ** ---------------------------------------------------------------------------------------------------------- 1083 ** | Class Code | RevID | 08h 1084 ** ---------------------------------------------------------------------------------------------------------- 1085 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 1086 ** ---------------------------------------------------------------------------------------------------------- 1087 ** | Reserved | 10h 1088 ** ---------------------------------------------------------------------------------------------------------- 1089 ** | Reserved | 14h 1090 ** ---------------------------------------------------------------------------------------------------------- 1091 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 1092 ** ---------------------------------------------------------------------------------------------------------- 1093 ** | Secondary Status | I/O Limit | I/O Base | 1Ch 1094 ** ---------------------------------------------------------------------------------------------------------- 1095 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 1096 ** ---------------------------------------------------------------------------------------------------------- 1097 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 1098 ** ---------------------------------------------------------------------------------------------------------- 1099 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h 1100 ** ---------------------------------------------------------------------------------------------------------- 1101 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 1102 ** ---------------------------------------------------------------------------------------------------------- 1103 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 1104 ** ---------------------------------------------------------------------------------------------------------- 1105 ** | Reserved | Capabilities Pointer | 34h 1106 ** ---------------------------------------------------------------------------------------------------------- 1107 ** | Reserved | 38h 1108 ** ---------------------------------------------------------------------------------------------------------- 1109 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 1110 **============================================================================================================= 1111 */ 1112 /* 1113 **============================================================================================================= 1114 ** 0x03-0x00 : 1115 ** Bit Default Description 1116 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 1117 ** ID is unique per product speed as indicated. 1118 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 1119 **============================================================================================================= 1120 */ 1121 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 1122 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 1123 /* 1124 **============================================================================== 1125 ** 0x05-0x04 : command register 1126 ** Bit Default Description 1127 **15:11 00h Reserved 1128 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 1129 ** The bridge does not support interrupts. 1130 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 1131 ** transactions on the primary bus. 1132 ** The bridge does not generate fast back to back 1133 ** transactions on the primary bus. 1134 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 1135 ** 0=The bridge does not assert P_SERR#. 1136 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 1137 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 1138 ** that bridge does not perform address or data stepping, 1139 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 1140 ** 0=When a data parity error is detected bridge does not assert S_PERR#. 1141 ** Also bridge does not assert P_SERR# in response to 1142 ** a detected address or attribute parity error. 1143 ** 1=When a data parity error is detected bridge asserts S_PERR#. 1144 ** The bridge also asserts P_SERR# 1145 ** (when enabled globally via bit(8) of this register) 1146 ** in response to a detected address or attribute parity error. 1147 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 1148 ** VGA palette write transactions are I/O transactions 1149 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 1150 ** P_AD[15:10] are not decoded (i.e. aliases are claimed), 1151 ** or are fully decoding 1152 ** (i.e., must be all 0's depending upon the VGA 1153 ** aliasing bit in the Bridge Control Register, offset 3Eh. 1154 ** P_AD[31:16] equal to 0000h 1155 ** 0=The bridge ignores VGA palette write transactions, 1156 ** unless decoded by the standard I/O address range window. 1157 ** 1=The bridge responds to VGA palette write transactions 1158 ** with medium DEVSEL# timing and forwards them to the secondary bus. 1159 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 1160 ** MWI transactions targeting resources on the opposite side of the bridge, 1161 ** however, are forwarded as MWI transactions. 1162 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 1163 ** This bit is read only and always returns 0 when read 1164 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 1165 ** Initiation of configuration transactions is not affected by the state of this bit. 1166 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 1167 ** 1=The bridge is enabled to function as an initiator on the primary interface. 1168 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 1169 ** 0=The bridge target response to memory transactions on the primary interface is disabled. 1170 ** 1=The bridge target response to memory transactions on the primary interface is enabled. 1171 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 1172 ** 0=The bridge target response to I/O transactions on the primary interface is disabled. 1173 ** 1=The bridge target response to I/O transactions on the primary interface is enabled. 1174 **============================================================================== 1175 */ 1176 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 1177 #define PCI_DISABLE_INTERRUPT 0x0400 1178 /* 1179 **============================================================================== 1180 ** 0x07-0x06 : status register 1181 ** Bit Default Description 1182 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1183 ** attribute or data parity error. 1184 ** This bit is set regardless of the state of the PER bit in the command register. 1185 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 1186 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 1187 ** acting as the initiator on the primary bus, 1188 ** its transaction (with the exception of special cycles) 1189 ** has been terminated with a Master Abort. 1190 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 1191 ** acting as the initiator on the primary bus, 1192 ** its transaction has been terminated with a Target Abort. 1193 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 1194 ** as the target of a transaction, terminates it with a Target Abort. 1195 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1196 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 1197 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1198 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1199 ** The bridge is the current master on the primary bus 1200 ** S_PERR# is detected asserted or is asserted by bridge 1201 ** The Parity Error Response bit is set in the Command register 1202 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 1203 ** is able to respond to fast back to back transactions on its primary interface. 1204 ** 06 0 Reserved 1205 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 1206 ** 1 = 1207 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 1208 ** Offset 34h (Capability Pointer register) 1209 ** provides the offset for the first entry 1210 ** in the linked list of enhanced capabilities. 1211 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 1212 ** The bridge does not support interrupts. 1213 ** 02:00 000 Reserved 1214 **============================================================================== 1215 */ 1216 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 1217 #define ARCMSR_ADAP_66MHZ 0x20 1218 /* 1219 **============================================================================== 1220 ** 0x08 : revision ID 1221 ** Bit Default Description 1222 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 1223 **============================================================================== 1224 */ 1225 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 1226 /* 1227 **============================================================================== 1228 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 1229 ** Bit Default Description 1230 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 1231 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 1232 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 1233 **============================================================================== 1234 */ 1235 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 1236 /* 1237 **============================================================================== 1238 ** 0x0c : cache line size 1239 ** Bit Default Description 1240 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 1241 ** The contents of this register are factored into 1242 ** internal policy decisions associated with memory read prefetching, 1243 ** and the promotion of Memory Write transactions to MWI transactions. 1244 ** Valid cache line sizes are 8 and 16 dwords. 1245 ** When the cache line size is set to an invalid value, 1246 ** bridge behaves as though the cache line size was set to 00h. 1247 **============================================================================== 1248 */ 1249 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 1250 /* 1251 **============================================================================== 1252 ** 0x0d : latency timer (number of pci clock 00-ff ) 1253 ** Bit Default Description 1254 ** Primary Latency Timer (PTV): 1255 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 1256 ** referenced from the assertion of FRAME# to the expiration of the timer, 1257 ** when bridge may continue as master of the current transaction. All bits are writable, 1258 ** resulting in a granularity of 1 PCI clock cycle. 1259 ** When the timer expires (i.e., equals 00h) 1260 ** bridge relinquishes the bus after the first data transfer 1261 ** when its PCI bus grant has been deasserted. 1262 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 1263 ** Indicates the number of PCI clock cycles, 1264 ** referenced from the assertion of FRAME# to the expiration of the timer, 1265 ** when bridge may continue as master of the current transaction. 1266 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 1267 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1268 ** (Except in the case where MLT expires within 3 data phases 1269 ** of an ADB.In this case bridge continues on 1270 ** until it reaches the next ADB before relinquishing the bus.) 1271 **============================================================================== 1272 */ 1273 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 1274 /* 1275 **============================================================================== 1276 ** 0x0e : (header type,single function ) 1277 ** Bit Default Description 1278 ** 07 0 Multi-function device (MVD): 80331 is a single-function device. 1279 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 1280 ** Returns ��01h�� when read indicating 1281 ** that the register layout conforms to the standard PCI-to-PCI bridge layout. 1282 **============================================================================== 1283 */ 1284 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 1285 /* 1286 **============================================================================== 1287 ** 0x0f : 1288 **============================================================================== 1289 */ 1290 /* 1291 **============================================================================== 1292 ** 0x13-0x10 : 1293 ** PCI CFG Base Address #0 (0x10) 1294 **============================================================================== 1295 */ 1296 /* 1297 **============================================================================== 1298 ** 0x17-0x14 : 1299 ** PCI CFG Base Address #1 (0x14) 1300 **============================================================================== 1301 */ 1302 /* 1303 **============================================================================== 1304 ** 0x1b-0x18 : 1305 ** PCI CFG Base Address #2 (0x18) 1306 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR 1307 ** Bit Default Description 1308 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 1309 ** Any Type 1 configuration cycle 1310 ** on the primary bus whose bus number is greater than the secondary bus number, 1311 ** and less than or equal to the subordinate bus number 1312 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 1313 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 1314 ** Any Type 1 configuration cycle matching this bus number 1315 ** is translated to a Type 0 configuration cycle (or a Special Cycle) 1316 ** before being executed on bridge's secondary PCI bus. 1317 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 1318 ** Any Type 1 configuration cycle on the primary interface 1319 ** with a bus number that is less than the contents 1320 ** of this register field does not be claimed by bridge. 1321 **-----------------0x1B--Secondary Latency Timer Register - SLTR 1322 ** Bit Default Description 1323 ** Secondary Latency Timer (STV): 1324 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 1325 ** Indicates the number of PCI clock cycles, 1326 ** referenced from the assertion of FRAME# to the expiration of the timer, 1327 ** when bridge may continue as master of the current transaction. All bits are writable, 1328 ** resulting in a granularity of 1 PCI clock cycle. 1329 ** When the timer expires (i.e., equals 00h) 1330 ** bridge relinquishes the bus after the first data transfer 1331 ** when its PCI bus grant has been deasserted. 1332 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 1333 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 1334 ** to the expiration of the timer, 1335 ** when bridge may continue as master of the current transaction. All bits are writable, 1336 ** resulting in a granularity of 1 PCI clock cycle. 1337 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1338 ** (Except in the case where MLT expires within 3 data phases of an ADB. 1339 ** In this case bridge continues on until it reaches the next ADB 1340 ** before relinquishing the bus) 1341 **============================================================================== 1342 */ 1343 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 1344 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 1345 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 1346 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 1347 /* 1348 **============================================================================== 1349 ** 0x1f-0x1c : 1350 ** PCI CFG Base Address #3 (0x1C) 1351 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 1352 ** Bit Default Description 1353 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 1354 ** determine when to forward I/O transactions from one interface to the other. 1355 ** These bits correspond to address lines 15:12 for 4KB alignment. 1356 ** Bits 11:0 are assumed to be FFFh. 1357 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 1358 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 1359 ** an address range to determine when to forward I/O transactions 1360 ** from one interface to the other. 1361 ** These bits correspond to address lines 15:12 for 4KB alignment. 1362 ** Bits 11:0 are assumed to be 000h. 1363 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 1364 **-----------------0x1F,0x1E--Secondary Status Register - SSR 1365 ** Bit Default Description 1366 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1367 ** attribute or data parity error on its secondary interface. 1368 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 1369 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 1370 ** acting as the initiator on the secondary bus, 1371 ** it's transaction (with the exception of special cycles) 1372 ** has been terminated with a Master Abort. 1373 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 1374 ** acting as the initiator on the secondary bus, 1375 ** it's transaction has been terminated with a Target Abort. 1376 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 1377 ** as the target of a transaction, terminates it with a Target Abort. 1378 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1379 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 1380 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1381 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1382 ** The bridge is the current master on the secondary bus 1383 ** S_PERR# is detected asserted or is asserted by bridge 1384 ** The Parity Error Response bit is set in the Command register 1385 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 1386 ** 06 0b Reserved 1387 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 1388 ** 1 = 1389 ** 04:00 00h Reserved 1390 **============================================================================== 1391 */ 1392 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 1393 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 1394 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 1395 /* 1396 **============================================================================== 1397 ** 0x23-0x20 : 1398 ** PCI CFG Base Address #4 (0x20) 1399 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 1400 ** Bit Default Description 1401 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1402 ** the upper 1MB aligned value (exclusive) of the range. 1403 ** The incoming address must be less than or equal to this value. 1404 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1405 ** are assumed to be F FFFFh. 1406 ** 19:16 0h Reserved. 1407 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 1408 ** of the incoming address to determine the lower 1MB 1409 ** aligned value (inclusive) of the range. 1410 ** The incoming address must be greater than or equal to this value. 1411 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1412 ** are assumed to be 0 0000h. 1413 ** 03:00 0h Reserved. 1414 **============================================================================== 1415 */ 1416 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 1417 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 1418 /* 1419 **============================================================================== 1420 ** 0x27-0x24 : 1421 ** PCI CFG Base Address #5 (0x24) 1422 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 1423 ** Bit Default Description 1424 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1425 ** the upper 1MB aligned value (exclusive) of the range. 1426 ** The incoming address must be less than or equal to this value. 1427 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1428 ** are assumed to be F FFFFh. 1429 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1430 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 1431 ** of the incoming address to determine the lower 1MB aligned value (inclusive) 1432 ** of the range. 1433 ** The incoming address must be greater than or equal to this value. 1434 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1435 ** are assumed to be 0 0000h. 1436 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1437 **============================================================================== 1438 */ 1439 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 1440 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 1441 /* 1442 **============================================================================== 1443 ** 0x2b-0x28 : 1444 ** Bit Default Description 1445 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 1446 ** bridge supports full 64-bit addressing. 1447 **============================================================================== 1448 */ 1449 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 1450 /* 1451 **============================================================================== 1452 ** 0x2f-0x2c : 1453 ** Bit Default Description 1454 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 1455 ** bridge supports full 64-bit addressing. 1456 **============================================================================== 1457 */ 1458 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 1459 /* 1460 **============================================================================== 1461 ** 0x33-0x30 : 1462 ** Bit Default Description 1463 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 1464 ** space. (Power Management Capability Registers) 1465 **============================================================================== 1466 */ 1467 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 1468 /* 1469 **============================================================================== 1470 ** 0x3b-0x35 : reserved 1471 **============================================================================== 1472 */ 1473 /* 1474 **============================================================================== 1475 ** 0x3d-0x3c : 1476 ** 1477 ** Bit Default Description 1478 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1479 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1480 **============================================================================== 1481 */ 1482 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1483 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1484 /* 1485 **============================================================================== 1486 ** 0x3f-0x3e : 1487 ** Bit Default Description 1488 ** 15:12 0h Reserved 1489 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1490 ** to a timer discard on either the primary or secondary interface. 1491 ** 0b=SERR# is not asserted. 1492 ** 1b=SERR# is asserted. 1493 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1494 ** The delayed completion is then discarded. 1495 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1496 ** that bridge waits for an initiator on the secondary bus 1497 ** to repeat a delayed transaction request. 1498 ** The counter starts when the delayed transaction completion is ready 1499 ** to be returned to the initiator. 1500 ** When the initiator has not repeated the transaction 1501 ** at least once before the counter expires,bridge 1502 ** discards the delayed transaction from its queues. 1503 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1504 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1505 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1506 ** that bridge waits for an initiator on the primary bus 1507 ** to repeat a delayed transaction request. 1508 ** The counter starts when the delayed transaction completion 1509 ** is ready to be returned to the initiator. 1510 ** When the initiator has not repeated the transaction 1511 ** at least once before the counter expires, 1512 ** bridge discards the delayed transaction from its queues. 1513 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1514 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1515 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1516 ** 06 0b Secondary Bus Reset (SBR): 1517 ** When cleared to 0b: The bridge deasserts S_RST#, 1518 ** when it had been asserted by writing this bit to a 1b. 1519 ** When set to 1b: The bridge asserts S_RST#. 1520 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1521 ** when a master abort termination occurs in response to 1522 ** a delayed transaction initiated by bridge on the target bus. 1523 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1524 ** and returns FFFF FFFFh when a read. 1525 ** 1b=When the transaction had not yet been completed on the initiator bus 1526 ** (e.g.,delayed reads, or non-posted writes), 1527 ** then bridge returns a Target Abort in response to the original requester 1528 ** when it returns looking for its delayed completion on the initiator bus. 1529 ** When the transaction had completed on the initiator bus (e.g., a PMW), 1530 ** then bridge asserts P_SERR# (when enabled). 1531 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1532 ** while attempting to deliver a posted memory write on the destination bus. 1533 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1534 ** (also of this register), 1535 ** and the VGA Palette Snoop Enable bit (Command Register). 1536 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 1537 ** the VGA Aliasing bit for the corresponding enabled functionality,: 1538 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1539 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1540 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 1541 ** then this bit has no impact on bridge behavior. 1542 ** 03 0b VGA Enable: Setting this bit enables address decoding 1543 ** and transaction forwarding of the following VGA transactions from the primary bus 1544 ** to the secondary bus: 1545 ** frame buffer memory addresses 000A0000h:000BFFFFh, 1546 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares), 1547 ** or must be ��000000b�� 1548 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1549 ** I/O and Memory Enable bits must be set in the Command register 1550 ** to enable forwarding of VGA cycles. 1551 ** 02 0b ISA Enable: Setting this bit enables special handling 1552 ** for the forwarding of ISA I/O transactions that fall within the address range 1553 ** specified by the I/O Base and Limit registers, 1554 ** and are within the lowest 64Kbyte of the I/O address map 1555 ** (i.e., 0000 0000h - 0000 FFFFh). 1556 ** 0b=All I/O transactions that fall within the I/O Base 1557 ** and Limit registers' specified range are forwarded 1558 ** from primary to secondary unfiltered. 1559 ** 1b=Blocks the forwarding from primary to secondary 1560 ** of the top 768 bytes of each 1Kbyte alias. 1561 ** On the secondary the top 768 bytes of each 1K alias 1562 ** are inversely decoded and forwarded 1563 ** from secondary to primary. 1564 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1565 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 1566 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1567 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error 1568 ** that is detected on its secondary interface. 1569 ** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1570 ** Also bridge does not assert P_SERR# in response to a detected address 1571 ** or attribute parity error. 1572 ** 1b=When a data parity error is detected bridge asserts S_PERR#. 1573 ** The bridge also asserts P_SERR# (when enabled globally via bit(8) 1574 ** of the Command register) 1575 ** in response to a detected address or attribute parity error. 1576 **============================================================================== 1577 */ 1578 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 1579 /* 1580 ************************************************************************** 1581 ** Device Specific Registers 40-A7h 1582 ************************************************************************** 1583 ** ---------------------------------------------------------------------------------------------------------- 1584 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1585 ** ---------------------------------------------------------------------------------------------------------- 1586 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 1587 ** ---------------------------------------------------------------------------------------------------------- 1588 ** | Bridge Control 2 | Bridge Control 1 | 44h 1589 ** ---------------------------------------------------------------------------------------------------------- 1590 ** | Reserved | Bridge Status | 48h 1591 ** ---------------------------------------------------------------------------------------------------------- 1592 ** | Reserved | 4Ch 1593 ** ---------------------------------------------------------------------------------------------------------- 1594 ** | Prefetch Policy | Multi-Transaction Timer | 50h 1595 ** ---------------------------------------------------------------------------------------------------------- 1596 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 1597 ** ---------------------------------------------------------------------------------------------------------- 1598 ** | Reserved | Reserved | Secondary Decode Enable | 58h 1599 ** ---------------------------------------------------------------------------------------------------------- 1600 ** | Reserved | Secondary IDSEL | 5Ch 1601 ** ---------------------------------------------------------------------------------------------------------- 1602 ** | Reserved | 5Ch 1603 ** ---------------------------------------------------------------------------------------------------------- 1604 ** | Reserved | 68h:CBh 1605 ** ---------------------------------------------------------------------------------------------------------- 1606 ************************************************************************** 1607 **============================================================================== 1608 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 1609 ** Bit Default Description 1610 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 1611 ** (PCI=16 clocks,PCI-X=6 clocks). 1612 ** Note that this field is only meaningful when: 1613 ** # Bit[11] of this register is set to 1b, 1614 ** indicating that a Grant Time-out violation had occurred. 1615 ** # bridge internal arbiter is enabled. 1616 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 1617 ** 0000b REQ#/GNT#[0] 1618 ** 0001b REQ#/GNT#[1] 1619 ** 0010b REQ#/GNT#[2] 1620 ** 0011b REQ#/GNT#[3] 1621 ** 1111b Default Value (no violation detected) 1622 ** When bit[11] is cleared by software, this field reverts back to its default value. 1623 ** All other values are Reserved 1624 ** 11 0b Grant Time-out Occurred: When set to 1b, 1625 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 1626 ** Software clears this bit by writing a 1b to it. 1627 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 1628 ** 1=During bus idle, bridge parks the bus on itself. 1629 ** The bus grant is removed from the last master and internally asserted to bridge. 1630 ** 09:08 00b Reserved 1631 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 1632 ** Each bit of this field assigns its corresponding secondary 1633 ** bus master to either the high priority arbiter ring (1b) 1634 ** or to the low priority arbiter ring (0b). 1635 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 1636 ** Bit [6] corresponds to the bridge internal secondary bus request 1637 ** while Bit [7] corresponds to the SATU secondary bus request. 1638 ** Bits [5:4] are unused. 1639 ** 0b=Indicates that the master belongs to the low priority group. 1640 ** 1b=Indicates that the master belongs to the high priority group 1641 **================================================================================= 1642 ** 0x43: Bridge Control Register 0 - BCR0 1643 ** Bit Default Description 1644 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 1645 ** and the Posted Write data is limited to 4KB. 1646 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 1647 ** 14 Posted Memory Write transactions and 8KB of posted write data. 1648 ** 06:03 0H Reserved. 1649 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 1650 ** to perform upstream prefetch operations for Memory 1651 ** Read requests received on its secondary interface. 1652 ** This bit also controls the bridge's ability to generate advanced read commands 1653 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 1654 ** to a Conventional PCI bus. 1655 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 1656 ** The use of Memory Read Line and Memory Read 1657 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request 1658 ** to an upstream bus operating in Conventional PCI mode. 1659 ** 1b=bridge treats upstream PCI Memory Read requests as though 1660 ** they target non-prefetchable memory and forwards upstream PCI-X Memory 1661 ** Read Block commands as Memory Read 1662 ** when the primary bus is operating 1663 ** in Conventional PCI mode. 1664 ** NOTE: This bit does not affect bridge ability to perform read prefetching 1665 ** when the received command is Memory Read Line or Memory Read Multiple. 1666 **================================================================================= 1667 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 1668 ** Bit Default Description 1669 ** 15:08 0000000b Reserved 1670 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, 1671 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 1672 ** The three options for handling these alias commands are to either pass it as is, 1673 ** re-map to the actual block memory read/write command encoding, or ignore 1674 ** the transaction forcing a Master Abort to occur on the Origination Bus. 1675 ** Bit (7:6) Handling of command 1676 ** 0 0 Re-map to Memory Read/Write Block before forwarding 1677 ** 0 1 Enqueue and forward the alias command code unaltered 1678 ** 1 0 Ignore the transaction, forcing Master Abort 1679 ** 1 1 Reserved 1680 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 1681 ** The watchdog timers are used to detect prohibitively long latencies in the system. 1682 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 1683 ** or Split Requests (PCI-X mode) is not completed within 2 24 events 1684 ** (��events�� are defined as PCI Clocks when operating in PCI-X mode, 1685 ** and as the number of times being retried when operating in Conventional PCI mode) 1686 ** 0b=All 2 24 watchdog timers are enabled. 1687 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to 1688 ** the number of attempts bridge makes when initiating a PMW, 1689 ** transacting a Delayed Transaction, or how long it waits for 1690 ** a split completion corresponding to one of its requests. 1691 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 1692 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 1693 ** 0b=The Secondary bus arbiter times out an agent 1694 ** that does not assert FRAME# within 16/6 clocks of receiving its grant, 1695 ** once the bus has gone idle. 1696 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 1697 ** An infringing agent does not receive a subsequent GNT# 1698 ** until it de-asserts its REQ# for at least one clock cycle. 1699 ** 1b=GNT# time-out mechanism is disabled. 1700 ** 03 00b Reserved. 1701 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 1702 ** The time out mechanism is used to ensure that initiators 1703 ** of delayed transactions return for their delayed completion data/status 1704 ** within a reasonable amount of time after it is available from bridge. 1705 ** 0b=The secondary master time-out counter is enabled 1706 ** and uses the value specified by the Secondary Discard Timer bit 1707 ** (see Bridge Control Register). 1708 ** 1b=The secondary master time-out counter is disabled. 1709 ** The bridge waits indefinitely for a secondary bus master 1710 ** to repeat a delayed transaction. 1711 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 1712 ** The time out mechanism is used to ensure that initiators 1713 ** of delayed transactions return for their delayed completion data/status 1714 ** within a reasonable amount of time after it is available from bridge. 1715 ** 0b=The primary master time-out counter is enabled and uses the value specified 1716 ** by the Primary Discard Timer bit (see Bridge Control Register). 1717 ** 1b=The secondary master time-out counter is disabled. 1718 ** The bridge waits indefinitely for a secondary bus master 1719 ** to repeat a delayed transaction. 1720 ** 00 0b Reserved 1721 **================================================================================= 1722 ** 0x47-0x46: Bridge Control Register 2 - BCR2 1723 ** Bit Default Description 1724 ** 15:07 0000b Reserved. 1725 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 1726 ** This bit disables all of the secondary PCI clock outputs including 1727 ** the feedback clock S_CLKOUT. 1728 ** This means that the user is required to provide an S_CLKIN input source. 1729 ** 05:04 11 (66 MHz) Preserved. 1730 ** 01 (100 MHz) 1731 ** 00 (133 MHz) 1732 ** 03:00 Fh (100 MHz & 66 MHz) 1733 ** 7h (133 MHz) 1734 ** This 4 bit field provides individual enable/disable mask bits for each of bridge 1735 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 1736 ** default to being enabled following the rising edge of P_RST#, depending on the 1737 ** frequency of the secondary bus clock: 1738 ** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with 1739 ** all four S_CLKOs enabled by default. (SCLKO[3:0])�P 1740 ** �E Designs with 133 MHz Secondary PCI clock power up 1741 ** with the lower order 3 S_CLKOs enabled by default. 1742 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 1743 ** to downstream device clock inputs. 1744 **================================================================================= 1745 ** 0x49-0x48: Bridge Status Register - BSR 1746 ** Bit Default Description 1747 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1748 ** is conditionally asserted when the secondary discard timer expires. 1749 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 1750 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1751 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 1752 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1753 ** when bridge discards an upstream split read request 1754 ** after waiting in excess of 2 24 clocks for the corresponding 1755 ** Split Completion to arrive. 1756 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 1757 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1758 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 1759 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 1760 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 1761 ** Split Completion to arrive. 1762 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1763 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1764 ** by bridge, to retire a PMW upstream. 1765 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1766 ** is conditionally asserted when a Target Abort occurs as a result of an attempt, 1767 ** by bridge, to retire a PMW upstream. 1768 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1769 ** is conditionally asserted when bridge discards an upstream PMW transaction 1770 ** after receiving 2 24 target retries from the primary bus target 1771 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1772 ** is conditionally asserted when a data parity error is detected by bridge 1773 ** while attempting to retire a PMW upstream 1774 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 1775 ** is conditionally asserted when bridge detects an address parity error on 1776 ** the secondary bus. 1777 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1778 ** is conditionally asserted when the primary bus discard timer expires. 1779 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 1780 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1781 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 1782 ** from the secondary bus target. 1783 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1784 ** when bridge discards a downstream split read request 1785 ** after waiting in excess of 2 24 clocks for the corresponding 1786 ** Split Completion to arrive. 1787 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 1788 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1789 ** when bridge discards a downstream delayed write transaction request 1790 ** after receiving 2 24 target retries from the secondary bus target. 1791 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 1792 ** is conditionally asserted when bridge discards a downstream 1793 ** split write request after waiting in excess of 2 24 clocks 1794 ** for the corresponding Split Completion to arrive. 1795 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 1796 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1797 ** by bridge, to retire a PMW downstream. 1798 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 1799 ** when a Target Abort occurs as a result of an attempt, by bridge, 1800 ** to retire a PMW downstream. 1801 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1802 ** is conditionally asserted when bridge discards a downstream PMW transaction 1803 ** after receiving 2 24 target retries from the secondary bus target 1804 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1805 ** is conditionally asserted when a data parity error is detected by bridge 1806 ** while attempting to retire a PMW downstream. 1807 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 1808 ** when bridge detects an address parity error on the primary bus. 1809 **================================================================================== 1810 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 1811 ** Bit Default Description 1812 ** 15:13 000b Reserved 1813 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 1814 ** that a secondary bus master has its grant maintained in order to enable 1815 ** multiple transactions to execute within the same arbitration cycle. 1816 ** Bit[02:00] GNT# Extended Duration 1817 ** 000 MTT Disabled (Default=no GNT# extension) 1818 ** 001 16 clocks 1819 ** 010 32 clocks 1820 ** 011 64 clocks 1821 ** 100 128 clocks 1822 ** 101 256 clocks 1823 ** 110 Invalid (treated as 000) 1824 ** 111 Invalid (treated as 000) 1825 ** 09:08 00b Reserved 1826 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 1827 ** pair supported by bridge secondary arbiter. 1828 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 1829 ** bit(6) corresponds to bridge internal REQ#/GNT# pair, 1830 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 1831 ** When a given bit is set to 1b, its corresponding REQ#/GNT# 1832 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 1833 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 1834 **================================================================================== 1835 ** 0x53-0x52: Read Prefetch Policy Register - RPPR 1836 ** Bit Default Description 1837 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 1838 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 1839 ** using the FirstRead parameter. 1840 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 1841 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 1842 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 1843 ** the number of bytes to prefetch from the secondary bus interface 1844 ** on the initial PreFetch operation. 1845 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 1846 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 1847 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 1848 ** in calculating the number of bytes to prefetch from the primary 1849 ** bus interface on subsequent PreFetch operations given 1850 ** that the read demands were not satisfied using 1851 ** the FirstRead parameter. 1852 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 1853 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 1854 ** Memory Read Multiple 6 cache lines 1855 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 1856 ** in calculating the number of bytes to prefetch from 1857 ** the primary bus interface on the initial PreFetch operation. 1858 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 1859 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 1860 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 1861 ** algorithm for the secondary and the primary bus interfaces. 1862 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 1863 ** enable bits for REQ#/GNT#[2:0]. 1864 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 1865 ** 1b: enables the staged pre-fetch feature 1866 ** 0b: disables staged pre-fetch, 1867 ** and hardwires read pre-fetch policy to the following for 1868 ** Memory Read, 1869 ** Memory Read Line, 1870 ** and Memory Read Multiple commands: 1871 ** Command Type Hardwired Pre-Fetch Amount... 1872 ** Memory Read 4 DWORDs 1873 ** Memory Read Line 1 cache line 1874 ** Memory Read Multiple 2 cache lines 1875 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 1876 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read 1877 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 1878 **================================================================================== 1879 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 1880 ** Bit Default Description 1881 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 1882 ** in response to its discarding of a delayed transaction that was initiated from the primary bus. 1883 ** 0b=bridge asserts P_SERR#. 1884 ** 1b=bridge does not assert P_SERR# 1885 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1886 ** 0b=bridge asserts P_SERR#. 1887 ** 1b=bridge does not assert P_SERR# 1888 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1889 ** 0b=bridge asserts P_SERR#. 1890 ** 1b=bridge does not assert P_SERR# 1891 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 1892 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 1893 ** 0b=bridge asserts P_SERR#. 1894 ** 1b=bridge does not assert P_SERR# 1895 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 1896 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 1897 ** 0b=bridge asserts P_SERR#. 1898 ** 1b=bridge does not assert P_SERR# 1899 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 1900 ** it discards an upstream posted write transaction. 1901 ** 0b=bridge asserts P_SERR#. 1902 ** 1b=bridge does not assert P_SERR# 1903 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 1904 ** when a data parity error is detected while attempting to retire on of its PMWs upstream. 1905 ** 0b=bridge asserts P_SERR#. 1906 ** 1b=bridge does not assert P_SERR# 1907 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 1908 ** when it detects an address parity error on the secondary bus. 1909 ** 0b=bridge asserts P_SERR#. 1910 ** 1b=bridge does not assert P_SERR# 1911 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 1912 ** its discarding of a delayed transaction that was initiated on the secondary bus. 1913 ** 0b=bridge asserts P_SERR#. 1914 ** 1b=bridge does not assert P_SERR# 1915 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1916 ** 0b=bridge asserts P_SERR#. 1917 ** 1b=bridge does not assert P_SERR# 1918 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1919 ** 0b=bridge asserts P_SERR#. 1920 ** 1b=bridge does not assert P_SERR# 1921 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 1922 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 1923 ** 0b=bridge asserts P_SERR#. 1924 ** 1b=bridge does not assert P_SERR# 1925 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 1926 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 1927 ** 0b=bridge asserts P_SERR#. 1928 ** 1b=bridge does not assert P_SERR# 1929 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 1930 ** that it discards a downstream posted write transaction. 1931 ** 0b=bridge asserts P_SERR#. 1932 ** 1b=bridge does not assert P_SERR# 1933 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 1934 ** when a data parity error is detected while attempting to retire on of its PMWs downstream. 1935 ** 0b=bridge asserts P_SERR#. 1936 ** 1b=bridge does not assert P_SERR# 1937 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 1938 ** when it detects an address parity error on the primary bus. 1939 ** 0b=bridge asserts P_SERR#. 1940 ** 1b=bridge does not assert P_SERR# 1941 **=============================================================================== 1942 ** 0x56: Pre-Boot Status Register - PBSR 1943 ** Bit Default Description 1944 ** 07 1 Reserved 1945 ** 06 - Reserved - value indeterminate 1946 ** 05:02 0 Reserved 1947 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 1948 ** This bit reflect captured S_133EN strap, 1949 ** indicating the maximum secondary bus clock frequency when in PCI-X mode. 1950 ** Max Allowable Secondary Bus Frequency 1951 ** ** S_133EN PCI-X Mode 1952 ** ** 0 100 MHz 1953 ** ** 1 133 MH 1954 ** 00 0b Reserved 1955 **=============================================================================== 1956 ** 0x59-0x58: Secondary Decode Enable Register - SDER 1957 ** Bit Default Description 1958 ** 15:03 FFF1h Preserved. 1959 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 1960 ** bridge overrides its secondary inverse decode logic and not 1961 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 1962 ** This creates a private memory space on the Secondary PCI bus 1963 ** that allows peer-to-peer transactions. 1964 ** 01:00 10 2 Preserved. 1965 **=============================================================================== 1966 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 1967 ** Bit Default Description 1968 ** 15:10 000000 2 Reserved. 1969 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 1970 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 1971 ** When this bit is clear, 1972 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 1973 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 1974 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 1975 ** When this bit is clear, 1976 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 1977 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 1978 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 1979 ** When this bit is clear, 1980 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 1981 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 1982 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 1983 ** When this bit is clear, 1984 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 1985 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 1986 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 1987 ** When this bit is clear, 1988 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 1989 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 1990 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 1991 ** When this bit is clear, 1992 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 1993 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 1994 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 1995 ** When this bit is clear, 1996 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 1997 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 1998 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 1999 ** When this bit is clear, 2000 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 2001 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 2002 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 2003 ** When this bit is clear, 2004 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 2005 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 2006 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 2007 ** When this bit is clear, 2008 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 2009 ************************************************************************** 2010 */ 2011 /* 2012 ************************************************************************** 2013 ** Reserved A8-CBh 2014 ************************************************************************** 2015 */ 2016 /* 2017 ************************************************************************** 2018 ** PCI Extended Enhanced Capabilities List CC-FFh 2019 ************************************************************************** 2020 ** ---------------------------------------------------------------------------------------------------------- 2021 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2022 ** ---------------------------------------------------------------------------------------------------------- 2023 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 2024 ** ---------------------------------------------------------------------------------------------------------- 2025 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h 2026 ** ---------------------------------------------------------------------------------------------------------- 2027 ** | Reserved | Reserved | Reserved | E4h 2028 ** ---------------------------------------------------------------------------------------------------------- 2029 ** | Reserved | E8h 2030 ** ---------------------------------------------------------------------------------------------------------- 2031 ** | Reserved | Reserved | Reserved | Reserved | ECh 2032 ** ---------------------------------------------------------------------------------------------------------- 2033 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 2034 ** ---------------------------------------------------------------------------------------------------------- 2035 ** | PCI-X Bridge Status | F4h 2036 ** ---------------------------------------------------------------------------------------------------------- 2037 ** | PCI-X Upstream Split Transaction Control | F8h 2038 ** ---------------------------------------------------------------------------------------------------------- 2039 ** | PCI-X Downstream Split Transaction Control | FCh 2040 ** ---------------------------------------------------------------------------------------------------------- 2041 **=============================================================================== 2042 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID 2043 ** Bit Default Description 2044 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 2045 **=============================================================================== 2046 ** 0xDD: Next Item Pointer - PM_NXTP 2047 ** Bit Default Description 2048 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 2049 **=============================================================================== 2050 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR 2051 ** Bit Default Description 2052 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 2053 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 2054 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 2055 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 2056 ** This returns 000b as PME# wake-up for bridge is not implemented. 2057 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 2058 ** 04:03 00 Reserved 2059 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 2060 **=============================================================================== 2061 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 2062 ** Bit Default Description 2063 ** 15:09 00h Reserved 2064 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 2065 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 2066 ** 07:02 00h Reserved 2067 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 2068 ** a function and to set the Function into a new power state. 2069 ** 00 - D0 state 2070 ** 01 - D1 state 2071 ** 10 - D2 state 2072 ** 11 - D3 hot state 2073 **=============================================================================== 2074 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 2075 ** Bit Default Description 2076 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 2077 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 2078 ** is to occur as a direct result of programming the function to D3 hot. 2079 ** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 2080 ** 05:00 00h Reserved 2081 **=============================================================================== 2082 ** 0xE3: Power Management Data Register - PMDR 2083 ** Bit Default Description 2084 ** 07:00 00h Reserved 2085 **=============================================================================== 2086 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 2087 ** Bit Default Description 2088 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 2089 **=============================================================================== 2090 ** 0xF1: Next Item Pointer - PX_NXTP 2091 ** Bit Default Description 2092 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 2093 ** register is 00h indicating that this is the last entry in the linked list of capabilities. 2094 **=============================================================================== 2095 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 2096 ** Bit Default Description 2097 ** 15:09 00h Reserved 2098 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 2099 ** The values are: 2100 ** ** BitsMax FrequencyClock Period 2101 ** ** 000PCI ModeN/A 2102 ** ** 00166 15 2103 ** ** 01010010 2104 ** ** 0111337.5 2105 ** ** 1xxreservedreserved 2106 ** ** The default value for this register is the operating frequency of the secondary bus 2107 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 2108 ** secondary bus to the primary bus because there is not enough room within the limit 2109 ** specified in the Split Transaction Commitment Limit field in the Downstream Split 2110 ** Transaction Control register. The bridge does not set this bit. 2111 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 2112 ** The bridge does not set this bit. 2113 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 2114 ** equal to bridge secondary bus number, device number 00h, 2115 ** and function number 0 is received on the secondary interface. 2116 ** This bit is cleared by software writing a '1'. 2117 ** 02 0b Split Completion Discarded (SCD): This bit is set 2118 ** when bridge discards a split completion moving toward the secondary bus 2119 ** because the requester would not accept it. This bit cleared by software writing a '1'. 2120 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 2121 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 2122 **=============================================================================== 2123 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 2124 ** Bit Default Description 2125 ** 31:22 0 Reserved 2126 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 2127 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 2128 ** because bridge throttles traffic on the completion side. 2129 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 2130 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 2131 ** this bit by writing a 1b to it. 2132 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 2133 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 2134 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 2135 ** 0=The maximum operating frequency is 66 MHz. 2136 ** 1=The maximum operating frequency is 133 MHz. 2137 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 2138 ** 0=Primary Interface is connected as a 32-bit PCI bus. 2139 ** 1=Primary Interface is connected as a 64-bit PCI bus. 2140 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 2141 ** of the BNUM register at offset 18h. 2142 ** Apparently it was deemed necessary reflect it here for diagnostic purposes. 2143 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 2144 ** May be updated whenever a PCI-X 2145 ** configuration write cycle that targets bridge scores a hit. 2146 ** 02:00 0h Function Number (FNUM): The bridge Function # 2147 **=============================================================================== 2148 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 2149 ** Bit Default Description 2150 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2151 ** Software is permitted to program this register to any value greater than or equal to 2152 ** the contents of the Split Transaction Capacity register. A value less than the contents 2153 ** of the Split Transaction Capacity register causes unspecified results. 2154 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2155 ** size regardless of the amount of buffer space available. 2156 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2157 ** split completions. This register controls behavior of the bridge buffers for forwarding 2158 ** Split Transactions from a primary bus requester to a secondary bus completer. 2159 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 2160 **=============================================================================== 2161 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 2162 ** Bit Default Description 2163 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2164 ** Software is permitted to program this register to any value greater than or equal to 2165 ** the contents of the Split Transaction Capacity register. A value less than the contents 2166 ** of the Split Transaction Capacity register causes unspecified results. 2167 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2168 ** size regardless of the amount of buffer space available. 2169 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2170 ** split completions. This register controls behavior of the bridge buffers for forwarding 2171 ** Split Transactions from a primary bus requester to a secondary bus completer. 2172 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs 2173 ** (7936 bytes). 2174 ************************************************************************** 2175 */ 2176 2177 2178 2179 2180 /* 2181 ************************************************************************************************************************************* 2182 ** 80331 Address Translation Unit Register Definitions 2183 ** ATU Interface Configuration Header Format 2184 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 2185 ************************************************************************************************************************************* 2186 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 2187 **=================================================================================================================================== 2188 ** | ATU Device ID | Vendor ID | 00h 2189 ** ---------------------------------------------------------------------------------------------------------- 2190 ** | Status | Command | 04H 2191 ** ---------------------------------------------------------------------------------------------------------- 2192 ** | ATU Class Code | Revision ID | 08H 2193 ** ---------------------------------------------------------------------------------------------------------- 2194 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 2195 ** ---------------------------------------------------------------------------------------------------------- 2196 ** | Inbound ATU Base Address 0 | 10H 2197 ** ---------------------------------------------------------------------------------------------------------- 2198 ** | Inbound ATU Upper Base Address 0 | 14H 2199 ** ---------------------------------------------------------------------------------------------------------- 2200 ** | Inbound ATU Base Address 1 | 18H 2201 ** ---------------------------------------------------------------------------------------------------------- 2202 ** | Inbound ATU Upper Base Address 1 | 1CH 2203 ** ---------------------------------------------------------------------------------------------------------- 2204 ** | Inbound ATU Base Address 2 | 20H 2205 ** ---------------------------------------------------------------------------------------------------------- 2206 ** | Inbound ATU Upper Base Address 2 | 24H 2207 ** ---------------------------------------------------------------------------------------------------------- 2208 ** | Reserved | 28H 2209 ** ---------------------------------------------------------------------------------------------------------- 2210 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 2211 ** ---------------------------------------------------------------------------------------------------------- 2212 ** | Expansion ROM Base Address | 30H 2213 ** ---------------------------------------------------------------------------------------------------------- 2214 ** | Reserved Capabilities Pointer | 34H 2215 ** ---------------------------------------------------------------------------------------------------------- 2216 ** | Reserved | 38H 2217 ** ---------------------------------------------------------------------------------------------------------- 2218 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 2219 ** ---------------------------------------------------------------------------------------------------------- 2220 ********************************************************************************************************************* 2221 */ 2222 /* 2223 *********************************************************************************** 2224 ** ATU Vendor ID Register - ATUVID 2225 ** ----------------------------------------------------------------- 2226 ** Bit Default Description 2227 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 2228 ** This register, combined with the DID, uniquely identify the PCI device. 2229 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 2230 ** to simulate the interface of a standard mechanism currently used by existing application software. 2231 *********************************************************************************** 2232 */ 2233 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 2234 /* 2235 *********************************************************************************** 2236 ** ATU Device ID Register - ATUDID 2237 ** ----------------------------------------------------------------- 2238 ** Bit Default Description 2239 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 2240 ** This ID, combined with the VID, uniquely identify any PCI device. 2241 *********************************************************************************** 2242 */ 2243 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 2244 /* 2245 *********************************************************************************** 2246 ** ATU Command Register - ATUCMD 2247 ** ----------------------------------------------------------------- 2248 ** Bit Default Description 2249 ** 15:11 000000 2 Reserved 2250 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 2251 ** 0=enables the assertion of interrupt signal. 2252 ** 1=disables the assertion of its interrupt signal. 2253 ** 09 0 2 Fast Back to Back Enable - When cleared, 2254 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 2255 ** Ignored when operating in the PCI-X mode. 2256 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 2257 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 2258 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 2259 ** of address stepping for PCI-X mode. 2260 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 2261 ** is detected. When cleared, parity checking is disabled. 2262 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 2263 ** does not perform VGA palette snooping. 2264 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 2265 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 2266 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 2267 ** Not implemented and a reserved bit field. 2268 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 2269 ** When cleared, disables the device from generating PCI accesses. 2270 ** When set, allows the device to behave as a PCI bus master. 2271 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 2272 ** of the state of this bit. 2273 ** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. 2274 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 2275 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 2276 ** Not implemented and a reserved bit field. 2277 *********************************************************************************** 2278 */ 2279 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 2280 /* 2281 *********************************************************************************** 2282 ** ATU Status Register - ATUSR (Sheet 1 of 2) 2283 ** ----------------------------------------------------------------- 2284 ** Bit Default Description 2285 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 2286 ** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 2287 ** �E Write Data Parity Error when the ATU is a target (inbound write). 2288 ** �E Read Data Parity Error when the ATU is a requester (outbound read). 2289 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 2290 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 2291 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 2292 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 2293 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 2294 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 2295 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 2296 ** terminates the transaction on the PCI bus with a target abort. 2297 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 2298 ** timing for a target device in Conventional PCI Mode regardless of the operating mode 2299 ** (except configuration accesses). 2300 ** 00 2=Fast 2301 ** 01 2=Medium 2302 ** 10 2=Slow 2303 ** 11 2=Reserved 2304 ** The ATU interface uses Medium timing. 2305 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 2306 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2307 ** �E And the ATU acted as the requester 2308 ** for the operation in which the error occurred. 2309 ** �E And the ATUCMD register��s Parity Error Response bit is set 2310 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2311 ** �E And the ATUCMD register��s Parity Error Response bit is set 2312 ** 07 1 2 (Conventional mode) 2313 ** 0 2 (PCI-X mode) 2314 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 2315 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 2316 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 2317 ** 06 0 2 UDF Supported - User Definable Features are not supported 2318 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 2319 ** 04 1 2 Capabilities - When set, this function implements extended capabilities. 2320 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt 2321 ** when the Interrupt Disable bit in the command register is a 0. 2322 ** 0=ATU interrupt signal deasserted. 2323 ** 1=ATU interrupt signal asserted. 2324 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 2325 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 2326 ** interrupt signal. 2327 ** 02:00 00000 2 Reserved. 2328 *********************************************************************************** 2329 */ 2330 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 2331 /* 2332 *********************************************************************************** 2333 ** ATU Revision ID Register - ATURID 2334 ** ----------------------------------------------------------------- 2335 ** Bit Default Description 2336 ** 07:00 00H ATU Revision - identifies the 80331 revision number. 2337 *********************************************************************************** 2338 */ 2339 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 2340 /* 2341 *********************************************************************************** 2342 ** ATU Class Code Register - ATUCCR 2343 ** ----------------------------------------------------------------- 2344 ** Bit Default Description 2345 ** 23:16 05H Base Class - Memory Controller 2346 ** 15:08 80H Sub Class - Other Memory Controller 2347 ** 07:00 00H Programming Interface - None defined 2348 *********************************************************************************** 2349 */ 2350 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 2351 /* 2352 *********************************************************************************** 2353 ** ATU Cacheline Size Register - ATUCLSR 2354 ** ----------------------------------------------------------------- 2355 ** Bit Default Description 2356 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 2357 *********************************************************************************** 2358 */ 2359 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 2360 /* 2361 *********************************************************************************** 2362 ** ATU Latency Timer Register - ATULT 2363 ** ----------------------------------------------------------------- 2364 ** Bit Default Description 2365 ** 07:03 00000 2 (for Conventional mode) 2366 ** 01000 2 (for PCI-X mode) 2367 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 2368 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 2369 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 2370 *********************************************************************************** 2371 */ 2372 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 2373 /* 2374 *********************************************************************************** 2375 ** ATU Header Type Register - ATUHTR 2376 ** ----------------------------------------------------------------- 2377 ** Bit Default Description 2378 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 2379 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 2380 ** header conforms to PCI Local Bus Specification, Revision 2.3. 2381 *********************************************************************************** 2382 */ 2383 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 2384 /* 2385 *********************************************************************************** 2386 ** ATU BIST Register - ATUBISTR 2387 ** 2388 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 2389 ** initiated. This register is the interface between the host processor requesting BIST functions and 2390 ** the 80331 replying with the results from the software implementation of the BIST functionality. 2391 ** ----------------------------------------------------------------- 2392 ** Bit Default Description 2393 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 2394 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 2395 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 2396 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 2397 ** found in ATUBISTR register bits [3:0]. 2398 ** When the ATUCR BIST Interrupt Enable bit is clear: 2399 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 2400 ** The Intel XScale core does not clear this bit. 2401 ** 05:04 00 2 Reserved 2402 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 2403 ** The Intel XScale core places the results of the software BIST in these bits. 2404 ** A nonzero value indicates a device-specific error. 2405 *********************************************************************************** 2406 */ 2407 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 2408 2409 /* 2410 *************************************************************************************** 2411 ** ATU Base Registers and Associated Limit Registers 2412 *************************************************************************************** 2413 ** Base Address Register Limit Register Description 2414 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 2415 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 2416 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 2417 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 2418 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 2419 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 2420 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 2421 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 2422 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 2423 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 2424 **-------------------------------------------------------------------------------------- 2425 ** ATU Inbound Window 1 is not a translate window. 2426 ** The ATU does not claim any PCI accesses that fall within this range. 2427 ** This window is used to allocate host memory for use by Private Devices. 2428 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 2429 *********************************************************************************** 2430 */ 2431 2432 /* 2433 *********************************************************************************** 2434 ** Inbound ATU Base Address Register 0 - IABAR0 2435 ** 2436 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 2437 ** defines the block of memory addresses where the inbound translation window 0 begins. 2438 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2439 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 2440 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 2441 ** depending on the value located within the IALR0. 2442 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 2443 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 2444 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2445 ** Warning: 2446 ** When IALR0 is cleared prior to host configuration: 2447 ** the user should also clear the Prefetchable Indicator and the Type Indicator. 2448 ** Assuming IALR0 is not cleared: 2449 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2450 ** when the Prefetchable Indicator is cleared prior to host configuration, 2451 ** the user should also set the Type Indicator for 32 bit addressability. 2452 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 2453 ** when the Prefetchable Indicator is set prior to host configuration, the user 2454 ** should also set the Type Indicator for 64 bit addressability. 2455 ** This is the default for IABAR0. 2456 ** ----------------------------------------------------------------- 2457 ** Bit Default Description 2458 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location 2459 ** the translation function is to respond to when addressed from the PCI bus. 2460 ** 11:04 00H Reserved. 2461 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2462 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 2463 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2464 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2465 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2466 ** The ATU does not occupy I/O space, 2467 ** thus this bit must be zero. 2468 *********************************************************************************** 2469 */ 2470 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 2471 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 2472 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2473 /* 2474 *********************************************************************************** 2475 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2476 ** 2477 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2478 ** Together with the Translation Base Address this register defines the actual location the translation 2479 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2480 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2481 ** Note: 2482 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2483 ** the IAUBAR0 register attributes are read-only. 2484 ** ----------------------------------------------------------------- 2485 ** Bit Default Description 2486 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2487 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2488 *********************************************************************************** 2489 */ 2490 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2491 /* 2492 *********************************************************************************** 2493 ** Inbound ATU Base Address Register 1 - IABAR1 2494 ** 2495 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2496 ** defines the block of memory addresses where the inbound translation window 1 begins. 2497 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2498 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2499 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2500 ** Warning: 2501 ** When a non-zero value is not written to IALR1 prior to host configuration, 2502 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2503 ** This is the default for IABAR1. 2504 ** Assuming a non-zero value is written to IALR1, 2505 ** the user may set the Prefetchable Indicator 2506 ** or the Type Indicator: 2507 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2508 ** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2509 ** the user should also leave the Type Indicator set for 32 bit addressability. 2510 ** This is the default for IABAR1. 2511 ** b. when the Prefetchable Indicator is set prior to host configuration, 2512 ** the user should also set the Type Indicator for 64 bit addressability. 2513 ** ----------------------------------------------------------------- 2514 ** Bit Default Description 2515 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2516 ** 11:04 00H Reserved. 2517 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2518 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2519 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2520 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2521 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2522 ** The ATU does not occupy I/O space, 2523 ** thus this bit must be zero. 2524 *********************************************************************************** 2525 */ 2526 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2527 /* 2528 *********************************************************************************** 2529 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2530 ** 2531 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2532 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2533 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2534 ** The programmed value within the base address register must comply with the PCI programming 2535 ** requirements for address alignment. 2536 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2537 ** from the PCI bus. 2538 ** Note: 2539 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 2540 ** the IAUBAR1 register attributes are read-only. 2541 ** This is the default for IABAR1. 2542 ** ----------------------------------------------------------------- 2543 ** Bit Default Description 2544 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 2545 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 2546 *********************************************************************************** 2547 */ 2548 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 2549 /* 2550 *********************************************************************************** 2551 ** Inbound ATU Base Address Register 2 - IABAR2 2552 ** 2553 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 2554 ** defines the block of memory addresses where the inbound translation window 2 begins. 2555 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2556 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 2557 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 2558 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2559 ** Warning: 2560 ** When a non-zero value is not written to IALR2 prior to host configuration, 2561 ** the user should not set either the Prefetchable Indicator 2562 ** or the Type Indicator for 64 bit addressability. 2563 ** This is the default for IABAR2. 2564 ** Assuming a non-zero value is written to IALR2, 2565 ** the user may set the Prefetchable Indicator 2566 ** or the Type Indicator: 2567 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2568 ** when the Prefetchable Indicator is not set prior to host configuration, 2569 ** the user should also leave the Type Indicator set for 32 bit addressability. 2570 ** This is the default for IABAR2. 2571 ** b. when the Prefetchable Indicator is set prior to host configuration, 2572 ** the user should also set the Type Indicator for 64 bit addressability. 2573 ** ----------------------------------------------------------------- 2574 ** Bit Default Description 2575 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location 2576 ** the translation function is to respond to when addressed from the PCI bus. 2577 ** 11:04 00H Reserved. 2578 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2579 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2580 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2581 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2582 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2583 ** The ATU does not occupy I/O space, 2584 ** thus this bit must be zero. 2585 *********************************************************************************** 2586 */ 2587 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 2588 /* 2589 *********************************************************************************** 2590 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2 2591 ** 2592 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2593 ** Together with the Translation Base Address this register defines the actual location 2594 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2595 ** The programmed value within the base address register must comply with the PCI programming 2596 ** requirements for address alignment. 2597 ** Note: 2598 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 2599 ** the IAUBAR2 register attributes are read-only. 2600 ** This is the default for IABAR2. 2601 ** ----------------------------------------------------------------- 2602 ** Bit Default Description 2603 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 2604 ** these bits define the actual location the translation function is to respond to 2605 ** when addressed from the PCI bus for addresses > 4GBytes. 2606 *********************************************************************************** 2607 */ 2608 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 2609 /* 2610 *********************************************************************************** 2611 ** ATU Subsystem Vendor ID Register - ASVIR 2612 ** ----------------------------------------------------------------- 2613 ** Bit Default Description 2614 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 2615 *********************************************************************************** 2616 */ 2617 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 2618 /* 2619 *********************************************************************************** 2620 ** ATU Subsystem ID Register - ASIR 2621 ** ----------------------------------------------------------------- 2622 ** Bit Default Description 2623 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 2624 *********************************************************************************** 2625 */ 2626 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 2627 /* 2628 *********************************************************************************** 2629 ** Expansion ROM Base Address Register -ERBAR 2630 ** ----------------------------------------------------------------- 2631 ** Bit Default Description 2632 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 2633 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 2634 ** 11:01 000H Reserved 2635 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address 2636 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 2637 *********************************************************************************** 2638 */ 2639 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 2640 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 2641 /* 2642 *********************************************************************************** 2643 ** ATU Capabilities Pointer Register - ATU_CAP_PTR 2644 ** ----------------------------------------------------------------- 2645 ** Bit Default Description 2646 ** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space 2647 ** that points to the 80331 PCl Bus Power Management extended capability. 2648 *********************************************************************************** 2649 */ 2650 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 2651 /* 2652 *********************************************************************************** 2653 ** Determining Block Sizes for Base Address Registers 2654 ** The required address size and type can be determined by writing ones to a base address register and 2655 ** reading from the registers. By scanning the returned value from the least-significant bit of the base 2656 ** address registers upwards, the programmer can determine the required address space size. The 2657 ** binary-weighted value of the first non-zero bit found indicates the required amount of space. 2658 ** Table 105 describes the relationship between the values read back and the byte sizes the base 2659 ** address register requires. 2660 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 2661 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 2662 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 2663 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 2664 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 2665 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 2666 ** associated limit registers to enable which bits within the base address register are read/write and 2667 ** which bits are read only (0). This allows the programming of these registers in a manner similar to 2668 ** other PCI devices even though the limit is variable. 2669 ** Table 105. Memory Block Size Read Response 2670 ** Response After Writing all 1s 2671 ** to the Base Address Register 2672 ** Size 2673 ** (Bytes) 2674 ** Response After Writing all 1s 2675 ** to the Base Address Register 2676 ** Size 2677 ** (Bytes) 2678 ** FFFFFFF0H 16 FFF00000H 1 M 2679 ** FFFFFFE0H 32 FFE00000H 2 M 2680 ** FFFFFFC0H 64 FFC00000H 4 M 2681 ** FFFFFF80H 128 FF800000H 8 M 2682 ** FFFFFF00H 256 FF000000H 16 M 2683 ** FFFFFE00H 512 FE000000H 32 M 2684 ** FFFFFC00H 1K FC000000H 64 M 2685 ** FFFFF800H 2K F8000000H 128 M 2686 ** FFFFF000H 4K F0000000H 256 M 2687 ** FFFFE000H 8K E0000000H 512 M 2688 ** FFFFC000H 16K C0000000H 1 G 2689 ** FFFF8000H 32K 80000000H 2 G 2690 ** FFFF0000H 64K 2691 ** 00000000H 2692 ** Register not 2693 ** imple-mented, 2694 ** no 2695 ** address 2696 ** space 2697 ** required. 2698 ** FFFE0000H 128K 2699 ** FFFC0000H 256K 2700 ** FFF80000H 512K 2701 ** 2702 *************************************************************************************** 2703 */ 2704 2705 2706 2707 /* 2708 *********************************************************************************** 2709 ** ATU Interrupt Line Register - ATUILR 2710 ** ----------------------------------------------------------------- 2711 ** Bit Default Description 2712 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 2713 ** request line connects to the device's PCI interrupt request lines 2714 ** (as specified in the interrupt pin register). 2715 ** A value of FFH signifies ��no connection�� or ��unknown��. 2716 *********************************************************************************** 2717 */ 2718 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 2719 /* 2720 *********************************************************************************** 2721 ** ATU Interrupt Pin Register - ATUIPR 2722 ** ----------------------------------------------------------------- 2723 ** Bit Default Description 2724 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 2725 *********************************************************************************** 2726 */ 2727 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 2728 /* 2729 *********************************************************************************** 2730 ** ATU Minimum Grant Register - ATUMGNT 2731 ** ----------------------------------------------------------------- 2732 ** Bit Default Description 2733 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 2734 *********************************************************************************** 2735 */ 2736 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 2737 /* 2738 *********************************************************************************** 2739 ** ATU Maximum Latency Register - ATUMLAT 2740 ** ----------------------------------------------------------------- 2741 ** Bit Default Description 2742 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 2743 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 2744 *********************************************************************************** 2745 */ 2746 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 2747 /* 2748 *********************************************************************************** 2749 ** Inbound Address Translation 2750 ** 2751 ** The ATU allows external PCI bus initiators to directly access the internal bus. 2752 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 2753 ** The process of inbound address translation involves two steps: 2754 ** 1. Address Detection. 2755 ** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 2756 ** within the address windows defined for the inbound ATU. 2757 ** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 2758 ** mode and with Decode A DEVSEL# timing in the PCI-X mode. 2759 ** 2. Address Translation. 2760 ** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 2761 ** The ATU uses the following registers in inbound address window 0 translation: 2762 ** �E Inbound ATU Base Address Register 0 2763 ** �E Inbound ATU Limit Register 0 2764 ** �E Inbound ATU Translate Value Register 0 2765 ** The ATU uses the following registers in inbound address window 2 translation: 2766 ** �E Inbound ATU Base Address Register 2 2767 ** �E Inbound ATU Limit Register 2 2768 ** �E Inbound ATU Translate Value Register 2 2769 ** The ATU uses the following registers in inbound address window 3 translation: 2770 ** �E Inbound ATU Base Address Register 3 2771 ** �E Inbound ATU Limit Register 3 2772 ** �E Inbound ATU Translate Value Register 3 2773 ** Note: Inbound Address window 1 is not a translate window. 2774 ** Instead, window 1 may be used to allocate host memory for Private Devices. 2775 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 2776 ** thus the host BIOS does not configure window 3. 2777 ** Window 3 is intended to be used as a special window into local memory for private PCI 2778 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 2779 ** PCI-to-PCI Bridge in 80331 or 2780 ** Inbound address detection is determined from the 32-bit PCI address, 2781 ** (64-bit PCI address during DACs) the base address register and the limit register. 2782 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 2783 ** 2784 ** The algorithm for detection is: 2785 ** 2786 ** Equation 1. Inbound Address Detection 2787 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 2788 ** the PCI Address is claimed by the Inbound ATU. 2789 ** 2790 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 2791 ** with the associated inbound limit register. 2792 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 2793 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 2794 ** 2795 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 2796 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 2797 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 2798 ** lower 32-bits are used during address translation. 2799 ** The algorithm is: 2800 ** 2801 ** 2802 ** Equation 2. Inbound Translation 2803 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 2804 ** 2805 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 2806 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 2807 ** the result is the internal bus address. This translation mechanism is used for all inbound memory 2808 ** read and write commands excluding inbound configuration read and writes. 2809 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 2810 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 2811 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 2812 ** example: 2813 ** Register Values 2814 ** Base_Register=3A00 0000H 2815 ** Limit_Register=FF80 0000H (8 Mbyte limit value) 2816 ** Value_Register=B100 0000H 2817 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 2818 ** 2819 ** Address Detection (32-bit address) 2820 ** 2821 ** PCI_Address & Limit_Register == Base_Register 2822 ** 3A45 012CH & FF80 0000H == 3A00 0000H 2823 ** 2824 ** ANS: PCI_Address is in the Inbound Translation Window 2825 ** Address Translation (to get internal bus address) 2826 ** 2827 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 2828 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 2829 ** 2830 ** ANS:IB_Address=B145 012CH 2831 *********************************************************************************** 2832 */ 2833 2834 2835 2836 /* 2837 *********************************************************************************** 2838 ** Inbound ATU Limit Register 0 - IALR0 2839 ** 2840 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 2841 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2842 ** PCI addresses to internal bus addresses. 2843 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 2844 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 2845 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2846 ** Specification, Revision 2.3 for additional information on programming base address registers. 2847 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 2848 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 2849 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 2850 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 2851 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 2852 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 2853 ** ----------------------------------------------------------------- 2854 ** Bit Default Description 2855 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 2856 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 2857 ** 11:00 000H Reserved 2858 *********************************************************************************** 2859 */ 2860 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 2861 /* 2862 *********************************************************************************** 2863 ** Inbound ATU Translate Value Register 0 - IATVR0 2864 ** 2865 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 2866 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2867 ** inbound ATU address translation. 2868 ** ----------------------------------------------------------------- 2869 ** Bit Default Description 2870 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 2871 ** This value must be 64-bit aligned on the internal bus. 2872 ** The default address allows the ATU to access the internal 80331 memory-mapped registers. 2873 ** 11:00 000H Reserved 2874 *********************************************************************************** 2875 */ 2876 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 2877 /* 2878 *********************************************************************************** 2879 ** Expansion ROM Limit Register - ERLR 2880 ** 2881 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 2882 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 2883 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 2884 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 2885 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 2886 ** the corresponding bit within the ERBAR read/write from PCI. 2887 ** ----------------------------------------------------------------- 2888 ** Bit Default Description 2889 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 2890 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 2891 ** 11:00 000H Reserved. 2892 *********************************************************************************** 2893 */ 2894 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 2895 /* 2896 *********************************************************************************** 2897 ** Expansion ROM Translate Value Register - ERTVR 2898 ** 2899 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 2900 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 2901 ** Expansion ROM address translation. 2902 ** ----------------------------------------------------------------- 2903 ** Bit Default Description 2904 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 2905 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 2906 ** 11:00 000H Reserved 2907 *********************************************************************************** 2908 */ 2909 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 2910 /* 2911 *********************************************************************************** 2912 ** Inbound ATU Limit Register 1 - IALR1 2913 ** 2914 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 2915 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 2916 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 2917 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 2918 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 2919 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 2920 ** register. 2921 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 2922 ** not process any PCI bus transactions to this memory range. 2923 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 2924 ** IAUBAR1, and IALR1. 2925 ** ----------------------------------------------------------------- 2926 ** Bit Default Description 2927 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 2928 ** required for the ATUs memory window 1. 2929 ** 11:00 000H Reserved 2930 *********************************************************************************** 2931 */ 2932 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 2933 /* 2934 *********************************************************************************** 2935 ** Inbound ATU Limit Register 2 - IALR2 2936 ** 2937 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 2938 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2939 ** PCI addresses to internal bus addresses. 2940 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 2941 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 2942 ** register provides the block size requirements for the base address register. The remaining registers 2943 ** used for performing address translation are discussed in Section 3.2.1.1. 2944 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 2945 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 2946 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2947 ** Specification, Revision 2.3 for additional information on programming base address registers. 2948 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 2949 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 2950 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 2951 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 2952 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 2953 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 2954 ** register. 2955 ** ----------------------------------------------------------------- 2956 ** Bit Default Description 2957 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 2958 ** required for the ATUs memory window 2. 2959 ** 11:00 000H Reserved 2960 *********************************************************************************** 2961 */ 2962 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 2963 /* 2964 *********************************************************************************** 2965 ** Inbound ATU Translate Value Register 2 - IATVR2 2966 ** 2967 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 2968 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2969 ** inbound ATU address translation. 2970 ** ----------------------------------------------------------------- 2971 ** Bit Default Description 2972 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 2973 ** This value must be 64-bit aligned on the internal bus. 2974 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 2975 ** 11:00 000H Reserved 2976 *********************************************************************************** 2977 */ 2978 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 2979 /* 2980 *********************************************************************************** 2981 ** Outbound I/O Window Translate Value Register - OIOWTVR 2982 ** 2983 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 2984 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 2985 ** result of the outbound ATU address translation. 2986 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 2987 ** length of 64 Kbytes. 2988 ** ----------------------------------------------------------------- 2989 ** Bit Default Description 2990 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 2991 ** 15:00 0000H Reserved 2992 *********************************************************************************** 2993 */ 2994 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 2995 /* 2996 *********************************************************************************** 2997 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0 2998 ** 2999 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 3000 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3001 ** driven on the PCI bus as a result of the outbound ATU address translation. 3002 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 3003 ** of 64 Mbytes. 3004 ** ----------------------------------------------------------------- 3005 ** Bit Default Description 3006 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3007 ** 25:02 00 0000H Reserved 3008 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3009 ** Only linear incrementing mode is supported. 3010 *********************************************************************************** 3011 */ 3012 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 3013 /* 3014 *********************************************************************************** 3015 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 3016 ** 3017 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 3018 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3019 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3020 ** a SAC is generated on the PCI bus. 3021 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 3022 ** length of 64 Mbytes. 3023 ** ----------------------------------------------------------------- 3024 ** Bit Default Description 3025 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3026 *********************************************************************************** 3027 */ 3028 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 3029 /* 3030 *********************************************************************************** 3031 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1 3032 ** 3033 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 3034 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3035 ** driven on the PCI bus as a result of the outbound ATU address translation. 3036 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3037 ** of 64 Mbytes. 3038 ** ----------------------------------------------------------------- 3039 ** Bit Default Description 3040 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3041 ** 25:02 00 0000H Reserved 3042 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3043 ** Only linear incrementing mode is supported. 3044 *********************************************************************************** 3045 */ 3046 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 3047 /* 3048 *********************************************************************************** 3049 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 3050 ** 3051 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 3052 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3053 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3054 ** a SAC is generated on the PCI bus. 3055 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3056 ** of 64 Mbytes. 3057 ** ----------------------------------------------------------------- 3058 ** Bit Default Description 3059 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3060 *********************************************************************************** 3061 */ 3062 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 3063 /* 3064 *********************************************************************************** 3065 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 3066 ** 3067 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 3068 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 3069 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 3070 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 3071 ** ----------------------------------------------------------------- 3072 ** Bit Default Description 3073 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3074 *********************************************************************************** 3075 */ 3076 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 3077 /* 3078 *********************************************************************************** 3079 ** ATU Configuration Register - ATUCR 3080 ** 3081 ** The ATU Configuration Register controls the outbound address translation for address translation 3082 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 3083 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 3084 ** interrupt enabling. 3085 ** ----------------------------------------------------------------- 3086 ** Bit Default Description 3087 ** 31:20 00H Reserved 3088 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 3089 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 3090 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 3091 ** applicable in the PCI-X mode. 3092 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 3093 ** with Direct Addressing enabled (bit 7 of the ATUCR set), 3094 ** the ATU forwards internal bus cycles with an address between 0000.0040H and 3095 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 3096 ** When clear, no translation occurs. 3097 ** 17 0 2 Reserved 3098 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 3099 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 3100 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 3101 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 3102 ** 14:10 00000 2 Reserved 3103 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 3104 ** when the ATU detects that SERR# was asserted. When clear, 3105 ** the Intel XScale core is not interrupted when SERR# is detected. 3106 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 3107 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 3108 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 3109 ** the ATUCR. 3110 ** 07:04 0000 2 Reserved 3111 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 3112 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 3113 ** in the ATUBISTR register. 3114 ** 02 0 2 Reserved 3115 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 3116 ** When cleared, disables the outbound ATU. 3117 ** 00 0 2 Reserved 3118 *********************************************************************************** 3119 */ 3120 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 3121 /* 3122 *********************************************************************************** 3123 ** PCI Configuration and Status Register - PCSR 3124 ** 3125 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring 3126 ** various features of the PCI bus interface. 3127 ** ----------------------------------------------------------------- 3128 ** Bit Default Description 3129 ** 31:19 0000H Reserved 3130 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 3131 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 3132 ** Response bit is cleared. Set under the following conditions: 3133 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 3134 ** 17:16 Varies with 3135 ** external state 3136 ** of DEVSEL#, 3137 ** STOP#, and 3138 ** TRDY#, 3139 ** during 3140 ** P_RST# 3141 ** PCI-X capability - These two bits define the mode of 3142 ** the PCI bus (conventional or PCI-X) as well as the 3143 ** operating frequency in the case of PCI-X mode. 3144 ** 00 - Conventional PCI mode 3145 ** 01 - PCI-X 66 3146 ** 10 - PCI-X 100 3147 ** 11 - PCI-X 133 3148 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 3149 ** Revision 1.0a, the operating 3150 ** mode is determined by an initialization pattern on the PCI bus during 3151 ** P_RST# assertion: 3152 ** DEVSEL# STOP# TRDY# Mode 3153 ** Deasserted Deasserted Deasserted Conventional 3154 ** Deasserted Deasserted Asserted PCI-X 66 3155 ** Deasserted Asserted Deasserted PCI-X 100 3156 ** Deasserted Asserted Asserted PCI-X 133 3157 ** All other patterns are reserved. 3158 ** 15 0 2 3159 ** Outbound Transaction Queue Busy: 3160 ** 0=Outbound Transaction Queue Empty 3161 ** 1=Outbound Transaction Queue Busy 3162 ** 14 0 2 3163 ** Inbound Transaction Queue Busy: 3164 ** 0=Inbound Transaction Queue Empty 3165 ** 1=Inbound Transaction Queue Busy 3166 ** 13 0 2 Reserved. 3167 ** 12 0 2 Discard Timer Value - This bit controls the time-out value 3168 ** for the four discard timers attached to the queues holding read data. 3169 ** A value of 0 indicates the time-out value is 2 15 clocks. 3170 ** A value of 1 indicates the time-out value is 2 10 clocks. 3171 ** 11 0 2 Reserved. 3172 ** 10 Varies with 3173 ** external state 3174 ** of M66EN 3175 ** during 3176 ** P_RST# 3177 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 3178 ** Conventional PCI mode by the assertion of M66EN during bus initialization. 3179 ** When clear, the interface 3180 ** has been initialized as a 33 MHz bus. 3181 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 3182 ** 09 0 2 Reserved 3183 ** 08 Varies with 3184 ** external state 3185 ** of REQ64# 3186 ** during 3187 ** P_RST# 3188 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 3189 ** configured as 64-bit capable by 3190 ** the assertion of REQ64# on the rising edge of P_RST#. When set, 3191 ** the PCI interface is configured as 3192 ** 32-bit only. 3193 ** 07:06 00 2 Reserved. 3194 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 3195 ** and all units on the internal 3196 ** bus. In addition to the internal bus initialization, 3197 ** this bit triggers the assertion of the M_RST# pin for 3198 ** initialization of registered DIMMs. When set: 3199 ** When operating in the conventional PCI mode: 3200 ** �E All current PCI transactions being mastered by the ATU completes, 3201 ** and the ATU master interfaces 3202 ** proceeds to an idle state. No additional transactions is mastered by these units 3203 ** until the internal bus reset is complete. 3204 ** �E All current transactions being slaved by the ATU on either the PCI bus 3205 ** or the internal bus 3206 ** completes, and the ATU target interfaces proceeds to an idle state. 3207 ** All future slave transactions master aborts, 3208 ** with the exception of the completion cycle for the transaction that set the Reset 3209 ** Internal Bus bit in the PCSR. 3210 ** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 3211 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 3212 ** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 3213 ** Internal Bus clocks. 3214 ** �E The 80331 hardware clears this bit after the reset operation completes. 3215 ** When operating in the PCI-X mode: 3216 ** The ATU hardware responds the same as in Conventional PCI-X mode. 3217 ** However, this may create a problem in PCI-X mode for split requests in 3218 ** that there may still be an outstanding split completion that the 3219 ** ATU is either waiting to receive (Outbound Request) or initiate 3220 ** (Inbound Read Request). For a cleaner 3221 ** internal bus reset, host software can take the following steps prior 3222 ** to asserting Reset Internal bus: 3223 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 3224 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 3225 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 3226 ** queue busy bits to be clear. 3227 ** 3. Set the Reset Internal Bus bit 3228 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 3229 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split 3230 ** completion transactions. 3231 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 3232 ** guaranteed that any prior configuration cycles have properly completed since there is only a one 3233 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 3234 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 3235 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the 3236 ** Bus Master Indicator signal P_BMI used 3237 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 3238 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 3239 ** 03 Varies with external state of PRIVDEV during 3240 ** P_RST# 3241 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 3242 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 3243 ** 0=Private Device control Disabled - SISR register bits default to zero 3244 ** 1=Private Device control Enabled - SISR register bits default to one 3245 ** 02 Varies with external state of RETRY during P_RST# 3246 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 3247 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 3248 ** configuration cycles. 3249 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 3250 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 3251 ** low, the bit is cleared. 3252 ** 01 Varies with external state of CORE_RST# during P_RST# 3253 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 3254 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 3255 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 3256 ** XScale core reset. 3257 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 3258 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 3259 ** high, the bit is clear. 3260 ** 00 Varies with external state of PRIVMEM during P_RST# 3261 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 3262 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 3263 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero 3264 ** 1=Private Memory control Enabled - SDER register bits 2 default to one 3265 *********************************************************************************** 3266 */ 3267 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 3268 /* 3269 *********************************************************************************** 3270 ** ATU Interrupt Status Register - ATUISR 3271 ** 3272 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 3273 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 3274 ** of the 80331. All bits in this register are Read/Clear. 3275 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 3276 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 3277 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 3278 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 3279 ** register. 3280 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 3281 ** ----------------------------------------------------------------- 3282 ** Bit Default Description 3283 ** 31:18 0000H Reserved 3284 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 3285 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 3286 ** this bit results in the assertion of the ATU Configure Register Write Interrupt. 3287 ** 16 0 2 Reserved 3288 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 3289 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 3290 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 3291 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 3292 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 3293 ** Configure Register Write Interrupt. 3294 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 3295 ** Message on the PCI Bus with the Split Completion Error attribute bit set. 3296 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3297 ** Message from the PCI Bus with the Split Completion Error attribute bit set. 3298 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 3299 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 3300 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 3301 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 3302 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 3303 ** register��s Parity Error Response bit is cleared. Set under the following conditions: 3304 ** �E Write Data Parity Error when the ATU is a target (inbound write). 3305 ** �E Read Data Parity Error when the ATU is an initiator (outbound read). 3306 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 3307 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 3308 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 3309 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 3310 ** register bits 3:0. 3311 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 3312 ** of the ATU Configure Register Write Interrupt. 3313 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 3314 ** 06:05 00 2 Reserved. 3315 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 3316 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 3317 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 3318 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 3319 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 3320 ** conditions: 3321 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 3322 ** �E And the ATU acted as the requester for the operation in which the error occurred. 3323 ** �E And the ATUCMD register��s Parity Error Response bit is set 3324 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 3325 ** �E And the ATUCMD register��s Parity Error Response bit is set 3326 *********************************************************************************** 3327 */ 3328 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 3329 /* 3330 *********************************************************************************** 3331 ** ATU Interrupt Mask Register - ATUIMR 3332 ** 3333 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 3334 ** generated by the ATU. 3335 ** ----------------------------------------------------------------- 3336 ** Bit Default Description 3337 ** 31:15 0 0000H Reserved 3338 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 3339 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 3340 ** 0=Not Masked 3341 ** 1=Masked 3342 ** 13 0 2 Reserved 3343 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 3344 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 3345 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 3346 ** 0=Not Masked 3347 ** 1=Masked 3348 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 3349 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 3350 ** IABAR1 register or the IAUBAR1 register. 3351 ** 0=Not Masked 3352 ** 1=Masked 3353 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 3354 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 3355 ** 0=Not Masked 3356 ** 1=Masked 3357 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 3358 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 3359 ** PCIXSR being set. 3360 ** 0=Not Masked 3361 ** 1=Masked 3362 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 3363 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 3364 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 3365 ** 0=Not Masked 3366 ** 1=Masked 3367 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 3368 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 3369 ** 0=Not Masked 3370 ** 1=Masked 3371 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 3372 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 3373 ** 0=Not Masked 3374 ** 1=Masked 3375 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 3376 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 3377 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 3378 ** 0=Not Masked 3379 ** 1=Masked 3380 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 3381 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 3382 ** 0=Not Masked 3383 ** 1=Masked 3384 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 3385 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 3386 ** 0=Not Masked 3387 ** 1=Masked 3388 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 3389 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 3390 ** 0=Not Masked 3391 ** 1=Masked 3392 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 3393 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 3394 ** inbound write transaction. 3395 ** 0=SERR# Not Asserted due to error 3396 ** 1=SERR# Asserted due to error 3397 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 3398 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 3399 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is 3400 ** actually requested from the inbound read queue. 3401 ** 0=Disconnect with data 3402 ** (the data being up to 64 bits of 1��s) 3403 ** 1=Target Abort 3404 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 3405 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 3406 ** independent of the setting of this bit. 3407 *********************************************************************************** 3408 */ 3409 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 3410 /* 3411 *********************************************************************************** 3412 ** Inbound ATU Base Address Register 3 - IABAR3 3413 ** 3414 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 3415 ** of memory addresses where the inbound translation window 3 begins. 3416 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 3417 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 3418 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 3419 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 3420 ** Note: 3421 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 3422 ** IABAR3 is not configured by the host during normal system initialization. 3423 ** Warning: 3424 ** When a non-zero value is not written to IALR3, 3425 ** the user should not set either the Prefetchable Indicator 3426 ** or the Type Indicator for 64 bit addressability. 3427 ** This is the default for IABAR3. 3428 ** Assuming a non-zero value is written to IALR3, 3429 ** the user may set the Prefetchable Indicator 3430 ** or the Type Indicator: 3431 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 3432 ** when the Prefetchable Indicator is not set, 3433 ** the user should also leave the Type Indicator set for 32 bit addressability. 3434 ** This is the default for IABAR3. 3435 ** b. when the Prefetchable Indicator is set, 3436 ** the user should also set the Type Indicator for 64 bit addressability. 3437 ** ----------------------------------------------------------------- 3438 ** Bit Default Description 3439 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location 3440 ** the translation function is to respond to when addressed from the PCI bus. 3441 ** 11:04 00H Reserved. 3442 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 3443 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 3444 ** 00 - Memory Window is locatable anywhere in 32 bit address space 3445 ** 10 - Memory Window is locatable anywhere in 64 bit address space 3446 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3447 ** The ATU does not occupy I/O space, 3448 ** thus this bit must be zero. 3449 *********************************************************************************** 3450 */ 3451 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 3452 /* 3453 *********************************************************************************** 3454 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3 3455 ** 3456 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3457 ** Together with the Translation Base Address this register defines the actual location 3458 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3459 ** The programmed value within the base address register must comply with the PCI programming 3460 ** requirements for address alignment. 3461 ** Note: 3462 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 3463 ** the IAUBAR3 register attributes are read-only. 3464 ** This is the default for IABAR3. 3465 ** ----------------------------------------------------------------- 3466 ** Bit Default Description 3467 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 3468 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 3469 *********************************************************************************** 3470 */ 3471 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 3472 /* 3473 *********************************************************************************** 3474 ** Inbound ATU Limit Register 3 - IALR3 3475 ** 3476 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3477 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3478 ** PCI addresses to internal bus addresses. 3479 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3480 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3481 ** register provides the block size requirements for the base address register. The remaining registers 3482 ** used for performing address translation are discussed in Section 3.2.1.1. 3483 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3484 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3485 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3486 ** Specification, Revision 2.3 for additional information on programming base address registers. 3487 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3488 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3489 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3490 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3491 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3492 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3493 ** register. 3494 ** ----------------------------------------------------------------- 3495 ** Bit Default Description 3496 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3497 ** for the ATUs memory window 3. 3498 ** 11:00 000H Reserved 3499 *********************************************************************************** 3500 */ 3501 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3502 /* 3503 *********************************************************************************** 3504 ** Inbound ATU Translate Value Register 3 - IATVR3 3505 ** 3506 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3507 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3508 ** inbound ATU address translation. 3509 ** ----------------------------------------------------------------- 3510 ** Bit Default Description 3511 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3512 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3513 ** access the internal 80331 memory-mapped registers. 3514 ** 11:00 000H Reserved 3515 *********************************************************************************** 3516 */ 3517 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3518 /* 3519 *********************************************************************************** 3520 ** Outbound Configuration Cycle Address Register - OCCAR 3521 ** 3522 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3523 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3524 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3525 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3526 ** PCI bus. 3527 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3528 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3529 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3530 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3531 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3532 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3533 ** ----------------------------------------------------------------- 3534 ** Bit Default Description 3535 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3536 ** configuration read or write cycle. 3537 *********************************************************************************** 3538 */ 3539 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3540 /* 3541 *********************************************************************************** 3542 ** Outbound Configuration Cycle Data Register - OCCDR 3543 ** 3544 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 3545 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 3546 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to 3547 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 3548 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 3549 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 3550 ** actually entered into the data register (which does not physically exist). 3551 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 3552 ** within the ATU configuration space. 3553 ** ----------------------------------------------------------------- 3554 ** Bit Default Description 3555 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 3556 ** or write cycle. 3557 *********************************************************************************** 3558 */ 3559 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 3560 /* 3561 *********************************************************************************** 3562 ** VPD Capability Identifier Register - VPD_CAPID 3563 ** 3564 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3565 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3566 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 3567 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 3568 ** ----------------------------------------------------------------- 3569 ** Bit Default Description 3570 ** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability 3571 ** Headers as being the VPD capability registers. 3572 *********************************************************************************** 3573 */ 3574 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 3575 /* 3576 *********************************************************************************** 3577 ** VPD Next Item Pointer Register - VPD_NXTP 3578 ** 3579 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3580 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3581 ** For the 80331, this the final capability list, and hence, this register is set to 00H. 3582 ** ----------------------------------------------------------------- 3583 ** Bit Default Description 3584 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3585 ** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 3586 ** extended capabilities in the 80331, the register is set to 00H. 3587 *********************************************************************************** 3588 */ 3589 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 3590 /* 3591 *********************************************************************************** 3592 ** VPD Address Register - VPD_AR 3593 ** 3594 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 3595 ** accessed. The register is read/write and the initial value at power-up is indeterminate. 3596 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 3597 ** the Flag setting to determine whether the configuration write was intended to initiate a read or 3598 ** write of the VPD through the VPD Data Register. 3599 ** ----------------------------------------------------------------- 3600 ** Bit Default Description 3601 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 3602 ** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 3603 ** how the 80331 handles the data transfer. 3604 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 3605 ** Vital Product Data from the VPD storage component. 3606 *********************************************************************************** 3607 */ 3608 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 3609 /* 3610 *********************************************************************************** 3611 ** VPD Data Register - VPD_DR 3612 ** 3613 ** This register is used to transfer data between the 80331 and the VPD storage component. 3614 ** ----------------------------------------------------------------- 3615 ** Bit Default Description 3616 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 3617 *********************************************************************************** 3618 */ 3619 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 3620 /* 3621 *********************************************************************************** 3622 ** Power Management Capability Identifier Register -PM_CAPID 3623 ** 3624 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3625 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3626 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 3627 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 3628 ** Interface Specification, Revision 1.1. 3629 ** ----------------------------------------------------------------- 3630 ** Bit Default Description 3631 ** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability 3632 ** Headers as being the PCI Power Management Registers. 3633 *********************************************************************************** 3634 */ 3635 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 3636 /* 3637 *********************************************************************************** 3638 ** Power Management Next Item Pointer Register - PM_NXTP 3639 ** 3640 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3641 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3642 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 3643 ** ----------------------------------------------------------------- 3644 ** Bit Default Description 3645 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3646 ** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 3647 *********************************************************************************** 3648 */ 3649 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 3650 /* 3651 *********************************************************************************** 3652 ** Power Management Capabilities Register - PM_CAP 3653 ** 3654 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 3655 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 3656 ** information on the capabilities of the ATU function related to power management. 3657 ** ----------------------------------------------------------------- 3658 ** Bit Default Description 3659 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 3660 ** is not supported by the 80331. 3661 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 3662 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 3663 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 3664 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 3665 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 3666 ** following the transition to the D0 uninitialized state. 3667 ** 4 0 2 Reserved. 3668 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 3669 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 3670 ** Interface Specification, Revision 1.1 3671 *********************************************************************************** 3672 */ 3673 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 3674 /* 3675 *********************************************************************************** 3676 ** Power Management Control/Status Register - PM_CSR 3677 ** 3678 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 3679 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 3680 ** interface for the power management extended capability. 3681 ** ----------------------------------------------------------------- 3682 ** Bit Default Description 3683 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 3684 ** supported by the 80331. 3685 ** 14:9 00H Reserved 3686 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 3687 ** generation from any power state. 3688 ** 7:2 000000 2 Reserved 3689 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 3690 ** of a function and to set the function into a new power state. The definition of the values is: 3691 ** 00 2 - D0 3692 ** 01 2 - D1 3693 ** 10 2 - D2 (Unsupported) 3694 ** 11 2 - D3 hot 3695 ** The 80331 supports only the D0 and D3 hot states. 3696 ** 3697 *********************************************************************************** 3698 */ 3699 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 3700 /* 3701 *********************************************************************************** 3702 ** PCI-X Capability Identifier Register - PX_CAPID 3703 ** 3704 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3705 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3706 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 3707 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 3708 ** ----------------------------------------------------------------- 3709 ** Bit Default Description 3710 ** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability 3711 ** Headers as being the PCI-X capability registers. 3712 *********************************************************************************** 3713 */ 3714 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 3715 /* 3716 *********************************************************************************** 3717 ** PCI-X Next Item Pointer Register - PX_NXTP 3718 ** 3719 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3720 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3721 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 3722 ** to 00H. 3723 ** However, this register may be written to B8H prior to host configuration to include the VPD 3724 ** capability located at off-set B8H. 3725 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 3726 ** produce unpredictable system behavior. 3727 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be 3728 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 3729 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 3730 ** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 3731 ** PCSR�� on page 253 for more details on the 80331 initialization modes. 3732 ** ----------------------------------------------------------------- 3733 ** Bit Default Description 3734 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3735 ** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 3736 ** extended capabilities in the 80331, the register is set to 00H. 3737 ** However, this field may be written prior to host configuration with B8H to extend the list to include the 3738 ** VPD extended capabilities header. 3739 *********************************************************************************** 3740 */ 3741 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 3742 /* 3743 *********************************************************************************** 3744 ** PCI-X Command Register - PX_CMD 3745 ** 3746 ** This register controls various modes and features of ATU and Message Unit when operating in the 3747 ** PCI-X mode. 3748 ** ----------------------------------------------------------------- 3749 ** Bit Default Description 3750 ** 15:7 000000000 2 Reserved. 3751 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 3752 ** the device is permitted to have outstanding at one time. 3753 ** Register Maximum Outstanding 3754 ** 0 1 3755 ** 1 2 3756 ** 2 3 3757 ** 3 4 3758 ** 4 8 3759 ** 5 12 3760 ** 6 16 3761 ** 7 32 3762 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 3763 ** initiating a Sequence with one of the burst memory read commands. 3764 ** Register Maximum Byte Count 3765 ** 0 512 3766 ** 1 1024 3767 ** 2 2048 3768 ** 3 4096 3769 ** 1 0 2 3770 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 3771 ** of Transactions. 3772 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 3773 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 3774 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 3775 *********************************************************************************** 3776 */ 3777 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 3778 /* 3779 *********************************************************************************** 3780 ** PCI-X Status Register - PX_SR 3781 ** 3782 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 3783 ** Unit when operating in the PCI-X mode. 3784 ** ----------------------------------------------------------------- 3785 ** Bit Default Description 3786 ** 31:30 00 2 Reserved 3787 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3788 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 3789 ** writes a 1 to this location. 3790 ** 0=no Split Completion error message received. 3791 ** 1=a Split Completion error message has been received. 3792 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 3793 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 3794 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 3795 ** 1 16 512 (Default) 3796 ** 2 32 1024 3797 ** 2 32 2048 3798 ** 2 32 4096 3799 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 3800 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 3801 ** to 1024 bytes. 3802 ** 20 1 2 80331 is a complex device. 3803 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 3804 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 3805 ** 0=no unexpected Split Completion has been received. 3806 ** 1=an unexpected Split Completion has been received. 3807 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 3808 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 3809 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 3810 ** location. 3811 ** 0=no Split Completion has been discarded. 3812 ** 1=a Split Completion has been discarded. 3813 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 3814 ** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 3815 ** 17 1 2 80331 is a 133 MHz capable device. 3816 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 3817 ** therefore this bit is always set. 3818 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 3819 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 3820 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled 3821 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 3822 ** 0=The bus is 32 bits wide. 3823 ** 1=The bus is 64 bits wide. 3824 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 3825 ** segment for the device containing this function. The function uses this number as part of its Requester 3826 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 3827 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 3828 ** of the attribute phase of the Configuration Write, regardless of which register in the function is 3829 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 3830 ** the following are true: 3831 ** 1. The transaction uses a Configuration Write command. 3832 ** 2. IDSEL is asserted during the address phase. 3833 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 3834 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 3835 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 3836 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 3837 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection 3838 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 3839 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 3840 ** time the function is addressed by a Configuration Write transaction, the device must update this register 3841 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 3842 ** register in the function is addressed by the transaction. The function is addressed by a Configuration 3843 ** Write transaction when all of the following are true: 3844 ** 1. The transaction uses a Configuration Write command. 3845 ** 2. IDSEL is asserted during the address phase. 3846 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 3847 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 3848 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 3849 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 3850 ** configuration transaction to which this function responds. The function uses this number as part of its 3851 ** Requester ID and Completer ID. 3852 ** 3853 ************************************************************************** 3854 */ 3855 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 3856 3857 /* 3858 ************************************************************************** 3859 ** Inbound Read Transaction 3860 ** ======================================================================== 3861 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 3862 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through 3863 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 3864 ** (IRQ). 3865 ** When operating in the conventional PCI mode, all inbound read transactions are processed as 3866 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 3867 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 3868 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 3869 ** an inbound read transaction on the PCI bus is summarized in the following statements: 3870 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 3871 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 3872 ** Address Register during DACs) and Inbound Limit Register. 3873 ** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 3874 ** information from a previous delayed read, the current transaction information is compared to 3875 ** the previous transaction information (based on the setting of the DRC Alias bit in 3876 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 3877 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 3878 ** match and the data is not available, a Retry is signaled with no other action taken. When there 3879 ** is not a match and when the ITQ has less than eight entries, capture the transaction 3880 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and 3881 ** when the ITQ is full, then signal a Retry with no other action taken. 3882 ** �X When an address parity error is detected, the address parity response defined in 3883 ** Section 3.7 is used. 3884 ** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 3885 ** the IRQ, it continues until one of the following is true: 3886 ** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 3887 ** data is flushed. 3888 ** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 3889 ** Target Abort is never entered into the IRQ, and therefore is never returned. 3890 ** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 3891 ** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 3892 ** the initiator on the last data word available. 3893 ** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 3894 ** command are latched into the available ITQ and a Split Response Termination is signalled to 3895 ** the initiator. 3896 ** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 3897 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target 3898 ** before returning read data by generating the split completion transaction on the PCI-X bus. 3899 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 3900 ** transfer by returning data in 1024 byte aligned chunks. 3901 ** �E When operating in the PCI-X mode, once a split completion transaction has started, it 3902 ** continues until one of the following is true: 3903 ** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 3904 ** ADB (when the requester is a bridge) 3905 ** �X The byte count is satisfied. 3906 ** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 3907 ** Message (message class=2h - completer error, and message index=81h - target abort) to 3908 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 3909 ** Refer to Section 3.7.1. 3910 ** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 3911 ** Message (message class=2h - completer error, and message index=80h - Master abort) to 3912 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 3913 ** Refer to Section 3.7.1 3914 ** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 3915 ** bus, the ATU PCI slave interface waits with no premature disconnects. 3916 ** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 3917 ** taken by the target interface. Refer to Section 3.7.2.5. 3918 ** �E When operating in the conventional PCI mode, when the read on the internal bus is 3919 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 3920 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 3921 ** target abort is used, when clear, a disconnect is used. 3922 ** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 3923 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 3924 ** a Split Completion Message (message class=2h - completer error, and message index=81h - 3925 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU 3926 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 3927 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 3928 ** transaction is flushed. Refer to Section 3.7.1. 3929 ** �E When operating in the conventional PCI mode, when the transaction on the internal bus 3930 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the 3931 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 3932 ** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 3933 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer 3934 ** error, and message index=80h - internal bus master abort) to inform the requester about the 3935 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 3936 ** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 3937 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 3938 ** prevents it from accepting the completion it requested. In this case, since the Split Request 3939 ** addresses a location that has no read side effects, the completer must discard the Split 3940 ** Completion and take no further action. 3941 ** The data flow for an inbound read transaction on the internal bus is summarized in the following 3942 ** statements: 3943 ** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 3944 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 3945 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 3946 ** always uses conventional PCI ordering rules. 3947 ** �E Once the internal bus is granted, the internal bus master interface drives the translated address 3948 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 3949 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded 3950 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 3951 ** master has been delivered the target abort). 3952 ** �E Once the translated address is on the bus and the transaction has been accepted, the internal 3953 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 3954 ** received by the IRQ until one of the following is true: 3955 ** �X The full byte count requested by the ATU read request is received. The ATU internal bus 3956 ** initiator interface performs a initiator completion in this case. 3957 ** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 3958 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 3959 ** informed. 3960 ** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 3961 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 3962 ** Completion Message (message class=2h - completer error, and message index=81h - 3963 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The 3964 ** ITQ for this transaction is flushed. 3965 ** �X When operating in the conventional PCI mode, a single data phase disconnection is 3966 ** received from the internal bus target. When the data has not been received up to the next 3967 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 3968 ** When not, the bus returns to idle. 3969 ** �X When operating in the PCI-X mode, a single data phase disconnection is received from 3970 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 3971 ** obtain remaining data. 3972 ** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 3973 ** from the internal bus target. The bus returns to idle. 3974 ** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 3975 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 3976 ** remaining data. 3977 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 3978 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 3979 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 3980 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 3981 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 3982 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 3983 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 3984 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 3985 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 3986 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 3987 ** commands did not match, only the address. 3988 ************************************************************************** 3989 */ 3990 /* 3991 ************************************************************************** 3992 ** Inbound Write Transaction 3993 **======================================================================== 3994 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 3995 ** memory or a 80331 memory-mapped register. 3996 ** Data flow for an inbound write transaction on the PCI bus is summarized as: 3997 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 3998 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 3999 ** Base Address Register during DACs) and Inbound Limit Register. 4000 ** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 4001 ** available, the address is captured and the first data phase is accepted. 4002 ** �E The PCI interface continues to accept write data until one of the following is true: 4003 ** �X The initiator performs a disconnect. 4004 ** �X The transaction crosses a buffer boundary. 4005 ** �E When an address parity error is detected during the address phase of the transaction, the 4006 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 4007 ** parity error response. 4008 ** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 4009 ** parity error mechanism described in Section 3.7.1 is used. 4010 ** �E When a data parity error is detected while accepting data, the slave interface sets the 4011 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 4012 ** for details of the inbound write data parity error response. 4013 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 4014 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 4015 ** interface becomes aware of the inbound write. When there are additional write transactions ahead 4016 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 4017 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 4018 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 4019 ** interface, when operating in the PCI mode. 4020 ** In the PCI-X mode memory writes are always executed as immediate transactions, while 4021 ** configuration write transactions are processed as split transactions. The ATU generates a Split 4022 ** Completion Message, (with Message class=0h - Write Completion Class and Message index = 4023 ** 00h - Write Completion Message) once a configuration write is successfully executed. 4024 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 4025 ** The ATU handles such transactions as independent transactions. 4026 ** Data flow for the inbound write transaction on the internal bus is summarized as: 4027 ** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 4028 ** with associated data in the IWQ. 4029 ** �E When the internal bus is granted, the internal bus master interface initiates the write 4030 ** transaction by driving the translated address onto the internal bus. For details on inbound 4031 ** address translation. 4032 ** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 4033 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 4034 ** interface. 4035 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 4036 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 4037 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 4038 ** from the IWQ to the internal bus when data is available and the internal bus interface retains 4039 ** internal bus ownership. 4040 ** �E The internal bus interface stops transferring data from the current transaction to the internal 4041 ** bus when one of the following conditions becomes true: 4042 ** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 4043 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 4044 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 4045 ** complete the delivery of remaining data using the same sequence ID but with the 4046 ** modified starting address and byte count. 4047 ** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 4048 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 4049 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 4050 ** complete the delivery of remaining data using the same sequence ID but with the 4051 ** modified starting address and byte count. 4052 ** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 4053 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 4054 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 4055 ** bus to complete the delivery of remaining data using the same sequence ID but with the 4056 ** modified starting address and byte count. 4057 ** �X The data from the current transaction has completed (satisfaction of byte count). An 4058 ** initiator termination is performed and the bus returns to idle. 4059 ** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 4060 ** Data is flushed from the IWQ. 4061 ***************************************************************** 4062 */ 4063 4064 4065 4066 /* 4067 ************************************************************************** 4068 ** Inbound Read Completions Data Parity Errors 4069 **======================================================================== 4070 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4071 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 4072 ** completion transaction, the ATU attempts to complete the transaction normally and no further 4073 ** action is taken. 4074 ************************************************************************** 4075 */ 4076 4077 /* 4078 ************************************************************************** 4079 ** Inbound Configuration Write Completion Message Data Parity Errors 4080 **======================================================================== 4081 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4082 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 4083 ** assertion during the split completion transaction, the ATU attempts to complete the transaction 4084 ** normally and no further action is taken. 4085 ************************************************************************** 4086 */ 4087 4088 /* 4089 ************************************************************************** 4090 ** Inbound Read Request Data Parity Errors 4091 **===================== Immediate Data Transfer ========================== 4092 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 4093 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 4094 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 4095 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 4096 ** required and no error bits are set. 4097 **=====================Split Response Termination========================= 4098 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4099 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may 4100 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 4101 ** action is required and no error bits are set. 4102 ************************************************************************** 4103 */ 4104 4105 /* 4106 ************************************************************************** 4107 ** Inbound Write Request Data Parity Errors 4108 **======================================================================== 4109 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4110 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on 4111 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 4112 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with 4113 ** the given constraints are taken by the ATU: 4114 ** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 4115 ** following the data phase in which the data parity error is detected on the bus. This is only 4116 ** done when the Parity Error Response bit in the ATUCMD is set. 4117 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4118 ** actions is taken: 4119 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4120 ** Detected Parity Error bit in the ATUISR. When set, no action. 4121 *************************************************************************** 4122 */ 4123 4124 4125 /* 4126 *************************************************************************** 4127 ** Inbound Configuration Write Request 4128 ** ===================================================================== 4129 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4130 ** =============================================== 4131 ** Conventional PCI Mode 4132 ** =============================================== 4133 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 4134 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 4135 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following 4136 ** parts of the transactions: 4137 ** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 4138 ** address/command and data for delayed delivery to the internal configuration register. 4139 ** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 4140 ** of the operation back to the original master. 4141 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 4142 ** inbound transactions during Delayed Write Request cycles with the given constraints: 4143 ** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 4144 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 4145 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 4146 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 4147 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 4148 ** forwarded to the internal bus. PERR# is not asserted. 4149 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4150 ** actions is taken: 4151 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4152 ** Detected Parity Error bit in the ATUISR. When set, no action. 4153 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI 4154 ** bus and the ATU returns the status from the internal bus, completing the transaction. 4155 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 4156 ** therefore does not agree with the status being returned from the internal bus (i.e. status being 4157 ** returned is normal completion) the ATU performs the following actions with the given constraints: 4158 ** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 4159 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 4160 ** the IDWQ remains since the data of retried command did not match the data within the queue. 4161 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4162 ** actions is taken: 4163 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4164 ** Detected Parity Error bit in the ATUISR. When set, no action. 4165 ** =================================================== 4166 ** PCI-X Mode 4167 ** =================================================== 4168 ** Data parity errors occurring during configuration write operations received by the ATU may cause 4169 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 4170 ** occurs, the ATU accepts the write data and complete with a Split Response Termination. 4171 ** Specifically, the following actions with the given constraints are then taken by the ATU: 4172 ** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 4173 ** cycles following the Split Response Termination in which the data parity error is detected on 4174 ** the bus. When the ATU asserts PERR#, additional actions is taken: 4175 ** �X A Split Write Data Parity Error message (with message class=2h - completer error and 4176 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 4177 ** that addresses the requester of the configuration write. 4178 ** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 4179 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 4180 ** action. 4181 ** �X The Split Write Request is not enqueued and forwarded to the internal bus. 4182 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4183 ** actions is taken: 4184 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4185 ** Detected Parity Error bit in the ATUISR. When set, no action. 4186 ** 4187 *************************************************************************** 4188 */ 4189 4190 /* 4191 *************************************************************************** 4192 ** Split Completion Messages 4193 ** ======================================================================= 4194 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4195 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 4196 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 4197 ** ATU accepts the data and complete normally. Specifically, the following actions with the given 4198 ** constraints are taken by the ATU: 4199 ** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 4200 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 4201 ** is set. When the ATU asserts PERR#, additional actions is taken: 4202 ** �X The Master Parity Error bit in the ATUSR is set. 4203 ** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 4204 ** PCI Master Parity Error bit in the ATUISR. When set, no action. 4205 ** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 4206 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 4207 ** When the ATU asserts SERR#, additional actions is taken: 4208 ** Set the SERR# Asserted bit in the ATUSR. 4209 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 4210 ** SERR# Asserted bit in the ATUISR. When set, no action. 4211 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 4212 ** SERR# Detected bit in the ATUISR. When clear, no action. 4213 ** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 4214 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 4215 ** When the ATU sets this bit, additional actions is taken: 4216 ** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 4217 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 4218 ** When set, no action. 4219 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4220 ** actions is taken: 4221 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4222 ** Detected Parity Error bit in the ATUISR. When set, no action. 4223 ** �E The transaction associated with the Split Completion Message is discarded. 4224 ** �E When the discarded transaction was a read, a completion error message (with message 4225 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 4226 ** the internal bus of the 80331. 4227 ***************************************************************************** 4228 */ 4229 4230 4231 /* 4232 ****************************************************************************************************** 4233 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 4234 ** ================================================================================================== 4235 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331 4236 ** notifies the respective system when new data arrives. 4237 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 4238 ** window defined by: 4239 ** 1.Inbound ATU Base Address Register 0 (IABAR0) 4240 ** 2.Inbound ATU Limit Register 0 (IALR0) 4241 ** All of the Messaging Unit errors are reported in the same manner as ATU errors. 4242 ** Error conditions and status can be found in : 4243 ** 1.ATUSR 4244 ** 2.ATUISR 4245 **==================================================================================================== 4246 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 4247 **---------------------------------------------------------------------------------------------------- 4248 ** Message Registers 2 Inbound Optional Optional 4249 ** 2 Outbound 4250 **---------------------------------------------------------------------------------------------------- 4251 ** Doorbell Registers 1 Inbound Optional Optional 4252 ** 1 Outbound 4253 **---------------------------------------------------------------------------------------------------- 4254 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 4255 **---------------------------------------------------------------------------------------------------- 4256 ** Index Registers 1004 32-bit Memory Locations No Optional 4257 **==================================================================================================== 4258 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 4259 **==================================================================================================== 4260 ** 0000H Reserved 4261 ** 0004H Reserved 4262 ** 0008H Reserved 4263 ** 000CH Reserved 4264 **------------------------------------------------------------------------ 4265 ** 0010H Inbound Message Register 0 ] 4266 ** 0014H Inbound Message Register 1 ] 4267 ** 0018H Outbound Message Register 0 ] 4268 ** 001CH Outbound Message Register 1 ] 4 Message Registers 4269 **------------------------------------------------------------------------ 4270 ** 0020H Inbound Doorbell Register ] 4271 ** 0024H Inbound Interrupt Status Register ] 4272 ** 0028H Inbound Interrupt Mask Register ] 4273 ** 002CH Outbound Doorbell Register ] 4274 ** 0030H Outbound Interrupt Status Register ] 4275 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 4276 **------------------------------------------------------------------------ 4277 ** 0038H Reserved 4278 ** 003CH Reserved 4279 **------------------------------------------------------------------------ 4280 ** 0040H Inbound Queue Port ] 4281 ** 0044H Outbound Queue Port ] 2 Queue Ports 4282 **------------------------------------------------------------------------ 4283 ** 0048H Reserved 4284 ** 004CH Reserved 4285 **------------------------------------------------------------------------ 4286 ** 0050H ] 4287 ** : ] 4288 ** : Intel Xscale Microarchitecture Local Memory ] 4289 ** : ] 4290 ** 0FFCH ] 1004 Index Registers 4291 ******************************************************************************* 4292 */ 4293 /* 4294 ***************************************************************************** 4295 ** Theory of MU Operation 4296 ***************************************************************************** 4297 **-------------------- 4298 ** inbound_msgaddr0: 4299 ** inbound_msgaddr1: 4300 ** outbound_msgaddr0: 4301 ** outbound_msgaddr1: 4302 ** . The MU has four independent messaging mechanisms. 4303 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 4304 ** Each holds a 32-bit value and generates an interrupt when written. 4305 **-------------------- 4306 ** inbound_doorbell: 4307 ** outbound_doorbell: 4308 ** . The two Doorbell Registers support software interrupts. 4309 ** When a bit is set in a Doorbell Register, an interrupt is generated. 4310 **-------------------- 4311 ** inbound_queueport: 4312 ** outbound_queueport: 4313 ** 4314 ** 4315 ** . The Circular Queues support a message passing scheme that uses 4 circular queues. 4316 ** The 4 circular queues are implemented in 80331 local memory. 4317 ** Two queues are used for inbound messages and two are used for outbound messages. 4318 ** Interrupts may be generated when the queue is written. 4319 **-------------------- 4320 ** local_buffer 0x0050 ....0x0FFF 4321 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 4322 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 4323 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 4324 ** Each interrupt generated by the Messaging Unit can be masked. 4325 **-------------------- 4326 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 4327 ** with the exception of Multi-DWORD reads to the index registers. 4328 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 4329 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 4330 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 4331 ** and the data is returned through split completion transaction(s). 4332 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 4333 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 4334 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 4335 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 4336 **-------------------- 4337 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 4338 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 4339 ** This PCI address window is used for PCI transactions that access the 80331 local memory. 4340 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 4341 **-------------------- 4342 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 4343 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 4344 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 4345 ** The Messaging Unit reports all PCI errors in the ATU Status Register. 4346 **-------------------- 4347 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 4348 ** The register interface, message registers, doorbell registers, 4349 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 4350 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 4351 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 4352 ************************************************************************** 4353 */ 4354 /* 4355 ************************************************************************** 4356 ** Message Registers 4357 ** ============================== 4358 ** . Messages can be sent and received by the 80331 through the use of the Message Registers. 4359 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 4360 ** . Inbound messages are sent by the host processor and received by the 80331. 4361 ** Outbound messages are sent by the 80331 and received by the host processor. 4362 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 4363 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 4364 ** 4365 ** Inbound Messages: 4366 ** ----------------- 4367 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 4368 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 4369 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 4370 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 4371 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 4372 ** The interrupt is cleared when the Intel XScale core writes a value of 4373 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 4374 ** ------------------------------------------------------------------------ 4375 ** Inbound Message Register - IMRx 4376 ** 4377 ** . There are two Inbound Message Registers: IMR0 and IMR1. 4378 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 4379 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 4380 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 4381 ** ----------------------------------------------------------------- 4382 ** Bit Default Description 4383 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 4384 ** When written, an interrupt to the Intel XScale core may be generated. 4385 ************************************************************************** 4386 */ 4387 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 4388 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 4389 /* 4390 ************************************************************************** 4391 ** Outbound Message Register - OMRx 4392 ** -------------------------------- 4393 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 4394 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 4395 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 4396 ** Interrupt Mask Register. 4397 ** 4398 ** Bit Default Description 4399 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 4400 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 4401 ************************************************************************** 4402 */ 4403 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 4404 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 4405 /* 4406 ************************************************************************** 4407 ** Doorbell Registers 4408 ** ============================== 4409 ** There are two Doorbell Registers: 4410 ** Inbound Doorbell Register 4411 ** Outbound Doorbell Register 4412 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 4413 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 4414 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 4415 ** 4416 ** Inbound Doorbells: 4417 ** ------------------ 4418 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 4419 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 4420 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 4421 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 4422 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4423 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 4424 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 4425 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 4426 ** and not the values written to the Inbound Doorbell Register. 4427 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 4428 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 4429 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 4430 ** ------------------------------------------------------------------------ 4431 ** Inbound Doorbell Register - IDR 4432 ** 4433 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 4434 ** . Bit 31 is reserved for generating an Error Doorbell interrupt. 4435 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 4436 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 4437 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 4438 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 4439 ** ------------------------------------------------------------------------ 4440 ** Bit Default Description 4441 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 4442 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 4443 ** When all bits are clear, do not generate a Normal Interrupt. 4444 ************************************************************************** 4445 */ 4446 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 4447 /* 4448 ************************************************************************** 4449 ** Inbound Interrupt Status Register - IISR 4450 ** 4451 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4452 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4453 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4454 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4455 ** these two are routed to the Messaging Unit Error interrupt input. 4456 ** The generation of interrupts recorded in the Inbound Interrupt Status Register 4457 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4458 ** Some of the bits in this register are Read Only. 4459 ** For those bits, the interrupt must be cleared through another register. 4460 ** 4461 ** Bit Default Description 4462 ** 31:07 0000000H 0 2 Reserved 4463 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4464 ** when an Index Register has been written after a PCI transaction. 4465 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4466 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4467 ** An Error interrupt is generated for this condition. 4468 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4469 ** Once cleared, an interrupt does NOT be generated 4470 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4471 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4472 ** software must retain the information that the Inbound Post queue status is not empty. 4473 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4474 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4475 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4476 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4477 ** Normal Interrupt bit in the Inbound Doorbell Register is set. 4478 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4479 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4480 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4481 ************************************************************************** 4482 */ 4483 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4484 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4485 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4486 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4487 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4488 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4489 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4490 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4491 /* 4492 ************************************************************************** 4493 ** Inbound Interrupt Mask Register - IIMR 4494 ** 4495 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4496 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4497 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4498 ** They only affect the generation of the Intel XScale core interrupt. 4499 ** ------------------------------------------------------------------------ 4500 ** Bit Default Description 4501 ** 31:07 000000H 0 2 Reserved 4502 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4503 ** when an Index Register has been written after a PCI transaction. 4504 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4505 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4506 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4507 ** by the MU hardware when the Inbound Post Queue has been written. 4508 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4509 ** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4510 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4511 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4512 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4513 ** Interrupt generated by a write to the Inbound Message 1 Register. 4514 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4515 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4516 ************************************************************************** 4517 */ 4518 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4519 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4520 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4521 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4522 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4523 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4524 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4525 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4526 /* 4527 ************************************************************************** 4528 ** Outbound Doorbell Register - ODR 4529 ** 4530 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4531 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4532 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4533 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4534 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4535 ** be cleared by an external PCI agent. 4536 ** ---------------------------------------------------------------------- 4537 ** Bit Default Description 4538 ** 31 0 2 Reserved 4539 ** 30 0 2 Reserved. 4540 ** 29 0 2 Reserved 4541 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4542 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4543 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4544 ** When this bit is cleared, the P_INTC# interrupt output 4545 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4546 ** signal is deasserted. 4547 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 4548 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4549 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 4550 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 4551 ** signal is deasserted. 4552 ************************************************************************** 4553 */ 4554 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 4555 /* 4556 ************************************************************************** 4557 ** Outbound Interrupt Status Register - OISR 4558 ** 4559 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 4560 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 4561 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 4562 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 4563 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 4564 ** register. 4565 ** ---------------------------------------------------------------------- 4566 ** Bit Default Description 4567 ** 31:05 000000H 000 2 Reserved 4568 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 4569 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 4570 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 4571 ** cleared when any prefetch data has been read from the Outbound Queue Port. 4572 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 4573 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 4574 ** Doorbell Register must all be clear. 4575 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 4576 ** written. Clearing this bit clears the interrupt. 4577 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 4578 ** written. Clearing this bit clears the interrupt. 4579 ************************************************************************** 4580 */ 4581 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 4582 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 4583 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 4584 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 4585 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 4586 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 4587 /* 4588 ************************************************************************** 4589 ** Outbound Interrupt Mask Register - OIMR 4590 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 4591 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 4592 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 4593 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 4594 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 4595 ** only affect the generation of the PCI interrupt. 4596 ** ---------------------------------------------------------------------- 4597 ** Bit Default Description 4598 ** 31:05 000000H Reserved 4599 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 4600 ** in the Outbound Doorbell Register is set. 4601 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 4602 ** the prefetch buffer is valid. 4603 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 4604 ** Doorbell Register. 4605 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 4606 ** generated by a write to the Outbound Message 1 Register. 4607 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 4608 ** generated by a write to the Outbound Message 0 Register. 4609 ************************************************************************** 4610 */ 4611 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 4612 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 4613 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 4614 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 4615 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 4616 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 4617 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 4618 /* 4619 ************************************************************************** 4620 ** 4621 ************************************************************************** 4622 */ 4623 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 4624 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 4625 /* 4626 ************************************************************************** 4627 ** Circular Queues 4628 ** ====================================================================== 4629 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 4630 ** this case, inbound and outbound refer to the direction of the flow of posted messages. 4631 ** Inbound messages are either: 4632 ** �E posted messages by other processors for the Intel XScale core to process or 4633 ** �E free (or empty) messages that can be reused by other processors. 4634 ** Outbound messages are either: 4635 ** �E posted messages by the Intel XScale core for other processors to process or 4636 ** �E free (or empty) messages that can be reused by the Intel XScale core. 4637 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 4638 ** The four Circular Queues are used to pass messages in the following manner. 4639 ** . The two inbound queues are used to handle inbound messages 4640 ** and the two outbound queues are used to handle outbound messages. 4641 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 4642 ** The other inbound queue is designated the Post queue and it contains inbound posted messages. 4643 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 4644 ** 4645 ** ============================================================================================================= 4646 ** Circular Queue Summary 4647 ** _____________________________________________________________________________________________________________ 4648 ** | Queue Name | Purpose | Action on PCI Interface| 4649 ** |______________________|____________________________________________________________|_________________________| 4650 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 4651 ** | | waiting to be processed by the 80331 | | 4652 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 4653 ** | | available for use by other processors | | 4654 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 4655 ** | | that are being posted to the other processors | | 4656 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 4657 ** | | available for use by the 80331 | | 4658 ** |______________________|____________________________________________________________|_________________________| 4659 ** 4660 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 4661 ** queue and to receive free messages returning from the 80331. 4662 ** The host processor posts inbound messages, 4663 ** the Intel XScale core receives the posted message and when it is finished with the message, 4664 ** places it back on the inbound free queue for reuse by the host processor. 4665 ** 4666 ** The circular queues are accessed by external PCI agents through two port locations in the PCI 4667 ** address space: 4668 ** Inbound Queue Port 4669 ** and Outbound Queue Port. 4670 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 4671 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 4672 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 4673 ** does not cause the MU hardware to increment the queue pointers. 4674 ** This is treated as when the PCI transaction did not occur. 4675 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 4676 ** ====================================================================================== 4677 ** Overview of Circular Queue Operation 4678 ** ====================================================================================== 4679 ** . The data storage for the circular queues must be provided by the 80331 local memory. 4680 ** . The base address of the circular queues is contained in the Queue Base Address Register. 4681 ** Each entry in the queue is a 32-bit data value. 4682 ** . Each read from or write to the queue may access only one queue entry. 4683 ** . Multi-DWORD accesses to the circular queues are not allowed. 4684 ** Sub-DWORD accesses are promoted to DWORD accesses. 4685 ** . Each circular queue has a head pointer and a tail pointer. 4686 ** The pointers are offsets from the Queue Base Address. 4687 ** . Writes to a queue occur at the head of the queue and reads occur from the tail. 4688 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 4689 ** Which unit maintains the pointer is determined by the writer of the queue. 4690 ** More details about the pointers are given in the queue descriptions below. 4691 ** The pointers are incremented after the queue access. 4692 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 4693 ** 4694 ** Messaging Unit... 4695 ** 4696 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 4697 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 4698 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 4699 ** . All four queues must be the same size and may be contiguous. 4700 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 4701 ** The Queue size is determined by the Queue Size field in the MU Configuration Register. 4702 ** . There is one base address for all four queues. 4703 ** It is stored in the Queue Base Address Register (QBAR). 4704 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 4705 ** here shows an example of how the circular queues should be set up based on the 4706 ** Intelligent I/O (I 2 O) Architecture Specification. 4707 ** Other ordering of the circular queues is possible. 4708 ** 4709 ** Queue Starting Address 4710 ** Inbound Free Queue QBAR 4711 ** Inbound Post Queue QBAR + Queue Size 4712 ** Outbound Post Queue QBAR + 2 * Queue Size 4713 ** Outbound Free Queue QBAR + 3 * Queue Size 4714 ** =================================================================================== 4715 ** Inbound Post Queue 4716 ** ------------------ 4717 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 4718 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 4719 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 4720 ** For a PCI write transaction that accesses the Inbound Queue Port, 4721 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 4722 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 4723 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 4724 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 4725 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 4726 ** The interrupt can be masked by the Inbound Interrupt Mask Register. 4727 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 4728 ** that the full condition is recognized by the core processor. 4729 ** In addition, to guarantee that the queue does not get overwritten, 4730 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 4731 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4732 ** Only a new message posting the in the inbound queue generates a new interrupt. 4733 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4734 ** software must retain the information that the Inbound Post queue status. 4735 ** From the time that the PCI write transaction is received until the data is written 4736 ** in local memory and the Inbound Post Head Pointer Register is incremented, 4737 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 4738 ** The Intel XScale core may read messages from the Inbound Post Queue 4739 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 4740 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 4741 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 4742 ** the hardware retries any PCI writes until a slot in the queue becomes available. 4743 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 4744 ** =================================================================================== 4745 ** Inbound Free Queue 4746 ** ------------------ 4747 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 4748 ** This queue is read from the queue tail by external PCI agents. 4749 ** It is written to the queue head by the Intel XScale core. 4750 ** The tail pointer is maintained by the MU hardware. 4751 ** The head pointer is maintained by the Intel XScale core. 4752 ** For a PCI read transaction that accesses the Inbound Queue Port, 4753 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 4754 ** When the queue is not empty (head and tail pointers are not equal) 4755 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 4756 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 4757 ** the value of -1 (FFFF.FFFFH) is returned. 4758 ** When the queue was not empty and the MU succeeded in returning the data at the tail, 4759 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 4760 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 4761 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 4762 ** When the PCI read access occurs, the data is read directly from the prefetch register. 4763 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 4764 ** when the head and tail pointers are equal and the queue is empty. 4765 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 4766 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 4767 ** and the Inbound Free Head Pointer Register is written. 4768 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 4769 ** A prefetch must appear atomic from the perspective of the external PCI agent. 4770 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 4771 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 4772 ** local memory location pointed to by the Inbound Free Head Pointer Register. 4773 ** The processor must then increment the Inbound Free Head Pointer Register. 4774 ** ================================================================================== 4775 ** Outbound Post Queue 4776 ** ------------------- 4777 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 4778 ** core for other processors to process. This queue is read from the queue tail by external PCI agents. 4779 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 4780 ** MU hardware. The head pointer is maintained by the Intel XScale core. 4781 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 4782 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 4783 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 4784 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail 4785 ** pointers are equal and the head pointer was last updated by hardware), the value of -1 4786 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 4787 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 4788 ** Register. 4789 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 4790 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 4791 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 4792 ** occurs, the data is read directly from the prefetch register. 4793 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 4794 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 4795 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 4796 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 4797 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 4798 ** Pointer Register when it adds messages to the queue. 4799 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 4800 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 4801 ** until the prefetch is completed. 4802 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 4803 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 4804 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 4805 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 4806 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 4807 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 4808 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then 4809 ** increment the Outbound Post Head Pointer Register. 4810 ** ================================================== 4811 ** Outbound Free Queue 4812 ** ----------------------- 4813 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel 4814 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 4815 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 4816 ** XScale core. The head pointer is maintained by the MU hardware. 4817 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 4818 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the 4819 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 4820 ** Head Pointer Register. 4821 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 4822 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 4823 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 4824 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 4825 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 4826 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 4827 ** core processor. 4828 ** From the time that a PCI write transaction is received until the data is written in local memory and 4829 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 4830 ** access the Outbound Free Queue Port is signalled a retry. 4831 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 4832 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 4833 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 4834 ** the hardware must retry any PCI writes until a slot in the queue becomes available. 4835 ** 4836 ** ================================================================================== 4837 ** Circular Queue Summary 4838 ** ---------------------- 4839 ** ________________________________________________________________________________________________________________________________________________ 4840 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 4841 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4842 ** |Inbound Post | Inbound Queue | | | | | 4843 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 4844 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4845 ** |Inbound Free | Inbound Queue | | | | | 4846 ** | Queue | Port | NO | NO | Intel XScale | MU hardware | 4847 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4848 ** ================================================================================== 4849 ** Circular Queue Status Summary 4850 ** ---------------------- 4851 ** ____________________________________________________________________________________________________ 4852 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 4853 ** |_____________________|________________|_____________________|_______________________________________| 4854 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 4855 ** |_____________________|________________|_____________________|_______________________________________| 4856 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 4857 ** |_____________________|________________|_____________________|_______________________________________| 4858 ************************************************************************** 4859 */ 4860 4861 /* 4862 ************************************************************************** 4863 ** Index Registers 4864 ** ======================== 4865 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 4866 ** These registers are for inbound messages only. 4867 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4868 ** The storage for the Index Registers is allocated from the 80331 local memory. 4869 ** PCI write accesses to the Index Registers write the data to local memory. 4870 ** PCI read accesses to the Index Registers read the data from local memory. 4871 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 4872 ** to Inbound ATU Translate Value Register + FFFH. 4873 ** . The address of the first write access is stored in the Index Address Register. 4874 ** This register is written during the earliest write access and provides a means to determine which Index Register was written. 4875 ** Once updated by the MU, the Index Address Register is not updated until the Index Register 4876 ** Interrupt bit in the Inbound Interrupt Status Register is cleared. 4877 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 4878 ** Writes by the Intel XScale core to the local memory used by the Index Registers 4879 ** does not cause an interrupt and does not update the Index Address Register. 4880 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 4881 ************************************************************************** 4882 */ 4883 /* 4884 ************************************************************************** 4885 ** Messaging Unit Internal Bus Memory Map 4886 ** ======================================= 4887 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 4888 ** FFFF E300H reserved | 4889 ** .. .. | 4890 ** FFFF E30CH reserved | 4891 ** FFFF E310H Inbound Message Register 0 | Available through 4892 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 4893 ** FFFF E318H Outbound Message Register 0 | 4894 ** FFFF E31CH Outbound Message Register 1 | or 4895 ** FFFF E320H Inbound Doorbell Register | 4896 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 4897 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 4898 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 4899 ** FFFF E330H Outbound Interrupt Status Register | 4900 ** FFFF E334H Outbound Interrupt Mask Register | 4901 ** ______________________________________________________________________|________________________________________ 4902 ** FFFF E338H reserved | 4903 ** FFFF E33CH reserved | 4904 ** FFFF E340H reserved | 4905 ** FFFF E344H reserved | 4906 ** FFFF E348H reserved | 4907 ** FFFF E34CH reserved | 4908 ** FFFF E350H MU Configuration Register | 4909 ** FFFF E354H Queue Base Address Register | 4910 ** FFFF E358H reserved | 4911 ** FFFF E35CH reserved | must translate PCI address to 4912 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 4913 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 4914 ** FFFF E368H Inbound Post Head pointer Register | 4915 ** FFFF E36CH Inbound Post Tail Pointer Register | 4916 ** FFFF E370H Outbound Free Head Pointer Register | 4917 ** FFFF E374H Outbound Free Tail Pointer Register | 4918 ** FFFF E378H Outbound Post Head pointer Register | 4919 ** FFFF E37CH Outbound Post Tail Pointer Register | 4920 ** FFFF E380H Index Address Register | 4921 ** FFFF E384H reserved | 4922 ** .. .. | 4923 ** FFFF E3FCH reserved | 4924 ** ______________________________________________________________________|_______________________________________ 4925 ************************************************************************** 4926 */ 4927 /* 4928 ************************************************************************** 4929 ** MU Configuration Register - MUCR FFFF.E350H 4930 ** 4931 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 4932 ** . The Circular Queue Enable bit enables or disables the Circular Queues. 4933 ** The Circular Queues are disabled at reset to allow the software to initialize the head 4934 ** and tail pointer registers before any PCI accesses to the Queue Ports. 4935 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 4936 ** ------------------------------------------------------------------------ 4937 ** Bit Default Description 4938 ** 31:06 000000H 00 2 Reserved 4939 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 4940 ** All four queues are the same size. 4941 ** �E 00001 2 - 4K Entries (16 Kbytes) 4942 ** �E 00010 2 - 8K Entries (32 Kbytes) 4943 ** �E 00100 2 - 16K Entries (64 Kbytes) 4944 ** �E 01000 2 - 32K Entries (128 Kbytes) 4945 ** �E 10000 2 - 64K Entries (256 Kbytes) 4946 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 4947 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 4948 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 4949 ** disabled. When set, the Circular Queues are fully enabled. 4950 ************************************************************************** 4951 */ 4952 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 4953 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 4954 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 4955 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 4956 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 4957 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 4958 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 4959 /* 4960 ************************************************************************** 4961 ** Queue Base Address Register - QBAR 4962 ** 4963 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 4964 ** The base address is required to be located on a 1 Mbyte address boundary. 4965 ** . All Circular Queue head and tail pointers are based on the QBAR. 4966 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 4967 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 4968 ** Warning: 4969 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 4970 ** ------------------------------------------------------------------------ 4971 ** Bit Default Description 4972 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4973 ** 19:00 00000H Reserved 4974 ************************************************************************** 4975 */ 4976 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 4977 /* 4978 ************************************************************************** 4979 ** Inbound Free Head Pointer Register - IFHPR 4980 ** 4981 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 4982 ** the Queue Base Address of the head pointer for the Inbound Free Queue. 4983 ** The Head Pointer must be aligned on a DWORD address boundary. 4984 ** When read, the Queue Base Address is provided in the upper 12 bits of the register. 4985 ** Writes to the upper 12 bits of the register are ignored. 4986 ** This register is maintained by software. 4987 ** ------------------------------------------------------------------------ 4988 ** Bit Default Description 4989 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4990 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 4991 ** 01:00 00 2 Reserved 4992 ************************************************************************** 4993 */ 4994 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 4995 /* 4996 ************************************************************************** 4997 ** Inbound Free Tail Pointer Register - IFTPR 4998 ** 4999 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 5000 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 5001 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5002 ** of the register. Writes to the upper 12 bits of the register are ignored. 5003 ** ------------------------------------------------------------------------ 5004 ** Bit Default Description 5005 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5006 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 5007 ** 01:00 00 2 Reserved 5008 ************************************************************************** 5009 */ 5010 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 5011 /* 5012 ************************************************************************** 5013 ** Inbound Post Head Pointer Register - IPHPR 5014 ** 5015 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 5016 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 5017 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5018 ** of the register. Writes to the upper 12 bits of the register are ignored. 5019 ** ------------------------------------------------------------------------ 5020 ** Bit Default Description 5021 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5022 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 5023 ** 01:00 00 2 Reserved 5024 ************************************************************************** 5025 */ 5026 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 5027 /* 5028 ************************************************************************** 5029 ** Inbound Post Tail Pointer Register - IPTPR 5030 ** 5031 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 5032 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 5033 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5034 ** of the register. Writes to the upper 12 bits of the register are ignored. 5035 ** ------------------------------------------------------------------------ 5036 ** Bit Default Description 5037 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5038 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 5039 ** 01:00 00 2 Reserved 5040 ************************************************************************** 5041 */ 5042 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 5043 /* 5044 ************************************************************************** 5045 ** Index Address Register - IAR 5046 ** 5047 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 5048 ** It is written by the MU when the Index Registers are written by a PCI agent. 5049 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 5050 ** . The local memory address of the Index Register least recently accessed is computed 5051 ** by adding the Index Address Register to the Inbound ATU Translate Value Register. 5052 ** ------------------------------------------------------------------------ 5053 ** Bit Default Description 5054 ** 31:12 000000H Reserved 5055 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 5056 ** 01:00 00 2 Reserved 5057 ************************************************************************** 5058 */ 5059 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 5060 /* 5061 ********************************************************************************************************** 5062 ** RS-232 Interface for Areca Raid Controller 5063 ** The low level command interface is exclusive with VT100 terminal 5064 ** -------------------------------------------------------------------- 5065 ** 1. Sequence of command execution 5066 ** -------------------------------------------------------------------- 5067 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5068 ** (B) Command block : variable length of data including length, command code, data and checksum byte 5069 ** (C) Return data : variable length of data 5070 ** -------------------------------------------------------------------- 5071 ** 2. Command block 5072 ** -------------------------------------------------------------------- 5073 ** (A) 1st byte : command block length (low byte) 5074 ** (B) 2nd byte : command block length (high byte) 5075 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 5076 ** (C) 3rd byte : command code 5077 ** (D) 4th and following bytes : variable length data bytes depends on command code 5078 ** (E) last byte : checksum byte (sum of 1st byte until last data byte) 5079 ** -------------------------------------------------------------------- 5080 ** 3. Command code and associated data 5081 ** -------------------------------------------------------------------- 5082 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 5083 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 5084 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 5085 ** enum 5086 ** { 5087 ** GUI_SET_SERIAL=0x10, 5088 ** GUI_SET_VENDOR, 5089 ** GUI_SET_MODEL, 5090 ** GUI_IDENTIFY, 5091 ** GUI_CHECK_PASSWORD, 5092 ** GUI_LOGOUT, 5093 ** GUI_HTTP, 5094 ** GUI_SET_ETHERNET_ADDR, 5095 ** GUI_SET_LOGO, 5096 ** GUI_POLL_EVENT, 5097 ** GUI_GET_EVENT, 5098 ** GUI_GET_HW_MONITOR, 5099 ** 5100 ** // GUI_QUICK_CREATE=0x20, (function removed) 5101 ** GUI_GET_INFO_R=0x20, 5102 ** GUI_GET_INFO_V, 5103 ** GUI_GET_INFO_P, 5104 ** GUI_GET_INFO_S, 5105 ** GUI_CLEAR_EVENT, 5106 ** 5107 ** GUI_MUTE_BEEPER=0x30, 5108 ** GUI_BEEPER_SETTING, 5109 ** GUI_SET_PASSWORD, 5110 ** GUI_HOST_INTERFACE_MODE, 5111 ** GUI_REBUILD_PRIORITY, 5112 ** GUI_MAX_ATA_MODE, 5113 ** GUI_RESET_CONTROLLER, 5114 ** GUI_COM_PORT_SETTING, 5115 ** GUI_NO_OPERATION, 5116 ** GUI_DHCP_IP, 5117 ** 5118 ** GUI_CREATE_PASS_THROUGH=0x40, 5119 ** GUI_MODIFY_PASS_THROUGH, 5120 ** GUI_DELETE_PASS_THROUGH, 5121 ** GUI_IDENTIFY_DEVICE, 5122 ** 5123 ** GUI_CREATE_RAIDSET=0x50, 5124 ** GUI_DELETE_RAIDSET, 5125 ** GUI_EXPAND_RAIDSET, 5126 ** GUI_ACTIVATE_RAIDSET, 5127 ** GUI_CREATE_HOT_SPARE, 5128 ** GUI_DELETE_HOT_SPARE, 5129 ** 5130 ** GUI_CREATE_VOLUME=0x60, 5131 ** GUI_MODIFY_VOLUME, 5132 ** GUI_DELETE_VOLUME, 5133 ** GUI_START_CHECK_VOLUME, 5134 ** GUI_STOP_CHECK_VOLUME 5135 ** }; 5136 ** 5137 ** Command description : 5138 ** 5139 ** GUI_SET_SERIAL : Set the controller serial# 5140 ** byte 0,1 : length 5141 ** byte 2 : command code 0x10 5142 ** byte 3 : password length (should be 0x0f) 5143 ** byte 4-0x13 : should be "ArEcATecHnoLogY" 5144 ** byte 0x14--0x23 : Serial number string (must be 16 bytes) 5145 ** GUI_SET_VENDOR : Set vendor string for the controller 5146 ** byte 0,1 : length 5147 ** byte 2 : command code 0x11 5148 ** byte 3 : password length (should be 0x08) 5149 ** byte 4-0x13 : should be "ArEcAvAr" 5150 ** byte 0x14--0x3B : vendor string (must be 40 bytes) 5151 ** GUI_SET_MODEL : Set the model name of the controller 5152 ** byte 0,1 : length 5153 ** byte 2 : command code 0x12 5154 ** byte 3 : password length (should be 0x08) 5155 ** byte 4-0x13 : should be "ArEcAvAr" 5156 ** byte 0x14--0x1B : model string (must be 8 bytes) 5157 ** GUI_IDENTIFY : Identify device 5158 ** byte 0,1 : length 5159 ** byte 2 : command code 0x13 5160 ** return "Areca RAID Subsystem " 5161 ** GUI_CHECK_PASSWORD : Verify password 5162 ** byte 0,1 : length 5163 ** byte 2 : command code 0x14 5164 ** byte 3 : password length 5165 ** byte 4-0x?? : user password to be checked 5166 ** GUI_LOGOUT : Logout GUI (force password checking on next command) 5167 ** byte 0,1 : length 5168 ** byte 2 : command code 0x15 5169 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 5170 ** 5171 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 5172 ** byte 0,1 : length 5173 ** byte 2 : command code 0x17 5174 ** byte 3 : password length (should be 0x08) 5175 ** byte 4-0x13 : should be "ArEcAvAr" 5176 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 5177 ** GUI_SET_LOGO : Set logo in HTTP 5178 ** byte 0,1 : length 5179 ** byte 2 : command code 0x18 5180 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 5181 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 5182 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 5183 ** note .... page0 1st 2 byte must be actual length of the JPG file 5184 ** GUI_POLL_EVENT : Poll If Event Log Changed 5185 ** byte 0,1 : length 5186 ** byte 2 : command code 0x19 5187 ** GUI_GET_EVENT : Read Event 5188 ** byte 0,1 : length 5189 ** byte 2 : command code 0x1a 5190 ** byte 3 : Event Page (0:1st page/1/2/3:last page) 5191 ** GUI_GET_HW_MONITOR : Get HW monitor data 5192 ** byte 0,1 : length 5193 ** byte 2 : command code 0x1b 5194 ** byte 3 : # of FANs(example 2) 5195 ** byte 4 : # of Voltage sensor(example 3) 5196 ** byte 5 : # of temperature sensor(example 2) 5197 ** byte 6 : # of power 5198 ** byte 7/8 : Fan#0 (RPM) 5199 ** byte 9/10 : Fan#1 5200 ** byte 11/12 : Voltage#0 original value in *1000 5201 ** byte 13/14 : Voltage#0 value 5202 ** byte 15/16 : Voltage#1 org 5203 ** byte 17/18 : Voltage#1 5204 ** byte 19/20 : Voltage#2 org 5205 ** byte 21/22 : Voltage#2 5206 ** byte 23 : Temp#0 5207 ** byte 24 : Temp#1 5208 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 5209 ** byte 26 : UPS indicator 5210 ** GUI_QUICK_CREATE : Quick create raid/volume set 5211 ** byte 0,1 : length 5212 ** byte 2 : command code 0x20 5213 ** byte 3/4/5/6 : raw capacity 5214 ** byte 7 : raid level 5215 ** byte 8 : stripe size 5216 ** byte 9 : spare 5217 ** byte 10/11/12/13: device mask (the devices to create raid/volume) 5218 ** This function is removed, application like to implement quick create function 5219 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 5220 ** GUI_GET_INFO_R : Get Raid Set Information 5221 ** byte 0,1 : length 5222 ** byte 2 : command code 0x20 5223 ** byte 3 : raidset# 5224 ** 5225 ** typedef struct sGUI_RAIDSET 5226 ** { 5227 ** BYTE grsRaidSetName[16]; 5228 ** DWORD grsCapacity; 5229 ** DWORD grsCapacityX; 5230 ** DWORD grsFailMask; 5231 ** BYTE grsDevArray[32]; 5232 ** BYTE grsMemberDevices; 5233 ** BYTE grsNewMemberDevices; 5234 ** BYTE grsRaidState; 5235 ** BYTE grsVolumes; 5236 ** BYTE grsVolumeList[16]; 5237 ** BYTE grsRes1; 5238 ** BYTE grsRes2; 5239 ** BYTE grsRes3; 5240 ** BYTE grsFreeSegments; 5241 ** DWORD grsRawStripes[8]; 5242 ** DWORD grsRes4; 5243 ** DWORD grsRes5; // Total to 128 bytes 5244 ** DWORD grsRes6; // Total to 128 bytes 5245 ** } sGUI_RAIDSET, *pGUI_RAIDSET; 5246 ** GUI_GET_INFO_V : Get Volume Set Information 5247 ** byte 0,1 : length 5248 ** byte 2 : command code 0x21 5249 ** byte 3 : volumeset# 5250 ** 5251 ** typedef struct sGUI_VOLUMESET 5252 ** { 5253 ** BYTE gvsVolumeName[16]; // 16 5254 ** DWORD gvsCapacity; 5255 ** DWORD gvsCapacityX; 5256 ** DWORD gvsFailMask; 5257 ** DWORD gvsStripeSize; 5258 ** DWORD gvsNewFailMask; 5259 ** DWORD gvsNewStripeSize; 5260 ** DWORD gvsVolumeStatus; 5261 ** DWORD gvsProgress; // 32 5262 ** sSCSI_ATTR gvsScsi; 5263 ** BYTE gvsMemberDisks; 5264 ** BYTE gvsRaidLevel; // 8 5265 ** 5266 ** BYTE gvsNewMemberDisks; 5267 ** BYTE gvsNewRaidLevel; 5268 ** BYTE gvsRaidSetNumber; 5269 ** BYTE gvsRes0; // 4 5270 ** BYTE gvsRes1[4]; // 64 bytes 5271 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 5272 ** 5273 ** GUI_GET_INFO_P : Get Physical Drive Information 5274 ** byte 0,1 : length 5275 ** byte 2 : command code 0x22 5276 ** byte 3 : drive # (from 0 to max-channels - 1) 5277 ** 5278 ** typedef struct sGUI_PHY_DRV 5279 ** { 5280 ** BYTE gpdModelName[40]; 5281 ** BYTE gpdSerialNumber[20]; 5282 ** BYTE gpdFirmRev[8]; 5283 ** DWORD gpdCapacity; 5284 ** DWORD gpdCapacityX; // Reserved for expansion 5285 ** BYTE gpdDeviceState; 5286 ** BYTE gpdPioMode; 5287 ** BYTE gpdCurrentUdmaMode; 5288 ** BYTE gpdUdmaMode; 5289 ** BYTE gpdDriveSelect; 5290 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 5291 ** sSCSI_ATTR gpdScsi; 5292 ** BYTE gpdReserved[40]; // Total to 128 bytes 5293 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 5294 ** 5295 ** GUI_GET_INFO_S : Get System Information 5296 ** byte 0,1 : length 5297 ** byte 2 : command code 0x23 5298 ** 5299 ** typedef struct sCOM_ATTR 5300 ** { 5301 ** BYTE comBaudRate; 5302 ** BYTE comDataBits; 5303 ** BYTE comStopBits; 5304 ** BYTE comParity; 5305 ** BYTE comFlowControl; 5306 ** } sCOM_ATTR, *pCOM_ATTR; 5307 ** 5308 ** typedef struct sSYSTEM_INFO 5309 ** { 5310 ** BYTE gsiVendorName[40]; 5311 ** BYTE gsiSerialNumber[16]; 5312 ** BYTE gsiFirmVersion[16]; 5313 ** BYTE gsiBootVersion[16]; 5314 ** BYTE gsiMbVersion[16]; 5315 ** BYTE gsiModelName[8]; 5316 ** BYTE gsiLocalIp[4]; 5317 ** BYTE gsiCurrentIp[4]; 5318 ** DWORD gsiTimeTick; 5319 ** DWORD gsiCpuSpeed; 5320 ** DWORD gsiICache; 5321 ** DWORD gsiDCache; 5322 ** DWORD gsiScache; 5323 ** DWORD gsiMemorySize; 5324 ** DWORD gsiMemorySpeed; 5325 ** DWORD gsiEvents; 5326 ** BYTE gsiMacAddress[6]; 5327 ** BYTE gsiDhcp; 5328 ** BYTE gsiBeeper; 5329 ** BYTE gsiChannelUsage; 5330 ** BYTE gsiMaxAtaMode; 5331 ** BYTE gsiSdramEcc; // 1:if ECC enabled 5332 ** BYTE gsiRebuildPriority; 5333 ** sCOM_ATTR gsiComA; // 5 bytes 5334 ** sCOM_ATTR gsiComB; // 5 bytes 5335 ** BYTE gsiIdeChannels; 5336 ** BYTE gsiScsiHostChannels; 5337 ** BYTE gsiIdeHostChannels; 5338 ** BYTE gsiMaxVolumeSet; 5339 ** BYTE gsiMaxRaidSet; 5340 ** BYTE gsiEtherPort; // 1:if ether net port supported 5341 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 5342 ** BYTE gsiRes[75]; 5343 ** } sSYSTEM_INFO, *pSYSTEM_INFO; 5344 ** 5345 ** GUI_CLEAR_EVENT : Clear System Event 5346 ** byte 0,1 : length 5347 ** byte 2 : command code 0x24 5348 ** 5349 ** GUI_MUTE_BEEPER : Mute current beeper 5350 ** byte 0,1 : length 5351 ** byte 2 : command code 0x30 5352 ** 5353 ** GUI_BEEPER_SETTING : Disable beeper 5354 ** byte 0,1 : length 5355 ** byte 2 : command code 0x31 5356 ** byte 3 : 0->disable, 1->enable 5357 ** 5358 ** GUI_SET_PASSWORD : Change password 5359 ** byte 0,1 : length 5360 ** byte 2 : command code 0x32 5361 ** byte 3 : pass word length ( must <= 15 ) 5362 ** byte 4 : password (must be alpha-numerical) 5363 ** 5364 ** GUI_HOST_INTERFACE_MODE : Set host interface mode 5365 ** byte 0,1 : length 5366 ** byte 2 : command code 0x33 5367 ** byte 3 : 0->Independent, 1->cluster 5368 ** 5369 ** GUI_REBUILD_PRIORITY : Set rebuild priority 5370 ** byte 0,1 : length 5371 ** byte 2 : command code 0x34 5372 ** byte 3 : 0/1/2/3 (low->high) 5373 ** 5374 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 5375 ** byte 0,1 : length 5376 ** byte 2 : command code 0x35 5377 ** byte 3 : 0/1/2/3 (133/100/66/33) 5378 ** 5379 ** GUI_RESET_CONTROLLER : Reset Controller 5380 ** byte 0,1 : length 5381 ** byte 2 : command code 0x36 5382 ** *Response with VT100 screen (discard it) 5383 ** 5384 ** GUI_COM_PORT_SETTING : COM port setting 5385 ** byte 0,1 : length 5386 ** byte 2 : command code 0x37 5387 ** byte 3 : 0->COMA (term port), 1->COMB (debug port) 5388 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 5389 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 5390 ** byte 6 : stop bit (0:1, 1:2 stop bits) 5391 ** byte 7 : parity (0:none, 1:off, 2:even) 5392 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 5393 ** 5394 ** GUI_NO_OPERATION : No operation 5395 ** byte 0,1 : length 5396 ** byte 2 : command code 0x38 5397 ** 5398 ** GUI_DHCP_IP : Set DHCP option and local IP address 5399 ** byte 0,1 : length 5400 ** byte 2 : command code 0x39 5401 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled 5402 ** byte 4/5/6/7 : IP address 5403 ** 5404 ** GUI_CREATE_PASS_THROUGH : Create pass through disk 5405 ** byte 0,1 : length 5406 ** byte 2 : command code 0x40 5407 ** byte 3 : device # 5408 ** byte 4 : scsi channel (0/1) 5409 ** byte 5 : scsi id (0-->15) 5410 ** byte 6 : scsi lun (0-->7) 5411 ** byte 7 : tagged queue (1 : enabled) 5412 ** byte 8 : cache mode (1 : enabled) 5413 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5414 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5415 ** 5416 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 5417 ** byte 0,1 : length 5418 ** byte 2 : command code 0x41 5419 ** byte 3 : device # 5420 ** byte 4 : scsi channel (0/1) 5421 ** byte 5 : scsi id (0-->15) 5422 ** byte 6 : scsi lun (0-->7) 5423 ** byte 7 : tagged queue (1 : enabled) 5424 ** byte 8 : cache mode (1 : enabled) 5425 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5426 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5427 ** 5428 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk 5429 ** byte 0,1 : length 5430 ** byte 2 : command code 0x42 5431 ** byte 3 : device# to be deleted 5432 ** 5433 ** GUI_IDENTIFY_DEVICE : Identify Device 5434 ** byte 0,1 : length 5435 ** byte 2 : command code 0x43 5436 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 5437 ** byte 4/5/6/7 : IDE device mask to be flashed 5438 ** note .... no response data available 5439 ** 5440 ** GUI_CREATE_RAIDSET : Create Raid Set 5441 ** byte 0,1 : length 5442 ** byte 2 : command code 0x50 5443 ** byte 3/4/5/6 : device mask 5444 ** byte 7-22 : raidset name (if byte 7 == 0:use default) 5445 ** 5446 ** GUI_DELETE_RAIDSET : Delete Raid Set 5447 ** byte 0,1 : length 5448 ** byte 2 : command code 0x51 5449 ** byte 3 : raidset# 5450 ** 5451 ** GUI_EXPAND_RAIDSET : Expand Raid Set 5452 ** byte 0,1 : length 5453 ** byte 2 : command code 0x52 5454 ** byte 3 : raidset# 5455 ** byte 4/5/6/7 : device mask for expansion 5456 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5457 ** byte 11/12/13 : repeat for each volume in the raidset .... 5458 ** 5459 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5460 ** byte 0,1 : length 5461 ** byte 2 : command code 0x53 5462 ** byte 3 : raidset# 5463 ** 5464 ** GUI_CREATE_HOT_SPARE : Create hot spare disk 5465 ** byte 0,1 : length 5466 ** byte 2 : command code 0x54 5467 ** byte 3/4/5/6 : device mask for hot spare creation 5468 ** 5469 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5470 ** byte 0,1 : length 5471 ** byte 2 : command code 0x55 5472 ** byte 3/4/5/6 : device mask for hot spare deletion 5473 ** 5474 ** GUI_CREATE_VOLUME : Create volume set 5475 ** byte 0,1 : length 5476 ** byte 2 : command code 0x60 5477 ** byte 3 : raidset# 5478 ** byte 4-19 : volume set name (if byte4 == 0, use default) 5479 ** byte 20-27 : volume capacity (blocks) 5480 ** byte 28 : raid level 5481 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5482 ** byte 30 : channel 5483 ** byte 31 : ID 5484 ** byte 32 : LUN 5485 ** byte 33 : 1 enable tag 5486 ** byte 34 : 1 enable cache 5487 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5488 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5489 ** byte 36 : 1 to select quick init 5490 ** 5491 ** GUI_MODIFY_VOLUME : Modify volume Set 5492 ** byte 0,1 : length 5493 ** byte 2 : command code 0x61 5494 ** byte 3 : volumeset# 5495 ** byte 4-19 : new volume set name (if byte4 == 0, not change) 5496 ** byte 20-27 : new volume capacity (reserved) 5497 ** byte 28 : new raid level 5498 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5499 ** byte 30 : new channel 5500 ** byte 31 : new ID 5501 ** byte 32 : new LUN 5502 ** byte 33 : 1 enable tag 5503 ** byte 34 : 1 enable cache 5504 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5505 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5506 ** 5507 ** GUI_DELETE_VOLUME : Delete volume set 5508 ** byte 0,1 : length 5509 ** byte 2 : command code 0x62 5510 ** byte 3 : volumeset# 5511 ** 5512 ** GUI_START_CHECK_VOLUME : Start volume consistency check 5513 ** byte 0,1 : length 5514 ** byte 2 : command code 0x63 5515 ** byte 3 : volumeset# 5516 ** 5517 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5518 ** byte 0,1 : length 5519 ** byte 2 : command code 0x64 5520 ** --------------------------------------------------------------------- 5521 ** 4. Returned data 5522 ** --------------------------------------------------------------------- 5523 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5524 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5525 ** (C) status or data : 5526 ** <1> If length == 1 ==> 1 byte status code 5527 ** #define GUI_OK 0x41 5528 ** #define GUI_RAIDSET_NOT_NORMAL 0x42 5529 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5530 ** #define GUI_NO_RAIDSET 0x44 5531 ** #define GUI_NO_VOLUMESET 0x45 5532 ** #define GUI_NO_PHYSICAL_DRIVE 0x46 5533 ** #define GUI_PARAMETER_ERROR 0x47 5534 ** #define GUI_UNSUPPORTED_COMMAND 0x48 5535 ** #define GUI_DISK_CONFIG_CHANGED 0x49 5536 ** #define GUI_INVALID_PASSWORD 0x4a 5537 ** #define GUI_NO_DISK_SPACE 0x4b 5538 ** #define GUI_CHECKSUM_ERROR 0x4c 5539 ** #define GUI_PASSWORD_REQUIRED 0x4d 5540 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5541 ** (E) Checksum : checksum of length and status or data byte 5542 ************************************************************************** 5543 */ 5544