1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** SPDX-License-Identifier: BSD-3-Clause 13 ** 14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 15 ** 16 ** Redistribution and use in source and binary forms, with or without 17 ** modification, are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice, this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice, this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ******************************************************************************** 38 ** History 39 ** 40 ** REV# DATE NAME DESCRIPTION 41 ** 1.00.00.00 03/31/2004 Erich Chen First release 42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 43 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 44 ** clean unused function 45 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 46 ** firmware version check 47 ** and firmware update notify for hardware bug fix 48 ** handling if none zero high part physical address 49 ** of srb resource 50 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 51 ** add iop message xfer 52 ** with scsi pass-through command 53 ** add new device id of sas raid adapters 54 ** code fit for SPARC64 & PPC 55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 56 ** and cause g_vfs_done() read write error 57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 59 ** bus_dmamem_alloc() with BUS_DMA_ZERO 60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 62 ** prevent cam_periph_error removing all LUN devices of one Target id 63 ** for any one LUN device failed 64 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 65 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 66 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 67 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 68 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 69 ** 02/14/2011 Ching Huang Modified pktRequestCount 70 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 71 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 72 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 73 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 74 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 75 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 76 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 77 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 78 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 79 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs 80 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883 81 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203 82 ** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884 83 ** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource 84 ** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller 85 ** 1.50.00.01 02/26/2021 Ching Huang Fixed no action of hot plugging device on type_F adapter 86 ** 1.50.00.02 04/16/2021 Ching Huang Fixed scsi command timeout on ARC-1886 when 87 ** scatter-gather count large than some number 88 ****************************************************************************************** 89 */ 90 91 #include <sys/cdefs.h> 92 __FBSDID("$FreeBSD$"); 93 94 #if 0 95 #define ARCMSR_DEBUG1 1 96 #endif 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/bus.h> 102 #include <sys/queue.h> 103 #include <sys/stat.h> 104 #include <sys/devicestat.h> 105 #include <sys/kthread.h> 106 #include <sys/module.h> 107 #include <sys/proc.h> 108 #include <sys/lock.h> 109 #include <sys/sysctl.h> 110 #include <sys/poll.h> 111 #include <sys/ioccom.h> 112 #include <vm/vm.h> 113 #include <vm/vm_param.h> 114 #include <vm/pmap.h> 115 116 #include <isa/rtc.h> 117 118 #include <machine/bus.h> 119 #include <machine/resource.h> 120 #include <machine/atomic.h> 121 #include <sys/conf.h> 122 #include <sys/rman.h> 123 124 #include <cam/cam.h> 125 #include <cam/cam_ccb.h> 126 #include <cam/cam_sim.h> 127 #include <cam/cam_periph.h> 128 #include <cam/cam_xpt_periph.h> 129 #include <cam/cam_xpt_sim.h> 130 #include <cam/cam_debug.h> 131 #include <cam/scsi/scsi_all.h> 132 #include <cam/scsi/scsi_message.h> 133 /* 134 ************************************************************************** 135 ************************************************************************** 136 */ 137 #include <sys/selinfo.h> 138 #include <sys/mutex.h> 139 #include <sys/endian.h> 140 #include <dev/pci/pcivar.h> 141 #include <dev/pci/pcireg.h> 142 143 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 144 145 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.02 2021-04-16" 146 #include <dev/arcmsr/arcmsr.h> 147 /* 148 ************************************************************************** 149 ************************************************************************** 150 */ 151 static void arcmsr_free_srb(struct CommandControlBlock *srb); 152 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 153 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 154 static int arcmsr_probe(device_t dev); 155 static int arcmsr_attach(device_t dev); 156 static int arcmsr_detach(device_t dev); 157 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 158 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 159 static int arcmsr_shutdown(device_t dev); 160 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 161 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 162 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 163 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 164 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 165 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 166 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 167 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 168 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 169 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 170 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 171 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 172 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 173 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 174 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 175 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 176 static int arcmsr_resume(device_t dev); 177 static int arcmsr_suspend(device_t dev); 178 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 179 static void arcmsr_polling_devmap(void *arg); 180 static void arcmsr_srb_timeout(void *arg); 181 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 182 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb); 183 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb); 184 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb); 185 #ifdef ARCMSR_DEBUG1 186 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 187 #endif 188 /* 189 ************************************************************************** 190 ************************************************************************** 191 */ 192 static void UDELAY(u_int32_t us) { DELAY(us); } 193 /* 194 ************************************************************************** 195 ************************************************************************** 196 */ 197 static bus_dmamap_callback_t arcmsr_map_free_srb; 198 static bus_dmamap_callback_t arcmsr_execute_srb; 199 /* 200 ************************************************************************** 201 ************************************************************************** 202 */ 203 static d_open_t arcmsr_open; 204 static d_close_t arcmsr_close; 205 static d_ioctl_t arcmsr_ioctl; 206 207 static device_method_t arcmsr_methods[]={ 208 DEVMETHOD(device_probe, arcmsr_probe), 209 DEVMETHOD(device_attach, arcmsr_attach), 210 DEVMETHOD(device_detach, arcmsr_detach), 211 DEVMETHOD(device_shutdown, arcmsr_shutdown), 212 DEVMETHOD(device_suspend, arcmsr_suspend), 213 DEVMETHOD(device_resume, arcmsr_resume), 214 DEVMETHOD_END 215 }; 216 217 static driver_t arcmsr_driver={ 218 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 219 }; 220 221 static devclass_t arcmsr_devclass; 222 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 223 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 224 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 225 #ifndef BUS_DMA_COHERENT 226 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 227 #endif 228 static struct cdevsw arcmsr_cdevsw={ 229 .d_version = D_VERSION, 230 .d_open = arcmsr_open, /* open */ 231 .d_close = arcmsr_close, /* close */ 232 .d_ioctl = arcmsr_ioctl, /* ioctl */ 233 .d_name = "arcmsr", /* name */ 234 }; 235 /* 236 ************************************************************************** 237 ************************************************************************** 238 */ 239 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 240 { 241 int unit = dev2unit(dev); 242 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 243 244 if (acb == NULL) { 245 return ENXIO; 246 } 247 return (0); 248 } 249 /* 250 ************************************************************************** 251 ************************************************************************** 252 */ 253 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 254 { 255 int unit = dev2unit(dev); 256 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 257 258 if (acb == NULL) { 259 return ENXIO; 260 } 261 return 0; 262 } 263 /* 264 ************************************************************************** 265 ************************************************************************** 266 */ 267 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 268 { 269 int unit = dev2unit(dev); 270 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 271 272 if (acb == NULL) { 273 return ENXIO; 274 } 275 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 276 } 277 /* 278 ********************************************************************** 279 ********************************************************************** 280 */ 281 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 282 { 283 u_int32_t intmask_org = 0; 284 285 switch (acb->adapter_type) { 286 case ACB_ADAPTER_TYPE_A: { 287 /* disable all outbound interrupt */ 288 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 289 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 290 } 291 break; 292 case ACB_ADAPTER_TYPE_B: { 293 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 294 /* disable all outbound interrupt */ 295 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask) 296 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 297 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */ 298 } 299 break; 300 case ACB_ADAPTER_TYPE_C: { 301 /* disable all outbound interrupt */ 302 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 303 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 304 } 305 break; 306 case ACB_ADAPTER_TYPE_D: { 307 /* disable all outbound interrupt */ 308 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */ 309 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 310 } 311 break; 312 case ACB_ADAPTER_TYPE_E: 313 case ACB_ADAPTER_TYPE_F: { 314 /* disable all outbound interrupt */ 315 intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 316 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE); 317 } 318 break; 319 } 320 return (intmask_org); 321 } 322 /* 323 ********************************************************************** 324 ********************************************************************** 325 */ 326 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 327 { 328 u_int32_t mask; 329 330 switch (acb->adapter_type) { 331 case ACB_ADAPTER_TYPE_A: { 332 /* enable outbound Post Queue, outbound doorbell Interrupt */ 333 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 334 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 335 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 336 } 337 break; 338 case ACB_ADAPTER_TYPE_B: { 339 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 340 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 341 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 342 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 343 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 344 } 345 break; 346 case ACB_ADAPTER_TYPE_C: { 347 /* enable outbound Post Queue, outbound doorbell Interrupt */ 348 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 349 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 350 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 351 } 352 break; 353 case ACB_ADAPTER_TYPE_D: { 354 /* enable outbound Post Queue, outbound doorbell Interrupt */ 355 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 356 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 357 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 358 acb->outbound_int_enable = mask; 359 } 360 break; 361 case ACB_ADAPTER_TYPE_E: 362 case ACB_ADAPTER_TYPE_F: { 363 /* enable outbound Post Queue, outbound doorbell Interrupt */ 364 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 365 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask); 366 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 367 } 368 break; 369 } 370 } 371 /* 372 ********************************************************************** 373 ********************************************************************** 374 */ 375 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 376 { 377 u_int32_t Index; 378 u_int8_t Retries = 0x00; 379 380 do { 381 for(Index=0; Index < 100; Index++) { 382 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 383 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 384 return TRUE; 385 } 386 UDELAY(10000); 387 }/*max 1 seconds*/ 388 }while(Retries++ < 20);/*max 20 sec*/ 389 return (FALSE); 390 } 391 /* 392 ********************************************************************** 393 ********************************************************************** 394 */ 395 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 396 { 397 u_int32_t Index; 398 u_int8_t Retries = 0x00; 399 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 400 401 do { 402 for(Index=0; Index < 100; Index++) { 403 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 404 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 405 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 406 return TRUE; 407 } 408 UDELAY(10000); 409 }/*max 1 seconds*/ 410 }while(Retries++ < 20);/*max 20 sec*/ 411 return (FALSE); 412 } 413 /* 414 ********************************************************************** 415 ********************************************************************** 416 */ 417 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 418 { 419 u_int32_t Index; 420 u_int8_t Retries = 0x00; 421 422 do { 423 for(Index=0; Index < 100; Index++) { 424 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 425 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 426 return TRUE; 427 } 428 UDELAY(10000); 429 }/*max 1 seconds*/ 430 }while(Retries++ < 20);/*max 20 sec*/ 431 return (FALSE); 432 } 433 /* 434 ********************************************************************** 435 ********************************************************************** 436 */ 437 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 438 { 439 u_int32_t Index; 440 u_int8_t Retries = 0x00; 441 442 do { 443 for(Index=0; Index < 100; Index++) { 444 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 445 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 446 return TRUE; 447 } 448 UDELAY(10000); 449 }/*max 1 seconds*/ 450 }while(Retries++ < 20);/*max 20 sec*/ 451 return (FALSE); 452 } 453 /* 454 ********************************************************************** 455 ********************************************************************** 456 */ 457 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb) 458 { 459 u_int32_t Index, read_doorbell; 460 u_int8_t Retries = 0x00; 461 462 do { 463 for(Index=0; Index < 100; Index++) { 464 read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 465 if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 466 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/ 467 acb->in_doorbell = read_doorbell; 468 return TRUE; 469 } 470 UDELAY(10000); 471 }/*max 1 seconds*/ 472 }while(Retries++ < 20);/*max 20 sec*/ 473 return (FALSE); 474 } 475 /* 476 ************************************************************************ 477 ************************************************************************ 478 */ 479 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 480 { 481 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 482 483 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 484 do { 485 if(arcmsr_hba_wait_msgint_ready(acb)) { 486 break; 487 } else { 488 retry_count--; 489 } 490 }while(retry_count != 0); 491 } 492 /* 493 ************************************************************************ 494 ************************************************************************ 495 */ 496 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 497 { 498 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 499 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 500 501 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 502 do { 503 if(arcmsr_hbb_wait_msgint_ready(acb)) { 504 break; 505 } else { 506 retry_count--; 507 } 508 }while(retry_count != 0); 509 } 510 /* 511 ************************************************************************ 512 ************************************************************************ 513 */ 514 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 515 { 516 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 517 518 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 519 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 520 do { 521 if(arcmsr_hbc_wait_msgint_ready(acb)) { 522 break; 523 } else { 524 retry_count--; 525 } 526 }while(retry_count != 0); 527 } 528 /* 529 ************************************************************************ 530 ************************************************************************ 531 */ 532 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 533 { 534 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 535 536 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 537 do { 538 if(arcmsr_hbd_wait_msgint_ready(acb)) { 539 break; 540 } else { 541 retry_count--; 542 } 543 }while(retry_count != 0); 544 } 545 /* 546 ************************************************************************ 547 ************************************************************************ 548 */ 549 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb) 550 { 551 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 552 553 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 554 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 555 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 556 do { 557 if(arcmsr_hbe_wait_msgint_ready(acb)) { 558 break; 559 } else { 560 retry_count--; 561 } 562 }while(retry_count != 0); 563 } 564 /* 565 ************************************************************************ 566 ************************************************************************ 567 */ 568 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 569 { 570 switch (acb->adapter_type) { 571 case ACB_ADAPTER_TYPE_A: { 572 arcmsr_flush_hba_cache(acb); 573 } 574 break; 575 case ACB_ADAPTER_TYPE_B: { 576 arcmsr_flush_hbb_cache(acb); 577 } 578 break; 579 case ACB_ADAPTER_TYPE_C: { 580 arcmsr_flush_hbc_cache(acb); 581 } 582 break; 583 case ACB_ADAPTER_TYPE_D: { 584 arcmsr_flush_hbd_cache(acb); 585 } 586 break; 587 case ACB_ADAPTER_TYPE_E: 588 case ACB_ADAPTER_TYPE_F: { 589 arcmsr_flush_hbe_cache(acb); 590 } 591 break; 592 } 593 } 594 /* 595 ******************************************************************************* 596 ******************************************************************************* 597 */ 598 static int arcmsr_suspend(device_t dev) 599 { 600 struct AdapterControlBlock *acb = device_get_softc(dev); 601 602 /* flush controller */ 603 arcmsr_iop_parking(acb); 604 /* disable all outbound interrupt */ 605 arcmsr_disable_allintr(acb); 606 return(0); 607 } 608 /* 609 ******************************************************************************* 610 ******************************************************************************* 611 */ 612 static int arcmsr_resume(device_t dev) 613 { 614 struct AdapterControlBlock *acb = device_get_softc(dev); 615 616 arcmsr_iop_init(acb); 617 return(0); 618 } 619 /* 620 ********************************************************************************* 621 ********************************************************************************* 622 */ 623 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 624 { 625 u_int8_t target_id, target_lun; 626 627 switch (code) { 628 case AC_LOST_DEVICE: 629 target_id = xpt_path_target_id(path); 630 target_lun = xpt_path_lun_id(path); 631 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 632 break; 633 } 634 break; 635 default: 636 break; 637 } 638 } 639 /* 640 ********************************************************************** 641 ********************************************************************** 642 */ 643 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 644 { 645 union ccb *pccb = srb->pccb; 646 647 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 648 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 649 if(pccb->csio.sense_len) { 650 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 651 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 652 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 653 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 654 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 655 } 656 } 657 /* 658 ********************************************************************* 659 ********************************************************************* 660 */ 661 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 662 { 663 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 664 if(!arcmsr_hba_wait_msgint_ready(acb)) { 665 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 666 } 667 } 668 /* 669 ********************************************************************* 670 ********************************************************************* 671 */ 672 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 673 { 674 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 675 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 676 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 677 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 678 } 679 } 680 /* 681 ********************************************************************* 682 ********************************************************************* 683 */ 684 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 685 { 686 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 687 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 688 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 689 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 690 } 691 } 692 /* 693 ********************************************************************* 694 ********************************************************************* 695 */ 696 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 697 { 698 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 699 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 700 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 701 } 702 } 703 /* 704 ********************************************************************* 705 ********************************************************************* 706 */ 707 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb) 708 { 709 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 710 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 711 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 712 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 713 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 714 } 715 } 716 /* 717 ********************************************************************* 718 ********************************************************************* 719 */ 720 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 721 { 722 switch (acb->adapter_type) { 723 case ACB_ADAPTER_TYPE_A: { 724 arcmsr_abort_hba_allcmd(acb); 725 } 726 break; 727 case ACB_ADAPTER_TYPE_B: { 728 arcmsr_abort_hbb_allcmd(acb); 729 } 730 break; 731 case ACB_ADAPTER_TYPE_C: { 732 arcmsr_abort_hbc_allcmd(acb); 733 } 734 break; 735 case ACB_ADAPTER_TYPE_D: { 736 arcmsr_abort_hbd_allcmd(acb); 737 } 738 break; 739 case ACB_ADAPTER_TYPE_E: 740 case ACB_ADAPTER_TYPE_F: { 741 arcmsr_abort_hbe_allcmd(acb); 742 } 743 break; 744 } 745 } 746 /* 747 ********************************************************************** 748 ********************************************************************** 749 */ 750 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 751 { 752 struct AdapterControlBlock *acb = srb->acb; 753 union ccb *pccb = srb->pccb; 754 755 if(srb->srb_flags & SRB_FLAG_TIMER_START) 756 callout_stop(&srb->ccb_callout); 757 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 758 bus_dmasync_op_t op; 759 760 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 761 op = BUS_DMASYNC_POSTREAD; 762 } else { 763 op = BUS_DMASYNC_POSTWRITE; 764 } 765 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 766 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 767 } 768 if(stand_flag == 1) { 769 atomic_subtract_int(&acb->srboutstandingcount, 1); 770 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 771 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 772 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 773 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 774 } 775 } 776 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 777 arcmsr_free_srb(srb); 778 acb->pktReturnCount++; 779 xpt_done(pccb); 780 } 781 /* 782 ************************************************************************** 783 ************************************************************************** 784 */ 785 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 786 { 787 int target, lun; 788 789 target = srb->pccb->ccb_h.target_id; 790 lun = srb->pccb->ccb_h.target_lun; 791 if(error == FALSE) { 792 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 793 acb->devstate[target][lun] = ARECA_RAID_GOOD; 794 } 795 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 796 arcmsr_srb_complete(srb, 1); 797 } else { 798 switch(srb->arcmsr_cdb.DeviceStatus) { 799 case ARCMSR_DEV_SELECT_TIMEOUT: { 800 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 801 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 802 } 803 acb->devstate[target][lun] = ARECA_RAID_GONE; 804 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 805 arcmsr_srb_complete(srb, 1); 806 } 807 break; 808 case ARCMSR_DEV_ABORTED: 809 case ARCMSR_DEV_INIT_FAIL: { 810 acb->devstate[target][lun] = ARECA_RAID_GONE; 811 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 812 arcmsr_srb_complete(srb, 1); 813 } 814 break; 815 case SCSISTAT_CHECK_CONDITION: { 816 acb->devstate[target][lun] = ARECA_RAID_GOOD; 817 arcmsr_report_sense_info(srb); 818 arcmsr_srb_complete(srb, 1); 819 } 820 break; 821 default: 822 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 823 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 824 acb->devstate[target][lun] = ARECA_RAID_GONE; 825 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 826 /*unknown error or crc error just for retry*/ 827 arcmsr_srb_complete(srb, 1); 828 break; 829 } 830 } 831 } 832 /* 833 ************************************************************************** 834 ************************************************************************** 835 */ 836 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 837 { 838 struct CommandControlBlock *srb; 839 840 /* check if command done with no error*/ 841 switch (acb->adapter_type) { 842 case ACB_ADAPTER_TYPE_A: 843 case ACB_ADAPTER_TYPE_B: 844 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 845 break; 846 case ACB_ADAPTER_TYPE_C: 847 case ACB_ADAPTER_TYPE_D: 848 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 849 break; 850 case ACB_ADAPTER_TYPE_E: 851 case ACB_ADAPTER_TYPE_F: 852 srb = acb->psrb_pool[flag_srb]; 853 break; 854 default: 855 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 856 break; 857 } 858 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 859 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 860 arcmsr_free_srb(srb); 861 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 862 return; 863 } 864 printf("arcmsr%d: return srb has been completed\n" 865 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 866 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 867 return; 868 } 869 arcmsr_report_srb_state(acb, srb, error); 870 } 871 /* 872 ************************************************************************** 873 ************************************************************************** 874 */ 875 static void arcmsr_srb_timeout(void *arg) 876 { 877 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 878 struct AdapterControlBlock *acb; 879 int target, lun; 880 u_int8_t cmd; 881 882 target = srb->pccb->ccb_h.target_id; 883 lun = srb->pccb->ccb_h.target_lun; 884 acb = srb->acb; 885 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 886 if(srb->srb_state == ARCMSR_SRB_START) 887 { 888 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0]; 889 srb->srb_state = ARCMSR_SRB_TIMEOUT; 890 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 891 arcmsr_srb_complete(srb, 1); 892 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 893 acb->pci_unit, target, lun, cmd, srb); 894 } 895 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 896 #ifdef ARCMSR_DEBUG1 897 arcmsr_dump_data(acb); 898 #endif 899 } 900 901 /* 902 ********************************************************************** 903 ********************************************************************** 904 */ 905 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 906 { 907 int i=0; 908 u_int32_t flag_srb; 909 u_int16_t error; 910 911 switch (acb->adapter_type) { 912 case ACB_ADAPTER_TYPE_A: { 913 u_int32_t outbound_intstatus; 914 915 /*clear and abort all outbound posted Q*/ 916 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 917 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 918 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 919 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 920 arcmsr_drain_donequeue(acb, flag_srb, error); 921 } 922 } 923 break; 924 case ACB_ADAPTER_TYPE_B: { 925 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 926 927 /*clear all outbound posted Q*/ 928 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 929 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 930 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 931 phbbmu->done_qbuffer[i] = 0; 932 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 933 arcmsr_drain_donequeue(acb, flag_srb, error); 934 } 935 phbbmu->post_qbuffer[i] = 0; 936 }/*drain reply FIFO*/ 937 phbbmu->doneq_index = 0; 938 phbbmu->postq_index = 0; 939 } 940 break; 941 case ACB_ADAPTER_TYPE_C: { 942 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 943 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 944 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 945 arcmsr_drain_donequeue(acb, flag_srb, error); 946 } 947 } 948 break; 949 case ACB_ADAPTER_TYPE_D: 950 arcmsr_hbd_postqueue_isr(acb); 951 break; 952 case ACB_ADAPTER_TYPE_E: 953 arcmsr_hbe_postqueue_isr(acb); 954 break; 955 case ACB_ADAPTER_TYPE_F: 956 arcmsr_hbf_postqueue_isr(acb); 957 break; 958 } 959 } 960 /* 961 **************************************************************************** 962 **************************************************************************** 963 */ 964 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 965 { 966 struct CommandControlBlock *srb; 967 u_int32_t intmask_org; 968 u_int32_t i=0; 969 970 if(acb->srboutstandingcount>0) { 971 /* disable all outbound interrupt */ 972 intmask_org = arcmsr_disable_allintr(acb); 973 /*clear and abort all outbound posted Q*/ 974 arcmsr_done4abort_postqueue(acb); 975 /* talk to iop 331 outstanding command aborted*/ 976 arcmsr_abort_allcmd(acb); 977 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 978 srb = acb->psrb_pool[i]; 979 if(srb->srb_state == ARCMSR_SRB_START) { 980 srb->srb_state = ARCMSR_SRB_ABORTED; 981 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 982 arcmsr_srb_complete(srb, 1); 983 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n" 984 , acb->pci_unit, srb->pccb->ccb_h.target_id 985 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 986 } 987 } 988 /* enable all outbound interrupt */ 989 arcmsr_enable_allintr(acb, intmask_org); 990 } 991 acb->srboutstandingcount = 0; 992 acb->workingsrb_doneindex = 0; 993 acb->workingsrb_startindex = 0; 994 acb->pktRequestCount = 0; 995 acb->pktReturnCount = 0; 996 } 997 /* 998 ********************************************************************** 999 ********************************************************************** 1000 */ 1001 static void arcmsr_build_srb(struct CommandControlBlock *srb, 1002 bus_dma_segment_t *dm_segs, u_int32_t nseg) 1003 { 1004 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 1005 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 1006 u_int32_t address_lo, address_hi; 1007 union ccb *pccb = srb->pccb; 1008 struct ccb_scsiio *pcsio = &pccb->csio; 1009 u_int32_t arccdbsize = 0x30; 1010 1011 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 1012 arcmsr_cdb->Bus = 0; 1013 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 1014 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 1015 arcmsr_cdb->Function = 1; 1016 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 1017 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len); 1018 if(nseg != 0) { 1019 struct AdapterControlBlock *acb = srb->acb; 1020 bus_dmasync_op_t op; 1021 u_int32_t length, i, cdb_sgcount = 0; 1022 1023 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1024 op = BUS_DMASYNC_PREREAD; 1025 } else { 1026 op = BUS_DMASYNC_PREWRITE; 1027 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1028 srb->srb_flags |= SRB_FLAG_WRITE; 1029 } 1030 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1031 for(i=0; i < nseg; i++) { 1032 /* Get the physical address of the current data pointer */ 1033 length = arcmsr_htole32(dm_segs[i].ds_len); 1034 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1035 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1036 if(address_hi == 0) { 1037 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1038 pdma_sg->address = address_lo; 1039 pdma_sg->length = length; 1040 psge += sizeof(struct SG32ENTRY); 1041 arccdbsize += sizeof(struct SG32ENTRY); 1042 } else { 1043 u_int32_t sg64s_size = 0, tmplength = length; 1044 1045 while(1) { 1046 u_int64_t span4G, length0; 1047 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1048 1049 span4G = (u_int64_t)address_lo + tmplength; 1050 pdma_sg->addresshigh = address_hi; 1051 pdma_sg->address = address_lo; 1052 if(span4G > 0x100000000) { 1053 /*see if cross 4G boundary*/ 1054 length0 = 0x100000000-address_lo; 1055 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1056 address_hi = address_hi+1; 1057 address_lo = 0; 1058 tmplength = tmplength - (u_int32_t)length0; 1059 sg64s_size += sizeof(struct SG64ENTRY); 1060 psge += sizeof(struct SG64ENTRY); 1061 cdb_sgcount++; 1062 } else { 1063 pdma_sg->length = tmplength | IS_SG64_ADDR; 1064 sg64s_size += sizeof(struct SG64ENTRY); 1065 psge += sizeof(struct SG64ENTRY); 1066 break; 1067 } 1068 } 1069 arccdbsize += sg64s_size; 1070 } 1071 cdb_sgcount++; 1072 } 1073 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1074 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1075 if( arccdbsize > 256) { 1076 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1077 } 1078 } else { 1079 arcmsr_cdb->DataLength = 0; 1080 } 1081 srb->arc_cdb_size = arccdbsize; 1082 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1083 } 1084 /* 1085 ************************************************************************** 1086 ************************************************************************** 1087 */ 1088 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1089 { 1090 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1091 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1092 1093 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1094 atomic_add_int(&acb->srboutstandingcount, 1); 1095 srb->srb_state = ARCMSR_SRB_START; 1096 1097 switch (acb->adapter_type) { 1098 case ACB_ADAPTER_TYPE_A: { 1099 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1100 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1101 } else { 1102 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1103 } 1104 } 1105 break; 1106 case ACB_ADAPTER_TYPE_B: { 1107 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1108 int ending_index, index; 1109 1110 index = phbbmu->postq_index; 1111 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1112 phbbmu->post_qbuffer[ending_index] = 0; 1113 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1114 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1115 } else { 1116 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1117 } 1118 index++; 1119 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1120 phbbmu->postq_index = index; 1121 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1122 } 1123 break; 1124 case ACB_ADAPTER_TYPE_C: { 1125 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1126 1127 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1128 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1129 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1130 if(cdb_phyaddr_hi32) 1131 { 1132 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1133 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1134 } 1135 else 1136 { 1137 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1138 } 1139 } 1140 break; 1141 case ACB_ADAPTER_TYPE_D: { 1142 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1143 u_int16_t index_stripped; 1144 u_int16_t postq_index; 1145 struct InBound_SRB *pinbound_srb; 1146 1147 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1148 postq_index = phbdmu->postq_index; 1149 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1150 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1151 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1152 pinbound_srb->length = srb->arc_cdb_size >> 2; 1153 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1154 if (postq_index & 0x4000) { 1155 index_stripped = postq_index & 0xFF; 1156 index_stripped += 1; 1157 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1158 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1159 } else { 1160 index_stripped = postq_index; 1161 index_stripped += 1; 1162 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1163 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1164 } 1165 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1166 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1167 } 1168 break; 1169 case ACB_ADAPTER_TYPE_E: { 1170 u_int32_t ccb_post_stamp, arc_cdb_size; 1171 1172 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1173 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6)); 1174 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0); 1175 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1176 } 1177 break; 1178 case ACB_ADAPTER_TYPE_F: { 1179 u_int32_t ccb_post_stamp, arc_cdb_size; 1180 1181 if (srb->arc_cdb_size <= 0x300) 1182 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1; 1183 else { 1184 arc_cdb_size = ((srb->arc_cdb_size + 0xff) >> 8) + 2; 1185 if (arc_cdb_size > 0xF) 1186 arc_cdb_size = 0xF; 1187 arc_cdb_size = (arc_cdb_size << 1) | 1; 1188 } 1189 ccb_post_stamp = (srb->smid | arc_cdb_size); 1190 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0); 1191 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1192 } 1193 break; 1194 } 1195 } 1196 /* 1197 ************************************************************************ 1198 ************************************************************************ 1199 */ 1200 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1201 { 1202 struct QBUFFER *qbuffer=NULL; 1203 1204 switch (acb->adapter_type) { 1205 case ACB_ADAPTER_TYPE_A: { 1206 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1207 1208 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1209 } 1210 break; 1211 case ACB_ADAPTER_TYPE_B: { 1212 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1213 1214 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1215 } 1216 break; 1217 case ACB_ADAPTER_TYPE_C: { 1218 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1219 1220 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1221 } 1222 break; 1223 case ACB_ADAPTER_TYPE_D: { 1224 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1225 1226 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1227 } 1228 break; 1229 case ACB_ADAPTER_TYPE_E: { 1230 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1231 1232 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1233 } 1234 break; 1235 case ACB_ADAPTER_TYPE_F: 1236 qbuffer = (struct QBUFFER *)acb->message_rbuffer; 1237 break; 1238 } 1239 return(qbuffer); 1240 } 1241 /* 1242 ************************************************************************ 1243 ************************************************************************ 1244 */ 1245 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1246 { 1247 struct QBUFFER *qbuffer = NULL; 1248 1249 switch (acb->adapter_type) { 1250 case ACB_ADAPTER_TYPE_A: { 1251 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1252 1253 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1254 } 1255 break; 1256 case ACB_ADAPTER_TYPE_B: { 1257 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1258 1259 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1260 } 1261 break; 1262 case ACB_ADAPTER_TYPE_C: { 1263 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1264 1265 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1266 } 1267 break; 1268 case ACB_ADAPTER_TYPE_D: { 1269 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1270 1271 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1272 } 1273 break; 1274 case ACB_ADAPTER_TYPE_E: { 1275 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1276 1277 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1278 } 1279 break; 1280 case ACB_ADAPTER_TYPE_F: 1281 qbuffer = (struct QBUFFER *)acb->message_wbuffer; 1282 break; 1283 } 1284 return(qbuffer); 1285 } 1286 /* 1287 ************************************************************************** 1288 ************************************************************************** 1289 */ 1290 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1291 { 1292 switch (acb->adapter_type) { 1293 case ACB_ADAPTER_TYPE_A: { 1294 /* let IOP know data has been read */ 1295 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1296 } 1297 break; 1298 case ACB_ADAPTER_TYPE_B: { 1299 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1300 /* let IOP know data has been read */ 1301 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1302 } 1303 break; 1304 case ACB_ADAPTER_TYPE_C: { 1305 /* let IOP know data has been read */ 1306 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1307 } 1308 break; 1309 case ACB_ADAPTER_TYPE_D: { 1310 /* let IOP know data has been read */ 1311 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1312 } 1313 break; 1314 case ACB_ADAPTER_TYPE_E: 1315 case ACB_ADAPTER_TYPE_F: { 1316 /* let IOP know data has been read */ 1317 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1318 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1319 } 1320 break; 1321 } 1322 } 1323 /* 1324 ************************************************************************** 1325 ************************************************************************** 1326 */ 1327 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1328 { 1329 switch (acb->adapter_type) { 1330 case ACB_ADAPTER_TYPE_A: { 1331 /* 1332 ** push inbound doorbell tell iop, driver data write ok 1333 ** and wait reply on next hwinterrupt for next Qbuffer post 1334 */ 1335 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1336 } 1337 break; 1338 case ACB_ADAPTER_TYPE_B: { 1339 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1340 /* 1341 ** push inbound doorbell tell iop, driver data write ok 1342 ** and wait reply on next hwinterrupt for next Qbuffer post 1343 */ 1344 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1345 } 1346 break; 1347 case ACB_ADAPTER_TYPE_C: { 1348 /* 1349 ** push inbound doorbell tell iop, driver data write ok 1350 ** and wait reply on next hwinterrupt for next Qbuffer post 1351 */ 1352 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1353 } 1354 break; 1355 case ACB_ADAPTER_TYPE_D: { 1356 /* 1357 ** push inbound doorbell tell iop, driver data write ok 1358 ** and wait reply on next hwinterrupt for next Qbuffer post 1359 */ 1360 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1361 } 1362 break; 1363 case ACB_ADAPTER_TYPE_E: 1364 case ACB_ADAPTER_TYPE_F: { 1365 /* 1366 ** push inbound doorbell tell iop, driver data write ok 1367 ** and wait reply on next hwinterrupt for next Qbuffer post 1368 */ 1369 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 1370 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1371 } 1372 break; 1373 } 1374 } 1375 /* 1376 ************************************************************************ 1377 ************************************************************************ 1378 */ 1379 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1380 { 1381 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1382 CHIP_REG_WRITE32(HBA_MessageUnit, 1383 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1384 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1385 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1386 , acb->pci_unit); 1387 } 1388 } 1389 /* 1390 ************************************************************************ 1391 ************************************************************************ 1392 */ 1393 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1394 { 1395 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1396 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1397 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1398 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1399 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1400 , acb->pci_unit); 1401 } 1402 } 1403 /* 1404 ************************************************************************ 1405 ************************************************************************ 1406 */ 1407 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1408 { 1409 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1410 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1411 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1412 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1413 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1414 } 1415 } 1416 /* 1417 ************************************************************************ 1418 ************************************************************************ 1419 */ 1420 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1421 { 1422 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1423 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1424 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1425 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1426 } 1427 } 1428 /* 1429 ************************************************************************ 1430 ************************************************************************ 1431 */ 1432 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb) 1433 { 1434 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1435 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1436 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1437 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1438 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 1439 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1440 } 1441 } 1442 /* 1443 ************************************************************************ 1444 ************************************************************************ 1445 */ 1446 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1447 { 1448 switch (acb->adapter_type) { 1449 case ACB_ADAPTER_TYPE_A: { 1450 arcmsr_stop_hba_bgrb(acb); 1451 } 1452 break; 1453 case ACB_ADAPTER_TYPE_B: { 1454 arcmsr_stop_hbb_bgrb(acb); 1455 } 1456 break; 1457 case ACB_ADAPTER_TYPE_C: { 1458 arcmsr_stop_hbc_bgrb(acb); 1459 } 1460 break; 1461 case ACB_ADAPTER_TYPE_D: { 1462 arcmsr_stop_hbd_bgrb(acb); 1463 } 1464 break; 1465 case ACB_ADAPTER_TYPE_E: 1466 case ACB_ADAPTER_TYPE_F: { 1467 arcmsr_stop_hbe_bgrb(acb); 1468 } 1469 break; 1470 } 1471 } 1472 /* 1473 ************************************************************************ 1474 ************************************************************************ 1475 */ 1476 static void arcmsr_poll(struct cam_sim *psim) 1477 { 1478 struct AdapterControlBlock *acb; 1479 int mutex; 1480 1481 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1482 mutex = mtx_owned(&acb->isr_lock); 1483 if( mutex == 0 ) 1484 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1485 arcmsr_interrupt(acb); 1486 if( mutex == 0 ) 1487 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1488 } 1489 /* 1490 ************************************************************************** 1491 ************************************************************************** 1492 */ 1493 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1494 struct QBUFFER *prbuffer) { 1495 u_int8_t *pQbuffer; 1496 u_int8_t *buf1 = NULL; 1497 u_int32_t *iop_data, *buf2 = NULL; 1498 u_int32_t iop_len, data_len; 1499 1500 iop_data = (u_int32_t *)prbuffer->data; 1501 iop_len = (u_int32_t)prbuffer->data_len; 1502 if ( iop_len > 0 ) 1503 { 1504 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1505 buf2 = (u_int32_t *)buf1; 1506 if( buf1 == NULL) 1507 return (0); 1508 data_len = iop_len; 1509 while(data_len >= 4) 1510 { 1511 *buf2++ = *iop_data++; 1512 data_len -= 4; 1513 } 1514 if(data_len) 1515 *buf2 = *iop_data; 1516 buf2 = (u_int32_t *)buf1; 1517 } 1518 while (iop_len > 0) { 1519 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1520 *pQbuffer = *buf1; 1521 acb->rqbuf_lastindex++; 1522 /* if last, index number set it to 0 */ 1523 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1524 buf1++; 1525 iop_len--; 1526 } 1527 if(buf2) 1528 free( (u_int8_t *)buf2, M_DEVBUF); 1529 /* let IOP know data has been read */ 1530 arcmsr_iop_message_read(acb); 1531 return (1); 1532 } 1533 /* 1534 ************************************************************************** 1535 ************************************************************************** 1536 */ 1537 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1538 struct QBUFFER *prbuffer) { 1539 u_int8_t *pQbuffer; 1540 u_int8_t *iop_data; 1541 u_int32_t iop_len; 1542 1543 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1544 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1545 } 1546 iop_data = (u_int8_t *)prbuffer->data; 1547 iop_len = (u_int32_t)prbuffer->data_len; 1548 while (iop_len > 0) { 1549 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1550 *pQbuffer = *iop_data; 1551 acb->rqbuf_lastindex++; 1552 /* if last, index number set it to 0 */ 1553 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1554 iop_data++; 1555 iop_len--; 1556 } 1557 /* let IOP know data has been read */ 1558 arcmsr_iop_message_read(acb); 1559 return (1); 1560 } 1561 /* 1562 ************************************************************************** 1563 ************************************************************************** 1564 */ 1565 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1566 { 1567 struct QBUFFER *prbuffer; 1568 int my_empty_len; 1569 1570 /*check this iop data if overflow my rqbuffer*/ 1571 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1572 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1573 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1574 (ARCMSR_MAX_QBUFFER-1); 1575 if(my_empty_len >= prbuffer->data_len) { 1576 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1577 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1578 } else { 1579 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1580 } 1581 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1582 } 1583 /* 1584 ********************************************************************** 1585 ********************************************************************** 1586 */ 1587 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1588 { 1589 u_int8_t *pQbuffer; 1590 struct QBUFFER *pwbuffer; 1591 u_int8_t *buf1 = NULL; 1592 u_int32_t *iop_data, *buf2 = NULL; 1593 u_int32_t allxfer_len = 0, data_len; 1594 1595 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1596 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1597 buf2 = (u_int32_t *)buf1; 1598 if( buf1 == NULL) 1599 return; 1600 1601 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1602 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1603 iop_data = (u_int32_t *)pwbuffer->data; 1604 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1605 && (allxfer_len < 124)) { 1606 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1607 *buf1 = *pQbuffer; 1608 acb->wqbuf_firstindex++; 1609 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1610 buf1++; 1611 allxfer_len++; 1612 } 1613 pwbuffer->data_len = allxfer_len; 1614 data_len = allxfer_len; 1615 buf1 = (u_int8_t *)buf2; 1616 while(data_len >= 4) 1617 { 1618 *iop_data++ = *buf2++; 1619 data_len -= 4; 1620 } 1621 if(data_len) 1622 *iop_data = *buf2; 1623 free( buf1, M_DEVBUF); 1624 arcmsr_iop_message_wrote(acb); 1625 } 1626 } 1627 /* 1628 ********************************************************************** 1629 ********************************************************************** 1630 */ 1631 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1632 { 1633 u_int8_t *pQbuffer; 1634 struct QBUFFER *pwbuffer; 1635 u_int8_t *iop_data; 1636 int32_t allxfer_len=0; 1637 1638 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1639 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1640 return; 1641 } 1642 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1643 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1644 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1645 iop_data = (u_int8_t *)pwbuffer->data; 1646 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1647 && (allxfer_len < 124)) { 1648 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1649 *iop_data = *pQbuffer; 1650 acb->wqbuf_firstindex++; 1651 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1652 iop_data++; 1653 allxfer_len++; 1654 } 1655 pwbuffer->data_len = allxfer_len; 1656 arcmsr_iop_message_wrote(acb); 1657 } 1658 } 1659 /* 1660 ************************************************************************** 1661 ************************************************************************** 1662 */ 1663 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1664 { 1665 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1666 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1667 /* 1668 ***************************************************************** 1669 ** check if there are any mail packages from user space program 1670 ** in my post bag, now is the time to send them into Areca's firmware 1671 ***************************************************************** 1672 */ 1673 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1674 arcmsr_Write_data_2iop_wqbuffer(acb); 1675 } 1676 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1677 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1678 } 1679 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1680 } 1681 /* 1682 ************************************************************************** 1683 ************************************************************************** 1684 */ 1685 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1686 { 1687 /* 1688 if (ccb->ccb_h.status != CAM_REQ_CMP) 1689 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1690 "failure status=%x\n", ccb->ccb_h.target_id, 1691 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1692 else 1693 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1694 */ 1695 xpt_free_path(ccb->ccb_h.path); 1696 xpt_free_ccb(ccb); 1697 } 1698 1699 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1700 { 1701 struct cam_path *path; 1702 union ccb *ccb; 1703 1704 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1705 return; 1706 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1707 { 1708 xpt_free_ccb(ccb); 1709 return; 1710 } 1711 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1712 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1713 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1714 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1715 ccb->crcn.flags = CAM_FLAG_NONE; 1716 xpt_action(ccb); 1717 } 1718 1719 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1720 { 1721 struct CommandControlBlock *srb; 1722 u_int32_t intmask_org; 1723 int i; 1724 1725 /* disable all outbound interrupts */ 1726 intmask_org = arcmsr_disable_allintr(acb); 1727 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1728 { 1729 srb = acb->psrb_pool[i]; 1730 if (srb->srb_state == ARCMSR_SRB_START) 1731 { 1732 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1733 { 1734 srb->srb_state = ARCMSR_SRB_ABORTED; 1735 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1736 arcmsr_srb_complete(srb, 1); 1737 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1738 } 1739 } 1740 } 1741 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1742 arcmsr_enable_allintr(acb, intmask_org); 1743 } 1744 /* 1745 ************************************************************************** 1746 ************************************************************************** 1747 */ 1748 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1749 u_int32_t devicemap; 1750 u_int32_t target, lun; 1751 u_int32_t deviceMapCurrent[4]={0}; 1752 u_int8_t *pDevMap; 1753 1754 switch (acb->adapter_type) { 1755 case ACB_ADAPTER_TYPE_A: 1756 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1757 for (target = 0; target < 4; target++) 1758 { 1759 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1760 devicemap += 4; 1761 } 1762 break; 1763 1764 case ACB_ADAPTER_TYPE_B: 1765 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1766 for (target = 0; target < 4; target++) 1767 { 1768 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1769 devicemap += 4; 1770 } 1771 break; 1772 1773 case ACB_ADAPTER_TYPE_C: 1774 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1775 for (target = 0; target < 4; target++) 1776 { 1777 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1778 devicemap += 4; 1779 } 1780 break; 1781 case ACB_ADAPTER_TYPE_D: 1782 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1783 for (target = 0; target < 4; target++) 1784 { 1785 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1786 devicemap += 4; 1787 } 1788 break; 1789 case ACB_ADAPTER_TYPE_E: 1790 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1791 for (target = 0; target < 4; target++) 1792 { 1793 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1794 devicemap += 4; 1795 } 1796 break; 1797 case ACB_ADAPTER_TYPE_F: 1798 devicemap = ARCMSR_FW_DEVMAP_OFFSET; 1799 for (target = 0; target < 4; target++) 1800 { 1801 deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap]; 1802 devicemap += 1; 1803 } 1804 break; 1805 } 1806 1807 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1808 { 1809 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1810 } 1811 /* 1812 ** adapter posted CONFIG message 1813 ** copy the new map, note if there are differences with the current map 1814 */ 1815 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1816 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1817 { 1818 if (*pDevMap != acb->device_map[target]) 1819 { 1820 u_int8_t difference, bit_check; 1821 1822 difference = *pDevMap ^ acb->device_map[target]; 1823 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1824 { 1825 bit_check = (1 << lun); /*check bit from 0....31*/ 1826 if(difference & bit_check) 1827 { 1828 if(acb->device_map[target] & bit_check) 1829 {/* unit departed */ 1830 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1831 arcmsr_abort_dr_ccbs(acb, target, lun); 1832 arcmsr_rescan_lun(acb, target, lun); 1833 acb->devstate[target][lun] = ARECA_RAID_GONE; 1834 } 1835 else 1836 {/* unit arrived */ 1837 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1838 arcmsr_rescan_lun(acb, target, lun); 1839 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1840 } 1841 } 1842 } 1843 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1844 acb->device_map[target] = *pDevMap; 1845 } 1846 pDevMap++; 1847 } 1848 } 1849 /* 1850 ************************************************************************** 1851 ************************************************************************** 1852 */ 1853 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1854 u_int32_t outbound_message; 1855 1856 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1857 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1858 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1859 arcmsr_dr_handle( acb ); 1860 } 1861 /* 1862 ************************************************************************** 1863 ************************************************************************** 1864 */ 1865 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1866 u_int32_t outbound_message; 1867 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1868 1869 /* clear interrupts */ 1870 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1871 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1872 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1873 arcmsr_dr_handle( acb ); 1874 } 1875 /* 1876 ************************************************************************** 1877 ************************************************************************** 1878 */ 1879 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1880 u_int32_t outbound_message; 1881 1882 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1883 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1884 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1885 arcmsr_dr_handle( acb ); 1886 } 1887 /* 1888 ************************************************************************** 1889 ************************************************************************** 1890 */ 1891 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1892 u_int32_t outbound_message; 1893 1894 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1895 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1896 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1897 arcmsr_dr_handle( acb ); 1898 } 1899 /* 1900 ************************************************************************** 1901 ************************************************************************** 1902 */ 1903 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) { 1904 u_int32_t outbound_message; 1905 1906 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); 1907 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 1908 outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]); 1909 else 1910 outbound_message = acb->msgcode_rwbuffer[0]; 1911 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1912 arcmsr_dr_handle( acb ); 1913 } 1914 /* 1915 ************************************************************************** 1916 ************************************************************************** 1917 */ 1918 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1919 { 1920 u_int32_t doorbell_status; 1921 1922 /* 1923 ******************************************************************* 1924 ** Maybe here we need to check wrqbuffer_lock is lock or not 1925 ** DOORBELL: din! don! 1926 ** check if there are any mail need to pack from firmware 1927 ******************************************************************* 1928 */ 1929 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 1930 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1931 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1932 arcmsr_iop2drv_data_wrote_handle(acb); 1933 } 1934 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1935 arcmsr_iop2drv_data_read_handle(acb); 1936 } 1937 } 1938 /* 1939 ************************************************************************** 1940 ************************************************************************** 1941 */ 1942 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1943 { 1944 u_int32_t doorbell_status; 1945 1946 /* 1947 ******************************************************************* 1948 ** Maybe here we need to check wrqbuffer_lock is lock or not 1949 ** DOORBELL: din! don! 1950 ** check if there are any mail need to pack from firmware 1951 ******************************************************************* 1952 */ 1953 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1954 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */ 1955 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1956 arcmsr_iop2drv_data_wrote_handle(acb); 1957 } 1958 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1959 arcmsr_iop2drv_data_read_handle(acb); 1960 } 1961 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1962 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1963 } 1964 } 1965 /* 1966 ************************************************************************** 1967 ************************************************************************** 1968 */ 1969 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1970 { 1971 u_int32_t doorbell_status; 1972 1973 /* 1974 ******************************************************************* 1975 ** Maybe here we need to check wrqbuffer_lock is lock or not 1976 ** DOORBELL: din! don! 1977 ** check if there are any mail need to pack from firmware 1978 ******************************************************************* 1979 */ 1980 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1981 if(doorbell_status) 1982 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1983 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1984 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1985 arcmsr_iop2drv_data_wrote_handle(acb); 1986 } 1987 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1988 arcmsr_iop2drv_data_read_handle(acb); 1989 } 1990 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1991 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1992 } 1993 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1994 if(doorbell_status) 1995 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1996 } 1997 } 1998 /* 1999 ************************************************************************** 2000 ************************************************************************** 2001 */ 2002 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb) 2003 { 2004 u_int32_t doorbell_status, in_doorbell; 2005 2006 /* 2007 ******************************************************************* 2008 ** Maybe here we need to check wrqbuffer_lock is lock or not 2009 ** DOORBELL: din! don! 2010 ** check if there are any mail need to pack from firmware 2011 ******************************************************************* 2012 */ 2013 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2014 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2015 doorbell_status = in_doorbell ^ acb->in_doorbell; 2016 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2017 arcmsr_iop2drv_data_wrote_handle(acb); 2018 } 2019 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2020 arcmsr_iop2drv_data_read_handle(acb); 2021 } 2022 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2023 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2024 } 2025 acb->in_doorbell = in_doorbell; 2026 } 2027 /* 2028 ************************************************************************** 2029 ************************************************************************** 2030 */ 2031 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 2032 { 2033 u_int32_t flag_srb; 2034 u_int16_t error; 2035 2036 /* 2037 ***************************************************************************** 2038 ** areca cdb command done 2039 ***************************************************************************** 2040 */ 2041 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2042 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2043 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 2044 0, outbound_queueport)) != 0xFFFFFFFF) { 2045 /* check if command done with no error*/ 2046 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 2047 arcmsr_drain_donequeue(acb, flag_srb, error); 2048 } /*drain reply FIFO*/ 2049 } 2050 /* 2051 ************************************************************************** 2052 ************************************************************************** 2053 */ 2054 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 2055 { 2056 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2057 u_int32_t flag_srb; 2058 int index; 2059 u_int16_t error; 2060 2061 /* 2062 ***************************************************************************** 2063 ** areca cdb command done 2064 ***************************************************************************** 2065 */ 2066 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2067 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2068 index = phbbmu->doneq_index; 2069 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 2070 phbbmu->done_qbuffer[index] = 0; 2071 index++; 2072 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 2073 phbbmu->doneq_index = index; 2074 /* check if command done with no error*/ 2075 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2076 arcmsr_drain_donequeue(acb, flag_srb, error); 2077 } /*drain reply FIFO*/ 2078 } 2079 /* 2080 ************************************************************************** 2081 ************************************************************************** 2082 */ 2083 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 2084 { 2085 u_int32_t flag_srb,throttling = 0; 2086 u_int16_t error; 2087 2088 /* 2089 ***************************************************************************** 2090 ** areca cdb command done 2091 ***************************************************************************** 2092 */ 2093 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2094 do { 2095 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 2096 if (flag_srb == 0xFFFFFFFF) 2097 break; 2098 /* check if command done with no error*/ 2099 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 2100 arcmsr_drain_donequeue(acb, flag_srb, error); 2101 throttling++; 2102 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2103 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 2104 throttling = 0; 2105 } 2106 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR); 2107 } 2108 /* 2109 ********************************************************************** 2110 ** 2111 ********************************************************************** 2112 */ 2113 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 2114 { 2115 uint16_t doneq_index, index_stripped; 2116 2117 doneq_index = phbdmu->doneq_index; 2118 if (doneq_index & 0x4000) { 2119 index_stripped = doneq_index & 0xFF; 2120 index_stripped += 1; 2121 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2122 phbdmu->doneq_index = index_stripped ? 2123 (index_stripped | 0x4000) : index_stripped; 2124 } else { 2125 index_stripped = doneq_index; 2126 index_stripped += 1; 2127 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2128 phbdmu->doneq_index = index_stripped ? 2129 index_stripped : (index_stripped | 0x4000); 2130 } 2131 return (phbdmu->doneq_index); 2132 } 2133 /* 2134 ************************************************************************** 2135 ************************************************************************** 2136 */ 2137 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 2138 { 2139 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 2140 u_int32_t outbound_write_pointer; 2141 u_int32_t addressLow; 2142 uint16_t doneq_index; 2143 u_int16_t error; 2144 /* 2145 ***************************************************************************** 2146 ** areca cdb command done 2147 ***************************************************************************** 2148 */ 2149 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 2150 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 2151 return; 2152 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2153 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2154 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2155 doneq_index = phbdmu->doneq_index; 2156 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 2157 doneq_index = arcmsr_get_doneq_index(phbdmu); 2158 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2159 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2160 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2161 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2162 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2163 } 2164 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2165 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2166 } 2167 /* 2168 ************************************************************************** 2169 ************************************************************************** 2170 */ 2171 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb) 2172 { 2173 u_int16_t error; 2174 uint32_t doneq_index; 2175 uint16_t cmdSMID; 2176 2177 /* 2178 ***************************************************************************** 2179 ** areca cdb command done 2180 ***************************************************************************** 2181 */ 2182 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2183 doneq_index = acb->doneq_index; 2184 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) { 2185 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2186 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2187 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2188 doneq_index++; 2189 if (doneq_index >= acb->completionQ_entry) 2190 doneq_index = 0; 2191 } 2192 acb->doneq_index = doneq_index; 2193 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2194 } 2195 2196 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb) 2197 { 2198 uint16_t error; 2199 uint32_t doneq_index; 2200 uint16_t cmdSMID; 2201 2202 /* 2203 ***************************************************************************** 2204 ** areca cdb command done 2205 ***************************************************************************** 2206 */ 2207 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2208 doneq_index = acb->doneq_index; 2209 while (1) { 2210 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2211 if (cmdSMID == 0xffff) 2212 break; 2213 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2214 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2215 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff; 2216 doneq_index++; 2217 if (doneq_index >= acb->completionQ_entry) 2218 doneq_index = 0; 2219 } 2220 acb->doneq_index = doneq_index; 2221 CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2222 } 2223 2224 /* 2225 ********************************************************************** 2226 ********************************************************************** 2227 */ 2228 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2229 { 2230 u_int32_t outbound_intStatus; 2231 /* 2232 ********************************************* 2233 ** check outbound intstatus 2234 ********************************************* 2235 */ 2236 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2237 if(!outbound_intStatus) { 2238 /*it must be share irq*/ 2239 return; 2240 } 2241 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2242 /* MU doorbell interrupts*/ 2243 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2244 arcmsr_hba_doorbell_isr(acb); 2245 } 2246 /* MU post queue interrupts*/ 2247 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2248 arcmsr_hba_postqueue_isr(acb); 2249 } 2250 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2251 arcmsr_hba_message_isr(acb); 2252 } 2253 } 2254 /* 2255 ********************************************************************** 2256 ********************************************************************** 2257 */ 2258 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2259 { 2260 u_int32_t outbound_doorbell; 2261 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2262 /* 2263 ********************************************* 2264 ** check outbound intstatus 2265 ********************************************* 2266 */ 2267 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable; 2268 if(!outbound_doorbell) { 2269 /*it must be share irq*/ 2270 return; 2271 } 2272 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2273 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell); 2274 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2275 /* MU ioctl transfer doorbell interrupts*/ 2276 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2277 arcmsr_iop2drv_data_wrote_handle(acb); 2278 } 2279 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2280 arcmsr_iop2drv_data_read_handle(acb); 2281 } 2282 /* MU post queue interrupts*/ 2283 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2284 arcmsr_hbb_postqueue_isr(acb); 2285 } 2286 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2287 arcmsr_hbb_message_isr(acb); 2288 } 2289 } 2290 /* 2291 ********************************************************************** 2292 ********************************************************************** 2293 */ 2294 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2295 { 2296 u_int32_t host_interrupt_status; 2297 /* 2298 ********************************************* 2299 ** check outbound intstatus 2300 ********************************************* 2301 */ 2302 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & 2303 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2304 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2305 if(!host_interrupt_status) { 2306 /*it must be share irq*/ 2307 return; 2308 } 2309 do { 2310 /* MU doorbell interrupts*/ 2311 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2312 arcmsr_hbc_doorbell_isr(acb); 2313 } 2314 /* MU post queue interrupts*/ 2315 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2316 arcmsr_hbc_postqueue_isr(acb); 2317 } 2318 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2319 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2320 } 2321 /* 2322 ********************************************************************** 2323 ********************************************************************** 2324 */ 2325 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2326 { 2327 u_int32_t host_interrupt_status; 2328 u_int32_t intmask_org; 2329 /* 2330 ********************************************* 2331 ** check outbound intstatus 2332 ********************************************* 2333 */ 2334 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2335 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2336 /*it must be share irq*/ 2337 return; 2338 } 2339 /* disable outbound interrupt */ 2340 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2341 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2342 /* MU doorbell interrupts*/ 2343 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2344 arcmsr_hbd_doorbell_isr(acb); 2345 } 2346 /* MU post queue interrupts*/ 2347 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2348 arcmsr_hbd_postqueue_isr(acb); 2349 } 2350 /* enable all outbound interrupt */ 2351 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2352 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2353 } 2354 /* 2355 ********************************************************************** 2356 ********************************************************************** 2357 */ 2358 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb) 2359 { 2360 u_int32_t host_interrupt_status; 2361 /* 2362 ********************************************* 2363 ** check outbound intstatus 2364 ********************************************* 2365 */ 2366 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) & 2367 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2368 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2369 if(!host_interrupt_status) { 2370 /*it must be share irq*/ 2371 return; 2372 } 2373 do { 2374 /* MU doorbell interrupts*/ 2375 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2376 arcmsr_hbe_doorbell_isr(acb); 2377 } 2378 /* MU post queue interrupts*/ 2379 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2380 arcmsr_hbe_postqueue_isr(acb); 2381 } 2382 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status); 2383 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2384 } 2385 2386 static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb) 2387 { 2388 u_int32_t host_interrupt_status; 2389 /* 2390 ********************************************* 2391 ** check outbound intstatus 2392 ********************************************* 2393 */ 2394 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) & 2395 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2396 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2397 if(!host_interrupt_status) { 2398 /*it must be share irq*/ 2399 return; 2400 } 2401 do { 2402 /* MU doorbell interrupts*/ 2403 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2404 arcmsr_hbe_doorbell_isr(acb); 2405 } 2406 /* MU post queue interrupts*/ 2407 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2408 arcmsr_hbf_postqueue_isr(acb); 2409 } 2410 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status); 2411 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2412 } 2413 /* 2414 ****************************************************************************** 2415 ****************************************************************************** 2416 */ 2417 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2418 { 2419 switch (acb->adapter_type) { 2420 case ACB_ADAPTER_TYPE_A: 2421 arcmsr_handle_hba_isr(acb); 2422 break; 2423 case ACB_ADAPTER_TYPE_B: 2424 arcmsr_handle_hbb_isr(acb); 2425 break; 2426 case ACB_ADAPTER_TYPE_C: 2427 arcmsr_handle_hbc_isr(acb); 2428 break; 2429 case ACB_ADAPTER_TYPE_D: 2430 arcmsr_handle_hbd_isr(acb); 2431 break; 2432 case ACB_ADAPTER_TYPE_E: 2433 arcmsr_handle_hbe_isr(acb); 2434 break; 2435 case ACB_ADAPTER_TYPE_F: 2436 arcmsr_handle_hbf_isr(acb); 2437 break; 2438 default: 2439 printf("arcmsr%d: interrupt service," 2440 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2441 break; 2442 } 2443 } 2444 /* 2445 ********************************************************************** 2446 ********************************************************************** 2447 */ 2448 static void arcmsr_intr_handler(void *arg) 2449 { 2450 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2451 2452 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2453 arcmsr_interrupt(acb); 2454 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2455 } 2456 /* 2457 ****************************************************************************** 2458 ****************************************************************************** 2459 */ 2460 static void arcmsr_polling_devmap(void *arg) 2461 { 2462 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2463 switch (acb->adapter_type) { 2464 case ACB_ADAPTER_TYPE_A: 2465 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2466 break; 2467 2468 case ACB_ADAPTER_TYPE_B: { 2469 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2470 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2471 } 2472 break; 2473 2474 case ACB_ADAPTER_TYPE_C: 2475 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2476 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2477 break; 2478 2479 case ACB_ADAPTER_TYPE_D: 2480 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2481 break; 2482 2483 case ACB_ADAPTER_TYPE_E: 2484 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2485 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2486 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2487 break; 2488 2489 case ACB_ADAPTER_TYPE_F: { 2490 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1); 2491 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) || 2492 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE)) 2493 goto nxt6s; 2494 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2495 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2496 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2497 break; 2498 } 2499 } 2500 nxt6s: 2501 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2502 { 2503 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2504 } 2505 } 2506 2507 /* 2508 ******************************************************************************* 2509 ** 2510 ******************************************************************************* 2511 */ 2512 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2513 { 2514 u_int32_t intmask_org; 2515 2516 if(acb != NULL) { 2517 /* stop adapter background rebuild */ 2518 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2519 intmask_org = arcmsr_disable_allintr(acb); 2520 arcmsr_stop_adapter_bgrb(acb); 2521 arcmsr_flush_adapter_cache(acb); 2522 arcmsr_enable_allintr(acb, intmask_org); 2523 } 2524 } 2525 } 2526 /* 2527 *********************************************************************** 2528 ** 2529 ************************************************************************ 2530 */ 2531 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2532 { 2533 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2534 u_int32_t retvalue = EINVAL; 2535 2536 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2537 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2538 return retvalue; 2539 } 2540 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2541 switch(ioctl_cmd) { 2542 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2543 u_int8_t *pQbuffer; 2544 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2545 u_int32_t allxfer_len=0; 2546 2547 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2548 && (allxfer_len < 1031)) { 2549 /*copy READ QBUFFER to srb*/ 2550 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2551 *ptmpQbuffer = *pQbuffer; 2552 acb->rqbuf_firstindex++; 2553 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2554 /*if last index number set it to 0 */ 2555 ptmpQbuffer++; 2556 allxfer_len++; 2557 } 2558 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2559 struct QBUFFER *prbuffer; 2560 2561 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2562 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2563 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2564 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2565 } 2566 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2567 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2568 retvalue = ARCMSR_MESSAGE_SUCCESS; 2569 } 2570 break; 2571 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2572 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2573 u_int8_t *pQbuffer; 2574 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2575 2576 user_len = pcmdmessagefld->cmdmessage.Length; 2577 /*check if data xfer length of this request will overflow my array qbuffer */ 2578 wqbuf_lastindex = acb->wqbuf_lastindex; 2579 wqbuf_firstindex = acb->wqbuf_firstindex; 2580 if(wqbuf_lastindex != wqbuf_firstindex) { 2581 arcmsr_Write_data_2iop_wqbuffer(acb); 2582 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2583 } else { 2584 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2585 (ARCMSR_MAX_QBUFFER - 1); 2586 if(my_empty_len >= user_len) { 2587 while(user_len > 0) { 2588 /*copy srb data to wqbuffer*/ 2589 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2590 *pQbuffer = *ptmpuserbuffer; 2591 acb->wqbuf_lastindex++; 2592 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2593 /*if last index number set it to 0 */ 2594 ptmpuserbuffer++; 2595 user_len--; 2596 } 2597 /*post fist Qbuffer*/ 2598 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2599 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2600 arcmsr_Write_data_2iop_wqbuffer(acb); 2601 } 2602 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2603 } else { 2604 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2605 } 2606 } 2607 retvalue = ARCMSR_MESSAGE_SUCCESS; 2608 } 2609 break; 2610 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2611 u_int8_t *pQbuffer = acb->rqbuffer; 2612 2613 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2614 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2615 arcmsr_iop_message_read(acb); 2616 /*signature, let IOP know data has been readed */ 2617 } 2618 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2619 acb->rqbuf_firstindex = 0; 2620 acb->rqbuf_lastindex = 0; 2621 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2622 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2623 retvalue = ARCMSR_MESSAGE_SUCCESS; 2624 } 2625 break; 2626 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2627 { 2628 u_int8_t *pQbuffer = acb->wqbuffer; 2629 2630 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2631 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2632 arcmsr_iop_message_read(acb); 2633 /*signature, let IOP know data has been readed */ 2634 } 2635 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2636 acb->wqbuf_firstindex = 0; 2637 acb->wqbuf_lastindex = 0; 2638 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2639 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2640 retvalue = ARCMSR_MESSAGE_SUCCESS; 2641 } 2642 break; 2643 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2644 u_int8_t *pQbuffer; 2645 2646 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2647 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2648 arcmsr_iop_message_read(acb); 2649 /*signature, let IOP know data has been readed */ 2650 } 2651 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2652 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2653 |ACB_F_MESSAGE_WQBUFFER_READ); 2654 acb->rqbuf_firstindex = 0; 2655 acb->rqbuf_lastindex = 0; 2656 acb->wqbuf_firstindex = 0; 2657 acb->wqbuf_lastindex = 0; 2658 pQbuffer = acb->rqbuffer; 2659 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2660 pQbuffer = acb->wqbuffer; 2661 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2662 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2663 retvalue = ARCMSR_MESSAGE_SUCCESS; 2664 } 2665 break; 2666 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2667 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2668 retvalue = ARCMSR_MESSAGE_SUCCESS; 2669 } 2670 break; 2671 case ARCMSR_MESSAGE_SAY_HELLO: { 2672 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2673 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2674 2675 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2676 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2677 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2678 return ENOIOCTL; 2679 } 2680 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2681 retvalue = ARCMSR_MESSAGE_SUCCESS; 2682 } 2683 break; 2684 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2685 arcmsr_iop_parking(acb); 2686 retvalue = ARCMSR_MESSAGE_SUCCESS; 2687 } 2688 break; 2689 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2690 arcmsr_flush_adapter_cache(acb); 2691 retvalue = ARCMSR_MESSAGE_SUCCESS; 2692 } 2693 break; 2694 } 2695 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2696 return (retvalue); 2697 } 2698 /* 2699 ************************************************************************** 2700 ************************************************************************** 2701 */ 2702 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2703 { 2704 struct AdapterControlBlock *acb; 2705 2706 acb = srb->acb; 2707 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2708 srb->srb_state = ARCMSR_SRB_DONE; 2709 srb->srb_flags = 0; 2710 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2711 acb->workingsrb_doneindex++; 2712 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2713 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2714 } 2715 /* 2716 ************************************************************************** 2717 ************************************************************************** 2718 */ 2719 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2720 { 2721 struct CommandControlBlock *srb = NULL; 2722 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2723 2724 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2725 workingsrb_doneindex = acb->workingsrb_doneindex; 2726 workingsrb_startindex = acb->workingsrb_startindex; 2727 srb = acb->srbworkingQ[workingsrb_startindex]; 2728 workingsrb_startindex++; 2729 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2730 if(workingsrb_doneindex != workingsrb_startindex) { 2731 acb->workingsrb_startindex = workingsrb_startindex; 2732 } else { 2733 srb = NULL; 2734 } 2735 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2736 return(srb); 2737 } 2738 /* 2739 ************************************************************************** 2740 ************************************************************************** 2741 */ 2742 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2743 { 2744 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2745 int retvalue = 0, transfer_len = 0; 2746 char *buffer; 2747 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio); 2748 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 | 2749 (u_int32_t ) ptr[6] << 16 | 2750 (u_int32_t ) ptr[7] << 8 | 2751 (u_int32_t ) ptr[8]; 2752 /* 4 bytes: Areca io control code */ 2753 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2754 buffer = pccb->csio.data_ptr; 2755 transfer_len = pccb->csio.dxfer_len; 2756 } else { 2757 retvalue = ARCMSR_MESSAGE_FAIL; 2758 goto message_out; 2759 } 2760 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2761 retvalue = ARCMSR_MESSAGE_FAIL; 2762 goto message_out; 2763 } 2764 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2765 switch(controlcode) { 2766 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2767 u_int8_t *pQbuffer; 2768 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2769 int32_t allxfer_len = 0; 2770 2771 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2772 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2773 && (allxfer_len < 1031)) { 2774 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2775 *ptmpQbuffer = *pQbuffer; 2776 acb->rqbuf_firstindex++; 2777 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2778 ptmpQbuffer++; 2779 allxfer_len++; 2780 } 2781 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2782 struct QBUFFER *prbuffer; 2783 2784 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2785 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2786 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2787 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2788 } 2789 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2790 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2791 retvalue = ARCMSR_MESSAGE_SUCCESS; 2792 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2793 } 2794 break; 2795 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2796 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2797 u_int8_t *pQbuffer; 2798 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2799 2800 user_len = pcmdmessagefld->cmdmessage.Length; 2801 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2802 wqbuf_lastindex = acb->wqbuf_lastindex; 2803 wqbuf_firstindex = acb->wqbuf_firstindex; 2804 if (wqbuf_lastindex != wqbuf_firstindex) { 2805 arcmsr_Write_data_2iop_wqbuffer(acb); 2806 /* has error report sensedata */ 2807 if(pccb->csio.sense_len) { 2808 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2809 /* Valid,ErrorCode */ 2810 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2811 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2812 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2813 /* AdditionalSenseLength */ 2814 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2815 /* AdditionalSenseCode */ 2816 } 2817 retvalue = ARCMSR_MESSAGE_FAIL; 2818 } else { 2819 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2820 &(ARCMSR_MAX_QBUFFER - 1); 2821 if (my_empty_len >= user_len) { 2822 while (user_len > 0) { 2823 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2824 *pQbuffer = *ptmpuserbuffer; 2825 acb->wqbuf_lastindex++; 2826 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2827 ptmpuserbuffer++; 2828 user_len--; 2829 } 2830 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2831 acb->acb_flags &= 2832 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2833 arcmsr_Write_data_2iop_wqbuffer(acb); 2834 } 2835 } else { 2836 /* has error report sensedata */ 2837 if(pccb->csio.sense_len) { 2838 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2839 /* Valid,ErrorCode */ 2840 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2841 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2842 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2843 /* AdditionalSenseLength */ 2844 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2845 /* AdditionalSenseCode */ 2846 } 2847 retvalue = ARCMSR_MESSAGE_FAIL; 2848 } 2849 } 2850 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2851 } 2852 break; 2853 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2854 u_int8_t *pQbuffer = acb->rqbuffer; 2855 2856 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2857 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2858 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2859 arcmsr_iop_message_read(acb); 2860 } 2861 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2862 acb->rqbuf_firstindex = 0; 2863 acb->rqbuf_lastindex = 0; 2864 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2865 pcmdmessagefld->cmdmessage.ReturnCode = 2866 ARCMSR_MESSAGE_RETURNCODE_OK; 2867 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2868 } 2869 break; 2870 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2871 u_int8_t *pQbuffer = acb->wqbuffer; 2872 2873 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2874 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2875 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2876 arcmsr_iop_message_read(acb); 2877 } 2878 acb->acb_flags |= 2879 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2880 ACB_F_MESSAGE_WQBUFFER_READ); 2881 acb->wqbuf_firstindex = 0; 2882 acb->wqbuf_lastindex = 0; 2883 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2884 pcmdmessagefld->cmdmessage.ReturnCode = 2885 ARCMSR_MESSAGE_RETURNCODE_OK; 2886 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2887 } 2888 break; 2889 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2890 u_int8_t *pQbuffer; 2891 2892 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2893 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2894 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2895 arcmsr_iop_message_read(acb); 2896 } 2897 acb->acb_flags |= 2898 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2899 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2900 | ACB_F_MESSAGE_WQBUFFER_READ); 2901 acb->rqbuf_firstindex = 0; 2902 acb->rqbuf_lastindex = 0; 2903 acb->wqbuf_firstindex = 0; 2904 acb->wqbuf_lastindex = 0; 2905 pQbuffer = acb->rqbuffer; 2906 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2907 pQbuffer = acb->wqbuffer; 2908 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2909 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2910 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2911 } 2912 break; 2913 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2914 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2915 } 2916 break; 2917 case ARCMSR_MESSAGE_SAY_HELLO: { 2918 int8_t *hello_string = "Hello! I am ARCMSR"; 2919 2920 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2921 , (int16_t)strlen(hello_string)); 2922 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2923 } 2924 break; 2925 case ARCMSR_MESSAGE_SAY_GOODBYE: 2926 arcmsr_iop_parking(acb); 2927 break; 2928 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2929 arcmsr_flush_adapter_cache(acb); 2930 break; 2931 default: 2932 retvalue = ARCMSR_MESSAGE_FAIL; 2933 } 2934 message_out: 2935 return (retvalue); 2936 } 2937 /* 2938 ********************************************************************* 2939 ********************************************************************* 2940 */ 2941 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2942 { 2943 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2944 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2945 union ccb *pccb; 2946 int target, lun; 2947 2948 pccb = srb->pccb; 2949 target = pccb->ccb_h.target_id; 2950 lun = pccb->ccb_h.target_lun; 2951 acb->pktRequestCount++; 2952 if(error != 0) { 2953 if(error != EFBIG) { 2954 printf("arcmsr%d: unexpected error %x" 2955 " returned from 'bus_dmamap_load' \n" 2956 , acb->pci_unit, error); 2957 } 2958 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2959 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2960 } 2961 arcmsr_srb_complete(srb, 0); 2962 return; 2963 } 2964 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2965 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2966 arcmsr_srb_complete(srb, 0); 2967 return; 2968 } 2969 if(acb->acb_flags & ACB_F_BUS_RESET) { 2970 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2971 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2972 arcmsr_srb_complete(srb, 0); 2973 return; 2974 } 2975 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2976 u_int8_t block_cmd, cmd; 2977 2978 cmd = scsiio_cdb_ptr(&pccb->csio)[0]; 2979 block_cmd = cmd & 0x0f; 2980 if(block_cmd == 0x08 || block_cmd == 0x0a) { 2981 printf("arcmsr%d:block 'read/write' command " 2982 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 2983 , acb->pci_unit, cmd, target, lun); 2984 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2985 arcmsr_srb_complete(srb, 0); 2986 return; 2987 } 2988 } 2989 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 2990 if(nseg != 0) { 2991 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 2992 } 2993 arcmsr_srb_complete(srb, 0); 2994 return; 2995 } 2996 if(acb->srboutstandingcount >= acb->maxOutstanding) { 2997 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 2998 { 2999 xpt_freeze_simq(acb->psim, 1); 3000 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 3001 } 3002 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 3003 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 3004 arcmsr_srb_complete(srb, 0); 3005 return; 3006 } 3007 pccb->ccb_h.status |= CAM_SIM_QUEUED; 3008 arcmsr_build_srb(srb, dm_segs, nseg); 3009 arcmsr_post_srb(acb, srb); 3010 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 3011 { 3012 arcmsr_callout_init(&srb->ccb_callout); 3013 callout_reset_sbt(&srb->ccb_callout, SBT_1MS * 3014 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0, 3015 arcmsr_srb_timeout, srb, 0); 3016 srb->srb_flags |= SRB_FLAG_TIMER_START; 3017 } 3018 } 3019 /* 3020 ***************************************************************************************** 3021 ***************************************************************************************** 3022 */ 3023 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 3024 { 3025 struct CommandControlBlock *srb; 3026 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 3027 u_int32_t intmask_org; 3028 int i = 0; 3029 3030 acb->num_aborts++; 3031 /* 3032 *************************************************************************** 3033 ** It is the upper layer do abort command this lock just prior to calling us. 3034 ** First determine if we currently own this command. 3035 ** Start by searching the device queue. If not found 3036 ** at all, and the system wanted us to just abort the 3037 ** command return success. 3038 *************************************************************************** 3039 */ 3040 if(acb->srboutstandingcount != 0) { 3041 /* disable all outbound interrupt */ 3042 intmask_org = arcmsr_disable_allintr(acb); 3043 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3044 srb = acb->psrb_pool[i]; 3045 if(srb->srb_state == ARCMSR_SRB_START) { 3046 if(srb->pccb == abortccb) { 3047 srb->srb_state = ARCMSR_SRB_ABORTED; 3048 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'" 3049 "outstanding command \n" 3050 , acb->pci_unit, abortccb->ccb_h.target_id 3051 , (uintmax_t)abortccb->ccb_h.target_lun, srb); 3052 arcmsr_polling_srbdone(acb, srb); 3053 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3054 arcmsr_enable_allintr(acb, intmask_org); 3055 return (TRUE); 3056 } 3057 } 3058 } 3059 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3060 arcmsr_enable_allintr(acb, intmask_org); 3061 } 3062 return(FALSE); 3063 } 3064 /* 3065 **************************************************************************** 3066 **************************************************************************** 3067 */ 3068 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 3069 { 3070 int retry = 0; 3071 3072 acb->num_resets++; 3073 acb->acb_flags |= ACB_F_BUS_RESET; 3074 while(acb->srboutstandingcount != 0 && retry < 400) { 3075 arcmsr_interrupt(acb); 3076 UDELAY(25000); 3077 retry++; 3078 } 3079 arcmsr_iop_reset(acb); 3080 acb->acb_flags &= ~ACB_F_BUS_RESET; 3081 } 3082 /* 3083 ************************************************************************** 3084 ************************************************************************** 3085 */ 3086 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 3087 union ccb *pccb) 3088 { 3089 if (pccb->ccb_h.target_lun) { 3090 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3091 xpt_done(pccb); 3092 return; 3093 } 3094 pccb->ccb_h.status |= CAM_REQ_CMP; 3095 switch (scsiio_cdb_ptr(&pccb->csio)[0]) { 3096 case INQUIRY: { 3097 unsigned char inqdata[36]; 3098 char *buffer = pccb->csio.data_ptr; 3099 3100 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 3101 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 3102 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 3103 inqdata[3] = 0; 3104 inqdata[4] = 31; /* length of additional data */ 3105 inqdata[5] = 0; 3106 inqdata[6] = 0; 3107 inqdata[7] = 0; 3108 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 3109 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 3110 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 3111 memcpy(buffer, inqdata, sizeof(inqdata)); 3112 xpt_done(pccb); 3113 } 3114 break; 3115 case WRITE_BUFFER: 3116 case READ_BUFFER: { 3117 if (arcmsr_iop_message_xfer(acb, pccb)) { 3118 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 3119 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 3120 } 3121 xpt_done(pccb); 3122 } 3123 break; 3124 default: 3125 xpt_done(pccb); 3126 } 3127 } 3128 /* 3129 ********************************************************************* 3130 ********************************************************************* 3131 */ 3132 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 3133 { 3134 struct AdapterControlBlock *acb; 3135 3136 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 3137 if(acb == NULL) { 3138 pccb->ccb_h.status |= CAM_REQ_INVALID; 3139 xpt_done(pccb); 3140 return; 3141 } 3142 switch (pccb->ccb_h.func_code) { 3143 case XPT_SCSI_IO: { 3144 struct CommandControlBlock *srb; 3145 int target = pccb->ccb_h.target_id; 3146 int error; 3147 3148 if (pccb->ccb_h.flags & CAM_CDB_PHYS) { 3149 pccb->ccb_h.status = CAM_REQ_INVALID; 3150 xpt_done(pccb); 3151 return; 3152 } 3153 3154 if(target == 16) { 3155 /* virtual device for iop message transfer */ 3156 arcmsr_handle_virtual_command(acb, pccb); 3157 return; 3158 } 3159 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 3160 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 3161 xpt_done(pccb); 3162 return; 3163 } 3164 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 3165 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 3166 srb->pccb = pccb; 3167 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 3168 , srb->dm_segs_dmamap 3169 , pccb 3170 , arcmsr_execute_srb, srb, /*flags*/0); 3171 if(error == EINPROGRESS) { 3172 xpt_freeze_simq(acb->psim, 1); 3173 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 3174 } 3175 break; 3176 } 3177 case XPT_PATH_INQ: { 3178 struct ccb_pathinq *cpi = &pccb->cpi; 3179 3180 cpi->version_num = 1; 3181 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 3182 cpi->target_sprt = 0; 3183 cpi->hba_misc = 0; 3184 cpi->hba_eng_cnt = 0; 3185 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 3186 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 3187 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 3188 cpi->bus_id = cam_sim_bus(psim); 3189 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3190 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 3191 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 3192 cpi->unit_number = cam_sim_unit(psim); 3193 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3194 cpi->base_transfer_speed = 1200000; 3195 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3196 cpi->base_transfer_speed = 600000; 3197 else 3198 cpi->base_transfer_speed = 300000; 3199 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3200 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3201 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3202 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3203 { 3204 cpi->transport = XPORT_SAS; 3205 cpi->transport_version = 0; 3206 cpi->protocol_version = SCSI_REV_SPC2; 3207 } 3208 else 3209 { 3210 cpi->transport = XPORT_SPI; 3211 cpi->transport_version = 2; 3212 cpi->protocol_version = SCSI_REV_2; 3213 } 3214 cpi->protocol = PROTO_SCSI; 3215 cpi->ccb_h.status |= CAM_REQ_CMP; 3216 xpt_done(pccb); 3217 break; 3218 } 3219 case XPT_ABORT: { 3220 union ccb *pabort_ccb; 3221 3222 pabort_ccb = pccb->cab.abort_ccb; 3223 switch (pabort_ccb->ccb_h.func_code) { 3224 case XPT_ACCEPT_TARGET_IO: 3225 case XPT_CONT_TARGET_IO: 3226 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 3227 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 3228 xpt_done(pabort_ccb); 3229 pccb->ccb_h.status |= CAM_REQ_CMP; 3230 } else { 3231 xpt_print_path(pabort_ccb->ccb_h.path); 3232 printf("Not found\n"); 3233 pccb->ccb_h.status |= CAM_PATH_INVALID; 3234 } 3235 break; 3236 case XPT_SCSI_IO: 3237 pccb->ccb_h.status |= CAM_UA_ABORT; 3238 break; 3239 default: 3240 pccb->ccb_h.status |= CAM_REQ_INVALID; 3241 break; 3242 } 3243 xpt_done(pccb); 3244 break; 3245 } 3246 case XPT_RESET_BUS: 3247 case XPT_RESET_DEV: { 3248 u_int32_t i; 3249 3250 arcmsr_bus_reset(acb); 3251 for (i=0; i < 500; i++) { 3252 DELAY(1000); 3253 } 3254 pccb->ccb_h.status |= CAM_REQ_CMP; 3255 xpt_done(pccb); 3256 break; 3257 } 3258 case XPT_TERM_IO: { 3259 pccb->ccb_h.status |= CAM_REQ_INVALID; 3260 xpt_done(pccb); 3261 break; 3262 } 3263 case XPT_GET_TRAN_SETTINGS: { 3264 struct ccb_trans_settings *cts; 3265 3266 if(pccb->ccb_h.target_id == 16) { 3267 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3268 xpt_done(pccb); 3269 break; 3270 } 3271 cts = &pccb->cts; 3272 { 3273 struct ccb_trans_settings_scsi *scsi; 3274 struct ccb_trans_settings_spi *spi; 3275 struct ccb_trans_settings_sas *sas; 3276 3277 scsi = &cts->proto_specific.scsi; 3278 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 3279 scsi->valid = CTS_SCSI_VALID_TQ; 3280 cts->protocol = PROTO_SCSI; 3281 3282 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3283 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3284 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3285 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3286 { 3287 cts->protocol_version = SCSI_REV_SPC2; 3288 cts->transport_version = 0; 3289 cts->transport = XPORT_SAS; 3290 sas = &cts->xport_specific.sas; 3291 sas->valid = CTS_SAS_VALID_SPEED; 3292 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3293 sas->bitrate = 1200000; 3294 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3295 sas->bitrate = 600000; 3296 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G) 3297 sas->bitrate = 300000; 3298 } 3299 else 3300 { 3301 cts->protocol_version = SCSI_REV_2; 3302 cts->transport_version = 2; 3303 cts->transport = XPORT_SPI; 3304 spi = &cts->xport_specific.spi; 3305 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 3306 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3307 spi->sync_period = 1; 3308 else 3309 spi->sync_period = 2; 3310 spi->sync_offset = 32; 3311 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3312 spi->valid = CTS_SPI_VALID_DISC 3313 | CTS_SPI_VALID_SYNC_RATE 3314 | CTS_SPI_VALID_SYNC_OFFSET 3315 | CTS_SPI_VALID_BUS_WIDTH; 3316 } 3317 } 3318 pccb->ccb_h.status |= CAM_REQ_CMP; 3319 xpt_done(pccb); 3320 break; 3321 } 3322 case XPT_SET_TRAN_SETTINGS: { 3323 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3324 xpt_done(pccb); 3325 break; 3326 } 3327 case XPT_CALC_GEOMETRY: 3328 if(pccb->ccb_h.target_id == 16) { 3329 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3330 xpt_done(pccb); 3331 break; 3332 } 3333 cam_calc_geometry(&pccb->ccg, 1); 3334 xpt_done(pccb); 3335 break; 3336 default: 3337 pccb->ccb_h.status |= CAM_REQ_INVALID; 3338 xpt_done(pccb); 3339 break; 3340 } 3341 } 3342 /* 3343 ********************************************************************** 3344 ********************************************************************** 3345 */ 3346 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3347 { 3348 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3349 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3350 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3351 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3352 } 3353 } 3354 /* 3355 ********************************************************************** 3356 ********************************************************************** 3357 */ 3358 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3359 { 3360 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3361 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3362 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3363 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3364 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3365 } 3366 } 3367 /* 3368 ********************************************************************** 3369 ********************************************************************** 3370 */ 3371 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3372 { 3373 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3374 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3375 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3376 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3377 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3378 } 3379 } 3380 /* 3381 ********************************************************************** 3382 ********************************************************************** 3383 */ 3384 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3385 { 3386 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3387 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3388 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3389 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3390 } 3391 } 3392 /* 3393 ********************************************************************** 3394 ********************************************************************** 3395 */ 3396 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb) 3397 { 3398 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3399 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3400 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3401 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3402 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3403 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3404 } 3405 } 3406 /* 3407 ********************************************************************** 3408 ********************************************************************** 3409 */ 3410 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3411 { 3412 switch (acb->adapter_type) { 3413 case ACB_ADAPTER_TYPE_A: 3414 arcmsr_start_hba_bgrb(acb); 3415 break; 3416 case ACB_ADAPTER_TYPE_B: 3417 arcmsr_start_hbb_bgrb(acb); 3418 break; 3419 case ACB_ADAPTER_TYPE_C: 3420 arcmsr_start_hbc_bgrb(acb); 3421 break; 3422 case ACB_ADAPTER_TYPE_D: 3423 arcmsr_start_hbd_bgrb(acb); 3424 break; 3425 case ACB_ADAPTER_TYPE_E: 3426 case ACB_ADAPTER_TYPE_F: 3427 arcmsr_start_hbe_bgrb(acb); 3428 break; 3429 } 3430 } 3431 /* 3432 ********************************************************************** 3433 ** 3434 ********************************************************************** 3435 */ 3436 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3437 { 3438 struct CommandControlBlock *srb; 3439 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3440 u_int16_t error; 3441 3442 polling_ccb_retry: 3443 poll_count++; 3444 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3445 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3446 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3447 while(1) { 3448 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3449 0, outbound_queueport)) == 0xFFFFFFFF) { 3450 if(poll_srb_done) { 3451 break;/*chip FIFO no ccb for completion already*/ 3452 } else { 3453 UDELAY(25000); 3454 if ((poll_count > 100) && (poll_srb != NULL)) { 3455 break; 3456 } 3457 goto polling_ccb_retry; 3458 } 3459 } 3460 /* check if command done with no error*/ 3461 srb = (struct CommandControlBlock *) 3462 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3463 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3464 poll_srb_done = (srb == poll_srb) ? 1:0; 3465 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3466 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3467 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3468 "poll command abort successfully \n" 3469 , acb->pci_unit 3470 , srb->pccb->ccb_h.target_id 3471 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3472 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3473 arcmsr_srb_complete(srb, 1); 3474 continue; 3475 } 3476 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3477 "srboutstandingcount=%d \n" 3478 , acb->pci_unit 3479 , srb, acb->srboutstandingcount); 3480 continue; 3481 } 3482 arcmsr_report_srb_state(acb, srb, error); 3483 } /*drain reply FIFO*/ 3484 } 3485 /* 3486 ********************************************************************** 3487 ** 3488 ********************************************************************** 3489 */ 3490 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3491 { 3492 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3493 struct CommandControlBlock *srb; 3494 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3495 int index; 3496 u_int16_t error; 3497 3498 polling_ccb_retry: 3499 poll_count++; 3500 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3501 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3502 while(1) { 3503 index = phbbmu->doneq_index; 3504 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3505 if(poll_srb_done) { 3506 break;/*chip FIFO no ccb for completion already*/ 3507 } else { 3508 UDELAY(25000); 3509 if ((poll_count > 100) && (poll_srb != NULL)) { 3510 break; 3511 } 3512 goto polling_ccb_retry; 3513 } 3514 } 3515 phbbmu->done_qbuffer[index] = 0; 3516 index++; 3517 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3518 phbbmu->doneq_index = index; 3519 /* check if command done with no error*/ 3520 srb = (struct CommandControlBlock *) 3521 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3522 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3523 poll_srb_done = (srb == poll_srb) ? 1:0; 3524 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3525 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3526 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3527 "poll command abort successfully \n" 3528 , acb->pci_unit 3529 , srb->pccb->ccb_h.target_id 3530 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3531 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3532 arcmsr_srb_complete(srb, 1); 3533 continue; 3534 } 3535 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3536 "srboutstandingcount=%d \n" 3537 , acb->pci_unit 3538 , srb, acb->srboutstandingcount); 3539 continue; 3540 } 3541 arcmsr_report_srb_state(acb, srb, error); 3542 } /*drain reply FIFO*/ 3543 } 3544 /* 3545 ********************************************************************** 3546 ** 3547 ********************************************************************** 3548 */ 3549 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3550 { 3551 struct CommandControlBlock *srb; 3552 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3553 u_int16_t error; 3554 3555 polling_ccb_retry: 3556 poll_count++; 3557 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3558 while(1) { 3559 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3560 if(poll_srb_done) { 3561 break;/*chip FIFO no ccb for completion already*/ 3562 } else { 3563 UDELAY(25000); 3564 if ((poll_count > 100) && (poll_srb != NULL)) { 3565 break; 3566 } 3567 if (acb->srboutstandingcount == 0) { 3568 break; 3569 } 3570 goto polling_ccb_retry; 3571 } 3572 } 3573 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3574 /* check if command done with no error*/ 3575 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3576 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3577 if (poll_srb != NULL) 3578 poll_srb_done = (srb == poll_srb) ? 1:0; 3579 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3580 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3581 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3582 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3583 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3584 arcmsr_srb_complete(srb, 1); 3585 continue; 3586 } 3587 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3588 , acb->pci_unit, srb, acb->srboutstandingcount); 3589 continue; 3590 } 3591 arcmsr_report_srb_state(acb, srb, error); 3592 } /*drain reply FIFO*/ 3593 } 3594 /* 3595 ********************************************************************** 3596 ** 3597 ********************************************************************** 3598 */ 3599 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3600 { 3601 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3602 struct CommandControlBlock *srb; 3603 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3604 u_int32_t outbound_write_pointer; 3605 u_int16_t error, doneq_index; 3606 3607 polling_ccb_retry: 3608 poll_count++; 3609 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3610 while(1) { 3611 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3612 doneq_index = phbdmu->doneq_index; 3613 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3614 if(poll_srb_done) { 3615 break;/*chip FIFO no ccb for completion already*/ 3616 } else { 3617 UDELAY(25000); 3618 if ((poll_count > 100) && (poll_srb != NULL)) { 3619 break; 3620 } 3621 if (acb->srboutstandingcount == 0) { 3622 break; 3623 } 3624 goto polling_ccb_retry; 3625 } 3626 } 3627 doneq_index = arcmsr_get_doneq_index(phbdmu); 3628 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3629 /* check if command done with no error*/ 3630 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3631 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3632 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3633 if (poll_srb != NULL) 3634 poll_srb_done = (srb == poll_srb) ? 1:0; 3635 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3636 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3637 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3638 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3639 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3640 arcmsr_srb_complete(srb, 1); 3641 continue; 3642 } 3643 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3644 , acb->pci_unit, srb, acb->srboutstandingcount); 3645 continue; 3646 } 3647 arcmsr_report_srb_state(acb, srb, error); 3648 } /*drain reply FIFO*/ 3649 } 3650 /* 3651 ********************************************************************** 3652 ** 3653 ********************************************************************** 3654 */ 3655 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3656 { 3657 struct CommandControlBlock *srb; 3658 u_int32_t poll_srb_done=0, poll_count=0, doneq_index; 3659 u_int16_t error, cmdSMID; 3660 3661 polling_ccb_retry: 3662 poll_count++; 3663 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3664 while(1) { 3665 doneq_index = acb->doneq_index; 3666 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) { 3667 if(poll_srb_done) { 3668 break;/*chip FIFO no ccb for completion already*/ 3669 } else { 3670 UDELAY(25000); 3671 if ((poll_count > 100) && (poll_srb != NULL)) { 3672 break; 3673 } 3674 if (acb->srboutstandingcount == 0) { 3675 break; 3676 } 3677 goto polling_ccb_retry; 3678 } 3679 } 3680 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3681 doneq_index++; 3682 if (doneq_index >= acb->completionQ_entry) 3683 doneq_index = 0; 3684 acb->doneq_index = doneq_index; 3685 srb = acb->psrb_pool[cmdSMID]; 3686 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3687 if (poll_srb != NULL) 3688 poll_srb_done = (srb == poll_srb) ? 1:0; 3689 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3690 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3691 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3692 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3693 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3694 arcmsr_srb_complete(srb, 1); 3695 continue; 3696 } 3697 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3698 , acb->pci_unit, srb, acb->srboutstandingcount); 3699 continue; 3700 } 3701 arcmsr_report_srb_state(acb, srb, error); 3702 } /*drain reply FIFO*/ 3703 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index); 3704 } 3705 /* 3706 ********************************************************************** 3707 ********************************************************************** 3708 */ 3709 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3710 { 3711 switch (acb->adapter_type) { 3712 case ACB_ADAPTER_TYPE_A: 3713 arcmsr_polling_hba_srbdone(acb, poll_srb); 3714 break; 3715 case ACB_ADAPTER_TYPE_B: 3716 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3717 break; 3718 case ACB_ADAPTER_TYPE_C: 3719 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3720 break; 3721 case ACB_ADAPTER_TYPE_D: 3722 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3723 break; 3724 case ACB_ADAPTER_TYPE_E: 3725 case ACB_ADAPTER_TYPE_F: 3726 arcmsr_polling_hbe_srbdone(acb, poll_srb); 3727 break; 3728 } 3729 } 3730 /* 3731 ********************************************************************** 3732 ********************************************************************** 3733 */ 3734 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3735 { 3736 char *acb_firm_model = acb->firm_model; 3737 char *acb_firm_version = acb->firm_version; 3738 char *acb_device_map = acb->device_map; 3739 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3740 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3741 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3742 int i; 3743 3744 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3745 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3746 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3747 } 3748 i = 0; 3749 while(i < 8) { 3750 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3751 /* 8 bytes firm_model, 15, 60-67*/ 3752 acb_firm_model++; 3753 i++; 3754 } 3755 i=0; 3756 while(i < 16) { 3757 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3758 /* 16 bytes firm_version, 17, 68-83*/ 3759 acb_firm_version++; 3760 i++; 3761 } 3762 i=0; 3763 while(i < 16) { 3764 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3765 acb_device_map++; 3766 i++; 3767 } 3768 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3769 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3770 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3771 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3772 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3773 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3774 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3775 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3776 else 3777 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3778 } 3779 /* 3780 ********************************************************************** 3781 ********************************************************************** 3782 */ 3783 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3784 { 3785 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3786 char *acb_firm_model = acb->firm_model; 3787 char *acb_firm_version = acb->firm_version; 3788 char *acb_device_map = acb->device_map; 3789 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3790 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3791 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3792 int i; 3793 3794 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3795 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3796 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3797 } 3798 i = 0; 3799 while(i < 8) { 3800 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3801 /* 8 bytes firm_model, 15, 60-67*/ 3802 acb_firm_model++; 3803 i++; 3804 } 3805 i = 0; 3806 while(i < 16) { 3807 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3808 /* 16 bytes firm_version, 17, 68-83*/ 3809 acb_firm_version++; 3810 i++; 3811 } 3812 i = 0; 3813 while(i < 16) { 3814 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3815 acb_device_map++; 3816 i++; 3817 } 3818 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3819 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3820 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3821 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3822 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3823 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3824 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3825 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3826 else 3827 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3828 } 3829 /* 3830 ********************************************************************** 3831 ********************************************************************** 3832 */ 3833 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3834 { 3835 char *acb_firm_model = acb->firm_model; 3836 char *acb_firm_version = acb->firm_version; 3837 char *acb_device_map = acb->device_map; 3838 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3839 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3840 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3841 int i; 3842 3843 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3844 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3845 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3846 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3847 } 3848 i = 0; 3849 while(i < 8) { 3850 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3851 /* 8 bytes firm_model, 15, 60-67*/ 3852 acb_firm_model++; 3853 i++; 3854 } 3855 i = 0; 3856 while(i < 16) { 3857 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3858 /* 16 bytes firm_version, 17, 68-83*/ 3859 acb_firm_version++; 3860 i++; 3861 } 3862 i = 0; 3863 while(i < 16) { 3864 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3865 acb_device_map++; 3866 i++; 3867 } 3868 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3869 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3870 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3871 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3872 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3873 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3874 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3875 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3876 else 3877 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3878 } 3879 /* 3880 ********************************************************************** 3881 ********************************************************************** 3882 */ 3883 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3884 { 3885 char *acb_firm_model = acb->firm_model; 3886 char *acb_firm_version = acb->firm_version; 3887 char *acb_device_map = acb->device_map; 3888 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3889 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3890 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3891 int i; 3892 3893 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3894 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3895 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3896 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3897 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3898 } 3899 i = 0; 3900 while(i < 8) { 3901 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3902 /* 8 bytes firm_model, 15, 60-67*/ 3903 acb_firm_model++; 3904 i++; 3905 } 3906 i = 0; 3907 while(i < 16) { 3908 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3909 /* 16 bytes firm_version, 17, 68-83*/ 3910 acb_firm_version++; 3911 i++; 3912 } 3913 i = 0; 3914 while(i < 16) { 3915 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3916 acb_device_map++; 3917 i++; 3918 } 3919 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3920 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3921 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3922 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3923 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3924 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3925 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3926 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3927 else 3928 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3929 } 3930 /* 3931 ********************************************************************** 3932 ********************************************************************** 3933 */ 3934 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb) 3935 { 3936 char *acb_firm_model = acb->firm_model; 3937 char *acb_firm_version = acb->firm_version; 3938 char *acb_device_map = acb->device_map; 3939 size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3940 size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3941 size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3942 int i; 3943 3944 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3945 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3946 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3947 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3948 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3949 } 3950 3951 i = 0; 3952 while(i < 8) { 3953 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3954 /* 8 bytes firm_model, 15, 60-67*/ 3955 acb_firm_model++; 3956 i++; 3957 } 3958 i = 0; 3959 while(i < 16) { 3960 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3961 /* 16 bytes firm_version, 17, 68-83*/ 3962 acb_firm_version++; 3963 i++; 3964 } 3965 i = 0; 3966 while(i < 16) { 3967 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3968 acb_device_map++; 3969 i++; 3970 } 3971 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3972 acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3973 acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3974 acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3975 acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3976 acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3977 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3978 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3979 else 3980 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3981 } 3982 /* 3983 ********************************************************************** 3984 ********************************************************************** 3985 */ 3986 static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb) 3987 { 3988 u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model; 3989 u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version; 3990 u_int32_t *acb_device_map = (u_int32_t *)acb->device_map; 3991 size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/ 3992 size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/ 3993 size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET; 3994 int i; 3995 3996 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3997 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3998 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3999 if(!arcmsr_hbe_wait_msgint_ready(acb)) 4000 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 4001 4002 i = 0; 4003 while(i < 2) { 4004 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model]; 4005 /* 8 bytes firm_model, 15, 60-67*/ 4006 acb_firm_model++; 4007 iop_firm_model++; 4008 i++; 4009 } 4010 i = 0; 4011 while(i < 4) { 4012 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version]; 4013 /* 16 bytes firm_version, 17, 68-83*/ 4014 acb_firm_version++; 4015 iop_firm_version++; 4016 i++; 4017 } 4018 i = 0; 4019 while(i < 4) { 4020 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map]; 4021 acb_device_map++; 4022 iop_device_map++; 4023 i++; 4024 } 4025 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 4026 acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/ 4027 acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/ 4028 acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/ 4029 acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/ 4030 acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/ 4031 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 4032 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 4033 else 4034 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4035 } 4036 /* 4037 ********************************************************************** 4038 ********************************************************************** 4039 */ 4040 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 4041 { 4042 switch (acb->adapter_type) { 4043 case ACB_ADAPTER_TYPE_A: 4044 arcmsr_get_hba_config(acb); 4045 break; 4046 case ACB_ADAPTER_TYPE_B: 4047 arcmsr_get_hbb_config(acb); 4048 break; 4049 case ACB_ADAPTER_TYPE_C: 4050 arcmsr_get_hbc_config(acb); 4051 break; 4052 case ACB_ADAPTER_TYPE_D: 4053 arcmsr_get_hbd_config(acb); 4054 break; 4055 case ACB_ADAPTER_TYPE_E: 4056 arcmsr_get_hbe_config(acb); 4057 break; 4058 case ACB_ADAPTER_TYPE_F: 4059 arcmsr_get_hbf_config(acb); 4060 break; 4061 } 4062 } 4063 /* 4064 ********************************************************************** 4065 ********************************************************************** 4066 */ 4067 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 4068 { 4069 int timeout=0; 4070 4071 switch (acb->adapter_type) { 4072 case ACB_ADAPTER_TYPE_A: { 4073 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 4074 { 4075 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4076 { 4077 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 4078 return; 4079 } 4080 UDELAY(15000); /* wait 15 milli-seconds */ 4081 } 4082 } 4083 break; 4084 case ACB_ADAPTER_TYPE_B: { 4085 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4086 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 4087 { 4088 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4089 { 4090 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 4091 return; 4092 } 4093 UDELAY(15000); /* wait 15 milli-seconds */ 4094 } 4095 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 4096 } 4097 break; 4098 case ACB_ADAPTER_TYPE_C: { 4099 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 4100 { 4101 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4102 { 4103 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4104 return; 4105 } 4106 UDELAY(15000); /* wait 15 milli-seconds */ 4107 } 4108 } 4109 break; 4110 case ACB_ADAPTER_TYPE_D: { 4111 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 4112 { 4113 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4114 { 4115 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4116 return; 4117 } 4118 UDELAY(15000); /* wait 15 milli-seconds */ 4119 } 4120 } 4121 break; 4122 case ACB_ADAPTER_TYPE_E: 4123 case ACB_ADAPTER_TYPE_F: { 4124 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0) 4125 { 4126 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */ 4127 { 4128 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4129 return; 4130 } 4131 UDELAY(15000); /* wait 15 milli-seconds */ 4132 } 4133 } 4134 break; 4135 } 4136 } 4137 /* 4138 ********************************************************************** 4139 ********************************************************************** 4140 */ 4141 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 4142 { 4143 u_int32_t outbound_doorbell; 4144 4145 switch (acb->adapter_type) { 4146 case ACB_ADAPTER_TYPE_A: { 4147 /* empty doorbell Qbuffer if door bell ringed */ 4148 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 4149 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4150 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 4151 } 4152 break; 4153 case ACB_ADAPTER_TYPE_B: { 4154 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4155 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 4156 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 4157 /* let IOP know data has been read */ 4158 } 4159 break; 4160 case ACB_ADAPTER_TYPE_C: { 4161 /* empty doorbell Qbuffer if door bell ringed */ 4162 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 4163 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 4164 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 4165 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 4166 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 4167 } 4168 break; 4169 case ACB_ADAPTER_TYPE_D: { 4170 /* empty doorbell Qbuffer if door bell ringed */ 4171 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 4172 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4173 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 4174 } 4175 break; 4176 case ACB_ADAPTER_TYPE_E: 4177 case ACB_ADAPTER_TYPE_F: { 4178 /* empty doorbell Qbuffer if door bell ringed */ 4179 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 4180 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */ 4181 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4182 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4183 } 4184 break; 4185 } 4186 } 4187 /* 4188 ************************************************************************ 4189 ************************************************************************ 4190 */ 4191 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 4192 { 4193 unsigned long srb_phyaddr; 4194 u_int32_t srb_phyaddr_hi32; 4195 u_int32_t srb_phyaddr_lo32; 4196 4197 /* 4198 ******************************************************************** 4199 ** here we need to tell iop 331 our freesrb.HighPart 4200 ** if freesrb.HighPart is not zero 4201 ******************************************************************** 4202 */ 4203 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 4204 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 4205 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 4206 switch (acb->adapter_type) { 4207 case ACB_ADAPTER_TYPE_A: { 4208 if(srb_phyaddr_hi32 != 0) { 4209 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4210 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4211 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4212 if(!arcmsr_hba_wait_msgint_ready(acb)) { 4213 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4214 return FALSE; 4215 } 4216 } 4217 } 4218 break; 4219 /* 4220 *********************************************************************** 4221 ** if adapter type B, set window of "post command Q" 4222 *********************************************************************** 4223 */ 4224 case ACB_ADAPTER_TYPE_B: { 4225 u_int32_t post_queue_phyaddr; 4226 struct HBB_MessageUnit *phbbmu; 4227 4228 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4229 phbbmu->postq_index = 0; 4230 phbbmu->doneq_index = 0; 4231 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 4232 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4233 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 4234 return FALSE; 4235 } 4236 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 4237 + offsetof(struct HBB_MessageUnit, post_qbuffer); 4238 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4239 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 4240 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 4241 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 4242 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 4243 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 4244 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4245 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 4246 return FALSE; 4247 } 4248 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 4249 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4250 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 4251 return FALSE; 4252 } 4253 } 4254 break; 4255 case ACB_ADAPTER_TYPE_C: { 4256 if(srb_phyaddr_hi32 != 0) { 4257 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4258 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4259 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4260 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 4261 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 4262 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4263 return FALSE; 4264 } 4265 } 4266 } 4267 break; 4268 case ACB_ADAPTER_TYPE_D: { 4269 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 4270 struct HBD_MessageUnit0 *phbdmu; 4271 4272 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4273 phbdmu->postq_index = 0; 4274 phbdmu->doneq_index = 0x40FF; 4275 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4276 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 4277 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4278 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 4279 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4280 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4281 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 4282 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 4283 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 4284 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4285 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 4286 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4287 return FALSE; 4288 } 4289 } 4290 break; 4291 case ACB_ADAPTER_TYPE_E: { 4292 u_int32_t cdb_phyaddr_lo32; 4293 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4294 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4295 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884); 4296 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32); 4297 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32); 4298 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE); 4299 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4300 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32); 4301 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32); 4302 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE); 4303 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4304 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4305 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4306 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4307 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4308 return FALSE; 4309 } 4310 } 4311 break; 4312 case ACB_ADAPTER_TYPE_F: { 4313 u_int32_t cdb_phyaddr_lo32; 4314 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4315 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG; 4316 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886; 4317 acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32; 4318 acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32; 4319 acb->msgcode_rwbuffer[4] = SRB_SIZE; 4320 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4321 acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32; 4322 acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32; 4323 acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE; 4324 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4325 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4326 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4327 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4328 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4329 return FALSE; 4330 } 4331 } 4332 break; 4333 } 4334 return (TRUE); 4335 } 4336 /* 4337 ************************************************************************ 4338 ************************************************************************ 4339 */ 4340 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4341 { 4342 if (acb->adapter_type == ACB_ADAPTER_TYPE_B) 4343 { 4344 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4345 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 4346 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4347 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 4348 return; 4349 } 4350 } 4351 } 4352 /* 4353 ********************************************************************** 4354 ********************************************************************** 4355 */ 4356 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4357 { 4358 u_int32_t intmask_org; 4359 4360 /* disable all outbound interrupt */ 4361 intmask_org = arcmsr_disable_allintr(acb); 4362 arcmsr_wait_firmware_ready(acb); 4363 arcmsr_iop_confirm(acb); 4364 arcmsr_get_firmware_spec(acb); 4365 /*start background rebuild*/ 4366 arcmsr_start_adapter_bgrb(acb); 4367 /* empty doorbell Qbuffer if door bell ringed */ 4368 arcmsr_clear_doorbell_queue_buffer(acb); 4369 arcmsr_enable_eoi_mode(acb); 4370 /* enable outbound Post Queue, outbound doorbell Interrupt */ 4371 arcmsr_enable_allintr(acb, intmask_org); 4372 acb->acb_flags |= ACB_F_IOP_INITED; 4373 } 4374 /* 4375 ********************************************************************** 4376 ********************************************************************** 4377 */ 4378 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4379 { 4380 struct AdapterControlBlock *acb = arg; 4381 struct CommandControlBlock *srb_tmp; 4382 u_int32_t i; 4383 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 4384 4385 acb->srb_phyaddr.phyaddr = srb_phyaddr; 4386 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 4387 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4388 if(bus_dmamap_create(acb->dm_segs_dmat, 4389 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 4390 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 4391 printf("arcmsr%d:" 4392 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 4393 return; 4394 } 4395 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D) 4396 || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F)) 4397 { 4398 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 4399 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 4400 } 4401 else 4402 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 4403 srb_tmp->acb = acb; 4404 srb_tmp->smid = i << 16; 4405 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 4406 srb_phyaddr = srb_phyaddr + SRB_SIZE; 4407 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 4408 } 4409 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 4410 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4411 else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) { 4412 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4413 acb->completeQ_phys = srb_phyaddr; 4414 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE); 4415 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE); 4416 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100); 4417 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200); 4418 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE); 4419 } 4420 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 4421 } 4422 /* 4423 ************************************************************************ 4424 ************************************************************************ 4425 */ 4426 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 4427 { 4428 /* remove the control device */ 4429 if(acb->ioctl_dev != NULL) { 4430 destroy_dev(acb->ioctl_dev); 4431 } 4432 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 4433 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 4434 bus_dma_tag_destroy(acb->srb_dmat); 4435 bus_dma_tag_destroy(acb->dm_segs_dmat); 4436 bus_dma_tag_destroy(acb->parent_dmat); 4437 } 4438 /* 4439 ************************************************************************ 4440 ************************************************************************ 4441 */ 4442 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 4443 { 4444 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 4445 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 4446 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 4447 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 4448 } 4449 /* 4450 ************************************************************************ 4451 ************************************************************************ 4452 */ 4453 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 4454 { 4455 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 4456 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 4457 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 4458 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 4459 } 4460 /* 4461 ************************************************************************ 4462 ************************************************************************ 4463 */ 4464 static u_int32_t arcmsr_initialize(device_t dev) 4465 { 4466 struct AdapterControlBlock *acb = device_get_softc(dev); 4467 u_int16_t pci_command; 4468 int i, j,max_coherent_size; 4469 u_int32_t vendor_dev_id; 4470 4471 vendor_dev_id = pci_get_devid(dev); 4472 acb->vendor_device_id = vendor_dev_id; 4473 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4474 switch (vendor_dev_id) { 4475 case PCIDevVenIDARC1880: 4476 case PCIDevVenIDARC1882: 4477 case PCIDevVenIDARC1213: 4478 case PCIDevVenIDARC1223: { 4479 acb->adapter_type = ACB_ADAPTER_TYPE_C; 4480 if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) || 4481 (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) || 4482 (acb->sub_device_id == ARECA_SUB_DEV_ID_1226)) 4483 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4484 else 4485 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4486 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4487 } 4488 break; 4489 case PCIDevVenIDARC1884: 4490 acb->adapter_type = ACB_ADAPTER_TYPE_E; 4491 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4492 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE; 4493 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4494 break; 4495 case PCIDevVenIDARC1886_: 4496 case PCIDevVenIDARC1886: 4497 acb->adapter_type = ACB_ADAPTER_TYPE_F; 4498 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4499 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE; 4500 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4501 break; 4502 case PCIDevVenIDARC1214: { 4503 acb->adapter_type = ACB_ADAPTER_TYPE_D; 4504 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4505 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 4506 } 4507 break; 4508 case PCIDevVenIDARC1200: 4509 case PCIDevVenIDARC1201: { 4510 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4511 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4512 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4513 } 4514 break; 4515 case PCIDevVenIDARC1203: { 4516 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4517 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4518 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4519 } 4520 break; 4521 case PCIDevVenIDARC1110: 4522 case PCIDevVenIDARC1120: 4523 case PCIDevVenIDARC1130: 4524 case PCIDevVenIDARC1160: 4525 case PCIDevVenIDARC1170: 4526 case PCIDevVenIDARC1210: 4527 case PCIDevVenIDARC1220: 4528 case PCIDevVenIDARC1230: 4529 case PCIDevVenIDARC1231: 4530 case PCIDevVenIDARC1260: 4531 case PCIDevVenIDARC1261: 4532 case PCIDevVenIDARC1270: 4533 case PCIDevVenIDARC1280: 4534 case PCIDevVenIDARC1212: 4535 case PCIDevVenIDARC1222: 4536 case PCIDevVenIDARC1380: 4537 case PCIDevVenIDARC1381: 4538 case PCIDevVenIDARC1680: 4539 case PCIDevVenIDARC1681: { 4540 acb->adapter_type = ACB_ADAPTER_TYPE_A; 4541 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4542 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4543 } 4544 break; 4545 default: { 4546 printf("arcmsr%d:" 4547 " unknown RAID adapter type \n", device_get_unit(dev)); 4548 return ENOMEM; 4549 } 4550 } 4551 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4552 /*alignemnt*/ 1, 4553 /*boundary*/ 0, 4554 /*lowaddr*/ BUS_SPACE_MAXADDR, 4555 /*highaddr*/ BUS_SPACE_MAXADDR, 4556 /*filter*/ NULL, 4557 /*filterarg*/ NULL, 4558 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4559 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4560 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4561 /*flags*/ 0, 4562 /*lockfunc*/ NULL, 4563 /*lockarg*/ NULL, 4564 &acb->parent_dmat) != 0) 4565 { 4566 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4567 return ENOMEM; 4568 } 4569 4570 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4571 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4572 /*alignment*/ 1, 4573 /*boundary*/ 0, 4574 #ifdef PAE 4575 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4576 #else 4577 /*lowaddr*/ BUS_SPACE_MAXADDR, 4578 #endif 4579 /*highaddr*/ BUS_SPACE_MAXADDR, 4580 /*filter*/ NULL, 4581 /*filterarg*/ NULL, 4582 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4583 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4584 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4585 /*flags*/ 0, 4586 /*lockfunc*/ busdma_lock_mutex, 4587 /*lockarg*/ &acb->isr_lock, 4588 &acb->dm_segs_dmat) != 0) 4589 { 4590 bus_dma_tag_destroy(acb->parent_dmat); 4591 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4592 return ENOMEM; 4593 } 4594 4595 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4596 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4597 /*alignment*/ 0x20, 4598 /*boundary*/ 0, 4599 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4600 /*highaddr*/ BUS_SPACE_MAXADDR, 4601 /*filter*/ NULL, 4602 /*filterarg*/ NULL, 4603 /*maxsize*/ max_coherent_size, 4604 /*nsegments*/ 1, 4605 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4606 /*flags*/ 0, 4607 /*lockfunc*/ NULL, 4608 /*lockarg*/ NULL, 4609 &acb->srb_dmat) != 0) 4610 { 4611 bus_dma_tag_destroy(acb->dm_segs_dmat); 4612 bus_dma_tag_destroy(acb->parent_dmat); 4613 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4614 return ENXIO; 4615 } 4616 /* Allocation for our srbs */ 4617 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4618 bus_dma_tag_destroy(acb->srb_dmat); 4619 bus_dma_tag_destroy(acb->dm_segs_dmat); 4620 bus_dma_tag_destroy(acb->parent_dmat); 4621 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4622 return ENXIO; 4623 } 4624 /* And permanently map them */ 4625 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4626 bus_dma_tag_destroy(acb->srb_dmat); 4627 bus_dma_tag_destroy(acb->dm_segs_dmat); 4628 bus_dma_tag_destroy(acb->parent_dmat); 4629 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4630 return ENXIO; 4631 } 4632 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4633 pci_command |= PCIM_CMD_BUSMASTEREN; 4634 pci_command |= PCIM_CMD_PERRESPEN; 4635 pci_command |= PCIM_CMD_MWRICEN; 4636 /* Enable Busmaster */ 4637 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4638 switch(acb->adapter_type) { 4639 case ACB_ADAPTER_TYPE_A: { 4640 u_int32_t rid0 = PCIR_BAR(0); 4641 vm_offset_t mem_base0; 4642 4643 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4644 if(acb->sys_res_arcmsr[0] == NULL) { 4645 arcmsr_free_resource(acb); 4646 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4647 return ENOMEM; 4648 } 4649 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4650 arcmsr_free_resource(acb); 4651 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4652 return ENXIO; 4653 } 4654 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4655 if(mem_base0 == 0) { 4656 arcmsr_free_resource(acb); 4657 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4658 return ENXIO; 4659 } 4660 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4661 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4662 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4663 acb->rid[0] = rid0; 4664 } 4665 break; 4666 case ACB_ADAPTER_TYPE_B: { 4667 struct HBB_MessageUnit *phbbmu; 4668 struct CommandControlBlock *freesrb; 4669 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4670 vm_offset_t mem_base[]={0,0}; 4671 for(i=0; i < 2; i++) { 4672 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE); 4673 if(acb->sys_res_arcmsr[i] == NULL) { 4674 arcmsr_free_resource(acb); 4675 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4676 return ENOMEM; 4677 } 4678 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4679 arcmsr_free_resource(acb); 4680 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4681 return ENXIO; 4682 } 4683 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4684 if(mem_base[i] == 0) { 4685 arcmsr_free_resource(acb); 4686 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4687 return ENXIO; 4688 } 4689 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4690 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4691 } 4692 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4693 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4694 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4695 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4696 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4697 if (vendor_dev_id == PCIDevVenIDARC1203) { 4698 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell); 4699 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask); 4700 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell); 4701 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask); 4702 } else { 4703 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell); 4704 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask); 4705 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell); 4706 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask); 4707 } 4708 acb->rid[0] = rid[0]; 4709 acb->rid[1] = rid[1]; 4710 } 4711 break; 4712 case ACB_ADAPTER_TYPE_C: { 4713 u_int32_t rid0 = PCIR_BAR(1); 4714 vm_offset_t mem_base0; 4715 4716 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4717 if(acb->sys_res_arcmsr[0] == NULL) { 4718 arcmsr_free_resource(acb); 4719 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4720 return ENOMEM; 4721 } 4722 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4723 arcmsr_free_resource(acb); 4724 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4725 return ENXIO; 4726 } 4727 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4728 if(mem_base0 == 0) { 4729 arcmsr_free_resource(acb); 4730 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4731 return ENXIO; 4732 } 4733 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4734 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4735 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4736 acb->rid[0] = rid0; 4737 } 4738 break; 4739 case ACB_ADAPTER_TYPE_D: { 4740 struct HBD_MessageUnit0 *phbdmu; 4741 u_int32_t rid0 = PCIR_BAR(0); 4742 vm_offset_t mem_base0; 4743 4744 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4745 if(acb->sys_res_arcmsr[0] == NULL) { 4746 arcmsr_free_resource(acb); 4747 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4748 return ENOMEM; 4749 } 4750 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4751 arcmsr_free_resource(acb); 4752 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4753 return ENXIO; 4754 } 4755 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4756 if(mem_base0 == 0) { 4757 arcmsr_free_resource(acb); 4758 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4759 return ENXIO; 4760 } 4761 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4762 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4763 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4764 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4765 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4766 acb->rid[0] = rid0; 4767 } 4768 break; 4769 case ACB_ADAPTER_TYPE_E: { 4770 u_int32_t rid0 = PCIR_BAR(1); 4771 vm_offset_t mem_base0; 4772 4773 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4774 if(acb->sys_res_arcmsr[0] == NULL) { 4775 arcmsr_free_resource(acb); 4776 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4777 return ENOMEM; 4778 } 4779 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4780 arcmsr_free_resource(acb); 4781 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4782 return ENXIO; 4783 } 4784 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4785 if(mem_base0 == 0) { 4786 arcmsr_free_resource(acb); 4787 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4788 return ENXIO; 4789 } 4790 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4791 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4792 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4793 acb->doneq_index = 0; 4794 acb->in_doorbell = 0; 4795 acb->out_doorbell = 0; 4796 acb->rid[0] = rid0; 4797 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4798 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4799 } 4800 break; 4801 case ACB_ADAPTER_TYPE_F: { 4802 u_int32_t rid0 = PCIR_BAR(0); 4803 vm_offset_t mem_base0; 4804 unsigned long host_buffer_dma; 4805 4806 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4807 if(acb->sys_res_arcmsr[0] == NULL) { 4808 arcmsr_free_resource(acb); 4809 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4810 return ENOMEM; 4811 } 4812 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4813 arcmsr_free_resource(acb); 4814 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4815 return ENXIO; 4816 } 4817 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4818 if(mem_base0 == 0) { 4819 arcmsr_free_resource(acb); 4820 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4821 return ENXIO; 4822 } 4823 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4824 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4825 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4826 acb->doneq_index = 0; 4827 acb->in_doorbell = 0; 4828 acb->out_doorbell = 0; 4829 acb->rid[0] = rid0; 4830 arcmsr_wait_firmware_ready(acb); 4831 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4832 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4833 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE; 4834 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */ 4835 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */ 4836 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */ 4837 } 4838 break; 4839 } 4840 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4841 arcmsr_free_resource(acb); 4842 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4843 return ENXIO; 4844 } 4845 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4846 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4847 /* 4848 ******************************************************************** 4849 ** init raid volume state 4850 ******************************************************************** 4851 */ 4852 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4853 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4854 acb->devstate[i][j] = ARECA_RAID_GONE; 4855 } 4856 } 4857 arcmsr_iop_init(acb); 4858 return(0); 4859 } 4860 4861 static int arcmsr_setup_msix(struct AdapterControlBlock *acb) 4862 { 4863 int i; 4864 4865 for (i = 0; i < acb->msix_vectors; i++) { 4866 acb->irq_id[i] = 1 + i; 4867 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev, 4868 SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE); 4869 if (acb->irqres[i] == NULL) { 4870 printf("arcmsr: Can't allocate MSI-X resource\n"); 4871 goto irq_alloc_failed; 4872 } 4873 if (bus_setup_intr(acb->pci_dev, acb->irqres[i], 4874 INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler, 4875 acb, &acb->ih[i])) { 4876 printf("arcmsr: Cannot set up MSI-X interrupt handler\n"); 4877 goto irq_alloc_failed; 4878 } 4879 } 4880 printf("arcmsr: MSI-X INT enabled\n"); 4881 acb->acb_flags |= ACB_F_MSIX_ENABLED; 4882 return TRUE; 4883 4884 irq_alloc_failed: 4885 arcmsr_teardown_intr(acb->pci_dev, acb); 4886 return FALSE; 4887 } 4888 4889 /* 4890 ************************************************************************ 4891 ************************************************************************ 4892 */ 4893 static int arcmsr_attach(device_t dev) 4894 { 4895 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4896 u_int32_t unit=device_get_unit(dev); 4897 struct ccb_setasync csa; 4898 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4899 struct resource *irqres; 4900 4901 if(acb == NULL) { 4902 printf("arcmsr%d: cannot allocate softc\n", unit); 4903 return (ENOMEM); 4904 } 4905 arcmsr_mutex_init(acb); 4906 acb->pci_dev = dev; 4907 acb->pci_unit = unit; 4908 if(arcmsr_initialize(dev)) { 4909 printf("arcmsr%d: initialize failure!\n", unit); 4910 goto initialize_failed; 4911 } 4912 /* After setting up the adapter, map our interrupt */ 4913 acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS; 4914 if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) { 4915 if (arcmsr_setup_msix(acb) == TRUE) 4916 goto irqx; 4917 } 4918 acb->irq_id[0] = 0; 4919 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE); 4920 if(irqres == NULL || 4921 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) { 4922 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4923 goto setup_intr_failed; 4924 } 4925 acb->irqres[0] = irqres; 4926 irqx: 4927 /* 4928 * Now let the CAM generic SCSI layer find the SCSI devices on 4929 * the bus * start queue to reset to the idle loop. * 4930 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4931 * max_sim_transactions 4932 */ 4933 devq = cam_simq_alloc(acb->maxOutstanding); 4934 if(devq == NULL) { 4935 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4936 goto simq_alloc_failed; 4937 } 4938 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4939 if(acb->psim == NULL) { 4940 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4941 goto sim_alloc_failed; 4942 } 4943 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4944 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4945 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4946 goto xpt_bus_failed; 4947 } 4948 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4949 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4950 goto xpt_path_failed; 4951 } 4952 /* 4953 **************************************************** 4954 */ 4955 memset(&csa, 0, sizeof(csa)); 4956 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4957 csa.ccb_h.func_code = XPT_SASYNC_CB; 4958 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4959 csa.callback = arcmsr_async; 4960 csa.callback_arg = acb->psim; 4961 xpt_action((union ccb *)&csa); 4962 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4963 /* Create the control device. */ 4964 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 4965 4966 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4967 arcmsr_callout_init(&acb->devmap_callout); 4968 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4969 return (0); 4970 xpt_path_failed: 4971 xpt_bus_deregister(cam_sim_path(acb->psim)); 4972 xpt_bus_failed: 4973 cam_sim_free(acb->psim, /* free_simq */ TRUE); 4974 sim_alloc_failed: 4975 cam_simq_free(devq); 4976 simq_alloc_failed: 4977 arcmsr_teardown_intr(dev, acb); 4978 setup_intr_failed: 4979 arcmsr_free_resource(acb); 4980 initialize_failed: 4981 arcmsr_mutex_destroy(acb); 4982 return ENXIO; 4983 } 4984 4985 /* 4986 ************************************************************************ 4987 ************************************************************************ 4988 */ 4989 static int arcmsr_probe(device_t dev) 4990 { 4991 u_int32_t id; 4992 u_int16_t sub_device_id; 4993 static char buf[256]; 4994 char x_type[]={"unknown"}; 4995 char *type; 4996 int raid6 = 1; 4997 4998 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 4999 return (ENXIO); 5000 } 5001 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 5002 switch(id = pci_get_devid(dev)) { 5003 case PCIDevVenIDARC1110: 5004 case PCIDevVenIDARC1200: 5005 case PCIDevVenIDARC1201: 5006 case PCIDevVenIDARC1210: 5007 raid6 = 0; 5008 /*FALLTHRU*/ 5009 case PCIDevVenIDARC1120: 5010 case PCIDevVenIDARC1130: 5011 case PCIDevVenIDARC1160: 5012 case PCIDevVenIDARC1170: 5013 case PCIDevVenIDARC1220: 5014 case PCIDevVenIDARC1230: 5015 case PCIDevVenIDARC1231: 5016 case PCIDevVenIDARC1260: 5017 case PCIDevVenIDARC1261: 5018 case PCIDevVenIDARC1270: 5019 case PCIDevVenIDARC1280: 5020 type = "SATA 3G"; 5021 break; 5022 case PCIDevVenIDARC1212: 5023 case PCIDevVenIDARC1222: 5024 case PCIDevVenIDARC1380: 5025 case PCIDevVenIDARC1381: 5026 case PCIDevVenIDARC1680: 5027 case PCIDevVenIDARC1681: 5028 type = "SAS 3G"; 5029 break; 5030 case PCIDevVenIDARC1880: 5031 case PCIDevVenIDARC1882: 5032 case PCIDevVenIDARC1213: 5033 case PCIDevVenIDARC1223: 5034 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) || 5035 (sub_device_id == ARECA_SUB_DEV_ID_1216) || 5036 (sub_device_id == ARECA_SUB_DEV_ID_1226)) 5037 type = "SAS 12G"; 5038 else 5039 type = "SAS 6G"; 5040 break; 5041 case PCIDevVenIDARC1884: 5042 type = "SAS 12G"; 5043 break; 5044 case PCIDevVenIDARC1886_: 5045 case PCIDevVenIDARC1886: 5046 type = "NVME,SAS-12G,SATA-6G"; 5047 break; 5048 case PCIDevVenIDARC1214: 5049 case PCIDevVenIDARC1203: 5050 type = "SATA 6G"; 5051 break; 5052 default: 5053 type = x_type; 5054 raid6 = 0; 5055 break; 5056 } 5057 if(type == x_type) 5058 return(ENXIO); 5059 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n", 5060 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 5061 device_set_desc_copy(dev, buf); 5062 return (BUS_PROBE_DEFAULT); 5063 } 5064 /* 5065 ************************************************************************ 5066 ************************************************************************ 5067 */ 5068 static int arcmsr_shutdown(device_t dev) 5069 { 5070 u_int32_t i; 5071 struct CommandControlBlock *srb; 5072 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5073 5074 /* stop adapter background rebuild */ 5075 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5076 /* disable all outbound interrupt */ 5077 arcmsr_disable_allintr(acb); 5078 arcmsr_stop_adapter_bgrb(acb); 5079 arcmsr_flush_adapter_cache(acb); 5080 /* abort all outstanding command */ 5081 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 5082 acb->acb_flags &= ~ACB_F_IOP_INITED; 5083 if(acb->srboutstandingcount != 0) { 5084 /*clear and abort all outbound posted Q*/ 5085 arcmsr_done4abort_postqueue(acb); 5086 /* talk to iop 331 outstanding command aborted*/ 5087 arcmsr_abort_allcmd(acb); 5088 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 5089 srb = acb->psrb_pool[i]; 5090 if(srb->srb_state == ARCMSR_SRB_START) { 5091 srb->srb_state = ARCMSR_SRB_ABORTED; 5092 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 5093 arcmsr_srb_complete(srb, 1); 5094 } 5095 } 5096 } 5097 acb->srboutstandingcount = 0; 5098 acb->workingsrb_doneindex = 0; 5099 acb->workingsrb_startindex = 0; 5100 acb->pktRequestCount = 0; 5101 acb->pktReturnCount = 0; 5102 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5103 return (0); 5104 } 5105 /* 5106 ************************************************************************ 5107 ************************************************************************ 5108 */ 5109 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb) 5110 { 5111 int i; 5112 5113 if (acb->acb_flags & ACB_F_MSIX_ENABLED) { 5114 for (i = 0; i < acb->msix_vectors; i++) { 5115 if (acb->ih[i]) 5116 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]); 5117 if (acb->irqres[i] != NULL) 5118 bus_release_resource(dev, SYS_RES_IRQ, 5119 acb->irq_id[i], acb->irqres[i]); 5120 5121 acb->ih[i] = NULL; 5122 } 5123 pci_release_msi(dev); 5124 } else { 5125 if (acb->ih[0]) 5126 bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]); 5127 if (acb->irqres[0] != NULL) 5128 bus_release_resource(dev, SYS_RES_IRQ, 5129 acb->irq_id[0], acb->irqres[0]); 5130 acb->ih[0] = NULL; 5131 } 5132 5133 } 5134 /* 5135 ************************************************************************ 5136 ************************************************************************ 5137 */ 5138 static int arcmsr_detach(device_t dev) 5139 { 5140 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5141 int i; 5142 5143 callout_stop(&acb->devmap_callout); 5144 arcmsr_teardown_intr(dev, acb); 5145 arcmsr_shutdown(dev); 5146 arcmsr_free_resource(acb); 5147 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 5148 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]); 5149 } 5150 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5151 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 5152 xpt_free_path(acb->ppath); 5153 xpt_bus_deregister(cam_sim_path(acb->psim)); 5154 cam_sim_free(acb->psim, TRUE); 5155 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5156 arcmsr_mutex_destroy(acb); 5157 return (0); 5158 } 5159 5160 #ifdef ARCMSR_DEBUG1 5161 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 5162 { 5163 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 5164 return; 5165 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 5166 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 5167 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 5168 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 5169 } 5170 #endif 5171