1 /*- 2 * Interface for the 93C66/56/46/26/06 serial eeprom parts. 3 * 4 * Copyright (c) 1995, 1996 Daniel M. Eischen 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.c#19 $ 32 */ 33 34 /* 35 * The instruction set of the 93C66/56/46/26/06 chips are as follows: 36 * 37 * Start OP * 38 * Function Bit Code Address** Data Description 39 * ------------------------------------------------------------------- 40 * READ 1 10 A5 - A0 Reads data stored in memory, 41 * starting at specified address 42 * EWEN 1 00 11XXXX Write enable must precede 43 * all programming modes 44 * ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0 45 * WRITE 1 01 A5 - A0 D15 - D0 Writes register 46 * ERAL 1 00 10XXXX Erase all registers 47 * WRAL 1 00 01XXXX D15 - D0 Writes to all registers 48 * EWDS 1 00 00XXXX Disables all programming 49 * instructions 50 * *Note: A value of X for address is a don't care condition. 51 * **Note: There are 8 address bits for the 93C56/66 chips unlike 52 * the 93C46/26/06 chips which have 6 address bits. 53 * 54 * The 93C46 has a four wire interface: clock, chip select, data in, and 55 * data out. In order to perform one of the above functions, you need 56 * to enable the chip select for a clock period (typically a minimum of 57 * 1 usec, with the clock high and low a minimum of 750 and 250 nsec 58 * respectively). While the chip select remains high, you can clock in 59 * the instructions (above) starting with the start bit, followed by the 60 * OP code, Address, and Data (if needed). For the READ instruction, the 61 * requested 16-bit register contents is read from the data out line but 62 * is preceded by an initial zero (leading 0, followed by 16-bits, MSB 63 * first). The clock cycling from low to high initiates the next data 64 * bit to be sent from the chip. 65 */ 66 67 #include <dev/aic7xxx/aic7xxx_osm.h> 68 #include <dev/aic7xxx/aic7xxx_inline.h> 69 #include <dev/aic7xxx/aic7xxx_93cx6.h> 70 71 /* 72 * Right now, we only have to read the SEEPROM. But we make it easier to 73 * add other 93Cx6 functions. 74 */ 75 struct seeprom_cmd { 76 uint8_t len; 77 uint8_t bits[11]; 78 }; 79 80 /* Short opcodes for the c46 */ 81 static struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}}; 82 static struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}}; 83 84 /* Long opcodes for the C56/C66 */ 85 static struct seeprom_cmd seeprom_long_ewen = {11, {1, 0, 0, 1, 1, 0, 0, 0, 0}}; 86 static struct seeprom_cmd seeprom_long_ewds = {11, {1, 0, 0, 0, 0, 0, 0, 0, 0}}; 87 88 /* Common opcodes */ 89 static struct seeprom_cmd seeprom_write = {3, {1, 0, 1}}; 90 static struct seeprom_cmd seeprom_read = {3, {1, 1, 0}}; 91 92 /* 93 * Wait for the SEERDY to go high; about 800 ns. 94 */ 95 #define CLOCK_PULSE(sd, rdy) \ 96 while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) { \ 97 ; /* Do nothing */ \ 98 } \ 99 (void)SEEPROM_INB(sd); /* Clear clock */ 100 101 /* 102 * Send a START condition and the given command 103 */ 104 static void 105 send_seeprom_cmd(struct seeprom_descriptor *sd, struct seeprom_cmd *cmd) 106 { 107 uint8_t temp; 108 int i = 0; 109 110 /* Send chip select for one clock cycle. */ 111 temp = sd->sd_MS ^ sd->sd_CS; 112 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 113 CLOCK_PULSE(sd, sd->sd_RDY); 114 115 for (i = 0; i < cmd->len; i++) { 116 if (cmd->bits[i] != 0) 117 temp ^= sd->sd_DO; 118 SEEPROM_OUTB(sd, temp); 119 CLOCK_PULSE(sd, sd->sd_RDY); 120 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 121 CLOCK_PULSE(sd, sd->sd_RDY); 122 if (cmd->bits[i] != 0) 123 temp ^= sd->sd_DO; 124 } 125 } 126 127 /* 128 * Clear CS put the chip in the reset state, where it can wait for new commands. 129 */ 130 static void 131 reset_seeprom(struct seeprom_descriptor *sd) 132 { 133 uint8_t temp; 134 135 temp = sd->sd_MS; 136 SEEPROM_OUTB(sd, temp); 137 CLOCK_PULSE(sd, sd->sd_RDY); 138 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 139 CLOCK_PULSE(sd, sd->sd_RDY); 140 SEEPROM_OUTB(sd, temp); 141 CLOCK_PULSE(sd, sd->sd_RDY); 142 } 143 144 /* 145 * Read the serial EEPROM and returns 1 if successful and 0 if 146 * not successful. 147 */ 148 int 149 ahc_read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf, 150 u_int start_addr, u_int count) 151 { 152 int i = 0; 153 u_int k = 0; 154 uint16_t v; 155 uint8_t temp; 156 157 /* 158 * Read the requested registers of the seeprom. The loop 159 * will range from 0 to count-1. 160 */ 161 for (k = start_addr; k < count + start_addr; k++) { 162 /* 163 * Now we're ready to send the read command followed by the 164 * address of the 16-bit register we want to read. 165 */ 166 send_seeprom_cmd(sd, &seeprom_read); 167 168 /* Send the 6 or 8 bit address (MSB first, LSB last). */ 169 temp = sd->sd_MS ^ sd->sd_CS; 170 for (i = (sd->sd_chip - 1); i >= 0; i--) { 171 if ((k & (1 << i)) != 0) 172 temp ^= sd->sd_DO; 173 SEEPROM_OUTB(sd, temp); 174 CLOCK_PULSE(sd, sd->sd_RDY); 175 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 176 CLOCK_PULSE(sd, sd->sd_RDY); 177 if ((k & (1 << i)) != 0) 178 temp ^= sd->sd_DO; 179 } 180 181 /* 182 * Now read the 16 bit register. An initial 0 precedes the 183 * register contents which begins with bit 15 (MSB) and ends 184 * with bit 0 (LSB). The initial 0 will be shifted off the 185 * top of our word as we let the loop run from 0 to 16. 186 */ 187 v = 0; 188 for (i = 16; i >= 0; i--) { 189 SEEPROM_OUTB(sd, temp); 190 CLOCK_PULSE(sd, sd->sd_RDY); 191 v <<= 1; 192 if (SEEPROM_DATA_INB(sd) & sd->sd_DI) 193 v |= 1; 194 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 195 CLOCK_PULSE(sd, sd->sd_RDY); 196 } 197 198 buf[k - start_addr] = v; 199 200 /* Reset the chip select for the next command cycle. */ 201 reset_seeprom(sd); 202 } 203 #ifdef AHC_DUMP_EEPROM 204 printf("\nSerial EEPROM:\n\t"); 205 for (k = 0; k < count; k = k + 1) { 206 if (((k % 8) == 0) && (k != 0)) { 207 printf ("\n\t"); 208 } 209 printf (" 0x%x", buf[k]); 210 } 211 printf ("\n"); 212 #endif 213 return (1); 214 } 215 216 /* 217 * Write the serial EEPROM and return 1 if successful and 0 if 218 * not successful. 219 */ 220 int 221 ahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf, 222 u_int start_addr, u_int count) 223 { 224 struct seeprom_cmd *ewen, *ewds; 225 uint16_t v; 226 uint8_t temp; 227 int i, k; 228 229 /* Place the chip into write-enable mode */ 230 if (sd->sd_chip == C46) { 231 ewen = &seeprom_ewen; 232 ewds = &seeprom_ewds; 233 } else if (sd->sd_chip == C56_66) { 234 ewen = &seeprom_long_ewen; 235 ewds = &seeprom_long_ewds; 236 } else { 237 printf("ahc_write_seeprom: unsupported seeprom type %d\n", 238 sd->sd_chip); 239 return (0); 240 } 241 242 send_seeprom_cmd(sd, ewen); 243 reset_seeprom(sd); 244 245 /* Write all requested data out to the seeprom. */ 246 temp = sd->sd_MS ^ sd->sd_CS; 247 for (k = start_addr; k < count + start_addr; k++) { 248 /* Send the write command */ 249 send_seeprom_cmd(sd, &seeprom_write); 250 251 /* Send the 6 or 8 bit address (MSB first). */ 252 for (i = (sd->sd_chip - 1); i >= 0; i--) { 253 if ((k & (1 << i)) != 0) 254 temp ^= sd->sd_DO; 255 SEEPROM_OUTB(sd, temp); 256 CLOCK_PULSE(sd, sd->sd_RDY); 257 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 258 CLOCK_PULSE(sd, sd->sd_RDY); 259 if ((k & (1 << i)) != 0) 260 temp ^= sd->sd_DO; 261 } 262 263 /* Write the 16 bit value, MSB first */ 264 v = buf[k - start_addr]; 265 for (i = 15; i >= 0; i--) { 266 if ((v & (1 << i)) != 0) 267 temp ^= sd->sd_DO; 268 SEEPROM_OUTB(sd, temp); 269 CLOCK_PULSE(sd, sd->sd_RDY); 270 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 271 CLOCK_PULSE(sd, sd->sd_RDY); 272 if ((v & (1 << i)) != 0) 273 temp ^= sd->sd_DO; 274 } 275 276 /* Wait for the chip to complete the write */ 277 temp = sd->sd_MS; 278 SEEPROM_OUTB(sd, temp); 279 CLOCK_PULSE(sd, sd->sd_RDY); 280 temp = sd->sd_MS ^ sd->sd_CS; 281 do { 282 SEEPROM_OUTB(sd, temp); 283 CLOCK_PULSE(sd, sd->sd_RDY); 284 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 285 CLOCK_PULSE(sd, sd->sd_RDY); 286 } while ((SEEPROM_DATA_INB(sd) & sd->sd_DI) == 0); 287 288 reset_seeprom(sd); 289 } 290 291 /* Put the chip back into write-protect mode */ 292 send_seeprom_cmd(sd, ewds); 293 reset_seeprom(sd); 294 295 return (1); 296 } 297 298 int 299 ahc_verify_cksum(struct seeprom_config *sc) 300 { 301 int i; 302 int maxaddr; 303 uint32_t checksum; 304 uint16_t *scarray; 305 306 maxaddr = (sizeof(*sc)/2) - 1; 307 checksum = 0; 308 scarray = (uint16_t *)sc; 309 310 for (i = 0; i < maxaddr; i++) 311 checksum = checksum + scarray[i]; 312 if (checksum == 0 313 || (checksum & 0xFFFF) != sc->checksum) { 314 return (0); 315 } else { 316 return(1); 317 } 318 } 319