1 /* 2 * DO NOT EDIT - This file is automatically generated 3 * from the following source files: 4 * 5 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $ 6 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $ 7 */ 8 9 #include <sys/cdefs.h> 10 __FBSDID("$FreeBSD$"); 11 #include <dev/aic7xxx/aic79xx_osm.h> 12 13 static ahd_reg_parse_entry_t MODE_PTR_parse_table[] = { 14 { "SRC_MODE", 0x07, 0x07 }, 15 { "DST_MODE", 0x70, 0x70 } 16 }; 17 18 int 19 ahd_mode_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 20 { 21 return (ahd_print_register(MODE_PTR_parse_table, 2, "MODE_PTR", 22 0x00, regvalue, cur_col, wrap)); 23 } 24 25 static ahd_reg_parse_entry_t INTSTAT_parse_table[] = { 26 { "SPLTINT", 0x01, 0x01 }, 27 { "CMDCMPLT", 0x02, 0x02 }, 28 { "SEQINT", 0x04, 0x04 }, 29 { "SCSIINT", 0x08, 0x08 }, 30 { "PCIINT", 0x10, 0x10 }, 31 { "SWTMINT", 0x20, 0x20 }, 32 { "BRKADRINT", 0x40, 0x40 }, 33 { "HWERRINT", 0x80, 0x80 }, 34 { "INT_PEND", 0xff, 0xff } 35 }; 36 37 int 38 ahd_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap) 39 { 40 return (ahd_print_register(INTSTAT_parse_table, 9, "INTSTAT", 41 0x01, regvalue, cur_col, wrap)); 42 } 43 44 static ahd_reg_parse_entry_t SEQINTCODE_parse_table[] = { 45 { "NO_SEQINT", 0x00, 0xff }, 46 { "BAD_PHASE", 0x01, 0xff }, 47 { "SEND_REJECT", 0x02, 0xff }, 48 { "PROTO_VIOLATION", 0x03, 0xff }, 49 { "NO_MATCH", 0x04, 0xff }, 50 { "IGN_WIDE_RES", 0x05, 0xff }, 51 { "PDATA_REINIT", 0x06, 0xff }, 52 { "HOST_MSG_LOOP", 0x07, 0xff }, 53 { "BAD_STATUS", 0x08, 0xff }, 54 { "DATA_OVERRUN", 0x09, 0xff }, 55 { "MKMSG_FAILED", 0x0a, 0xff }, 56 { "MISSED_BUSFREE", 0x0b, 0xff }, 57 { "DUMP_CARD_STATE", 0x0c, 0xff }, 58 { "ILLEGAL_PHASE", 0x0d, 0xff }, 59 { "INVALID_SEQINT", 0x0e, 0xff }, 60 { "CFG4ISTAT_INTR", 0x0f, 0xff }, 61 { "STATUS_OVERRUN", 0x10, 0xff }, 62 { "CFG4OVERRUN", 0x11, 0xff }, 63 { "ENTERING_NONPACK", 0x12, 0xff }, 64 { "TASKMGMT_FUNC_COMPLETE",0x13, 0xff }, 65 { "TASKMGMT_CMD_CMPLT_OKAY",0x14, 0xff }, 66 { "TRACEPOINT0", 0x15, 0xff }, 67 { "TRACEPOINT1", 0x16, 0xff }, 68 { "TRACEPOINT2", 0x17, 0xff }, 69 { "TRACEPOINT3", 0x18, 0xff }, 70 { "SAW_HWERR", 0x19, 0xff }, 71 { "BAD_SCB_STATUS", 0x1a, 0xff } 72 }; 73 74 int 75 ahd_seqintcode_print(u_int regvalue, u_int *cur_col, u_int wrap) 76 { 77 return (ahd_print_register(SEQINTCODE_parse_table, 27, "SEQINTCODE", 78 0x02, regvalue, cur_col, wrap)); 79 } 80 81 static ahd_reg_parse_entry_t CLRINT_parse_table[] = { 82 { "CLRSPLTINT", 0x01, 0x01 }, 83 { "CLRCMDINT", 0x02, 0x02 }, 84 { "CLRSEQINT", 0x04, 0x04 }, 85 { "CLRSCSIINT", 0x08, 0x08 }, 86 { "CLRPCIINT", 0x10, 0x10 }, 87 { "CLRSWTMINT", 0x20, 0x20 }, 88 { "CLRBRKADRINT", 0x40, 0x40 }, 89 { "CLRHWERRINT", 0x80, 0x80 } 90 }; 91 92 int 93 ahd_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap) 94 { 95 return (ahd_print_register(CLRINT_parse_table, 8, "CLRINT", 96 0x03, regvalue, cur_col, wrap)); 97 } 98 99 static ahd_reg_parse_entry_t ERROR_parse_table[] = { 100 { "DSCTMOUT", 0x02, 0x02 }, 101 { "ILLOPCODE", 0x04, 0x04 }, 102 { "SQPARERR", 0x08, 0x08 }, 103 { "DPARERR", 0x10, 0x10 }, 104 { "MPARERR", 0x20, 0x20 }, 105 { "CIOACCESFAIL", 0x40, 0x40 }, 106 { "CIOPARERR", 0x80, 0x80 } 107 }; 108 109 int 110 ahd_error_print(u_int regvalue, u_int *cur_col, u_int wrap) 111 { 112 return (ahd_print_register(ERROR_parse_table, 7, "ERROR", 113 0x04, regvalue, cur_col, wrap)); 114 } 115 116 static ahd_reg_parse_entry_t CLRERR_parse_table[] = { 117 { "CLRDSCTMOUT", 0x02, 0x02 }, 118 { "CLRILLOPCODE", 0x04, 0x04 }, 119 { "CLRSQPARERR", 0x08, 0x08 }, 120 { "CLRDPARERR", 0x10, 0x10 }, 121 { "CLRMPARERR", 0x20, 0x20 }, 122 { "CLRCIOACCESFAIL", 0x40, 0x40 }, 123 { "CLRCIOPARERR", 0x80, 0x80 } 124 }; 125 126 int 127 ahd_clrerr_print(u_int regvalue, u_int *cur_col, u_int wrap) 128 { 129 return (ahd_print_register(CLRERR_parse_table, 7, "CLRERR", 130 0x04, regvalue, cur_col, wrap)); 131 } 132 133 static ahd_reg_parse_entry_t HCNTRL_parse_table[] = { 134 { "CHIPRST", 0x01, 0x01 }, 135 { "CHIPRSTACK", 0x01, 0x01 }, 136 { "INTEN", 0x02, 0x02 }, 137 { "PAUSE", 0x04, 0x04 }, 138 { "SWTIMER_START_B", 0x08, 0x08 }, 139 { "SWINT", 0x10, 0x10 }, 140 { "POWRDN", 0x40, 0x40 }, 141 { "SEQ_RESET", 0x80, 0x80 } 142 }; 143 144 int 145 ahd_hcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap) 146 { 147 return (ahd_print_register(HCNTRL_parse_table, 8, "HCNTRL", 148 0x05, regvalue, cur_col, wrap)); 149 } 150 151 int 152 ahd_hnscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 153 { 154 return (ahd_print_register(NULL, 0, "HNSCB_QOFF", 155 0x06, regvalue, cur_col, wrap)); 156 } 157 158 int 159 ahd_hescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 160 { 161 return (ahd_print_register(NULL, 0, "HESCB_QOFF", 162 0x08, regvalue, cur_col, wrap)); 163 } 164 165 static ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = { 166 { "ENINT_COALESCE", 0x40, 0x40 }, 167 { "HOST_TQINPOS", 0x80, 0x80 } 168 }; 169 170 int 171 ahd_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap) 172 { 173 return (ahd_print_register(HS_MAILBOX_parse_table, 2, "HS_MAILBOX", 174 0x0b, regvalue, cur_col, wrap)); 175 } 176 177 static ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = { 178 { "SEQ_SPLTINT", 0x01, 0x01 }, 179 { "SEQ_PCIINT", 0x02, 0x02 }, 180 { "SEQ_SCSIINT", 0x04, 0x04 }, 181 { "SEQ_SEQINT", 0x08, 0x08 }, 182 { "SEQ_SWTMRTO", 0x10, 0x10 } 183 }; 184 185 int 186 ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap) 187 { 188 return (ahd_print_register(SEQINTSTAT_parse_table, 5, "SEQINTSTAT", 189 0x0c, regvalue, cur_col, wrap)); 190 } 191 192 static ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = { 193 { "CLRSEQ_SPLTINT", 0x01, 0x01 }, 194 { "CLRSEQ_PCIINT", 0x02, 0x02 }, 195 { "CLRSEQ_SCSIINT", 0x04, 0x04 }, 196 { "CLRSEQ_SEQINT", 0x08, 0x08 }, 197 { "CLRSEQ_SWTMRTO", 0x10, 0x10 } 198 }; 199 200 int 201 ahd_clrseqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap) 202 { 203 return (ahd_print_register(CLRSEQINTSTAT_parse_table, 5, "CLRSEQINTSTAT", 204 0x0c, regvalue, cur_col, wrap)); 205 } 206 207 int 208 ahd_swtimer_print(u_int regvalue, u_int *cur_col, u_int wrap) 209 { 210 return (ahd_print_register(NULL, 0, "SWTIMER", 211 0x0e, regvalue, cur_col, wrap)); 212 } 213 214 int 215 ahd_snscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 216 { 217 return (ahd_print_register(NULL, 0, "SNSCB_QOFF", 218 0x10, regvalue, cur_col, wrap)); 219 } 220 221 int 222 ahd_sescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 223 { 224 return (ahd_print_register(NULL, 0, "SESCB_QOFF", 225 0x12, regvalue, cur_col, wrap)); 226 } 227 228 int 229 ahd_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 230 { 231 return (ahd_print_register(NULL, 0, "SDSCB_QOFF", 232 0x14, regvalue, cur_col, wrap)); 233 } 234 235 static ahd_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = { 236 { "SCB_QSIZE_4", 0x00, 0x0f }, 237 { "SCB_QSIZE_8", 0x01, 0x0f }, 238 { "SCB_QSIZE_16", 0x02, 0x0f }, 239 { "SCB_QSIZE_32", 0x03, 0x0f }, 240 { "SCB_QSIZE_64", 0x04, 0x0f }, 241 { "SCB_QSIZE_128", 0x05, 0x0f }, 242 { "SCB_QSIZE_256", 0x06, 0x0f }, 243 { "SCB_QSIZE_512", 0x07, 0x0f }, 244 { "SCB_QSIZE_1024", 0x08, 0x0f }, 245 { "SCB_QSIZE_2048", 0x09, 0x0f }, 246 { "SCB_QSIZE_4096", 0x0a, 0x0f }, 247 { "SCB_QSIZE_8192", 0x0b, 0x0f }, 248 { "SCB_QSIZE_16384", 0x0c, 0x0f }, 249 { "SCB_QSIZE", 0x0f, 0x0f }, 250 { "HS_MAILBOX_ACT", 0x10, 0x10 }, 251 { "SDSCB_ROLLOVR", 0x20, 0x20 }, 252 { "NEW_SCB_AVAIL", 0x40, 0x40 }, 253 { "EMPTY_SCB_AVAIL", 0x80, 0x80 } 254 }; 255 256 int 257 ahd_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap) 258 { 259 return (ahd_print_register(QOFF_CTLSTA_parse_table, 18, "QOFF_CTLSTA", 260 0x16, regvalue, cur_col, wrap)); 261 } 262 263 static ahd_reg_parse_entry_t INTCTL_parse_table[] = { 264 { "SPLTINTEN", 0x01, 0x01 }, 265 { "SEQINTEN", 0x02, 0x02 }, 266 { "SCSIINTEN", 0x04, 0x04 }, 267 { "PCIINTEN", 0x08, 0x08 }, 268 { "AUTOCLRCMDINT", 0x10, 0x10 }, 269 { "SWTIMER_START", 0x20, 0x20 }, 270 { "SWTMINTEN", 0x40, 0x40 }, 271 { "SWTMINTMASK", 0x80, 0x80 } 272 }; 273 274 int 275 ahd_intctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 276 { 277 return (ahd_print_register(INTCTL_parse_table, 8, "INTCTL", 278 0x18, regvalue, cur_col, wrap)); 279 } 280 281 static ahd_reg_parse_entry_t DFCNTRL_parse_table[] = { 282 { "DIRECTIONEN", 0x01, 0x01 }, 283 { "FIFOFLUSH", 0x02, 0x02 }, 284 { "FIFOFLUSHACK", 0x02, 0x02 }, 285 { "DIRECTION", 0x04, 0x04 }, 286 { "DIRECTIONACK", 0x04, 0x04 }, 287 { "HDMAEN", 0x08, 0x08 }, 288 { "HDMAENACK", 0x08, 0x08 }, 289 { "SCSIEN", 0x20, 0x20 }, 290 { "SCSIENACK", 0x20, 0x20 }, 291 { "SCSIENWRDIS", 0x40, 0x40 }, 292 { "PRELOADEN", 0x80, 0x80 } 293 }; 294 295 int 296 ahd_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap) 297 { 298 return (ahd_print_register(DFCNTRL_parse_table, 11, "DFCNTRL", 299 0x19, regvalue, cur_col, wrap)); 300 } 301 302 static ahd_reg_parse_entry_t DSCOMMAND0_parse_table[] = { 303 { "CIOPARCKEN", 0x01, 0x01 }, 304 { "DISABLE_TWATE", 0x02, 0x02 }, 305 { "EXTREQLCK", 0x10, 0x10 }, 306 { "MPARCKEN", 0x20, 0x20 }, 307 { "DPARCKEN", 0x40, 0x40 }, 308 { "CACHETHEN", 0x80, 0x80 } 309 }; 310 311 int 312 ahd_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap) 313 { 314 return (ahd_print_register(DSCOMMAND0_parse_table, 6, "DSCOMMAND0", 315 0x19, regvalue, cur_col, wrap)); 316 } 317 318 static ahd_reg_parse_entry_t DFSTATUS_parse_table[] = { 319 { "FIFOEMP", 0x01, 0x01 }, 320 { "FIFOFULL", 0x02, 0x02 }, 321 { "DFTHRESH", 0x04, 0x04 }, 322 { "HDONE", 0x08, 0x08 }, 323 { "MREQPEND", 0x10, 0x10 }, 324 { "PKT_PRELOAD_AVAIL", 0x40, 0x40 }, 325 { "PRELOAD_AVAIL", 0x80, 0x80 } 326 }; 327 328 int 329 ahd_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap) 330 { 331 return (ahd_print_register(DFSTATUS_parse_table, 7, "DFSTATUS", 332 0x1a, regvalue, cur_col, wrap)); 333 } 334 335 static ahd_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = { 336 { "LAST_SEG_DONE", 0x01, 0x01 }, 337 { "LAST_SEG", 0x02, 0x02 }, 338 { "ODD_SEG", 0x04, 0x04 }, 339 { "SG_ADDR_MASK", 0xf8, 0xf8 } 340 }; 341 342 int 343 ahd_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap) 344 { 345 return (ahd_print_register(SG_CACHE_SHADOW_parse_table, 4, "SG_CACHE_SHADOW", 346 0x1b, regvalue, cur_col, wrap)); 347 } 348 349 static ahd_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = { 350 { "LAST_SEG", 0x02, 0x02 }, 351 { "ODD_SEG", 0x04, 0x04 }, 352 { "SG_ADDR_MASK", 0xf8, 0xf8 } 353 }; 354 355 int 356 ahd_sg_cache_pre_print(u_int regvalue, u_int *cur_col, u_int wrap) 357 { 358 return (ahd_print_register(SG_CACHE_PRE_parse_table, 3, "SG_CACHE_PRE", 359 0x1b, regvalue, cur_col, wrap)); 360 } 361 362 static ahd_reg_parse_entry_t ARBCTL_parse_table[] = { 363 { "USE_TIME", 0x07, 0x07 }, 364 { "RETRY_SWEN", 0x08, 0x08 }, 365 { "RESET_HARB", 0x80, 0x80 } 366 }; 367 368 int 369 ahd_arbctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 370 { 371 return (ahd_print_register(ARBCTL_parse_table, 3, "ARBCTL", 372 0x1b, regvalue, cur_col, wrap)); 373 } 374 375 int 376 ahd_lqin_print(u_int regvalue, u_int *cur_col, u_int wrap) 377 { 378 return (ahd_print_register(NULL, 0, "LQIN", 379 0x20, regvalue, cur_col, wrap)); 380 } 381 382 int 383 ahd_typeptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 384 { 385 return (ahd_print_register(NULL, 0, "TYPEPTR", 386 0x20, regvalue, cur_col, wrap)); 387 } 388 389 int 390 ahd_tagptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 391 { 392 return (ahd_print_register(NULL, 0, "TAGPTR", 393 0x21, regvalue, cur_col, wrap)); 394 } 395 396 int 397 ahd_lunptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 398 { 399 return (ahd_print_register(NULL, 0, "LUNPTR", 400 0x22, regvalue, cur_col, wrap)); 401 } 402 403 int 404 ahd_datalenptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 405 { 406 return (ahd_print_register(NULL, 0, "DATALENPTR", 407 0x23, regvalue, cur_col, wrap)); 408 } 409 410 int 411 ahd_statlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 412 { 413 return (ahd_print_register(NULL, 0, "STATLENPTR", 414 0x24, regvalue, cur_col, wrap)); 415 } 416 417 int 418 ahd_cmdlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 419 { 420 return (ahd_print_register(NULL, 0, "CMDLENPTR", 421 0x25, regvalue, cur_col, wrap)); 422 } 423 424 int 425 ahd_attrptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 426 { 427 return (ahd_print_register(NULL, 0, "ATTRPTR", 428 0x26, regvalue, cur_col, wrap)); 429 } 430 431 int 432 ahd_flagptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 433 { 434 return (ahd_print_register(NULL, 0, "FLAGPTR", 435 0x27, regvalue, cur_col, wrap)); 436 } 437 438 int 439 ahd_cmdptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 440 { 441 return (ahd_print_register(NULL, 0, "CMDPTR", 442 0x28, regvalue, cur_col, wrap)); 443 } 444 445 int 446 ahd_qnextptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 447 { 448 return (ahd_print_register(NULL, 0, "QNEXTPTR", 449 0x29, regvalue, cur_col, wrap)); 450 } 451 452 int 453 ahd_idptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 454 { 455 return (ahd_print_register(NULL, 0, "IDPTR", 456 0x2a, regvalue, cur_col, wrap)); 457 } 458 459 int 460 ahd_abrtbyteptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 461 { 462 return (ahd_print_register(NULL, 0, "ABRTBYTEPTR", 463 0x2b, regvalue, cur_col, wrap)); 464 } 465 466 int 467 ahd_abrtbitptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 468 { 469 return (ahd_print_register(NULL, 0, "ABRTBITPTR", 470 0x2c, regvalue, cur_col, wrap)); 471 } 472 473 int 474 ahd_maxcmdbytes_print(u_int regvalue, u_int *cur_col, u_int wrap) 475 { 476 return (ahd_print_register(NULL, 0, "MAXCMDBYTES", 477 0x2d, regvalue, cur_col, wrap)); 478 } 479 480 int 481 ahd_maxcmd2rcv_print(u_int regvalue, u_int *cur_col, u_int wrap) 482 { 483 return (ahd_print_register(NULL, 0, "MAXCMD2RCV", 484 0x2e, regvalue, cur_col, wrap)); 485 } 486 487 int 488 ahd_shortthresh_print(u_int regvalue, u_int *cur_col, u_int wrap) 489 { 490 return (ahd_print_register(NULL, 0, "SHORTTHRESH", 491 0x2f, regvalue, cur_col, wrap)); 492 } 493 494 static ahd_reg_parse_entry_t LUNLEN_parse_table[] = { 495 { "ILUNLEN", 0x0f, 0x0f }, 496 { "TLUNLEN", 0xf0, 0xf0 } 497 }; 498 499 int 500 ahd_lunlen_print(u_int regvalue, u_int *cur_col, u_int wrap) 501 { 502 return (ahd_print_register(LUNLEN_parse_table, 2, "LUNLEN", 503 0x30, regvalue, cur_col, wrap)); 504 } 505 506 int 507 ahd_cdblimit_print(u_int regvalue, u_int *cur_col, u_int wrap) 508 { 509 return (ahd_print_register(NULL, 0, "CDBLIMIT", 510 0x31, regvalue, cur_col, wrap)); 511 } 512 513 int 514 ahd_maxcmd_print(u_int regvalue, u_int *cur_col, u_int wrap) 515 { 516 return (ahd_print_register(NULL, 0, "MAXCMD", 517 0x32, regvalue, cur_col, wrap)); 518 } 519 520 int 521 ahd_maxcmdcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 522 { 523 return (ahd_print_register(NULL, 0, "MAXCMDCNT", 524 0x33, regvalue, cur_col, wrap)); 525 } 526 527 int 528 ahd_lqrsvd01_print(u_int regvalue, u_int *cur_col, u_int wrap) 529 { 530 return (ahd_print_register(NULL, 0, "LQRSVD01", 531 0x34, regvalue, cur_col, wrap)); 532 } 533 534 int 535 ahd_lqrsvd16_print(u_int regvalue, u_int *cur_col, u_int wrap) 536 { 537 return (ahd_print_register(NULL, 0, "LQRSVD16", 538 0x35, regvalue, cur_col, wrap)); 539 } 540 541 int 542 ahd_lqrsvd17_print(u_int regvalue, u_int *cur_col, u_int wrap) 543 { 544 return (ahd_print_register(NULL, 0, "LQRSVD17", 545 0x36, regvalue, cur_col, wrap)); 546 } 547 548 int 549 ahd_cmdrsvd0_print(u_int regvalue, u_int *cur_col, u_int wrap) 550 { 551 return (ahd_print_register(NULL, 0, "CMDRSVD0", 552 0x37, regvalue, cur_col, wrap)); 553 } 554 555 static ahd_reg_parse_entry_t LQCTL0_parse_table[] = { 556 { "LQ0INITGCLT", 0x03, 0x03 }, 557 { "LQ0TARGCLT", 0x0c, 0x0c }, 558 { "LQIINITGCLT", 0x30, 0x30 }, 559 { "LQITARGCLT", 0xc0, 0xc0 } 560 }; 561 562 int 563 ahd_lqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) 564 { 565 return (ahd_print_register(LQCTL0_parse_table, 4, "LQCTL0", 566 0x38, regvalue, cur_col, wrap)); 567 } 568 569 static ahd_reg_parse_entry_t LQCTL1_parse_table[] = { 570 { "ABORTPENDING", 0x01, 0x01 }, 571 { "SINGLECMD", 0x02, 0x02 }, 572 { "PCI2PCI", 0x04, 0x04 } 573 }; 574 575 int 576 ahd_lqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) 577 { 578 return (ahd_print_register(LQCTL1_parse_table, 3, "LQCTL1", 579 0x38, regvalue, cur_col, wrap)); 580 } 581 582 static ahd_reg_parse_entry_t LQCTL2_parse_table[] = { 583 { "LQOPAUSE", 0x01, 0x01 }, 584 { "LQOTOIDLE", 0x02, 0x02 }, 585 { "LQOCONTINUE", 0x04, 0x04 }, 586 { "LQORETRY", 0x08, 0x08 }, 587 { "LQIPAUSE", 0x10, 0x10 }, 588 { "LQITOIDLE", 0x20, 0x20 }, 589 { "LQICONTINUE", 0x40, 0x40 }, 590 { "LQIRETRY", 0x80, 0x80 } 591 }; 592 593 int 594 ahd_lqctl2_print(u_int regvalue, u_int *cur_col, u_int wrap) 595 { 596 return (ahd_print_register(LQCTL2_parse_table, 8, "LQCTL2", 597 0x39, regvalue, cur_col, wrap)); 598 } 599 600 static ahd_reg_parse_entry_t SCSBIST0_parse_table[] = { 601 { "OSBISTRUN", 0x01, 0x01 }, 602 { "OSBISTDONE", 0x02, 0x02 }, 603 { "OSBISTERR", 0x04, 0x04 }, 604 { "GSBISTRUN", 0x10, 0x10 }, 605 { "GSBISTDONE", 0x20, 0x20 }, 606 { "GSBISTERR", 0x40, 0x40 } 607 }; 608 609 int 610 ahd_scsbist0_print(u_int regvalue, u_int *cur_col, u_int wrap) 611 { 612 return (ahd_print_register(SCSBIST0_parse_table, 6, "SCSBIST0", 613 0x39, regvalue, cur_col, wrap)); 614 } 615 616 static ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = { 617 { "SCSIRSTO", 0x01, 0x01 }, 618 { "FORCEBUSFREE", 0x10, 0x10 }, 619 { "ENARBO", 0x20, 0x20 }, 620 { "ENSELO", 0x40, 0x40 }, 621 { "TEMODEO", 0x80, 0x80 } 622 }; 623 624 int 625 ahd_scsiseq0_print(u_int regvalue, u_int *cur_col, u_int wrap) 626 { 627 return (ahd_print_register(SCSISEQ0_parse_table, 5, "SCSISEQ0", 628 0x3a, regvalue, cur_col, wrap)); 629 } 630 631 static ahd_reg_parse_entry_t SCSBIST1_parse_table[] = { 632 { "NTBISTRUN", 0x01, 0x01 }, 633 { "NTBISTDONE", 0x02, 0x02 }, 634 { "NTBISTERR", 0x04, 0x04 } 635 }; 636 637 int 638 ahd_scsbist1_print(u_int regvalue, u_int *cur_col, u_int wrap) 639 { 640 return (ahd_print_register(SCSBIST1_parse_table, 3, "SCSBIST1", 641 0x3a, regvalue, cur_col, wrap)); 642 } 643 644 static ahd_reg_parse_entry_t SCSISEQ1_parse_table[] = { 645 { "ALTSTIM", 0x01, 0x01 }, 646 { "ENAUTOATNP", 0x02, 0x02 }, 647 { "MANUALP", 0x0c, 0x0c }, 648 { "ENRSELI", 0x10, 0x10 }, 649 { "ENSELI", 0x20, 0x20 }, 650 { "MANUALCTL", 0x40, 0x40 } 651 }; 652 653 int 654 ahd_scsiseq1_print(u_int regvalue, u_int *cur_col, u_int wrap) 655 { 656 return (ahd_print_register(SCSISEQ1_parse_table, 6, "SCSISEQ1", 657 0x3b, regvalue, cur_col, wrap)); 658 } 659 660 int 661 ahd_businitid_print(u_int regvalue, u_int *cur_col, u_int wrap) 662 { 663 return (ahd_print_register(NULL, 0, "BUSINITID", 664 0x3c, regvalue, cur_col, wrap)); 665 } 666 667 static ahd_reg_parse_entry_t SXFRCTL0_parse_table[] = { 668 { "SPIOEN", 0x08, 0x08 }, 669 { "BIOSCANCELEN", 0x10, 0x10 }, 670 { "DFPEXP", 0x40, 0x40 }, 671 { "DFON", 0x80, 0x80 } 672 }; 673 674 int 675 ahd_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) 676 { 677 return (ahd_print_register(SXFRCTL0_parse_table, 4, "SXFRCTL0", 678 0x3c, regvalue, cur_col, wrap)); 679 } 680 681 int 682 ahd_dlcount_print(u_int regvalue, u_int *cur_col, u_int wrap) 683 { 684 return (ahd_print_register(NULL, 0, "DLCOUNT", 685 0x3c, regvalue, cur_col, wrap)); 686 } 687 688 static ahd_reg_parse_entry_t SXFRCTL1_parse_table[] = { 689 { "STPWEN", 0x01, 0x01 }, 690 { "ACTNEGEN", 0x02, 0x02 }, 691 { "ENSTIMER", 0x04, 0x04 }, 692 { "STIMESEL", 0x18, 0x18 }, 693 { "ENSPCHK", 0x20, 0x20 }, 694 { "ENSACHK", 0x40, 0x40 }, 695 { "BITBUCKET", 0x80, 0x80 } 696 }; 697 698 int 699 ahd_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) 700 { 701 return (ahd_print_register(SXFRCTL1_parse_table, 7, "SXFRCTL1", 702 0x3d, regvalue, cur_col, wrap)); 703 } 704 705 int 706 ahd_bustargid_print(u_int regvalue, u_int *cur_col, u_int wrap) 707 { 708 return (ahd_print_register(NULL, 0, "BUSTARGID", 709 0x3e, regvalue, cur_col, wrap)); 710 } 711 712 static ahd_reg_parse_entry_t SXFRCTL2_parse_table[] = { 713 { "ASU", 0x07, 0x07 }, 714 { "CMDDMAEN", 0x08, 0x08 }, 715 { "AUTORSTDIS", 0x10, 0x10 } 716 }; 717 718 int 719 ahd_sxfrctl2_print(u_int regvalue, u_int *cur_col, u_int wrap) 720 { 721 return (ahd_print_register(SXFRCTL2_parse_table, 3, "SXFRCTL2", 722 0x3e, regvalue, cur_col, wrap)); 723 } 724 725 static ahd_reg_parse_entry_t DFFSTAT_parse_table[] = { 726 { "CURRFIFO_0", 0x00, 0x03 }, 727 { "CURRFIFO_1", 0x01, 0x03 }, 728 { "CURRFIFO_NONE", 0x03, 0x03 }, 729 { "FIFO0FREE", 0x10, 0x10 }, 730 { "FIFO1FREE", 0x20, 0x20 }, 731 { "CURRFIFO", 0x03, 0x03 } 732 }; 733 734 int 735 ahd_dffstat_print(u_int regvalue, u_int *cur_col, u_int wrap) 736 { 737 return (ahd_print_register(DFFSTAT_parse_table, 6, "DFFSTAT", 738 0x3f, regvalue, cur_col, wrap)); 739 } 740 741 static ahd_reg_parse_entry_t SCSISIGO_parse_table[] = { 742 { "P_DATAOUT", 0x00, 0xe0 }, 743 { "P_DATAOUT_DT", 0x20, 0xe0 }, 744 { "P_DATAIN", 0x40, 0xe0 }, 745 { "P_DATAIN_DT", 0x60, 0xe0 }, 746 { "P_COMMAND", 0x80, 0xe0 }, 747 { "P_MESGOUT", 0xa0, 0xe0 }, 748 { "P_STATUS", 0xc0, 0xe0 }, 749 { "P_MESGIN", 0xe0, 0xe0 }, 750 { "ACKO", 0x01, 0x01 }, 751 { "REQO", 0x02, 0x02 }, 752 { "BSYO", 0x04, 0x04 }, 753 { "SELO", 0x08, 0x08 }, 754 { "ATNO", 0x10, 0x10 }, 755 { "MSGO", 0x20, 0x20 }, 756 { "IOO", 0x40, 0x40 }, 757 { "CDO", 0x80, 0x80 }, 758 { "PHASE_MASK", 0xe0, 0xe0 } 759 }; 760 761 int 762 ahd_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap) 763 { 764 return (ahd_print_register(SCSISIGO_parse_table, 17, "SCSISIGO", 765 0x40, regvalue, cur_col, wrap)); 766 } 767 768 int 769 ahd_multargid_print(u_int regvalue, u_int *cur_col, u_int wrap) 770 { 771 return (ahd_print_register(NULL, 0, "MULTARGID", 772 0x40, regvalue, cur_col, wrap)); 773 } 774 775 static ahd_reg_parse_entry_t SCSISIGI_parse_table[] = { 776 { "P_DATAOUT", 0x00, 0xe0 }, 777 { "P_DATAOUT_DT", 0x20, 0xe0 }, 778 { "P_DATAIN", 0x40, 0xe0 }, 779 { "P_DATAIN_DT", 0x60, 0xe0 }, 780 { "P_COMMAND", 0x80, 0xe0 }, 781 { "P_MESGOUT", 0xa0, 0xe0 }, 782 { "P_STATUS", 0xc0, 0xe0 }, 783 { "P_MESGIN", 0xe0, 0xe0 }, 784 { "ACKI", 0x01, 0x01 }, 785 { "REQI", 0x02, 0x02 }, 786 { "BSYI", 0x04, 0x04 }, 787 { "SELI", 0x08, 0x08 }, 788 { "ATNI", 0x10, 0x10 }, 789 { "MSGI", 0x20, 0x20 }, 790 { "IOI", 0x40, 0x40 }, 791 { "CDI", 0x80, 0x80 }, 792 { "PHASE_MASK", 0xe0, 0xe0 } 793 }; 794 795 int 796 ahd_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap) 797 { 798 return (ahd_print_register(SCSISIGI_parse_table, 17, "SCSISIGI", 799 0x41, regvalue, cur_col, wrap)); 800 } 801 802 static ahd_reg_parse_entry_t SCSIPHASE_parse_table[] = { 803 { "DATA_OUT_PHASE", 0x01, 0x03 }, 804 { "DATA_IN_PHASE", 0x02, 0x03 }, 805 { "DATA_PHASE_MASK", 0x03, 0x03 }, 806 { "MSG_OUT_PHASE", 0x04, 0x04 }, 807 { "MSG_IN_PHASE", 0x08, 0x08 }, 808 { "COMMAND_PHASE", 0x10, 0x10 }, 809 { "STATUS_PHASE", 0x20, 0x20 } 810 }; 811 812 int 813 ahd_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap) 814 { 815 return (ahd_print_register(SCSIPHASE_parse_table, 7, "SCSIPHASE", 816 0x42, regvalue, cur_col, wrap)); 817 } 818 819 int 820 ahd_scsidat0_img_print(u_int regvalue, u_int *cur_col, u_int wrap) 821 { 822 return (ahd_print_register(NULL, 0, "SCSIDAT0_IMG", 823 0x43, regvalue, cur_col, wrap)); 824 } 825 826 int 827 ahd_scsidat_print(u_int regvalue, u_int *cur_col, u_int wrap) 828 { 829 return (ahd_print_register(NULL, 0, "SCSIDAT", 830 0x44, regvalue, cur_col, wrap)); 831 } 832 833 int 834 ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap) 835 { 836 return (ahd_print_register(NULL, 0, "SCSIBUS", 837 0x46, regvalue, cur_col, wrap)); 838 } 839 840 static ahd_reg_parse_entry_t TARGIDIN_parse_table[] = { 841 { "TARGID", 0x0f, 0x0f }, 842 { "CLKOUT", 0x80, 0x80 } 843 }; 844 845 int 846 ahd_targidin_print(u_int regvalue, u_int *cur_col, u_int wrap) 847 { 848 return (ahd_print_register(TARGIDIN_parse_table, 2, "TARGIDIN", 849 0x48, regvalue, cur_col, wrap)); 850 } 851 852 static ahd_reg_parse_entry_t SELID_parse_table[] = { 853 { "ONEBIT", 0x08, 0x08 }, 854 { "SELID_MASK", 0xf0, 0xf0 } 855 }; 856 857 int 858 ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap) 859 { 860 return (ahd_print_register(SELID_parse_table, 2, "SELID", 861 0x49, regvalue, cur_col, wrap)); 862 } 863 864 static ahd_reg_parse_entry_t OPTIONMODE_parse_table[] = { 865 { "AUTO_MSGOUT_DE", 0x02, 0x02 }, 866 { "ENDGFORMCHK", 0x04, 0x04 }, 867 { "BUSFREEREV", 0x10, 0x10 }, 868 { "BIASCANCTL", 0x20, 0x20 }, 869 { "AUTOACKEN", 0x40, 0x40 }, 870 { "BIOSCANCTL", 0x80, 0x80 }, 871 { "OPTIONMODE_DEFAULTS",0x02, 0x02 } 872 }; 873 874 int 875 ahd_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap) 876 { 877 return (ahd_print_register(OPTIONMODE_parse_table, 7, "OPTIONMODE", 878 0x4a, regvalue, cur_col, wrap)); 879 } 880 881 static ahd_reg_parse_entry_t SBLKCTL_parse_table[] = { 882 { "SELWIDE", 0x02, 0x02 }, 883 { "ENAB20", 0x04, 0x04 }, 884 { "ENAB40", 0x08, 0x08 }, 885 { "DIAGLEDON", 0x40, 0x40 }, 886 { "DIAGLEDEN", 0x80, 0x80 } 887 }; 888 889 int 890 ahd_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 891 { 892 return (ahd_print_register(SBLKCTL_parse_table, 5, "SBLKCTL", 893 0x4a, regvalue, cur_col, wrap)); 894 } 895 896 static ahd_reg_parse_entry_t SIMODE0_parse_table[] = { 897 { "ENARBDO", 0x01, 0x01 }, 898 { "ENSPIORDY", 0x02, 0x02 }, 899 { "ENOVERRUN", 0x04, 0x04 }, 900 { "ENIOERR", 0x08, 0x08 }, 901 { "ENSELINGO", 0x10, 0x10 }, 902 { "ENSELDI", 0x20, 0x20 }, 903 { "ENSELDO", 0x40, 0x40 } 904 }; 905 906 int 907 ahd_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap) 908 { 909 return (ahd_print_register(SIMODE0_parse_table, 7, "SIMODE0", 910 0x4b, regvalue, cur_col, wrap)); 911 } 912 913 static ahd_reg_parse_entry_t SSTAT0_parse_table[] = { 914 { "ARBDO", 0x01, 0x01 }, 915 { "SPIORDY", 0x02, 0x02 }, 916 { "OVERRUN", 0x04, 0x04 }, 917 { "IOERR", 0x08, 0x08 }, 918 { "SELINGO", 0x10, 0x10 }, 919 { "SELDI", 0x20, 0x20 }, 920 { "SELDO", 0x40, 0x40 }, 921 { "TARGET", 0x80, 0x80 } 922 }; 923 924 int 925 ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 926 { 927 return (ahd_print_register(SSTAT0_parse_table, 8, "SSTAT0", 928 0x4b, regvalue, cur_col, wrap)); 929 } 930 931 static ahd_reg_parse_entry_t CLRSINT0_parse_table[] = { 932 { "CLRARBDO", 0x01, 0x01 }, 933 { "CLRSPIORDY", 0x02, 0x02 }, 934 { "CLROVERRUN", 0x04, 0x04 }, 935 { "CLRIOERR", 0x08, 0x08 }, 936 { "CLRSELINGO", 0x10, 0x10 }, 937 { "CLRSELDI", 0x20, 0x20 }, 938 { "CLRSELDO", 0x40, 0x40 } 939 }; 940 941 int 942 ahd_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap) 943 { 944 return (ahd_print_register(CLRSINT0_parse_table, 7, "CLRSINT0", 945 0x4b, regvalue, cur_col, wrap)); 946 } 947 948 static ahd_reg_parse_entry_t SSTAT1_parse_table[] = { 949 { "REQINIT", 0x01, 0x01 }, 950 { "STRB2FAST", 0x02, 0x02 }, 951 { "SCSIPERR", 0x04, 0x04 }, 952 { "BUSFREE", 0x08, 0x08 }, 953 { "PHASEMIS", 0x10, 0x10 }, 954 { "SCSIRSTI", 0x20, 0x20 }, 955 { "ATNTARG", 0x40, 0x40 }, 956 { "SELTO", 0x80, 0x80 } 957 }; 958 959 int 960 ahd_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 961 { 962 return (ahd_print_register(SSTAT1_parse_table, 8, "SSTAT1", 963 0x4c, regvalue, cur_col, wrap)); 964 } 965 966 static ahd_reg_parse_entry_t CLRSINT1_parse_table[] = { 967 { "CLRREQINIT", 0x01, 0x01 }, 968 { "CLRSTRB2FAST", 0x02, 0x02 }, 969 { "CLRSCSIPERR", 0x04, 0x04 }, 970 { "CLRBUSFREE", 0x08, 0x08 }, 971 { "CLRSCSIRSTI", 0x20, 0x20 }, 972 { "CLRATNO", 0x40, 0x40 }, 973 { "CLRSELTIMEO", 0x80, 0x80 } 974 }; 975 976 int 977 ahd_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap) 978 { 979 return (ahd_print_register(CLRSINT1_parse_table, 7, "CLRSINT1", 980 0x4c, regvalue, cur_col, wrap)); 981 } 982 983 static ahd_reg_parse_entry_t SSTAT2_parse_table[] = { 984 { "BUSFREE_LQO", 0x40, 0xc0 }, 985 { "BUSFREE_DFF0", 0x80, 0xc0 }, 986 { "BUSFREE_DFF1", 0xc0, 0xc0 }, 987 { "DMADONE", 0x01, 0x01 }, 988 { "SDONE", 0x02, 0x02 }, 989 { "WIDE_RES", 0x04, 0x04 }, 990 { "BSYX", 0x08, 0x08 }, 991 { "EXP_ACTIVE", 0x10, 0x10 }, 992 { "NONPACKREQ", 0x20, 0x20 }, 993 { "BUSFREETIME", 0xc0, 0xc0 } 994 }; 995 996 int 997 ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap) 998 { 999 return (ahd_print_register(SSTAT2_parse_table, 10, "SSTAT2", 1000 0x4d, regvalue, cur_col, wrap)); 1001 } 1002 1003 static ahd_reg_parse_entry_t CLRSINT2_parse_table[] = { 1004 { "CLRDMADONE", 0x01, 0x01 }, 1005 { "CLRSDONE", 0x02, 0x02 }, 1006 { "CLRWIDE_RES", 0x04, 0x04 }, 1007 { "CLRNONPACKREQ", 0x20, 0x20 } 1008 }; 1009 1010 int 1011 ahd_clrsint2_print(u_int regvalue, u_int *cur_col, u_int wrap) 1012 { 1013 return (ahd_print_register(CLRSINT2_parse_table, 4, "CLRSINT2", 1014 0x4d, regvalue, cur_col, wrap)); 1015 } 1016 1017 static ahd_reg_parse_entry_t SIMODE2_parse_table[] = { 1018 { "ENDMADONE", 0x01, 0x01 }, 1019 { "ENSDONE", 0x02, 0x02 }, 1020 { "ENWIDE_RES", 0x04, 0x04 } 1021 }; 1022 1023 int 1024 ahd_simode2_print(u_int regvalue, u_int *cur_col, u_int wrap) 1025 { 1026 return (ahd_print_register(SIMODE2_parse_table, 3, "SIMODE2", 1027 0x4d, regvalue, cur_col, wrap)); 1028 } 1029 1030 static ahd_reg_parse_entry_t PERRDIAG_parse_table[] = { 1031 { "DTERR", 0x01, 0x01 }, 1032 { "DGFORMERR", 0x02, 0x02 }, 1033 { "CRCERR", 0x04, 0x04 }, 1034 { "AIPERR", 0x08, 0x08 }, 1035 { "PARITYERR", 0x10, 0x10 }, 1036 { "PREVPHASE", 0x20, 0x20 }, 1037 { "HIPERR", 0x40, 0x40 }, 1038 { "HIZERO", 0x80, 0x80 } 1039 }; 1040 1041 int 1042 ahd_perrdiag_print(u_int regvalue, u_int *cur_col, u_int wrap) 1043 { 1044 return (ahd_print_register(PERRDIAG_parse_table, 8, "PERRDIAG", 1045 0x4e, regvalue, cur_col, wrap)); 1046 } 1047 1048 int 1049 ahd_lqistate_print(u_int regvalue, u_int *cur_col, u_int wrap) 1050 { 1051 return (ahd_print_register(NULL, 0, "LQISTATE", 1052 0x4e, regvalue, cur_col, wrap)); 1053 } 1054 1055 int 1056 ahd_soffcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1057 { 1058 return (ahd_print_register(NULL, 0, "SOFFCNT", 1059 0x4f, regvalue, cur_col, wrap)); 1060 } 1061 1062 int 1063 ahd_lqostate_print(u_int regvalue, u_int *cur_col, u_int wrap) 1064 { 1065 return (ahd_print_register(NULL, 0, "LQOSTATE", 1066 0x4f, regvalue, cur_col, wrap)); 1067 } 1068 1069 static ahd_reg_parse_entry_t LQISTAT0_parse_table[] = { 1070 { "LQIATNCMD", 0x01, 0x01 }, 1071 { "LQIATNLQ", 0x02, 0x02 }, 1072 { "LQIBADLQT", 0x04, 0x04 }, 1073 { "LQICRCT2", 0x08, 0x08 }, 1074 { "LQICRCT1", 0x10, 0x10 }, 1075 { "LQIATNQAS", 0x20, 0x20 } 1076 }; 1077 1078 int 1079 ahd_lqistat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1080 { 1081 return (ahd_print_register(LQISTAT0_parse_table, 6, "LQISTAT0", 1082 0x50, regvalue, cur_col, wrap)); 1083 } 1084 1085 static ahd_reg_parse_entry_t CLRLQIINT0_parse_table[] = { 1086 { "CLRLQIATNCMD", 0x01, 0x01 }, 1087 { "CLRLQIATNLQ", 0x02, 0x02 }, 1088 { "CLRLQIBADLQT", 0x04, 0x04 }, 1089 { "CLRLQICRCT2", 0x08, 0x08 }, 1090 { "CLRLQICRCT1", 0x10, 0x10 }, 1091 { "CLRLQIATNQAS", 0x20, 0x20 } 1092 }; 1093 1094 int 1095 ahd_clrlqiint0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1096 { 1097 return (ahd_print_register(CLRLQIINT0_parse_table, 6, "CLRLQIINT0", 1098 0x50, regvalue, cur_col, wrap)); 1099 } 1100 1101 static ahd_reg_parse_entry_t LQIMODE0_parse_table[] = { 1102 { "ENLQIATNCMD", 0x01, 0x01 }, 1103 { "ENLQIATNLQ", 0x02, 0x02 }, 1104 { "ENLQIBADLQT", 0x04, 0x04 }, 1105 { "ENLQICRCT2", 0x08, 0x08 }, 1106 { "ENLQICRCT1", 0x10, 0x10 }, 1107 { "ENLQIATNQASK", 0x20, 0x20 } 1108 }; 1109 1110 int 1111 ahd_lqimode0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1112 { 1113 return (ahd_print_register(LQIMODE0_parse_table, 6, "LQIMODE0", 1114 0x50, regvalue, cur_col, wrap)); 1115 } 1116 1117 static ahd_reg_parse_entry_t LQISTAT1_parse_table[] = { 1118 { "LQIOVERI_NLQ", 0x01, 0x01 }, 1119 { "LQIOVERI_LQ", 0x02, 0x02 }, 1120 { "LQIBADLQI", 0x04, 0x04 }, 1121 { "LQICRCI_NLQ", 0x08, 0x08 }, 1122 { "LQICRCI_LQ", 0x10, 0x10 }, 1123 { "LQIABORT", 0x20, 0x20 }, 1124 { "LQIPHASE_NLQ", 0x40, 0x40 }, 1125 { "LQIPHASE_LQ", 0x80, 0x80 } 1126 }; 1127 1128 int 1129 ahd_lqistat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1130 { 1131 return (ahd_print_register(LQISTAT1_parse_table, 8, "LQISTAT1", 1132 0x51, regvalue, cur_col, wrap)); 1133 } 1134 1135 static ahd_reg_parse_entry_t CLRLQIINT1_parse_table[] = { 1136 { "CLRLQIOVERI_NLQ", 0x01, 0x01 }, 1137 { "CLRLQIOVERI_LQ", 0x02, 0x02 }, 1138 { "CLRLQIBADLQI", 0x04, 0x04 }, 1139 { "CLRLQICRCI_NLQ", 0x08, 0x08 }, 1140 { "CLRLQICRCI_LQ", 0x10, 0x10 }, 1141 { "CLRLIQABORT", 0x20, 0x20 }, 1142 { "CLRLQIPHASE_NLQ", 0x40, 0x40 }, 1143 { "CLRLQIPHASE_LQ", 0x80, 0x80 } 1144 }; 1145 1146 int 1147 ahd_clrlqiint1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1148 { 1149 return (ahd_print_register(CLRLQIINT1_parse_table, 8, "CLRLQIINT1", 1150 0x51, regvalue, cur_col, wrap)); 1151 } 1152 1153 static ahd_reg_parse_entry_t LQIMODE1_parse_table[] = { 1154 { "ENLQIOVERI_NLQ", 0x01, 0x01 }, 1155 { "ENLQIOVERI_LQ", 0x02, 0x02 }, 1156 { "ENLQIBADLQI", 0x04, 0x04 }, 1157 { "ENLQICRCI_NLQ", 0x08, 0x08 }, 1158 { "ENLQICRCI_LQ", 0x10, 0x10 }, 1159 { "ENLIQABORT", 0x20, 0x20 }, 1160 { "ENLQIPHASE_NLQ", 0x40, 0x40 }, 1161 { "ENLQIPHASE_LQ", 0x80, 0x80 } 1162 }; 1163 1164 int 1165 ahd_lqimode1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1166 { 1167 return (ahd_print_register(LQIMODE1_parse_table, 8, "LQIMODE1", 1168 0x51, regvalue, cur_col, wrap)); 1169 } 1170 1171 static ahd_reg_parse_entry_t LQISTAT2_parse_table[] = { 1172 { "LQIGSAVAIL", 0x01, 0x01 }, 1173 { "LQISTOPCMD", 0x02, 0x02 }, 1174 { "LQISTOPLQ", 0x04, 0x04 }, 1175 { "LQISTOPPKT", 0x08, 0x08 }, 1176 { "LQIWAITFIFO", 0x10, 0x10 }, 1177 { "LQIWORKONLQ", 0x20, 0x20 }, 1178 { "LQIPHASE_OUTPKT", 0x40, 0x40 }, 1179 { "PACKETIZED", 0x80, 0x80 } 1180 }; 1181 1182 int 1183 ahd_lqistat2_print(u_int regvalue, u_int *cur_col, u_int wrap) 1184 { 1185 return (ahd_print_register(LQISTAT2_parse_table, 8, "LQISTAT2", 1186 0x52, regvalue, cur_col, wrap)); 1187 } 1188 1189 static ahd_reg_parse_entry_t SSTAT3_parse_table[] = { 1190 { "OSRAMPERR", 0x01, 0x01 }, 1191 { "NTRAMPERR", 0x02, 0x02 } 1192 }; 1193 1194 int 1195 ahd_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap) 1196 { 1197 return (ahd_print_register(SSTAT3_parse_table, 2, "SSTAT3", 1198 0x53, regvalue, cur_col, wrap)); 1199 } 1200 1201 static ahd_reg_parse_entry_t CLRSINT3_parse_table[] = { 1202 { "CLROSRAMPERR", 0x01, 0x01 }, 1203 { "CLRNTRAMPERR", 0x02, 0x02 } 1204 }; 1205 1206 int 1207 ahd_clrsint3_print(u_int regvalue, u_int *cur_col, u_int wrap) 1208 { 1209 return (ahd_print_register(CLRSINT3_parse_table, 2, "CLRSINT3", 1210 0x53, regvalue, cur_col, wrap)); 1211 } 1212 1213 static ahd_reg_parse_entry_t SIMODE3_parse_table[] = { 1214 { "ENOSRAMPERR", 0x01, 0x01 }, 1215 { "ENNTRAMPERR", 0x02, 0x02 } 1216 }; 1217 1218 int 1219 ahd_simode3_print(u_int regvalue, u_int *cur_col, u_int wrap) 1220 { 1221 return (ahd_print_register(SIMODE3_parse_table, 2, "SIMODE3", 1222 0x53, regvalue, cur_col, wrap)); 1223 } 1224 1225 static ahd_reg_parse_entry_t LQOMODE0_parse_table[] = { 1226 { "ENLQOTCRC", 0x01, 0x01 }, 1227 { "ENLQOATNPKT", 0x02, 0x02 }, 1228 { "ENLQOATNLQ", 0x04, 0x04 }, 1229 { "ENLQOSTOPT2", 0x08, 0x08 }, 1230 { "ENLQOTARGSCBPERR", 0x10, 0x10 } 1231 }; 1232 1233 int 1234 ahd_lqomode0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1235 { 1236 return (ahd_print_register(LQOMODE0_parse_table, 5, "LQOMODE0", 1237 0x54, regvalue, cur_col, wrap)); 1238 } 1239 1240 static ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = { 1241 { "LQOTCRC", 0x01, 0x01 }, 1242 { "LQOATNPKT", 0x02, 0x02 }, 1243 { "LQOATNLQ", 0x04, 0x04 }, 1244 { "LQOSTOPT2", 0x08, 0x08 }, 1245 { "LQOTARGSCBPERR", 0x10, 0x10 } 1246 }; 1247 1248 int 1249 ahd_lqostat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1250 { 1251 return (ahd_print_register(LQOSTAT0_parse_table, 5, "LQOSTAT0", 1252 0x54, regvalue, cur_col, wrap)); 1253 } 1254 1255 static ahd_reg_parse_entry_t CLRLQOINT0_parse_table[] = { 1256 { "CLRLQOTCRC", 0x01, 0x01 }, 1257 { "CLRLQOATNPKT", 0x02, 0x02 }, 1258 { "CLRLQOATNLQ", 0x04, 0x04 }, 1259 { "CLRLQOSTOPT2", 0x08, 0x08 }, 1260 { "CLRLQOTARGSCBPERR", 0x10, 0x10 } 1261 }; 1262 1263 int 1264 ahd_clrlqoint0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1265 { 1266 return (ahd_print_register(CLRLQOINT0_parse_table, 5, "CLRLQOINT0", 1267 0x54, regvalue, cur_col, wrap)); 1268 } 1269 1270 static ahd_reg_parse_entry_t LQOMODE1_parse_table[] = { 1271 { "ENLQOPHACHGINPKT", 0x01, 0x01 }, 1272 { "ENLQOBUSFREE", 0x02, 0x02 }, 1273 { "ENLQOBADQAS", 0x04, 0x04 }, 1274 { "ENLQOSTOPI2", 0x08, 0x08 }, 1275 { "ENLQOINITSCBPERR", 0x10, 0x10 } 1276 }; 1277 1278 int 1279 ahd_lqomode1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1280 { 1281 return (ahd_print_register(LQOMODE1_parse_table, 5, "LQOMODE1", 1282 0x55, regvalue, cur_col, wrap)); 1283 } 1284 1285 static ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = { 1286 { "LQOPHACHGINPKT", 0x01, 0x01 }, 1287 { "LQOBUSFREE", 0x02, 0x02 }, 1288 { "LQOBADQAS", 0x04, 0x04 }, 1289 { "LQOSTOPI2", 0x08, 0x08 }, 1290 { "LQOINITSCBPERR", 0x10, 0x10 } 1291 }; 1292 1293 int 1294 ahd_lqostat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1295 { 1296 return (ahd_print_register(LQOSTAT1_parse_table, 5, "LQOSTAT1", 1297 0x55, regvalue, cur_col, wrap)); 1298 } 1299 1300 static ahd_reg_parse_entry_t CLRLQOINT1_parse_table[] = { 1301 { "CLRLQOPHACHGINPKT", 0x01, 0x01 }, 1302 { "CLRLQOBUSFREE", 0x02, 0x02 }, 1303 { "CLRLQOBADQAS", 0x04, 0x04 }, 1304 { "CLRLQOSTOPI2", 0x08, 0x08 }, 1305 { "CLRLQOINITSCBPERR", 0x10, 0x10 } 1306 }; 1307 1308 int 1309 ahd_clrlqoint1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1310 { 1311 return (ahd_print_register(CLRLQOINT1_parse_table, 5, "CLRLQOINT1", 1312 0x55, regvalue, cur_col, wrap)); 1313 } 1314 1315 int 1316 ahd_os_space_cnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1317 { 1318 return (ahd_print_register(NULL, 0, "OS_SPACE_CNT", 1319 0x56, regvalue, cur_col, wrap)); 1320 } 1321 1322 static ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = { 1323 { "LQOSTOP0", 0x01, 0x01 }, 1324 { "LQOPHACHGOUTPKT", 0x02, 0x02 }, 1325 { "LQOWAITFIFO", 0x10, 0x10 }, 1326 { "LQOPKT", 0xe0, 0xe0 } 1327 }; 1328 1329 int 1330 ahd_lqostat2_print(u_int regvalue, u_int *cur_col, u_int wrap) 1331 { 1332 return (ahd_print_register(LQOSTAT2_parse_table, 4, "LQOSTAT2", 1333 0x56, regvalue, cur_col, wrap)); 1334 } 1335 1336 static ahd_reg_parse_entry_t SIMODE1_parse_table[] = { 1337 { "ENREQINIT", 0x01, 0x01 }, 1338 { "ENSTRB2FAST", 0x02, 0x02 }, 1339 { "ENSCSIPERR", 0x04, 0x04 }, 1340 { "ENBUSFREE", 0x08, 0x08 }, 1341 { "ENPHASEMIS", 0x10, 0x10 }, 1342 { "ENSCSIRST", 0x20, 0x20 }, 1343 { "ENATNTARG", 0x40, 0x40 }, 1344 { "ENSELTIMO", 0x80, 0x80 } 1345 }; 1346 1347 int 1348 ahd_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1349 { 1350 return (ahd_print_register(SIMODE1_parse_table, 8, "SIMODE1", 1351 0x57, regvalue, cur_col, wrap)); 1352 } 1353 1354 int 1355 ahd_gsfifo_print(u_int regvalue, u_int *cur_col, u_int wrap) 1356 { 1357 return (ahd_print_register(NULL, 0, "GSFIFO", 1358 0x58, regvalue, cur_col, wrap)); 1359 } 1360 1361 static ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = { 1362 { "RSTCHN", 0x01, 0x01 }, 1363 { "CLRCHN", 0x02, 0x02 }, 1364 { "CLRSHCNT", 0x04, 0x04 }, 1365 { "DFFBITBUCKET", 0x08, 0x08 } 1366 }; 1367 1368 int 1369 ahd_dffsxfrctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1370 { 1371 return (ahd_print_register(DFFSXFRCTL_parse_table, 4, "DFFSXFRCTL", 1372 0x5a, regvalue, cur_col, wrap)); 1373 } 1374 1375 int 1376 ahd_nextscb_print(u_int regvalue, u_int *cur_col, u_int wrap) 1377 { 1378 return (ahd_print_register(NULL, 0, "NEXTSCB", 1379 0x5a, regvalue, cur_col, wrap)); 1380 } 1381 1382 static ahd_reg_parse_entry_t LQOSCSCTL_parse_table[] = { 1383 { "LQONOCHKOVER", 0x01, 0x01 }, 1384 { "LQOH2A_VERSION", 0x80, 0x80 } 1385 }; 1386 1387 int 1388 ahd_lqoscsctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1389 { 1390 return (ahd_print_register(LQOSCSCTL_parse_table, 2, "LQOSCSCTL", 1391 0x5a, regvalue, cur_col, wrap)); 1392 } 1393 1394 static ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = { 1395 { "CFG4TCMD", 0x01, 0x01 }, 1396 { "CFG4ICMD", 0x02, 0x02 }, 1397 { "CFG4TSTAT", 0x04, 0x04 }, 1398 { "CFG4ISTAT", 0x08, 0x08 }, 1399 { "CFG4DATA", 0x10, 0x10 }, 1400 { "SAVEPTRS", 0x20, 0x20 }, 1401 { "CTXTDONE", 0x40, 0x40 } 1402 }; 1403 1404 int 1405 ahd_seqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap) 1406 { 1407 return (ahd_print_register(SEQINTSRC_parse_table, 7, "SEQINTSRC", 1408 0x5b, regvalue, cur_col, wrap)); 1409 } 1410 1411 static ahd_reg_parse_entry_t CLRSEQINTSRC_parse_table[] = { 1412 { "CLRCFG4TCMD", 0x01, 0x01 }, 1413 { "CLRCFG4ICMD", 0x02, 0x02 }, 1414 { "CLRCFG4TSTAT", 0x04, 0x04 }, 1415 { "CLRCFG4ISTAT", 0x08, 0x08 }, 1416 { "CLRCFG4DATA", 0x10, 0x10 }, 1417 { "CLRSAVEPTRS", 0x20, 0x20 }, 1418 { "CLRCTXTDONE", 0x40, 0x40 } 1419 }; 1420 1421 int 1422 ahd_clrseqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap) 1423 { 1424 return (ahd_print_register(CLRSEQINTSRC_parse_table, 7, "CLRSEQINTSRC", 1425 0x5b, regvalue, cur_col, wrap)); 1426 } 1427 1428 int 1429 ahd_currscb_print(u_int regvalue, u_int *cur_col, u_int wrap) 1430 { 1431 return (ahd_print_register(NULL, 0, "CURRSCB", 1432 0x5c, regvalue, cur_col, wrap)); 1433 } 1434 1435 static ahd_reg_parse_entry_t SEQIMODE_parse_table[] = { 1436 { "ENCFG4TCMD", 0x01, 0x01 }, 1437 { "ENCFG4ICMD", 0x02, 0x02 }, 1438 { "ENCFG4TSTAT", 0x04, 0x04 }, 1439 { "ENCFG4ISTAT", 0x08, 0x08 }, 1440 { "ENCFG4DATA", 0x10, 0x10 }, 1441 { "ENSAVEPTRS", 0x20, 0x20 }, 1442 { "ENCTXTDONE", 0x40, 0x40 } 1443 }; 1444 1445 int 1446 ahd_seqimode_print(u_int regvalue, u_int *cur_col, u_int wrap) 1447 { 1448 return (ahd_print_register(SEQIMODE_parse_table, 7, "SEQIMODE", 1449 0x5c, regvalue, cur_col, wrap)); 1450 } 1451 1452 static ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = { 1453 { "FIFOFREE", 0x01, 0x01 }, 1454 { "DATAINFIFO", 0x02, 0x02 }, 1455 { "DLZERO", 0x04, 0x04 }, 1456 { "SHVALID", 0x08, 0x08 }, 1457 { "LASTSDONE", 0x10, 0x10 }, 1458 { "SHCNTMINUS1", 0x20, 0x20 }, 1459 { "SHCNTNEGATIVE", 0x40, 0x40 } 1460 }; 1461 1462 int 1463 ahd_mdffstat_print(u_int regvalue, u_int *cur_col, u_int wrap) 1464 { 1465 return (ahd_print_register(MDFFSTAT_parse_table, 7, "MDFFSTAT", 1466 0x5d, regvalue, cur_col, wrap)); 1467 } 1468 1469 static ahd_reg_parse_entry_t CRCCONTROL_parse_table[] = { 1470 { "CRCVALCHKEN", 0x40, 0x40 } 1471 }; 1472 1473 int 1474 ahd_crccontrol_print(u_int regvalue, u_int *cur_col, u_int wrap) 1475 { 1476 return (ahd_print_register(CRCCONTROL_parse_table, 1, "CRCCONTROL", 1477 0x5d, regvalue, cur_col, wrap)); 1478 } 1479 1480 static ahd_reg_parse_entry_t SCSITEST_parse_table[] = { 1481 { "SEL_TXPLL_DEBUG", 0x04, 0x04 }, 1482 { "CNTRTEST", 0x08, 0x08 } 1483 }; 1484 1485 int 1486 ahd_scsitest_print(u_int regvalue, u_int *cur_col, u_int wrap) 1487 { 1488 return (ahd_print_register(SCSITEST_parse_table, 2, "SCSITEST", 1489 0x5e, regvalue, cur_col, wrap)); 1490 } 1491 1492 int 1493 ahd_dfftag_print(u_int regvalue, u_int *cur_col, u_int wrap) 1494 { 1495 return (ahd_print_register(NULL, 0, "DFFTAG", 1496 0x5e, regvalue, cur_col, wrap)); 1497 } 1498 1499 int 1500 ahd_lastscb_print(u_int regvalue, u_int *cur_col, u_int wrap) 1501 { 1502 return (ahd_print_register(NULL, 0, "LASTSCB", 1503 0x5e, regvalue, cur_col, wrap)); 1504 } 1505 1506 static ahd_reg_parse_entry_t IOPDNCTL_parse_table[] = { 1507 { "PDN_DIFFSENSE", 0x01, 0x01 }, 1508 { "PDN_IDIST", 0x04, 0x04 }, 1509 { "DISABLE_OE", 0x80, 0x80 } 1510 }; 1511 1512 int 1513 ahd_iopdnctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1514 { 1515 return (ahd_print_register(IOPDNCTL_parse_table, 3, "IOPDNCTL", 1516 0x5f, regvalue, cur_col, wrap)); 1517 } 1518 1519 int 1520 ahd_negoaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1521 { 1522 return (ahd_print_register(NULL, 0, "NEGOADDR", 1523 0x60, regvalue, cur_col, wrap)); 1524 } 1525 1526 int 1527 ahd_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1528 { 1529 return (ahd_print_register(NULL, 0, "SHADDR", 1530 0x60, regvalue, cur_col, wrap)); 1531 } 1532 1533 int 1534 ahd_dgrpcrci_print(u_int regvalue, u_int *cur_col, u_int wrap) 1535 { 1536 return (ahd_print_register(NULL, 0, "DGRPCRCI", 1537 0x60, regvalue, cur_col, wrap)); 1538 } 1539 1540 int 1541 ahd_negperiod_print(u_int regvalue, u_int *cur_col, u_int wrap) 1542 { 1543 return (ahd_print_register(NULL, 0, "NEGPERIOD", 1544 0x61, regvalue, cur_col, wrap)); 1545 } 1546 1547 int 1548 ahd_packcrci_print(u_int regvalue, u_int *cur_col, u_int wrap) 1549 { 1550 return (ahd_print_register(NULL, 0, "PACKCRCI", 1551 0x62, regvalue, cur_col, wrap)); 1552 } 1553 1554 int 1555 ahd_negoffset_print(u_int regvalue, u_int *cur_col, u_int wrap) 1556 { 1557 return (ahd_print_register(NULL, 0, "NEGOFFSET", 1558 0x62, regvalue, cur_col, wrap)); 1559 } 1560 1561 static ahd_reg_parse_entry_t NEGPPROPTS_parse_table[] = { 1562 { "PPROPT_IUT", 0x01, 0x01 }, 1563 { "PPROPT_DT", 0x02, 0x02 }, 1564 { "PPROPT_QAS", 0x04, 0x04 }, 1565 { "PPROPT_PACE", 0x08, 0x08 } 1566 }; 1567 1568 int 1569 ahd_negppropts_print(u_int regvalue, u_int *cur_col, u_int wrap) 1570 { 1571 return (ahd_print_register(NEGPPROPTS_parse_table, 4, "NEGPPROPTS", 1572 0x63, regvalue, cur_col, wrap)); 1573 } 1574 1575 static ahd_reg_parse_entry_t NEGCONOPTS_parse_table[] = { 1576 { "WIDEXFER", 0x01, 0x01 }, 1577 { "ENAUTOATNO", 0x02, 0x02 }, 1578 { "ENAUTOATNI", 0x04, 0x04 }, 1579 { "ENSLOWCRC", 0x08, 0x08 }, 1580 { "RTI_OVRDTRN", 0x10, 0x10 }, 1581 { "RTI_WRTDIS", 0x20, 0x20 }, 1582 { "ENSNAPSHOT", 0x40, 0x40 } 1583 }; 1584 1585 int 1586 ahd_negconopts_print(u_int regvalue, u_int *cur_col, u_int wrap) 1587 { 1588 return (ahd_print_register(NEGCONOPTS_parse_table, 7, "NEGCONOPTS", 1589 0x64, regvalue, cur_col, wrap)); 1590 } 1591 1592 int 1593 ahd_annexcol_print(u_int regvalue, u_int *cur_col, u_int wrap) 1594 { 1595 return (ahd_print_register(NULL, 0, "ANNEXCOL", 1596 0x65, regvalue, cur_col, wrap)); 1597 } 1598 1599 int 1600 ahd_annexdat_print(u_int regvalue, u_int *cur_col, u_int wrap) 1601 { 1602 return (ahd_print_register(NULL, 0, "ANNEXDAT", 1603 0x66, regvalue, cur_col, wrap)); 1604 } 1605 1606 static ahd_reg_parse_entry_t SCSCHKN_parse_table[] = { 1607 { "LSTSGCLRDIS", 0x01, 0x01 }, 1608 { "SHVALIDSTDIS", 0x02, 0x02 }, 1609 { "DFFACTCLR", 0x04, 0x04 }, 1610 { "SDONEMSKDIS", 0x08, 0x08 }, 1611 { "WIDERESEN", 0x10, 0x10 }, 1612 { "CURRFIFODEF", 0x20, 0x20 }, 1613 { "STSELSKIDDIS", 0x40, 0x40 } 1614 }; 1615 1616 int 1617 ahd_scschkn_print(u_int regvalue, u_int *cur_col, u_int wrap) 1618 { 1619 return (ahd_print_register(SCSCHKN_parse_table, 7, "SCSCHKN", 1620 0x66, regvalue, cur_col, wrap)); 1621 } 1622 1623 int 1624 ahd_iownid_print(u_int regvalue, u_int *cur_col, u_int wrap) 1625 { 1626 return (ahd_print_register(NULL, 0, "IOWNID", 1627 0x67, regvalue, cur_col, wrap)); 1628 } 1629 1630 int 1631 ahd_shcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1632 { 1633 return (ahd_print_register(NULL, 0, "SHCNT", 1634 0x68, regvalue, cur_col, wrap)); 1635 } 1636 1637 static ahd_reg_parse_entry_t PLL960CTL0_parse_table[] = { 1638 { "PLL_ENFBM", 0x01, 0x01 }, 1639 { "PLL_DLPF", 0x02, 0x02 }, 1640 { "PLL_ENLPF", 0x04, 0x04 }, 1641 { "PLL_ENLUD", 0x08, 0x08 }, 1642 { "PLL_NS", 0x30, 0x30 }, 1643 { "PLL_PWDN", 0x40, 0x40 }, 1644 { "PLL_VCOSEL", 0x80, 0x80 } 1645 }; 1646 1647 int 1648 ahd_pll960ctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1649 { 1650 return (ahd_print_register(PLL960CTL0_parse_table, 7, "PLL960CTL0", 1651 0x68, regvalue, cur_col, wrap)); 1652 } 1653 1654 static ahd_reg_parse_entry_t PLL960CTL1_parse_table[] = { 1655 { "PLL_RST", 0x01, 0x01 }, 1656 { "PLL_CNTCLR", 0x40, 0x40 }, 1657 { "PLL_CNTEN", 0x80, 0x80 } 1658 }; 1659 1660 int 1661 ahd_pll960ctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1662 { 1663 return (ahd_print_register(PLL960CTL1_parse_table, 3, "PLL960CTL1", 1664 0x69, regvalue, cur_col, wrap)); 1665 } 1666 1667 int 1668 ahd_townid_print(u_int regvalue, u_int *cur_col, u_int wrap) 1669 { 1670 return (ahd_print_register(NULL, 0, "TOWNID", 1671 0x69, regvalue, cur_col, wrap)); 1672 } 1673 1674 int 1675 ahd_xsig_print(u_int regvalue, u_int *cur_col, u_int wrap) 1676 { 1677 return (ahd_print_register(NULL, 0, "XSIG", 1678 0x6a, regvalue, cur_col, wrap)); 1679 } 1680 1681 int 1682 ahd_pll960cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1683 { 1684 return (ahd_print_register(NULL, 0, "PLL960CNT0", 1685 0x6a, regvalue, cur_col, wrap)); 1686 } 1687 1688 int 1689 ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap) 1690 { 1691 return (ahd_print_register(NULL, 0, "SELOID", 1692 0x6b, regvalue, cur_col, wrap)); 1693 } 1694 1695 int 1696 ahd_fairness_print(u_int regvalue, u_int *cur_col, u_int wrap) 1697 { 1698 return (ahd_print_register(NULL, 0, "FAIRNESS", 1699 0x6c, regvalue, cur_col, wrap)); 1700 } 1701 1702 static ahd_reg_parse_entry_t PLL400CTL0_parse_table[] = { 1703 { "PLL_ENFBM", 0x01, 0x01 }, 1704 { "PLL_DLPF", 0x02, 0x02 }, 1705 { "PLL_ENLPF", 0x04, 0x04 }, 1706 { "PLL_ENLUD", 0x08, 0x08 }, 1707 { "PLL_NS", 0x30, 0x30 }, 1708 { "PLL_PWDN", 0x40, 0x40 }, 1709 { "PLL_VCOSEL", 0x80, 0x80 } 1710 }; 1711 1712 int 1713 ahd_pll400ctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1714 { 1715 return (ahd_print_register(PLL400CTL0_parse_table, 7, "PLL400CTL0", 1716 0x6c, regvalue, cur_col, wrap)); 1717 } 1718 1719 static ahd_reg_parse_entry_t PLL400CTL1_parse_table[] = { 1720 { "PLL_RST", 0x01, 0x01 }, 1721 { "PLL_CNTCLR", 0x40, 0x40 }, 1722 { "PLL_CNTEN", 0x80, 0x80 } 1723 }; 1724 1725 int 1726 ahd_pll400ctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1727 { 1728 return (ahd_print_register(PLL400CTL1_parse_table, 3, "PLL400CTL1", 1729 0x6d, regvalue, cur_col, wrap)); 1730 } 1731 1732 int 1733 ahd_pll400cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1734 { 1735 return (ahd_print_register(NULL, 0, "PLL400CNT0", 1736 0x6e, regvalue, cur_col, wrap)); 1737 } 1738 1739 int 1740 ahd_unfairness_print(u_int regvalue, u_int *cur_col, u_int wrap) 1741 { 1742 return (ahd_print_register(NULL, 0, "UNFAIRNESS", 1743 0x6e, regvalue, cur_col, wrap)); 1744 } 1745 1746 int 1747 ahd_hodmaadr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1748 { 1749 return (ahd_print_register(NULL, 0, "HODMAADR", 1750 0x70, regvalue, cur_col, wrap)); 1751 } 1752 1753 int 1754 ahd_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1755 { 1756 return (ahd_print_register(NULL, 0, "HADDR", 1757 0x70, regvalue, cur_col, wrap)); 1758 } 1759 1760 static ahd_reg_parse_entry_t PLLDELAY_parse_table[] = { 1761 { "SPLIT_DROP_REQ", 0x80, 0x80 } 1762 }; 1763 1764 int 1765 ahd_plldelay_print(u_int regvalue, u_int *cur_col, u_int wrap) 1766 { 1767 return (ahd_print_register(PLLDELAY_parse_table, 1, "PLLDELAY", 1768 0x70, regvalue, cur_col, wrap)); 1769 } 1770 1771 int 1772 ahd_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1773 { 1774 return (ahd_print_register(NULL, 0, "HCNT", 1775 0x78, regvalue, cur_col, wrap)); 1776 } 1777 1778 int 1779 ahd_hodmacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1780 { 1781 return (ahd_print_register(NULL, 0, "HODMACNT", 1782 0x78, regvalue, cur_col, wrap)); 1783 } 1784 1785 int 1786 ahd_hodmaen_print(u_int regvalue, u_int *cur_col, u_int wrap) 1787 { 1788 return (ahd_print_register(NULL, 0, "HODMAEN", 1789 0x7a, regvalue, cur_col, wrap)); 1790 } 1791 1792 int 1793 ahd_scbhaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1794 { 1795 return (ahd_print_register(NULL, 0, "SCBHADDR", 1796 0x7c, regvalue, cur_col, wrap)); 1797 } 1798 1799 int 1800 ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1801 { 1802 return (ahd_print_register(NULL, 0, "SGHADDR", 1803 0x7c, regvalue, cur_col, wrap)); 1804 } 1805 1806 int 1807 ahd_scbhcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1808 { 1809 return (ahd_print_register(NULL, 0, "SCBHCNT", 1810 0x84, regvalue, cur_col, wrap)); 1811 } 1812 1813 int 1814 ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1815 { 1816 return (ahd_print_register(NULL, 0, "SGHCNT", 1817 0x84, regvalue, cur_col, wrap)); 1818 } 1819 1820 static ahd_reg_parse_entry_t DFF_THRSH_parse_table[] = { 1821 { "WR_DFTHRSH_MIN", 0x00, 0x70 }, 1822 { "RD_DFTHRSH_MIN", 0x00, 0x07 }, 1823 { "RD_DFTHRSH_25", 0x01, 0x07 }, 1824 { "RD_DFTHRSH_50", 0x02, 0x07 }, 1825 { "RD_DFTHRSH_63", 0x03, 0x07 }, 1826 { "RD_DFTHRSH_75", 0x04, 0x07 }, 1827 { "RD_DFTHRSH_85", 0x05, 0x07 }, 1828 { "RD_DFTHRSH_90", 0x06, 0x07 }, 1829 { "RD_DFTHRSH_MAX", 0x07, 0x07 }, 1830 { "WR_DFTHRSH_25", 0x10, 0x70 }, 1831 { "WR_DFTHRSH_50", 0x20, 0x70 }, 1832 { "WR_DFTHRSH_63", 0x30, 0x70 }, 1833 { "WR_DFTHRSH_75", 0x40, 0x70 }, 1834 { "WR_DFTHRSH_85", 0x50, 0x70 }, 1835 { "WR_DFTHRSH_90", 0x60, 0x70 }, 1836 { "WR_DFTHRSH_MAX", 0x70, 0x70 }, 1837 { "RD_DFTHRSH", 0x07, 0x07 }, 1838 { "WR_DFTHRSH", 0x70, 0x70 } 1839 }; 1840 1841 int 1842 ahd_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap) 1843 { 1844 return (ahd_print_register(DFF_THRSH_parse_table, 18, "DFF_THRSH", 1845 0x88, regvalue, cur_col, wrap)); 1846 } 1847 1848 int 1849 ahd_romaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1850 { 1851 return (ahd_print_register(NULL, 0, "ROMADDR", 1852 0x8a, regvalue, cur_col, wrap)); 1853 } 1854 1855 static ahd_reg_parse_entry_t ROMCNTRL_parse_table[] = { 1856 { "RDY", 0x01, 0x01 }, 1857 { "REPEAT", 0x02, 0x02 }, 1858 { "ROMSPD", 0x18, 0x18 }, 1859 { "ROMOP", 0xe0, 0xe0 } 1860 }; 1861 1862 int 1863 ahd_romcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1864 { 1865 return (ahd_print_register(ROMCNTRL_parse_table, 4, "ROMCNTRL", 1866 0x8d, regvalue, cur_col, wrap)); 1867 } 1868 1869 int 1870 ahd_romdata_print(u_int regvalue, u_int *cur_col, u_int wrap) 1871 { 1872 return (ahd_print_register(NULL, 0, "ROMDATA", 1873 0x8e, regvalue, cur_col, wrap)); 1874 } 1875 1876 static ahd_reg_parse_entry_t DCHRXMSG0_parse_table[] = { 1877 { "CFNUM", 0x07, 0x07 }, 1878 { "CDNUM", 0xf8, 0xf8 } 1879 }; 1880 1881 int 1882 ahd_dchrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1883 { 1884 return (ahd_print_register(DCHRXMSG0_parse_table, 2, "DCHRXMSG0", 1885 0x90, regvalue, cur_col, wrap)); 1886 } 1887 1888 static ahd_reg_parse_entry_t OVLYRXMSG0_parse_table[] = { 1889 { "CFNUM", 0x07, 0x07 }, 1890 { "CDNUM", 0xf8, 0xf8 } 1891 }; 1892 1893 int 1894 ahd_ovlyrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1895 { 1896 return (ahd_print_register(OVLYRXMSG0_parse_table, 2, "OVLYRXMSG0", 1897 0x90, regvalue, cur_col, wrap)); 1898 } 1899 1900 static ahd_reg_parse_entry_t CMCRXMSG0_parse_table[] = { 1901 { "CFNUM", 0x07, 0x07 }, 1902 { "CDNUM", 0xf8, 0xf8 } 1903 }; 1904 1905 int 1906 ahd_cmcrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1907 { 1908 return (ahd_print_register(CMCRXMSG0_parse_table, 2, "CMCRXMSG0", 1909 0x90, regvalue, cur_col, wrap)); 1910 } 1911 1912 static ahd_reg_parse_entry_t ROENABLE_parse_table[] = { 1913 { "DCH0ROEN", 0x01, 0x01 }, 1914 { "DCH1ROEN", 0x02, 0x02 }, 1915 { "SGROEN", 0x04, 0x04 }, 1916 { "CMCROEN", 0x08, 0x08 }, 1917 { "OVLYROEN", 0x10, 0x10 }, 1918 { "MSIROEN", 0x20, 0x20 } 1919 }; 1920 1921 int 1922 ahd_roenable_print(u_int regvalue, u_int *cur_col, u_int wrap) 1923 { 1924 return (ahd_print_register(ROENABLE_parse_table, 6, "ROENABLE", 1925 0x90, regvalue, cur_col, wrap)); 1926 } 1927 1928 static ahd_reg_parse_entry_t DCHRXMSG1_parse_table[] = { 1929 { "CBNUM", 0xff, 0xff } 1930 }; 1931 1932 int 1933 ahd_dchrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1934 { 1935 return (ahd_print_register(DCHRXMSG1_parse_table, 1, "DCHRXMSG1", 1936 0x91, regvalue, cur_col, wrap)); 1937 } 1938 1939 static ahd_reg_parse_entry_t OVLYRXMSG1_parse_table[] = { 1940 { "CBNUM", 0xff, 0xff } 1941 }; 1942 1943 int 1944 ahd_ovlyrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1945 { 1946 return (ahd_print_register(OVLYRXMSG1_parse_table, 1, "OVLYRXMSG1", 1947 0x91, regvalue, cur_col, wrap)); 1948 } 1949 1950 static ahd_reg_parse_entry_t CMCRXMSG1_parse_table[] = { 1951 { "CBNUM", 0xff, 0xff } 1952 }; 1953 1954 int 1955 ahd_cmcrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1956 { 1957 return (ahd_print_register(CMCRXMSG1_parse_table, 1, "CMCRXMSG1", 1958 0x91, regvalue, cur_col, wrap)); 1959 } 1960 1961 static ahd_reg_parse_entry_t NSENABLE_parse_table[] = { 1962 { "DCH0NSEN", 0x01, 0x01 }, 1963 { "DCH1NSEN", 0x02, 0x02 }, 1964 { "SGNSEN", 0x04, 0x04 }, 1965 { "CMCNSEN", 0x08, 0x08 }, 1966 { "OVLYNSEN", 0x10, 0x10 }, 1967 { "MSINSEN", 0x20, 0x20 } 1968 }; 1969 1970 int 1971 ahd_nsenable_print(u_int regvalue, u_int *cur_col, u_int wrap) 1972 { 1973 return (ahd_print_register(NSENABLE_parse_table, 6, "NSENABLE", 1974 0x91, regvalue, cur_col, wrap)); 1975 } 1976 1977 static ahd_reg_parse_entry_t DCHRXMSG2_parse_table[] = { 1978 { "MINDEX", 0xff, 0xff } 1979 }; 1980 1981 int 1982 ahd_dchrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap) 1983 { 1984 return (ahd_print_register(DCHRXMSG2_parse_table, 1, "DCHRXMSG2", 1985 0x92, regvalue, cur_col, wrap)); 1986 } 1987 1988 static ahd_reg_parse_entry_t OVLYRXMSG2_parse_table[] = { 1989 { "MINDEX", 0xff, 0xff } 1990 }; 1991 1992 int 1993 ahd_ovlyrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap) 1994 { 1995 return (ahd_print_register(OVLYRXMSG2_parse_table, 1, "OVLYRXMSG2", 1996 0x92, regvalue, cur_col, wrap)); 1997 } 1998 1999 static ahd_reg_parse_entry_t CMCRXMSG2_parse_table[] = { 2000 { "MINDEX", 0xff, 0xff } 2001 }; 2002 2003 int 2004 ahd_cmcrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap) 2005 { 2006 return (ahd_print_register(CMCRXMSG2_parse_table, 1, "CMCRXMSG2", 2007 0x92, regvalue, cur_col, wrap)); 2008 } 2009 2010 int 2011 ahd_ost_print(u_int regvalue, u_int *cur_col, u_int wrap) 2012 { 2013 return (ahd_print_register(NULL, 0, "OST", 2014 0x92, regvalue, cur_col, wrap)); 2015 } 2016 2017 static ahd_reg_parse_entry_t DCHRXMSG3_parse_table[] = { 2018 { "MCLASS", 0x0f, 0x0f } 2019 }; 2020 2021 int 2022 ahd_dchrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap) 2023 { 2024 return (ahd_print_register(DCHRXMSG3_parse_table, 1, "DCHRXMSG3", 2025 0x93, regvalue, cur_col, wrap)); 2026 } 2027 2028 static ahd_reg_parse_entry_t OVLYRXMSG3_parse_table[] = { 2029 { "MCLASS", 0x0f, 0x0f } 2030 }; 2031 2032 int 2033 ahd_ovlyrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap) 2034 { 2035 return (ahd_print_register(OVLYRXMSG3_parse_table, 1, "OVLYRXMSG3", 2036 0x93, regvalue, cur_col, wrap)); 2037 } 2038 2039 static ahd_reg_parse_entry_t CMCRXMSG3_parse_table[] = { 2040 { "MCLASS", 0x0f, 0x0f } 2041 }; 2042 2043 int 2044 ahd_cmcrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap) 2045 { 2046 return (ahd_print_register(CMCRXMSG3_parse_table, 1, "CMCRXMSG3", 2047 0x93, regvalue, cur_col, wrap)); 2048 } 2049 2050 static ahd_reg_parse_entry_t PCIXCTL_parse_table[] = { 2051 { "CMPABCDIS", 0x01, 0x01 }, 2052 { "TSCSERREN", 0x02, 0x02 }, 2053 { "SRSPDPEEN", 0x04, 0x04 }, 2054 { "SPLTSTADIS", 0x08, 0x08 }, 2055 { "SPLTSMADIS", 0x10, 0x10 }, 2056 { "UNEXPSCIEN", 0x20, 0x20 }, 2057 { "SERRPULSE", 0x80, 0x80 } 2058 }; 2059 2060 int 2061 ahd_pcixctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2062 { 2063 return (ahd_print_register(PCIXCTL_parse_table, 7, "PCIXCTL", 2064 0x93, regvalue, cur_col, wrap)); 2065 } 2066 2067 int 2068 ahd_cmcseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2069 { 2070 return (ahd_print_register(NULL, 0, "CMCSEQBCNT", 2071 0x94, regvalue, cur_col, wrap)); 2072 } 2073 2074 int 2075 ahd_dchseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2076 { 2077 return (ahd_print_register(NULL, 0, "DCHSEQBCNT", 2078 0x94, regvalue, cur_col, wrap)); 2079 } 2080 2081 int 2082 ahd_ovlyseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2083 { 2084 return (ahd_print_register(NULL, 0, "OVLYSEQBCNT", 2085 0x94, regvalue, cur_col, wrap)); 2086 } 2087 2088 static ahd_reg_parse_entry_t CMCSPLTSTAT0_parse_table[] = { 2089 { "RXSPLTRSP", 0x01, 0x01 }, 2090 { "RXSCEMSG", 0x02, 0x02 }, 2091 { "RXOVRUN", 0x04, 0x04 }, 2092 { "CNTNOTCMPLT", 0x08, 0x08 }, 2093 { "SCDATBUCKET", 0x10, 0x10 }, 2094 { "SCADERR", 0x20, 0x20 }, 2095 { "SCBCERR", 0x40, 0x40 }, 2096 { "STAETERM", 0x80, 0x80 } 2097 }; 2098 2099 int 2100 ahd_cmcspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2101 { 2102 return (ahd_print_register(CMCSPLTSTAT0_parse_table, 8, "CMCSPLTSTAT0", 2103 0x96, regvalue, cur_col, wrap)); 2104 } 2105 2106 static ahd_reg_parse_entry_t DCHSPLTSTAT0_parse_table[] = { 2107 { "RXSPLTRSP", 0x01, 0x01 }, 2108 { "RXSCEMSG", 0x02, 0x02 }, 2109 { "RXOVRUN", 0x04, 0x04 }, 2110 { "CNTNOTCMPLT", 0x08, 0x08 }, 2111 { "SCDATBUCKET", 0x10, 0x10 }, 2112 { "SCADERR", 0x20, 0x20 }, 2113 { "SCBCERR", 0x40, 0x40 }, 2114 { "STAETERM", 0x80, 0x80 } 2115 }; 2116 2117 int 2118 ahd_dchspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2119 { 2120 return (ahd_print_register(DCHSPLTSTAT0_parse_table, 8, "DCHSPLTSTAT0", 2121 0x96, regvalue, cur_col, wrap)); 2122 } 2123 2124 static ahd_reg_parse_entry_t OVLYSPLTSTAT0_parse_table[] = { 2125 { "RXSPLTRSP", 0x01, 0x01 }, 2126 { "RXSCEMSG", 0x02, 0x02 }, 2127 { "RXOVRUN", 0x04, 0x04 }, 2128 { "CNTNOTCMPLT", 0x08, 0x08 }, 2129 { "SCDATBUCKET", 0x10, 0x10 }, 2130 { "SCADERR", 0x20, 0x20 }, 2131 { "SCBCERR", 0x40, 0x40 }, 2132 { "STAETERM", 0x80, 0x80 } 2133 }; 2134 2135 int 2136 ahd_ovlyspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2137 { 2138 return (ahd_print_register(OVLYSPLTSTAT0_parse_table, 8, "OVLYSPLTSTAT0", 2139 0x96, regvalue, cur_col, wrap)); 2140 } 2141 2142 static ahd_reg_parse_entry_t CMCSPLTSTAT1_parse_table[] = { 2143 { "RXDATABUCKET", 0x01, 0x01 } 2144 }; 2145 2146 int 2147 ahd_cmcspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2148 { 2149 return (ahd_print_register(CMCSPLTSTAT1_parse_table, 1, "CMCSPLTSTAT1", 2150 0x97, regvalue, cur_col, wrap)); 2151 } 2152 2153 static ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = { 2154 { "RXDATABUCKET", 0x01, 0x01 } 2155 }; 2156 2157 int 2158 ahd_dchspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2159 { 2160 return (ahd_print_register(DCHSPLTSTAT1_parse_table, 1, "DCHSPLTSTAT1", 2161 0x97, regvalue, cur_col, wrap)); 2162 } 2163 2164 static ahd_reg_parse_entry_t OVLYSPLTSTAT1_parse_table[] = { 2165 { "RXDATABUCKET", 0x01, 0x01 } 2166 }; 2167 2168 int 2169 ahd_ovlyspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2170 { 2171 return (ahd_print_register(OVLYSPLTSTAT1_parse_table, 1, "OVLYSPLTSTAT1", 2172 0x97, regvalue, cur_col, wrap)); 2173 } 2174 2175 static ahd_reg_parse_entry_t SGRXMSG0_parse_table[] = { 2176 { "CFNUM", 0x07, 0x07 }, 2177 { "CDNUM", 0xf8, 0xf8 } 2178 }; 2179 2180 int 2181 ahd_sgrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2182 { 2183 return (ahd_print_register(SGRXMSG0_parse_table, 2, "SGRXMSG0", 2184 0x98, regvalue, cur_col, wrap)); 2185 } 2186 2187 static ahd_reg_parse_entry_t SLVSPLTOUTADR0_parse_table[] = { 2188 { "LOWER_ADDR", 0x7f, 0x7f } 2189 }; 2190 2191 int 2192 ahd_slvspltoutadr0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2193 { 2194 return (ahd_print_register(SLVSPLTOUTADR0_parse_table, 1, "SLVSPLTOUTADR0", 2195 0x98, regvalue, cur_col, wrap)); 2196 } 2197 2198 static ahd_reg_parse_entry_t SGRXMSG1_parse_table[] = { 2199 { "CBNUM", 0xff, 0xff } 2200 }; 2201 2202 int 2203 ahd_sgrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2204 { 2205 return (ahd_print_register(SGRXMSG1_parse_table, 1, "SGRXMSG1", 2206 0x99, regvalue, cur_col, wrap)); 2207 } 2208 2209 static ahd_reg_parse_entry_t SLVSPLTOUTADR1_parse_table[] = { 2210 { "REQ_FNUM", 0x07, 0x07 }, 2211 { "REQ_DNUM", 0xf8, 0xf8 } 2212 }; 2213 2214 int 2215 ahd_slvspltoutadr1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2216 { 2217 return (ahd_print_register(SLVSPLTOUTADR1_parse_table, 2, "SLVSPLTOUTADR1", 2218 0x99, regvalue, cur_col, wrap)); 2219 } 2220 2221 static ahd_reg_parse_entry_t SGRXMSG2_parse_table[] = { 2222 { "MINDEX", 0xff, 0xff } 2223 }; 2224 2225 int 2226 ahd_sgrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap) 2227 { 2228 return (ahd_print_register(SGRXMSG2_parse_table, 1, "SGRXMSG2", 2229 0x9a, regvalue, cur_col, wrap)); 2230 } 2231 2232 static ahd_reg_parse_entry_t SLVSPLTOUTADR2_parse_table[] = { 2233 { "REQ_BNUM", 0xff, 0xff } 2234 }; 2235 2236 int 2237 ahd_slvspltoutadr2_print(u_int regvalue, u_int *cur_col, u_int wrap) 2238 { 2239 return (ahd_print_register(SLVSPLTOUTADR2_parse_table, 1, "SLVSPLTOUTADR2", 2240 0x9a, regvalue, cur_col, wrap)); 2241 } 2242 2243 static ahd_reg_parse_entry_t SGRXMSG3_parse_table[] = { 2244 { "MCLASS", 0x0f, 0x0f } 2245 }; 2246 2247 int 2248 ahd_sgrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap) 2249 { 2250 return (ahd_print_register(SGRXMSG3_parse_table, 1, "SGRXMSG3", 2251 0x9b, regvalue, cur_col, wrap)); 2252 } 2253 2254 static ahd_reg_parse_entry_t SLVSPLTOUTADR3_parse_table[] = { 2255 { "RLXORD", 0x10, 0x10 }, 2256 { "TAG_NUM", 0x1f, 0x1f } 2257 }; 2258 2259 int 2260 ahd_slvspltoutadr3_print(u_int regvalue, u_int *cur_col, u_int wrap) 2261 { 2262 return (ahd_print_register(SLVSPLTOUTADR3_parse_table, 2, "SLVSPLTOUTADR3", 2263 0x9b, regvalue, cur_col, wrap)); 2264 } 2265 2266 static ahd_reg_parse_entry_t SLVSPLTOUTATTR0_parse_table[] = { 2267 { "LOWER_BCNT", 0xff, 0xff } 2268 }; 2269 2270 int 2271 ahd_slvspltoutattr0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2272 { 2273 return (ahd_print_register(SLVSPLTOUTATTR0_parse_table, 1, "SLVSPLTOUTATTR0", 2274 0x9c, regvalue, cur_col, wrap)); 2275 } 2276 2277 int 2278 ahd_sgseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2279 { 2280 return (ahd_print_register(NULL, 0, "SGSEQBCNT", 2281 0x9c, regvalue, cur_col, wrap)); 2282 } 2283 2284 static ahd_reg_parse_entry_t SLVSPLTOUTATTR1_parse_table[] = { 2285 { "CMPLT_FNUM", 0x07, 0x07 }, 2286 { "CMPLT_DNUM", 0xf8, 0xf8 } 2287 }; 2288 2289 int 2290 ahd_slvspltoutattr1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2291 { 2292 return (ahd_print_register(SLVSPLTOUTATTR1_parse_table, 2, "SLVSPLTOUTATTR1", 2293 0x9d, regvalue, cur_col, wrap)); 2294 } 2295 2296 static ahd_reg_parse_entry_t SLVSPLTOUTATTR2_parse_table[] = { 2297 { "CMPLT_BNUM", 0xff, 0xff } 2298 }; 2299 2300 int 2301 ahd_slvspltoutattr2_print(u_int regvalue, u_int *cur_col, u_int wrap) 2302 { 2303 return (ahd_print_register(SLVSPLTOUTATTR2_parse_table, 1, "SLVSPLTOUTATTR2", 2304 0x9e, regvalue, cur_col, wrap)); 2305 } 2306 2307 static ahd_reg_parse_entry_t SGSPLTSTAT0_parse_table[] = { 2308 { "RXSPLTRSP", 0x01, 0x01 }, 2309 { "RXSCEMSG", 0x02, 0x02 }, 2310 { "RXOVRUN", 0x04, 0x04 }, 2311 { "CNTNOTCMPLT", 0x08, 0x08 }, 2312 { "SCDATBUCKET", 0x10, 0x10 }, 2313 { "SCADERR", 0x20, 0x20 }, 2314 { "SCBCERR", 0x40, 0x40 }, 2315 { "STAETERM", 0x80, 0x80 } 2316 }; 2317 2318 int 2319 ahd_sgspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2320 { 2321 return (ahd_print_register(SGSPLTSTAT0_parse_table, 8, "SGSPLTSTAT0", 2322 0x9e, regvalue, cur_col, wrap)); 2323 } 2324 2325 static ahd_reg_parse_entry_t SFUNCT_parse_table[] = { 2326 { "TEST_NUM", 0x0f, 0x0f }, 2327 { "TEST_GROUP", 0xf0, 0xf0 } 2328 }; 2329 2330 int 2331 ahd_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap) 2332 { 2333 return (ahd_print_register(SFUNCT_parse_table, 2, "SFUNCT", 2334 0x9f, regvalue, cur_col, wrap)); 2335 } 2336 2337 static ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = { 2338 { "RXDATABUCKET", 0x01, 0x01 } 2339 }; 2340 2341 int 2342 ahd_sgspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2343 { 2344 return (ahd_print_register(SGSPLTSTAT1_parse_table, 1, "SGSPLTSTAT1", 2345 0x9f, regvalue, cur_col, wrap)); 2346 } 2347 2348 static ahd_reg_parse_entry_t DF0PCISTAT_parse_table[] = { 2349 { "DPR", 0x01, 0x01 }, 2350 { "TWATERR", 0x02, 0x02 }, 2351 { "RDPERR", 0x04, 0x04 }, 2352 { "SCAAPERR", 0x08, 0x08 }, 2353 { "RTA", 0x10, 0x10 }, 2354 { "RMA", 0x20, 0x20 }, 2355 { "SSE", 0x40, 0x40 }, 2356 { "DPE", 0x80, 0x80 } 2357 }; 2358 2359 int 2360 ahd_df0pcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2361 { 2362 return (ahd_print_register(DF0PCISTAT_parse_table, 8, "DF0PCISTAT", 2363 0xa0, regvalue, cur_col, wrap)); 2364 } 2365 2366 int 2367 ahd_reg0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2368 { 2369 return (ahd_print_register(NULL, 0, "REG0", 2370 0xa0, regvalue, cur_col, wrap)); 2371 } 2372 2373 static ahd_reg_parse_entry_t DF1PCISTAT_parse_table[] = { 2374 { "DPR", 0x01, 0x01 }, 2375 { "TWATERR", 0x02, 0x02 }, 2376 { "RDPERR", 0x04, 0x04 }, 2377 { "SCAAPERR", 0x08, 0x08 }, 2378 { "RTA", 0x10, 0x10 }, 2379 { "RMA", 0x20, 0x20 }, 2380 { "SSE", 0x40, 0x40 }, 2381 { "DPE", 0x80, 0x80 } 2382 }; 2383 2384 int 2385 ahd_df1pcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2386 { 2387 return (ahd_print_register(DF1PCISTAT_parse_table, 8, "DF1PCISTAT", 2388 0xa1, regvalue, cur_col, wrap)); 2389 } 2390 2391 static ahd_reg_parse_entry_t SGPCISTAT_parse_table[] = { 2392 { "DPR", 0x01, 0x01 }, 2393 { "RDPERR", 0x04, 0x04 }, 2394 { "SCAAPERR", 0x08, 0x08 }, 2395 { "RTA", 0x10, 0x10 }, 2396 { "RMA", 0x20, 0x20 }, 2397 { "SSE", 0x40, 0x40 }, 2398 { "DPE", 0x80, 0x80 } 2399 }; 2400 2401 int 2402 ahd_sgpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2403 { 2404 return (ahd_print_register(SGPCISTAT_parse_table, 7, "SGPCISTAT", 2405 0xa2, regvalue, cur_col, wrap)); 2406 } 2407 2408 int 2409 ahd_reg1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2410 { 2411 return (ahd_print_register(NULL, 0, "REG1", 2412 0xa2, regvalue, cur_col, wrap)); 2413 } 2414 2415 static ahd_reg_parse_entry_t CMCPCISTAT_parse_table[] = { 2416 { "DPR", 0x01, 0x01 }, 2417 { "TWATERR", 0x02, 0x02 }, 2418 { "RDPERR", 0x04, 0x04 }, 2419 { "SCAAPERR", 0x08, 0x08 }, 2420 { "RTA", 0x10, 0x10 }, 2421 { "RMA", 0x20, 0x20 }, 2422 { "SSE", 0x40, 0x40 }, 2423 { "DPE", 0x80, 0x80 } 2424 }; 2425 2426 int 2427 ahd_cmcpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2428 { 2429 return (ahd_print_register(CMCPCISTAT_parse_table, 8, "CMCPCISTAT", 2430 0xa3, regvalue, cur_col, wrap)); 2431 } 2432 2433 static ahd_reg_parse_entry_t OVLYPCISTAT_parse_table[] = { 2434 { "DPR", 0x01, 0x01 }, 2435 { "RDPERR", 0x04, 0x04 }, 2436 { "SCAAPERR", 0x08, 0x08 }, 2437 { "RTA", 0x10, 0x10 }, 2438 { "RMA", 0x20, 0x20 }, 2439 { "SSE", 0x40, 0x40 }, 2440 { "DPE", 0x80, 0x80 } 2441 }; 2442 2443 int 2444 ahd_ovlypcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2445 { 2446 return (ahd_print_register(OVLYPCISTAT_parse_table, 7, "OVLYPCISTAT", 2447 0xa4, regvalue, cur_col, wrap)); 2448 } 2449 2450 int 2451 ahd_reg_isr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2452 { 2453 return (ahd_print_register(NULL, 0, "REG_ISR", 2454 0xa4, regvalue, cur_col, wrap)); 2455 } 2456 2457 static ahd_reg_parse_entry_t MSIPCISTAT_parse_table[] = { 2458 { "DPR", 0x01, 0x01 }, 2459 { "TWATERR", 0x02, 0x02 }, 2460 { "CLRPENDMSI", 0x08, 0x08 }, 2461 { "RTA", 0x10, 0x10 }, 2462 { "RMA", 0x20, 0x20 }, 2463 { "SSE", 0x40, 0x40 } 2464 }; 2465 2466 int 2467 ahd_msipcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2468 { 2469 return (ahd_print_register(MSIPCISTAT_parse_table, 6, "MSIPCISTAT", 2470 0xa6, regvalue, cur_col, wrap)); 2471 } 2472 2473 static ahd_reg_parse_entry_t SG_STATE_parse_table[] = { 2474 { "SEGS_AVAIL", 0x01, 0x01 }, 2475 { "LOADING_NEEDED", 0x02, 0x02 }, 2476 { "FETCH_INPROG", 0x04, 0x04 } 2477 }; 2478 2479 int 2480 ahd_sg_state_print(u_int regvalue, u_int *cur_col, u_int wrap) 2481 { 2482 return (ahd_print_register(SG_STATE_parse_table, 3, "SG_STATE", 2483 0xa6, regvalue, cur_col, wrap)); 2484 } 2485 2486 static ahd_reg_parse_entry_t TARGPCISTAT_parse_table[] = { 2487 { "TWATERR", 0x02, 0x02 }, 2488 { "STA", 0x08, 0x08 }, 2489 { "SSE", 0x40, 0x40 }, 2490 { "DPE", 0x80, 0x80 } 2491 }; 2492 2493 int 2494 ahd_targpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2495 { 2496 return (ahd_print_register(TARGPCISTAT_parse_table, 4, "TARGPCISTAT", 2497 0xa7, regvalue, cur_col, wrap)); 2498 } 2499 2500 int 2501 ahd_data_count_odd_print(u_int regvalue, u_int *cur_col, u_int wrap) 2502 { 2503 return (ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 2504 0xa7, regvalue, cur_col, wrap)); 2505 } 2506 2507 int 2508 ahd_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2509 { 2510 return (ahd_print_register(NULL, 0, "SCBPTR", 2511 0xa8, regvalue, cur_col, wrap)); 2512 } 2513 2514 int 2515 ahd_ccscbacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2516 { 2517 return (ahd_print_register(NULL, 0, "CCSCBACNT", 2518 0xab, regvalue, cur_col, wrap)); 2519 } 2520 2521 static ahd_reg_parse_entry_t SCBAUTOPTR_parse_table[] = { 2522 { "SCBPTR_OFF", 0x07, 0x07 }, 2523 { "SCBPTR_ADDR", 0x38, 0x38 }, 2524 { "AUSCBPTR_EN", 0x80, 0x80 } 2525 }; 2526 2527 int 2528 ahd_scbautoptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2529 { 2530 return (ahd_print_register(SCBAUTOPTR_parse_table, 3, "SCBAUTOPTR", 2531 0xab, regvalue, cur_col, wrap)); 2532 } 2533 2534 int 2535 ahd_ccscbadr_bk_print(u_int regvalue, u_int *cur_col, u_int wrap) 2536 { 2537 return (ahd_print_register(NULL, 0, "CCSCBADR_BK", 2538 0xac, regvalue, cur_col, wrap)); 2539 } 2540 2541 int 2542 ahd_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2543 { 2544 return (ahd_print_register(NULL, 0, "CCSGADDR", 2545 0xac, regvalue, cur_col, wrap)); 2546 } 2547 2548 int 2549 ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2550 { 2551 return (ahd_print_register(NULL, 0, "CCSCBADDR", 2552 0xac, regvalue, cur_col, wrap)); 2553 } 2554 2555 static ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = { 2556 { "CCSCBRESET", 0x01, 0x01 }, 2557 { "CCSCBDIR", 0x04, 0x04 }, 2558 { "CCSCBEN", 0x08, 0x08 }, 2559 { "CCARREN", 0x10, 0x10 }, 2560 { "ARRDONE", 0x40, 0x40 }, 2561 { "CCSCBDONE", 0x80, 0x80 } 2562 }; 2563 2564 int 2565 ahd_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2566 { 2567 return (ahd_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL", 2568 0xad, regvalue, cur_col, wrap)); 2569 } 2570 2571 static ahd_reg_parse_entry_t CCSGCTL_parse_table[] = { 2572 { "CCSGRESET", 0x01, 0x01 }, 2573 { "SG_FETCH_REQ", 0x02, 0x02 }, 2574 { "CCSGENACK", 0x08, 0x08 }, 2575 { "SG_CACHE_AVAIL", 0x10, 0x10 }, 2576 { "CCSGDONE", 0x80, 0x80 }, 2577 { "CCSGEN", 0x0c, 0x0c } 2578 }; 2579 2580 int 2581 ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2582 { 2583 return (ahd_print_register(CCSGCTL_parse_table, 6, "CCSGCTL", 2584 0xad, regvalue, cur_col, wrap)); 2585 } 2586 2587 static ahd_reg_parse_entry_t CMC_RAMBIST_parse_table[] = { 2588 { "CMC_BUFFER_BIST_EN", 0x01, 0x01 }, 2589 { "CMC_BUFFER_BIST_FAIL",0x02, 0x02 }, 2590 { "SG_BIST_EN", 0x10, 0x10 }, 2591 { "SG_BIST_FAIL", 0x20, 0x20 }, 2592 { "SCBRAMBIST_FAIL", 0x40, 0x40 }, 2593 { "SG_ELEMENT_SIZE", 0x80, 0x80 } 2594 }; 2595 2596 int 2597 ahd_cmc_rambist_print(u_int regvalue, u_int *cur_col, u_int wrap) 2598 { 2599 return (ahd_print_register(CMC_RAMBIST_parse_table, 6, "CMC_RAMBIST", 2600 0xad, regvalue, cur_col, wrap)); 2601 } 2602 2603 int 2604 ahd_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap) 2605 { 2606 return (ahd_print_register(NULL, 0, "CCSGRAM", 2607 0xb0, regvalue, cur_col, wrap)); 2608 } 2609 2610 int 2611 ahd_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap) 2612 { 2613 return (ahd_print_register(NULL, 0, "CCSCBRAM", 2614 0xb0, regvalue, cur_col, wrap)); 2615 } 2616 2617 int 2618 ahd_flexadr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2619 { 2620 return (ahd_print_register(NULL, 0, "FLEXADR", 2621 0xb0, regvalue, cur_col, wrap)); 2622 } 2623 2624 int 2625 ahd_flexcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2626 { 2627 return (ahd_print_register(NULL, 0, "FLEXCNT", 2628 0xb3, regvalue, cur_col, wrap)); 2629 } 2630 2631 static ahd_reg_parse_entry_t FLEXDMASTAT_parse_table[] = { 2632 { "FLEXDMADONE", 0x01, 0x01 }, 2633 { "FLEXDMAERR", 0x02, 0x02 } 2634 }; 2635 2636 int 2637 ahd_flexdmastat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2638 { 2639 return (ahd_print_register(FLEXDMASTAT_parse_table, 2, "FLEXDMASTAT", 2640 0xb5, regvalue, cur_col, wrap)); 2641 } 2642 2643 int 2644 ahd_flexdata_print(u_int regvalue, u_int *cur_col, u_int wrap) 2645 { 2646 return (ahd_print_register(NULL, 0, "FLEXDATA", 2647 0xb6, regvalue, cur_col, wrap)); 2648 } 2649 2650 int 2651 ahd_brddat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2652 { 2653 return (ahd_print_register(NULL, 0, "BRDDAT", 2654 0xb8, regvalue, cur_col, wrap)); 2655 } 2656 2657 static ahd_reg_parse_entry_t BRDCTL_parse_table[] = { 2658 { "BRDSTB", 0x01, 0x01 }, 2659 { "BRDRW", 0x02, 0x02 }, 2660 { "BRDEN", 0x04, 0x04 }, 2661 { "BRDADDR", 0x38, 0x38 }, 2662 { "FLXARBREQ", 0x40, 0x40 }, 2663 { "FLXARBACK", 0x80, 0x80 } 2664 }; 2665 2666 int 2667 ahd_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2668 { 2669 return (ahd_print_register(BRDCTL_parse_table, 6, "BRDCTL", 2670 0xb9, regvalue, cur_col, wrap)); 2671 } 2672 2673 int 2674 ahd_seeadr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2675 { 2676 return (ahd_print_register(NULL, 0, "SEEADR", 2677 0xba, regvalue, cur_col, wrap)); 2678 } 2679 2680 int 2681 ahd_seedat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2682 { 2683 return (ahd_print_register(NULL, 0, "SEEDAT", 2684 0xbc, regvalue, cur_col, wrap)); 2685 } 2686 2687 static ahd_reg_parse_entry_t SEECTL_parse_table[] = { 2688 { "SEEOP_ERAL", 0x40, 0x70 }, 2689 { "SEEOP_WRITE", 0x50, 0x70 }, 2690 { "SEEOP_READ", 0x60, 0x70 }, 2691 { "SEEOP_ERASE", 0x70, 0x70 }, 2692 { "SEESTART", 0x01, 0x01 }, 2693 { "SEERST", 0x02, 0x02 }, 2694 { "SEEOPCODE", 0x70, 0x70 }, 2695 { "SEEOP_EWEN", 0x40, 0x40 }, 2696 { "SEEOP_WALL", 0x40, 0x40 }, 2697 { "SEEOP_EWDS", 0x40, 0x40 } 2698 }; 2699 2700 int 2701 ahd_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2702 { 2703 return (ahd_print_register(SEECTL_parse_table, 10, "SEECTL", 2704 0xbe, regvalue, cur_col, wrap)); 2705 } 2706 2707 static ahd_reg_parse_entry_t SEESTAT_parse_table[] = { 2708 { "SEESTART", 0x01, 0x01 }, 2709 { "SEEBUSY", 0x02, 0x02 }, 2710 { "SEEARBACK", 0x04, 0x04 }, 2711 { "LDALTID_L", 0x08, 0x08 }, 2712 { "SEEOPCODE", 0x70, 0x70 }, 2713 { "INIT_DONE", 0x80, 0x80 } 2714 }; 2715 2716 int 2717 ahd_seestat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2718 { 2719 return (ahd_print_register(SEESTAT_parse_table, 6, "SEESTAT", 2720 0xbe, regvalue, cur_col, wrap)); 2721 } 2722 2723 int 2724 ahd_scbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2725 { 2726 return (ahd_print_register(NULL, 0, "SCBCNT", 2727 0xbf, regvalue, cur_col, wrap)); 2728 } 2729 2730 static ahd_reg_parse_entry_t DSPFLTRCTL_parse_table[] = { 2731 { "DSPFCNTSEL", 0x0f, 0x0f }, 2732 { "EDGESENSE", 0x10, 0x10 }, 2733 { "FLTRDISABLE", 0x20, 0x20 } 2734 }; 2735 2736 int 2737 ahd_dspfltrctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2738 { 2739 return (ahd_print_register(DSPFLTRCTL_parse_table, 3, "DSPFLTRCTL", 2740 0xc0, regvalue, cur_col, wrap)); 2741 } 2742 2743 int 2744 ahd_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2745 { 2746 return (ahd_print_register(NULL, 0, "DFWADDR", 2747 0xc0, regvalue, cur_col, wrap)); 2748 } 2749 2750 static ahd_reg_parse_entry_t DSPDATACTL_parse_table[] = { 2751 { "XMITOFFSTDIS", 0x02, 0x02 }, 2752 { "RCVROFFSTDIS", 0x04, 0x04 }, 2753 { "DESQDIS", 0x10, 0x10 }, 2754 { "BYPASSENAB", 0x80, 0x80 } 2755 }; 2756 2757 int 2758 ahd_dspdatactl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2759 { 2760 return (ahd_print_register(DSPDATACTL_parse_table, 4, "DSPDATACTL", 2761 0xc1, regvalue, cur_col, wrap)); 2762 } 2763 2764 static ahd_reg_parse_entry_t DSPREQCTL_parse_table[] = { 2765 { "MANREQDLY", 0x3f, 0x3f }, 2766 { "MANREQCTL", 0xc0, 0xc0 } 2767 }; 2768 2769 int 2770 ahd_dspreqctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2771 { 2772 return (ahd_print_register(DSPREQCTL_parse_table, 2, "DSPREQCTL", 2773 0xc2, regvalue, cur_col, wrap)); 2774 } 2775 2776 int 2777 ahd_dfraddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2778 { 2779 return (ahd_print_register(NULL, 0, "DFRADDR", 2780 0xc2, regvalue, cur_col, wrap)); 2781 } 2782 2783 static ahd_reg_parse_entry_t DSPACKCTL_parse_table[] = { 2784 { "MANACKDLY", 0x3f, 0x3f }, 2785 { "MANACKCTL", 0xc0, 0xc0 } 2786 }; 2787 2788 int 2789 ahd_dspackctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2790 { 2791 return (ahd_print_register(DSPACKCTL_parse_table, 2, "DSPACKCTL", 2792 0xc3, regvalue, cur_col, wrap)); 2793 } 2794 2795 int 2796 ahd_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2797 { 2798 return (ahd_print_register(NULL, 0, "DFDAT", 2799 0xc4, regvalue, cur_col, wrap)); 2800 } 2801 2802 static ahd_reg_parse_entry_t DSPSELECT_parse_table[] = { 2803 { "DSPSEL", 0x1f, 0x1f }, 2804 { "AUTOINCEN", 0x80, 0x80 } 2805 }; 2806 2807 int 2808 ahd_dspselect_print(u_int regvalue, u_int *cur_col, u_int wrap) 2809 { 2810 return (ahd_print_register(DSPSELECT_parse_table, 2, "DSPSELECT", 2811 0xc4, regvalue, cur_col, wrap)); 2812 } 2813 2814 static ahd_reg_parse_entry_t WRTBIASCTL_parse_table[] = { 2815 { "XMITMANVAL", 0x3f, 0x3f }, 2816 { "AUTOXBCDIS", 0x80, 0x80 } 2817 }; 2818 2819 int 2820 ahd_wrtbiasctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2821 { 2822 return (ahd_print_register(WRTBIASCTL_parse_table, 2, "WRTBIASCTL", 2823 0xc5, regvalue, cur_col, wrap)); 2824 } 2825 2826 static ahd_reg_parse_entry_t RCVRBIOSCTL_parse_table[] = { 2827 { "RCVRMANVAL", 0x3f, 0x3f }, 2828 { "AUTORBCDIS", 0x80, 0x80 } 2829 }; 2830 2831 int 2832 ahd_rcvrbiosctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2833 { 2834 return (ahd_print_register(RCVRBIOSCTL_parse_table, 2, "RCVRBIOSCTL", 2835 0xc6, regvalue, cur_col, wrap)); 2836 } 2837 2838 int 2839 ahd_wrtbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap) 2840 { 2841 return (ahd_print_register(NULL, 0, "WRTBIASCALC", 2842 0xc7, regvalue, cur_col, wrap)); 2843 } 2844 2845 int 2846 ahd_dfptrs_print(u_int regvalue, u_int *cur_col, u_int wrap) 2847 { 2848 return (ahd_print_register(NULL, 0, "DFPTRS", 2849 0xc8, regvalue, cur_col, wrap)); 2850 } 2851 2852 int 2853 ahd_rcvrbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap) 2854 { 2855 return (ahd_print_register(NULL, 0, "RCVRBIASCALC", 2856 0xc8, regvalue, cur_col, wrap)); 2857 } 2858 2859 int 2860 ahd_dfbkptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2861 { 2862 return (ahd_print_register(NULL, 0, "DFBKPTR", 2863 0xc9, regvalue, cur_col, wrap)); 2864 } 2865 2866 int 2867 ahd_skewcalc_print(u_int regvalue, u_int *cur_col, u_int wrap) 2868 { 2869 return (ahd_print_register(NULL, 0, "SKEWCALC", 2870 0xc9, regvalue, cur_col, wrap)); 2871 } 2872 2873 static ahd_reg_parse_entry_t DFDBCTL_parse_table[] = { 2874 { "DFF_RAMBIST_EN", 0x01, 0x01 }, 2875 { "DFF_RAMBIST_DONE", 0x02, 0x02 }, 2876 { "DFF_RAMBIST_FAIL", 0x04, 0x04 }, 2877 { "DFF_DIR_ERR", 0x08, 0x08 }, 2878 { "DFF_CIO_RD_RDY", 0x10, 0x10 }, 2879 { "DFF_CIO_WR_RDY", 0x20, 0x20 } 2880 }; 2881 2882 int 2883 ahd_dfdbctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2884 { 2885 return (ahd_print_register(DFDBCTL_parse_table, 6, "DFDBCTL", 2886 0xcb, regvalue, cur_col, wrap)); 2887 } 2888 2889 int 2890 ahd_dfscnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2891 { 2892 return (ahd_print_register(NULL, 0, "DFSCNT", 2893 0xcc, regvalue, cur_col, wrap)); 2894 } 2895 2896 int 2897 ahd_dfbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2898 { 2899 return (ahd_print_register(NULL, 0, "DFBCNT", 2900 0xce, regvalue, cur_col, wrap)); 2901 } 2902 2903 int 2904 ahd_ovlyaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2905 { 2906 return (ahd_print_register(NULL, 0, "OVLYADDR", 2907 0xd4, regvalue, cur_col, wrap)); 2908 } 2909 2910 static ahd_reg_parse_entry_t SEQCTL0_parse_table[] = { 2911 { "LOADRAM", 0x01, 0x01 }, 2912 { "SEQRESET", 0x02, 0x02 }, 2913 { "STEP", 0x04, 0x04 }, 2914 { "BRKADRINTEN", 0x08, 0x08 }, 2915 { "FASTMODE", 0x10, 0x10 }, 2916 { "FAILDIS", 0x20, 0x20 }, 2917 { "PAUSEDIS", 0x40, 0x40 }, 2918 { "PERRORDIS", 0x80, 0x80 } 2919 }; 2920 2921 int 2922 ahd_seqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2923 { 2924 return (ahd_print_register(SEQCTL0_parse_table, 8, "SEQCTL0", 2925 0xd6, regvalue, cur_col, wrap)); 2926 } 2927 2928 static ahd_reg_parse_entry_t SEQCTL1_parse_table[] = { 2929 { "RAMBIST_EN", 0x01, 0x01 }, 2930 { "RAMBIST_FAIL", 0x02, 0x02 }, 2931 { "RAMBIST_DONE", 0x04, 0x04 }, 2932 { "OVRLAY_DATA_CHK", 0x08, 0x08 } 2933 }; 2934 2935 int 2936 ahd_seqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2937 { 2938 return (ahd_print_register(SEQCTL1_parse_table, 4, "SEQCTL1", 2939 0xd7, regvalue, cur_col, wrap)); 2940 } 2941 2942 static ahd_reg_parse_entry_t FLAGS_parse_table[] = { 2943 { "CARRY", 0x01, 0x01 }, 2944 { "ZERO", 0x02, 0x02 } 2945 }; 2946 2947 int 2948 ahd_flags_print(u_int regvalue, u_int *cur_col, u_int wrap) 2949 { 2950 return (ahd_print_register(FLAGS_parse_table, 2, "FLAGS", 2951 0xd8, regvalue, cur_col, wrap)); 2952 } 2953 2954 static ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = { 2955 { "IRET", 0x01, 0x01 }, 2956 { "INTMASK1", 0x02, 0x02 }, 2957 { "INTMASK2", 0x04, 0x04 }, 2958 { "SCS_SEQ_INT1M0", 0x08, 0x08 }, 2959 { "SCS_SEQ_INT1M1", 0x10, 0x10 }, 2960 { "INT1_CONTEXT", 0x20, 0x20 }, 2961 { "INTVEC1DSL", 0x80, 0x80 } 2962 }; 2963 2964 int 2965 ahd_seqintctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2966 { 2967 return (ahd_print_register(SEQINTCTL_parse_table, 7, "SEQINTCTL", 2968 0xd9, regvalue, cur_col, wrap)); 2969 } 2970 2971 int 2972 ahd_seqram_print(u_int regvalue, u_int *cur_col, u_int wrap) 2973 { 2974 return (ahd_print_register(NULL, 0, "SEQRAM", 2975 0xda, regvalue, cur_col, wrap)); 2976 } 2977 2978 int 2979 ahd_prgmcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2980 { 2981 return (ahd_print_register(NULL, 0, "PRGMCNT", 2982 0xde, regvalue, cur_col, wrap)); 2983 } 2984 2985 int 2986 ahd_accum_print(u_int regvalue, u_int *cur_col, u_int wrap) 2987 { 2988 return (ahd_print_register(NULL, 0, "ACCUM", 2989 0xe0, regvalue, cur_col, wrap)); 2990 } 2991 2992 int 2993 ahd_sindex_print(u_int regvalue, u_int *cur_col, u_int wrap) 2994 { 2995 return (ahd_print_register(NULL, 0, "SINDEX", 2996 0xe2, regvalue, cur_col, wrap)); 2997 } 2998 2999 int 3000 ahd_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap) 3001 { 3002 return (ahd_print_register(NULL, 0, "DINDEX", 3003 0xe4, regvalue, cur_col, wrap)); 3004 } 3005 3006 static ahd_reg_parse_entry_t BRKADDR1_parse_table[] = { 3007 { "BRKDIS", 0x80, 0x80 } 3008 }; 3009 3010 int 3011 ahd_brkaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap) 3012 { 3013 return (ahd_print_register(BRKADDR1_parse_table, 1, "BRKADDR1", 3014 0xe6, regvalue, cur_col, wrap)); 3015 } 3016 3017 int 3018 ahd_brkaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap) 3019 { 3020 return (ahd_print_register(NULL, 0, "BRKADDR0", 3021 0xe6, regvalue, cur_col, wrap)); 3022 } 3023 3024 int 3025 ahd_allones_print(u_int regvalue, u_int *cur_col, u_int wrap) 3026 { 3027 return (ahd_print_register(NULL, 0, "ALLONES", 3028 0xe8, regvalue, cur_col, wrap)); 3029 } 3030 3031 int 3032 ahd_none_print(u_int regvalue, u_int *cur_col, u_int wrap) 3033 { 3034 return (ahd_print_register(NULL, 0, "NONE", 3035 0xea, regvalue, cur_col, wrap)); 3036 } 3037 3038 int 3039 ahd_allzeros_print(u_int regvalue, u_int *cur_col, u_int wrap) 3040 { 3041 return (ahd_print_register(NULL, 0, "ALLZEROS", 3042 0xea, regvalue, cur_col, wrap)); 3043 } 3044 3045 int 3046 ahd_sindir_print(u_int regvalue, u_int *cur_col, u_int wrap) 3047 { 3048 return (ahd_print_register(NULL, 0, "SINDIR", 3049 0xec, regvalue, cur_col, wrap)); 3050 } 3051 3052 int 3053 ahd_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap) 3054 { 3055 return (ahd_print_register(NULL, 0, "DINDIR", 3056 0xed, regvalue, cur_col, wrap)); 3057 } 3058 3059 int 3060 ahd_function1_print(u_int regvalue, u_int *cur_col, u_int wrap) 3061 { 3062 return (ahd_print_register(NULL, 0, "FUNCTION1", 3063 0xf0, regvalue, cur_col, wrap)); 3064 } 3065 3066 int 3067 ahd_stack_print(u_int regvalue, u_int *cur_col, u_int wrap) 3068 { 3069 return (ahd_print_register(NULL, 0, "STACK", 3070 0xf2, regvalue, cur_col, wrap)); 3071 } 3072 3073 int 3074 ahd_intvec1_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3075 { 3076 return (ahd_print_register(NULL, 0, "INTVEC1_ADDR", 3077 0xf4, regvalue, cur_col, wrap)); 3078 } 3079 3080 int 3081 ahd_curaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3082 { 3083 return (ahd_print_register(NULL, 0, "CURADDR", 3084 0xf4, regvalue, cur_col, wrap)); 3085 } 3086 3087 int 3088 ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3089 { 3090 return (ahd_print_register(NULL, 0, "INTVEC2_ADDR", 3091 0xf6, regvalue, cur_col, wrap)); 3092 } 3093 3094 int 3095 ahd_lastaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3096 { 3097 return (ahd_print_register(NULL, 0, "LASTADDR", 3098 0xf6, regvalue, cur_col, wrap)); 3099 } 3100 3101 int 3102 ahd_longjmp_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3103 { 3104 return (ahd_print_register(NULL, 0, "LONGJMP_ADDR", 3105 0xf8, regvalue, cur_col, wrap)); 3106 } 3107 3108 int 3109 ahd_accum_save_print(u_int regvalue, u_int *cur_col, u_int wrap) 3110 { 3111 return (ahd_print_register(NULL, 0, "ACCUM_SAVE", 3112 0xfa, regvalue, cur_col, wrap)); 3113 } 3114 3115 int 3116 ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 3117 { 3118 return (ahd_print_register(NULL, 0, "SRAM_BASE", 3119 0x100, regvalue, cur_col, wrap)); 3120 } 3121 3122 int 3123 ahd_waiting_scb_tails_print(u_int regvalue, u_int *cur_col, u_int wrap) 3124 { 3125 return (ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 3126 0x100, regvalue, cur_col, wrap)); 3127 } 3128 3129 int 3130 ahd_ahd_pci_config_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 3131 { 3132 return (ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 3133 0x100, regvalue, cur_col, wrap)); 3134 } 3135 3136 int 3137 ahd_waiting_tid_head_print(u_int regvalue, u_int *cur_col, u_int wrap) 3138 { 3139 return (ahd_print_register(NULL, 0, "WAITING_TID_HEAD", 3140 0x120, regvalue, cur_col, wrap)); 3141 } 3142 3143 int 3144 ahd_waiting_tid_tail_print(u_int regvalue, u_int *cur_col, u_int wrap) 3145 { 3146 return (ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 3147 0x122, regvalue, cur_col, wrap)); 3148 } 3149 3150 int 3151 ahd_next_queued_scb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3152 { 3153 return (ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", 3154 0x124, regvalue, cur_col, wrap)); 3155 } 3156 3157 int 3158 ahd_complete_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap) 3159 { 3160 return (ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", 3161 0x128, regvalue, cur_col, wrap)); 3162 } 3163 3164 int 3165 ahd_complete_scb_dmainprog_head_print(u_int regvalue, u_int *cur_col, u_int wrap) 3166 { 3167 return (ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", 3168 0x12a, regvalue, cur_col, wrap)); 3169 } 3170 3171 int 3172 ahd_complete_dma_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap) 3173 { 3174 return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", 3175 0x12c, regvalue, cur_col, wrap)); 3176 } 3177 3178 int 3179 ahd_complete_dma_scb_tail_print(u_int regvalue, u_int *cur_col, u_int wrap) 3180 { 3181 return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL", 3182 0x12e, regvalue, cur_col, wrap)); 3183 } 3184 3185 int 3186 ahd_complete_on_qfreeze_head_print(u_int regvalue, u_int *cur_col, u_int wrap) 3187 { 3188 return (ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD", 3189 0x130, regvalue, cur_col, wrap)); 3190 } 3191 3192 int 3193 ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap) 3194 { 3195 return (ahd_print_register(NULL, 0, "QFREEZE_COUNT", 3196 0x132, regvalue, cur_col, wrap)); 3197 } 3198 3199 int 3200 ahd_kernel_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap) 3201 { 3202 return (ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 3203 0x134, regvalue, cur_col, wrap)); 3204 } 3205 3206 int 3207 ahd_saved_mode_print(u_int regvalue, u_int *cur_col, u_int wrap) 3208 { 3209 return (ahd_print_register(NULL, 0, "SAVED_MODE", 3210 0x136, regvalue, cur_col, wrap)); 3211 } 3212 3213 int 3214 ahd_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap) 3215 { 3216 return (ahd_print_register(NULL, 0, "MSG_OUT", 3217 0x137, regvalue, cur_col, wrap)); 3218 } 3219 3220 static ahd_reg_parse_entry_t DMAPARAMS_parse_table[] = { 3221 { "FIFORESET", 0x01, 0x01 }, 3222 { "FIFOFLUSH", 0x02, 0x02 }, 3223 { "DIRECTION", 0x04, 0x04 }, 3224 { "HDMAEN", 0x08, 0x08 }, 3225 { "HDMAENACK", 0x08, 0x08 }, 3226 { "SDMAEN", 0x10, 0x10 }, 3227 { "SDMAENACK", 0x10, 0x10 }, 3228 { "SCSIEN", 0x20, 0x20 }, 3229 { "WIDEODD", 0x40, 0x40 }, 3230 { "PRELOADEN", 0x80, 0x80 } 3231 }; 3232 3233 int 3234 ahd_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap) 3235 { 3236 return (ahd_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS", 3237 0x138, regvalue, cur_col, wrap)); 3238 } 3239 3240 static ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { 3241 { "NO_DISCONNECT", 0x01, 0x01 }, 3242 { "SPHASE_PENDING", 0x02, 0x02 }, 3243 { "DPHASE_PENDING", 0x04, 0x04 }, 3244 { "CMDPHASE_PENDING", 0x08, 0x08 }, 3245 { "TARG_CMD_PENDING", 0x10, 0x10 }, 3246 { "DPHASE", 0x20, 0x20 }, 3247 { "NO_CDB_SENT", 0x40, 0x40 }, 3248 { "TARGET_CMD_IS_TAGGED",0x40, 0x40 }, 3249 { "NOT_IDENTIFIED", 0x80, 0x80 } 3250 }; 3251 3252 int 3253 ahd_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap) 3254 { 3255 return (ahd_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS", 3256 0x139, regvalue, cur_col, wrap)); 3257 } 3258 3259 int 3260 ahd_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) 3261 { 3262 return (ahd_print_register(NULL, 0, "SAVED_SCSIID", 3263 0x13a, regvalue, cur_col, wrap)); 3264 } 3265 3266 int 3267 ahd_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap) 3268 { 3269 return (ahd_print_register(NULL, 0, "SAVED_LUN", 3270 0x13b, regvalue, cur_col, wrap)); 3271 } 3272 3273 static ahd_reg_parse_entry_t LASTPHASE_parse_table[] = { 3274 { "P_DATAOUT", 0x00, 0xe0 }, 3275 { "P_DATAOUT_DT", 0x20, 0xe0 }, 3276 { "P_DATAIN", 0x40, 0xe0 }, 3277 { "P_DATAIN_DT", 0x60, 0xe0 }, 3278 { "P_COMMAND", 0x80, 0xe0 }, 3279 { "P_MESGOUT", 0xa0, 0xe0 }, 3280 { "P_STATUS", 0xc0, 0xe0 }, 3281 { "P_MESGIN", 0xe0, 0xe0 }, 3282 { "P_BUSFREE", 0x01, 0x01 }, 3283 { "MSGI", 0x20, 0x20 }, 3284 { "IOI", 0x40, 0x40 }, 3285 { "CDI", 0x80, 0x80 }, 3286 { "PHASE_MASK", 0xe0, 0xe0 } 3287 }; 3288 3289 int 3290 ahd_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap) 3291 { 3292 return (ahd_print_register(LASTPHASE_parse_table, 13, "LASTPHASE", 3293 0x13c, regvalue, cur_col, wrap)); 3294 } 3295 3296 int 3297 ahd_qoutfifo_entry_valid_tag_print(u_int regvalue, u_int *cur_col, u_int wrap) 3298 { 3299 return (ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", 3300 0x13d, regvalue, cur_col, wrap)); 3301 } 3302 3303 int 3304 ahd_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) 3305 { 3306 return (ahd_print_register(NULL, 0, "KERNEL_TQINPOS", 3307 0x13e, regvalue, cur_col, wrap)); 3308 } 3309 3310 int 3311 ahd_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) 3312 { 3313 return (ahd_print_register(NULL, 0, "TQINPOS", 3314 0x13f, regvalue, cur_col, wrap)); 3315 } 3316 3317 int 3318 ahd_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3319 { 3320 return (ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 3321 0x140, regvalue, cur_col, wrap)); 3322 } 3323 3324 int 3325 ahd_qoutfifo_next_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3326 { 3327 return (ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", 3328 0x144, regvalue, cur_col, wrap)); 3329 } 3330 3331 static ahd_reg_parse_entry_t ARG_1_parse_table[] = { 3332 { "CONT_MSG_LOOP_TARG", 0x02, 0x02 }, 3333 { "CONT_MSG_LOOP_READ", 0x03, 0x03 }, 3334 { "CONT_MSG_LOOP_WRITE",0x04, 0x04 }, 3335 { "EXIT_MSG_LOOP", 0x08, 0x08 }, 3336 { "MSGOUT_PHASEMIS", 0x10, 0x10 }, 3337 { "SEND_REJ", 0x20, 0x20 }, 3338 { "SEND_SENSE", 0x40, 0x40 }, 3339 { "SEND_MSG", 0x80, 0x80 } 3340 }; 3341 3342 int 3343 ahd_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap) 3344 { 3345 return (ahd_print_register(ARG_1_parse_table, 8, "ARG_1", 3346 0x148, regvalue, cur_col, wrap)); 3347 } 3348 3349 int 3350 ahd_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap) 3351 { 3352 return (ahd_print_register(NULL, 0, "ARG_2", 3353 0x149, regvalue, cur_col, wrap)); 3354 } 3355 3356 int 3357 ahd_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap) 3358 { 3359 return (ahd_print_register(NULL, 0, "LAST_MSG", 3360 0x14a, regvalue, cur_col, wrap)); 3361 } 3362 3363 static ahd_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = { 3364 { "ALTSTIM", 0x01, 0x01 }, 3365 { "ENAUTOATNP", 0x02, 0x02 }, 3366 { "MANUALP", 0x0c, 0x0c }, 3367 { "ENRSELI", 0x10, 0x10 }, 3368 { "ENSELI", 0x20, 0x20 }, 3369 { "MANUALCTL", 0x40, 0x40 } 3370 }; 3371 3372 int 3373 ahd_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap) 3374 { 3375 return (ahd_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE", 3376 0x14b, regvalue, cur_col, wrap)); 3377 } 3378 3379 int 3380 ahd_initiator_tag_print(u_int regvalue, u_int *cur_col, u_int wrap) 3381 { 3382 return (ahd_print_register(NULL, 0, "INITIATOR_TAG", 3383 0x14c, regvalue, cur_col, wrap)); 3384 } 3385 3386 static ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = { 3387 { "PENDING_MK_MESSAGE", 0x01, 0x01 }, 3388 { "TARGET_MSG_PENDING", 0x02, 0x02 }, 3389 { "SELECTOUT_QFROZEN", 0x04, 0x04 } 3390 }; 3391 3392 int 3393 ahd_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap) 3394 { 3395 return (ahd_print_register(SEQ_FLAGS2_parse_table, 3, "SEQ_FLAGS2", 3396 0x14d, regvalue, cur_col, wrap)); 3397 } 3398 3399 int 3400 ahd_allocfifo_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3401 { 3402 return (ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", 3403 0x14e, regvalue, cur_col, wrap)); 3404 } 3405 3406 int 3407 ahd_int_coalescing_timer_print(u_int regvalue, u_int *cur_col, u_int wrap) 3408 { 3409 return (ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", 3410 0x150, regvalue, cur_col, wrap)); 3411 } 3412 3413 int 3414 ahd_int_coalescing_maxcmds_print(u_int regvalue, u_int *cur_col, u_int wrap) 3415 { 3416 return (ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", 3417 0x152, regvalue, cur_col, wrap)); 3418 } 3419 3420 int 3421 ahd_int_coalescing_mincmds_print(u_int regvalue, u_int *cur_col, u_int wrap) 3422 { 3423 return (ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", 3424 0x153, regvalue, cur_col, wrap)); 3425 } 3426 3427 int 3428 ahd_cmds_pending_print(u_int regvalue, u_int *cur_col, u_int wrap) 3429 { 3430 return (ahd_print_register(NULL, 0, "CMDS_PENDING", 3431 0x154, regvalue, cur_col, wrap)); 3432 } 3433 3434 int 3435 ahd_int_coalescing_cmdcount_print(u_int regvalue, u_int *cur_col, u_int wrap) 3436 { 3437 return (ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", 3438 0x156, regvalue, cur_col, wrap)); 3439 } 3440 3441 int 3442 ahd_local_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap) 3443 { 3444 return (ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", 3445 0x157, regvalue, cur_col, wrap)); 3446 } 3447 3448 int 3449 ahd_cmdsize_table_print(u_int regvalue, u_int *cur_col, u_int wrap) 3450 { 3451 return (ahd_print_register(NULL, 0, "CMDSIZE_TABLE", 3452 0x158, regvalue, cur_col, wrap)); 3453 } 3454 3455 int 3456 ahd_mk_message_scb_print(u_int regvalue, u_int *cur_col, u_int wrap) 3457 { 3458 return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 3459 0x160, regvalue, cur_col, wrap)); 3460 } 3461 3462 int 3463 ahd_mk_message_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) 3464 { 3465 return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 3466 0x162, regvalue, cur_col, wrap)); 3467 } 3468 3469 int 3470 ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 3471 { 3472 return (ahd_print_register(NULL, 0, "SCB_BASE", 3473 0x180, regvalue, cur_col, wrap)); 3474 } 3475 3476 int 3477 ahd_scb_residual_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 3478 { 3479 return (ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 3480 0x180, regvalue, cur_col, wrap)); 3481 } 3482 3483 static ahd_reg_parse_entry_t SCB_RESIDUAL_SGPTR_parse_table[] = { 3484 { "SG_LIST_NULL", 0x01, 0x01 }, 3485 { "SG_OVERRUN_RESID", 0x02, 0x02 }, 3486 { "SG_ADDR_BIT", 0x04, 0x04 }, 3487 { "SG_ADDR_MASK", 0xf8, 0xf8 } 3488 }; 3489 3490 int 3491 ahd_scb_residual_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3492 { 3493 return (ahd_print_register(SCB_RESIDUAL_SGPTR_parse_table, 4, "SCB_RESIDUAL_SGPTR", 3494 0x184, regvalue, cur_col, wrap)); 3495 } 3496 3497 int 3498 ahd_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap) 3499 { 3500 return (ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 3501 0x188, regvalue, cur_col, wrap)); 3502 } 3503 3504 int 3505 ahd_scb_target_phases_print(u_int regvalue, u_int *cur_col, u_int wrap) 3506 { 3507 return (ahd_print_register(NULL, 0, "SCB_TARGET_PHASES", 3508 0x189, regvalue, cur_col, wrap)); 3509 } 3510 3511 int 3512 ahd_scb_target_data_dir_print(u_int regvalue, u_int *cur_col, u_int wrap) 3513 { 3514 return (ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 3515 0x18a, regvalue, cur_col, wrap)); 3516 } 3517 3518 int 3519 ahd_scb_target_itag_print(u_int regvalue, u_int *cur_col, u_int wrap) 3520 { 3521 return (ahd_print_register(NULL, 0, "SCB_TARGET_ITAG", 3522 0x18b, regvalue, cur_col, wrap)); 3523 } 3524 3525 int 3526 ahd_scb_sense_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3527 { 3528 return (ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 3529 0x18c, regvalue, cur_col, wrap)); 3530 } 3531 3532 int 3533 ahd_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap) 3534 { 3535 return (ahd_print_register(NULL, 0, "SCB_TAG", 3536 0x190, regvalue, cur_col, wrap)); 3537 } 3538 3539 static ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = { 3540 { "SCB_TAG_TYPE", 0x03, 0x03 }, 3541 { "DISCONNECTED", 0x04, 0x04 }, 3542 { "STATUS_RCVD", 0x08, 0x08 }, 3543 { "MK_MESSAGE", 0x10, 0x10 }, 3544 { "TAG_ENB", 0x20, 0x20 }, 3545 { "DISCENB", 0x40, 0x40 }, 3546 { "TARGET_SCB", 0x80, 0x80 } 3547 }; 3548 3549 int 3550 ahd_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap) 3551 { 3552 return (ahd_print_register(SCB_CONTROL_parse_table, 7, "SCB_CONTROL", 3553 0x192, regvalue, cur_col, wrap)); 3554 } 3555 3556 static ahd_reg_parse_entry_t SCB_SCSIID_parse_table[] = { 3557 { "OID", 0x0f, 0x0f }, 3558 { "TID", 0xf0, 0xf0 } 3559 }; 3560 3561 int 3562 ahd_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) 3563 { 3564 return (ahd_print_register(SCB_SCSIID_parse_table, 2, "SCB_SCSIID", 3565 0x193, regvalue, cur_col, wrap)); 3566 } 3567 3568 static ahd_reg_parse_entry_t SCB_LUN_parse_table[] = { 3569 { "LID", 0xff, 0xff } 3570 }; 3571 3572 int 3573 ahd_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap) 3574 { 3575 return (ahd_print_register(SCB_LUN_parse_table, 1, "SCB_LUN", 3576 0x194, regvalue, cur_col, wrap)); 3577 } 3578 3579 static ahd_reg_parse_entry_t SCB_TASK_ATTRIBUTE_parse_table[] = { 3580 { "SCB_XFERLEN_ODD", 0x01, 0x01 } 3581 }; 3582 3583 int 3584 ahd_scb_task_attribute_print(u_int regvalue, u_int *cur_col, u_int wrap) 3585 { 3586 return (ahd_print_register(SCB_TASK_ATTRIBUTE_parse_table, 1, "SCB_TASK_ATTRIBUTE", 3587 0x195, regvalue, cur_col, wrap)); 3588 } 3589 3590 static ahd_reg_parse_entry_t SCB_CDB_LEN_parse_table[] = { 3591 { "SCB_CDB_LEN_PTR", 0x80, 0x80 } 3592 }; 3593 3594 int 3595 ahd_scb_cdb_len_print(u_int regvalue, u_int *cur_col, u_int wrap) 3596 { 3597 return (ahd_print_register(SCB_CDB_LEN_parse_table, 1, "SCB_CDB_LEN", 3598 0x196, regvalue, cur_col, wrap)); 3599 } 3600 3601 int 3602 ahd_scb_task_management_print(u_int regvalue, u_int *cur_col, u_int wrap) 3603 { 3604 return (ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", 3605 0x197, regvalue, cur_col, wrap)); 3606 } 3607 3608 int 3609 ahd_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3610 { 3611 return (ahd_print_register(NULL, 0, "SCB_DATAPTR", 3612 0x198, regvalue, cur_col, wrap)); 3613 } 3614 3615 static ahd_reg_parse_entry_t SCB_DATACNT_parse_table[] = { 3616 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f }, 3617 { "SG_LAST_SEG", 0x80, 0x80 } 3618 }; 3619 3620 int 3621 ahd_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 3622 { 3623 return (ahd_print_register(SCB_DATACNT_parse_table, 2, "SCB_DATACNT", 3624 0x1a0, regvalue, cur_col, wrap)); 3625 } 3626 3627 static ahd_reg_parse_entry_t SCB_SGPTR_parse_table[] = { 3628 { "SG_LIST_NULL", 0x01, 0x01 }, 3629 { "SG_FULL_RESID", 0x02, 0x02 }, 3630 { "SG_STATUS_VALID", 0x04, 0x04 } 3631 }; 3632 3633 int 3634 ahd_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3635 { 3636 return (ahd_print_register(SCB_SGPTR_parse_table, 3, "SCB_SGPTR", 3637 0x1a4, regvalue, cur_col, wrap)); 3638 } 3639 3640 int 3641 ahd_scb_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3642 { 3643 return (ahd_print_register(NULL, 0, "SCB_BUSADDR", 3644 0x1a8, regvalue, cur_col, wrap)); 3645 } 3646 3647 int 3648 ahd_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap) 3649 { 3650 return (ahd_print_register(NULL, 0, "SCB_NEXT", 3651 0x1ac, regvalue, cur_col, wrap)); 3652 } 3653 3654 int 3655 ahd_scb_next2_print(u_int regvalue, u_int *cur_col, u_int wrap) 3656 { 3657 return (ahd_print_register(NULL, 0, "SCB_NEXT2", 3658 0x1ae, regvalue, cur_col, wrap)); 3659 } 3660 3661 int 3662 ahd_scb_spare_print(u_int regvalue, u_int *cur_col, u_int wrap) 3663 { 3664 return (ahd_print_register(NULL, 0, "SCB_SPARE", 3665 0x1b0, regvalue, cur_col, wrap)); 3666 } 3667 3668 int 3669 ahd_scb_disconnected_lists_print(u_int regvalue, u_int *cur_col, u_int wrap) 3670 { 3671 return (ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 3672 0x1b8, regvalue, cur_col, wrap)); 3673 } 3674