1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * Copyright (c) 2011 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Konstantin Belousov 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org> 36 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org> 37 * 38 * This is generic Intel GTT handling code, morphed from the AGP 39 * bridge code. 40 */ 41 42 #include <sys/cdefs.h> 43 __FBSDID("$FreeBSD$"); 44 45 #if 0 46 #define KTR_AGP_I810 KTR_DEV 47 #else 48 #define KTR_AGP_I810 0 49 #endif 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/ktr.h> 56 #include <sys/module.h> 57 #include <sys/bus.h> 58 #include <sys/lock.h> 59 #include <sys/mutex.h> 60 #include <sys/proc.h> 61 #include <sys/rwlock.h> 62 63 #include <dev/agp/agppriv.h> 64 #include <dev/agp/agpreg.h> 65 #include <dev/agp/agp_i810.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pci_private.h> 69 70 #include <vm/vm.h> 71 #include <vm/vm_extern.h> 72 #include <vm/vm_kern.h> 73 #include <vm/vm_param.h> 74 #include <vm/vm_object.h> 75 #include <vm/vm_page.h> 76 #include <vm/vm_pageout.h> 77 #include <vm/pmap.h> 78 79 #include <machine/bus.h> 80 #include <machine/resource.h> 81 #include <machine/md_var.h> 82 #include <sys/rman.h> 83 84 MALLOC_DECLARE(M_AGP); 85 86 struct agp_i810_match; 87 88 static int agp_i810_check_active(device_t bridge_dev); 89 static int agp_i830_check_active(device_t bridge_dev); 90 static int agp_i915_check_active(device_t bridge_dev); 91 92 static void agp_82852_set_desc(device_t dev, 93 const struct agp_i810_match *match); 94 static void agp_i810_set_desc(device_t dev, const struct agp_i810_match *match); 95 96 static void agp_i810_dump_regs(device_t dev); 97 static void agp_i830_dump_regs(device_t dev); 98 static void agp_i855_dump_regs(device_t dev); 99 static void agp_i915_dump_regs(device_t dev); 100 static void agp_i965_dump_regs(device_t dev); 101 102 static int agp_i810_get_stolen_size(device_t dev); 103 static int agp_i830_get_stolen_size(device_t dev); 104 static int agp_i915_get_stolen_size(device_t dev); 105 106 static int agp_i810_get_gtt_mappable_entries(device_t dev); 107 static int agp_i830_get_gtt_mappable_entries(device_t dev); 108 static int agp_i915_get_gtt_mappable_entries(device_t dev); 109 110 static int agp_i810_get_gtt_total_entries(device_t dev); 111 static int agp_i965_get_gtt_total_entries(device_t dev); 112 static int agp_gen5_get_gtt_total_entries(device_t dev); 113 114 static int agp_i810_install_gatt(device_t dev); 115 static int agp_i830_install_gatt(device_t dev); 116 static int agp_i965_install_gatt(device_t dev); 117 static int agp_g4x_install_gatt(device_t dev); 118 119 static void agp_i810_deinstall_gatt(device_t dev); 120 static void agp_i830_deinstall_gatt(device_t dev); 121 122 static void agp_i810_install_gtt_pte(device_t dev, u_int index, 123 vm_offset_t physical, int flags); 124 static void agp_i830_install_gtt_pte(device_t dev, u_int index, 125 vm_offset_t physical, int flags); 126 static void agp_i915_install_gtt_pte(device_t dev, u_int index, 127 vm_offset_t physical, int flags); 128 static void agp_i965_install_gtt_pte(device_t dev, u_int index, 129 vm_offset_t physical, int flags); 130 static void agp_g4x_install_gtt_pte(device_t dev, u_int index, 131 vm_offset_t physical, int flags); 132 133 static void agp_i810_write_gtt(device_t dev, u_int index, uint32_t pte); 134 static void agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte); 135 static void agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte); 136 static void agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte); 137 138 static u_int32_t agp_i810_read_gtt_pte(device_t dev, u_int index); 139 static u_int32_t agp_i915_read_gtt_pte(device_t dev, u_int index); 140 static u_int32_t agp_i965_read_gtt_pte(device_t dev, u_int index); 141 static u_int32_t agp_g4x_read_gtt_pte(device_t dev, u_int index); 142 143 static vm_paddr_t agp_i810_read_gtt_pte_paddr(device_t dev, u_int index); 144 static vm_paddr_t agp_i915_read_gtt_pte_paddr(device_t dev, u_int index); 145 146 static int agp_i810_set_aperture(device_t dev, u_int32_t aperture); 147 static int agp_i830_set_aperture(device_t dev, u_int32_t aperture); 148 static int agp_i915_set_aperture(device_t dev, u_int32_t aperture); 149 150 static int agp_i810_chipset_flush_setup(device_t dev); 151 static int agp_i915_chipset_flush_setup(device_t dev); 152 static int agp_i965_chipset_flush_setup(device_t dev); 153 154 static void agp_i810_chipset_flush_teardown(device_t dev); 155 static void agp_i915_chipset_flush_teardown(device_t dev); 156 static void agp_i965_chipset_flush_teardown(device_t dev); 157 158 static void agp_i810_chipset_flush(device_t dev); 159 static void agp_i830_chipset_flush(device_t dev); 160 static void agp_i915_chipset_flush(device_t dev); 161 162 enum { 163 CHIP_I810, /* i810/i815 */ 164 CHIP_I830, /* 830M/845G */ 165 CHIP_I855, /* 852GM/855GM/865G */ 166 CHIP_I915, /* 915G/915GM */ 167 CHIP_I965, /* G965 */ 168 CHIP_G33, /* G33/Q33/Q35 */ 169 CHIP_IGD, /* Pineview */ 170 CHIP_G4X, /* G45/Q45 */ 171 }; 172 173 /* The i810 through i855 have the registers at BAR 1, and the GATT gets 174 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the 175 * start of the stolen memory, and should only be accessed by the OS through 176 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB 177 * is registers, second 512KB is GATT. 178 */ 179 static struct resource_spec agp_i810_res_spec[] = { 180 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE }, 181 { -1, 0 } 182 }; 183 184 static struct resource_spec agp_i915_res_spec[] = { 185 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE }, 186 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE }, 187 { -1, 0 } 188 }; 189 190 static struct resource_spec agp_i965_res_spec[] = { 191 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE }, 192 { SYS_RES_MEMORY, AGP_I965_APBASE, RF_ACTIVE | RF_SHAREABLE }, 193 { -1, 0 } 194 }; 195 196 struct agp_i810_softc { 197 struct agp_softc agp; 198 u_int32_t initial_aperture; /* aperture size at startup */ 199 struct agp_gatt *gatt; 200 u_int32_t dcache_size; /* i810 only */ 201 u_int32_t stolen; /* number of i830/845 gtt 202 entries for stolen memory */ 203 u_int stolen_size; /* BIOS-reserved graphics memory */ 204 u_int gtt_total_entries; /* Total number of gtt ptes */ 205 u_int gtt_mappable_entries; /* Number of gtt ptes mappable by CPU */ 206 device_t bdev; /* bridge device */ 207 void *argb_cursor; /* contigmalloc area for ARGB cursor */ 208 struct resource *sc_res[2]; 209 const struct agp_i810_match *match; 210 int sc_flush_page_rid; 211 struct resource *sc_flush_page_res; 212 void *sc_flush_page_vaddr; 213 int sc_bios_allocated_flush_page; 214 }; 215 216 static device_t intel_agp; 217 218 struct agp_i810_driver { 219 int chiptype; 220 int gen; 221 int busdma_addr_mask_sz; 222 struct resource_spec *res_spec; 223 int (*check_active)(device_t); 224 void (*set_desc)(device_t, const struct agp_i810_match *); 225 void (*dump_regs)(device_t); 226 int (*get_stolen_size)(device_t); 227 int (*get_gtt_total_entries)(device_t); 228 int (*get_gtt_mappable_entries)(device_t); 229 int (*install_gatt)(device_t); 230 void (*deinstall_gatt)(device_t); 231 void (*write_gtt)(device_t, u_int, uint32_t); 232 void (*install_gtt_pte)(device_t, u_int, vm_offset_t, int); 233 u_int32_t (*read_gtt_pte)(device_t, u_int); 234 vm_paddr_t (*read_gtt_pte_paddr)(device_t , u_int); 235 int (*set_aperture)(device_t, u_int32_t); 236 int (*chipset_flush_setup)(device_t); 237 void (*chipset_flush_teardown)(device_t); 238 void (*chipset_flush)(device_t); 239 }; 240 241 static struct { 242 struct intel_gtt base; 243 } intel_private; 244 245 static const struct agp_i810_driver agp_i810_i810_driver = { 246 .chiptype = CHIP_I810, 247 .gen = 1, 248 .busdma_addr_mask_sz = 32, 249 .res_spec = agp_i810_res_spec, 250 .check_active = agp_i810_check_active, 251 .set_desc = agp_i810_set_desc, 252 .dump_regs = agp_i810_dump_regs, 253 .get_stolen_size = agp_i810_get_stolen_size, 254 .get_gtt_mappable_entries = agp_i810_get_gtt_mappable_entries, 255 .get_gtt_total_entries = agp_i810_get_gtt_total_entries, 256 .install_gatt = agp_i810_install_gatt, 257 .deinstall_gatt = agp_i810_deinstall_gatt, 258 .write_gtt = agp_i810_write_gtt, 259 .install_gtt_pte = agp_i810_install_gtt_pte, 260 .read_gtt_pte = agp_i810_read_gtt_pte, 261 .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr, 262 .set_aperture = agp_i810_set_aperture, 263 .chipset_flush_setup = agp_i810_chipset_flush_setup, 264 .chipset_flush_teardown = agp_i810_chipset_flush_teardown, 265 .chipset_flush = agp_i810_chipset_flush, 266 }; 267 268 static const struct agp_i810_driver agp_i810_i815_driver = { 269 .chiptype = CHIP_I810, 270 .gen = 2, 271 .busdma_addr_mask_sz = 32, 272 .res_spec = agp_i810_res_spec, 273 .check_active = agp_i810_check_active, 274 .set_desc = agp_i810_set_desc, 275 .dump_regs = agp_i810_dump_regs, 276 .get_stolen_size = agp_i810_get_stolen_size, 277 .get_gtt_mappable_entries = agp_i830_get_gtt_mappable_entries, 278 .get_gtt_total_entries = agp_i810_get_gtt_total_entries, 279 .install_gatt = agp_i810_install_gatt, 280 .deinstall_gatt = agp_i810_deinstall_gatt, 281 .write_gtt = agp_i810_write_gtt, 282 .install_gtt_pte = agp_i810_install_gtt_pte, 283 .read_gtt_pte = agp_i810_read_gtt_pte, 284 .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr, 285 .set_aperture = agp_i810_set_aperture, 286 .chipset_flush_setup = agp_i810_chipset_flush_setup, 287 .chipset_flush_teardown = agp_i810_chipset_flush_teardown, 288 .chipset_flush = agp_i830_chipset_flush, 289 }; 290 291 static const struct agp_i810_driver agp_i810_i830_driver = { 292 .chiptype = CHIP_I830, 293 .gen = 2, 294 .busdma_addr_mask_sz = 32, 295 .res_spec = agp_i810_res_spec, 296 .check_active = agp_i830_check_active, 297 .set_desc = agp_i810_set_desc, 298 .dump_regs = agp_i830_dump_regs, 299 .get_stolen_size = agp_i830_get_stolen_size, 300 .get_gtt_mappable_entries = agp_i830_get_gtt_mappable_entries, 301 .get_gtt_total_entries = agp_i810_get_gtt_total_entries, 302 .install_gatt = agp_i830_install_gatt, 303 .deinstall_gatt = agp_i830_deinstall_gatt, 304 .write_gtt = agp_i810_write_gtt, 305 .install_gtt_pte = agp_i830_install_gtt_pte, 306 .read_gtt_pte = agp_i810_read_gtt_pte, 307 .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr, 308 .set_aperture = agp_i830_set_aperture, 309 .chipset_flush_setup = agp_i810_chipset_flush_setup, 310 .chipset_flush_teardown = agp_i810_chipset_flush_teardown, 311 .chipset_flush = agp_i830_chipset_flush, 312 }; 313 314 static const struct agp_i810_driver agp_i810_i855_driver = { 315 .chiptype = CHIP_I855, 316 .gen = 2, 317 .busdma_addr_mask_sz = 32, 318 .res_spec = agp_i810_res_spec, 319 .check_active = agp_i830_check_active, 320 .set_desc = agp_82852_set_desc, 321 .dump_regs = agp_i855_dump_regs, 322 .get_stolen_size = agp_i915_get_stolen_size, 323 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, 324 .get_gtt_total_entries = agp_i810_get_gtt_total_entries, 325 .install_gatt = agp_i830_install_gatt, 326 .deinstall_gatt = agp_i830_deinstall_gatt, 327 .write_gtt = agp_i810_write_gtt, 328 .install_gtt_pte = agp_i830_install_gtt_pte, 329 .read_gtt_pte = agp_i810_read_gtt_pte, 330 .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr, 331 .set_aperture = agp_i830_set_aperture, 332 .chipset_flush_setup = agp_i810_chipset_flush_setup, 333 .chipset_flush_teardown = agp_i810_chipset_flush_teardown, 334 .chipset_flush = agp_i830_chipset_flush, 335 }; 336 337 static const struct agp_i810_driver agp_i810_i865_driver = { 338 .chiptype = CHIP_I855, 339 .gen = 2, 340 .busdma_addr_mask_sz = 32, 341 .res_spec = agp_i810_res_spec, 342 .check_active = agp_i830_check_active, 343 .set_desc = agp_i810_set_desc, 344 .dump_regs = agp_i855_dump_regs, 345 .get_stolen_size = agp_i915_get_stolen_size, 346 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, 347 .get_gtt_total_entries = agp_i810_get_gtt_total_entries, 348 .install_gatt = agp_i830_install_gatt, 349 .deinstall_gatt = agp_i830_deinstall_gatt, 350 .write_gtt = agp_i810_write_gtt, 351 .install_gtt_pte = agp_i830_install_gtt_pte, 352 .read_gtt_pte = agp_i810_read_gtt_pte, 353 .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr, 354 .set_aperture = agp_i915_set_aperture, 355 .chipset_flush_setup = agp_i810_chipset_flush_setup, 356 .chipset_flush_teardown = agp_i810_chipset_flush_teardown, 357 .chipset_flush = agp_i830_chipset_flush, 358 }; 359 360 static const struct agp_i810_driver agp_i810_i915_driver = { 361 .chiptype = CHIP_I915, 362 .gen = 3, 363 .busdma_addr_mask_sz = 32, 364 .res_spec = agp_i915_res_spec, 365 .check_active = agp_i915_check_active, 366 .set_desc = agp_i810_set_desc, 367 .dump_regs = agp_i915_dump_regs, 368 .get_stolen_size = agp_i915_get_stolen_size, 369 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, 370 .get_gtt_total_entries = agp_i810_get_gtt_total_entries, 371 .install_gatt = agp_i830_install_gatt, 372 .deinstall_gatt = agp_i830_deinstall_gatt, 373 .write_gtt = agp_i915_write_gtt, 374 .install_gtt_pte = agp_i915_install_gtt_pte, 375 .read_gtt_pte = agp_i915_read_gtt_pte, 376 .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr, 377 .set_aperture = agp_i915_set_aperture, 378 .chipset_flush_setup = agp_i915_chipset_flush_setup, 379 .chipset_flush_teardown = agp_i915_chipset_flush_teardown, 380 .chipset_flush = agp_i915_chipset_flush, 381 }; 382 383 static const struct agp_i810_driver agp_i810_g33_driver = { 384 .chiptype = CHIP_G33, 385 .gen = 3, 386 .busdma_addr_mask_sz = 36, 387 .res_spec = agp_i915_res_spec, 388 .check_active = agp_i915_check_active, 389 .set_desc = agp_i810_set_desc, 390 .dump_regs = agp_i965_dump_regs, 391 .get_stolen_size = agp_i915_get_stolen_size, 392 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, 393 .get_gtt_total_entries = agp_i965_get_gtt_total_entries, 394 .install_gatt = agp_i830_install_gatt, 395 .deinstall_gatt = agp_i830_deinstall_gatt, 396 .write_gtt = agp_i915_write_gtt, 397 .install_gtt_pte = agp_i915_install_gtt_pte, 398 .read_gtt_pte = agp_i915_read_gtt_pte, 399 .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr, 400 .set_aperture = agp_i915_set_aperture, 401 .chipset_flush_setup = agp_i965_chipset_flush_setup, 402 .chipset_flush_teardown = agp_i965_chipset_flush_teardown, 403 .chipset_flush = agp_i915_chipset_flush, 404 }; 405 406 static const struct agp_i810_driver agp_i810_igd_driver = { 407 .chiptype = CHIP_IGD, 408 .gen = 3, 409 .busdma_addr_mask_sz = 36, 410 .res_spec = agp_i915_res_spec, 411 .check_active = agp_i915_check_active, 412 .set_desc = agp_i810_set_desc, 413 .dump_regs = agp_i915_dump_regs, 414 .get_stolen_size = agp_i915_get_stolen_size, 415 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, 416 .get_gtt_total_entries = agp_i965_get_gtt_total_entries, 417 .install_gatt = agp_i830_install_gatt, 418 .deinstall_gatt = agp_i830_deinstall_gatt, 419 .write_gtt = agp_i915_write_gtt, 420 .install_gtt_pte = agp_i915_install_gtt_pte, 421 .read_gtt_pte = agp_i915_read_gtt_pte, 422 .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr, 423 .set_aperture = agp_i915_set_aperture, 424 .chipset_flush_setup = agp_i965_chipset_flush_setup, 425 .chipset_flush_teardown = agp_i965_chipset_flush_teardown, 426 .chipset_flush = agp_i915_chipset_flush, 427 }; 428 429 static const struct agp_i810_driver agp_i810_g965_driver = { 430 .chiptype = CHIP_I965, 431 .gen = 4, 432 .busdma_addr_mask_sz = 36, 433 .res_spec = agp_i965_res_spec, 434 .check_active = agp_i915_check_active, 435 .set_desc = agp_i810_set_desc, 436 .dump_regs = agp_i965_dump_regs, 437 .get_stolen_size = agp_i915_get_stolen_size, 438 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, 439 .get_gtt_total_entries = agp_i965_get_gtt_total_entries, 440 .install_gatt = agp_i965_install_gatt, 441 .deinstall_gatt = agp_i830_deinstall_gatt, 442 .write_gtt = agp_i965_write_gtt, 443 .install_gtt_pte = agp_i965_install_gtt_pte, 444 .read_gtt_pte = agp_i965_read_gtt_pte, 445 .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr, 446 .set_aperture = agp_i915_set_aperture, 447 .chipset_flush_setup = agp_i965_chipset_flush_setup, 448 .chipset_flush_teardown = agp_i965_chipset_flush_teardown, 449 .chipset_flush = agp_i915_chipset_flush, 450 }; 451 452 static const struct agp_i810_driver agp_i810_g4x_driver = { 453 .chiptype = CHIP_G4X, 454 .gen = 5, 455 .busdma_addr_mask_sz = 36, 456 .res_spec = agp_i965_res_spec, 457 .check_active = agp_i915_check_active, 458 .set_desc = agp_i810_set_desc, 459 .dump_regs = agp_i965_dump_regs, 460 .get_stolen_size = agp_i915_get_stolen_size, 461 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, 462 .get_gtt_total_entries = agp_gen5_get_gtt_total_entries, 463 .install_gatt = agp_g4x_install_gatt, 464 .deinstall_gatt = agp_i830_deinstall_gatt, 465 .write_gtt = agp_g4x_write_gtt, 466 .install_gtt_pte = agp_g4x_install_gtt_pte, 467 .read_gtt_pte = agp_g4x_read_gtt_pte, 468 .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr, 469 .set_aperture = agp_i915_set_aperture, 470 .chipset_flush_setup = agp_i965_chipset_flush_setup, 471 .chipset_flush_teardown = agp_i965_chipset_flush_teardown, 472 .chipset_flush = agp_i915_chipset_flush, 473 }; 474 475 /* For adding new devices, devid is the id of the graphics controller 476 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the 477 * second head should never be added. The bridge_offset is the offset to 478 * subtract from devid to get the id of the hostb that the device is on. 479 */ 480 static const struct agp_i810_match { 481 int devid; 482 char *name; 483 const struct agp_i810_driver *driver; 484 } agp_i810_matches[] = { 485 { 486 .devid = 0x71218086, 487 .name = "Intel 82810 (i810 GMCH) SVGA controller", 488 .driver = &agp_i810_i810_driver 489 }, 490 { 491 .devid = 0x71238086, 492 .name = "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller", 493 .driver = &agp_i810_i810_driver 494 }, 495 { 496 .devid = 0x71258086, 497 .name = "Intel 82810E (i810E GMCH) SVGA controller", 498 .driver = &agp_i810_i810_driver 499 }, 500 { 501 .devid = 0x11328086, 502 .name = "Intel 82815 (i815 GMCH) SVGA controller", 503 .driver = &agp_i810_i815_driver 504 }, 505 { 506 .devid = 0x35778086, 507 .name = "Intel 82830M (830M GMCH) SVGA controller", 508 .driver = &agp_i810_i830_driver 509 }, 510 { 511 .devid = 0x25628086, 512 .name = "Intel 82845M (845M GMCH) SVGA controller", 513 .driver = &agp_i810_i830_driver 514 }, 515 { 516 .devid = 0x35828086, 517 .name = "Intel 82852/855GM SVGA controller", 518 .driver = &agp_i810_i855_driver 519 }, 520 { 521 .devid = 0x25728086, 522 .name = "Intel 82865G (865G GMCH) SVGA controller", 523 .driver = &agp_i810_i865_driver 524 }, 525 { 526 .devid = 0x25828086, 527 .name = "Intel 82915G (915G GMCH) SVGA controller", 528 .driver = &agp_i810_i915_driver 529 }, 530 { 531 .devid = 0x258A8086, 532 .name = "Intel E7221 SVGA controller", 533 .driver = &agp_i810_i915_driver 534 }, 535 { 536 .devid = 0x25928086, 537 .name = "Intel 82915GM (915GM GMCH) SVGA controller", 538 .driver = &agp_i810_i915_driver 539 }, 540 { 541 .devid = 0x27728086, 542 .name = "Intel 82945G (945G GMCH) SVGA controller", 543 .driver = &agp_i810_i915_driver 544 }, 545 { 546 .devid = 0x27A28086, 547 .name = "Intel 82945GM (945GM GMCH) SVGA controller", 548 .driver = &agp_i810_i915_driver 549 }, 550 { 551 .devid = 0x27AE8086, 552 .name = "Intel 945GME SVGA controller", 553 .driver = &agp_i810_i915_driver 554 }, 555 { 556 .devid = 0x29728086, 557 .name = "Intel 946GZ SVGA controller", 558 .driver = &agp_i810_g965_driver 559 }, 560 { 561 .devid = 0x29828086, 562 .name = "Intel G965 SVGA controller", 563 .driver = &agp_i810_g965_driver 564 }, 565 { 566 .devid = 0x29928086, 567 .name = "Intel Q965 SVGA controller", 568 .driver = &agp_i810_g965_driver 569 }, 570 { 571 .devid = 0x29A28086, 572 .name = "Intel G965 SVGA controller", 573 .driver = &agp_i810_g965_driver 574 }, 575 { 576 .devid = 0x29B28086, 577 .name = "Intel Q35 SVGA controller", 578 .driver = &agp_i810_g33_driver 579 }, 580 { 581 .devid = 0x29C28086, 582 .name = "Intel G33 SVGA controller", 583 .driver = &agp_i810_g33_driver 584 }, 585 { 586 .devid = 0x29D28086, 587 .name = "Intel Q33 SVGA controller", 588 .driver = &agp_i810_g33_driver 589 }, 590 { 591 .devid = 0xA0018086, 592 .name = "Intel Pineview SVGA controller", 593 .driver = &agp_i810_igd_driver 594 }, 595 { 596 .devid = 0xA0118086, 597 .name = "Intel Pineview (M) SVGA controller", 598 .driver = &agp_i810_igd_driver 599 }, 600 { 601 .devid = 0x2A028086, 602 .name = "Intel GM965 SVGA controller", 603 .driver = &agp_i810_g965_driver 604 }, 605 { 606 .devid = 0x2A128086, 607 .name = "Intel GME965 SVGA controller", 608 .driver = &agp_i810_g965_driver 609 }, 610 { 611 .devid = 0x2A428086, 612 .name = "Intel GM45 SVGA controller", 613 .driver = &agp_i810_g4x_driver 614 }, 615 { 616 .devid = 0x2E028086, 617 .name = "Intel Eaglelake SVGA controller", 618 .driver = &agp_i810_g4x_driver 619 }, 620 { 621 .devid = 0x2E128086, 622 .name = "Intel Q45 SVGA controller", 623 .driver = &agp_i810_g4x_driver 624 }, 625 { 626 .devid = 0x2E228086, 627 .name = "Intel G45 SVGA controller", 628 .driver = &agp_i810_g4x_driver 629 }, 630 { 631 .devid = 0x2E328086, 632 .name = "Intel G41 SVGA controller", 633 .driver = &agp_i810_g4x_driver 634 }, 635 { 636 .devid = 0x00428086, 637 .name = "Intel Ironlake (D) SVGA controller", 638 .driver = &agp_i810_g4x_driver 639 }, 640 { 641 .devid = 0x00468086, 642 .name = "Intel Ironlake (M) SVGA controller", 643 .driver = &agp_i810_g4x_driver 644 }, 645 { 646 .devid = 0, 647 } 648 }; 649 650 static const struct agp_i810_match* 651 agp_i810_match(device_t dev) 652 { 653 int i, devid; 654 655 if (pci_get_class(dev) != PCIC_DISPLAY 656 || (pci_get_subclass(dev) != PCIS_DISPLAY_VGA && 657 pci_get_subclass(dev) != PCIS_DISPLAY_OTHER)) 658 return (NULL); 659 660 devid = pci_get_devid(dev); 661 for (i = 0; agp_i810_matches[i].devid != 0; i++) { 662 if (agp_i810_matches[i].devid == devid) 663 break; 664 } 665 if (agp_i810_matches[i].devid == 0) 666 return (NULL); 667 else 668 return (&agp_i810_matches[i]); 669 } 670 671 /* 672 * Find bridge device. 673 */ 674 static device_t 675 agp_i810_find_bridge(device_t dev) 676 { 677 678 return (pci_find_dbsf(0, 0, 0, 0)); 679 } 680 681 static void 682 agp_i810_identify(driver_t *driver, device_t parent) 683 { 684 685 if (device_find_child(parent, "agp", -1) == NULL && 686 agp_i810_match(parent)) 687 device_add_child(parent, "agp", -1); 688 } 689 690 static int 691 agp_i810_check_active(device_t bridge_dev) 692 { 693 u_int8_t smram; 694 695 smram = pci_read_config(bridge_dev, AGP_I810_SMRAM, 1); 696 if ((smram & AGP_I810_SMRAM_GMS) == AGP_I810_SMRAM_GMS_DISABLED) 697 return (ENXIO); 698 return (0); 699 } 700 701 static int 702 agp_i830_check_active(device_t bridge_dev) 703 { 704 int gcc1; 705 706 gcc1 = pci_read_config(bridge_dev, AGP_I830_GCC1, 1); 707 if ((gcc1 & AGP_I830_GCC1_DEV2) == AGP_I830_GCC1_DEV2_DISABLED) 708 return (ENXIO); 709 return (0); 710 } 711 712 static int 713 agp_i915_check_active(device_t bridge_dev) 714 { 715 int deven; 716 717 deven = pci_read_config(bridge_dev, AGP_I915_DEVEN, 4); 718 if ((deven & AGP_I915_DEVEN_D2F0) == AGP_I915_DEVEN_D2F0_DISABLED) 719 return (ENXIO); 720 return (0); 721 } 722 723 static void 724 agp_82852_set_desc(device_t dev, const struct agp_i810_match *match) 725 { 726 727 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) { 728 case AGP_I855_GME: 729 device_set_desc(dev, 730 "Intel 82855GME (855GME GMCH) SVGA controller"); 731 break; 732 case AGP_I855_GM: 733 device_set_desc(dev, 734 "Intel 82855GM (855GM GMCH) SVGA controller"); 735 break; 736 case AGP_I852_GME: 737 device_set_desc(dev, 738 "Intel 82852GME (852GME GMCH) SVGA controller"); 739 break; 740 case AGP_I852_GM: 741 device_set_desc(dev, 742 "Intel 82852GM (852GM GMCH) SVGA controller"); 743 break; 744 default: 745 device_set_desc(dev, 746 "Intel 8285xM (85xGM GMCH) SVGA controller"); 747 break; 748 } 749 } 750 751 static void 752 agp_i810_set_desc(device_t dev, const struct agp_i810_match *match) 753 { 754 755 device_set_desc(dev, match->name); 756 } 757 758 static int 759 agp_i810_probe(device_t dev) 760 { 761 device_t bdev; 762 const struct agp_i810_match *match; 763 int err; 764 765 if (resource_disabled("agp", device_get_unit(dev))) 766 return (ENXIO); 767 match = agp_i810_match(dev); 768 if (match == NULL) 769 return (ENXIO); 770 771 bdev = agp_i810_find_bridge(dev); 772 if (bdev == NULL) { 773 if (bootverbose) 774 printf("I810: can't find bridge device\n"); 775 return (ENXIO); 776 } 777 778 /* 779 * checking whether internal graphics device has been activated. 780 */ 781 err = match->driver->check_active(bdev); 782 if (err != 0) { 783 if (bootverbose) 784 printf("i810: disabled, not probing\n"); 785 return (err); 786 } 787 788 match->driver->set_desc(dev, match); 789 return (BUS_PROBE_DEFAULT); 790 } 791 792 static void 793 agp_i810_dump_regs(device_t dev) 794 { 795 struct agp_i810_softc *sc = device_get_softc(dev); 796 797 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n", 798 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); 799 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n", 800 pci_read_config(sc->bdev, AGP_I810_MISCC, 2)); 801 } 802 803 static void 804 agp_i830_dump_regs(device_t dev) 805 { 806 struct agp_i810_softc *sc = device_get_softc(dev); 807 808 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n", 809 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); 810 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n", 811 pci_read_config(sc->bdev, AGP_I830_GCC1, 1)); 812 } 813 814 static void 815 agp_i855_dump_regs(device_t dev) 816 { 817 struct agp_i810_softc *sc = device_get_softc(dev); 818 819 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n", 820 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); 821 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n", 822 pci_read_config(sc->bdev, AGP_I855_GCC1, 1)); 823 } 824 825 static void 826 agp_i915_dump_regs(device_t dev) 827 { 828 struct agp_i810_softc *sc = device_get_softc(dev); 829 830 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n", 831 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); 832 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n", 833 pci_read_config(sc->bdev, AGP_I855_GCC1, 1)); 834 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n", 835 pci_read_config(sc->bdev, AGP_I915_MSAC, 1)); 836 } 837 838 static void 839 agp_i965_dump_regs(device_t dev) 840 { 841 struct agp_i810_softc *sc = device_get_softc(dev); 842 843 device_printf(dev, "AGP_I965_PGTBL_CTL2: %08x\n", 844 bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2)); 845 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n", 846 pci_read_config(sc->bdev, AGP_I855_GCC1, 1)); 847 device_printf(dev, "AGP_I965_MSAC: 0x%02x\n", 848 pci_read_config(sc->bdev, AGP_I965_MSAC, 1)); 849 } 850 851 static int 852 agp_i810_get_stolen_size(device_t dev) 853 { 854 struct agp_i810_softc *sc; 855 856 sc = device_get_softc(dev); 857 sc->stolen = 0; 858 sc->stolen_size = 0; 859 return (0); 860 } 861 862 static int 863 agp_i830_get_stolen_size(device_t dev) 864 { 865 struct agp_i810_softc *sc; 866 unsigned int gcc1; 867 868 sc = device_get_softc(dev); 869 870 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1); 871 switch (gcc1 & AGP_I830_GCC1_GMS) { 872 case AGP_I830_GCC1_GMS_STOLEN_512: 873 sc->stolen = (512 - 132) * 1024 / 4096; 874 sc->stolen_size = 512 * 1024; 875 break; 876 case AGP_I830_GCC1_GMS_STOLEN_1024: 877 sc->stolen = (1024 - 132) * 1024 / 4096; 878 sc->stolen_size = 1024 * 1024; 879 break; 880 case AGP_I830_GCC1_GMS_STOLEN_8192: 881 sc->stolen = (8192 - 132) * 1024 / 4096; 882 sc->stolen_size = 8192 * 1024; 883 break; 884 default: 885 sc->stolen = 0; 886 device_printf(dev, 887 "unknown memory configuration, disabling (GCC1 %x)\n", 888 gcc1); 889 return (EINVAL); 890 } 891 return (0); 892 } 893 894 static int 895 agp_i915_get_stolen_size(device_t dev) 896 { 897 struct agp_i810_softc *sc; 898 unsigned int gcc1, stolen, gtt_size; 899 900 sc = device_get_softc(dev); 901 902 /* 903 * Stolen memory is set up at the beginning of the aperture by 904 * the BIOS, consisting of the GATT followed by 4kb for the 905 * BIOS display. 906 */ 907 switch (sc->match->driver->chiptype) { 908 case CHIP_I855: 909 gtt_size = 128; 910 break; 911 case CHIP_I915: 912 gtt_size = 256; 913 break; 914 case CHIP_I965: 915 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) & 916 AGP_I810_PGTBL_SIZE_MASK) { 917 case AGP_I810_PGTBL_SIZE_128KB: 918 gtt_size = 128; 919 break; 920 case AGP_I810_PGTBL_SIZE_256KB: 921 gtt_size = 256; 922 break; 923 case AGP_I810_PGTBL_SIZE_512KB: 924 gtt_size = 512; 925 break; 926 case AGP_I965_PGTBL_SIZE_1MB: 927 gtt_size = 1024; 928 break; 929 case AGP_I965_PGTBL_SIZE_2MB: 930 gtt_size = 2048; 931 break; 932 case AGP_I965_PGTBL_SIZE_1_5MB: 933 gtt_size = 1024 + 512; 934 break; 935 default: 936 device_printf(dev, "Bad PGTBL size\n"); 937 return (EINVAL); 938 } 939 break; 940 case CHIP_G33: 941 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2); 942 switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) { 943 case AGP_G33_MGGC_GGMS_SIZE_1M: 944 gtt_size = 1024; 945 break; 946 case AGP_G33_MGGC_GGMS_SIZE_2M: 947 gtt_size = 2048; 948 break; 949 default: 950 device_printf(dev, "Bad PGTBL size\n"); 951 return (EINVAL); 952 } 953 break; 954 case CHIP_IGD: 955 case CHIP_G4X: 956 gtt_size = 0; 957 break; 958 default: 959 device_printf(dev, "Bad chiptype\n"); 960 return (EINVAL); 961 } 962 963 /* GCC1 is called MGGC on i915+ */ 964 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1); 965 switch (gcc1 & AGP_I855_GCC1_GMS) { 966 case AGP_I855_GCC1_GMS_STOLEN_1M: 967 stolen = 1024; 968 break; 969 case AGP_I855_GCC1_GMS_STOLEN_4M: 970 stolen = 4 * 1024; 971 break; 972 case AGP_I855_GCC1_GMS_STOLEN_8M: 973 stolen = 8 * 1024; 974 break; 975 case AGP_I855_GCC1_GMS_STOLEN_16M: 976 stolen = 16 * 1024; 977 break; 978 case AGP_I855_GCC1_GMS_STOLEN_32M: 979 stolen = 32 * 1024; 980 break; 981 case AGP_I915_GCC1_GMS_STOLEN_48M: 982 stolen = sc->match->driver->gen > 2 ? 48 * 1024 : 0; 983 break; 984 case AGP_I915_GCC1_GMS_STOLEN_64M: 985 stolen = sc->match->driver->gen > 2 ? 64 * 1024 : 0; 986 break; 987 case AGP_G33_GCC1_GMS_STOLEN_128M: 988 stolen = sc->match->driver->gen > 2 ? 128 * 1024 : 0; 989 break; 990 case AGP_G33_GCC1_GMS_STOLEN_256M: 991 stolen = sc->match->driver->gen > 2 ? 256 * 1024 : 0; 992 break; 993 case AGP_G4X_GCC1_GMS_STOLEN_96M: 994 if (sc->match->driver->chiptype == CHIP_I965 || 995 sc->match->driver->chiptype == CHIP_G4X) 996 stolen = 96 * 1024; 997 else 998 stolen = 0; 999 break; 1000 case AGP_G4X_GCC1_GMS_STOLEN_160M: 1001 if (sc->match->driver->chiptype == CHIP_I965 || 1002 sc->match->driver->chiptype == CHIP_G4X) 1003 stolen = 160 * 1024; 1004 else 1005 stolen = 0; 1006 break; 1007 case AGP_G4X_GCC1_GMS_STOLEN_224M: 1008 if (sc->match->driver->chiptype == CHIP_I965 || 1009 sc->match->driver->chiptype == CHIP_G4X) 1010 stolen = 224 * 1024; 1011 else 1012 stolen = 0; 1013 break; 1014 case AGP_G4X_GCC1_GMS_STOLEN_352M: 1015 if (sc->match->driver->chiptype == CHIP_I965 || 1016 sc->match->driver->chiptype == CHIP_G4X) 1017 stolen = 352 * 1024; 1018 else 1019 stolen = 0; 1020 break; 1021 default: 1022 device_printf(dev, 1023 "unknown memory configuration, disabling (GCC1 %x)\n", 1024 gcc1); 1025 return (EINVAL); 1026 } 1027 1028 gtt_size += 4; 1029 sc->stolen_size = stolen * 1024; 1030 sc->stolen = (stolen - gtt_size) * 1024 / 4096; 1031 1032 return (0); 1033 } 1034 1035 static int 1036 agp_i810_get_gtt_mappable_entries(device_t dev) 1037 { 1038 struct agp_i810_softc *sc; 1039 uint32_t ap; 1040 uint16_t miscc; 1041 1042 sc = device_get_softc(dev); 1043 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); 1044 if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32) 1045 ap = 32; 1046 else 1047 ap = 64; 1048 sc->gtt_mappable_entries = (ap * 1024 * 1024) >> AGP_PAGE_SHIFT; 1049 return (0); 1050 } 1051 1052 static int 1053 agp_i830_get_gtt_mappable_entries(device_t dev) 1054 { 1055 struct agp_i810_softc *sc; 1056 uint32_t ap; 1057 uint16_t gmch_ctl; 1058 1059 sc = device_get_softc(dev); 1060 gmch_ctl = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); 1061 if ((gmch_ctl & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1062 ap = 64; 1063 else 1064 ap = 128; 1065 sc->gtt_mappable_entries = (ap * 1024 * 1024) >> AGP_PAGE_SHIFT; 1066 return (0); 1067 } 1068 1069 static int 1070 agp_i915_get_gtt_mappable_entries(device_t dev) 1071 { 1072 struct agp_i810_softc *sc; 1073 uint32_t ap; 1074 1075 sc = device_get_softc(dev); 1076 ap = AGP_GET_APERTURE(dev); 1077 sc->gtt_mappable_entries = ap >> AGP_PAGE_SHIFT; 1078 return (0); 1079 } 1080 1081 static int 1082 agp_i810_get_gtt_total_entries(device_t dev) 1083 { 1084 struct agp_i810_softc *sc; 1085 1086 sc = device_get_softc(dev); 1087 sc->gtt_total_entries = sc->gtt_mappable_entries; 1088 return (0); 1089 } 1090 1091 static int 1092 agp_i965_get_gtt_total_entries(device_t dev) 1093 { 1094 struct agp_i810_softc *sc; 1095 uint32_t pgetbl_ctl; 1096 int error; 1097 1098 sc = device_get_softc(dev); 1099 error = 0; 1100 pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); 1101 switch (pgetbl_ctl & AGP_I810_PGTBL_SIZE_MASK) { 1102 case AGP_I810_PGTBL_SIZE_128KB: 1103 sc->gtt_total_entries = 128 * 1024 / 4; 1104 break; 1105 case AGP_I810_PGTBL_SIZE_256KB: 1106 sc->gtt_total_entries = 256 * 1024 / 4; 1107 break; 1108 case AGP_I810_PGTBL_SIZE_512KB: 1109 sc->gtt_total_entries = 512 * 1024 / 4; 1110 break; 1111 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ 1112 case AGP_I810_PGTBL_SIZE_1MB: 1113 sc->gtt_total_entries = 1024 * 1024 / 4; 1114 break; 1115 case AGP_I810_PGTBL_SIZE_2MB: 1116 sc->gtt_total_entries = 2 * 1024 * 1024 / 4; 1117 break; 1118 case AGP_I810_PGTBL_SIZE_1_5MB: 1119 sc->gtt_total_entries = (1024 + 512) * 1024 / 4; 1120 break; 1121 default: 1122 device_printf(dev, "Unknown page table size\n"); 1123 error = ENXIO; 1124 } 1125 return (error); 1126 } 1127 1128 static void 1129 agp_gen5_adjust_pgtbl_size(device_t dev, uint32_t sz) 1130 { 1131 struct agp_i810_softc *sc; 1132 uint32_t pgetbl_ctl, pgetbl_ctl2; 1133 1134 sc = device_get_softc(dev); 1135 1136 /* Disable per-process page table. */ 1137 pgetbl_ctl2 = bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2); 1138 pgetbl_ctl2 &= ~AGP_I810_PGTBL_ENABLED; 1139 bus_write_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2, pgetbl_ctl2); 1140 1141 /* Write the new ggtt size. */ 1142 pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); 1143 pgetbl_ctl &= ~AGP_I810_PGTBL_SIZE_MASK; 1144 pgetbl_ctl |= sz; 1145 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgetbl_ctl); 1146 } 1147 1148 static int 1149 agp_gen5_get_gtt_total_entries(device_t dev) 1150 { 1151 struct agp_i810_softc *sc; 1152 uint16_t gcc1; 1153 1154 sc = device_get_softc(dev); 1155 1156 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); 1157 switch (gcc1 & AGP_G4x_GCC1_SIZE_MASK) { 1158 case AGP_G4x_GCC1_SIZE_1M: 1159 case AGP_G4x_GCC1_SIZE_VT_1M: 1160 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_1MB); 1161 break; 1162 case AGP_G4x_GCC1_SIZE_VT_1_5M: 1163 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_1_5MB); 1164 break; 1165 case AGP_G4x_GCC1_SIZE_2M: 1166 case AGP_G4x_GCC1_SIZE_VT_2M: 1167 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_2MB); 1168 break; 1169 default: 1170 device_printf(dev, "Unknown page table size\n"); 1171 return (ENXIO); 1172 } 1173 1174 return (agp_i965_get_gtt_total_entries(dev)); 1175 } 1176 1177 static int 1178 agp_i810_install_gatt(device_t dev) 1179 { 1180 struct agp_i810_softc *sc; 1181 1182 sc = device_get_softc(dev); 1183 1184 /* Some i810s have on-chip memory called dcache. */ 1185 if ((bus_read_1(sc->sc_res[0], AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 1186 != 0) 1187 sc->dcache_size = 4 * 1024 * 1024; 1188 else 1189 sc->dcache_size = 0; 1190 1191 /* According to the specs the gatt on the i810 must be 64k. */ 1192 sc->gatt->ag_virtual = (void *)kmem_alloc_contig(64 * 1024, M_NOWAIT | 1193 M_ZERO, 0, ~0, PAGE_SIZE, 0, VM_MEMATTR_WRITE_COMBINING); 1194 if (sc->gatt->ag_virtual == NULL) { 1195 if (bootverbose) 1196 device_printf(dev, "contiguous allocation failed\n"); 1197 return (ENOMEM); 1198 } 1199 1200 sc->gatt->ag_physical = vtophys((vm_offset_t)sc->gatt->ag_virtual); 1201 /* Install the GATT. */ 1202 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 1203 sc->gatt->ag_physical | 1); 1204 return (0); 1205 } 1206 1207 static void 1208 agp_i830_install_gatt_init(struct agp_i810_softc *sc) 1209 { 1210 uint32_t pgtblctl; 1211 1212 /* 1213 * The i830 automatically initializes the 128k gatt on boot. 1214 * GATT address is already in there, make sure it's enabled. 1215 */ 1216 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); 1217 pgtblctl |= 1; 1218 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); 1219 1220 sc->gatt->ag_physical = pgtblctl & ~1; 1221 } 1222 1223 static int 1224 agp_i830_install_gatt(device_t dev) 1225 { 1226 struct agp_i810_softc *sc; 1227 1228 sc = device_get_softc(dev); 1229 agp_i830_install_gatt_init(sc); 1230 return (0); 1231 } 1232 1233 static int 1234 agp_gen4_install_gatt(device_t dev, const vm_size_t gtt_offset) 1235 { 1236 struct agp_i810_softc *sc; 1237 1238 sc = device_get_softc(dev); 1239 pmap_change_attr((vm_offset_t)rman_get_virtual(sc->sc_res[0]) + 1240 gtt_offset, rman_get_size(sc->sc_res[0]) - gtt_offset, 1241 VM_MEMATTR_WRITE_COMBINING); 1242 agp_i830_install_gatt_init(sc); 1243 return (0); 1244 } 1245 1246 static int 1247 agp_i965_install_gatt(device_t dev) 1248 { 1249 1250 return (agp_gen4_install_gatt(dev, 512 * 1024)); 1251 } 1252 1253 static int 1254 agp_g4x_install_gatt(device_t dev) 1255 { 1256 1257 return (agp_gen4_install_gatt(dev, 2 * 1024 * 1024)); 1258 } 1259 1260 static int 1261 agp_i810_attach(device_t dev) 1262 { 1263 struct agp_i810_softc *sc; 1264 int error; 1265 1266 sc = device_get_softc(dev); 1267 sc->bdev = agp_i810_find_bridge(dev); 1268 if (sc->bdev == NULL) 1269 return (ENOENT); 1270 1271 sc->match = agp_i810_match(dev); 1272 1273 agp_set_aperture_resource(dev, sc->match->driver->gen <= 2 ? 1274 AGP_APBASE : AGP_I915_GMADR); 1275 error = agp_generic_attach(dev); 1276 if (error) 1277 return (error); 1278 1279 if (ptoa((vm_paddr_t)Maxmem) > 1280 (1ULL << sc->match->driver->busdma_addr_mask_sz) - 1) { 1281 device_printf(dev, "agp_i810 does not support physical " 1282 "memory above %ju.\n", (uintmax_t)(1ULL << 1283 sc->match->driver->busdma_addr_mask_sz) - 1); 1284 return (ENOENT); 1285 } 1286 1287 if (bus_alloc_resources(dev, sc->match->driver->res_spec, sc->sc_res)) { 1288 agp_generic_detach(dev); 1289 return (ENODEV); 1290 } 1291 1292 sc->initial_aperture = AGP_GET_APERTURE(dev); 1293 sc->gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_WAITOK); 1294 sc->gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT; 1295 1296 if ((error = sc->match->driver->get_stolen_size(dev)) != 0 || 1297 (error = sc->match->driver->install_gatt(dev)) != 0 || 1298 (error = sc->match->driver->get_gtt_mappable_entries(dev)) != 0 || 1299 (error = sc->match->driver->get_gtt_total_entries(dev)) != 0 || 1300 (error = sc->match->driver->chipset_flush_setup(dev)) != 0) { 1301 bus_release_resources(dev, sc->match->driver->res_spec, 1302 sc->sc_res); 1303 free(sc->gatt, M_AGP); 1304 agp_generic_detach(dev); 1305 return (error); 1306 } 1307 1308 intel_agp = dev; 1309 device_printf(dev, "aperture size is %dM", 1310 sc->initial_aperture / 1024 / 1024); 1311 if (sc->stolen > 0) 1312 printf(", detected %dk stolen memory\n", sc->stolen * 4); 1313 else 1314 printf("\n"); 1315 if (bootverbose) { 1316 sc->match->driver->dump_regs(dev); 1317 device_printf(dev, "Mappable GTT entries: %d\n", 1318 sc->gtt_mappable_entries); 1319 device_printf(dev, "Total GTT entries: %d\n", 1320 sc->gtt_total_entries); 1321 } 1322 return (0); 1323 } 1324 1325 static void 1326 agp_i810_deinstall_gatt(device_t dev) 1327 { 1328 struct agp_i810_softc *sc; 1329 1330 sc = device_get_softc(dev); 1331 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0); 1332 kmem_free((vm_offset_t)sc->gatt->ag_virtual, 64 * 1024); 1333 } 1334 1335 static void 1336 agp_i830_deinstall_gatt(device_t dev) 1337 { 1338 struct agp_i810_softc *sc; 1339 unsigned int pgtblctl; 1340 1341 sc = device_get_softc(dev); 1342 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); 1343 pgtblctl &= ~1; 1344 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); 1345 } 1346 1347 static int 1348 agp_i810_detach(device_t dev) 1349 { 1350 struct agp_i810_softc *sc; 1351 1352 sc = device_get_softc(dev); 1353 agp_free_cdev(dev); 1354 1355 /* Clear the GATT base. */ 1356 sc->match->driver->deinstall_gatt(dev); 1357 1358 sc->match->driver->chipset_flush_teardown(dev); 1359 1360 /* Put the aperture back the way it started. */ 1361 AGP_SET_APERTURE(dev, sc->initial_aperture); 1362 1363 free(sc->gatt, M_AGP); 1364 bus_release_resources(dev, sc->match->driver->res_spec, sc->sc_res); 1365 agp_free_res(dev); 1366 1367 return (0); 1368 } 1369 1370 static int 1371 agp_i810_resume(device_t dev) 1372 { 1373 struct agp_i810_softc *sc; 1374 sc = device_get_softc(dev); 1375 1376 AGP_SET_APERTURE(dev, sc->initial_aperture); 1377 1378 /* Install the GATT. */ 1379 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 1380 sc->gatt->ag_physical | 1); 1381 1382 return (bus_generic_resume(dev)); 1383 } 1384 1385 /** 1386 * Sets the PCI resource size of the aperture on i830-class and below chipsets, 1387 * while returning failure on later chipsets when an actual change is 1388 * requested. 1389 * 1390 * This whole function is likely bogus, as the kernel would probably need to 1391 * reconfigure the placement of the AGP aperture if a larger size is requested, 1392 * which doesn't happen currently. 1393 */ 1394 static int 1395 agp_i810_set_aperture(device_t dev, u_int32_t aperture) 1396 { 1397 struct agp_i810_softc *sc; 1398 u_int16_t miscc; 1399 1400 sc = device_get_softc(dev); 1401 /* 1402 * Double check for sanity. 1403 */ 1404 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) { 1405 device_printf(dev, "bad aperture size %d\n", aperture); 1406 return (EINVAL); 1407 } 1408 1409 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); 1410 miscc &= ~AGP_I810_MISCC_WINSIZE; 1411 if (aperture == 32 * 1024 * 1024) 1412 miscc |= AGP_I810_MISCC_WINSIZE_32; 1413 else 1414 miscc |= AGP_I810_MISCC_WINSIZE_64; 1415 1416 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2); 1417 return (0); 1418 } 1419 1420 static int 1421 agp_i830_set_aperture(device_t dev, u_int32_t aperture) 1422 { 1423 struct agp_i810_softc *sc; 1424 u_int16_t gcc1; 1425 1426 sc = device_get_softc(dev); 1427 1428 if (aperture != 64 * 1024 * 1024 && 1429 aperture != 128 * 1024 * 1024) { 1430 device_printf(dev, "bad aperture size %d\n", aperture); 1431 return (EINVAL); 1432 } 1433 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); 1434 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 1435 if (aperture == 64 * 1024 * 1024) 1436 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 1437 else 1438 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 1439 1440 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2); 1441 return (0); 1442 } 1443 1444 static int 1445 agp_i915_set_aperture(device_t dev, u_int32_t aperture) 1446 { 1447 1448 return (agp_generic_set_aperture(dev, aperture)); 1449 } 1450 1451 static int 1452 agp_i810_method_set_aperture(device_t dev, u_int32_t aperture) 1453 { 1454 struct agp_i810_softc *sc; 1455 1456 sc = device_get_softc(dev); 1457 return (sc->match->driver->set_aperture(dev, aperture)); 1458 } 1459 1460 /** 1461 * Writes a GTT entry mapping the page at the given offset from the 1462 * beginning of the aperture to the given physical address. Setup the 1463 * caching mode according to flags. 1464 * 1465 * For gen 1, 2 and 3, GTT start is located at AGP_I810_GTT offset 1466 * from corresponding BAR start. For gen 4, offset is 512KB + 1467 * AGP_I810_GTT, for gen 5 and 6 it is 2MB + AGP_I810_GTT. 1468 * 1469 * Also, the bits of the physical page address above 4GB needs to be 1470 * placed into bits 40-32 of PTE. 1471 */ 1472 static void 1473 agp_i810_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical, 1474 int flags) 1475 { 1476 uint32_t pte; 1477 1478 pte = (u_int32_t)physical | I810_PTE_VALID; 1479 if (flags == AGP_DCACHE_MEMORY) 1480 pte |= I810_PTE_LOCAL; 1481 else if (flags == AGP_USER_CACHED_MEMORY) 1482 pte |= I830_PTE_SYSTEM_CACHED; 1483 agp_i810_write_gtt(dev, index, pte); 1484 } 1485 1486 static void 1487 agp_i810_write_gtt(device_t dev, u_int index, uint32_t pte) 1488 { 1489 struct agp_i810_softc *sc; 1490 1491 sc = device_get_softc(dev); 1492 bus_write_4(sc->sc_res[0], AGP_I810_GTT + index * 4, pte); 1493 CTR2(KTR_AGP_I810, "810_pte %x %x", index, pte); 1494 } 1495 1496 static void 1497 agp_i830_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical, 1498 int flags) 1499 { 1500 uint32_t pte; 1501 1502 pte = (u_int32_t)physical | I810_PTE_VALID; 1503 if (flags == AGP_USER_CACHED_MEMORY) 1504 pte |= I830_PTE_SYSTEM_CACHED; 1505 agp_i810_write_gtt(dev, index, pte); 1506 } 1507 1508 static void 1509 agp_i915_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical, 1510 int flags) 1511 { 1512 uint32_t pte; 1513 1514 pte = (u_int32_t)physical | I810_PTE_VALID; 1515 if (flags == AGP_USER_CACHED_MEMORY) 1516 pte |= I830_PTE_SYSTEM_CACHED; 1517 pte |= (physical & 0x0000000f00000000ull) >> 28; 1518 agp_i915_write_gtt(dev, index, pte); 1519 } 1520 1521 static void 1522 agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte) 1523 { 1524 struct agp_i810_softc *sc; 1525 1526 sc = device_get_softc(dev); 1527 bus_write_4(sc->sc_res[1], index * 4, pte); 1528 CTR2(KTR_AGP_I810, "915_pte %x %x", index, pte); 1529 } 1530 1531 static void 1532 agp_i965_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical, 1533 int flags) 1534 { 1535 uint32_t pte; 1536 1537 pte = (u_int32_t)physical | I810_PTE_VALID; 1538 if (flags == AGP_USER_CACHED_MEMORY) 1539 pte |= I830_PTE_SYSTEM_CACHED; 1540 pte |= (physical & 0x0000000f00000000ull) >> 28; 1541 agp_i965_write_gtt(dev, index, pte); 1542 } 1543 1544 static void 1545 agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte) 1546 { 1547 struct agp_i810_softc *sc; 1548 1549 sc = device_get_softc(dev); 1550 bus_write_4(sc->sc_res[0], index * 4 + (512 * 1024), pte); 1551 CTR2(KTR_AGP_I810, "965_pte %x %x", index, pte); 1552 } 1553 1554 static void 1555 agp_g4x_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical, 1556 int flags) 1557 { 1558 uint32_t pte; 1559 1560 pte = (u_int32_t)physical | I810_PTE_VALID; 1561 if (flags == AGP_USER_CACHED_MEMORY) 1562 pte |= I830_PTE_SYSTEM_CACHED; 1563 pte |= (physical & 0x0000000f00000000ull) >> 28; 1564 agp_g4x_write_gtt(dev, index, pte); 1565 } 1566 1567 static void 1568 agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte) 1569 { 1570 struct agp_i810_softc *sc; 1571 1572 sc = device_get_softc(dev); 1573 bus_write_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024), pte); 1574 CTR2(KTR_AGP_I810, "g4x_pte %x %x", index, pte); 1575 } 1576 1577 static int 1578 agp_i810_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical) 1579 { 1580 struct agp_i810_softc *sc = device_get_softc(dev); 1581 u_int index; 1582 1583 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 1584 device_printf(dev, "failed: offset is 0x%08jx, " 1585 "shift is %d, entries is %d\n", (intmax_t)offset, 1586 AGP_PAGE_SHIFT, sc->gatt->ag_entries); 1587 return (EINVAL); 1588 } 1589 index = offset >> AGP_PAGE_SHIFT; 1590 if (sc->stolen != 0 && index < sc->stolen) { 1591 device_printf(dev, "trying to bind into stolen memory\n"); 1592 return (EINVAL); 1593 } 1594 sc->match->driver->install_gtt_pte(dev, index, physical, 0); 1595 return (0); 1596 } 1597 1598 static int 1599 agp_i810_unbind_page(device_t dev, vm_offset_t offset) 1600 { 1601 struct agp_i810_softc *sc; 1602 u_int index; 1603 1604 sc = device_get_softc(dev); 1605 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 1606 return (EINVAL); 1607 index = offset >> AGP_PAGE_SHIFT; 1608 if (sc->stolen != 0 && index < sc->stolen) { 1609 device_printf(dev, "trying to unbind from stolen memory\n"); 1610 return (EINVAL); 1611 } 1612 sc->match->driver->install_gtt_pte(dev, index, 0, 0); 1613 return (0); 1614 } 1615 1616 static u_int32_t 1617 agp_i810_read_gtt_pte(device_t dev, u_int index) 1618 { 1619 struct agp_i810_softc *sc; 1620 u_int32_t pte; 1621 1622 sc = device_get_softc(dev); 1623 pte = bus_read_4(sc->sc_res[0], AGP_I810_GTT + index * 4); 1624 return (pte); 1625 } 1626 1627 static u_int32_t 1628 agp_i915_read_gtt_pte(device_t dev, u_int index) 1629 { 1630 struct agp_i810_softc *sc; 1631 u_int32_t pte; 1632 1633 sc = device_get_softc(dev); 1634 pte = bus_read_4(sc->sc_res[1], index * 4); 1635 return (pte); 1636 } 1637 1638 static u_int32_t 1639 agp_i965_read_gtt_pte(device_t dev, u_int index) 1640 { 1641 struct agp_i810_softc *sc; 1642 u_int32_t pte; 1643 1644 sc = device_get_softc(dev); 1645 pte = bus_read_4(sc->sc_res[0], index * 4 + (512 * 1024)); 1646 return (pte); 1647 } 1648 1649 static u_int32_t 1650 agp_g4x_read_gtt_pte(device_t dev, u_int index) 1651 { 1652 struct agp_i810_softc *sc; 1653 u_int32_t pte; 1654 1655 sc = device_get_softc(dev); 1656 pte = bus_read_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024)); 1657 return (pte); 1658 } 1659 1660 static vm_paddr_t 1661 agp_i810_read_gtt_pte_paddr(device_t dev, u_int index) 1662 { 1663 struct agp_i810_softc *sc; 1664 u_int32_t pte; 1665 vm_paddr_t res; 1666 1667 sc = device_get_softc(dev); 1668 pte = sc->match->driver->read_gtt_pte(dev, index); 1669 res = pte & ~PAGE_MASK; 1670 return (res); 1671 } 1672 1673 static vm_paddr_t 1674 agp_i915_read_gtt_pte_paddr(device_t dev, u_int index) 1675 { 1676 struct agp_i810_softc *sc; 1677 u_int32_t pte; 1678 vm_paddr_t res; 1679 1680 sc = device_get_softc(dev); 1681 pte = sc->match->driver->read_gtt_pte(dev, index); 1682 res = (pte & ~PAGE_MASK) | ((pte & 0xf0) << 28); 1683 return (res); 1684 } 1685 1686 /* 1687 * Writing via memory mapped registers already flushes all TLBs. 1688 */ 1689 static void 1690 agp_i810_flush_tlb(device_t dev) 1691 { 1692 } 1693 1694 static int 1695 agp_i810_enable(device_t dev, u_int32_t mode) 1696 { 1697 1698 return (0); 1699 } 1700 1701 static struct agp_memory * 1702 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size) 1703 { 1704 struct agp_i810_softc *sc; 1705 struct agp_memory *mem; 1706 vm_page_t m; 1707 1708 sc = device_get_softc(dev); 1709 1710 if ((size & (AGP_PAGE_SIZE - 1)) != 0 || 1711 sc->agp.as_allocated + size > sc->agp.as_maxmem) 1712 return (0); 1713 1714 if (type == 1) { 1715 /* 1716 * Mapping local DRAM into GATT. 1717 */ 1718 if (sc->match->driver->chiptype != CHIP_I810) 1719 return (0); 1720 if (size != sc->dcache_size) 1721 return (0); 1722 } else if (type == 2) { 1723 /* 1724 * Type 2 is the contiguous physical memory type, that hands 1725 * back a physical address. This is used for cursors on i810. 1726 * Hand back as many single pages with physical as the user 1727 * wants, but only allow one larger allocation (ARGB cursor) 1728 * for simplicity. 1729 */ 1730 if (size != AGP_PAGE_SIZE) { 1731 if (sc->argb_cursor != NULL) 1732 return (0); 1733 1734 /* Allocate memory for ARGB cursor, if we can. */ 1735 sc->argb_cursor = contigmalloc(size, M_AGP, 1736 0, 0, ~0, PAGE_SIZE, 0); 1737 if (sc->argb_cursor == NULL) 1738 return (0); 1739 } 1740 } 1741 1742 mem = malloc(sizeof *mem, M_AGP, M_WAITOK); 1743 mem->am_id = sc->agp.as_nextid++; 1744 mem->am_size = size; 1745 mem->am_type = type; 1746 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE)) 1747 mem->am_obj = vm_object_allocate(OBJT_DEFAULT, 1748 atop(round_page(size))); 1749 else 1750 mem->am_obj = 0; 1751 1752 if (type == 2) { 1753 if (size == AGP_PAGE_SIZE) { 1754 /* 1755 * Allocate and wire down the page now so that we can 1756 * get its physical address. 1757 */ 1758 VM_OBJECT_WLOCK(mem->am_obj); 1759 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY | 1760 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1761 VM_OBJECT_WUNLOCK(mem->am_obj); 1762 mem->am_physical = VM_PAGE_TO_PHYS(m); 1763 } else { 1764 /* Our allocation is already nicely wired down for us. 1765 * Just grab the physical address. 1766 */ 1767 mem->am_physical = vtophys(sc->argb_cursor); 1768 } 1769 } else 1770 mem->am_physical = 0; 1771 1772 mem->am_offset = 0; 1773 mem->am_is_bound = 0; 1774 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link); 1775 sc->agp.as_allocated += size; 1776 1777 return (mem); 1778 } 1779 1780 static int 1781 agp_i810_free_memory(device_t dev, struct agp_memory *mem) 1782 { 1783 struct agp_i810_softc *sc; 1784 vm_page_t m; 1785 1786 if (mem->am_is_bound) 1787 return (EBUSY); 1788 1789 sc = device_get_softc(dev); 1790 1791 if (mem->am_type == 2) { 1792 if (mem->am_size == AGP_PAGE_SIZE) { 1793 /* 1794 * Unwire the page which we wired in alloc_memory. 1795 */ 1796 VM_OBJECT_WLOCK(mem->am_obj); 1797 m = vm_page_lookup(mem->am_obj, 0); 1798 vm_page_unwire(m, PQ_INACTIVE); 1799 VM_OBJECT_WUNLOCK(mem->am_obj); 1800 } else { 1801 contigfree(sc->argb_cursor, mem->am_size, M_AGP); 1802 sc->argb_cursor = NULL; 1803 } 1804 } 1805 1806 sc->agp.as_allocated -= mem->am_size; 1807 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link); 1808 if (mem->am_obj) 1809 vm_object_deallocate(mem->am_obj); 1810 free(mem, M_AGP); 1811 return (0); 1812 } 1813 1814 static int 1815 agp_i810_bind_memory(device_t dev, struct agp_memory *mem, vm_offset_t offset) 1816 { 1817 struct agp_i810_softc *sc; 1818 vm_offset_t i; 1819 1820 /* Do some sanity checks first. */ 1821 if ((offset & (AGP_PAGE_SIZE - 1)) != 0 || 1822 offset + mem->am_size > AGP_GET_APERTURE(dev)) { 1823 device_printf(dev, "binding memory at bad offset %#x\n", 1824 (int)offset); 1825 return (EINVAL); 1826 } 1827 1828 sc = device_get_softc(dev); 1829 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { 1830 mtx_lock(&sc->agp.as_lock); 1831 if (mem->am_is_bound) { 1832 mtx_unlock(&sc->agp.as_lock); 1833 return (EINVAL); 1834 } 1835 /* The memory's already wired down, just stick it in the GTT. */ 1836 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1837 sc->match->driver->install_gtt_pte(dev, (offset + i) >> 1838 AGP_PAGE_SHIFT, mem->am_physical + i, 0); 1839 } 1840 mem->am_offset = offset; 1841 mem->am_is_bound = 1; 1842 mtx_unlock(&sc->agp.as_lock); 1843 return (0); 1844 } 1845 1846 if (mem->am_type != 1) 1847 return (agp_generic_bind_memory(dev, mem, offset)); 1848 1849 /* 1850 * Mapping local DRAM into GATT. 1851 */ 1852 if (sc->match->driver->chiptype != CHIP_I810) 1853 return (EINVAL); 1854 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1855 bus_write_4(sc->sc_res[0], 1856 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3); 1857 1858 return (0); 1859 } 1860 1861 static int 1862 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem) 1863 { 1864 struct agp_i810_softc *sc; 1865 vm_offset_t i; 1866 1867 sc = device_get_softc(dev); 1868 1869 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { 1870 mtx_lock(&sc->agp.as_lock); 1871 if (!mem->am_is_bound) { 1872 mtx_unlock(&sc->agp.as_lock); 1873 return (EINVAL); 1874 } 1875 1876 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1877 sc->match->driver->install_gtt_pte(dev, 1878 (mem->am_offset + i) >> AGP_PAGE_SHIFT, 0, 0); 1879 } 1880 mem->am_is_bound = 0; 1881 mtx_unlock(&sc->agp.as_lock); 1882 return (0); 1883 } 1884 1885 if (mem->am_type != 1) 1886 return (agp_generic_unbind_memory(dev, mem)); 1887 1888 if (sc->match->driver->chiptype != CHIP_I810) 1889 return (EINVAL); 1890 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1891 sc->match->driver->install_gtt_pte(dev, i >> AGP_PAGE_SHIFT, 1892 0, 0); 1893 } 1894 return (0); 1895 } 1896 1897 static device_method_t agp_i810_methods[] = { 1898 /* Device interface */ 1899 DEVMETHOD(device_identify, agp_i810_identify), 1900 DEVMETHOD(device_probe, agp_i810_probe), 1901 DEVMETHOD(device_attach, agp_i810_attach), 1902 DEVMETHOD(device_detach, agp_i810_detach), 1903 DEVMETHOD(device_suspend, bus_generic_suspend), 1904 DEVMETHOD(device_resume, agp_i810_resume), 1905 1906 /* AGP interface */ 1907 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture), 1908 DEVMETHOD(agp_set_aperture, agp_i810_method_set_aperture), 1909 DEVMETHOD(agp_bind_page, agp_i810_bind_page), 1910 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page), 1911 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb), 1912 DEVMETHOD(agp_enable, agp_i810_enable), 1913 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory), 1914 DEVMETHOD(agp_free_memory, agp_i810_free_memory), 1915 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory), 1916 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory), 1917 DEVMETHOD(agp_chipset_flush, agp_intel_gtt_chipset_flush), 1918 { 0, 0 } 1919 }; 1920 1921 static driver_t agp_i810_driver = { 1922 "agp", 1923 agp_i810_methods, 1924 sizeof(struct agp_i810_softc), 1925 }; 1926 1927 static devclass_t agp_devclass; 1928 1929 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0); 1930 MODULE_DEPEND(agp_i810, agp, 1, 1, 1); 1931 MODULE_DEPEND(agp_i810, pci, 1, 1, 1); 1932 1933 void 1934 agp_intel_gtt_clear_range(device_t dev, u_int first_entry, u_int num_entries) 1935 { 1936 struct agp_i810_softc *sc; 1937 u_int i; 1938 1939 sc = device_get_softc(dev); 1940 for (i = 0; i < num_entries; i++) 1941 sc->match->driver->install_gtt_pte(dev, first_entry + i, 1942 VM_PAGE_TO_PHYS(bogus_page), 0); 1943 sc->match->driver->read_gtt_pte(dev, first_entry + num_entries - 1); 1944 } 1945 1946 void 1947 agp_intel_gtt_insert_pages(device_t dev, u_int first_entry, u_int num_entries, 1948 vm_page_t *pages, u_int flags) 1949 { 1950 struct agp_i810_softc *sc; 1951 u_int i; 1952 1953 sc = device_get_softc(dev); 1954 for (i = 0; i < num_entries; i++) { 1955 MPASS(pages[i]->valid == VM_PAGE_BITS_ALL); 1956 MPASS(pages[i]->ref_count > 0); 1957 sc->match->driver->install_gtt_pte(dev, first_entry + i, 1958 VM_PAGE_TO_PHYS(pages[i]), flags); 1959 } 1960 sc->match->driver->read_gtt_pte(dev, first_entry + num_entries - 1); 1961 } 1962 1963 struct intel_gtt 1964 agp_intel_gtt_get(device_t dev) 1965 { 1966 struct agp_i810_softc *sc; 1967 struct intel_gtt res; 1968 1969 sc = device_get_softc(dev); 1970 res.stolen_size = sc->stolen_size; 1971 res.gtt_total_entries = sc->gtt_total_entries; 1972 res.gtt_mappable_entries = sc->gtt_mappable_entries; 1973 res.do_idle_maps = 0; 1974 res.scratch_page_dma = VM_PAGE_TO_PHYS(bogus_page); 1975 if (sc->agp.as_aperture != NULL) 1976 res.gma_bus_addr = rman_get_start(sc->agp.as_aperture); 1977 else 1978 res.gma_bus_addr = 0; 1979 return (res); 1980 } 1981 1982 static int 1983 agp_i810_chipset_flush_setup(device_t dev) 1984 { 1985 1986 return (0); 1987 } 1988 1989 static void 1990 agp_i810_chipset_flush_teardown(device_t dev) 1991 { 1992 1993 /* Nothing to do. */ 1994 } 1995 1996 static void 1997 agp_i810_chipset_flush(device_t dev) 1998 { 1999 2000 /* Nothing to do. */ 2001 } 2002 2003 static void 2004 agp_i830_chipset_flush(device_t dev) 2005 { 2006 struct agp_i810_softc *sc; 2007 uint32_t hic; 2008 int i; 2009 2010 sc = device_get_softc(dev); 2011 pmap_invalidate_cache(); 2012 hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC); 2013 bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1U << 31)); 2014 for (i = 0; i < 20000 /* 1 sec */; i++) { 2015 hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC); 2016 if ((hic & (1U << 31)) == 0) 2017 break; 2018 DELAY(50); 2019 } 2020 } 2021 2022 static int 2023 agp_i915_chipset_flush_alloc_page(device_t dev, uint64_t start, uint64_t end) 2024 { 2025 struct agp_i810_softc *sc; 2026 device_t vga; 2027 2028 sc = device_get_softc(dev); 2029 vga = device_get_parent(dev); 2030 sc->sc_flush_page_rid = 100; 2031 sc->sc_flush_page_res = BUS_ALLOC_RESOURCE(device_get_parent(vga), dev, 2032 SYS_RES_MEMORY, &sc->sc_flush_page_rid, start, end, PAGE_SIZE, 2033 RF_ACTIVE); 2034 if (sc->sc_flush_page_res == NULL) { 2035 device_printf(dev, "Failed to allocate flush page at 0x%jx\n", 2036 (uintmax_t)start); 2037 return (EINVAL); 2038 } 2039 sc->sc_flush_page_vaddr = rman_get_virtual(sc->sc_flush_page_res); 2040 if (bootverbose) { 2041 device_printf(dev, "Allocated flush page phys 0x%jx virt %p\n", 2042 (uintmax_t)rman_get_start(sc->sc_flush_page_res), 2043 sc->sc_flush_page_vaddr); 2044 } 2045 return (0); 2046 } 2047 2048 static void 2049 agp_i915_chipset_flush_free_page(device_t dev) 2050 { 2051 struct agp_i810_softc *sc; 2052 device_t vga; 2053 2054 sc = device_get_softc(dev); 2055 vga = device_get_parent(dev); 2056 if (sc->sc_flush_page_res == NULL) 2057 return; 2058 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev, SYS_RES_MEMORY, 2059 sc->sc_flush_page_rid, sc->sc_flush_page_res); 2060 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev, SYS_RES_MEMORY, 2061 sc->sc_flush_page_rid, sc->sc_flush_page_res); 2062 } 2063 2064 static int 2065 agp_i915_chipset_flush_setup(device_t dev) 2066 { 2067 struct agp_i810_softc *sc; 2068 uint32_t temp; 2069 int error; 2070 2071 sc = device_get_softc(dev); 2072 temp = pci_read_config(sc->bdev, AGP_I915_IFPADDR, 4); 2073 if ((temp & 1) != 0) { 2074 temp &= ~1; 2075 if (bootverbose) 2076 device_printf(dev, 2077 "Found already configured flush page at 0x%jx\n", 2078 (uintmax_t)temp); 2079 sc->sc_bios_allocated_flush_page = 1; 2080 /* 2081 * In the case BIOS initialized the flush pointer (?) 2082 * register, expect that BIOS also set up the resource 2083 * for the page. 2084 */ 2085 error = agp_i915_chipset_flush_alloc_page(dev, temp, 2086 temp + PAGE_SIZE - 1); 2087 if (error != 0) 2088 return (error); 2089 } else { 2090 sc->sc_bios_allocated_flush_page = 0; 2091 error = agp_i915_chipset_flush_alloc_page(dev, 0, 0xffffffff); 2092 if (error != 0) 2093 return (error); 2094 temp = rman_get_start(sc->sc_flush_page_res); 2095 pci_write_config(sc->bdev, AGP_I915_IFPADDR, temp | 1, 4); 2096 } 2097 return (0); 2098 } 2099 2100 static void 2101 agp_i915_chipset_flush_teardown(device_t dev) 2102 { 2103 struct agp_i810_softc *sc; 2104 uint32_t temp; 2105 2106 sc = device_get_softc(dev); 2107 if (sc->sc_flush_page_res == NULL) 2108 return; 2109 if (!sc->sc_bios_allocated_flush_page) { 2110 temp = pci_read_config(sc->bdev, AGP_I915_IFPADDR, 4); 2111 temp &= ~1; 2112 pci_write_config(sc->bdev, AGP_I915_IFPADDR, temp, 4); 2113 } 2114 agp_i915_chipset_flush_free_page(dev); 2115 } 2116 2117 static int 2118 agp_i965_chipset_flush_setup(device_t dev) 2119 { 2120 struct agp_i810_softc *sc; 2121 uint64_t temp; 2122 uint32_t temp_hi, temp_lo; 2123 int error; 2124 2125 sc = device_get_softc(dev); 2126 2127 temp_hi = pci_read_config(sc->bdev, AGP_I965_IFPADDR + 4, 4); 2128 temp_lo = pci_read_config(sc->bdev, AGP_I965_IFPADDR, 4); 2129 2130 if ((temp_lo & 1) != 0) { 2131 temp = ((uint64_t)temp_hi << 32) | (temp_lo & ~1); 2132 if (bootverbose) 2133 device_printf(dev, 2134 "Found already configured flush page at 0x%jx\n", 2135 (uintmax_t)temp); 2136 sc->sc_bios_allocated_flush_page = 1; 2137 /* 2138 * In the case BIOS initialized the flush pointer (?) 2139 * register, expect that BIOS also set up the resource 2140 * for the page. 2141 */ 2142 error = agp_i915_chipset_flush_alloc_page(dev, temp, 2143 temp + PAGE_SIZE - 1); 2144 if (error != 0) 2145 return (error); 2146 } else { 2147 sc->sc_bios_allocated_flush_page = 0; 2148 error = agp_i915_chipset_flush_alloc_page(dev, 0, ~0); 2149 if (error != 0) 2150 return (error); 2151 temp = rman_get_start(sc->sc_flush_page_res); 2152 pci_write_config(sc->bdev, AGP_I965_IFPADDR + 4, 2153 (temp >> 32) & UINT32_MAX, 4); 2154 pci_write_config(sc->bdev, AGP_I965_IFPADDR, 2155 (temp & UINT32_MAX) | 1, 4); 2156 } 2157 return (0); 2158 } 2159 2160 static void 2161 agp_i965_chipset_flush_teardown(device_t dev) 2162 { 2163 struct agp_i810_softc *sc; 2164 uint32_t temp_lo; 2165 2166 sc = device_get_softc(dev); 2167 if (sc->sc_flush_page_res == NULL) 2168 return; 2169 if (!sc->sc_bios_allocated_flush_page) { 2170 temp_lo = pci_read_config(sc->bdev, AGP_I965_IFPADDR, 4); 2171 temp_lo &= ~1; 2172 pci_write_config(sc->bdev, AGP_I965_IFPADDR, temp_lo, 4); 2173 } 2174 agp_i915_chipset_flush_free_page(dev); 2175 } 2176 2177 static void 2178 agp_i915_chipset_flush(device_t dev) 2179 { 2180 struct agp_i810_softc *sc; 2181 2182 sc = device_get_softc(dev); 2183 *(uint32_t *)sc->sc_flush_page_vaddr = 1; 2184 } 2185 2186 int 2187 agp_intel_gtt_chipset_flush(device_t dev) 2188 { 2189 struct agp_i810_softc *sc; 2190 2191 sc = device_get_softc(dev); 2192 sc->match->driver->chipset_flush(dev); 2193 return (0); 2194 } 2195 2196 void 2197 agp_intel_gtt_unmap_memory(device_t dev, struct sglist *sg_list) 2198 { 2199 } 2200 2201 int 2202 agp_intel_gtt_map_memory(device_t dev, vm_page_t *pages, u_int num_entries, 2203 struct sglist **sg_list) 2204 { 2205 struct agp_i810_softc *sc; 2206 struct sglist *sg; 2207 int i; 2208 #if 0 2209 int error; 2210 bus_dma_tag_t dmat; 2211 #endif 2212 2213 if (*sg_list != NULL) 2214 return (0); 2215 sc = device_get_softc(dev); 2216 sg = sglist_alloc(num_entries, M_WAITOK /* XXXKIB */); 2217 for (i = 0; i < num_entries; i++) { 2218 sg->sg_segs[i].ss_paddr = VM_PAGE_TO_PHYS(pages[i]); 2219 sg->sg_segs[i].ss_len = PAGE_SIZE; 2220 } 2221 2222 #if 0 2223 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2224 1 /* alignment */, 0 /* boundary */, 2225 1ULL << sc->match->busdma_addr_mask_sz /* lowaddr */, 2226 BUS_SPACE_MAXADDR /* highaddr */, 2227 NULL /* filtfunc */, NULL /* filtfuncarg */, 2228 BUS_SPACE_MAXADDR /* maxsize */, 2229 BUS_SPACE_UNRESTRICTED /* nsegments */, 2230 BUS_SPACE_MAXADDR /* maxsegsz */, 2231 0 /* flags */, NULL /* lockfunc */, NULL /* lockfuncarg */, 2232 &dmat); 2233 if (error != 0) { 2234 sglist_free(sg); 2235 return (error); 2236 } 2237 /* XXXKIB */ 2238 #endif 2239 *sg_list = sg; 2240 return (0); 2241 } 2242 2243 static void 2244 agp_intel_gtt_install_pte(device_t dev, u_int index, vm_paddr_t addr, 2245 u_int flags) 2246 { 2247 struct agp_i810_softc *sc; 2248 2249 sc = device_get_softc(dev); 2250 sc->match->driver->install_gtt_pte(dev, index, addr, flags); 2251 } 2252 2253 void 2254 agp_intel_gtt_insert_sg_entries(device_t dev, struct sglist *sg_list, 2255 u_int first_entry, u_int flags) 2256 { 2257 struct agp_i810_softc *sc; 2258 vm_paddr_t spaddr; 2259 size_t slen; 2260 u_int i, j; 2261 2262 sc = device_get_softc(dev); 2263 for (i = j = 0; j < sg_list->sg_nseg; j++) { 2264 spaddr = sg_list->sg_segs[i].ss_paddr; 2265 slen = sg_list->sg_segs[i].ss_len; 2266 for (; slen > 0; i++) { 2267 sc->match->driver->install_gtt_pte(dev, first_entry + i, 2268 spaddr, flags); 2269 spaddr += AGP_PAGE_SIZE; 2270 slen -= AGP_PAGE_SIZE; 2271 } 2272 } 2273 sc->match->driver->read_gtt_pte(dev, first_entry + i - 1); 2274 } 2275 2276 void 2277 intel_gtt_clear_range(u_int first_entry, u_int num_entries) 2278 { 2279 2280 agp_intel_gtt_clear_range(intel_agp, first_entry, num_entries); 2281 } 2282 2283 void 2284 intel_gtt_insert_pages(u_int first_entry, u_int num_entries, vm_page_t *pages, 2285 u_int flags) 2286 { 2287 2288 agp_intel_gtt_insert_pages(intel_agp, first_entry, num_entries, 2289 pages, flags); 2290 } 2291 2292 struct intel_gtt * 2293 intel_gtt_get(void) 2294 { 2295 2296 intel_private.base = agp_intel_gtt_get(intel_agp); 2297 return (&intel_private.base); 2298 } 2299 2300 int 2301 intel_gtt_chipset_flush(void) 2302 { 2303 2304 return (agp_intel_gtt_chipset_flush(intel_agp)); 2305 } 2306 2307 void 2308 intel_gtt_unmap_memory(struct sglist *sg_list) 2309 { 2310 2311 agp_intel_gtt_unmap_memory(intel_agp, sg_list); 2312 } 2313 2314 int 2315 intel_gtt_map_memory(vm_page_t *pages, u_int num_entries, 2316 struct sglist **sg_list) 2317 { 2318 2319 return (agp_intel_gtt_map_memory(intel_agp, pages, num_entries, 2320 sg_list)); 2321 } 2322 2323 void 2324 intel_gtt_insert_sg_entries(struct sglist *sg_list, u_int first_entry, 2325 u_int flags) 2326 { 2327 2328 agp_intel_gtt_insert_sg_entries(intel_agp, sg_list, first_entry, flags); 2329 } 2330 2331 void 2332 intel_gtt_install_pte(u_int index, vm_paddr_t addr, u_int flags) 2333 { 2334 2335 agp_intel_gtt_install_pte(intel_agp, index, addr, flags); 2336 } 2337 2338 device_t 2339 intel_gtt_get_bridge_device(void) 2340 { 2341 struct agp_i810_softc *sc; 2342 2343 sc = device_get_softc(intel_agp); 2344 return (sc->bdev); 2345 } 2346 2347 vm_paddr_t 2348 intel_gtt_read_pte_paddr(u_int entry) 2349 { 2350 struct agp_i810_softc *sc; 2351 2352 sc = device_get_softc(intel_agp); 2353 return (sc->match->driver->read_gtt_pte_paddr(intel_agp, entry)); 2354 } 2355 2356 u_int32_t 2357 intel_gtt_read_pte(u_int entry) 2358 { 2359 struct agp_i810_softc *sc; 2360 2361 sc = device_get_softc(intel_agp); 2362 return (sc->match->driver->read_gtt_pte(intel_agp, entry)); 2363 } 2364 2365 void 2366 intel_gtt_write(u_int entry, uint32_t val) 2367 { 2368 struct agp_i810_softc *sc; 2369 2370 sc = device_get_softc(intel_agp); 2371 return (sc->match->driver->write_gtt(intel_agp, entry, val)); 2372 } 2373