1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU111 4 * 5 * (C) Copyright 2017 - 2019, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/phy/phy.h> 17 18/ { 19 model = "ZynqMP ZCU111 RevA"; 20 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; 21 22 aliases { 23 ethernet0 = &gem3; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 mmc0 = &sdhci1; 27 rtc0 = &rtc; 28 serial0 = &uart0; 29 serial1 = &dcc; 30 }; 31 32 chosen { 33 bootargs = "earlycon"; 34 stdout-path = "serial0:115200n8"; 35 }; 36 37 memory@0 { 38 device_type = "memory"; 39 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 40 /* Another 4GB connected to PL */ 41 }; 42 43 gpio-keys { 44 compatible = "gpio-keys"; 45 autorepeat; 46 sw19 { 47 label = "sw19"; 48 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 49 linux,code = <KEY_DOWN>; 50 wakeup-source; 51 autorepeat; 52 }; 53 }; 54 55 leds { 56 compatible = "gpio-leds"; 57 heartbeat-led { 58 label = "heartbeat"; 59 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 60 linux,default-trigger = "heartbeat"; 61 }; 62 }; 63 64 ina226-u67 { 65 compatible = "iio-hwmon"; 66 io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; 67 }; 68 ina226-u59 { 69 compatible = "iio-hwmon"; 70 io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; 71 }; 72 ina226-u61 { 73 compatible = "iio-hwmon"; 74 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; 75 }; 76 ina226-u60 { 77 compatible = "iio-hwmon"; 78 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; 79 }; 80 ina226-u64 { 81 compatible = "iio-hwmon"; 82 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; 83 }; 84 ina226-u69 { 85 compatible = "iio-hwmon"; 86 io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; 87 }; 88 ina226-u66 { 89 compatible = "iio-hwmon"; 90 io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; 91 }; 92 ina226-u65 { 93 compatible = "iio-hwmon"; 94 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 95 }; 96 ina226-u63 { 97 compatible = "iio-hwmon"; 98 io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; 99 }; 100 ina226-u3 { 101 compatible = "iio-hwmon"; 102 io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; 103 }; 104 ina226-u71 { 105 compatible = "iio-hwmon"; 106 io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; 107 }; 108 ina226-u77 { 109 compatible = "iio-hwmon"; 110 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 111 }; 112 ina226-u73 { 113 compatible = "iio-hwmon"; 114 io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; 115 }; 116 ina226-u79 { 117 compatible = "iio-hwmon"; 118 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 119 }; 120 121 /* 48MHz reference crystal */ 122 ref48: ref48M { 123 compatible = "fixed-clock"; 124 #clock-cells = <0>; 125 clock-frequency = <48000000>; 126 }; 127}; 128 129&dcc { 130 status = "okay"; 131}; 132 133&fpd_dma_chan1 { 134 status = "okay"; 135}; 136 137&fpd_dma_chan2 { 138 status = "okay"; 139}; 140 141&fpd_dma_chan3 { 142 status = "okay"; 143}; 144 145&fpd_dma_chan4 { 146 status = "okay"; 147}; 148 149&fpd_dma_chan5 { 150 status = "okay"; 151}; 152 153&fpd_dma_chan6 { 154 status = "okay"; 155}; 156 157&fpd_dma_chan7 { 158 status = "okay"; 159}; 160 161&fpd_dma_chan8 { 162 status = "okay"; 163}; 164 165&gem3 { 166 status = "okay"; 167 phy-handle = <&phy0>; 168 phy-mode = "rgmii-id"; 169 phy0: ethernet-phy@c { 170 reg = <0xc>; 171 ti,rx-internal-delay = <0x8>; 172 ti,tx-internal-delay = <0xa>; 173 ti,fifo-depth = <0x1>; 174 ti,dp83867-rxctrl-strap-quirk; 175 }; 176}; 177 178&gpio { 179 status = "okay"; 180}; 181 182&i2c0 { 183 status = "okay"; 184 clock-frequency = <400000>; 185 186 tca6416_u22: gpio@20 { 187 compatible = "ti,tca6416"; 188 reg = <0x20>; 189 gpio-controller; /* interrupt not connected */ 190 #gpio-cells = <2>; 191 /* 192 * IRQ not connected 193 * Lines: 194 * 0 - MAX6643_OT_B 195 * 1 - MAX6643_FANFAIL_B 196 * 2 - MIO26_PMU_INPUT_LS 197 * 4 - SFP_SI5382_INT_ALM 198 * 5 - IIC_MUX_RESET_B 199 * 6 - GEM3_EXP_RESET_B 200 * 10 - FMCP_HSPC_PRSNT_M2C_B 201 * 11 - CLK_SPI_MUX_SEL0 202 * 12 - CLK_SPI_MUX_SEL1 203 * 16 - IRPS5401_ALERT_B 204 * 17 - INA226_PMBUS_ALERT 205 * 3, 7, 13-15 - not connected 206 */ 207 }; 208 209 i2c-mux@75 { /* u23 */ 210 compatible = "nxp,pca9544"; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 reg = <0x75>; 214 i2c@0 { 215 #address-cells = <1>; 216 #size-cells = <0>; 217 reg = <0>; 218 /* PS_PMBUS */ 219 /* PMBUS_ALERT done via pca9544 */ 220 u67: ina226@40 { /* u67 */ 221 compatible = "ti,ina226"; 222 #io-channel-cells = <1>; 223 label = "ina226-u67"; 224 reg = <0x40>; 225 shunt-resistor = <2000>; 226 }; 227 u59: ina226@41 { /* u59 */ 228 compatible = "ti,ina226"; 229 #io-channel-cells = <1>; 230 label = "ina226-u59"; 231 reg = <0x41>; 232 shunt-resistor = <5000>; 233 }; 234 u61: ina226@42 { /* u61 */ 235 compatible = "ti,ina226"; 236 #io-channel-cells = <1>; 237 label = "ina226-u61"; 238 reg = <0x42>; 239 shunt-resistor = <5000>; 240 }; 241 u60: ina226@43 { /* u60 */ 242 compatible = "ti,ina226"; 243 #io-channel-cells = <1>; 244 label = "ina226-u60"; 245 reg = <0x43>; 246 shunt-resistor = <5000>; 247 }; 248 u64: ina226@45 { /* u64 */ 249 compatible = "ti,ina226"; 250 #io-channel-cells = <1>; 251 label = "ina226-u64"; 252 reg = <0x45>; 253 shunt-resistor = <5000>; 254 }; 255 u69: ina226@46 { /* u69 */ 256 compatible = "ti,ina226"; 257 #io-channel-cells = <1>; 258 label = "ina226-u69"; 259 reg = <0x46>; 260 shunt-resistor = <2000>; 261 }; 262 u66: ina226@47 { /* u66 */ 263 compatible = "ti,ina226"; 264 #io-channel-cells = <1>; 265 label = "ina226-u66"; 266 reg = <0x47>; 267 shunt-resistor = <5000>; 268 }; 269 u65: ina226@48 { /* u65 */ 270 compatible = "ti,ina226"; 271 #io-channel-cells = <1>; 272 label = "ina226-u65"; 273 reg = <0x48>; 274 shunt-resistor = <5000>; 275 }; 276 u63: ina226@49 { /* u63 */ 277 compatible = "ti,ina226"; 278 #io-channel-cells = <1>; 279 label = "ina226-u63"; 280 reg = <0x49>; 281 shunt-resistor = <5000>; 282 }; 283 u3: ina226@4a { /* u3 */ 284 compatible = "ti,ina226"; 285 #io-channel-cells = <1>; 286 label = "ina226-u3"; 287 reg = <0x4a>; 288 shunt-resistor = <5000>; 289 }; 290 u71: ina226@4b { /* u71 */ 291 compatible = "ti,ina226"; 292 #io-channel-cells = <1>; 293 label = "ina226-u71"; 294 reg = <0x4b>; 295 shunt-resistor = <5000>; 296 }; 297 u77: ina226@4c { /* u77 */ 298 compatible = "ti,ina226"; 299 #io-channel-cells = <1>; 300 label = "ina226-u77"; 301 reg = <0x4c>; 302 shunt-resistor = <5000>; 303 }; 304 u73: ina226@4d { /* u73 */ 305 compatible = "ti,ina226"; 306 #io-channel-cells = <1>; 307 label = "ina226-u73"; 308 reg = <0x4d>; 309 shunt-resistor = <5000>; 310 }; 311 u79: ina226@4e { /* u79 */ 312 compatible = "ti,ina226"; 313 #io-channel-cells = <1>; 314 label = "ina226-u79"; 315 reg = <0x4e>; 316 shunt-resistor = <5000>; 317 }; 318 }; 319 i2c@1 { 320 #address-cells = <1>; 321 #size-cells = <0>; 322 reg = <1>; 323 /* NC */ 324 }; 325 i2c@2 { 326 #address-cells = <1>; 327 #size-cells = <0>; 328 reg = <2>; 329 irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ 330 reg = <0x43>; 331 }; 332 irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ 333 reg = <0x44>; 334 }; 335 irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ 336 reg = <0x45>; 337 }; 338 /* u68 IR38064 +0 */ 339 /* u70 IR38060 +1 */ 340 /* u74 IR38060 +2 */ 341 /* u75 IR38060 +6 */ 342 /* J19 header too */ 343 344 }; 345 i2c@3 { 346 #address-cells = <1>; 347 #size-cells = <0>; 348 reg = <3>; 349 /* SYSMON */ 350 }; 351 }; 352}; 353 354&i2c1 { 355 status = "okay"; 356 clock-frequency = <400000>; 357 358 i2c-mux@74 { /* u26 */ 359 compatible = "nxp,pca9548"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 reg = <0x74>; 363 i2c@0 { 364 #address-cells = <1>; 365 #size-cells = <0>; 366 reg = <0>; 367 /* 368 * IIC_EEPROM 1kB memory which uses 256B blocks 369 * where every block has different address. 370 * 0 - 256B address 0x54 371 * 256B - 512B address 0x55 372 * 512B - 768B address 0x56 373 * 768B - 1024B address 0x57 374 */ 375 eeprom: eeprom@54 { /* u88 */ 376 compatible = "atmel,24c08"; 377 reg = <0x54>; 378 }; 379 }; 380 i2c@1 { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 reg = <1>; 384 si5341: clock-generator@36 { /* SI5341 - u46 */ 385 compatible = "silabs,si5341"; 386 reg = <0x36>; 387 #clock-cells = <2>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 clocks = <&ref48>; 391 clock-names = "xtal"; 392 clock-output-names = "si5341"; 393 394 si5341_0: out@0 { 395 /* refclk0 for PS-GT, used for DP */ 396 reg = <0>; 397 always-on; 398 }; 399 si5341_2: out@2 { 400 /* refclk2 for PS-GT, used for USB3 */ 401 reg = <2>; 402 always-on; 403 }; 404 si5341_3: out@3 { 405 /* refclk3 for PS-GT, used for SATA */ 406 reg = <3>; 407 always-on; 408 }; 409 si5341_5: out@5 { 410 /* refclk5 PL CLK100 */ 411 reg = <5>; 412 always-on; 413 }; 414 si5341_6: out@6 { 415 /* refclk6 PL CLK125 */ 416 reg = <6>; 417 always-on; 418 }; 419 si5341_9: out@9 { 420 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 421 reg = <9>; 422 always-on; 423 }; 424 }; 425 }; 426 i2c@2 { 427 #address-cells = <1>; 428 #size-cells = <0>; 429 reg = <2>; 430 si570_1: clock-generator@5d { /* USER SI570 - u47 */ 431 #clock-cells = <0>; 432 compatible = "silabs,si570"; 433 reg = <0x5d>; 434 temperature-stability = <50>; 435 factory-fout = <300000000>; 436 clock-frequency = <300000000>; 437 clock-output-names = "si570_user"; 438 }; 439 }; 440 i2c@3 { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 reg = <3>; 444 si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ 445 #clock-cells = <0>; 446 compatible = "silabs,si570"; 447 reg = <0x5d>; 448 temperature-stability = <50>; 449 factory-fout = <156250000>; 450 clock-frequency = <156250000>; 451 clock-output-names = "si570_mgt"; 452 }; 453 }; 454 i2c@4 { 455 #address-cells = <1>; 456 #size-cells = <0>; 457 reg = <4>; 458 si5382: clock-generator@69 { /* SI5382 - u48 */ 459 reg = <0x69>; 460 }; 461 }; 462 i2c@5 { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 reg = <5>; 466 sc18is603@2f { /* sc18is602 - u93 */ 467 compatible = "nxp,sc18is603"; 468 reg = <0x2f>; 469 /* 4 gpios for CS not handled by driver */ 470 /* 471 * USB2ANY cable or 472 * LMK04208 - u90 or 473 * LMX2594 - u102 or 474 * LMX2594 - u103 or 475 * LMX2594 - u104 476 */ 477 }; 478 }; 479 i2c@6 { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 reg = <6>; 483 /* FMC connector */ 484 }; 485 /* 7 NC */ 486 }; 487 488 i2c-mux@75 { 489 compatible = "nxp,pca9548"; /* u27 */ 490 #address-cells = <1>; 491 #size-cells = <0>; 492 reg = <0x75>; 493 494 i2c@0 { 495 #address-cells = <1>; 496 #size-cells = <0>; 497 reg = <0>; 498 /* FMCP_HSPC_IIC */ 499 }; 500 i2c@1 { 501 #address-cells = <1>; 502 #size-cells = <0>; 503 reg = <1>; 504 /* NC */ 505 }; 506 i2c@2 { 507 #address-cells = <1>; 508 #size-cells = <0>; 509 reg = <2>; 510 /* SYSMON */ 511 }; 512 i2c@3 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 reg = <3>; 516 /* DDR4 SODIMM */ 517 }; 518 i2c@4 { 519 #address-cells = <1>; 520 #size-cells = <0>; 521 reg = <4>; 522 /* SFP3 */ 523 }; 524 i2c@5 { 525 #address-cells = <1>; 526 #size-cells = <0>; 527 reg = <5>; 528 /* SFP2 */ 529 }; 530 i2c@6 { 531 #address-cells = <1>; 532 #size-cells = <0>; 533 reg = <6>; 534 /* SFP1 */ 535 }; 536 i2c@7 { 537 #address-cells = <1>; 538 #size-cells = <0>; 539 reg = <7>; 540 /* SFP0 */ 541 }; 542 }; 543}; 544 545&psgtr { 546 status = "okay"; 547 /* nc, sata, usb3, dp */ 548 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 549 clock-names = "ref1", "ref2", "ref3"; 550}; 551 552&rtc { 553 status = "okay"; 554}; 555 556&sata { 557 status = "okay"; 558 /* SATA OOB timing settings */ 559 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 560 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 561 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 562 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 563 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 564 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 565 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 566 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 567 phy-names = "sata-phy"; 568 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 569}; 570 571/* SD1 with level shifter */ 572&sdhci1 { 573 status = "okay"; 574 no-1-8-v; 575 xlnx,mio-bank = <1>; 576}; 577 578&uart0 { 579 status = "okay"; 580}; 581 582/* ULPI SMSC USB3320 */ 583&usb0 { 584 status = "okay"; 585 dr_mode = "host"; 586}; 587 588&zynqmp_dpdma { 589 status = "okay"; 590}; 591 592&zynqmp_dpsub { 593 status = "okay"; 594 phy-names = "dp-phy0", "dp-phy1"; 595 phys = <&psgtr 1 PHY_TYPE_DP 0 1>, 596 <&psgtr 0 PHY_TYPE_DP 1 1>; 597}; 598