1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/net/ti-dp83867.h> 14 15/ { 16 compatible = "ti,j721e-sk", "ti,j721e"; 17 model = "Texas Instruments J721E SK"; 18 19 aliases { 20 serial0 = &wkup_uart0; 21 serial1 = &mcu_uart0; 22 serial2 = &main_uart0; 23 serial3 = &main_uart1; 24 ethernet0 = &cpsw_port1; 25 mmc1 = &main_sdhci1; 26 }; 27 28 chosen { 29 stdout-path = "serial2:115200n8"; 30 }; 31 32 memory@80000000 { 33 device_type = "memory"; 34 bootph-all; 35 /* 4G RAM */ 36 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 37 <0x00000008 0x80000000 0x00000000 0x80000000>; 38 }; 39 40 reserved_memory: reserved-memory { 41 #address-cells = <2>; 42 #size-cells = <2>; 43 ranges; 44 45 secure_ddr: optee@9e800000 { 46 reg = <0x00 0x9e800000 0x00 0x01800000>; 47 alignment = <0x1000>; 48 no-map; 49 }; 50 51 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 52 compatible = "shared-dma-pool"; 53 reg = <0x00 0xa0000000 0x00 0x100000>; 54 no-map; 55 }; 56 57 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 58 compatible = "shared-dma-pool"; 59 reg = <0x00 0xa0100000 0x00 0xf00000>; 60 no-map; 61 }; 62 63 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 64 compatible = "shared-dma-pool"; 65 reg = <0x00 0xa1000000 0x00 0x100000>; 66 no-map; 67 }; 68 69 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 70 compatible = "shared-dma-pool"; 71 reg = <0x00 0xa1100000 0x00 0xf00000>; 72 no-map; 73 }; 74 75 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 76 compatible = "shared-dma-pool"; 77 reg = <0x00 0xa2000000 0x00 0x100000>; 78 no-map; 79 }; 80 81 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 82 compatible = "shared-dma-pool"; 83 reg = <0x00 0xa2100000 0x00 0xf00000>; 84 no-map; 85 }; 86 87 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 88 compatible = "shared-dma-pool"; 89 reg = <0x00 0xa3000000 0x00 0x100000>; 90 no-map; 91 }; 92 93 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 94 compatible = "shared-dma-pool"; 95 reg = <0x00 0xa3100000 0x00 0xf00000>; 96 no-map; 97 }; 98 99 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 100 compatible = "shared-dma-pool"; 101 reg = <0x00 0xa4000000 0x00 0x100000>; 102 no-map; 103 }; 104 105 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 106 compatible = "shared-dma-pool"; 107 reg = <0x00 0xa4100000 0x00 0xf00000>; 108 no-map; 109 }; 110 111 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 112 compatible = "shared-dma-pool"; 113 reg = <0x00 0xa5000000 0x00 0x100000>; 114 no-map; 115 }; 116 117 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 118 compatible = "shared-dma-pool"; 119 reg = <0x00 0xa5100000 0x00 0xf00000>; 120 no-map; 121 }; 122 123 c66_0_dma_memory_region: c66-dma-memory@a6000000 { 124 compatible = "shared-dma-pool"; 125 reg = <0x00 0xa6000000 0x00 0x100000>; 126 no-map; 127 }; 128 129 c66_0_memory_region: c66-memory@a6100000 { 130 compatible = "shared-dma-pool"; 131 reg = <0x00 0xa6100000 0x00 0xf00000>; 132 no-map; 133 }; 134 135 c66_1_dma_memory_region: c66-dma-memory@a7000000 { 136 compatible = "shared-dma-pool"; 137 reg = <0x00 0xa7000000 0x00 0x100000>; 138 no-map; 139 }; 140 141 c66_1_memory_region: c66-memory@a7100000 { 142 compatible = "shared-dma-pool"; 143 reg = <0x00 0xa7100000 0x00 0xf00000>; 144 no-map; 145 }; 146 147 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 148 compatible = "shared-dma-pool"; 149 reg = <0x00 0xa8000000 0x00 0x100000>; 150 no-map; 151 }; 152 153 c71_0_memory_region: c71-memory@a8100000 { 154 compatible = "shared-dma-pool"; 155 reg = <0x00 0xa8100000 0x00 0xf00000>; 156 no-map; 157 }; 158 159 rtos_ipc_memory_region: ipc-memories@aa000000 { 160 reg = <0x00 0xaa000000 0x00 0x01c00000>; 161 alignment = <0x1000>; 162 no-map; 163 }; 164 }; 165 166 vusb_main: fixedregulator-vusb-main5v0 { 167 /* USB MAIN INPUT 5V DC */ 168 compatible = "regulator-fixed"; 169 regulator-name = "vusb-main5v0"; 170 regulator-min-microvolt = <5000000>; 171 regulator-max-microvolt = <5000000>; 172 regulator-always-on; 173 regulator-boot-on; 174 }; 175 176 vsys_3v3: fixedregulator-vsys3v3 { 177 /* Output of LM5141 */ 178 compatible = "regulator-fixed"; 179 regulator-name = "vsys_3v3"; 180 regulator-min-microvolt = <3300000>; 181 regulator-max-microvolt = <3300000>; 182 vin-supply = <&vusb_main>; 183 regulator-always-on; 184 regulator-boot-on; 185 }; 186 187 vsys_5v0: fixedregulator-vsys5v0 { 188 /* Output of LM61460 */ 189 compatible = "regulator-fixed"; 190 regulator-name = "vsys_5v0"; 191 regulator-min-microvolt = <5000000>; 192 regulator-max-microvolt = <5000000>; 193 vin-supply = <&vusb_main>; 194 regulator-always-on; 195 regulator-boot-on; 196 }; 197 198 vdd_mmc1: fixedregulator-sd { 199 compatible = "regulator-fixed"; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&vdd_mmc1_en_pins_default>; 202 regulator-name = "vdd_mmc1"; 203 regulator-min-microvolt = <3300000>; 204 regulator-max-microvolt = <3300000>; 205 regulator-boot-on; 206 enable-active-high; 207 vin-supply = <&vsys_3v3>; 208 gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; 209 }; 210 211 vdd_sd_dv_alt: gpio-regulator-tps659411 { 212 compatible = "regulator-gpio"; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 215 regulator-name = "tps659411"; 216 regulator-min-microvolt = <1800000>; 217 regulator-max-microvolt = <3300000>; 218 regulator-boot-on; 219 vin-supply = <&vsys_3v3>; 220 gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; 221 states = <1800000 0x0>, 222 <3300000 0x1>; 223 }; 224 225 vdd_sd_dv: gpio-regulator-TLV71033 { 226 compatible = "regulator-gpio"; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&vdd_sd_dv_pins_default>; 229 regulator-name = "tlv71033"; 230 regulator-min-microvolt = <1800000>; 231 regulator-max-microvolt = <3300000>; 232 regulator-boot-on; 233 vin-supply = <&vsys_5v0>; 234 gpios = <&main_gpio0 118 GPIO_ACTIVE_HIGH>; 235 states = <1800000 0x0>, 236 <3300000 0x1>; 237 }; 238 239 transceiver1: can-phy1 { 240 compatible = "ti,tcan1042"; 241 #phy-cells = <0>; 242 max-bitrate = <5000000>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 245 standby-gpios = <&wkup_gpio0 3 GPIO_ACTIVE_HIGH>; 246 }; 247 248 transceiver2: can-phy2 { 249 compatible = "ti,tcan1042"; 250 #phy-cells = <0>; 251 max-bitrate = <5000000>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&main_mcan0_gpio_pins_default>; 254 standby-gpios = <&main_gpio0 65 GPIO_ACTIVE_HIGH>; 255 }; 256 257 transceiver3: can-phy3 { 258 compatible = "ti,tcan1042"; 259 #phy-cells = <0>; 260 max-bitrate = <5000000>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&main_mcan5_gpio_pins_default>; 263 standby-gpios = <&main_gpio0 66 GPIO_ACTIVE_HIGH>; 264 }; 265 266 transceiver4: can-phy4 { 267 compatible = "ti,tcan1042"; 268 #phy-cells = <0>; 269 max-bitrate = <5000000>; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&main_mcan9_gpio_pins_default>; 272 standby-gpios = <&main_gpio0 67 GPIO_ACTIVE_HIGH>; 273 }; 274 275 dp_pwr_3v3: fixedregulator-dp-prw { 276 compatible = "regulator-fixed"; 277 regulator-name = "dp-pwr"; 278 regulator-min-microvolt = <3300000>; 279 regulator-max-microvolt = <3300000>; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&dp_pwr_en_pins_default>; 282 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ 283 enable-active-high; 284 }; 285 286 dp0: connector { 287 compatible = "dp-connector"; 288 label = "DP0"; 289 type = "full-size"; 290 dp-pwr-supply = <&dp_pwr_3v3>; 291 292 port { 293 dp_connector_in: endpoint { 294 remote-endpoint = <&dp0_out>; 295 }; 296 }; 297 }; 298 299 hdmi-connector { 300 compatible = "hdmi-connector"; 301 label = "hdmi"; 302 type = "a"; 303 304 pinctrl-names = "default"; 305 pinctrl-0 = <&hdmi_hpd_pins_default>; 306 307 ddc-i2c-bus = <&main_i2c1>; 308 309 /* HDMI_HPD */ 310 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>; 311 312 port { 313 hdmi_connector_in: endpoint { 314 remote-endpoint = <&tfp410_out>; 315 }; 316 }; 317 }; 318 319 dvi-bridge { 320 compatible = "ti,tfp410"; 321 322 pinctrl-names = "default"; 323 pinctrl-0 = <&hdmi_pdn_pins_default>; 324 325 powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>; 326 ti,deskew = <0>; 327 328 ports { 329 #address-cells = <1>; 330 #size-cells = <0>; 331 332 port@0 { 333 reg = <0>; 334 335 tfp410_in: endpoint { 336 remote-endpoint = <&dpi1_out>; 337 pclk-sample = <1>; 338 }; 339 }; 340 341 port@1 { 342 reg = <1>; 343 344 tfp410_out: endpoint { 345 remote-endpoint = 346 <&hdmi_connector_in>; 347 }; 348 }; 349 }; 350 }; 351 352 csi_mux: mux-controller { 353 compatible = "gpio-mux"; 354 #mux-state-cells = <1>; 355 mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>; 356 idle-state = <0>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&main_csi_mux_sel_pins_default>; 359 }; 360}; 361 362&main_pmx0 { 363 main_mmc1_pins_default: main-mmc1-default-pins { 364 pinctrl-single,pins = < 365 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 366 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 367 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 368 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 369 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 370 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 371 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 372 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 373 >; 374 bootph-all; 375 }; 376 377 main_uart0_pins_default: main-uart0-default-pins { 378 pinctrl-single,pins = < 379 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ 380 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ 381 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 382 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 383 >; 384 bootph-all; 385 }; 386 387 main_uart1_pins_default: main-uart1-default-pins { 388 pinctrl-single,pins = < 389 J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ 390 J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ 391 >; 392 }; 393 394 main_i2c0_pins_default: main-i2c0-default-pins { 395 pinctrl-single,pins = < 396 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 397 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 398 >; 399 }; 400 401 main_i2c1_pins_default: main-i2c1-default-pins { 402 pinctrl-single,pins = < 403 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 404 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 405 >; 406 }; 407 408 main_i2c3_pins_default: main-i2c3-default-pins { 409 pinctrl-single,pins = < 410 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 411 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 412 >; 413 }; 414 415 main_usbss0_pins_default: main-usbss0-default-pins { 416 pinctrl-single,pins = < 417 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 418 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 419 >; 420 bootph-all; 421 }; 422 423 main_usbss1_pins_default: main-usbss1-default-pins { 424 pinctrl-single,pins = < 425 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 426 >; 427 bootph-all; 428 }; 429 430 main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { 431 pinctrl-single,pins = < 432 J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ 433 >; 434 }; 435 436 main_mcan0_pins_default: main-mcan0-default-pins { 437 pinctrl-single,pins = < 438 J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ 439 J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ 440 >; 441 }; 442 443 main_mcan0_gpio_pins_default: main-mcan0-gpio-default-pins { 444 pinctrl-single,pins = < 445 J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */ 446 >; 447 }; 448 449 main_mcan5_pins_default: main-mcan5-default-pins { 450 pinctrl-single,pins = < 451 J721E_IOPAD(0x050, PIN_INPUT, 6) /* (AE21) PRG1_PRU0_GPO18.MCAN5_RX */ 452 J721E_IOPAD(0x04c, PIN_OUTPUT, 6) /* (AJ21) PRG1_PRU0_GPO17.MCAN5_TX */ 453 >; 454 }; 455 456 main_mcan5_gpio_pins_default: main-mcan5-gpio-default-pins { 457 pinctrl-single,pins = < 458 J721E_IOPAD(0x10c, PIN_INPUT, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */ 459 >; 460 }; 461 462 main_mcan9_pins_default: main-mcan9-default-pins { 463 pinctrl-single,pins = < 464 J721E_IOPAD(0x0d0, PIN_INPUT, 6) /* (AC27) PRG0_PRU0_GPO8.MCAN9_RX */ 465 J721E_IOPAD(0x0cc, PIN_OUTPUT, 6) /* (AC28) PRG0_PRU0_GPO7.MCAN9_TX */ 466 >; 467 }; 468 469 main_mcan9_gpio_pins_default: main-mcan9-gpio-default-pins { 470 pinctrl-single,pins = < 471 J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */ 472 >; 473 }; 474 475 dp0_pins_default: dp0-default-pins { 476 pinctrl-single,pins = < 477 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 478 >; 479 }; 480 481 dp_pwr_en_pins_default: dp-pwr-en-default-pins { 482 pinctrl-single,pins = < 483 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ 484 >; 485 }; 486 487 dss_vout0_pins_default: dss-vout0-default-pins { 488 pinctrl-single,pins = < 489 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ 490 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ 491 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ 492 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ 493 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ 494 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ 495 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ 496 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ 497 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ 498 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ 499 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ 500 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ 501 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ 502 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ 503 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ 504 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ 505 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ 506 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ 507 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ 508 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ 509 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ 510 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ 511 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ 512 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ 513 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ 514 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ 515 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ 516 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ 517 >; 518 }; 519 520 hdmi_hpd_pins_default: hdmi-hpd-default-pins { 521 pinctrl-single,pins = < 522 J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ 523 >; 524 }; 525 526 hdmi_pdn_pins_default: hdmi-pdn-default-pins { 527 pinctrl-single,pins = < 528 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ 529 >; 530 }; 531 532 /* Reset for M.2 E Key slot on PCIe0 */ 533 ekey_reset_pins_default: ekey-reset-pns-default-pins { 534 pinctrl-single,pins = < 535 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ 536 >; 537 }; 538 539 main_i2c5_pins_default: main-i2c5-default-pins { 540 pinctrl-single,pins = < 541 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ 542 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ 543 >; 544 }; 545 546 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { 547 pinctrl-single,pins = < 548 J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ 549 J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ 550 J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ 551 J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ 552 J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ 553 J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ 554 J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ 555 J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ 556 J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ 557 J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ 558 J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ 559 J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ 560 J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ 561 J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ 562 J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ 563 J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ 564 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ 565 J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ 566 J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ 567 J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ 568 J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ 569 J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ 570 J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ 571 >; 572 }; 573 574 rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins { 575 pinctrl-single,pins = < 576 J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ 577 >; 578 }; 579}; 580 581&wkup_pmx0 { 582 pmic_irq_pins_default: pmic-irq-default-pins { 583 pinctrl-single,pins = < 584 J721E_WKUP_IOPAD(0x0cc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ 585 >; 586 }; 587 588 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 589 pinctrl-single,pins = < 590 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 591 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 592 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 593 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 594 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 595 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 596 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 597 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 598 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 599 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 600 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 601 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 602 >; 603 }; 604 605 mcu_mdio_pins_default: mcu-mdio1-default-pins { 606 pinctrl-single,pins = < 607 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 608 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 609 >; 610 }; 611 612 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 613 pinctrl-single,pins = < 614 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ 615 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ 616 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ 617 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ 618 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ 619 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ 620 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ 621 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ 622 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ 623 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ 624 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ 625 >; 626 bootph-all; 627 }; 628 629 vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { 630 pinctrl-single,pins = < 631 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ 632 >; 633 }; 634 635 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { 636 pinctrl-single,pins = < 637 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ 638 >; 639 }; 640 641 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 642 pinctrl-single,pins = < 643 J721E_IOPAD(0x1dc, PIN_OUTPUT, 7) /* (Y1) SPI1_CLK.GPIO0_118 */ 644 >; 645 }; 646 647 wkup_uart0_pins_default: wkup-uart0-default-pins { 648 pinctrl-single,pins = < 649 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ 650 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ 651 >; 652 }; 653 654 mcu_uart0_pins_default: mcu-uart0-default-pins { 655 pinctrl-single,pins = < 656 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ 657 J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ 658 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ 659 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ 660 >; 661 bootph-all; 662 }; 663 664 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 665 pinctrl-single,pins = < 666 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 667 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 668 >; 669 bootph-all; 670 }; 671 672 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 673 pinctrl-single,pins = < 674 J721E_WKUP_IOPAD(0x0ac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ 675 J721E_WKUP_IOPAD(0x0a8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ 676 >; 677 }; 678 679 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 680 pinctrl-single,pins = < 681 J721E_WKUP_IOPAD(0x0bc, PIN_INPUT, 7) /* (F27) WKUP_GPIO0_3 */ 682 >; 683 }; 684 685 /* Reset for M.2 M Key slot on PCIe1 */ 686 mkey_reset_pins_default: mkey-reset-pns-default-pins { 687 pinctrl-single,pins = < 688 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ 689 >; 690 }; 691}; 692 693&wkup_uart0 { 694 /* Wakeup UART is used by System firmware */ 695 status = "reserved"; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&wkup_uart0_pins_default>; 698 bootph-all; 699}; 700 701&wkup_i2c0 { 702 status = "okay"; 703 pinctrl-names = "default"; 704 pinctrl-0 = <&wkup_i2c0_pins_default>; 705 clock-frequency = <400000>; 706 707 eeprom@51 { 708 /* AT24C512C-MAHM-T */ 709 compatible = "atmel,24c512"; 710 reg = <0x51>; 711 }; 712 713 tps659413: pmic@48 { 714 compatible = "ti,tps6594-q1"; 715 reg = <0x48>; 716 system-power-controller; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&pmic_irq_pins_default>; 719 interrupt-parent = <&wkup_gpio0>; 720 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 721 gpio-controller; 722 #gpio-cells = <2>; 723 ti,primary-pmic; 724 buck123-supply = <&vsys_3v3>; 725 buck4-supply = <&vsys_3v3>; 726 buck5-supply = <&vsys_3v3>; 727 ldo1-supply = <&vsys_3v3>; 728 ldo2-supply = <&vsys_3v3>; 729 ldo3-supply = <&vsys_3v3>; 730 ldo4-supply = <&vsys_3v3>; 731 732 regulators { 733 bucka123: buck123 { 734 regulator-name = "vdd_cpu_avs"; 735 regulator-min-microvolt = <600000>; 736 regulator-max-microvolt = <900000>; 737 regulator-boot-on; 738 regulator-always-on; 739 bootph-pre-ram; 740 }; 741 742 bucka4: buck4 { 743 regulator-name = "vdd_mcu_0v85"; 744 regulator-min-microvolt = <850000>; 745 regulator-max-microvolt = <850000>; 746 regulator-boot-on; 747 regulator-always-on; 748 }; 749 750 bucka5: buck5 { 751 regulator-name = "vdd_phyio_1v8"; 752 regulator-min-microvolt = <1800000>; 753 regulator-max-microvolt = <1800000>; 754 regulator-boot-on; 755 regulator-always-on; 756 }; 757 758 ldoa1: ldo1 { 759 regulator-name = "vdd1_lpddr4_1v8"; 760 regulator-min-microvolt = <1800000>; 761 regulator-max-microvolt = <1800000>; 762 regulator-boot-on; 763 regulator-always-on; 764 }; 765 766 ldoa2: ldo2 { 767 regulator-name = "vdd_mcuio_1v8"; 768 regulator-min-microvolt = <1800000>; 769 regulator-max-microvolt = <1800000>; 770 regulator-boot-on; 771 regulator-always-on; 772 }; 773 774 ldoa3: ldo3 { 775 regulator-name = "vdda_dll_0v8"; 776 regulator-min-microvolt = <800000>; 777 regulator-max-microvolt = <800000>; 778 regulator-boot-on; 779 regulator-always-on; 780 }; 781 782 ldoa4: ldo4 { 783 regulator-name = "vda_mcu_1v8"; 784 regulator-min-microvolt = <1800000>; 785 regulator-max-microvolt = <1800000>; 786 regulator-boot-on; 787 regulator-always-on; 788 }; 789 }; 790 }; 791 792 tps659411: pmic@4c { 793 compatible = "ti,tps6594-q1"; 794 reg = <0x4c>; 795 system-power-controller; 796 interrupt-parent = <&wkup_gpio0>; 797 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 798 gpio-controller; 799 #gpio-cells = <2>; 800 buck1234-supply = <&vsys_3v3>; 801 buck5-supply = <&vsys_3v3>; 802 ldo1-supply = <&vsys_3v3>; 803 ldo2-supply = <&vsys_3v3>; 804 ldo3-supply = <&vsys_3v3>; 805 ldo4-supply = <&vsys_3v3>; 806 807 regulators { 808 buckb1234: buck1234 { 809 regulator-name = "vdd_core_0v8"; 810 regulator-min-microvolt = <800000>; 811 regulator-max-microvolt = <800000>; 812 regulator-boot-on; 813 regulator-always-on; 814 }; 815 816 buckb5: buck5 { 817 regulator-name = "vdd_ram_0v85"; 818 regulator-min-microvolt = <850000>; 819 regulator-max-microvolt = <850000>; 820 regulator-boot-on; 821 regulator-always-on; 822 }; 823 824 ldob1: ldo1 { 825 regulator-name = "vdd_sd_dv"; 826 regulator-min-microvolt = <1800000>; 827 regulator-max-microvolt = <3300000>; 828 regulator-boot-on; 829 regulator-always-on; 830 }; 831 832 ldob2: ldo2 { 833 regulator-name = "vdd_usb_3v3"; 834 regulator-min-microvolt = <3300000>; 835 regulator-max-microvolt = <3300000>; 836 regulator-boot-on; 837 regulator-always-on; 838 }; 839 840 ldob3: ldo3 { 841 regulator-name = "vdd_io_1v8"; 842 regulator-min-microvolt = <1800000>; 843 regulator-max-microvolt = <1800000>; 844 regulator-boot-on; 845 regulator-always-on; 846 }; 847 848 ldob4: ldo4 { 849 regulator-name = "vda_pll_1v8"; 850 regulator-min-microvolt = <1800000>; 851 regulator-max-microvolt = <1800000>; 852 regulator-boot-on; 853 regulator-always-on; 854 }; 855 }; 856 }; 857}; 858 859&mcu_uart0 { 860 status = "okay"; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&mcu_uart0_pins_default>; 863 bootph-all; 864}; 865 866&main_uart0 { 867 status = "okay"; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&main_uart0_pins_default>; 870 /* Shared with ATF on this platform */ 871 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 872 bootph-all; 873}; 874 875&main_uart1 { 876 status = "okay"; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&main_uart1_pins_default>; 879}; 880 881&main_sdhci1 { 882 /* SD Card */ 883 status = "okay"; 884 vmmc-supply = <&vdd_mmc1>; 885 vqmmc-supply = <&vdd_sd_dv_alt>; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&main_mmc1_pins_default>; 888 bootph-all; 889 ti,driver-strength-ohm = <50>; 890 disable-wp; 891}; 892 893&ospi0 { 894 status = "okay"; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 897 898 flash@0 { 899 compatible = "jedec,spi-nor"; 900 reg = <0x0>; 901 spi-tx-bus-width = <8>; 902 spi-rx-bus-width = <8>; 903 spi-max-frequency = <25000000>; 904 cdns,tshsl-ns = <60>; 905 cdns,tsd2d-ns = <60>; 906 cdns,tchsh-ns = <60>; 907 cdns,tslch-ns = <60>; 908 cdns,read-delay = <4>; 909 910 partitions { 911 compatible = "fixed-partitions"; 912 #address-cells = <1>; 913 #size-cells = <1>; 914 915 partition@0 { 916 label = "ospi.tiboot3"; 917 reg = <0x0 0x80000>; 918 }; 919 920 partition@80000 { 921 label = "ospi.tispl"; 922 reg = <0x80000 0x200000>; 923 }; 924 925 partition@280000 { 926 label = "ospi.u-boot"; 927 reg = <0x280000 0x400000>; 928 }; 929 930 partition@680000 { 931 label = "ospi.env"; 932 reg = <0x680000 0x40000>; 933 }; 934 935 partition@6c0000 { 936 label = "ospi.sysfw"; 937 reg = <0x6c0000 0x100000>; 938 }; 939 940 partition@7c0000 { 941 label = "ospi.env.backup"; 942 reg = <0x7c0000 0x40000>; 943 }; 944 945 partition@800000 { 946 label = "ospi.rootfs"; 947 reg = <0x800000 0x37c0000>; 948 }; 949 950 partition@3fc0000 { 951 label = "ospi.phypattern"; 952 reg = <0x3fc0000 0x40000>; 953 bootph-all; 954 }; 955 }; 956 }; 957}; 958 959&main_i2c0 { 960 status = "okay"; 961 pinctrl-names = "default"; 962 pinctrl-0 = <&main_i2c0_pins_default>; 963 clock-frequency = <400000>; 964 965 i2c-mux@71 { 966 compatible = "nxp,pca9543"; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 reg = <0x71>; 970 971 /* PCIe1 M.2 M Key I2C */ 972 i2c@0 { 973 #address-cells = <1>; 974 #size-cells = <0>; 975 reg = <0>; 976 }; 977 978 /* PCIe0 M.2 E Key I2C */ 979 i2c@1 { 980 #address-cells = <1>; 981 #size-cells = <0>; 982 reg = <1>; 983 }; 984 }; 985}; 986 987&main_i2c1 { 988 status = "okay"; 989 pinctrl-names = "default"; 990 pinctrl-0 = <&main_i2c1_pins_default>; 991 /* i2c1 is used for DVI DDC, so we need to use 100kHz */ 992 clock-frequency = <100000>; 993}; 994 995&main_i2c3 { 996 status = "okay"; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&main_i2c3_pins_default>; 999 clock-frequency = <400000>; 1000 1001 i2c-mux@70 { 1002 compatible = "nxp,pca9543"; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 reg = <0x70>; 1006 1007 /* CSI0 I2C */ 1008 cam0_i2c: i2c@0 { 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 reg = <0>; 1012 }; 1013 1014 /* CSI1 I2C */ 1015 cam1_i2c: i2c@1 { 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 reg = <1>; 1019 }; 1020 }; 1021}; 1022 1023&main_i2c5 { 1024 /* Brought out on RPi Header */ 1025 status = "okay"; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&main_i2c5_pins_default>; 1028 clock-frequency = <400000>; 1029}; 1030 1031&main_gpio0 { 1032 status = "okay"; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&rpi_header_gpio0_pins_default>; 1035}; 1036 1037&main_gpio1 { 1038 status = "okay"; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&rpi_header_gpio1_pins_default>; 1041}; 1042 1043&wkup_gpio0 { 1044 status = "okay"; 1045}; 1046 1047&usb_serdes_mux { 1048 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 1049 bootph-all; 1050}; 1051 1052&serdes_ln_ctrl { 1053 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 1054 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 1055 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 1056 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 1057 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 1058 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 1059 bootph-all; 1060}; 1061 1062&serdes_wiz3 { 1063 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 1064 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 1065}; 1066 1067&serdes3 { 1068 serdes3_usb_link: phy@0 { 1069 reg = <0>; 1070 cdns,num-lanes = <2>; 1071 #phy-cells = <0>; 1072 cdns,phy-type = <PHY_TYPE_USB3>; 1073 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 1074 bootph-all; 1075 }; 1076}; 1077 1078&serdes4 { 1079 torrent_phy_dp: phy@0 { 1080 reg = <0>; 1081 resets = <&serdes_wiz4 1>; 1082 cdns,phy-type = <PHY_TYPE_DP>; 1083 cdns,num-lanes = <4>; 1084 cdns,max-bit-rate = <5400>; 1085 #phy-cells = <0>; 1086 }; 1087}; 1088 1089&mhdp { 1090 phys = <&torrent_phy_dp>; 1091 phy-names = "dpphy"; 1092 pinctrl-names = "default"; 1093 pinctrl-0 = <&dp0_pins_default>; 1094}; 1095 1096&usbss0 { 1097 pinctrl-names = "default"; 1098 pinctrl-0 = <&main_usbss0_pins_default>; 1099 bootph-all; 1100 ti,vbus-divider; 1101}; 1102 1103&usb0 { 1104 dr_mode = "otg"; 1105 maximum-speed = "super-speed"; 1106 phys = <&serdes3_usb_link>; 1107 phy-names = "cdns3,usb3-phy"; 1108 bootph-all; 1109}; 1110 1111&serdes2 { 1112 serdes2_usb_link: phy@1 { 1113 reg = <1>; 1114 cdns,num-lanes = <1>; 1115 #phy-cells = <0>; 1116 cdns,phy-type = <PHY_TYPE_USB3>; 1117 resets = <&serdes_wiz2 2>; 1118 }; 1119}; 1120 1121&usbss1 { 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&main_usbss1_pins_default>; 1124 bootph-all; 1125 ti,vbus-divider; 1126}; 1127 1128&usb1 { 1129 dr_mode = "host"; 1130 maximum-speed = "super-speed"; 1131 phys = <&serdes2_usb_link>; 1132 phy-names = "cdns3,usb3-phy"; 1133 bootph-all; 1134}; 1135 1136&mcu_cpsw { 1137 pinctrl-names = "default"; 1138 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 1139}; 1140 1141&davinci_mdio { 1142 phy0: ethernet-phy@0 { 1143 reg = <0>; 1144 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 1145 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 1146 }; 1147}; 1148 1149&cpsw_port1 { 1150 phy-mode = "rgmii-rxid"; 1151 phy-handle = <&phy0>; 1152}; 1153 1154&dss { 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&dss_vout0_pins_default>; 1157 1158 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 1159 <&k3_clks 152 4>, /* VP 2 pixel clock */ 1160 <&k3_clks 152 9>, /* VP 3 pixel clock */ 1161 <&k3_clks 152 13>; /* VP 4 pixel clock */ 1162 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 1163 <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ 1164 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 1165 <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ 1166}; 1167 1168&dss_ports { 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 1172 port@0 { 1173 reg = <0>; 1174 1175 dpi0_out: endpoint { 1176 remote-endpoint = <&dp0_in>; 1177 }; 1178 }; 1179 1180 port@1 { 1181 reg = <1>; 1182 1183 dpi1_out: endpoint { 1184 remote-endpoint = <&tfp410_in>; 1185 }; 1186 }; 1187}; 1188 1189&dp0_ports { 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 1193 port@0 { 1194 reg = <0>; 1195 dp0_in: endpoint { 1196 remote-endpoint = <&dpi0_out>; 1197 }; 1198 }; 1199 1200 port@4 { 1201 reg = <4>; 1202 dp0_out: endpoint { 1203 remote-endpoint = <&dp_connector_in>; 1204 }; 1205 }; 1206}; 1207 1208&serdes0 { 1209 serdes0_pcie_link: phy@0 { 1210 reg = <0>; 1211 cdns,num-lanes = <1>; 1212 #phy-cells = <0>; 1213 cdns,phy-type = <PHY_TYPE_PCIE>; 1214 resets = <&serdes_wiz0 1>; 1215 }; 1216}; 1217 1218&serdes1 { 1219 serdes1_pcie_link: phy@0 { 1220 reg = <0>; 1221 cdns,num-lanes = <2>; 1222 #phy-cells = <0>; 1223 cdns,phy-type = <PHY_TYPE_PCIE>; 1224 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 1225 }; 1226}; 1227 1228&pcie0_rc { 1229 status = "okay"; 1230 pinctrl-names = "default"; 1231 pinctrl-0 = <&ekey_reset_pins_default>; 1232 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; 1233 1234 phys = <&serdes0_pcie_link>; 1235 phy-names = "pcie-phy"; 1236 num-lanes = <1>; 1237}; 1238 1239&pcie1_rc { 1240 status = "okay"; 1241 pinctrl-names = "default"; 1242 pinctrl-0 = <&mkey_reset_pins_default>; 1243 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; 1244 1245 phys = <&serdes1_pcie_link>; 1246 phy-names = "pcie-phy"; 1247 num-lanes = <2>; 1248}; 1249 1250&mcu_mcan0 { 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&mcu_mcan0_pins_default>; 1253 phys = <&transceiver1>; 1254 status = "okay"; 1255}; 1256 1257&main_mcan0 { 1258 pinctrl-names = "default"; 1259 pinctrl-0 = <&main_mcan0_pins_default>; 1260 phys = <&transceiver2>; 1261 status = "okay"; 1262}; 1263 1264&main_mcan5 { 1265 pinctrl-names = "default"; 1266 pinctrl-0 = <&main_mcan5_pins_default>; 1267 phys = <&transceiver3>; 1268 status = "okay"; 1269}; 1270 1271&main_mcan9 { 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&main_mcan9_pins_default>; 1274 phys = <&transceiver4>; 1275 status = "okay"; 1276}; 1277 1278&ufs_wrapper { 1279 status = "disabled"; 1280}; 1281 1282&mailbox0_cluster0 { 1283 status = "okay"; 1284 interrupts = <436>; 1285 1286 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 1287 ti,mbox-rx = <0 0 0>; 1288 ti,mbox-tx = <1 0 0>; 1289 }; 1290 1291 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 1292 ti,mbox-rx = <2 0 0>; 1293 ti,mbox-tx = <3 0 0>; 1294 }; 1295}; 1296 1297&mailbox0_cluster1 { 1298 status = "okay"; 1299 interrupts = <432>; 1300 1301 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 1302 ti,mbox-rx = <0 0 0>; 1303 ti,mbox-tx = <1 0 0>; 1304 }; 1305 1306 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 1307 ti,mbox-rx = <2 0 0>; 1308 ti,mbox-tx = <3 0 0>; 1309 }; 1310}; 1311 1312&mailbox0_cluster2 { 1313 status = "okay"; 1314 interrupts = <428>; 1315 1316 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 1317 ti,mbox-rx = <0 0 0>; 1318 ti,mbox-tx = <1 0 0>; 1319 }; 1320 1321 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 1322 ti,mbox-rx = <2 0 0>; 1323 ti,mbox-tx = <3 0 0>; 1324 }; 1325}; 1326 1327&mailbox0_cluster3 { 1328 status = "okay"; 1329 interrupts = <424>; 1330 1331 mbox_c66_0: mbox-c66-0 { 1332 ti,mbox-rx = <0 0 0>; 1333 ti,mbox-tx = <1 0 0>; 1334 }; 1335 1336 mbox_c66_1: mbox-c66-1 { 1337 ti,mbox-rx = <2 0 0>; 1338 ti,mbox-tx = <3 0 0>; 1339 }; 1340}; 1341 1342&mailbox0_cluster4 { 1343 status = "okay"; 1344 interrupts = <420>; 1345 1346 mbox_c71_0: mbox-c71-0 { 1347 ti,mbox-rx = <0 0 0>; 1348 ti,mbox-tx = <1 0 0>; 1349 }; 1350}; 1351 1352&mcu_r5fss0_core0 { 1353 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 1354 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1355 <&mcu_r5fss0_core0_memory_region>; 1356}; 1357 1358&mcu_r5fss0_core1 { 1359 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 1360 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1361 <&mcu_r5fss0_core1_memory_region>; 1362}; 1363 1364&main_r5fss0 { 1365 ti,cluster-mode = <0>; 1366}; 1367 1368&main_r5fss1 { 1369 ti,cluster-mode = <0>; 1370}; 1371 1372/* Timers are used by Remoteproc firmware */ 1373&main_timer0 { 1374 status = "reserved"; 1375}; 1376 1377&main_timer1 { 1378 status = "reserved"; 1379}; 1380 1381&main_timer2 { 1382 status = "reserved"; 1383}; 1384 1385&main_timer12 { 1386 status = "reserved"; 1387}; 1388 1389&main_timer13 { 1390 status = "reserved"; 1391}; 1392 1393&main_timer14 { 1394 status = "reserved"; 1395}; 1396 1397&main_timer15 { 1398 status = "reserved"; 1399}; 1400 1401&main_r5fss0_core0 { 1402 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1403 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1404 <&main_r5fss0_core0_memory_region>; 1405}; 1406 1407&main_r5fss0_core1 { 1408 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1409 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1410 <&main_r5fss0_core1_memory_region>; 1411}; 1412 1413&main_r5fss1_core0 { 1414 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1415 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1416 <&main_r5fss1_core0_memory_region>; 1417}; 1418 1419&main_r5fss1_core1 { 1420 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1421 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1422 <&main_r5fss1_core1_memory_region>; 1423}; 1424 1425&c66_0 { 1426 status = "okay"; 1427 mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 1428 memory-region = <&c66_0_dma_memory_region>, 1429 <&c66_0_memory_region>; 1430}; 1431 1432&c66_1 { 1433 status = "okay"; 1434 mboxes = <&mailbox0_cluster3 &mbox_c66_1>; 1435 memory-region = <&c66_1_dma_memory_region>, 1436 <&c66_1_memory_region>; 1437}; 1438 1439&c71_0 { 1440 status = "okay"; 1441 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1442 memory-region = <&c71_0_dma_memory_region>, 1443 <&c71_0_memory_region>; 1444}; 1445